diff --git a/Readme.md b/Readme.md index b669db8..7253dab 100644 --- a/Readme.md +++ b/Readme.md @@ -1,91 +1,43 @@ -# 🧪 Fault -![Swift 5.8+](https://img.shields.io/badge/Swift-5.8-orange?logo=swift) [![ReadTheDocs](https://readthedocs.org/projects/Fault/badge)](https://fault.readthedocs.io) [![Built with Nix](https://img.shields.io/static/v1?logo=nixos&logoColor=white&label=&message=Built%20with%20Nix&color=41439a)](https://nixos.org) +

🧪 Fault

-Fault is a complete open source design for testing (DFT) Solution that includes automatic test pattern generation for netlists, scan chain stitching, synthesis scripts and a number of other convenience features. - -# Installation and Usage - -See the documentation at https://fault.readthedocs.io. - -# Running -## Subcommands -### synth -Synth is a synthesis script included with Fault that generates a netlist. You may elect to use your own synthesis script, but this is provided for your convenience. - -To run it, `fault synth --top --liberty `. - -For more options, you can invoke `fault synth --help`. - -### cut -`fault cut ` - -This exposes the D-flipflops as ports for use with the main script. - -For more options, you can invoke `fault cut --help`. - -### main -`fault --clock --cellModel `. - -A set of assumptions are made about the input file: -* It is a netlist -* It is flattened (there is only one module with no submodules) -* The flipflops have been cut away and replaced with outputs and inputs. - -Generated test vectors are printed to stdout by default, but you can use `-o ` (or simply redirect the output). - -For more options, you can invoke `fault --help`. +

+ Swift 5.8 or higher + Read the Docs + Built with Nix +

  -### chain -`fault chain --liberty --clock --reset <--activeLow> `. -Chain is another synthesis script that links registers together for scan insertion. It takes all the assumptions made in the main program but the last, and one more: -* All instantiated D flipflops start with "DFF". - -A note about the liberty file in use in this step is that we recommend a modified liberty file that keeps only a buffer, an and gate, and a multiplexer (and an inverter if necessary), as abc tends to overthink multiplexers. - -Chain will output information about the scan chain embedded in the output netlist as `/* FAULT METADATA: '' */` after the boilerplate. This metadata includes things like port names, the DFF count and the order of the registers in the scan chain. - -You can have Chain automagically verify its generated scanchain-- see the help for more options, but the gist of it is `-v `. - -For more options, you can invoke `fault chain --help`. - -### asm -`fault asm `, in any order, will assemble a .bin file for use with `$readmemb`. - -For more options, you can invoke `fault asm --help`. - -### compact -`fault compact ` - -This performs static compaction on the generated test vectors by reducing the test vectors count while keeping the same coverage. - -For more options, you can invoke `fault compact --help`. - -### tap -`fault tap --liberty [--cellModel ] --clock --reset ` - -Tap adds JTAG interface to a chained netlist. Currently, two scan chains are supported: the boundary cell scan chain and the internal registers chain. Tap supports the IEEE 1149.1 four mandatory: Extest, Bypass, Sample, and Preload. Also, it has been extended to support ScanIn (4'b 0100) instruction to select the internal register chain. - -A cell model can optionally be passed to verify the tap. +Fault is a complete open source design for testing (DFT) Solution that includes automatic test pattern generation for netlists, scan chain stitching, synthesis scripts and a number of other convenience features. -For more information on the supported instructions, check the example [testbench](Tests/Testbenches/TestTap.sv). +![A flowchart demonstrating the Fault flow](./docs/flow.png) -For more options, you can invoke `fault tap --help`. +# Installation and Usage +See the documentation at https://fault.readthedocs.io. # Copyright & Licensing All rights reserved ©2018-2024 The American University in Cairo and other contributors. Fault is available under the Apache 2.0 License: See `License`. -SOFTWARE INCLUDED WITH FAULT DISTRIBUTIONS, I.E. ATALANTA AND PODEM, WHILE FREE TO DISTRIBUTE, ARE PROPRIETARY, AND MAY NOT BE USED FOR COMMERCIAL PURPOSES. +SOFTWARE INCLUDED WITH SOME FAULT DISTRIBUTIONS, I.E. ATALANTA AND PODEM, WHILE +FREE TO DISTRIBUTE, ARE PROPRIETARY, AND MAY NOT BE USED FOR COMMERCIAL +PURPOSES. # References -- Z. Navabi, Digital System Test and Testable Design : Using Hdl Models and Architectures. 2010;2011;. DOI: 10.1007/978-1-4419-7548-5. -[Book](https://ieeexplore.ieee.org/book/5266057) -- Shinya Takamaeda-Yamazaki: Pyverilog: A Python-based Hardware Design Processing Toolkit for Verilog HDL, 11th International Symposium on Applied Reconfigurable Computing (ARC 2015) (Poster), Lecture Notes in Computer Science, Vol.9040/2015, pp.451-460, April 2015. -[Paper](http://link.springer.com/chapter/10.1007/978-3-319-16214-0_42) +- Z. Navabi, Digital System Test and Testable Design : Using Hdl Models and + Architectures. 2010;2011;. DOI: 10.1007/978-1-4419-7548-5. + [Book](https://ieeexplore.ieee.org/book/5266057) +- Shinya Takamaeda-Yamazaki: Pyverilog: A Python-based Hardware Design + Processing Toolkit for Verilog HDL, 11th International Symposium on Applied + Reconfigurable Computing (ARC 2015) (Poster), Lecture Notes in Computer + Science, Vol.9040/2015, pp.451-460, April 2015. + [Paper](http://link.springer.com/chapter/10.1007/978-3-319-16214-0_42) # Publication(s) -- M. Abdelatty, M. Gaber, M. Shalan, "Fault: Open Source EDA’s Missing DFT Toolchain," IEEE Design & Test Magazine. April 2021. [Paper](https://ieeexplore.ieee.org/document/9324799) -- Mohamed Gaber, Manar Abdelatty, and Mohamed Shalan, "Fault, an Open Source DFT Toolchain," Article No.13, Workshop on Open-Source EDA Technology (WOSET), 2019. -[Paper](https://woset-workshop.github.io/PDFs/2019/a13.pdf) +- M. Abdelatty, M. Gaber, M. Shalan, "Fault: Open Source EDA’s Missing DFT + Toolchain," IEEE Design & Test Magazine. April 2021. + [Paper](https://ieeexplore.ieee.org/document/9324799) +- Mohamed Gaber, Manar Abdelatty, and Mohamed Shalan, "Fault, an Open Source DFT + Toolchain," Article No.13, Workshop on Open-Source EDA Technology (WOSET), + 2019. [Paper](https://woset-workshop.github.io/PDFs/2019/a13.pdf) diff --git a/docs/Source/index.md b/docs/Source/index.md index cd64154..05f622e 100644 --- a/docs/Source/index.md +++ b/docs/Source/index.md @@ -5,12 +5,7 @@ automatic test pattern generation (ATPG), scan stitching, static test vector compaction, and JTAG insertion. Fault generates test vectors pseudo-randomly and performs fault simulations using the stuck-at-fault model. -
- -

Fault Design Flow.

-
- -Fault is composed of seven main options: +Fault is composed of five main options: ## 1. Synth @@ -36,14 +31,14 @@ linear feedback shift register (LFSR). ATPG also optimizes the test vector set by eliminating redundant vectors. -### 4. Chain +## 4. Chain Chain performs scan-chain stitching. Using [Pyverilog](https://github.com/PyHDI/Pyverilog), a boundary scan chain is constructed through a netlist's input and output ports. An internal register chain is also constructed through the netlist's D-flip-flops. -### 5. Tap +## 5. Tap Tap adds the [JTAG interface](https://opencores.org/websvn/listing?repname=adv_debug_sys&path=%2Fadv_debug_sys%2Ftrunk%2FHardware%2Fjtag%2Ftap%2Fdoc%2F#path_adv_debug_sys_trunk_Hardware_jtag_tap_doc_) diff --git a/docs/flow.png b/docs/flow.png new file mode 100644 index 0000000..ca0345a Binary files /dev/null and b/docs/flow.png differ