fpga directory

Author: DLX4

fpga/vivado2014.4_diagram/sobel_hls_zed_vivado2014.4.pdf

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+#include "top.h"
+void hls_sobel(AXI_STREAM_IN& input, AXI_STREAM_OUT& output, int rows, int cols) {
+#pragma HLS RESOURCE variable=input core=AXI4Stream metadata="-bus_bundle INPUT_STREAM"
+#pragma HLS RESOURCE variable=output core=AXI4Stream metadata="-bus_bundle OUTPUT_STREAM"
+#pragma HLS INTERFACE ap_none port=cols
+#pragma HLS INTERFACE ap_none port=rows
+//AP_CONTROL_BUS_AXI(CONTROL_BUS);
+//set_directive_interface -mode ap_ctrl_none hls_sobel
+#pragma HLS interface ap_ctrl_none port=return
+
+RGB_IMAGE img_0(rows, cols);
+RGB_IMAGE img_1(rows, cols);
+#pragma HLS DATAFLOW // must use data flow to stream the data
+hls::AXIvideo2Mat(input, img_0); //read video stream by frames
+hls::Sobel<1,0,1>(img_0, img_1);//use Hls Sobel
+hls::Mat2AXIvideo(img_1, output); //write the frames to video stream
+
+}

fpga/vivado2014.4_hls_src/hls_sobel.cpp

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+#ifndef _TOP_H_
+#define _TOP_H_
+#include "hls_video.h" //这里调用可以综合的视频库
+
+// maximum image size
+#define MAX_WIDTH 1920
+#define MAX_HEIGHT 1080
+// I/O Image Settings
+#define INPUT_IMAGE "test_1080p.jpg"
+#define OUTPUT_IMAGE "result_1080p.jpg"
+#define OUTPUT_IMAGE_GOLDEN "result_1080p_golden.jpg"
+// typedef video library core structures
+typedef hls::stream<ap_axiu<24,1,1,1> > AXI_STREAM_IN;
+typedef hls::stream<ap_axiu<24,1,1,1> > AXI_STREAM_OUT;
+typedef hls::Mat<MAX_HEIGHT, MAX_WIDTH, HLS_8UC3> RGB_IMAGE;
+typedef hls::Mat<MAX_HEIGHT, MAX_WIDTH, HLS_8UC1> GRAY_IMAGE;
+// top level function for HW synthesis
+void hls_sobel(AXI_STREAM_IN& src_axi, AXI_STREAM_OUT& dst_axi, int rows, int cols);
+
+#endif

fpga/vivado2014.4_hls_src/top.h

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+#include "top.h"
+#include "opencv/cv.h"
+#include "opencv/cxcore.h"
+#include "opencv/highgui.h"
+#include "hls_opencv.h"
+int main (int argc, char** argv) {
+    IplImage* src = cvLoadImage(INPUT_IMAGE);
+    IplImage* dst = cvCreateImage(cvGetSize(src), src->depth, src->nChannels);
+    AXI_STREAM_IN src_axi;
+    AXI_STREAM_OUT dst_axi;
+    IplImage2AXIvideo(src, src_axi); //½«Í¼ÏñתΪÊÓƵÁ÷½á¹¹
+    hls_sobel(src_axi, dst_axi, src->height, src->width);
+    AXIvideo2IplImage(dst_axi, dst);
+    cvSaveImage(OUTPUT_IMAGE, dst);
+    cvReleaseImage(&src);
+    cvReleaseImage(&dst);
+}

fpga/vivado2014.4_hls_testbench/test.cpp

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+/******************************************************************************
+*
+* Copyright (C) 2009 - 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+/*
+ * helloworld.c: simple test application
+ *
+ * This application configures UART 16550 to baud rate 9600.
+ * PS7 UART (Zynq) is not initialized by this application, since
+ * bootrom/bsp configures it to baud rate 115200
+ *
+ * ------------------------------------------------
+ * | UART TYPE   BAUD RATE                        |
+ * ------------------------------------------------
+ *   uartns550   9600
+ *   uartlite    Configurable only in HW design
+ *   ps7_uart    115200 (configured by bootrom/bsp)
+ */
+
+#include <stdio.h>
+#include "platform.h"
+#include "xparameters.h"
+void print(char *str);
+
+int main()
+{
+    init_platform();
+
+    print("Hello World\n\r");
+
+    Xil_Out32(XPAR_AXI_VDMA_0_BASEADDR + 0x0, 0x4); //reset   MM2S VDMA Control Register
+    Xil_Out32(XPAR_AXI_VDMA_0_BASEADDR + 0x0, 0x8); //gen-lock
+    Xil_Out32(XPAR_AXI_VDMA_0_BASEADDR + 0x5C,   0x04000000);   //MM2S Start Addresses
+
+    Xil_Out32(XPAR_AXI_VDMA_0_BASEADDR + 0x54, 640*3);//MM2S HSIZE Register---buffer length
+    Xil_Out32(XPAR_AXI_VDMA_0_BASEADDR + 0x58, 0x01000780);//S2MM FRMDELAY_STRIDE Register 1920*3=5760 对齐之后为8192=0x2000
+
+    Xil_Out32(XPAR_AXI_VDMA_0_BASEADDR + 0x0, 0x03);//MM2S VDMA Control Register
+
+    //Xil_Out32(XPAR_AXI_VDMA_0_BASEADDR + 0x50, 480);//MM2S_VSIZE    启动传输
+
+
+
+
+
+    Xil_Out32(XPAR_AXI_VDMA_0_BASEADDR + 0xAC, 0x08000000);//S2MM Start Addresses
+    Xil_Out32(XPAR_AXI_VDMA_0_BASEADDR + 0xA4, 640*3);
+    Xil_Out32(XPAR_AXI_VDMA_0_BASEADDR + 0xA8, 0x01000780);//S2MM Frame Delay and Stride
+    Xil_Out32(XPAR_AXI_VDMA_0_BASEADDR + 0x30, 0x3);//S2MM VDMA Control Register
+
+
+
+    Xil_Out32(XPAR_AXI_VDMA_0_BASEADDR + 0x50, 480);//MM2S_VSIZE    启动传输
+    Xil_Out32(XPAR_AXI_VDMA_0_BASEADDR + 0xA0, 480);//S2MM Vertical Size  start an S2MM transfer
+
+    cleanup_platform();
+    return 0;
+}
+
+