UART_FPGA_map.map

Release 14.7 Map P.20131013 (nt64)
Xilinx Map Application Log File for Design 'UART_FPGA'

Design Information
------------------
Command Line   : map -intstyle ise -p xc3s100e-cp132-5 -cm area -ir off -pr off
-c 100 -o UART_FPGA_map.ncd UART_FPGA.ngd UART_FPGA.pcf 
Target Device  : xc3s100e
Target Package : cp132
Target Speed   : -5
Mapper Version : spartan3e -- $Revision: 1.55 $
Mapped Date    : Wed Mar 21 15:17:38 2018

Mapping design into LUTs...
Running directed packing...
Running delay-based LUT packing...
Running related packing...
Updating timing models...
WARNING:PhysDesignRules:372 - Gated clock. Clock net m1/baud_sel_debounce is
   sourced by a combinatorial pin. This is not good design practice. Use the CE
   pin to control the loading of data into the flip-flop.

Design Summary
--------------

Design Summary:
Number of errors:      0
Number of warnings:    1
Logic Utilization:
  Number of Slice Flip Flops:           110 out of   1,920    5%
  Number of 4 input LUTs:               149 out of   1,920    7%
Logic Distribution:
  Number of occupied Slices:             99 out of     960   10%
    Number of Slices containing only related logic:      99 out of      99 100%
    Number of Slices containing unrelated logic:          0 out of      99   0%
      *See NOTES below for an explanation of the effects of unrelated logic.
  Total Number of 4 input LUTs:         182 out of   1,920    9%
    Number used as logic:               149
    Number used as a route-thru:         33

  The Slice Logic Distribution report is not meaningful if the design is
  over-mapped for a non-slice resource or if Placement fails.

  Number of bonded IOBs:                 28 out of      83   33%
  Number of BUFGMUXs:                     2 out of      24    8%

Average Fanout of Non-Clock Nets:                3.35

Peak Memory Usage:  334 MB
Total REAL time to MAP completion:  14 secs 
Total CPU time to MAP completion:   2 secs 

NOTES:

   Related logic is defined as being logic that shares connectivity - e.g. two
   LUTs are "related" if they share common inputs.  When assembling slices,
   Map gives priority to combine logic that is related.  Doing so results in
   the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin packing
   unrelated logic into a slice once 99% of the slices are occupied through
   related logic packing.

   Note that once logic distribution reaches the 99% level through related
   logic packing, this does not mean the device is completely utilized.
   Unrelated logic packing will then begin, continuing until all usable LUTs
   and FFs are occupied.  Depending on your timing budget, increased levels of
   unrelated logic packing may adversely affect the overall timing performance
   of your design.

Mapping completed.
See MAP report file "UART_FPGA_map.mrp" for details.