From 4a9e9434b714984f89930c4353c6bd36c9563ccf Mon Sep 17 00:00:00 2001 From: zyren <585668@qq.com> Date: Sat, 3 Jun 2023 12:52:05 +0800 Subject: [PATCH 1/2] Reduce ADC noise --- radio/src/targets/horus/board.cpp | 4 ++++ radio/src/targets/taranis/board.cpp | 1 + 2 files changed, 5 insertions(+) diff --git a/radio/src/targets/horus/board.cpp b/radio/src/targets/horus/board.cpp index 18927589db1..2c30cd69f9b 100644 --- a/radio/src/targets/horus/board.cpp +++ b/radio/src/targets/horus/board.cpp @@ -70,6 +70,10 @@ void boardInit() board_set_bor_level(); #endif +#if defined(RADIO_TX16S) + FLASH_PrefetchBufferCmd(DISABLE); +#endif + pwrInit(); #if defined(FUNCTION_SWITCHES) && !defined(DEBUG_SEGGER_RTT) diff --git a/radio/src/targets/taranis/board.cpp b/radio/src/targets/taranis/board.cpp index d264e8dbdcf..6f9133aa037 100644 --- a/radio/src/targets/taranis/board.cpp +++ b/radio/src/targets/taranis/board.cpp @@ -79,6 +79,7 @@ void boardInit() #if defined(MANUFACTURER_RADIOMASTER) && defined(STM32F407xx) void board_set_bor_level(); board_set_bor_level(); + FLASH_PrefetchBufferCmd(DISABLE); #endif board_trainer_init(); From 2b9d0be22a0734b88ed824c155abd37aa44dca60 Mon Sep 17 00:00:00 2001 From: Peter Feerick Date: Mon, 8 Jul 2024 08:58:15 +0000 Subject: [PATCH 2/2] chore: disable prefetch, for testing purposes only --- radio/src/targets/common/arm/stm32/f2/system_stm32f2xx.c | 2 +- radio/src/targets/common/arm/stm32/f4/system_stm32f4xx.c | 2 +- radio/src/targets/horus/board.cpp | 4 ---- radio/src/targets/taranis/board.cpp | 1 - 4 files changed, 2 insertions(+), 7 deletions(-) diff --git a/radio/src/targets/common/arm/stm32/f2/system_stm32f2xx.c b/radio/src/targets/common/arm/stm32/f2/system_stm32f2xx.c index a6a7e4e4236..3d47d843aa1 100644 --- a/radio/src/targets/common/arm/stm32/f2/system_stm32f2xx.c +++ b/radio/src/targets/common/arm/stm32/f2/system_stm32f2xx.c @@ -299,7 +299,7 @@ static void SetSysClock(void) } /* Configure Flash prefetch, Instruction cache, Data cache and wait state */ - FLASH->ACR = FLASH_ACR_PRFTEN |FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_3WS; + FLASH->ACR = FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_3WS; /* Select the main PLL as system clock source */ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); diff --git a/radio/src/targets/common/arm/stm32/f4/system_stm32f4xx.c b/radio/src/targets/common/arm/stm32/f4/system_stm32f4xx.c index b8d67febee0..198b7b82c72 100644 --- a/radio/src/targets/common/arm/stm32/f4/system_stm32f4xx.c +++ b/radio/src/targets/common/arm/stm32/f4/system_stm32f4xx.c @@ -427,7 +427,7 @@ static void SetSysClock(void) } /* Configure Flash prefetch, Instruction cache, Data cache and wait state */ - FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_LATENCY_5WS; + FLASH->ACR = FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_LATENCY_5WS; /* Select the main PLL as system clock source */ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); diff --git a/radio/src/targets/horus/board.cpp b/radio/src/targets/horus/board.cpp index 2c30cd69f9b..18927589db1 100644 --- a/radio/src/targets/horus/board.cpp +++ b/radio/src/targets/horus/board.cpp @@ -70,10 +70,6 @@ void boardInit() board_set_bor_level(); #endif -#if defined(RADIO_TX16S) - FLASH_PrefetchBufferCmd(DISABLE); -#endif - pwrInit(); #if defined(FUNCTION_SWITCHES) && !defined(DEBUG_SEGGER_RTT) diff --git a/radio/src/targets/taranis/board.cpp b/radio/src/targets/taranis/board.cpp index 6f9133aa037..d264e8dbdcf 100644 --- a/radio/src/targets/taranis/board.cpp +++ b/radio/src/targets/taranis/board.cpp @@ -79,7 +79,6 @@ void boardInit() #if defined(MANUFACTURER_RADIOMASTER) && defined(STM32F407xx) void board_set_bor_level(); board_set_bor_level(); - FLASH_PrefetchBufferCmd(DISABLE); #endif board_trainer_init();