Handle non-aligned memory accesses

[lupino3]

See discussion below. The user asked if it's possible to handle non-aligned memory accesses.

This would require understanding the expectations of traditional load/store instructions in presence of unaligned addresses, implementing the behavior and adding an option to toggle it.

The misaligned semantics are described in appendix B of the most recent MIPS64 ISA spec: https://s3-eu-west-1.amazonaws.com/downloads-mips/documents/MD00083-2B-MIPS64INT-AFP-06.01.pdf

Discussed in #701

^{Originally posted by euro-phd August 28, 2022}
Hi, I'm studying MIPS64 at uni as part of the Computer Architecture course. One of the labs requires us to execute the following code:

.text
div.d f7,f9,f10
mul.d f2,f4,f3
sub.d f7,f7,f4
ld r1,78(r0)
add.d f4,f5,f6
halt

During the execution, using EduMIPS64, the error occurs.

However, on WinMIPS64, used by a lecturer, everything runs smoothly.

Is there a way to patch/reconfigure EduMIPS64 to receive the same results as WinMIPS64? It seems like WinMIPS64 fixed alignment on its own. However, I'm unsure how to code the same behavior in EduMIPS64.

Thanks