RFNoC "addsub" Block YAML Parameter #809
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Thanks for reporting. Can confirm. |
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We fixed the issue and will update |
marino-gnss
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Feb 17, 2025
When instantiating an addsub block, the quotes would get munged,
rendering the parameter as such:
.USE_IMPL(Verilog)
The correct rendering should be:
.USE_IMPL("Verilog")
This leads to Vivado complaining about how the expression `Verilog` is
not known (it should be a string constant).
We fix this by using the recently introduced 'q' filter.
Discussed in EttusResearch#809.
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Issue Description
The included "addsub" block's YAML definition contains a string parameter. The quotation marks do not carry forward to the generated
rfnoc_image_core.sv. Building FPGA image will fail.Setup Details
Expected Behavior
FPGA image builds successfully
Actual Behaviour
Synthesis fails with:
Steps to reproduce the problem
Just add an "addsub" block to your RFNoC image.
Additional Information
Can be fixed by adding a few lines to
addsub.ymlto usehdl_parametersas is done in OOT examplegain.yml.The text was updated successfully, but these errors were encountered: