From 4bdfa69d2019cd46d7ef2911fe692bbb9739b751 Mon Sep 17 00:00:00 2001 From: Michael Rogenmoser Date: Sat, 15 Jan 2022 11:08:14 +0100 Subject: [PATCH] `axi` and `common_cells` upgrade (#791) * Change questa version reference format * bump common_cells to v1.23 * Bump axi to v0.31.0, replace axi_node with axi_xbar * Bump register_interface for axi compatibility * add prot signals to axi_lite for compatibility --- .gitmodules | 3 - Bender.yml | 30 ++-- CHANGELOG.md | 3 + Makefile | 53 +++--- common/submodules/common_cells | 2 +- core/include/axi_intf.sv | 10 +- corev_apu/axi | 2 +- corev_apu/axi_node | 1 - corev_apu/fpga/scripts/run.tcl | 2 +- corev_apu/fpga/src/ariane_xilinx.sv | 84 ++++----- corev_apu/register_interface | 2 +- corev_apu/tb/ariane_testharness.sv | 255 +++++++++------------------- 12 files changed, 185 insertions(+), 262 deletions(-) delete mode 160000 corev_apu/axi_node diff --git a/.gitmodules b/.gitmodules index 44debea7f9..1c4aa614fc 100644 --- a/.gitmodules +++ b/.gitmodules @@ -1,9 +1,6 @@ [submodule "corev_apu/axi_mem_if"] path = corev_apu/axi_mem_if url = https://github.com/pulp-platform/axi_mem_if.git -[submodule "corev_apu/axi_node"] - path = corev_apu/axi_node - url = https://github.com/pulp-platform/axi_node.git [submodule "corev_apu/fpga-support"] path = corev_apu/fpga-support url = https://github.com/pulp-platform/fpga-support.git diff --git a/Bender.yml b/Bender.yml index e815c73b84..461b141943 100644 --- a/Bender.yml +++ b/Bender.yml @@ -9,6 +9,7 @@ package: export_include_dirs: - common/submodules/common_cells/include/ + - corev_apu/axi/include/ sources: - defines: @@ -120,25 +121,6 @@ sources: - corev_apu/fpga/src/axi_slice/src/axi_aw_buffer.sv - corev_apu/fpga/src/apb_timer/apb_timer.sv - corev_apu/fpga/src/apb_timer/timer.sv - - corev_apu/axi_node/src/axi_regs_top.sv - - corev_apu/axi_node/src/axi_BR_allocator.sv - - corev_apu/axi_node/src/axi_BW_allocator.sv - - corev_apu/axi_node/src/axi_address_decoder_BR.sv - - corev_apu/axi_node/src/axi_DW_allocator.sv - - corev_apu/axi_node/src/axi_address_decoder_BW.sv - - corev_apu/axi_node/src/axi_address_decoder_DW.sv - - corev_apu/axi_node/src/axi_node_arbiter.sv - - corev_apu/axi_node/src/axi_response_block.sv - - corev_apu/axi_node/src/axi_request_block.sv - - corev_apu/axi_node/src/axi_AR_allocator.sv - - corev_apu/axi_node/src/axi_AW_allocator.sv - - corev_apu/axi_node/src/axi_address_decoder_AR.sv - - corev_apu/axi_node/src/axi_address_decoder_AW.sv - - corev_apu/axi_node/src/apb_regs_top.sv - - corev_apu/axi_node/src/axi_node_intf_wrap.sv - - corev_apu/axi_node/src/axi_node.sv - - corev_apu/axi_node/src/axi_node_wrap_with_slices.sv - - corev_apu/axi_node/src/axi_multiplexer.sv - corev_apu/src/axi_riscv_atomics/src/axi_riscv_amos.sv - corev_apu/src/axi_riscv_atomics/src/axi_riscv_atomics.sv - corev_apu/src/axi_riscv_atomics/src/axi_res_tbl.sv @@ -161,6 +143,7 @@ sources: - corev_apu/riscv-dbg/debug_rom/debug_rom.sv - corev_apu/register_interface/src/apb_to_reg.sv - corev_apu/axi/src/axi_multicut.sv + - common/submodules/common_cells/src/cf_math_pkg.sv - common/submodules/common_cells/src/deprecated/generic_fifo.sv - common/submodules/common_cells/src/deprecated/pulp_sync.sv - common/submodules/common_cells/src/deprecated/find_first_one.sv @@ -178,11 +161,18 @@ sources: - corev_apu/axi/src/axi_join.sv - corev_apu/axi/src/axi_delayer.sv - corev_apu/axi/src/axi_to_axi_lite.sv + - corev_apu/axi/src/axi_id_prepend.sv + - corev_apu/axi/src/axi_atop_filter.sv + - corev_apu/axi/src/axi_err_slv.sv + - corev_apu/axi/src/axi_mux.sv + - corev_apu/axi/src/axi_demux.sv + - corev_apu/axi/src/axi_xbar.sv - corev_apu/fpga-support/rtl/SyncSpRamBeNx64.sv - common/submodules/common_cells/src/sync.sv - common/submodules/common_cells/src/popcount.sv - common/submodules/common_cells/src/unread.sv - common/submodules/common_cells/src/cdc_2phase.sv + - common/submodules/common_cells/src/spill_register_flushable.sv - common/submodules/common_cells/src/spill_register.sv - common/submodules/common_cells/src/edge_detect.sv - common/submodules/common_cells/src/fifo_v3.sv @@ -198,6 +188,8 @@ sources: - common/submodules/common_cells/src/counter.sv - common/submodules/common_cells/src/shift_reg.sv - common/submodules/common_cells/src/exp_backoff.sv + - common/submodules/common_cells/src/addr_decode.sv + - common/submodules/common_cells/src/stream_register.sv - corev_apu/src/tech_cells_generic/src/cluster_clock_inverter.sv - corev_apu/src/tech_cells_generic/src/pulp_clock_mux2.sv - target: not(cv32a6) diff --git a/CHANGELOG.md b/CHANGELOG.md index 215fa4056e..41711b5c54 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -13,6 +13,9 @@ and this project adheres to [Semantic Versioning](http://semver.org/spec/v2.0.0. - Fix non-setable MEIE bit in MIE CSR - Bump `fpnew` to `v0.6.2` - Restructured directories to separate CVA6 core from CVA6-APU (FPGA emulation platform for the core). See the [README](README.md#new-directory-structure) for details. +- Bump `common_cells` to `v1.23.0` +- Bump `axi` to `v0.31.0` +- Remove `axi_node` dependency, replace with `axi_xbar` from `axi` repository #### Moved Package files ``` diff --git a/Makefile b/Makefile index c2b402c6b9..6a9181a705 100644 --- a/Makefile +++ b/Makefile @@ -18,6 +18,12 @@ max_cycles ?= 10000000 test_case ?= core_test # QuestaSim Version questa_version ?= ${QUESTASIM_VERSION} +VLOG ?= vlog$(questa_version) +VSIM ?= vsim$(questa_version) +VOPT ?= vopt$(questa_version) +VCOM ?= vcom$(questa_version) +VLIB ?= vlib$(questa_version) +VMAP ?= vmap$(questa_version) # verilator version verilator ?= verilator # traget option @@ -162,7 +168,6 @@ src := $(filter-out core/ariane_regfile.sv, $(wildcard core/*.sv)) $(wildcard corev_apu/fpga/src/axi2apb/src/*.sv) \ $(wildcard corev_apu/fpga/src/apb_timer/*.sv) \ $(wildcard corev_apu/fpga/src/axi_slice/src/*.sv) \ - $(wildcard corev_apu/axi_node/src/*.sv) \ $(wildcard corev_apu/src/axi_riscv_atomics/src/*.sv) \ $(wildcard corev_apu/axi_mem_if/src/*.sv) \ $(wildcard core/pmp/src/*.sv) \ @@ -180,6 +185,7 @@ src := $(filter-out core/ariane_regfile.sv, $(wildcard core/*.sv)) corev_apu/riscv-dbg/debug_rom/debug_rom.sv \ corev_apu/register_interface/src/apb_to_reg.sv \ corev_apu/axi/src/axi_multicut.sv \ + common/submodules/common_cells/src/cf_math_pkg.sv \ common/submodules/common_cells/src/deprecated/generic_fifo.sv \ common/submodules/common_cells/src/deprecated/pulp_sync.sv \ common/submodules/common_cells/src/deprecated/find_first_one.sv \ @@ -188,6 +194,8 @@ src := $(filter-out core/ariane_regfile.sv, $(wildcard core/*.sv)) common/submodules/common_cells/src/stream_mux.sv \ common/submodules/common_cells/src/stream_demux.sv \ common/submodules/common_cells/src/exp_backoff.sv \ + common/submodules/common_cells/src/addr_decode.sv \ + common/submodules/common_cells/src/stream_register.sv \ common/local/util/axi_master_connect.sv \ common/local/util/axi_slave_connect.sv \ common/local/util/axi_master_connect_rev.sv \ @@ -196,10 +204,17 @@ src := $(filter-out core/ariane_regfile.sv, $(wildcard core/*.sv)) corev_apu/axi/src/axi_join.sv \ corev_apu/axi/src/axi_delayer.sv \ corev_apu/axi/src/axi_to_axi_lite.sv \ + corev_apu/axi/src/axi_id_prepend.sv \ + corev_apu/axi/src/axi_atop_filter.sv \ + corev_apu/axi/src/axi_err_slv.sv \ + corev_apu/axi/src/axi_mux.sv \ + corev_apu/axi/src/axi_demux.sv \ + corev_apu/axi/src/axi_xbar.sv \ corev_apu/fpga-support/rtl/SyncSpRamBeNx64.sv \ common/submodules/common_cells/src/unread.sv \ common/submodules/common_cells/src/sync.sv \ common/submodules/common_cells/src/cdc_2phase.sv \ + common/submodules/common_cells/src/spill_register_flushable.sv \ common/submodules/common_cells/src/spill_register.sv \ common/submodules/common_cells/src/sync_wedge.sv \ common/submodules/common_cells/src/edge_detect.sv \ @@ -268,7 +283,7 @@ riscv-fp-tests := $(shell xargs printf '\n%s' < $(riscv-fp-tests-list riscv-benchmarks := $(shell xargs printf '\n%s' < $(riscv-benchmarks-list) | cut -b 1-) # Search here for include files (e.g.: non-standalone components) -incdir := common/submodules/common_cells/include/ +incdir := common/submodules/common_cells/include/ corev_apu/axi/include/ # Compile and sim flags compile_flag += +cover=bcfst+/dut -incr -64 -nologo -quiet -suppress 13262 -permissive +define+$(defines) @@ -329,27 +344,27 @@ vcs: vcs_build # Build the TB and module using QuestaSim build: $(library) $(library)/.build-srcs $(library)/.build-tb $(dpi-library)/ariane_dpi.so # Optimize top level - vopt$(questa_version) $(compile_flag) -work $(library) $(top_level) -o $(top_level)_optimized +acc -check_synthesis + $(VOPT) $(compile_flag) -work $(library) $(top_level) -o $(top_level)_optimized +acc -check_synthesis # src files $(library)/.build-srcs: $(util) $(library) - vlog$(questa_version) $(compile_flag) -work $(library) $(filter %.sv,$(ariane_pkg)) $(list_incdir) -suppress 2583 - # vcom$(questa_version) $(compile_flag_vhd) -work $(library) -pedanticerrors $(filter %.vhd,$(ariane_pkg)) - vlog$(questa_version) $(compile_flag) -timescale "1ns / 1ns" -work $(library) $(filter %.sv,$(util)) $(list_incdir) -suppress 2583 + $(VLOG) $(compile_flag) -work $(library) $(filter %.sv,$(ariane_pkg)) $(list_incdir) -suppress 2583 + # $(VCOM) $(compile_flag_vhd) -work $(library) -pedanticerrors $(filter %.vhd,$(ariane_pkg)) + $(VLOG) $(compile_flag) -timescale "1ns / 1ns" -work $(library) $(filter %.sv,$(util)) $(list_incdir) -suppress 2583 # Suppress message that always_latch may not be checked thoroughly by QuestaSim. - vcom$(questa_version) $(compile_flag_vhd) -work $(library) -pedanticerrors $(filter %.vhd,$(uart_src)) - # vcom$(questa_version) $(compile_flag_vhd) -work $(library) -pedanticerrors $(filter %.vhd,$(src)) - vlog$(questa_version) $(compile_flag) -timescale "1ns / 1ns" -work $(library) -pedanticerrors $(filter %.sv,$(src)) $(list_incdir) -suppress 2583 + $(VCOM) $(compile_flag_vhd) -work $(library) -pedanticerrors $(filter %.vhd,$(uart_src)) + # $(VCOM) $(compile_flag_vhd) -work $(library) -pedanticerrors $(filter %.vhd,$(src)) + $(VLOG) $(compile_flag) -timescale "1ns / 1ns" -work $(library) -pedanticerrors $(filter %.sv,$(src)) $(list_incdir) -suppress 2583 touch $(library)/.build-srcs # build TBs $(library)/.build-tb: $(dpi) # Compile top level - vlog$(questa_version) $(compile_flag) -timescale "1ns / 1ns" -sv $(tbs) -work $(library) + $(VLOG) $(compile_flag) -timescale "1ns / 1ns" -sv $(tbs) -work $(library) $(list_incdir) touch $(library)/.build-tb $(library): - vlib${questa_version} $(library) + $(VLIB) $(library) # compile DPIs $(dpi-library)/%.o: corev_apu/tb/dpi/%.cc $(dpi_hdr) @@ -370,32 +385,32 @@ generate-trace-vsim: make generate-trace sim: build - vsim${questa_version} +permissive $(questa-flags) $(questa-cmd) -lib $(library) +MAX_CYCLES=$(max_cycles) +UVM_TESTNAME=$(test_case) \ + $(VSIM) +permissive $(questa-flags) $(questa-cmd) -lib $(library) +MAX_CYCLES=$(max_cycles) +UVM_TESTNAME=$(test_case) \ +BASEDIR=$(riscv-test-dir) $(uvm-flags) $(QUESTASIM_FLAGS) -gblso $(SPIKE_ROOT)/lib/libfesvr.so -sv_lib $(dpi-library)/ariane_dpi \ ${top_level}_optimized +permissive-off ++$(elf-bin) ++$(target-options) | tee sim.log $(riscv-asm-tests): build - vsim${questa_version} +permissive $(questa-flags) $(questa-cmd) -lib $(library) +max-cycles=$(max_cycles) +UVM_TESTNAME=$(test_case) \ + $(VSIM) +permissive $(questa-flags) $(questa-cmd) -lib $(library) +max-cycles=$(max_cycles) +UVM_TESTNAME=$(test_case) \ +BASEDIR=$(riscv-test-dir) $(uvm-flags) +jtag_rbb_enable=0 -gblso $(SPIKE_ROOT)/lib/libfesvr.so -sv_lib $(dpi-library)/ariane_dpi \ ${top_level}_optimized $(QUESTASIM_FLAGS) +permissive-off ++$(riscv-test-dir)/$@ ++$(target-options) | tee tmp/riscv-asm-tests-$@.log $(riscv-amo-tests): build - vsim${questa_version} +permissive $(questa-flags) $(questa-cmd) -lib $(library) +max-cycles=$(max_cycles) +UVM_TESTNAME=$(test_case) \ + $(VSIM) +permissive $(questa-flags) $(questa-cmd) -lib $(library) +max-cycles=$(max_cycles) +UVM_TESTNAME=$(test_case) \ +BASEDIR=$(riscv-test-dir) $(uvm-flags) +jtag_rbb_enable=0 -gblso $(SPIKE_ROOT)/lib/libfesvr.so -sv_lib $(dpi-library)/ariane_dpi \ ${top_level}_optimized $(QUESTASIM_FLAGS) +permissive-off ++$(riscv-test-dir)/$@ ++$(target-options) | tee tmp/riscv-amo-tests-$@.log $(riscv-mul-tests): build - vsim${questa_version} +permissive $(questa-flags) $(questa-cmd) -lib $(library) +max-cycles=$(max_cycles) +UVM_TESTNAME=$(test_case) \ + $(VSIM) +permissive $(questa-flags) $(questa-cmd) -lib $(library) +max-cycles=$(max_cycles) +UVM_TESTNAME=$(test_case) \ +BASEDIR=$(riscv-test-dir) $(uvm-flags) +jtag_rbb_enable=0 -gblso $(SPIKE_ROOT)/lib/libfesvr.so -sv_lib $(dpi-library)/ariane_dpi \ ${top_level}_optimized $(QUESTASIM_FLAGS) +permissive-off ++$(riscv-test-dir)/$@ ++$(target-options) | tee tmp/riscv-mul-tests-$@.log $(riscv-fp-tests): build - vsim${questa_version} +permissive $(questa-flags) $(questa-cmd) -lib $(library) +max-cycles=$(max_cycles) +UVM_TESTNAME=$(test_case) \ + $(VSIM) +permissive $(questa-flags) $(questa-cmd) -lib $(library) +max-cycles=$(max_cycles) +UVM_TESTNAME=$(test_case) \ +BASEDIR=$(riscv-test-dir) $(uvm-flags) +jtag_rbb_enable=0 -gblso $(SPIKE_ROOT)/lib/libfesvr.so -sv_lib $(dpi-library)/ariane_dpi \ ${top_level}_optimized $(QUESTASIM_FLAGS) +permissive-off ++$(riscv-test-dir)/$@ ++$(target-options) | tee tmp/riscv-fp-tests-$@.log $(riscv-benchmarks): build - vsim${questa_version} +permissive $(questa-flags) $(questa-cmd) -lib $(library) +max-cycles=$(max_cycles) +UVM_TESTNAME=$(test_case) \ + $(VSIM) +permissive $(questa-flags) $(questa-cmd) -lib $(library) +max-cycles=$(max_cycles) +UVM_TESTNAME=$(test_case) \ +BASEDIR=$(riscv-benchmarks-dir) $(uvm-flags) +jtag_rbb_enable=0 -gblso $(SPIKE_ROOT)/lib/libfesvr.so -sv_lib $(dpi-library)/ariane_dpi \ ${top_level}_optimized $(QUESTASIM_FLAGS) +permissive-off ++$(riscv-benchmarks-dir)/$@ ++$(target-options) | tee tmp/riscv-benchmarks-$@.log @@ -732,12 +747,12 @@ torture-rtest-verilator: verilate $(MAKE) check-torture run-torture: build - vsim${questa_version} +permissive $(questa-flags) $(questa-cmd) -lib $(library) +max-cycles=$(max_cycles)+UVM_TESTNAME=$(test_case) \ + $(VSIM) +permissive $(questa-flags) $(questa-cmd) -lib $(library) +max-cycles=$(max_cycles)+UVM_TESTNAME=$(test_case) \ +BASEDIR=$(riscv-torture-dir) $(uvm-flags) +jtag_rbb_enable=0 -gblso $(SPIKE_ROOT)/lib/libfesvr.so -sv_lib $(dpi-library)/ariane_dpi \ ${top_level}_optimized +permissive-off +signature=$(riscv-torture-dir)/$(test-location).rtlsim.sig ++$(riscv-torture-dir)/$(test-location) ++$(target-options) run-torture-log: build - vsim${questa_version} +permissive $(questa-flags) $(questa-cmd) -lib $(library) +max-cycles=$(max_cycles)+UVM_TESTNAME=$(test_case) \ + $(VSIM) +permissive $(questa-flags) $(questa-cmd) -lib $(library) +max-cycles=$(max_cycles)+UVM_TESTNAME=$(test_case) \ +BASEDIR=$(riscv-torture-dir) $(uvm-flags) +jtag_rbb_enable=0 -gblso $(SPIKE_ROOT)/lib/libfesvr.so -sv_lib $(dpi-library)/ariane_dpi \ ${top_level}_optimized +permissive-off +signature=$(riscv-torture-dir)/$(test-location).rtlsim.sig ++$(riscv-torture-dir)/$(test-location) ++$(target-options) cp vsim.wlf $(riscv-torture-dir)/$(test-location).wlf diff --git a/common/submodules/common_cells b/common/submodules/common_cells index b2a4b2d3de..dc55564322 160000 --- a/common/submodules/common_cells +++ b/common/submodules/common_cells @@ -1 +1 @@ -Subproject commit b2a4b2d3decdfc152ad9b4564a48ed3b2649fd6c +Subproject commit dc555643226419b7a602f0aa39d449545ea4c1f2 diff --git a/core/include/axi_intf.sv b/core/include/axi_intf.sv index 6c2a05e076..41d4b16ae0 100644 --- a/core/include/axi_intf.sv +++ b/core/include/axi_intf.sv @@ -201,6 +201,7 @@ interface AXI_LITE #( // AW channel addr_t aw_addr; + prot_t aw_prot; logic aw_valid; logic aw_ready; @@ -214,6 +215,7 @@ interface AXI_LITE #( logic b_ready; addr_t ar_addr; + prot_t ar_prot; logic ar_valid; logic ar_ready; @@ -223,18 +225,18 @@ interface AXI_LITE #( logic r_ready; modport Master ( - output aw_addr, aw_valid, input aw_ready, + output aw_addr, aw_prot, aw_valid, input aw_ready, output w_data, w_strb, w_valid, input w_ready, input b_resp, b_valid, output b_ready, - output ar_addr, ar_valid, input ar_ready, + output ar_addr, ar_prot, ar_valid, input ar_ready, input r_data, r_resp, r_valid, output r_ready ); modport Slave ( - input aw_addr, aw_valid, output aw_ready, + input aw_addr, aw_prot, aw_valid, output aw_ready, input w_data, w_strb, w_valid, output w_ready, output b_resp, b_valid, input b_ready, - input ar_addr, ar_valid, output ar_ready, + input ar_addr, ar_prot, ar_valid, output ar_ready, output r_data, r_resp, r_valid, input r_ready ); diff --git a/corev_apu/axi b/corev_apu/axi index 3f5d5b540a..697f13ff67 160000 --- a/corev_apu/axi +++ b/corev_apu/axi @@ -1 +1 @@ -Subproject commit 3f5d5b540a6403c5c611e507a14e99d9e7f22edf +Subproject commit 697f13ff67153a5243e347f2d1992a125018b6c2 diff --git a/corev_apu/axi_node b/corev_apu/axi_node deleted file mode 160000 index a29a69a543..0000000000 --- a/corev_apu/axi_node +++ /dev/null @@ -1 +0,0 @@ -Subproject commit a29a69a543e96d0c9f79ea9c7df20580b3da5002 diff --git a/corev_apu/fpga/scripts/run.tcl b/corev_apu/fpga/scripts/run.tcl index 71675bc4c8..fd2b15f2a3 100644 --- a/corev_apu/fpga/scripts/run.tcl +++ b/corev_apu/fpga/scripts/run.tcl @@ -38,7 +38,7 @@ read_ip { \ } # read_ip xilinx/xlnx_protocol_checker/ip/xlnx_protocol_checker.xci -set_property include_dirs { "src/axi_sd_bridge/include" "../../common/submodules/common_cells/include" } [current_fileset] +set_property include_dirs { "src/axi_sd_bridge/include" "../../common/submodules/common_cells/include" "../axi/include"} [current_fileset] source scripts/add_sources.tcl diff --git a/corev_apu/fpga/src/ariane_xilinx.sv b/corev_apu/fpga/src/ariane_xilinx.sv index d2900c4465..7e85f95c35 100644 --- a/corev_apu/fpga/src/ariane_xilinx.sv +++ b/corev_apu/fpga/src/ariane_xilinx.sv @@ -253,48 +253,50 @@ assign rst = ddr_sync_reset; // --------------- // AXI Xbar // --------------- -axi_node_wrap_with_slices #( - // three ports from Ariane (instruction, data and bypass) - .NB_SLAVE ( NBSlave ), - .NB_MASTER ( ariane_soc::NB_PERIPHERALS ), - .NB_REGION ( ariane_soc::NrRegion ), - .AXI_ADDR_WIDTH ( AxiAddrWidth ), - .AXI_DATA_WIDTH ( AxiDataWidth ), - .AXI_USER_WIDTH ( AxiUserWidth ), - .AXI_ID_WIDTH ( AxiIdWidthMaster ), - .MASTER_SLICE_DEPTH ( 2 ), - .SLAVE_SLICE_DEPTH ( 2 ) + +axi_pkg::xbar_rule_64_t [ariane_soc::NB_PERIPHERALS-1:0] addr_map; + +assign addr_map = '{ + '{ idx: ariane_soc::Debug, start_addr: ariane_soc::DebugBase, end_addr: ariane_soc::DebugBase + ariane_soc::DebugLength }, + '{ idx: ariane_soc::ROM, start_addr: ariane_soc::ROMBase, end_addr: ariane_soc::ROMBase + ariane_soc::ROMLength }, + '{ idx: ariane_soc::CLINT, start_addr: ariane_soc::CLINTBase, end_addr: ariane_soc::CLINTBase + ariane_soc::CLINTLength }, + '{ idx: ariane_soc::PLIC, start_addr: ariane_soc::PLICBase, end_addr: ariane_soc::PLICBase + ariane_soc::PLICLength }, + '{ idx: ariane_soc::UART, start_addr: ariane_soc::UARTBase, end_addr: ariane_soc::UARTBase + ariane_soc::UARTLength }, + '{ idx: ariane_soc::Timer, start_addr: ariane_soc::TimerBase, end_addr: ariane_soc::TimerBase + ariane_soc::TimerLength }, + '{ idx: ariane_soc::SPI, start_addr: ariane_soc::SPIBase, end_addr: ariane_soc::SPIBase + ariane_soc::SPILength }, + '{ idx: ariane_soc::Ethernet, start_addr: ariane_soc::EthernetBase, end_addr: ariane_soc::EthernetBase + ariane_soc::EthernetLength }, + '{ idx: ariane_soc::GPIO, start_addr: ariane_soc::GPIOBase, end_addr: ariane_soc::GPIOBase + ariane_soc::GPIOLength }, + '{ idx: ariane_soc::DRAM, start_addr: ariane_soc::DRAMBase, end_addr: ariane_soc::DRAMBase + ariane_soc::DRAMLength } +}; + +localparam axi_pkg::xbar_cfg_t AXI_XBAR_CFG = '{ + NoSlvPorts: ariane_soc::NrSlaves, + NoMstPorts: ariane_soc::NB_PERIPHERALS, + MaxMstTrans: 1, // Probably requires update + MaxSlvTrans: 1, // Probably requires update + FallThrough: 1'b0, + LatencyMode: axi_pkg::CUT_ALL_PORTS, + AxiIdWidthSlvPorts: AxiIdWidthMaster, + AxiIdUsedSlvPorts: AxiIdWidthMaster, + UniqueIds: 1'b0, + AxiAddrWidth: AxiAddrWidth, + AxiDataWidth: AxiDataWidth, + NoAddrRules: ariane_soc::NB_PERIPHERALS +}; + +axi_xbar_intf #( + .AXI_USER_WIDTH ( AxiUserWidth ), + .Cfg ( AXI_XBAR_CFG ), + .rule_t ( axi_pkg::xbar_rule_64_t ) ) i_axi_xbar ( - .clk ( clk ), - .rst_n ( ndmreset_n ), - .test_en_i ( test_en ), - .slave ( slave ), - .master ( master ), - .start_addr_i ({ - ariane_soc::DebugBase, - ariane_soc::ROMBase, - ariane_soc::CLINTBase, - ariane_soc::PLICBase, - ariane_soc::UARTBase, - ariane_soc::TimerBase, - ariane_soc::SPIBase, - ariane_soc::EthernetBase, - ariane_soc::GPIOBase, - ariane_soc::DRAMBase - }), - .end_addr_i ({ - ariane_soc::DebugBase + ariane_soc::DebugLength - 1, - ariane_soc::ROMBase + ariane_soc::ROMLength - 1, - ariane_soc::CLINTBase + ariane_soc::CLINTLength - 1, - ariane_soc::PLICBase + ariane_soc::PLICLength - 1, - ariane_soc::UARTBase + ariane_soc::UARTLength - 1, - ariane_soc::TimerBase + ariane_soc::TimerLength - 1, - ariane_soc::SPIBase + ariane_soc::SPILength - 1, - ariane_soc::EthernetBase + ariane_soc::EthernetLength -1, - ariane_soc::GPIOBase + ariane_soc::GPIOLength - 1, - ariane_soc::DRAMBase + ariane_soc::DRAMLength - 1 - }), - .valid_rule_i (ariane_soc::ValidRule) + .clk_i ( clk_i ), + .rst_ni ( ndmreset_n ), + .test_i ( test_en ), + .slv_ports ( slave ), + .mst_ports ( master ), + .addr_map_i ( addr_map ), + .en_default_mst_port_i ( '0 ), + .default_mst_port_i ( '0 ) ); // --------------- diff --git a/corev_apu/register_interface b/corev_apu/register_interface index d8aeccc65f..48a7d6cae9 160000 --- a/corev_apu/register_interface +++ b/corev_apu/register_interface @@ -1 +1 @@ -Subproject commit d8aeccc65fdbbb30ef9dd28e065c2947a2396eab +Subproject commit 48a7d6cae9bd9cac16cebde1920dd2a657a3bdc5 diff --git a/corev_apu/tb/ariane_testharness.sv b/corev_apu/tb/ariane_testharness.sv index 965af63ca5..7ea64508e8 100644 --- a/corev_apu/tb/ariane_testharness.sv +++ b/corev_apu/tb/ariane_testharness.sv @@ -13,6 +13,8 @@ // Description: Test-harness for Ariane // Instantiates an AXI-Bus and memories +`include "axi/assign.svh" + module ariane_testharness #( parameter int unsigned AXI_USER_WIDTH = 1, parameter int unsigned AXI_ADDRESS_WIDTH = 64, @@ -281,7 +283,8 @@ module ariane_testharness #( ); axi_adapter #( - .DATA_WIDTH ( AXI_DATA_WIDTH ) + .DATA_WIDTH ( AXI_DATA_WIDTH ), + .AXI_ID_WIDTH ( ariane_soc::IdWidth ) ) i_dm_axi_master ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), @@ -344,6 +347,30 @@ module ariane_testharness #( .rdata_o ( rom_rdata ) ); `endif + + // ------------------------------ + // GPIO + // ------------------------------ + + // GPIO not implemented, adding an error slave here + + ariane_axi_soc::req_t gpio_req; + ariane_axi_soc::resp_t gpio_resp; + `AXI_ASSIGN_TO_REQ(gpio_req, master[ariane_soc::GPIO]) + `AXI_ASSIGN_FROM_RESP(master[ariane_soc::GPIO], gpio_resp) + axi_err_slv #( + .AxiIdWidth ( ariane_soc::IdWidthSlave ), + .req_t ( ariane_axi_soc::req_t ), + .resp_t ( ariane_axi_soc::resp_t ) + ) i_gpio_err_slv ( + .clk_i ( clk_i ), + .rst_ni ( ndmreset_n ), + .test_i ( test_en ), + .slv_req_i ( gpio_req ), + .slv_resp_o ( gpio_resp ) + ); + + // ------------------------------ // Memory + Exclusive Access // ------------------------------ @@ -382,137 +409,22 @@ module ariane_testharness #( .AXI_USER_WIDTH ( AXI_USER_WIDTH ) ) dram_delayed(); - ariane_axi_soc::aw_chan_slv_t aw_chan_i; - ariane_axi_soc::w_chan_t w_chan_i; - ariane_axi_soc::b_chan_slv_t b_chan_o; - ariane_axi_soc::ar_chan_slv_t ar_chan_i; - ariane_axi_soc::r_chan_slv_t r_chan_o; - ariane_axi_soc::aw_chan_slv_t aw_chan_o; - ariane_axi_soc::w_chan_t w_chan_o; - ariane_axi_soc::b_chan_slv_t b_chan_i; - ariane_axi_soc::ar_chan_slv_t ar_chan_o; - ariane_axi_soc::r_chan_slv_t r_chan_i; - - axi_delayer #( - .aw_t ( ariane_axi_soc::aw_chan_slv_t ), - .w_t ( ariane_axi_soc::w_chan_t ), - .b_t ( ariane_axi_soc::b_chan_slv_t ), - .ar_t ( ariane_axi_soc::ar_chan_slv_t ), - .r_t ( ariane_axi_soc::r_chan_slv_t ), - .StallRandomOutput ( StallRandomOutput ), - .StallRandomInput ( StallRandomInput ), - .FixedDelayInput ( 0 ), - .FixedDelayOutput ( 0 ) + axi_delayer_intf #( + .AXI_ID_WIDTH ( ariane_soc::IdWidthSlave ), + .AXI_ADDR_WIDTH ( AXI_ADDRESS_WIDTH ), + .AXI_DATA_WIDTH ( AXI_DATA_WIDTH ), + .AXI_USER_WIDTH ( AXI_USER_WIDTH ), + .STALL_RANDOM_INPUT ( StallRandomInput ), + .STALL_RANDOM_OUTPUT ( StallRandomOutput ), + .FIXED_DELAY_INPUT ( 0 ), + .FIXED_DELAY_OUTPUT ( 0 ) ) i_axi_delayer ( - .clk_i ( clk_i ), - .rst_ni ( ndmreset_n ), - .aw_valid_i ( dram.aw_valid ), - .aw_chan_i ( aw_chan_i ), - .aw_ready_o ( dram.aw_ready ), - .w_valid_i ( dram.w_valid ), - .w_chan_i ( w_chan_i ), - .w_ready_o ( dram.w_ready ), - .b_valid_o ( dram.b_valid ), - .b_chan_o ( b_chan_o ), - .b_ready_i ( dram.b_ready ), - .ar_valid_i ( dram.ar_valid ), - .ar_chan_i ( ar_chan_i ), - .ar_ready_o ( dram.ar_ready ), - .r_valid_o ( dram.r_valid ), - .r_chan_o ( r_chan_o ), - .r_ready_i ( dram.r_ready ), - .aw_valid_o ( dram_delayed.aw_valid ), - .aw_chan_o ( aw_chan_o ), - .aw_ready_i ( dram_delayed.aw_ready ), - .w_valid_o ( dram_delayed.w_valid ), - .w_chan_o ( w_chan_o ), - .w_ready_i ( dram_delayed.w_ready ), - .b_valid_i ( dram_delayed.b_valid ), - .b_chan_i ( b_chan_i ), - .b_ready_o ( dram_delayed.b_ready ), - .ar_valid_o ( dram_delayed.ar_valid ), - .ar_chan_o ( ar_chan_o ), - .ar_ready_i ( dram_delayed.ar_ready ), - .r_valid_i ( dram_delayed.r_valid ), - .r_chan_i ( r_chan_i ), - .r_ready_o ( dram_delayed.r_ready ) + .clk_i ( clk_i ), + .rst_ni ( ndmreset_n ), + .slv ( dram ), + .mst ( dram_delayed ) ); - assign aw_chan_i.atop = dram.aw_atop; - assign aw_chan_i.id = dram.aw_id; - assign aw_chan_i.addr = dram.aw_addr; - assign aw_chan_i.len = dram.aw_len; - assign aw_chan_i.size = dram.aw_size; - assign aw_chan_i.burst = dram.aw_burst; - assign aw_chan_i.lock = dram.aw_lock; - assign aw_chan_i.cache = dram.aw_cache; - assign aw_chan_i.prot = dram.aw_prot; - assign aw_chan_i.qos = dram.aw_qos; - assign aw_chan_i.region = dram.aw_region; - - assign ar_chan_i.id = dram.ar_id; - assign ar_chan_i.addr = dram.ar_addr; - assign ar_chan_i.len = dram.ar_len; - assign ar_chan_i.size = dram.ar_size; - assign ar_chan_i.burst = dram.ar_burst; - assign ar_chan_i.lock = dram.ar_lock; - assign ar_chan_i.cache = dram.ar_cache; - assign ar_chan_i.prot = dram.ar_prot; - assign ar_chan_i.qos = dram.ar_qos; - assign ar_chan_i.region = dram.ar_region; - - assign w_chan_i.data = dram.w_data; - assign w_chan_i.strb = dram.w_strb; - assign w_chan_i.last = dram.w_last; - - assign dram.r_id = r_chan_o.id; - assign dram.r_data = r_chan_o.data; - assign dram.r_resp = r_chan_o.resp; - assign dram.r_last = r_chan_o.last; - - assign dram.b_id = b_chan_o.id; - assign dram.b_resp = b_chan_o.resp; - - assign dram_delayed.aw_id = aw_chan_o.id; - assign dram_delayed.aw_addr = aw_chan_o.addr; - assign dram_delayed.aw_len = aw_chan_o.len; - assign dram_delayed.aw_size = aw_chan_o.size; - assign dram_delayed.aw_burst = aw_chan_o.burst; - assign dram_delayed.aw_lock = aw_chan_o.lock; - assign dram_delayed.aw_cache = aw_chan_o.cache; - assign dram_delayed.aw_prot = aw_chan_o.prot; - assign dram_delayed.aw_qos = aw_chan_o.qos; - assign dram_delayed.aw_atop = aw_chan_o.atop; - assign dram_delayed.aw_region = aw_chan_o.region; - assign dram_delayed.aw_user = '0; - - assign dram_delayed.ar_id = ar_chan_o.id; - assign dram_delayed.ar_addr = ar_chan_o.addr; - assign dram_delayed.ar_len = ar_chan_o.len; - assign dram_delayed.ar_size = ar_chan_o.size; - assign dram_delayed.ar_burst = ar_chan_o.burst; - assign dram_delayed.ar_lock = ar_chan_o.lock; - assign dram_delayed.ar_cache = ar_chan_o.cache; - assign dram_delayed.ar_prot = ar_chan_o.prot; - assign dram_delayed.ar_qos = ar_chan_o.qos; - assign dram_delayed.ar_region = ar_chan_o.region; - assign dram_delayed.ar_user = '0; - - assign dram_delayed.w_data = w_chan_o.data; - assign dram_delayed.w_strb = w_chan_o.strb; - assign dram_delayed.w_last = w_chan_o.last; - assign dram_delayed.w_user = '0; - - assign r_chan_i.id = dram_delayed.r_id; - assign r_chan_i.data = dram_delayed.r_data; - assign r_chan_i.resp = dram_delayed.r_resp; - assign r_chan_i.last = dram_delayed.r_last; - assign dram.r_user = '0; - - assign b_chan_i.id = dram_delayed.b_id; - assign b_chan_i.resp = dram_delayed.b_resp; - assign dram.b_user = '0; - axi2mem #( .AXI_ID_WIDTH ( ariane_soc::IdWidthSlave ), .AXI_ADDR_WIDTH ( AXI_ADDRESS_WIDTH ), @@ -550,49 +462,50 @@ module ariane_testharness #( // --------------- // AXI Xbar // --------------- - typedef logic [ariane_soc::NrRegion-1:0][ariane_soc::NB_PERIPHERALS-1:0][AXI_ADDRESS_WIDTH-1:0] addr_map_t; - - axi_node_intf_wrap #( - .NB_SLAVE ( ariane_soc::NrSlaves ), - .NB_MASTER ( ariane_soc::NB_PERIPHERALS ), - .NB_REGION ( ariane_soc::NrRegion ), - .AXI_ADDR_WIDTH ( AXI_ADDRESS_WIDTH ), - .AXI_DATA_WIDTH ( AXI_DATA_WIDTH ), - .AXI_USER_WIDTH ( AXI_USER_WIDTH ), - .AXI_ID_WIDTH ( ariane_soc::IdWidth ) - // .MASTER_SLICE_DEPTH ( 0 ), - // .SLAVE_SLICE_DEPTH ( 0 ) + + axi_pkg::xbar_rule_64_t [ariane_soc::NB_PERIPHERALS-1:0] addr_map; + + assign addr_map = '{ + '{ idx: ariane_soc::Debug, start_addr: ariane_soc::DebugBase, end_addr: ariane_soc::DebugBase + ariane_soc::DebugLength }, + '{ idx: ariane_soc::ROM, start_addr: ariane_soc::ROMBase, end_addr: ariane_soc::ROMBase + ariane_soc::ROMLength }, + '{ idx: ariane_soc::CLINT, start_addr: ariane_soc::CLINTBase, end_addr: ariane_soc::CLINTBase + ariane_soc::CLINTLength }, + '{ idx: ariane_soc::PLIC, start_addr: ariane_soc::PLICBase, end_addr: ariane_soc::PLICBase + ariane_soc::PLICLength }, + '{ idx: ariane_soc::UART, start_addr: ariane_soc::UARTBase, end_addr: ariane_soc::UARTBase + ariane_soc::UARTLength }, + '{ idx: ariane_soc::Timer, start_addr: ariane_soc::TimerBase, end_addr: ariane_soc::TimerBase + ariane_soc::TimerLength }, + '{ idx: ariane_soc::SPI, start_addr: ariane_soc::SPIBase, end_addr: ariane_soc::SPIBase + ariane_soc::SPILength }, + '{ idx: ariane_soc::Ethernet, start_addr: ariane_soc::EthernetBase, end_addr: ariane_soc::EthernetBase + ariane_soc::EthernetLength }, + '{ idx: ariane_soc::GPIO, start_addr: ariane_soc::GPIOBase, end_addr: ariane_soc::GPIOBase + ariane_soc::GPIOLength }, + '{ idx: ariane_soc::DRAM, start_addr: ariane_soc::DRAMBase, end_addr: ariane_soc::DRAMBase + ariane_soc::DRAMLength } + }; + + localparam axi_pkg::xbar_cfg_t AXI_XBAR_CFG = '{ + NoSlvPorts: ariane_soc::NrSlaves, + NoMstPorts: ariane_soc::NB_PERIPHERALS, + MaxMstTrans: 1, // Probably requires update + MaxSlvTrans: 1, // Probably requires update + FallThrough: 1'b0, + LatencyMode: axi_pkg::NO_LATENCY, + AxiIdWidthSlvPorts: ariane_soc::IdWidth, + AxiIdUsedSlvPorts: ariane_soc::IdWidth, + UniqueIds: 1'b0, + AxiAddrWidth: AXI_ADDRESS_WIDTH, + AxiDataWidth: AXI_DATA_WIDTH, + NoAddrRules: ariane_soc::NB_PERIPHERALS + }; + + axi_xbar_intf #( + .AXI_USER_WIDTH ( AXI_USER_WIDTH ), + .Cfg ( AXI_XBAR_CFG ), + .rule_t ( axi_pkg::xbar_rule_64_t ) ) i_axi_xbar ( - .clk ( clk_i ), - .rst_n ( ndmreset_n ), - .test_en_i ( test_en ), - .slave ( slave ), - .master ( master ), - .start_addr_i ({ - ariane_soc::DebugBase, - ariane_soc::ROMBase, - ariane_soc::CLINTBase, - ariane_soc::PLICBase, - ariane_soc::UARTBase, - ariane_soc::TimerBase, - ariane_soc::SPIBase, - ariane_soc::EthernetBase, - ariane_soc::GPIOBase, - ariane_soc::DRAMBase - }), - .end_addr_i ({ - ariane_soc::DebugBase + ariane_soc::DebugLength - 1, - ariane_soc::ROMBase + ariane_soc::ROMLength - 1, - ariane_soc::CLINTBase + ariane_soc::CLINTLength - 1, - ariane_soc::PLICBase + ariane_soc::PLICLength - 1, - ariane_soc::UARTBase + ariane_soc::UARTLength - 1, - ariane_soc::TimerBase + ariane_soc::TimerLength - 1, - ariane_soc::SPIBase + ariane_soc::SPILength - 1, - ariane_soc::EthernetBase + ariane_soc::EthernetLength -1, - ariane_soc::GPIOBase + ariane_soc::GPIOLength - 1, - ariane_soc::DRAMBase + ariane_soc::DRAMLength - 1 - }), - .valid_rule_i (ariane_soc::ValidRule) + .clk_i ( clk_i ), + .rst_ni ( ndmreset_n ), + .test_i ( test_en ), + .slv_ports ( slave ), + .mst_ports ( master ), + .addr_map_i ( addr_map ), + .en_default_mst_port_i ( '0 ), + .default_mst_port_i ( '0 ) ); // ---------------