SA-1 Speed Test v5.1 shows some major differences

[birdybro]

The SNES SA-1 Speed Test v5.1 rom from @VitorVilela7 shows some interesting results. This is all tested with the 20220909 release build. These are minor observations, I am not sure if they actually impact gameplay that much at all, but figured it was worth it to document and put here in case it's useful.

MiSTer Results:

Compare these results to the real hardware tests from QcRetro:

https://github.com/VitorVilela7/SnesSpeedTest/tree/master/img/hardware#1l8b-10-v51

Most results are going quite a bit faster than the original hardware (there may be some hardware variation to account for some of this). The ones that stand out are:

• Page 3/4 - WRAM - ROM (JMP) is 3 MHz faster on MiSTer.
• Page 3/4 - ROM - ROM (JMP) is 1.34MHz faster on MiSTer.
• Page 3/4 - WRAM - ROM (JML) is 1.8MHz faster on MiSTer.
• Page 3/4 - ROM - ROM (RTL) is 1.5MHz slower on MiSTer.
• Page 3/4 - ROM - ROM (RTI) is 2.7MHz faster on MiSTer.
• Page 4/4 ROM - I --> BW-RAM P - Core Speed is 9.2MHz slower on MiSTer. (huge difference for some reason, 0.14MHz instead of 10.34MHz)
• Page 4/4 ROM - BW --> I-RAM P - Core Speed is 9.26MHz slower on MiSTer. (another huge difference, 0.14MHz instead of 10.40MHz)

I'm not sure if any gameplay is affected by these, just reporting them as @wwark brought it to my attention. There are some other minor differences, but I chose not to include ones that were less than 1MHz difference in the results, since it's possible hardware variance could account for this.

[paulb-nl]

The ROM is faster on this core because it reads the ROM at 10.74Mhz 16bits while it should be 5.37Mhz 16 bits.

Note 2: It's believed that the SA-1 ROM access is actually 5.37 MHz with a 16-bit bus. Since two values are accessed at once, the effective speed end up being 10.74 MHz, however with a cost of the jump and certain branch operations taking one additional cycle, which justifies the behavior from note 1. However, that also means when the S-CPU accesses the game ROM, it will use a whole 5.37 MHz cycle, meaning that the SA-1 CPU will only have a single 5.37 MHz cycle per time. In practice, parallel accesses by both CPUs will clock down the SA-1 CPU to 5.37 MHz, even if the SNES only does an access every 8 master cycles and SA-1 every 2 master cycles. A single S-CPU access will take 4 master cycles from ROM and the same from SA-1. However, internal SA-1 cycles are still 10.74 MHz.

For the Page 4/4 IRAM<->BWRAM DMA tests, the core speed is 0.14Mhz because during the test the SA1 accesses IRAM and currently the core pauses the SA1 when DMA and SA1 both access IRAM.

My guess is that because BWRAM is accessed at 5MHz and IRAM at 10MHz there is one 10Mhz idle cycle for IRAM during DMA so there is 1 cycle for DMA and 1 cycle for SA1 so it should not be paused.

[srg320]

The ROM is faster on this core because it reads the ROM at 10.74Mhz 16bits while it should be 5.37Mhz 16 bits.

No, it's not. Core just reads the high and low bytes over again every cycle. The original SA1 reads a word every 2 cycles, uses the high byte in the current cycle and saves the low byte for the next cycle. But after the jump commands you have to re-read the new word because the next byte follows the new address, not the next address. This feature is not emulated in the core.

For the Page 4/4 IRAM<->BWRAM DMA tests, the core speed is 0.14Mhz because during the test the SA1 accesses IRAM and currently the core pauses the SA1 when DMA and SA1 both access IRAM.

My guess is that because BWRAM is accessed at 5MHz and IRAM at 10MHz there is one 10Mhz idle cycle for IRAM during DMA so there is 1 cycle for DMA and 1 cycle for SA1 so it should not be paused.

I think the same thing.

I ordered the original cartridge with the SA1 chip. When I got it, I will try to research these aspects with the LA.