From 83b10c27884dad6006280f6c9b14234f413da704 Mon Sep 17 00:00:00 2001
From: Bernhard Manfred Gruber <bernhardmgruber@gmail.com>
Date: Tue, 28 Jan 2025 21:55:48 +0100
Subject: [PATCH 01/33] Update ptx_isa.h to include 8.6 and 8.7 (#3563)

---
 libcudacxx/include/cuda/std/__cccl/ptx_isa.h | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/libcudacxx/include/cuda/std/__cccl/ptx_isa.h b/libcudacxx/include/cuda/std/__cccl/ptx_isa.h
index c351d402a31..e64504fb1d8 100644
--- a/libcudacxx/include/cuda/std/__cccl/ptx_isa.h
+++ b/libcudacxx/include/cuda/std/__cccl/ptx_isa.h
@@ -31,11 +31,14 @@
  * https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#release-notes
  */
 
-// PTX ISA 8.5 is available from CUDA 12.5
+// PTX ISA 8.7 is available from CUDA 12.8
 // The first define is for future major versions of CUDACC.
 // We make sure that these get the highest known PTX ISA version.
 #if _CCCL_CUDACC_AT_LEAST(13, 0)
-#  define __cccl_ptx_isa 850ULL
+#  define __cccl_ptx_isa 870ULL
+// PTX ISA 8.7 is available from CUDA 12.8, driver r570
+#elif _CCCL_CUDACC_AT_LEAST(12, 8)
+#  define __cccl_ptx_isa 870ULL
 // PTX ISA 8.5 is available from CUDA 12.5, driver r555
 #elif _CCCL_CUDACC_AT_LEAST(12, 5)
 #  define __cccl_ptx_isa 850ULL

From 2a03b6e78ef476b596eb34a42c0b38fb15489efe Mon Sep 17 00:00:00 2001
From: Eric Niebler <eniebler@nvidia.com>
Date: Tue, 28 Jan 2025 19:10:33 -0800
Subject: [PATCH 02/33] add missing visibility annotations to ustdex types that
 have data members (#3571)

---
 .../experimental/__async/sender/basic_sender.cuh     |  6 +++---
 .../cuda/experimental/__async/sender/conditional.cuh |  4 ++--
 .../cuda/experimental/__async/sender/continue_on.cuh | 10 +++++-----
 .../include/cuda/experimental/__async/sender/env.cuh |  6 +++---
 .../cuda/experimental/__async/sender/just.cuh        |  4 ++--
 .../cuda/experimental/__async/sender/just_from.cuh   |  2 +-
 .../cuda/experimental/__async/sender/let_value.cuh   |  4 ++--
 .../cuda/experimental/__async/sender/read_env.cuh    |  8 ++++----
 .../cuda/experimental/__async/sender/sequence.cuh    |  6 +++---
 .../experimental/__async/sender/start_detached.cuh   |  4 ++--
 .../cuda/experimental/__async/sender/start_on.cuh    |  6 +++---
 .../cuda/experimental/__async/sender/sync_wait.cuh   |  2 +-
 .../cuda/experimental/__async/sender/then.cuh        |  4 ++--
 .../experimental/__async/sender/thread_context.cuh   |  2 +-
 .../cuda/experimental/__async/sender/when_all.cuh    | 12 ++++++------
 .../cuda/experimental/__async/sender/write_env.cuh   |  6 +++---
 16 files changed, 43 insertions(+), 43 deletions(-)

diff --git a/cudax/include/cuda/experimental/__async/sender/basic_sender.cuh b/cudax/include/cuda/experimental/__async/sender/basic_sender.cuh
index ae8ad239d46..273daaa5e07 100644
--- a/cudax/include/cuda/experimental/__async/sender/basic_sender.cuh
+++ b/cudax/include/cuda/experimental/__async/sender/basic_sender.cuh
@@ -75,7 +75,7 @@ struct receiver_defaults
 };
 
 template <class _Data, class _Rcvr>
-struct basic_receiver
+struct _CCCL_TYPE_VISIBILITY_DEFAULT basic_receiver
 {
   using receiver_concept = __async::receiver_t;
   using __rcvr_t         = typename _Data::receiver_tag;
@@ -212,10 +212,10 @@ _CUDAX_TRIVIAL_API auto __get_attrs(long, const _Data&, const _Sndrs&... __sndrs
 }
 
 template <class _Data, class... _Sndrs>
-struct basic_sender;
+struct _CCCL_TYPE_VISIBILITY_DEFAULT basic_sender;
 
 template <class _Data, class _Sndr>
-struct basic_sender<_Data, _Sndr>
+struct _CCCL_TYPE_VISIBILITY_DEFAULT basic_sender<_Data, _Sndr>
 {
   using sender_concept = __async::sender_t;
   using __tag_t        = typename _Data::sender_tag;
diff --git a/cudax/include/cuda/experimental/__async/sender/conditional.cuh b/cudax/include/cuda/experimental/__async/sender/conditional.cuh
index 89aca853851..d913d315638 100644
--- a/cudax/include/cuda/experimental/__async/sender/conditional.cuh
+++ b/cudax/include/cuda/experimental/__async/sender/conditional.cuh
@@ -135,7 +135,7 @@ struct __cond_t
   };
 
   template <class _Sndr, class _Pred, class _Then, class _Else>
-  struct __sndr_t;
+  struct _CCCL_TYPE_VISIBILITY_DEFAULT __sndr_t;
 
   template <class _Pred, class _Then, class _Else>
   struct __closure
@@ -174,7 +174,7 @@ struct __cond_t
 };
 
 template <class _Sndr, class _Pred, class _Then, class _Else>
-struct __cond_t::__sndr_t
+struct _CCCL_TYPE_VISIBILITY_DEFAULT __cond_t::__sndr_t
 {
   __cond_t __tag_;
   __cond_t::__data<_Pred, _Then, _Else> __data_;
diff --git a/cudax/include/cuda/experimental/__async/sender/continue_on.cuh b/cudax/include/cuda/experimental/__async/sender/continue_on.cuh
index 8da87a443a3..b0ccd33fb9e 100644
--- a/cudax/include/cuda/experimental/__async/sender/continue_on.cuh
+++ b/cudax/include/cuda/experimental/__async/sender/continue_on.cuh
@@ -65,7 +65,7 @@ private:
                               completion_signatures<set_error_t(__decay_t<_Error>), set_error_t(::std::exception_ptr)>>;
 
   template <class _Rcvr, class _Result>
-  struct __rcvr_t
+  struct _CCCL_TYPE_VISIBILITY_DEFAULT __rcvr_t
   {
     using receiver_concept = receiver_t;
     _Rcvr __rcvr_;
@@ -127,7 +127,7 @@ private:
   };
 
   template <class _Rcvr, class _CvSndr, class _Sch>
-  struct __opstate_t
+  struct _CCCL_TYPE_VISIBILITY_DEFAULT __opstate_t
   {
     _CUDAX_API friend auto get_env(const __opstate_t* __self) noexcept -> env_of_t<_Rcvr>
     {
@@ -197,7 +197,7 @@ private:
   };
 
   template <class _Sndr, class _Sch>
-  struct __sndr_t;
+  struct _CCCL_TYPE_VISIBILITY_DEFAULT __sndr_t;
 
   template <class _Sch>
   struct __closure_t;
@@ -211,7 +211,7 @@ public:
 };
 
 template <class _Sch>
-struct continue_on_t::__closure_t
+struct _CCCL_TYPE_VISIBILITY_DEFAULT continue_on_t::__closure_t
 {
   _Sch __sch;
 
@@ -223,7 +223,7 @@ struct continue_on_t::__closure_t
 };
 
 template <class _Sndr, class _Sch>
-struct continue_on_t::__sndr_t
+struct _CCCL_TYPE_VISIBILITY_DEFAULT continue_on_t::__sndr_t
 {
   using sender_concept = sender_t;
   _CCCL_NO_UNIQUE_ADDRESS continue_on_t __tag;
diff --git a/cudax/include/cuda/experimental/__async/sender/env.cuh b/cudax/include/cuda/experimental/__async/sender/env.cuh
index 3254181642b..eb0e232fead 100644
--- a/cudax/include/cuda/experimental/__async/sender/env.cuh
+++ b/cudax/include/cuda/experimental/__async/sender/env.cuh
@@ -63,7 +63,7 @@ template <class _Ty>
 using __unwrap_reference_t = decltype(__unwrap_ref<_Ty>);
 
 template <class _Query, class _Value>
-struct prop
+struct _CCCL_TYPE_VISIBILITY_DEFAULT prop
 {
   _CCCL_NO_UNIQUE_ADDRESS _Query __query;
   _CCCL_NO_UNIQUE_ADDRESS _Value __value;
@@ -77,7 +77,7 @@ struct prop
 };
 
 template <class... _Envs>
-struct env
+struct _CCCL_TYPE_VISIBILITY_DEFAULT env
 {
   __tuple<_Envs...> __envs_;
 
@@ -108,7 +108,7 @@ struct env
 
 // partial specialization for two environments
 template <class _Env0, class _Env1>
-struct env<_Env0, _Env1>
+struct _CCCL_TYPE_VISIBILITY_DEFAULT env<_Env0, _Env1>
 {
   _CCCL_NO_UNIQUE_ADDRESS _Env0 __env0_;
   _CCCL_NO_UNIQUE_ADDRESS _Env1 __env1_;
diff --git a/cudax/include/cuda/experimental/__async/sender/just.cuh b/cudax/include/cuda/experimental/__async/sender/just.cuh
index 3230b40ca93..3570de31624 100644
--- a/cudax/include/cuda/experimental/__async/sender/just.cuh
+++ b/cudax/include/cuda/experimental/__async/sender/just.cuh
@@ -61,7 +61,7 @@ private:
   using _SetTag  = decltype(__detail::__set_tag<_Disposition>());
 
   template <class _Rcvr, class... _Ts>
-  struct __opstate_t
+  struct _CCCL_TYPE_VISIBILITY_DEFAULT __opstate_t
   {
     using operation_state_concept = operation_state_t;
     using completion_signatures   = __async::completion_signatures<_SetTag(_Ts...)>;
@@ -85,7 +85,7 @@ private:
   };
 
   template <class... _Ts>
-  struct __sndr_t
+  struct _CCCL_TYPE_VISIBILITY_DEFAULT __sndr_t
   {
     using sender_concept        = sender_t;
     using completion_signatures = __async::completion_signatures<_SetTag(_Ts...)>;
diff --git a/cudax/include/cuda/experimental/__async/sender/just_from.cuh b/cudax/include/cuda/experimental/__async/sender/just_from.cuh
index 40df8b56825..f1e2ec87016 100644
--- a/cudax/include/cuda/experimental/__async/sender/just_from.cuh
+++ b/cudax/include/cuda/experimental/__async/sender/just_from.cuh
@@ -112,7 +112,7 @@ private:
   };
 
   template <class _Fn>
-  struct __sndr_t
+  struct _CCCL_TYPE_VISIBILITY_DEFAULT __sndr_t
   {
     using sender_concept = sender_t;
 
diff --git a/cudax/include/cuda/experimental/__async/sender/let_value.cuh b/cudax/include/cuda/experimental/__async/sender/let_value.cuh
index 6742a1c1d6c..f681b0ad88b 100644
--- a/cudax/include/cuda/experimental/__async/sender/let_value.cuh
+++ b/cudax/include/cuda/experimental/__async/sender/let_value.cuh
@@ -146,7 +146,7 @@ private:
   /// @tparam _Rcvr The receiver connected to the `let_(value|error|stopped)`
   /// sender.
   template <class _Rcvr, class _CvSndr, class _Fn>
-  struct __opstate_t
+  struct _CCCL_TYPE_VISIBILITY_DEFAULT __opstate_t
   {
     _CUDAX_API friend env_of_t<_Rcvr> get_env(const __opstate_t* __self) noexcept
     {
@@ -235,7 +235,7 @@ private:
   /// @tparam _Fn The function to be called when the predecessor sender
   /// completes.
   template <class _Sndr, class _Fn>
-  struct __sndr_t
+  struct _CCCL_TYPE_VISIBILITY_DEFAULT __sndr_t
   {
     using sender_concept = sender_t;
     _CCCL_NO_UNIQUE_ADDRESS _LetTag __tag_;
diff --git a/cudax/include/cuda/experimental/__async/sender/read_env.cuh b/cudax/include/cuda/experimental/__async/sender/read_env.cuh
index 758e37c5714..f62c0d27bd5 100644
--- a/cudax/include/cuda/experimental/__async/sender/read_env.cuh
+++ b/cudax/include/cuda/experimental/__async/sender/read_env.cuh
@@ -61,7 +61,7 @@ private:
   };
 
   template <class _Rcvr, class _Query>
-  struct __opstate_t
+  struct _CCCL_TYPE_VISIBILITY_DEFAULT __opstate_t
   {
     using operation_state_concept = operation_state_t;
     using completion_signatures   = //
@@ -107,7 +107,7 @@ private:
 
   // This makes read_env a dependent sender:
   template <class _Query>
-  struct __opstate_t<receiver_archetype, _Query>
+  struct _CCCL_TYPE_VISIBILITY_DEFAULT __opstate_t<receiver_archetype, _Query>
   {
     using operation_state_concept = operation_state_t;
     using completion_signatures   = dependent_completions;
@@ -116,7 +116,7 @@ private:
   };
 
   template <class _Query>
-  struct __sndr_t;
+  struct _CCCL_TYPE_VISIBILITY_DEFAULT __sndr_t;
 
 public:
   /// @brief Returns a sender that, when connected to a receiver and started,
@@ -127,7 +127,7 @@ public:
 };
 
 template <class _Query>
-struct read_env_t::__sndr_t
+struct _CCCL_TYPE_VISIBILITY_DEFAULT read_env_t::__sndr_t
 {
   using sender_concept = sender_t;
   _CCCL_NO_UNIQUE_ADDRESS read_env_t __tag;
diff --git a/cudax/include/cuda/experimental/__async/sender/sequence.cuh b/cudax/include/cuda/experimental/__async/sender/sequence.cuh
index 3f8b17c7413..87c5f05c2b7 100644
--- a/cudax/include/cuda/experimental/__async/sender/sequence.cuh
+++ b/cudax/include/cuda/experimental/__async/sender/sequence.cuh
@@ -43,7 +43,7 @@ struct __seq
   };
 
   template <class _Zip>
-  struct __opstate
+  struct _CCCL_TYPE_VISIBILITY_DEFAULT __opstate
   {
     using operation_state_concept = operation_state_t;
 
@@ -99,14 +99,14 @@ struct __seq
   };
 
   template <class _Sndr1, class _Sndr2>
-  struct __sndr_t;
+  struct _CCCL_TYPE_VISIBILITY_DEFAULT __sndr_t;
 
   template <class _Sndr1, class _Sndr2>
   _CUDAX_API auto operator()(_Sndr1 __sndr1, _Sndr2 __sndr2) const -> __sndr_t<_Sndr1, _Sndr2>;
 };
 
 template <class _Sndr1, class _Sndr2>
-struct __seq::__sndr_t
+struct _CCCL_TYPE_VISIBILITY_DEFAULT __seq::__sndr_t
 {
   using sender_concept = sender_t;
   using __sndr1_t      = _Sndr1;
diff --git a/cudax/include/cuda/experimental/__async/sender/start_detached.cuh b/cudax/include/cuda/experimental/__async/sender/start_detached.cuh
index df9d5c4e69e..7b4c620e5c1 100644
--- a/cudax/include/cuda/experimental/__async/sender/start_detached.cuh
+++ b/cudax/include/cuda/experimental/__async/sender/start_detached.cuh
@@ -40,7 +40,7 @@ private:
   struct __opstate_base_t : __immovable
   {};
 
-  struct __rcvr_t
+  struct _CCCL_TYPE_VISIBILITY_DEFAULT __rcvr_t
   {
     using receiver_concept = receiver_t;
 
@@ -66,7 +66,7 @@ private:
   };
 
   template <class _Sndr>
-  struct __opstate_t : __opstate_base_t
+  struct _CCCL_TYPE_VISIBILITY_DEFAULT __opstate_t : __opstate_base_t
   {
     using operation_state_concept = operation_state_t;
     using completion_signatures   = __async::completion_signatures_of_t<_Sndr, __rcvr_t>;
diff --git a/cudax/include/cuda/experimental/__async/sender/start_on.cuh b/cudax/include/cuda/experimental/__async/sender/start_on.cuh
index e2a04be7176..8656a57d489 100644
--- a/cudax/include/cuda/experimental/__async/sender/start_on.cuh
+++ b/cudax/include/cuda/experimental/__async/sender/start_on.cuh
@@ -52,7 +52,7 @@ private:
 #endif // !_CCCL_CUDA_COMPILER(NVCC)
 
   template <class _Rcvr, class _Sch, class _CvSndr>
-  struct __opstate_t
+  struct _CCCL_TYPE_VISIBILITY_DEFAULT __opstate_t
   {
     _CUDAX_API friend env_of_t<_Rcvr> get_env(const __opstate_t* __self) noexcept
     {
@@ -103,7 +103,7 @@ private:
   };
 
   template <class _Sch, class _Sndr>
-  struct __sndr_t;
+  struct _CCCL_TYPE_VISIBILITY_DEFAULT __sndr_t;
 
 public:
   template <class _Sch, class _Sndr>
@@ -112,7 +112,7 @@ public:
 } start_on{};
 
 template <class _Sch, class _Sndr>
-struct start_on_t::__sndr_t
+struct _CCCL_TYPE_VISIBILITY_DEFAULT start_on_t::__sndr_t
 {
   using sender_concept = sender_t;
   _CCCL_NO_UNIQUE_ADDRESS start_on_t __tag_;
diff --git a/cudax/include/cuda/experimental/__async/sender/sync_wait.cuh b/cudax/include/cuda/experimental/__async/sender/sync_wait.cuh
index 2f501b985df..ddf23694272 100644
--- a/cudax/include/cuda/experimental/__async/sender/sync_wait.cuh
+++ b/cudax/include/cuda/experimental/__async/sender/sync_wait.cuh
@@ -67,7 +67,7 @@ private:
   template <class _Sndr>
   struct __state_t
   {
-    struct __rcvr_t
+    struct _CCCL_TYPE_VISIBILITY_DEFAULT __rcvr_t
     {
       using receiver_concept = receiver_t;
       __state_t* __state_;
diff --git a/cudax/include/cuda/experimental/__async/sender/then.cuh b/cudax/include/cuda/experimental/__async/sender/then.cuh
index b2ab494f8d0..d9f6ca9ec3e 100644
--- a/cudax/include/cuda/experimental/__async/sender/then.cuh
+++ b/cudax/include/cuda/experimental/__async/sender/then.cuh
@@ -126,7 +126,7 @@ private:
                                    __type_try_quote<__concat_completion_signatures>::__call>;
 
   template <class _Rcvr, class _CvSndr, class _Fn>
-  struct __opstate_t
+  struct _CCCL_TYPE_VISIBILITY_DEFAULT __opstate_t
   {
     _CUDAX_API friend env_of_t<_Rcvr> get_env(const __opstate_t* __self) noexcept
     {
@@ -213,7 +213,7 @@ private:
   };
 
   template <class _Fn, class _Sndr>
-  struct __sndr_t
+  struct _CCCL_TYPE_VISIBILITY_DEFAULT __sndr_t
   {
     using sender_concept = sender_t;
     _CCCL_NO_UNIQUE_ADDRESS _UponTag __tag_;
diff --git a/cudax/include/cuda/experimental/__async/sender/thread_context.cuh b/cudax/include/cuda/experimental/__async/sender/thread_context.cuh
index 4a7c768ed25..c7b798a1734 100644
--- a/cudax/include/cuda/experimental/__async/sender/thread_context.cuh
+++ b/cudax/include/cuda/experimental/__async/sender/thread_context.cuh
@@ -33,7 +33,7 @@
 
 namespace cuda::experimental::__async
 {
-struct thread_context
+struct _CCCL_TYPE_VISIBILITY_DEFAULT thread_context
 {
   thread_context() noexcept
       : __thrd_{[this] {
diff --git a/cudax/include/cuda/experimental/__async/sender/when_all.cuh b/cudax/include/cuda/experimental/__async/sender/when_all.cuh
index 1274a725e44..de5f089b979 100644
--- a/cudax/include/cuda/experimental/__async/sender/when_all.cuh
+++ b/cudax/include/cuda/experimental/__async/sender/when_all.cuh
@@ -53,10 +53,10 @@ template <class>
 struct __env_t;
 
 template <class, size_t>
-struct __rcvr_t;
+struct _CCCL_TYPE_VISIBILITY_DEFAULT __rcvr_t;
 
 template <class, class, class>
-struct __opstate_t;
+struct _CCCL_TYPE_VISIBILITY_DEFAULT __opstate_t;
 
 using __tombstone = _ERROR<_WHERE(_IN_ALGORITHM, when_all_t), _WHAT(_SENDER_HAS_TOO_MANY_SUCCESS_COMPLETIONS)>;
 
@@ -322,7 +322,7 @@ struct __env_t
 };
 
 template <class _StateZip, size_t _Index>
-struct __rcvr_t
+struct _CCCL_TYPE_VISIBILITY_DEFAULT __rcvr_t
 {
   using receiver_concept = receiver_t;
   using __state_t        = __unzip<_StateZip>;
@@ -524,7 +524,7 @@ struct __state_t<_Rcvr, _CvFn, __tupl<_CUDA_VSTD::index_sequence<_Idx...>, _Sndr
 
 /// The operation state for when_all
 template <class _Rcvr, class _CvFn, size_t... _Idx, class... _Sndrs>
-struct __opstate_t<_Rcvr, _CvFn, __tupl<_CUDA_VSTD::index_sequence<_Idx...>, _Sndrs...>>
+struct _CCCL_TYPE_VISIBILITY_DEFAULT __opstate_t<_Rcvr, _CvFn, __tupl<_CUDA_VSTD::index_sequence<_Idx...>, _Sndrs...>>
 {
   using operation_state_concept = operation_state_t;
   using __sndrs_t               = _CUDA_VSTD::__type_call<_CvFn, __tuple<_Sndrs...>>;
@@ -605,7 +605,7 @@ struct __opstate_t<_Rcvr, _CvFn, __tupl<_CUDA_VSTD::index_sequence<_Idx...>, _Sn
 };
 
 template <class... _Sndrs>
-struct __sndr_t;
+struct _CCCL_TYPE_VISIBILITY_DEFAULT __sndr_t;
 } // namespace __when_all
 
 struct when_all_t
@@ -616,7 +616,7 @@ struct when_all_t
 
 // The sender for when_all
 template <class... _Sndrs>
-struct __when_all::__sndr_t
+struct _CCCL_TYPE_VISIBILITY_DEFAULT __when_all::__sndr_t
 {
   using sender_concept = sender_t;
   using __sndrs_t      = __tuple<_Sndrs...>;
diff --git a/cudax/include/cuda/experimental/__async/sender/write_env.cuh b/cudax/include/cuda/experimental/__async/sender/write_env.cuh
index 9cb61288671..1a9d6b913a8 100644
--- a/cudax/include/cuda/experimental/__async/sender/write_env.cuh
+++ b/cudax/include/cuda/experimental/__async/sender/write_env.cuh
@@ -41,7 +41,7 @@ private:
 #endif // !_CCCL_CUDA_COMPILER(NVCC)
 
   template <class _Rcvr, class _Sndr, class _Env>
-  struct __opstate_t
+  struct _CCCL_TYPE_VISIBILITY_DEFAULT __opstate_t
   {
     using operation_state_concept = operation_state_t;
     using completion_signatures   = completion_signatures_of_t<_Sndr, __rcvr_with_env_t<_Rcvr, _Env>*>;
@@ -63,7 +63,7 @@ private:
   };
 
   template <class _Sndr, class _Env>
-  struct __sndr_t;
+  struct _CCCL_TYPE_VISIBILITY_DEFAULT __sndr_t;
 
 public:
   /// @brief Wraps one sender in another that modifies the execution
@@ -74,7 +74,7 @@ public:
 };
 
 template <class _Sndr, class _Env>
-struct write_env_t::__sndr_t
+struct _CCCL_TYPE_VISIBILITY_DEFAULT write_env_t::__sndr_t
 {
   using sender_concept = sender_t;
   _CCCL_NO_UNIQUE_ADDRESS write_env_t __tag_;

From 74c17c662568c33bdd39532aa423c057c2f6d305 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?C=C3=A9dric=20Augonnet?=
 <158148890+caugonnet@users.noreply.github.com>
Date: Wed, 29 Jan 2025 17:57:00 +0100
Subject: [PATCH 03/33] [STF] Document dot sections (#3506)

* Start to document STF dot sections

* fix formatting

* Minor fixes in the doc

* Add missing file

* clang-format

* Remove dot_push_section and dot_pop_section and also fix a bazillion warnings

* Format

* More Format

* Add missing mv

* misc. C++ fixes and clang-format

* Update dot_section doc to reflect that we removed dot_push_section and dot_pop_section

* - Fix documentation error
- Use the dot_section doc example as a test
- do not use assert directly

* Review and a few more touches

* Improvement for docs/cudax/stf.rst

Co-authored-by: Bernhard Manfred Gruber <bernhardmgruber@gmail.com>

---------

Co-authored-by: Andrei Alexandrescu <andrei@erdani.com>
Co-authored-by: Bernhard Manfred Gruber <bernhardmgruber@gmail.com>
---
 .../stf/linear_algebra/07-cholesky.cu         |   8 +-
 cudax/examples/stf/linear_algebra/07-potri.cu |   8 +-
 cudax/examples/stf/linear_algebra/cg_csr.cu   |   9 ++-
 .../__stf/internal/backend_ctx.cuh            |  10 ---
 .../cuda/experimental/__stf/internal/dot.cuh  |  33 ++++++--
 cudax/include/cuda/experimental/stf.cuh       |  28 +------
 cudax/test/stf/CMakeLists.txt                 |   1 +
 .../jacobiCudaGraphs/jacobi.cu                |   2 +-
 cudax/test/stf/dot/sections_2.cu              |  49 ++++++++++++
 cudax/test/stf/examples/07-cholesky-redux.cu  |  46 ++++++------
 .../test/stf/examples/07-cholesky-unified.cu  |  48 ++++++------
 cudax/test/stf/gnu/06-pdgemm.cpp              |  20 ++---
 cudax/test/stf/gnu/07-cholesky.cpp            |  48 ++++++------
 docs/cudax/stf.rst                            |  71 ++++++++++++++++++
 docs/cudax/stf/images/dag-sections-0.dot      |   5 ++
 docs/cudax/stf/images/dag-sections-0.png      | Bin 0 -> 7100 bytes
 docs/cudax/stf/images/dag-sections-1.dot      |  14 ++++
 docs/cudax/stf/images/dag-sections-1.png      | Bin 0 -> 12081 bytes
 docs/cudax/stf/images/dag-sections-2.dot      |  36 +++++++++
 docs/cudax/stf/images/dag-sections-2.png      | Bin 0 -> 42824 bytes
 docs/cudax/stf/images/dag-sections.dot        |  69 +++++++++++++++++
 docs/cudax/stf/images/dag-sections.png        | Bin 0 -> 103821 bytes
 22 files changed, 369 insertions(+), 136 deletions(-)
 create mode 100644 cudax/test/stf/dot/sections_2.cu
 create mode 100644 docs/cudax/stf/images/dag-sections-0.dot
 create mode 100644 docs/cudax/stf/images/dag-sections-0.png
 create mode 100644 docs/cudax/stf/images/dag-sections-1.dot
 create mode 100644 docs/cudax/stf/images/dag-sections-1.png
 create mode 100644 docs/cudax/stf/images/dag-sections-2.dot
 create mode 100644 docs/cudax/stf/images/dag-sections-2.png
 create mode 100644 docs/cudax/stf/images/dag-sections.dot
 create mode 100644 docs/cudax/stf/images/dag-sections.png

diff --git a/cudax/examples/stf/linear_algebra/07-cholesky.cu b/cudax/examples/stf/linear_algebra/07-cholesky.cu
index 5c7947fc5ac..41b6f053bb3 100644
--- a/cudax/examples/stf/linear_algebra/07-cholesky.cu
+++ b/cudax/examples/stf/linear_algebra/07-cholesky.cu
@@ -659,14 +659,14 @@ int main(int argc, char** argv)
     return 1.0 / (col + row + 1.0) + 2.0 * N * (col == row);
   };
 
-  ctx.dot_push_section("fillA");
+  auto s = ctx.dot_section("fillA");
   if (check_result)
   {
     Aref.fill(hilbert);
   }
 
   A.fill(hilbert);
-  ctx.dot_pop_section();
+  s.end();
 
   /* Right-hand side */
   matrix<double> B_potrs(N, 1, NB, 1, false, "B");
@@ -693,9 +693,9 @@ int main(int argc, char** argv)
   cudaEvent_t startEvent_pdpotrf, stopEvent_pdpotrf;
   float milliseconds_pdpotrf = 0;
 
-  //    for (int row = 0; row < A.mt; row++)
+  //    for (size_t row = 0; row < A.mt; row++)
   //    {
-  //        for (int col = 0; col <= row; col++)
+  //        for (size_t col = 0; col <= row; col++)
   //        {
   //            cuda_safe_call(cudaSetDevice(A.get_preferred_devid(row, col)));
   //            NOOP(A, row, col);
diff --git a/cudax/examples/stf/linear_algebra/07-potri.cu b/cudax/examples/stf/linear_algebra/07-potri.cu
index e80fbffa663..37b9d93f78a 100644
--- a/cudax/examples/stf/linear_algebra/07-potri.cu
+++ b/cudax/examples/stf/linear_algebra/07-potri.cu
@@ -197,17 +197,17 @@ public:
   void print()
   {
     // print blocks by blocks
-    for (int colb = 0; colb < nt; colb++)
+    for (size_t colb = 0; colb < nt; colb++)
     {
       int low_rowb = sym_matrix ? colb : 0;
-      for (int rowb = low_rowb; rowb < mt; rowb++)
+      for (size_t rowb = low_rowb; rowb < mt; rowb++)
       {
         // Each task fills a block
         ctx.host_launch(get_handle(rowb, colb).read())->*[=](auto sA) {
-          for (int lcol = 0; lcol < sA.extent(1); lcol++)
+          for (size_t lcol = 0; lcol < sA.extent(1); lcol++)
           {
             size_t col = lcol + colb * sA.extent(1);
-            for (int lrow = 0; lrow < sA.extent(0); lrow++)
+            for (size_t lrow = 0; lrow < sA.extent(0); lrow++)
             {
               size_t row = lrow + rowb * sA.extent(0);
 
diff --git a/cudax/examples/stf/linear_algebra/cg_csr.cu b/cudax/examples/stf/linear_algebra/cg_csr.cu
index ec0d3f1c9ff..bfa537d1995 100644
--- a/cudax/examples/stf/linear_algebra/cg_csr.cu
+++ b/cudax/examples/stf/linear_algebra/cg_csr.cu
@@ -51,7 +51,7 @@ public:
   static void copy_vector(const vector& from, vector& to)
   {
     to.ctx.parallel_for(to.handle.shape(), to.handle.write(), from.handle.read()).set_symbol("copy_vector")
-        ->*[] _CCCL_DEVICE(size_t i, slice<double> dto, slice<double> dfrom) {
+        ->*[] _CCCL_DEVICE(size_t i, slice<double> dto, slice<const double> dfrom) {
               dto(i) = dfrom(i);
             };
   }
@@ -116,6 +116,13 @@ public:
     copy_scalar(a, *this);
   }
 
+  scalar& operator=(scalar&& a)
+  {
+    handle = mv(a.handle);
+    ctx    = mv(a.ctx);
+    return *this;
+  }
+
   scalar operator/(scalar const& rhs) const
   {
     // Submit a task that computes this/rhs
diff --git a/cudax/include/cuda/experimental/__stf/internal/backend_ctx.cuh b/cudax/include/cuda/experimental/__stf/internal/backend_ctx.cuh
index 4700ced4174..2ef462f103a 100644
--- a/cudax/include/cuda/experimental/__stf/internal/backend_ctx.cuh
+++ b/cudax/include/cuda/experimental/__stf/internal/backend_ctx.cuh
@@ -955,16 +955,6 @@ public:
     reserved::per_ctx_dot::set_parent_ctx(parent_ctx.get_dot(), get_dot());
   }
 
-  void dot_push_section(::std::string symbol) const
-  {
-    reserved::dot::section::push(mv(symbol));
-  }
-
-  void dot_pop_section() const
-  {
-    reserved::dot::section::pop();
-  }
-
   auto dot_section(::std::string symbol) const
   {
     return reserved::dot::section::guard(mv(symbol));
diff --git a/cudax/include/cuda/experimental/__stf/internal/dot.cuh b/cudax/include/cuda/experimental/__stf/internal/dot.cuh
index d711f32a6c4..cda74a1a899 100644
--- a/cudax/include/cuda/experimental/__stf/internal/dot.cuh
+++ b/cudax/include/cuda/experimental/__stf/internal/dot.cuh
@@ -163,7 +163,7 @@ public:
   static int get_current_section_id();
 
   template <typename task_type, typename data_type>
-  void add_vertex(task_type t)
+  void add_vertex(const task_type& t)
   {
     // Do this work outside the critical section
     const auto remove_deps = getenv("CUDASTF_DOT_REMOVE_DATA_DEPS");
@@ -208,7 +208,7 @@ public:
   }
 
   template <typename task_type>
-  void add_vertex_timing(task_type t, float time_ms, int device = -1)
+  void add_vertex_timing(const task_type& t, float time_ms, int device = -1)
   {
     ::std::lock_guard<::std::mutex> guard(mtx);
 
@@ -286,7 +286,7 @@ public:
   ::std::shared_ptr<per_ctx_dot> parent;
   ::std::vector<::std::shared_ptr<per_ctx_dot>> children;
 
-  const ::std::string get_ctx_symbol() const
+  const ::std::string& get_ctx_symbol() const
   {
     return ctx_symbol;
   }
@@ -352,7 +352,10 @@ public:
     // Constructor to initialize symbol and children
     section(::std::string sym)
         : symbol(mv(sym))
-    {}
+    {
+      static_assert(::std::is_move_constructible_v<section>, "section must be move constructible");
+      static_assert(::std::is_move_assignable_v<section>, "section must be move assignable");
+    }
 
     class guard
     {
@@ -362,10 +365,24 @@ public:
         section::push(mv(symbol));
       }
 
-      ~guard()
+      void end()
       {
+        _CCCL_ASSERT(active, "Attempting to end the same section twice.");
         section::pop();
+        active = false;
+      }
+
+      ~guard()
+      {
+        if (active)
+        {
+          section::pop();
+        }
       }
+
+    private:
+      // Have we called end() ?
+      bool active = true;
     };
 
     static auto& current()
@@ -380,7 +397,7 @@ public:
       auto sec = ::std::make_shared<section>(mv(symbol));
       int id   = sec->get_id();
 
-      int parent_id  = current().size() == 0 ? 0 : current().top();
+      int parent_id  = current().empty() ? 0 : current().top();
       sec->parent_id = parent_id;
 
       // Save the section in the map
@@ -416,7 +433,7 @@ public:
       return 1 + int(id);
     }
 
-    const ::std::string get_symbol() const
+    const ::std::string& get_symbol() const
     {
       return symbol;
     }
@@ -431,7 +448,7 @@ public:
     ::std::vector<int> children_ids;
 
   private:
-    int depth;
+    int depth = ::std::numeric_limits<int>::min();
 
     ::std::string symbol;
 
diff --git a/cudax/include/cuda/experimental/stf.cuh b/cudax/include/cuda/experimental/stf.cuh
index 267a0dbd4b1..276c5725c5f 100644
--- a/cudax/include/cuda/experimental/stf.cuh
+++ b/cudax/include/cuda/experimental/stf.cuh
@@ -635,32 +635,6 @@ public:
       payload);
   }
 
-  /**
-   * @brief Start a new section in the DOT file identified by its symbol
-   */
-  void dot_push_section(::std::string symbol) const
-  {
-    _CCCL_ASSERT(payload.index() != ::std::variant_npos, "Context is not initialized");
-    ::std::visit(
-      [symbol = mv(symbol)](auto& self) {
-        self.dot_push_section(symbol);
-      },
-      payload);
-  }
-
-  /**
-   * @brief Ends current dot section
-   */
-  void dot_pop_section() const
-  {
-    _CCCL_ASSERT(payload.index() != ::std::variant_npos, "Context is not initialized");
-    ::std::visit(
-      [](auto& self) {
-        self.dot_pop_section();
-      },
-      payload);
-  }
-
   /**
    * @brief RAII-style description of a new section in the DOT file identified by its symbol
    */
@@ -668,7 +642,7 @@ public:
   {
     _CCCL_ASSERT(payload.index() != ::std::variant_npos, "Context is not initialized");
     return ::std::visit(
-      [symbol = mv(symbol)](auto& self) {
+      [&symbol](auto& self) {
         return self.dot_section(symbol);
       },
       payload);
diff --git a/cudax/test/stf/CMakeLists.txt b/cudax/test/stf/CMakeLists.txt
index 20527586cfe..d53b2e22140 100644
--- a/cudax/test/stf/CMakeLists.txt
+++ b/cudax/test/stf/CMakeLists.txt
@@ -8,6 +8,7 @@ set(stf_test_sources
   dot/basic.cu
   dot/graph_print_to_dot.cu
   dot/sections.cu
+  dot/sections_2.cu
   dot/with_events.cu
   error_checks/ctx_mismatch.cu
   error_checks/data_interface_mismatch.cu
diff --git a/cudax/test/stf/cuda-samples/3_CUDA_Features/jacobiCudaGraphs/jacobi.cu b/cudax/test/stf/cuda-samples/3_CUDA_Features/jacobiCudaGraphs/jacobi.cu
index 4b8e8be4600..1e0e7235080 100644
--- a/cudax/test/stf/cuda-samples/3_CUDA_Features/jacobiCudaGraphs/jacobi.cu
+++ b/cudax/test/stf/cuda-samples/3_CUDA_Features/jacobiCudaGraphs/jacobi.cu
@@ -228,7 +228,7 @@ static __global__ void finalError(double* x, double* g_sum)
 double JacobiMethodGpuCudaGraphExecKernelSetParams(
   const float* A,
   const double* b,
-  const float conv_threshold,
+  float conv_threshold,
   const int max_iter,
   double* x,
   double* x_new,
diff --git a/cudax/test/stf/dot/sections_2.cu b/cudax/test/stf/dot/sections_2.cu
new file mode 100644
index 00000000000..d4cc74cf621
--- /dev/null
+++ b/cudax/test/stf/dot/sections_2.cu
@@ -0,0 +1,49 @@
+//===----------------------------------------------------------------------===//
+//
+// Part of CUDASTF in CUDA C++ Core Libraries,
+// under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+// SPDX-FileCopyrightText: Copyright (c) 2022-2024 NVIDIA CORPORATION & AFFILIATES.
+//
+//===----------------------------------------------------------------------===//
+
+/**
+ * @file
+ * @brief This test makes sure we can generate a dot file with sections
+ */
+
+#include <cuda/experimental/stf.cuh>
+
+using namespace cuda::experimental::stf;
+
+int main()
+{
+// TODO (miscco): Make it work for windows
+#if !_CCCL_COMPILER(MSVC)
+  context ctx;
+  auto lA = ctx.logical_token().set_symbol("A");
+  auto lB = ctx.logical_token().set_symbol("B");
+  auto lC = ctx.logical_token().set_symbol("C");
+
+  // Begin a top-level section named "foo"
+  auto s_foo = ctx.dot_section("foo");
+  for (size_t i = 0; i < 2; i++)
+  {
+    // Section named "bar" using RAII
+    auto s_bar = ctx.dot_section("bar");
+    ctx.task(lA.read(), lB.rw()).set_symbol("t1")->*[](cudaStream_t, auto, auto) {};
+    for (size_t j = 0; j < 2; j++)
+    {
+      // Section named "baz" using RAII
+      auto s_bar = ctx.dot_section("baz");
+      ctx.task(lA.read(), lC.rw()).set_symbol("t2")->*[](cudaStream_t, auto, auto) {};
+      ctx.task(lB.read(), lC.read(), lA.rw()).set_symbol("t3")->*[](cudaStream_t, auto, auto, auto) {};
+      // Implicit end of section "baz"
+    }
+    // Implicit end of section "bar"
+  }
+  s_foo.end(); // Explicit end of section "foo"
+  ctx.finalize();
+#endif // !_CCCL_COMPILER(MSVC)
+}
diff --git a/cudax/test/stf/examples/07-cholesky-redux.cu b/cudax/test/stf/examples/07-cholesky-redux.cu
index 44421ce7458..26a4f9ac569 100644
--- a/cudax/test/stf/examples/07-cholesky-redux.cu
+++ b/cudax/test/stf/examples/07-cholesky-redux.cu
@@ -91,10 +91,10 @@ public:
 
     handles.resize(mt * nt);
 
-    for (int colb = 0; colb < nt; colb++)
+    for (size_t colb = 0; colb < nt; colb++)
     {
       int low_rowb = sym_matrix ? colb : 0;
-      for (int rowb = low_rowb; rowb < mt; rowb++)
+      for (size_t rowb = low_rowb; rowb < mt; rowb++)
       {
         T* addr_h = get_block_h(rowb, colb);
         auto& h   = handle(rowb, colb);
@@ -171,10 +171,10 @@ public:
   {
     nvtxRangePushA("FILL");
     // Fill blocks by blocks
-    for (int colb = 0; colb < nt; colb++)
+    for (size_t colb = 0; colb < nt; colb++)
     {
       int low_rowb = sym_matrix ? colb : 0;
-      for (int rowb = low_rowb; rowb < mt; rowb++)
+      for (size_t rowb = low_rowb; rowb < mt; rowb++)
       {
         // Each task fills a block
         auto& h   = handle(rowb, colb);
@@ -367,9 +367,9 @@ void PDNRM2_HOST(matrix<double>* A, double* result)
   reserved::dot::set_current_color("red");
 #endif
 
-  for (int rowb = 0; rowb < A->mt; rowb++)
+  for (size_t rowb = 0; rowb < A->mt; rowb++)
   {
-    for (int colb = 0; colb < A->nt; colb++)
+    for (size_t colb = 0; colb < A->nt; colb++)
     {
       ctx.host_launch(A->handle(rowb, colb).read())->*[=](auto sA) {
         double res2 = 0.0;
@@ -454,17 +454,17 @@ void PDTRSM(cublasSideMode_t side,
       //===========================================
       if (trans == CUBLAS_OP_N)
       {
-        for (int k = 0; k < B.mt; k++)
+        for (size_t k = 0; k < B.mt; k++)
         {
           double lalpha = k == 0 ? alpha : 1.0;
-          for (int n = 0; n < B.nt; n++)
+          for (size_t n = 0; n < B.nt; n++)
           {
             cuda_safe_call(cudaSetDevice(A.get_preferred_devid(k, k)));
             DTRSM(side, uplo, trans, diag, lalpha, A, k, k, B, k, n);
           }
-          for (int m = k + 1; m < B.mt; m++)
+          for (size_t m = k + 1; m < B.mt; m++)
           {
-            for (int n = 0; n < B.nt; n++)
+            for (size_t n = 0; n < B.nt; n++)
             {
               cuda_safe_call(cudaSetDevice(A.get_preferred_devid(m, k)));
               DGEMM(CUBLAS_OP_N, CUBLAS_OP_N, -1.0, A, m, k, B, k, n, lalpha, B, m, n);
@@ -477,17 +477,17 @@ void PDTRSM(cublasSideMode_t side,
       //================================================
       else
       {
-        for (int k = 0; k < B.mt; k++)
+        for (size_t k = 0; k < B.mt; k++)
         {
           double lalpha = k == 0 ? alpha : 1.0;
-          for (int n = 0; n < B.nt; n++)
+          for (size_t n = 0; n < B.nt; n++)
           {
             cuda_safe_call(cudaSetDevice(A.get_preferred_devid(B.mt - k - 1, B.mt - k - 1)));
             DTRSM(side, uplo, trans, diag, lalpha, A, B.mt - k - 1, B.mt - k - 1, B, B.mt - k - 1, n);
           }
-          for (int m = k + 1; m < B.mt; m++)
+          for (size_t m = k + 1; m < B.mt; m++)
           {
-            for (int n = 0; n < B.nt; n++)
+            for (size_t n = 0; n < B.nt; n++)
             {
               cuda_safe_call(cudaSetDevice(A.get_preferred_devid(B.mt - k - 1, B.mt - 1 - m)));
               DGEMM(
@@ -544,9 +544,9 @@ void PDGEMM(cublasOperation_t transa,
   reserved::dot::set_current_color("blue");
 #endif
 
-  for (int m = 0; m < C.mt; m++)
+  for (size_t m = 0; m < C.mt; m++)
   {
-    for (int n = 0; n < C.nt; n++)
+    for (size_t n = 0; n < C.nt; n++)
     {
       //=========================================
       // alpha*A*B does not contribute; scale C
@@ -563,7 +563,7 @@ void PDGEMM(cublasOperation_t transa,
         //================================
         if (transb == CUBLAS_OP_N)
         {
-          for (int k = 0; k < A.nt; k++)
+          for (size_t k = 0; k < A.nt; k++)
           {
             double zbeta = k == 0 ? beta : 1.0;
             DGEMM(transa, transb, alpha, A, m, k, B, k, n, zbeta, C, m, n);
@@ -574,7 +574,7 @@ void PDGEMM(cublasOperation_t transa,
         //=====================================
         else
         {
-          for (int k = 0; k < A.nt; k++)
+          for (size_t k = 0; k < A.nt; k++)
           {
             double zbeta = k == 0 ? beta : 1.0;
             DGEMM(transa, transb, alpha, A, m, k, B, n, k, zbeta, C, m, n);
@@ -588,7 +588,7 @@ void PDGEMM(cublasOperation_t transa,
         //=====================================
         if (transb == CUBLAS_OP_N)
         {
-          for (int k = 0; k < A.mt; k++)
+          for (size_t k = 0; k < A.mt; k++)
           {
             double zbeta = k == 0 ? beta : 1.0;
             DGEMM(transa, transb, alpha, A, k, m, B, k, n, zbeta, C, m, n);
@@ -599,7 +599,7 @@ void PDGEMM(cublasOperation_t transa,
         //==========================================
         else
         {
-          for (int k = 0; k < A.mt; k++)
+          for (size_t k = 0; k < A.mt; k++)
           {
             double zbeta = k == 0 ? beta : 1.0;
             DGEMM(transa, transb, alpha, A, k, m, B, n, k, zbeta, C, m, n);
@@ -641,7 +641,7 @@ int main(int argc, char** argv)
   int ndevs;
   cuda_safe_call(cudaGetDeviceCount(&ndevs));
 
-  for (size_t d = 0; d < ndevs; d++)
+  for (int d = 0; d < ndevs; d++)
   {
     auto lX = ctx.logical_data(shape_of<slice<double>>(1));
     ctx.parallel_for(exec_place::device(d), lX.shape(), lX.write())->*[] __device__(size_t, auto) {};
@@ -690,9 +690,9 @@ int main(int argc, char** argv)
   cudaEvent_t startEvent_pdpotrf, stopEvent_pdpotrf;
   float milliseconds_pdpotrf = 0;
 
-  //    for (int row = 0; row < A.mt; row++)
+  //    for (size_t row = 0; row < A.mt; row++)
   //    {
-  //        for (int col = 0; col <= row; col++)
+  //        for (size_t col = 0; col <= row; col++)
   //        {
   //            cuda_safe_call(cudaSetDevice(A.get_preferred_devid(row, col)));
   //            NOOP(A, row, col);
diff --git a/cudax/test/stf/examples/07-cholesky-unified.cu b/cudax/test/stf/examples/07-cholesky-unified.cu
index 480029e97c8..60b740b4f17 100644
--- a/cudax/test/stf/examples/07-cholesky-unified.cu
+++ b/cudax/test/stf/examples/07-cholesky-unified.cu
@@ -84,10 +84,10 @@ public:
 
     handles.resize(mt * nt);
 
-    for (int colb = 0; colb < nt; colb++)
+    for (size_t colb = 0; colb < nt; colb++)
     {
       int low_rowb = sym_matrix ? colb : 0;
-      for (int rowb = low_rowb; rowb < mt; rowb++)
+      for (size_t rowb = low_rowb; rowb < mt; rowb++)
       {
         T* addr_h = get_block_h(rowb, colb);
         auto& h   = handle(rowb, colb);
@@ -162,17 +162,17 @@ public:
   void fill(Fun&& fun)
   {
     // Fill blocks by blocks
-    for (int colb = 0; colb < nt; colb++)
+    for (size_t colb = 0; colb < nt; colb++)
     {
       int low_rowb = sym_matrix ? colb : 0;
-      for (int rowb = low_rowb; rowb < mt; rowb++)
+      for (size_t rowb = low_rowb; rowb < mt; rowb++)
       {
         // Each task fills a block
         ctx.host_launch(handle(rowb, colb).write())->*[=, self = this](auto sA) {
-          for (int lcol = 0; lcol < sA.extent(1); lcol++)
+          for (size_t lcol = 0; lcol < sA.extent(1); lcol++)
           {
             size_t col = lcol + colb * sA.extent(1);
-            for (int lrow = 0; lrow < sA.extent(0); lrow++)
+            for (size_t lrow = 0; lrow < sA.extent(0); lrow++)
             {
               size_t row     = lrow + rowb * sA.extent(0);
               sA(lrow, lcol) = fun(*self, row, col);
@@ -348,9 +348,9 @@ void PDNRM2_HOST(matrix<double>* A, double* result)
   reserved::dot::set_current_color("red");
 #endif
 
-  for (int rowb = 0; rowb < A->mt; rowb++)
+  for (size_t rowb = 0; rowb < A->mt; rowb++)
   {
-    for (int colb = 0; colb < A->nt; colb++)
+    for (size_t colb = 0; colb < A->nt; colb++)
     {
       ctx.host_launch(A->handle(rowb, colb).read())->*[=](auto sA) {
         double res2 = 0.0;
@@ -435,17 +435,17 @@ void PDTRSM(cublasSideMode_t side,
       //===========================================
       if (trans == CUBLAS_OP_N)
       {
-        for (int k = 0; k < B.mt; k++)
+        for (size_t k = 0; k < B.mt; k++)
         {
           double lalpha = k == 0 ? alpha : 1.0;
-          for (int n = 0; n < B.nt; n++)
+          for (size_t n = 0; n < B.nt; n++)
           {
             cuda_safe_call(cudaSetDevice(A.get_preferred_devid(k, k)));
             DTRSM(side, uplo, trans, diag, lalpha, A, k, k, B, k, n);
           }
-          for (int m = k + 1; m < B.mt; m++)
+          for (size_t m = k + 1; m < B.mt; m++)
           {
-            for (int n = 0; n < B.nt; n++)
+            for (size_t n = 0; n < B.nt; n++)
             {
               cuda_safe_call(cudaSetDevice(A.get_preferred_devid(m, k)));
               DGEMM(CUBLAS_OP_N, CUBLAS_OP_N, -1.0, A, m, k, B, k, n, lalpha, B, m, n);
@@ -458,17 +458,17 @@ void PDTRSM(cublasSideMode_t side,
       //================================================
       else
       {
-        for (int k = 0; k < B.mt; k++)
+        for (size_t k = 0; k < B.mt; k++)
         {
           double lalpha = k == 0 ? alpha : 1.0;
-          for (int n = 0; n < B.nt; n++)
+          for (size_t n = 0; n < B.nt; n++)
           {
             cuda_safe_call(cudaSetDevice(A.get_preferred_devid(B.mt - k - 1, B.mt - k - 1)));
             DTRSM(side, uplo, trans, diag, lalpha, A, B.mt - k - 1, B.mt - k - 1, B, B.mt - k - 1, n);
           }
-          for (int m = k + 1; m < B.mt; m++)
+          for (size_t m = k + 1; m < B.mt; m++)
           {
-            for (int n = 0; n < B.nt; n++)
+            for (size_t n = 0; n < B.nt; n++)
             {
               cuda_safe_call(cudaSetDevice(A.get_preferred_devid(B.mt - k - 1, B.mt - 1 - m)));
               DGEMM(
@@ -525,9 +525,9 @@ void PDGEMM(cublasOperation_t transa,
   reserved::dot::set_current_color("blue");
 #endif
 
-  for (int m = 0; m < C.mt; m++)
+  for (size_t m = 0; m < C.mt; m++)
   {
-    for (int n = 0; n < C.nt; n++)
+    for (size_t n = 0; n < C.nt; n++)
     {
       //=========================================
       // alpha*A*B does not contribute; scale C
@@ -544,7 +544,7 @@ void PDGEMM(cublasOperation_t transa,
         //================================
         if (transb == CUBLAS_OP_N)
         {
-          for (int k = 0; k < A.nt; k++)
+          for (size_t k = 0; k < A.nt; k++)
           {
             double zbeta = k == 0 ? beta : 1.0;
             DGEMM(transa, transb, alpha, A, m, k, B, k, n, zbeta, C, m, n);
@@ -555,7 +555,7 @@ void PDGEMM(cublasOperation_t transa,
         //=====================================
         else
         {
-          for (int k = 0; k < A.nt; k++)
+          for (size_t k = 0; k < A.nt; k++)
           {
             double zbeta = k == 0 ? beta : 1.0;
             DGEMM(transa, transb, alpha, A, m, k, B, n, k, zbeta, C, m, n);
@@ -569,7 +569,7 @@ void PDGEMM(cublasOperation_t transa,
         //=====================================
         if (transb == CUBLAS_OP_N)
         {
-          for (int k = 0; k < A.mt; k++)
+          for (size_t k = 0; k < A.mt; k++)
           {
             double zbeta = k == 0 ? beta : 1.0;
             DGEMM(transa, transb, alpha, A, k, m, B, k, n, zbeta, C, m, n);
@@ -580,7 +580,7 @@ void PDGEMM(cublasOperation_t transa,
         //==========================================
         else
         {
-          for (int k = 0; k < A.mt; k++)
+          for (size_t k = 0; k < A.mt; k++)
           {
             double zbeta = k == 0 ? beta : 1.0;
             DGEMM(transa, transb, alpha, A, k, m, B, n, k, zbeta, C, m, n);
@@ -650,9 +650,9 @@ int main(int argc, char** argv)
     PDNRM2_HOST(&Bref_potrs, &Bref_nrm2);
   }
 
-  //    for (int row = 0; row < A.mt; row++)
+  //    for (size_t row = 0; row < A.mt; row++)
   //    {
-  //        for (int col = 0; col <= row; col++)
+  //        for (size_t col = 0; col <= row; col++)
   //        {
   //            cuda_safe_call(cudaSetDevice(A.get_preferred_devid(row, col)));
   //            NOOP(A, row, col);
diff --git a/cudax/test/stf/gnu/06-pdgemm.cpp b/cudax/test/stf/gnu/06-pdgemm.cpp
index 9e400b66e2e..6bb12f7633b 100644
--- a/cudax/test/stf/gnu/06-pdgemm.cpp
+++ b/cudax/test/stf/gnu/06-pdgemm.cpp
@@ -155,9 +155,9 @@ class matrix
   void fill(T (*func)(matrix<T>*, int, int))
   {
     // Fill blocks by blocks
-    for (int colb = 0; colb < nt; colb++)
+    for (size_t colb = 0; colb < nt; colb++)
     {
-      for (int rowb = 0; rowb < mt; rowb++)
+      for (size_t rowb = 0; rowb < mt; rowb++)
       {
         T* addr_h = get_block_h(rowb, colb);
 #ifdef TILED
@@ -167,9 +167,9 @@ class matrix
         int ld = m;
 #endif
 
-        for (int lrow = 0; lrow < mb; lrow++)
+        for (size_t lrow = 0; lrow < mb; lrow++)
         {
-          for (int lcol = 0; lcol < nb; lcol++)
+          for (size_t lcol = 0; lcol < nb; lcol++)
           {
             size_t row = lrow + rowb * mb;
             size_t col = lcol + colb * nb;
@@ -257,9 +257,9 @@ void PDGEMM(Ctx& ctx,
             double beta,
             matrix<double>& C)
 {
-  for (int m = 0; m < C.mt; m++)
+  for (size_t m = 0; m < C.mt; m++)
   {
-    for (int n = 0; n < C.nt; n++)
+    for (size_t n = 0; n < C.nt; n++)
     {
       //=========================================
       // alpha*A*B does not contribute; scale C
@@ -277,7 +277,7 @@ void PDGEMM(Ctx& ctx,
         if (transb == CUBLAS_OP_N)
         {
           assert(A.nt == B.mt);
-          for (int k = 0; k < A.nt; k++)
+          for (size_t k = 0; k < A.nt; k++)
           {
             double zbeta = k == 0 ? beta : 1.0;
             DGEMM(ctx, transa, transb, alpha, A, m, k, B, k, n, zbeta, C, m, n);
@@ -288,7 +288,7 @@ void PDGEMM(Ctx& ctx,
         //=====================================
         else
         {
-          for (int k = 0; k < A.nt; k++)
+          for (size_t k = 0; k < A.nt; k++)
           {
             double zbeta = k == 0 ? beta : 1.0;
             DGEMM(ctx, transa, transb, alpha, A, m, k, B, n, k, zbeta, C, m, n);
@@ -302,7 +302,7 @@ void PDGEMM(Ctx& ctx,
         //=====================================
         if (transb == CUBLAS_OP_N)
         {
-          for (int k = 0; k < A.mt; k++)
+          for (size_t k = 0; k < A.mt; k++)
           {
             double zbeta = k == 0 ? beta : 1.0;
             DGEMM(ctx, transa, transb, alpha, A, k, m, B, k, n, zbeta, C, m, n);
@@ -313,7 +313,7 @@ void PDGEMM(Ctx& ctx,
         //==========================================
         else
         {
-          for (int k = 0; k < A.mt; k++)
+          for (size_t k = 0; k < A.mt; k++)
           {
             double zbeta = k == 0 ? beta : 1.0;
             DGEMM(ctx, transa, transb, alpha, A, k, m, B, n, k, zbeta, C, m, n);
diff --git a/cudax/test/stf/gnu/07-cholesky.cpp b/cudax/test/stf/gnu/07-cholesky.cpp
index 1e40da9a3c5..178adcc06c8 100644
--- a/cudax/test/stf/gnu/07-cholesky.cpp
+++ b/cudax/test/stf/gnu/07-cholesky.cpp
@@ -90,10 +90,10 @@ class matrix
 
     handles.resize(mt * nt);
 
-    for (int colb = 0; colb < nt; colb++)
+    for (size_t colb = 0; colb < nt; colb++)
     {
       int low_rowb = sym_matrix ? colb : 0;
-      for (int rowb = low_rowb; rowb < mt; rowb++)
+      for (size_t rowb = low_rowb; rowb < mt; rowb++)
       {
         T* addr_h = get_block_h(rowb, colb);
         auto& h   = handle(rowb, colb);
@@ -168,17 +168,17 @@ class matrix
   void fill(Fun&& fun)
   {
     // Fill blocks by blocks
-    for (int colb = 0; colb < nt; colb++)
+    for (size_t colb = 0; colb < nt; colb++)
     {
       int low_rowb = sym_matrix ? colb : 0;
-      for (int rowb = low_rowb; rowb < mt; rowb++)
+      for (size_t rowb = low_rowb; rowb < mt; rowb++)
       {
         // Each task fills a block
         ctx.host_launch(handle(rowb, colb).write())->*[this, fun, rowb, colb](auto sA) {
-          for (int lcol = 0; lcol < sA.extent(1); lcol++)
+          for (size_t lcol = 0; lcol < sA.extent(1); lcol++)
           {
             size_t col = lcol + colb * sA.extent(1);
-            for (int lrow = 0; lrow < sA.extent(0); lrow++)
+            for (size_t lrow = 0; lrow < sA.extent(0); lrow++)
             {
               size_t row     = lrow + rowb * sA.extent(0);
               sA(lrow, lcol) = fun(*this, row, col);
@@ -351,9 +351,9 @@ void PDNRM2_HOST(matrix<double>* A, double* result)
   reserved::dot::set_current_color("red");
 #endif
 
-  for (int rowb = 0; rowb < A->mt; rowb++)
+  for (size_t rowb = 0; rowb < A->mt; rowb++)
   {
-    for (int colb = 0; colb < A->nt; colb++)
+    for (size_t colb = 0; colb < A->nt; colb++)
     {
       ctx.host_launch(A->handle(rowb, colb).read())->*[=](auto sA) {
         double res2 = 0.0;
@@ -437,17 +437,17 @@ void PDTRSM(cublasSideMode_t side,
       //===========================================
       if (trans == CUBLAS_OP_N)
       {
-        for (int k = 0; k < B.mt; k++)
+        for (size_t k = 0; k < B.mt; k++)
         {
           double lalpha = k == 0 ? alpha : 1.0;
-          for (int n = 0; n < B.nt; n++)
+          for (size_t n = 0; n < B.nt; n++)
           {
             cuda_safe_call(cudaSetDevice(A.get_preferred_devid(k, k)));
             DTRSM(side, uplo, trans, diag, lalpha, A, k, k, B, k, n);
           }
-          for (int m = k + 1; m < B.mt; m++)
+          for (size_t m = k + 1; m < B.mt; m++)
           {
-            for (int n = 0; n < B.nt; n++)
+            for (size_t n = 0; n < B.nt; n++)
             {
               cuda_safe_call(cudaSetDevice(A.get_preferred_devid(m, k)));
               DGEMM(CUBLAS_OP_N, CUBLAS_OP_N, -1.0, A, m, k, B, k, n, lalpha, B, m, n);
@@ -460,17 +460,17 @@ void PDTRSM(cublasSideMode_t side,
       //================================================
       else
       {
-        for (int k = 0; k < B.mt; k++)
+        for (size_t k = 0; k < B.mt; k++)
         {
           double lalpha = k == 0 ? alpha : 1.0;
-          for (int n = 0; n < B.nt; n++)
+          for (size_t n = 0; n < B.nt; n++)
           {
             cuda_safe_call(cudaSetDevice(A.get_preferred_devid(B.mt - k - 1, B.mt - k - 1)));
             DTRSM(side, uplo, trans, diag, lalpha, A, B.mt - k - 1, B.mt - k - 1, B, B.mt - k - 1, n);
           }
-          for (int m = k + 1; m < B.mt; m++)
+          for (size_t m = k + 1; m < B.mt; m++)
           {
-            for (int n = 0; n < B.nt; n++)
+            for (size_t n = 0; n < B.nt; n++)
             {
               cuda_safe_call(cudaSetDevice(A.get_preferred_devid(B.mt - k - 1, B.mt - 1 - m)));
               DGEMM(
@@ -527,9 +527,9 @@ void PDGEMM(cublasOperation_t transa,
   reserved::dot::set_current_color("blue");
 #endif
 
-  for (int m = 0; m < C.mt; m++)
+  for (size_t m = 0; m < C.mt; m++)
   {
-    for (int n = 0; n < C.nt; n++)
+    for (size_t n = 0; n < C.nt; n++)
     {
       //=========================================
       // alpha*A*B does not contribute; scale C
@@ -546,7 +546,7 @@ void PDGEMM(cublasOperation_t transa,
         //================================
         if (transb == CUBLAS_OP_N)
         {
-          for (int k = 0; k < A.nt; k++)
+          for (size_t k = 0; k < A.nt; k++)
           {
             double zbeta = k == 0 ? beta : 1.0;
             DGEMM(transa, transb, alpha, A, m, k, B, k, n, zbeta, C, m, n);
@@ -557,7 +557,7 @@ void PDGEMM(cublasOperation_t transa,
         //=====================================
         else
         {
-          for (int k = 0; k < A.nt; k++)
+          for (size_t k = 0; k < A.nt; k++)
           {
             double zbeta = k == 0 ? beta : 1.0;
             DGEMM(transa, transb, alpha, A, m, k, B, n, k, zbeta, C, m, n);
@@ -571,7 +571,7 @@ void PDGEMM(cublasOperation_t transa,
         //=====================================
         if (transb == CUBLAS_OP_N)
         {
-          for (int k = 0; k < A.mt; k++)
+          for (size_t k = 0; k < A.mt; k++)
           {
             double zbeta = k == 0 ? beta : 1.0;
             DGEMM(transa, transb, alpha, A, k, m, B, k, n, zbeta, C, m, n);
@@ -582,7 +582,7 @@ void PDGEMM(cublasOperation_t transa,
         //==========================================
         else
         {
-          for (int k = 0; k < A.mt; k++)
+          for (size_t k = 0; k < A.mt; k++)
           {
             double zbeta = k == 0 ? beta : 1.0;
             DGEMM(transa, transb, alpha, A, k, m, B, n, k, zbeta, C, m, n);
@@ -662,9 +662,9 @@ int main(int argc, char** argv)
   cudaEvent_t startEvent_pdpotrf, stopEvent_pdpotrf;
   float milliseconds_pdpotrf = 0;
 
-  //    for (int row = 0; row < A.mt; row++)
+  //    for (size_t row = 0; row < A.mt; row++)
   //    {
-  //        for (int col = 0; col <= row; col++)
+  //        for (size_t col = 0; col <= row; col++)
   //        {
   //            cuda_safe_call(cudaSetDevice(A.get_preferred_devid(row, col)));
   //            NOOP(A, row, col);
diff --git a/docs/cudax/stf.rst b/docs/cudax/stf.rst
index 63c8d6363d0..65a4b1ed105 100644
--- a/docs/cudax/stf.rst
+++ b/docs/cudax/stf.rst
@@ -1911,6 +1911,9 @@ helps to better understand the application, and can be helpful to
 optimize the algorithms as it sometimes allow to identify inefficient
 patterns.
 
+Generating visualizations of task graphs
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
 Let us consider the ``examples/01-axpy.cu`` example which we compile as
 usual with ``make build/examples/01-axpy``.
 
@@ -1999,6 +2002,74 @@ It is also possible to include timing information in this graph by setting the
 color the graph nodes according to their relative duration, and the measured
 duration will be included in task labels.
 
+Condensed and structured graphs visualization
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+Realistic workloads are typically made of thousands or millions of tasks which
+cannot be easily visualized using graphviz (dot). To simplify the generated
+graphs we can further
+annotate the application using dot sections.
+Dot sections can also be nested to better structure the visualization.
+
+This is achieved by creating `dot_section` objects in the application. `ctx.dot_section` returns
+an object whose lifetime defines a dot section valid until it is destroyed, or
+when calling the `end()` method on this object. The following example
+illustrates how to add nested sections:
+
+.. code:: c++
+
+    context ctx;
+    auto lA = ctx.logical_token().set_symbol("A");
+    auto lB = ctx.logical_token().set_symbol("B");
+    auto lC = ctx.logical_token().set_symbol("C");
+
+    // Begin a top-level section named "foo"
+    auto s_foo = ctx.dot_section("foo");
+    for (size_t i = 0; i < 2; i++)
+    {
+      // Section named "bar" using RAII
+      auto s_bar = ctx.dot_section("bar");
+      ctx.task(lA.read(), lB.rw()).set_symbol("t1")->*[](cudaStream_t, auto, auto) {};
+      for (size_t j = 0; j < 2; j++) {
+         // Section named "baz" using RAII
+         auto s_bar = ctx.dot_section("baz");
+         ctx.task(lA.read(), lC.rw()).set_symbol("t2")->*[](cudaStream_t, auto, auto) {};
+         ctx.task(lB.read(), lC.read(), lA.rw()).set_symbol("t3")->*[](cudaStream_t, auto, auto, auto) {};
+         // Implicit end of section "baz"
+      }
+      // Implicit end of section "bar"
+    }
+    s_foo.end(); // Explicit end of section "foo"
+    ctx.finalize();
+
+When running this with the `CUDASTF_DOT_FILE` environment variable for example
+set to `dag.dot`, we observe that the graph produced by `dot -Tpdf dag.dot -o
+dag.pdf` depicts these sections as dashed boxes.
+
+.. image:: stf/images/dag-sections.png
+
+Adding sections also makes it possible to define a maximum depth for the
+generated graphs by setting the `CUDASTF_DOT_MAX_DEPTH` environment variable.
+When it is undefined, CUDASTF will display all tasks. Otherwise, if
+`CUDASTF_DOT_MAX_DEPTH` is an integer value of `i` any sections and tasks which
+nesting level is deeper than `i` will be collapsed.
+
+When setting `CUDASTF_DOT_MAX_DEPTH=2`, the previous graph becomes:
+
+.. image:: stf/images/dag-sections-2.png
+
+When setting `CUDASTF_DOT_MAX_DEPTH=1`, one additional level is collapsed:
+
+.. image:: stf/images/dag-sections-1.png
+
+With `CUDASTF_DOT_MAX_DEPTH=0`, only the top-most tasks and sections are displayed:
+
+.. image:: stf/images/dag-sections-0.png
+
+Note that `CUDASTF_DOT_MAX_DEPTH` and `CUDASTF_DOT_TIMING` can be used in
+combination, and that the duration of a section corresponds to the duration of
+all tasks in this sections.
+
 Kernel tuning with ncu
 ^^^^^^^^^^^^^^^^^^^^^^
 
diff --git a/docs/cudax/stf/images/dag-sections-0.dot b/docs/cudax/stf/images/dag-sections-0.dot
new file mode 100644
index 00000000000..c447276ec43
--- /dev/null
+++ b/docs/cudax/stf/images/dag-sections-0.dot
@@ -0,0 +1,5 @@
+digraph {
+"NODE_23" [style="filled" fillcolor="red" label="task fence"]
+"NODE_3" -> "NODE_23"
+"NODE_3" [style="filled" fillcolor="white" label="foo"]
+}
diff --git a/docs/cudax/stf/images/dag-sections-0.png b/docs/cudax/stf/images/dag-sections-0.png
new file mode 100644
index 0000000000000000000000000000000000000000..bc15d5355cdefdd56af1bcbf513e78f9b852d48c
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diff --git a/docs/cudax/stf/images/dag-sections-1.dot b/docs/cudax/stf/images/dag-sections-1.dot
new file mode 100644
index 00000000000..eddf1e29d9c
--- /dev/null
+++ b/docs/cudax/stf/images/dag-sections-1.dot
@@ -0,0 +1,14 @@
+digraph {
+"NODE_23" [style="filled" fillcolor="red" label="task fence"]
+subgraph cluster_section_1 {
+     color=black;
+    style=dashed
+    label="foo"
+    "NODE_13"
+    "NODE_3"
+} // end subgraph cluster_section_1
+ "NODE_13" -> "NODE_23"
+"NODE_3" -> "NODE_13"
+"NODE_13" [style="filled" fillcolor="white" label="bar"]
+"NODE_3" [style="filled" fillcolor="white" label="bar"]
+}
diff --git a/docs/cudax/stf/images/dag-sections-1.png b/docs/cudax/stf/images/dag-sections-1.png
new file mode 100644
index 0000000000000000000000000000000000000000..6f5ca311117f7e31f2e3fd8c79b676b38108f4bc
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diff --git a/docs/cudax/stf/images/dag-sections-2.dot b/docs/cudax/stf/images/dag-sections-2.dot
new file mode 100644
index 00000000000..8c1da4d110c
--- /dev/null
+++ b/docs/cudax/stf/images/dag-sections-2.dot
@@ -0,0 +1,36 @@
+digraph {
+"NODE_23" [style="filled" fillcolor="red" label="task fence"]
+subgraph cluster_section_1 {
+ subgraph cluster_section_2 {
+     color=black;
+    style=dashed
+    label="bar"
+    "NODE_9"
+    "NODE_5"
+    "NODE_3"
+} // end subgraph cluster_section_2
+ subgraph cluster_section_5 {
+     color=black;
+    style=dashed
+    label="bar"
+    "NODE_19"
+    "NODE_15"
+    "NODE_13"
+} // end subgraph cluster_section_5
+     color=black;
+    style=dashed
+    label="foo"
+} // end subgraph cluster_section_1
+ "NODE_19" -> "NODE_23"
+"NODE_3" -> "NODE_5"
+"NODE_5" -> "NODE_9"
+"NODE_15" -> "NODE_19"
+"NODE_9" -> "NODE_13"
+"NODE_13" -> "NODE_15"
+"NODE_19" [style="filled" fillcolor="white" label="baz"]
+"NODE_15" [style="filled" fillcolor="white" label="baz"]
+"NODE_13" [style="filled" fillcolor="white" label="t1\nA(read)(0) \nB(rw)(0) "]
+"NODE_9" [style="filled" fillcolor="white" label="baz"]
+"NODE_5" [style="filled" fillcolor="white" label="baz"]
+"NODE_3" [style="filled" fillcolor="white" label="t1\nA(read)(0) \nB(rw)(0) "]
+}
diff --git a/docs/cudax/stf/images/dag-sections-2.png b/docs/cudax/stf/images/dag-sections-2.png
new file mode 100644
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diff --git a/docs/cudax/stf/images/dag-sections.dot b/docs/cudax/stf/images/dag-sections.dot
new file mode 100644
index 00000000000..bbf13630ee9
--- /dev/null
+++ b/docs/cudax/stf/images/dag-sections.dot
@@ -0,0 +1,69 @@
+digraph {
+"NODE_23" [style="filled" fillcolor="red" label="task fence"]
+subgraph cluster_section_1 {
+ subgraph cluster_section_2 {
+ subgraph cluster_section_3 {
+     color=black;
+    style=dashed
+    label="baz"
+    "NODE_7"
+    "NODE_5"
+} // end subgraph cluster_section_3
+ subgraph cluster_section_4 {
+     color=black;
+    style=dashed
+    label="baz"
+    "NODE_11"
+    "NODE_9"
+} // end subgraph cluster_section_4
+     color=black;
+    style=dashed
+    label="bar"
+    "NODE_3"
+} // end subgraph cluster_section_2
+ subgraph cluster_section_5 {
+ subgraph cluster_section_6 {
+     color=black;
+    style=dashed
+    label="baz"
+    "NODE_17"
+    "NODE_15"
+} // end subgraph cluster_section_6
+ subgraph cluster_section_7 {
+     color=black;
+    style=dashed
+    label="baz"
+    "NODE_21"
+    "NODE_19"
+} // end subgraph cluster_section_7
+     color=black;
+    style=dashed
+    label="bar"
+    "NODE_13"
+} // end subgraph cluster_section_5
+     color=black;
+    style=dashed
+    label="foo"
+} // end subgraph cluster_section_1
+ "NODE_15" -> "NODE_17"
+"NODE_9" -> "NODE_11"
+"NODE_11" -> "NODE_15"
+"NODE_13" -> "NODE_17"
+"NODE_19" -> "NODE_21"
+"NODE_11" -> "NODE_13"
+"NODE_7" -> "NODE_9"
+"NODE_5" -> "NODE_7"
+"NODE_17" -> "NODE_19"
+"NODE_3" -> "NODE_7"
+"NODE_21" -> "NODE_23"
+"NODE_21" [style="filled" fillcolor="white" label="t3\nA(rw)(0) \nB(read)(0) \nC(read)(0) "]
+"NODE_19" [style="filled" fillcolor="white" label="t2\nA(read)(0) \nC(rw)(0) "]
+"NODE_17" [style="filled" fillcolor="white" label="t3\nA(rw)(0) \nB(read)(0) \nC(read)(0) "]
+"NODE_15" [style="filled" fillcolor="white" label="t2\nA(read)(0) \nC(rw)(0) "]
+"NODE_13" [style="filled" fillcolor="white" label="t1\nA(read)(0) \nB(rw)(0) "]
+"NODE_11" [style="filled" fillcolor="white" label="t3\nA(rw)(0) \nB(read)(0) \nC(read)(0) "]
+"NODE_9" [style="filled" fillcolor="white" label="t2\nA(read)(0) \nC(rw)(0) "]
+"NODE_7" [style="filled" fillcolor="white" label="t3\nA(rw)(0) \nB(read)(0) \nC(read)(0) "]
+"NODE_5" [style="filled" fillcolor="white" label="t2\nA(read)(0) \nC(rw)(0) "]
+"NODE_3" [style="filled" fillcolor="white" label="t1\nA(read)(0) \nB(rw)(0) "]
+}
diff --git a/docs/cudax/stf/images/dag-sections.png b/docs/cudax/stf/images/dag-sections.png
new file mode 100644
index 0000000000000000000000000000000000000000..77a5ca2030d059407cdf12721dde35990fe9365c
GIT binary patch
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literal 0
HcmV?d00001


From 3f13d93ed315df1fa6cc3aac4c9244dafc8359f6 Mon Sep 17 00:00:00 2001
From: Allison Piper <alliepiper16@gmail.com>
Date: Wed, 29 Jan 2025 12:00:01 -0500
Subject: [PATCH 04/33] Remove nvks runners from testing pool. (#3580)

---
 ci/matrix.yaml | 14 +++++++-------
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/ci/matrix.yaml b/ci/matrix.yaml
index 6a98e8fc5b0..c3f03d323ab 100644
--- a/ci/matrix.yaml
+++ b/ci/matrix.yaml
@@ -257,13 +257,13 @@ projects:
 
 # testing -> Runner with GPU is in a nv-gh-runners testing pool
 gpus:
-  v100:     { sm: 70 }                # 32 GB,  40 runners
-  t4:       { sm: 75, testing: true } # 16 GB,   8 runners
-  rtx2080:  { sm: 75, testing: true } #  8 GB,   8 runners
-  rtxa6000: { sm: 86, testing: true } # 48 GB,  12 runners
-  l4:       { sm: 89, testing: true } # 24 GB,  48 runners
-  rtx4090:  { sm: 89, testing: true } # 24 GB,  10 runners
-  h100:     { sm: 90, testing: true } # 80 GB,  16 runners
+  v100:     { sm: 70 } # 32 GB,  40 runners
+  t4:       { sm: 75 } # 16 GB,  10 runners
+  rtx2080:  { sm: 75 } #  8 GB,  12 runners
+  rtxa6000: { sm: 86 } # 48 GB,  12 runners
+  l4:       { sm: 89 } # 24 GB,  48 runners
+  rtx4090:  { sm: 89 } # 24 GB,  10 runners
+  h100:     { sm: 90 } # 80 GB,  16 runners
 
 # Tags are used to define a `matrix job` in the workflow section.
 #

From d0f254490bad268887e33266dc64a0722318ef30 Mon Sep 17 00:00:00 2001
From: Michael Schellenberger Costa <miscco@nvidia.com>
Date: Wed, 29 Jan 2025 19:39:31 +0100
Subject: [PATCH 05/33] Try and get rapids green (#3503)

* Drop unneeded mdspan macros

* Guard `cub/detail/launcher/cuda_runtime.cuh` by a cuda compliler

* Fix formatting issue

* Fix bug in contiguous storage
---
 cub/cub/util_device.cuh                       |  4 ++-
 libcudacxx/include/cuda/std/__mdspan/config.h | 26 -------------------
 .../mdspan.mdspan.cons/ctad_c_array.pass.cpp  |  4 +--
 .../ctad_const_c_array.pass.cpp               |  2 +-
 thrust/thrust/detail/contiguous_storage.h     |  2 +-
 5 files changed, 7 insertions(+), 31 deletions(-)

diff --git a/cub/cub/util_device.cuh b/cub/cub/util_device.cuh
index 498f17c1259..fd356b8f9e5 100644
--- a/cub/cub/util_device.cuh
+++ b/cub/cub/util_device.cuh
@@ -713,4 +713,6 @@ private:
 
 CUB_NAMESPACE_END
 
-#include <cub/detail/launcher/cuda_runtime.cuh> // to complete the definition of TripleChevronFactory
+#if _CCCL_HAS_CUDA_COMPILER
+#  include <cub/detail/launcher/cuda_runtime.cuh> // to complete the definition of TripleChevronFactory
+#endif // _CCCL_HAS_CUDA_COMPILER
diff --git a/libcudacxx/include/cuda/std/__mdspan/config.h b/libcudacxx/include/cuda/std/__mdspan/config.h
index 9f1c9898dd2..4cbeffc18c2 100644
--- a/libcudacxx/include/cuda/std/__mdspan/config.h
+++ b/libcudacxx/include/cuda/std/__mdspan/config.h
@@ -245,32 +245,6 @@ static_assert(__MDSPAN_CPLUSPLUS >= __MDSPAN_CXX_STD_14, "mdspan requires C++14
 #    endif
 #  endif
 
-#  if __MDSPAN_USE_BRACKET_OPERATOR
-#    define __MDSPAN_OP(mds, ...) mds[__VA_ARGS__]
-// Corentins demo compiler for subscript chokes on empty [] call,
-// though I believe the proposal supports it?
-#    ifdef __MDSPAN_NO_EMPTY_BRACKET_OPERATOR
-#      define __MDSPAN_OP0(mds) mds.accessor().access(mds.data_handle(), 0)
-#    else
-#      define __MDSPAN_OP0(mds) mds[]
-#    endif
-#    define __MDSPAN_OP1(mds, a)                mds[a]
-#    define __MDSPAN_OP2(mds, a, b)             mds[a, b]
-#    define __MDSPAN_OP3(mds, a, b, c)          mds[a, b, c]
-#    define __MDSPAN_OP4(mds, a, b, c, d)       mds[a, b, c, d]
-#    define __MDSPAN_OP5(mds, a, b, c, d, e)    mds[a, b, c, d, e]
-#    define __MDSPAN_OP6(mds, a, b, c, d, e, f) mds[a, b, c, d, e, f]
-#  else
-#    define __MDSPAN_OP(mds, ...)               mds(__VA_ARGS__)
-#    define __MDSPAN_OP0(mds)                   mds()
-#    define __MDSPAN_OP1(mds, a)                mds(a)
-#    define __MDSPAN_OP2(mds, a, b)             mds(a, b)
-#    define __MDSPAN_OP3(mds, a, b, c)          mds(a, b, c)
-#    define __MDSPAN_OP4(mds, a, b, c, d)       mds(a, b, c, d)
-#    define __MDSPAN_OP5(mds, a, b, c, d, e)    mds(a, b, c, d, e)
-#    define __MDSPAN_OP6(mds, a, b, c, d, e, f) mds(a, b, c, d, e, f)
-#  endif
-
 #endif // _CCCL_STD_VER > 2011
 
 #endif // _LIBCUDACXX___MDSPAN_CONFIG_HPP
diff --git a/libcudacxx/test/libcudacxx/std/containers/views/mdspan/mdspan.mdspan.cons/ctad_c_array.pass.cpp b/libcudacxx/test/libcudacxx/std/containers/views/mdspan/mdspan.mdspan.cons/ctad_c_array.pass.cpp
index 930a772b596..9288d444402 100644
--- a/libcudacxx/test/libcudacxx/std/containers/views/mdspan/mdspan.mdspan.cons/ctad_c_array.pass.cpp
+++ b/libcudacxx/test/libcudacxx/std/containers/views/mdspan/mdspan.mdspan.cons/ctad_c_array.pass.cpp
@@ -32,7 +32,7 @@ int main(int, char**)
     assert(m.rank_dynamic() == 0);
     assert(m.static_extent(0) == 5);
     assert(m.extent(0) == 5);
-    assert(__MDSPAN_OP(m, 2) == 3);
+    assert(m[2] == 3);
 
     cuda::std::mdspan m2(data, 3);
 
@@ -43,7 +43,7 @@ int main(int, char**)
     assert(m2.rank() == 1);
     assert(m2.rank_dynamic() == 1);
     assert(m2.extent(0) == 3);
-    assert(__MDSPAN_OP(m2, 2) == 3);
+    assert(m2[2] == 3);
   }
 #endif
 
diff --git a/libcudacxx/test/libcudacxx/std/containers/views/mdspan/mdspan.mdspan.cons/ctad_const_c_array.pass.cpp b/libcudacxx/test/libcudacxx/std/containers/views/mdspan/mdspan.mdspan.cons/ctad_const_c_array.pass.cpp
index 7957a3cdd39..04656311604 100644
--- a/libcudacxx/test/libcudacxx/std/containers/views/mdspan/mdspan.mdspan.cons/ctad_const_c_array.pass.cpp
+++ b/libcudacxx/test/libcudacxx/std/containers/views/mdspan/mdspan.mdspan.cons/ctad_const_c_array.pass.cpp
@@ -32,7 +32,7 @@ int main(int, char**)
     assert(m.rank_dynamic() == 0);
     assert(m.static_extent(0) == 5);
     assert(m.extent(0) == 5);
-    assert(__MDSPAN_OP(m, 2) == 3);
+    assert(m[2] == 3);
   }
 #endif
 
diff --git a/thrust/thrust/detail/contiguous_storage.h b/thrust/thrust/detail/contiguous_storage.h
index 2391a3a968a..359b45c1ea2 100644
--- a/thrust/thrust/detail/contiguous_storage.h
+++ b/thrust/thrust/detail/contiguous_storage.h
@@ -131,7 +131,7 @@ class contiguous_storage
     }
     else if constexpr (!allocator_traits<Alloc>::is_always_equal::value)
     {
-      NV_IF_TARGET(NV_IS_DEVICE, (assert(m_allocator == other);), (if (m_allocator != other.m_allocator) {
+      NV_IF_TARGET(NV_IS_DEVICE, (assert(m_allocator == other.m_allocator);), (if (m_allocator != other.m_allocator) {
                      throw allocator_mismatch_on_swap();
                    }));
     }

From da97c370629e2f7620e47efc078071cb80d2b738 Mon Sep 17 00:00:00 2001
From: Elias Stehle <3958403+elstehle@users.noreply.github.com>
Date: Wed, 29 Jan 2025 20:36:26 +0100
Subject: [PATCH 06/33] fixes return type of tabulate out iter (#3573)

---
 thrust/thrust/iterator/detail/tabulate_output_iterator.inl | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/thrust/thrust/iterator/detail/tabulate_output_iterator.inl b/thrust/thrust/iterator/detail/tabulate_output_iterator.inl
index f9b740bca6b..56c093ff56a 100644
--- a/thrust/thrust/iterator/detail/tabulate_output_iterator.inl
+++ b/thrust/thrust/iterator/detail/tabulate_output_iterator.inl
@@ -53,7 +53,7 @@ template <typename BinaryFunction, typename System, typename DifferenceT>
 using tabulate_output_iterator_base =
   thrust::iterator_adaptor<tabulate_output_iterator<BinaryFunction, System, DifferenceT>,
                            counting_iterator<DifferenceT>,
-                           thrust::use_default,
+                           void,
                            System,
                            thrust::use_default,
                            tabulate_output_iterator_proxy<BinaryFunction, DifferenceT>>;

From 09b12009d906bdb69f9da60de5196991d0610f9e Mon Sep 17 00:00:00 2001
From: Federico Busato <50413820+fbusato@users.noreply.github.com>
Date: Wed, 29 Jan 2025 11:39:14 -0800
Subject: [PATCH 07/33] Add `__int128` and `__float128` detection macros
 (#3413)

---
 docs/cccl_development/macro.rst               | 22 +++++-----
 libcudacxx/include/cuda/__cccl_config         |  2 +-
 ...floating_point.h => extended_data_types.h} | 42 ++++++++++++++++---
 .../macros}/architecture.compile.pass.cpp     |  0
 ....cpp => extended_data_types.bf16.fail.cpp} | 24 ++---------
 .../macros/extended_data_types.fp128.fail.cpp | 23 ++++++++++
 .../macros/extended_data_types.fp16.fail.cpp  | 26 ++++++++++++
 .../macros/extended_data_types.fp8.fail.cpp   | 26 ++++++++++++
 .../macros/extended_data_types.i128.fail.cpp  | 24 +++++++++++
 ....pass.cpp => extended_data_types.pass.cpp} | 24 +++++++----
 .../macros}/os.compile.pass.cpp               |  0
 11 files changed, 169 insertions(+), 44 deletions(-)
 rename libcudacxx/include/cuda/std/__cccl/{extended_floating_point.h => extended_data_types.h} (54%)
 rename libcudacxx/test/libcudacxx/{std/cccl => libcxx/macros}/architecture.compile.pass.cpp (100%)
 rename libcudacxx/test/libcudacxx/libcxx/macros/{extended_floating_point.fail.cpp => extended_data_types.bf16.fail.cpp} (60%)
 create mode 100644 libcudacxx/test/libcudacxx/libcxx/macros/extended_data_types.fp128.fail.cpp
 create mode 100644 libcudacxx/test/libcudacxx/libcxx/macros/extended_data_types.fp16.fail.cpp
 create mode 100644 libcudacxx/test/libcudacxx/libcxx/macros/extended_data_types.fp8.fail.cpp
 create mode 100644 libcudacxx/test/libcudacxx/libcxx/macros/extended_data_types.i128.fail.cpp
 rename libcudacxx/test/libcudacxx/libcxx/macros/{extended_floating_point.pass.cpp => extended_data_types.pass.cpp} (62%)
 rename libcudacxx/test/libcudacxx/{std/cccl => libcxx/macros}/os.compile.pass.cpp (100%)

diff --git a/docs/cccl_development/macro.rst b/docs/cccl_development/macro.rst
index 5cc39f0f0d3..6b832da0000 100644
--- a/docs/cccl_development/macro.rst
+++ b/docs/cccl_development/macro.rst
@@ -184,18 +184,20 @@ Non-standard Types Support
 +------------------------------+-------------------------------------------------------------------------------------------------------------------------------+
 | ``_CCCL_HAS_NVBF16``         | ``__nv_bfloat16/__nv_bfloat162`` data types are supported and enabled.  Prefer over ``__CUDA_BF16_TYPES_EXIST__``             |
 +------------------------------+-------------------------------------------------------------------------------------------------------------------------------+
-| ``_CCCL_HAS_FP8()``          | ``__nv_fp8_e5m2/__nv_fp8_e4m3/__nv_fp8_e8m0`` data types are supported and enabled.  Prefer over ``__CUDA_FP8_TYPES_EXIST__`` |
+| ``_CCCL_HAS_NVFP8()``        | ``__nv_fp8_e5m2/__nv_fp8_e4m3/__nv_fp8_e8m0`` data types are supported and enabled.  Prefer over ``__CUDA_FP8_TYPES_EXIST__`` |
 +------------------------------+-------------------------------------------------------------------------------------------------------------------------------+
 
-+------------------------------+-------------------------------------------------------------------------+
-| ``_CCCL_DISABLE_INT128``     | Disable ``__int128/__uint128_t`` support                                |
-+------------------------------+-------------------------------------------------------------------------+
-| ``_CCCL_DISABLE_FLOAT128``   | Disable ``__float128`` support                                          |
-+------------------------------+-------------------------------------------------------------------------+
-| ``_LIBCUDACXX_HAS_NVFP16``   | ``__half/__half2`` host/device are supported  (CUDA 12.2+)              |
-+------------------------------+-------------------------------------------------------------------------+
-| ``_LIBCUDACXX_HAS_NVBF16``   | ``__nv_bfloat16/__nv_bfloat162`` host/device are supported (CUDA 12.2+) |
-+------------------------------+-------------------------------------------------------------------------+
++---------------------------------+-------------------------------------------------------------------------+
+| ``_CCCL_DISABLE_NVFP8_SUPPORT`` | Disable ``__nv_fp8_e5m2/__nv_fp8_e4m3/__nv_fp8_e8m0`` support           |
++---------------------------------+-------------------------------------------------------------------------+
+| ``_CCCL_DISABLE_INT128``        | Disable ``__int128/__uint128_t`` support                                |
++---------------------------------+-------------------------------------------------------------------------+
+| ``_CCCL_DISABLE_FLOAT128``      | Disable ``__float128`` support                                          |
++---------------------------------+-------------------------------------------------------------------------+
+| ``_LIBCUDACXX_HAS_NVFP16``      | ``__half/__half2`` host/device are supported  (CUDA 12.2+)              |
++---------------------------------+-------------------------------------------------------------------------+
+| ``_LIBCUDACXX_HAS_NVBF16``      | ``__nv_bfloat16/__nv_bfloat162`` host/device are supported (CUDA 12.2+) |
++---------------------------------+-------------------------------------------------------------------------+
 
 ----
 
diff --git a/libcudacxx/include/cuda/__cccl_config b/libcudacxx/include/cuda/__cccl_config
index fc28d63ace1..e7fdf26dcc5 100644
--- a/libcudacxx/include/cuda/__cccl_config
+++ b/libcudacxx/include/cuda/__cccl_config
@@ -21,7 +21,7 @@
 #include <cuda/std/__cccl/dialect.h> // IWYU pragma: export
 #include <cuda/std/__cccl/exceptions.h> // IWYU pragma: export
 #include <cuda/std/__cccl/execution_space.h> // IWYU pragma: export
-#include <cuda/std/__cccl/extended_floating_point.h> // IWYU pragma: export
+#include <cuda/std/__cccl/extended_data_types.h> // IWYU pragma: export
 #include <cuda/std/__cccl/os.h> // IWYU pragma: export
 #include <cuda/std/__cccl/preprocessor.h> // IWYU pragma: export
 #include <cuda/std/__cccl/ptx_isa.h> // IWYU pragma: export
diff --git a/libcudacxx/include/cuda/std/__cccl/extended_floating_point.h b/libcudacxx/include/cuda/std/__cccl/extended_data_types.h
similarity index 54%
rename from libcudacxx/include/cuda/std/__cccl/extended_floating_point.h
rename to libcudacxx/include/cuda/std/__cccl/extended_data_types.h
index dee553633d8..034ebc51b5f 100644
--- a/libcudacxx/include/cuda/std/__cccl/extended_floating_point.h
+++ b/libcudacxx/include/cuda/std/__cccl/extended_data_types.h
@@ -4,12 +4,12 @@
 // under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
-// SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES.
+// SPDX-FileCopyrightText: Copyright (c) 2025 NVIDIA CORPORATION & AFFILIATES.
 //
 //===----------------------------------------------------------------------===//
 
-#ifndef __CCCL_EXTENDED_FLOATING_POINT_H
-#define __CCCL_EXTENDED_FLOATING_POINT_H
+#ifndef __CCCL_EXTENDED_DATA_TYPES_H
+#define __CCCL_EXTENDED_DATA_TYPES_H
 
 #include <cuda/std/__cccl/compiler.h>
 #include <cuda/std/__cccl/system_header.h>
@@ -23,8 +23,21 @@
 #endif // no system header
 
 #include <cuda/std/__cccl/diagnostic.h>
+#include <cuda/std/__cccl/os.h>
 #include <cuda/std/__cccl/preprocessor.h>
 
+#if !defined(_CCCL_DISABLE_INT128)
+#  if _CCCL_COMPILER(NVRTC) && defined(__CUDACC_RTC_INT128__) && _CCCL_OS(LINUX)
+#    define _CCCL_HAS_INT128() 1
+#  elif defined(__SIZEOF_INT128__) && _CCCL_OS(LINUX)
+#    define _CCCL_HAS_INT128() 1
+#  else
+#    define _CCCL_HAS_INT128() 0
+#  endif
+#else
+#  define _CCCL_HAS_INT128() 0
+#endif // !_CCCL_DISABLE_INT128
+
 #if !defined(_CCCL_HAS_NVFP16)
 #  if _CCCL_HAS_INCLUDE(<cuda_fp16.h>) && (_CCCL_HAS_CUDA_COMPILER || defined(LIBCUDACXX_ENABLE_HOST_NVFP16)) \
                         && !defined(CCCL_DISABLE_FP16_SUPPORT)
@@ -44,9 +57,28 @@
 #    define _CCCL_HAS_NVFP8() 1
 #  else
 #    define _CCCL_HAS_NVFP8() 0
-#  endif // _CCCL_HAS_INCLUDE(<cuda_fp8.h>)
+#  endif // _CCCL_HAS_INCLUDE(<cuda_fp8.h>) && defined(_CCCL_HAS_NVFP16) && defined(_CCCL_HAS_NVBF16)
 #else
 #  define _CCCL_HAS_NVFP8() 0
 #endif // !defined(_CCCL_DISABLE_NVFP8_SUPPORT)
 
-#endif // __CCCL_EXTENDED_FLOATING_POINT_H
+#if !defined(_CCCL_DISABLE_FLOAT128)
+#  if _CCCL_COMPILER(NVRTC) && defined(__CUDACC_RTC_FLOAT128__) && _CCCL_OS(LINUX)
+#    if !defined(__CUDA_ARCH__) || (defined(__CUDA_ARCH__) && __CUDA_ARCH__ >= 1000)
+#      define _CCCL_HAS_FLOAT128() 1
+#    else
+#      define _CCCL_HAS_FLOAT128() 0
+#    endif
+// NVC++ support float128 only in host code
+#  elif (defined(__SIZEOF_FLOAT128__) || defined(__FLOAT128__)) && _CCCL_OS(LINUX) && !_CCCL_CUDA_COMPILER(NVHPC)
+#    if !defined(__CUDA_ARCH__) || (defined(__CUDA_ARCH__) && __CUDA_ARCH__ >= 1000)
+#      define _CCCL_HAS_FLOAT128() 1
+#    else
+#      define _CCCL_HAS_FLOAT128() 0
+#    endif
+#  else
+#    define _CCCL_HAS_FLOAT128() 0
+#  endif
+#endif // !defined(_CCCL_DISABLE_FLOAT128)
+
+#endif // __CCCL_EXTENDED_DATA_TYPES_H
diff --git a/libcudacxx/test/libcudacxx/std/cccl/architecture.compile.pass.cpp b/libcudacxx/test/libcudacxx/libcxx/macros/architecture.compile.pass.cpp
similarity index 100%
rename from libcudacxx/test/libcudacxx/std/cccl/architecture.compile.pass.cpp
rename to libcudacxx/test/libcudacxx/libcxx/macros/architecture.compile.pass.cpp
diff --git a/libcudacxx/test/libcudacxx/libcxx/macros/extended_floating_point.fail.cpp b/libcudacxx/test/libcudacxx/libcxx/macros/extended_data_types.bf16.fail.cpp
similarity index 60%
rename from libcudacxx/test/libcudacxx/libcxx/macros/extended_floating_point.fail.cpp
rename to libcudacxx/test/libcudacxx/libcxx/macros/extended_data_types.bf16.fail.cpp
index 3b6b457e633..fef41309a67 100644
--- a/libcudacxx/test/libcudacxx/libcxx/macros/extended_floating_point.fail.cpp
+++ b/libcudacxx/test/libcudacxx/libcxx/macros/extended_data_types.bf16.fail.cpp
@@ -6,37 +6,19 @@
 // SPDX-FileCopyrightText: Copyright (c) 2025 NVIDIA CORPORATION & AFFILIATES.
 //
 //===----------------------------------------------------------------------===//
-#include <cuda/std/__cccl/extended_floating_point.h>
+#include <cuda/std/__cccl/extended_data_types.h>
 
 #include "test_macros.h"
 
-#if !_CCCL_HAS_NVFP8()
-#  include <cuda_fp8.h>
-#endif
-#if !defined(_CCCL_HAS_NVFP16)
-#  include <cuda_fp16.h>
-#endif
 #if !defined(_CCCL_HAS_NVBF16)
 #  include <cuda_bf16.h>
 #endif
 
 int main(int, char**)
 {
-#if !_CCCL_HAS_NVFP8()
-  auto x = __nv_fp8_e4m3(1.0f);
-  unused(x);
-#else
-  static_assert(false);
-#endif
-#if !defined(_CCCL_HAS_NVFP16)
-  auto y = __half(1.0f);
-  unused(y);
-#else
-  static_assert(false);
-#endif
 #if !defined(_CCCL_HAS_NVBF16)
-  auto z = __nv_bfloat16(1.0f);
-  unused(z);
+  auto x3 = __nv_bfloat16(1.0f);
+  unused(x3);
 #else
   static_assert(false);
 #endif
diff --git a/libcudacxx/test/libcudacxx/libcxx/macros/extended_data_types.fp128.fail.cpp b/libcudacxx/test/libcudacxx/libcxx/macros/extended_data_types.fp128.fail.cpp
new file mode 100644
index 00000000000..5cebaa96168
--- /dev/null
+++ b/libcudacxx/test/libcudacxx/libcxx/macros/extended_data_types.fp128.fail.cpp
@@ -0,0 +1,23 @@
+//===----------------------------------------------------------------------===//
+//
+// Part of libcu++, the C++ Standard Library for your entire system,
+// under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+// SPDX-FileCopyrightText: Copyright (c) 2025 NVIDIA CORPORATION & AFFILIATES.
+//
+//===----------------------------------------------------------------------===//
+#include <cuda/std/__cccl/extended_data_types.h>
+
+#include "test_macros.h"
+
+int main(int, char**)
+{
+#if !_CCCL_HAS_FLOAT128()
+  __float128 x4 = __float128(3.14) + __float128(3.14);
+  unused(x4);
+#else
+  static_assert(false);
+#endif
+  return 0;
+}
diff --git a/libcudacxx/test/libcudacxx/libcxx/macros/extended_data_types.fp16.fail.cpp b/libcudacxx/test/libcudacxx/libcxx/macros/extended_data_types.fp16.fail.cpp
new file mode 100644
index 00000000000..d4925743db9
--- /dev/null
+++ b/libcudacxx/test/libcudacxx/libcxx/macros/extended_data_types.fp16.fail.cpp
@@ -0,0 +1,26 @@
+//===----------------------------------------------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+// SPDX-FileCopyrightText: Copyright (c) 2025 NVIDIA CORPORATION & AFFILIATES.
+//
+//===----------------------------------------------------------------------===//
+#include <cuda/std/__cccl/extended_data_types.h>
+
+#include "test_macros.h"
+
+#if !defined(_CCCL_HAS_NVFP16)
+#  include <cuda_fp16.h>
+#endif
+
+int main(int, char**)
+{
+#if !defined(_CCCL_HAS_NVFP16)
+  auto x2 = __half(1.0f);
+  unused(x2);
+#else
+  static_assert(false);
+#endif
+  return 0;
+}
diff --git a/libcudacxx/test/libcudacxx/libcxx/macros/extended_data_types.fp8.fail.cpp b/libcudacxx/test/libcudacxx/libcxx/macros/extended_data_types.fp8.fail.cpp
new file mode 100644
index 00000000000..7418e0030b7
--- /dev/null
+++ b/libcudacxx/test/libcudacxx/libcxx/macros/extended_data_types.fp8.fail.cpp
@@ -0,0 +1,26 @@
+//===----------------------------------------------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+// SPDX-FileCopyrightText: Copyright (c) 2025 NVIDIA CORPORATION & AFFILIATES.
+//
+//===----------------------------------------------------------------------===//
+#include <cuda/std/__cccl/extended_data_types.h>
+
+#include "test_macros.h"
+
+#if !_CCCL_HAS_NVFP8()
+#  include <cuda_fp8.h>
+#endif
+
+int main(int, char**)
+{
+#if !_CCCL_HAS_NVFP8()
+  auto x1 = __nv_fp8_e4m3(1.0f);
+  unused(x1);
+#else
+  static_assert(false);
+#endif
+  return 0;
+}
diff --git a/libcudacxx/test/libcudacxx/libcxx/macros/extended_data_types.i128.fail.cpp b/libcudacxx/test/libcudacxx/libcxx/macros/extended_data_types.i128.fail.cpp
new file mode 100644
index 00000000000..04dd7ea7525
--- /dev/null
+++ b/libcudacxx/test/libcudacxx/libcxx/macros/extended_data_types.i128.fail.cpp
@@ -0,0 +1,24 @@
+//===----------------------------------------------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+// SPDX-FileCopyrightText: Copyright (c) 2025 NVIDIA CORPORATION & AFFILIATES.
+//
+//===----------------------------------------------------------------------===//
+#include <cuda/std/__cccl/extended_data_types.h>
+
+#include "test_macros.h"
+
+int main(int, char**)
+{
+#if !_CCCL_HAS_INT128()
+  __int128 x    = __int128(123456789123) + __int128(123456789123);
+  __uint128_t y = __uint128_t(123456789123) + __uint128_t(123456789123);
+  unused(x);
+  unused(y);
+#else
+  static_assert(false);
+#endif
+  return 0;
+}
diff --git a/libcudacxx/test/libcudacxx/libcxx/macros/extended_floating_point.pass.cpp b/libcudacxx/test/libcudacxx/libcxx/macros/extended_data_types.pass.cpp
similarity index 62%
rename from libcudacxx/test/libcudacxx/libcxx/macros/extended_floating_point.pass.cpp
rename to libcudacxx/test/libcudacxx/libcxx/macros/extended_data_types.pass.cpp
index fa1476611bc..3b230d8710b 100644
--- a/libcudacxx/test/libcudacxx/libcxx/macros/extended_floating_point.pass.cpp
+++ b/libcudacxx/test/libcudacxx/libcxx/macros/extended_data_types.pass.cpp
@@ -6,7 +6,7 @@
 // SPDX-FileCopyrightText: Copyright (c) 2025 NVIDIA CORPORATION & AFFILIATES.
 //
 //===----------------------------------------------------------------------===//
-#include <cuda/std/__cccl/extended_floating_point.h>
+#include <cuda/std/__cccl/extended_data_types.h>
 
 #include "test_macros.h"
 
@@ -22,17 +22,27 @@
 
 int main(int, char**)
 {
+#if _CCCL_HAS_INT128()
+  auto x1 = __int128(123456789123) + __int128(123456789123);
+  auto y1 = __uint128_t(123456789123) + __uint128_t(123456789123);
+  unused(x1);
+  unused(y1);
+#endif
 #if _CCCL_HAS_NVFP8()
-  auto x = __nv_fp8_e4m3(1.0f);
-  unused(x);
+  auto x2 = __nv_fp8_e4m3(1.0f);
+  unused(x2);
 #endif
 #if defined(_CCCL_HAS_NVFP16)
-  auto y = __half(1.0f);
-  unused(y);
+  auto x3 = __half(1.0f);
+  unused(x3);
 #endif
 #if defined(_CCCL_HAS_NVBF16)
-  auto z = __nv_bfloat16(1.0f);
-  unused(z);
+  auto x4 = __nv_bfloat16(1.0f);
+  unused(x4);
+#endif
+#if _CCCL_HAS_FLOAT128()
+  __float128 x5 = __float128(3.14) + __float128(3.14);
+  unused(x5);
 #endif
   return 0;
 }
diff --git a/libcudacxx/test/libcudacxx/std/cccl/os.compile.pass.cpp b/libcudacxx/test/libcudacxx/libcxx/macros/os.compile.pass.cpp
similarity index 100%
rename from libcudacxx/test/libcudacxx/std/cccl/os.compile.pass.cpp
rename to libcudacxx/test/libcudacxx/libcxx/macros/os.compile.pass.cpp

From ced506dd40f78817047d8f93d785a2f898711d2e Mon Sep 17 00:00:00 2001
From: Federico Busato <50413820+fbusato@users.noreply.github.com>
Date: Wed, 29 Jan 2025 12:49:56 -0800
Subject: [PATCH 08/33] Remove all code paths and policies for SM37 and below
 (#3466)

---
 .../adjacent_difference/subtract_left.cu      |  4 +-
 cub/benchmarks/bench/copy/memcpy.cu           |  2 +-
 .../bench/histogram/histogram_common.cuh      |  2 +-
 cub/benchmarks/bench/partition/three_way.cu   |  2 +-
 cub/benchmarks/bench/reduce/by_key.cu         |  4 +-
 .../bench/run_length_encode/encode.cu         |  4 +-
 .../run_length_encode/non_trivial_runs.cu     |  4 +-
 cub/benchmarks/bench/segmented_sort/keys.cu   |  4 +-
 cub/benchmarks/bench/select/unique_by_key.cu  |  4 +-
 cub/benchmarks/bench/transform/common.h       |  2 +-
 .../device/dispatch/dispatch_spmv_orig.cuh    | 50 +----------
 .../tuning/tuning_adjacent_difference.cuh     | 14 +---
 .../dispatch/tuning/tuning_batch_memcpy.cuh   |  6 +-
 cub/cub/device/dispatch/tuning/tuning_for.cuh |  4 +-
 .../dispatch/tuning/tuning_histogram.cuh      |  9 +-
 .../device/dispatch/tuning/tuning_merge.cuh   | 14 +---
 .../dispatch/tuning/tuning_merge_sort.cuh     |  6 +-
 .../dispatch/tuning/tuning_radix_sort.cuh     | 83 +------------------
 .../device/dispatch/tuning/tuning_reduce.cuh  | 23 +----
 .../dispatch/tuning/tuning_reduce_by_key.cuh  |  6 +-
 .../tuning/tuning_run_length_encode.cuh       | 16 ++--
 .../device/dispatch/tuning/tuning_scan.cuh    |  4 +-
 .../dispatch/tuning/tuning_scan_by_key.cuh    |  4 +-
 .../dispatch/tuning/tuning_segmented_sort.cuh | 28 +------
 .../dispatch/tuning/tuning_select_if.cuh      |  6 +-
 .../tuning/tuning_three_way_partition.cuh     |  6 +-
 .../dispatch/tuning/tuning_unique_by_key.cuh  |  6 +-
 ...vice_run_length_encode_non_trivial_runs.cu |  4 +-
 cub/test/catch2_test_util_device.cu           | 21 ++---
 cub/test/catch2_test_vsmem.cu                 |  8 +-
 docs/cub/developer_overview.rst               |  6 +-
 docs/repo.toml                                |  2 +-
 .../libcudacxx/cuda/test_platform.pass.cpp    | 24 ------
 libcudacxx/test/support/concurrent_agents.h   |  4 -
 thrust/thrust/system/cuda/detail/core/util.h  | 40 +--------
 thrust/thrust/system/cuda/detail/reduce.h     | 16 +---
 .../thrust/system/cuda/detail/reduce_by_key.h | 49 +----------
 .../system/cuda/detail/set_operations.h       | 21 -----
 thrust/thrust/system/cuda/detail/unique.h     | 30 -------
 39 files changed, 86 insertions(+), 456 deletions(-)

diff --git a/cub/benchmarks/bench/adjacent_difference/subtract_left.cu b/cub/benchmarks/bench/adjacent_difference/subtract_left.cu
index 6976b024d37..89e4bc485e9 100644
--- a/cub/benchmarks/bench/adjacent_difference/subtract_left.cu
+++ b/cub/benchmarks/bench/adjacent_difference/subtract_left.cu
@@ -35,7 +35,7 @@
 #if !TUNE_BASE
 struct policy_hub_t
 {
-  struct Policy350 : cub::ChainedPolicy<350, Policy350, Policy350>
+  struct Policy500 : cub::ChainedPolicy<500, Policy500, Policy500>
   {
     using AdjacentDifferencePolicy =
       cub::AgentAdjacentDifferencePolicy<TUNE_THREADS_PER_BLOCK,
@@ -45,7 +45,7 @@ struct policy_hub_t
                                          cub::BLOCK_STORE_WARP_TRANSPOSE>;
   };
 
-  using MaxPolicy = Policy350;
+  using MaxPolicy = Policy500;
 };
 #endif // !TUNE_BASE
 
diff --git a/cub/benchmarks/bench/copy/memcpy.cu b/cub/benchmarks/bench/copy/memcpy.cu
index 678091cb0c0..07162bf602a 100644
--- a/cub/benchmarks/bench/copy/memcpy.cu
+++ b/cub/benchmarks/bench/copy/memcpy.cu
@@ -118,7 +118,7 @@ using block_delay_constructor_t =
 
 struct policy_hub_t
 {
-  struct policy_t : cub::ChainedPolicy<350, policy_t, policy_t>
+  struct policy_t : cub::ChainedPolicy<500, policy_t, policy_t>
   {
     using AgentSmallBufferPolicyT = cub::detail::AgentBatchMemcpyPolicy<
       TUNE_THREADS,
diff --git a/cub/benchmarks/bench/histogram/histogram_common.cuh b/cub/benchmarks/bench/histogram/histogram_common.cuh
index d6a7f9f9173..93eea3e8e02 100644
--- a/cub/benchmarks/bench/histogram/histogram_common.cuh
+++ b/cub/benchmarks/bench/histogram/histogram_common.cuh
@@ -62,7 +62,7 @@ constexpr cub::BlockHistogramMemoryPreference MEM_PREFERENCE = cub::BLEND;
 template <typename SampleT, int NUM_CHANNELS, int NUM_ACTIVE_CHANNELS>
 struct policy_hub_t
 {
-  struct policy_t : cub::ChainedPolicy<350, policy_t, policy_t>
+  struct policy_t : cub::ChainedPolicy<500, policy_t, policy_t>
   {
     static constexpr cub::BlockLoadAlgorithm load_algorithm =
       (TUNE_LOAD_ALGORITHM == cub::BLOCK_LOAD_STRIPED)
diff --git a/cub/benchmarks/bench/partition/three_way.cu b/cub/benchmarks/bench/partition/three_way.cu
index 9b1fdb0e18d..ff53970d824 100644
--- a/cub/benchmarks/bench/partition/three_way.cu
+++ b/cub/benchmarks/bench/partition/three_way.cu
@@ -47,7 +47,7 @@
 template <typename InputT>
 struct policy_hub_t
 {
-  struct policy_t : cub::ChainedPolicy<350, policy_t, policy_t>
+  struct policy_t : cub::ChainedPolicy<500, policy_t, policy_t>
   {
     using ThreeWayPartitionPolicy = //
       cub::AgentThreeWayPartitionPolicy<TUNE_THREADS_PER_BLOCK,
diff --git a/cub/benchmarks/bench/reduce/by_key.cu b/cub/benchmarks/bench/reduce/by_key.cu
index 435dfd7b2ca..8faa24cc7b8 100644
--- a/cub/benchmarks/bench/reduce/by_key.cu
+++ b/cub/benchmarks/bench/reduce/by_key.cu
@@ -53,7 +53,7 @@
 
 struct reduce_by_key_policy_hub
 {
-  struct Policy350 : cub::ChainedPolicy<350, Policy350, Policy350>
+  struct Policy500 : cub::ChainedPolicy<500, Policy500, Policy500>
   {
     using ReduceByKeyPolicyT =
       cub::AgentReduceByKeyPolicy<TUNE_THREADS,
@@ -64,7 +64,7 @@ struct reduce_by_key_policy_hub
                                   delay_constructor_t>;
   };
 
-  using MaxPolicy = Policy350;
+  using MaxPolicy = Policy500;
 };
 #endif // !TUNE_BASE
 
diff --git a/cub/benchmarks/bench/run_length_encode/encode.cu b/cub/benchmarks/bench/run_length_encode/encode.cu
index 9a62b073e75..481f9a4f2ae 100644
--- a/cub/benchmarks/bench/run_length_encode/encode.cu
+++ b/cub/benchmarks/bench/run_length_encode/encode.cu
@@ -55,7 +55,7 @@
 
 struct reduce_by_key_policy_hub
 {
-  struct Policy350 : cub::ChainedPolicy<350, Policy350, Policy350>
+  struct Policy500 : cub::ChainedPolicy<500, Policy500, Policy500>
   {
     using ReduceByKeyPolicyT =
       cub::AgentReduceByKeyPolicy<TUNE_THREADS,
@@ -66,7 +66,7 @@ struct reduce_by_key_policy_hub
                                   delay_constructor_t>;
   };
 
-  using MaxPolicy = Policy350;
+  using MaxPolicy = Policy500;
 };
 #endif // !TUNE_BASE
 
diff --git a/cub/benchmarks/bench/run_length_encode/non_trivial_runs.cu b/cub/benchmarks/bench/run_length_encode/non_trivial_runs.cu
index 112b716ca86..398711fed80 100644
--- a/cub/benchmarks/bench/run_length_encode/non_trivial_runs.cu
+++ b/cub/benchmarks/bench/run_length_encode/non_trivial_runs.cu
@@ -54,7 +54,7 @@
 
 struct device_rle_policy_hub
 {
-  struct Policy350 : cub::ChainedPolicy<350, Policy350, Policy350>
+  struct Policy500 : cub::ChainedPolicy<500, Policy500, Policy500>
   {
     using RleSweepPolicyT =
       cub::AgentRlePolicy<TUNE_THREADS,
@@ -66,7 +66,7 @@ struct device_rle_policy_hub
                           delay_constructor_t>;
   };
 
-  using MaxPolicy = Policy350;
+  using MaxPolicy = Policy500;
 };
 #endif // !TUNE_BASE
 
diff --git a/cub/benchmarks/bench/segmented_sort/keys.cu b/cub/benchmarks/bench/segmented_sort/keys.cu
index b3ecbf51656..8d793c67e44 100644
--- a/cub/benchmarks/bench/segmented_sort/keys.cu
+++ b/cub/benchmarks/bench/segmented_sort/keys.cu
@@ -109,7 +109,7 @@ struct device_seg_sort_policy_hub
 {
   using DominantT = KeyT;
 
-  struct Policy350 : cub::ChainedPolicy<350, Policy350, Policy350>
+  struct Policy500 : cub::ChainedPolicy<500, Policy500, Policy500>
   {
     static constexpr int BLOCK_THREADS          = TUNE_THREADS;
     static constexpr int RADIX_BITS             = TUNE_RADIX_BITS;
@@ -143,7 +143,7 @@ struct device_seg_sort_policy_hub
                                        TUNE_M_LOAD_MODIFIER>>;
   };
 
-  using MaxPolicy = Policy350;
+  using MaxPolicy = Policy500;
 };
 #endif // !TUNE_BASE
 
diff --git a/cub/benchmarks/bench/select/unique_by_key.cu b/cub/benchmarks/bench/select/unique_by_key.cu
index 7950aaeda2f..473aff6b589 100644
--- a/cub/benchmarks/bench/select/unique_by_key.cu
+++ b/cub/benchmarks/bench/select/unique_by_key.cu
@@ -53,7 +53,7 @@
 
 struct policy_hub
 {
-  struct Policy350 : cub::ChainedPolicy<350, Policy350, Policy350>
+  struct Policy500 : cub::ChainedPolicy<500, Policy500, Policy500>
   {
     using UniqueByKeyPolicyT =
       cub::AgentUniqueByKeyPolicy<TUNE_THREADS,
@@ -64,7 +64,7 @@ struct policy_hub
                                   delay_constructor_t>;
   };
 
-  using MaxPolicy = Policy350;
+  using MaxPolicy = Policy500;
 };
 #endif // !TUNE_BASE
 
diff --git a/cub/benchmarks/bench/transform/common.h b/cub/benchmarks/bench/transform/common.h
index d8339645429..3f8ad71f590 100644
--- a/cub/benchmarks/bench/transform/common.h
+++ b/cub/benchmarks/bench/transform/common.h
@@ -31,7 +31,7 @@ using policy_hub_t = cub::detail::transform::policy_hub<false, ::cuda::std::tupl
 #else
 struct policy_hub_t
 {
-  struct max_policy : cub::ChainedPolicy<350, max_policy, max_policy>
+  struct max_policy : cub::ChainedPolicy<500, max_policy, max_policy>
   {
     static constexpr int min_bif    = cub::detail::transform::arch_to_min_bytes_in_flight(__CUDA_ARCH_LIST__);
     static constexpr auto algorithm = static_cast<cub::detail::transform::Algorithm>(TUNE_ALGORITHM);
diff --git a/cub/cub/device/dispatch/dispatch_spmv_orig.cuh b/cub/cub/device/dispatch/dispatch_spmv_orig.cuh
index cd377a6d991..16353f392dc 100644
--- a/cub/cub/device/dispatch/dispatch_spmv_orig.cuh
+++ b/cub/cub/device/dispatch/dispatch_spmv_orig.cuh
@@ -383,40 +383,6 @@ struct CCCL_DEPRECATED_BECAUSE("Use the cuSPARSE library instead") DispatchSpmv
   // Tuning policies
   //---------------------------------------------------------------------
 
-  /// SM35
-  struct Policy350
-  {
-    using SpmvPolicyT =
-      AgentSpmvPolicy<(sizeof(ValueT) > 4) ? 96 : 128,
-                      (sizeof(ValueT) > 4) ? 4 : 7,
-                      LOAD_LDG,
-                      LOAD_CA,
-                      LOAD_LDG,
-                      LOAD_LDG,
-                      LOAD_LDG,
-                      (sizeof(ValueT) > 4) ? true : false,
-                      BLOCK_SCAN_WARP_SCANS>;
-
-    using SegmentFixupPolicyT = AgentSegmentFixupPolicy<128, 3, BLOCK_LOAD_VECTORIZE, LOAD_LDG, BLOCK_SCAN_WARP_SCANS>;
-  };
-
-  /// SM37
-  struct Policy370
-  {
-    using SpmvPolicyT =
-      AgentSpmvPolicy<(sizeof(ValueT) > 4) ? 128 : 128,
-                      (sizeof(ValueT) > 4) ? 9 : 14,
-                      LOAD_LDG,
-                      LOAD_CA,
-                      LOAD_LDG,
-                      LOAD_LDG,
-                      LOAD_LDG,
-                      false,
-                      BLOCK_SCAN_WARP_SCANS>;
-
-    using SegmentFixupPolicyT = AgentSegmentFixupPolicy<128, 3, BLOCK_LOAD_VECTORIZE, LOAD_LDG, BLOCK_SCAN_WARP_SCANS>;
-  };
-
   /// SM50
   struct Policy500
   {
@@ -459,15 +425,8 @@ struct CCCL_DEPRECATED_BECAUSE("Use the cuSPARSE library instead") DispatchSpmv
 #if (CUB_PTX_ARCH >= 600)
   using PtxPolicy = Policy600;
 
-#elif (CUB_PTX_ARCH >= 500)
-  using PtxPolicy = Policy500;
-
-#elif (CUB_PTX_ARCH >= 370)
-  using PtxPolicy = Policy370;
-
 #else
-  using PtxPolicy = Policy350;
-
+  using PtxPolicy = Policy500;
 #endif
 
   // "Opaque" policies (whose parameterizations aren't reflected in the type signature)
@@ -502,12 +461,9 @@ struct CCCL_DEPRECATED_BECAUSE("Use the cuSPARSE library instead") DispatchSpmv
         } else if (ptx_version >= 500) {
           spmv_config.template Init<typename Policy500::SpmvPolicyT>();
           segment_fixup_config.template Init<typename Policy500::SegmentFixupPolicyT>();
-        } else if (ptx_version >= 370) {
-          spmv_config.template Init<typename Policy370::SpmvPolicyT>();
-          segment_fixup_config.template Init<typename Policy370::SegmentFixupPolicyT>();
         } else {
-          spmv_config.template Init<typename Policy350::SpmvPolicyT>();
-          segment_fixup_config.template Init<typename Policy350::SegmentFixupPolicyT>();
+          spmv_config.template Init<typename Policy500::SpmvPolicyT>();
+          segment_fixup_config.template Init<typename Policy500::SegmentFixupPolicyT>();
         }));
   }
 
diff --git a/cub/cub/device/dispatch/tuning/tuning_adjacent_difference.cuh b/cub/cub/device/dispatch/tuning/tuning_adjacent_difference.cuh
index 20717e1c68a..b8d0a7557bd 100644
--- a/cub/cub/device/dispatch/tuning/tuning_adjacent_difference.cuh
+++ b/cub/cub/device/dispatch/tuning/tuning_adjacent_difference.cuh
@@ -52,17 +52,7 @@ struct policy_hub
 {
   using ValueT = typename std::iterator_traits<InputIteratorT>::value_type;
 
-  struct Policy300 : ChainedPolicy<300, Policy300, Policy300>
-  {
-    using AdjacentDifferencePolicy =
-      AgentAdjacentDifferencePolicy<128,
-                                    Nominal8BItemsToItems<ValueT>(7),
-                                    BLOCK_LOAD_WARP_TRANSPOSE,
-                                    LOAD_DEFAULT,
-                                    BLOCK_STORE_WARP_TRANSPOSE>;
-  };
-
-  struct Policy350 : ChainedPolicy<350, Policy350, Policy300>
+  struct Policy500 : ChainedPolicy<500, Policy500, Policy500>
   {
     using AdjacentDifferencePolicy =
       AgentAdjacentDifferencePolicy<128,
@@ -72,7 +62,7 @@ struct policy_hub
                                     BLOCK_STORE_WARP_TRANSPOSE>;
   };
 
-  using MaxPolicy = Policy350;
+  using MaxPolicy = Policy500;
 };
 } // namespace adjacent_difference
 } // namespace detail
diff --git a/cub/cub/device/dispatch/tuning/tuning_batch_memcpy.cuh b/cub/cub/device/dispatch/tuning/tuning_batch_memcpy.cuh
index 86fe3374d89..d0ebefe0a1f 100644
--- a/cub/cub/device/dispatch/tuning/tuning_batch_memcpy.cuh
+++ b/cub/cub/device/dispatch/tuning/tuning_batch_memcpy.cuh
@@ -75,8 +75,8 @@ struct policy_hub
   using buff_delay_constructor_t  = detail::default_delay_constructor_t<BufferOffsetT>;
   using block_delay_constructor_t = detail::default_delay_constructor_t<BlockOffsetT>;
 
-  /// SM35
-  struct Policy350 : ChainedPolicy<350, Policy350, Policy350>
+  /// SM50
+  struct Policy500 : ChainedPolicy<500, Policy500, Policy500>
   {
     static constexpr bool PREFER_POW2_BITS = true;
     using AgentSmallBufferPolicyT          = AgentBatchMemcpyPolicy<
@@ -95,7 +95,7 @@ struct policy_hub
   };
 
   /// SM70
-  struct Policy700 : ChainedPolicy<700, Policy700, Policy350>
+  struct Policy700 : ChainedPolicy<700, Policy700, Policy500>
   {
     static constexpr bool PREFER_POW2_BITS = false;
     using AgentSmallBufferPolicyT          = AgentBatchMemcpyPolicy<
diff --git a/cub/cub/device/dispatch/tuning/tuning_for.cuh b/cub/cub/device/dispatch/tuning/tuning_for.cuh
index 759d7e632e5..d0ec964ca90 100644
--- a/cub/cub/device/dispatch/tuning/tuning_for.cuh
+++ b/cub/cub/device/dispatch/tuning/tuning_for.cuh
@@ -49,12 +49,12 @@ namespace for_each
 
 struct policy_hub_t
 {
-  struct policy_350_t : ChainedPolicy<350, policy_350_t, policy_350_t>
+  struct policy_500_t : ChainedPolicy<500, policy_500_t, policy_500_t>
   {
     using for_policy_t = policy_t<256, 2>;
   };
 
-  using MaxPolicy = policy_350_t;
+  using MaxPolicy = policy_500_t;
 };
 
 } // namespace for_each
diff --git a/cub/cub/device/dispatch/tuning/tuning_histogram.cuh b/cub/cub/device/dispatch/tuning/tuning_histogram.cuh
index 1a06c25cb92..bd19489971e 100644
--- a/cub/cub/device/dispatch/tuning/tuning_histogram.cuh
+++ b/cub/cub/device/dispatch/tuning/tuning_histogram.cuh
@@ -136,15 +136,8 @@ struct policy_hub
     return (::cuda::std::max)(nominalItemsPerThread / NumActiveChannels / v_scale, 1);
   }
 
-  // SM35
-  struct Policy350 : ChainedPolicy<350, Policy350, Policy350>
-  {
-    // TODO This might be worth it to separate usual histogram and the multi one
-    using AgentHistogramPolicyT = AgentHistogramPolicy<128, t_scale(8), BLOCK_LOAD_DIRECT, LOAD_LDG, true, BLEND, true>;
-  };
-
   // SM50
-  struct Policy500 : ChainedPolicy<500, Policy500, Policy350>
+  struct Policy500 : ChainedPolicy<500, Policy500, Policy500>
   {
     // TODO This might be worth it to separate usual histogram and the multi one
     using AgentHistogramPolicyT =
diff --git a/cub/cub/device/dispatch/tuning/tuning_merge.cuh b/cub/cub/device/dispatch/tuning/tuning_merge.cuh
index 0d69dd45b95..2521de6e9c3 100644
--- a/cub/cub/device/dispatch/tuning/tuning_merge.cuh
+++ b/cub/cub/device/dispatch/tuning/tuning_merge.cuh
@@ -53,17 +53,7 @@ struct policy_hub
 
   using tune_type = char[has_values ? sizeof(KeyT) + sizeof(ValueT) : sizeof(KeyT)];
 
-  struct policy300 : ChainedPolicy<300, policy300, policy300>
-  {
-    using merge_policy =
-      agent_policy_t<128,
-                     Nominal4BItemsToItems<tune_type>(7),
-                     BLOCK_LOAD_WARP_TRANSPOSE,
-                     LOAD_DEFAULT,
-                     BLOCK_STORE_WARP_TRANSPOSE>;
-  };
-
-  struct policy350 : ChainedPolicy<350, policy350, policy300>
+  struct policy500 : ChainedPolicy<500, policy500, policy500>
   {
     using merge_policy =
       agent_policy_t<256,
@@ -73,7 +63,7 @@ struct policy_hub
                      BLOCK_STORE_WARP_TRANSPOSE>;
   };
 
-  struct policy520 : ChainedPolicy<520, policy520, policy350>
+  struct policy520 : ChainedPolicy<520, policy520, policy500>
   {
     using merge_policy =
       agent_policy_t<512,
diff --git a/cub/cub/device/dispatch/tuning/tuning_merge_sort.cuh b/cub/cub/device/dispatch/tuning/tuning_merge_sort.cuh
index 94d54b08509..29e98a3898a 100644
--- a/cub/cub/device/dispatch/tuning/tuning_merge_sort.cuh
+++ b/cub/cub/device/dispatch/tuning/tuning_merge_sort.cuh
@@ -51,7 +51,7 @@ struct policy_hub
 {
   using KeyT = value_t<KeyIteratorT>;
 
-  struct Policy350 : ChainedPolicy<350, Policy350, Policy350>
+  struct Policy500 : ChainedPolicy<500, Policy500, Policy500>
   {
     using MergeSortPolicy =
       AgentMergeSortPolicy<256,
@@ -63,9 +63,9 @@ struct policy_hub
 
   // NVBug 3384810
 #if defined(_NVHPC_CUDA)
-  using Policy520 = Policy350;
+  using Policy520 = Policy500;
 #else
-  struct Policy520 : ChainedPolicy<520, Policy520, Policy350>
+  struct Policy520 : ChainedPolicy<520, Policy520, Policy500>
   {
     using MergeSortPolicy =
       AgentMergeSortPolicy<512,
diff --git a/cub/cub/device/dispatch/tuning/tuning_radix_sort.cuh b/cub/cub/device/dispatch/tuning/tuning_radix_sort.cuh
index 99b8dbda413..72c464ec5ea 100644
--- a/cub/cub/device/dispatch/tuning/tuning_radix_sort.cuh
+++ b/cub/cub/device/dispatch/tuning/tuning_radix_sort.cuh
@@ -120,89 +120,8 @@ struct policy_hub
   // Architecture-specific tuning policies
   //------------------------------------------------------------------------------
 
-  /// SM35
-  struct Policy350 : ChainedPolicy<350, Policy350, Policy350>
-  {
-    enum
-    {
-      PRIMARY_RADIX_BITS = (sizeof(KeyT) > 1) ? 6 : 5, // 1.72B 32b keys/s, 1.17B 32b pairs/s, 1.55B 32b segmented
-                                                       // keys/s (K40m)
-      ONESWEEP            = false,
-      ONESWEEP_RADIX_BITS = 8,
-    };
-
-    // Histogram policy
-    using HistogramPolicy = AgentRadixSortHistogramPolicy<256, 8, 1, KeyT, ONESWEEP_RADIX_BITS>;
-
-    // Exclusive sum policy
-    using ExclusiveSumPolicy = AgentRadixSortExclusiveSumPolicy<256, ONESWEEP_RADIX_BITS>;
-
-    // Onesweep policy
-    using OnesweepPolicy = AgentRadixSortOnesweepPolicy<
-      256,
-      21,
-      DominantT,
-      1,
-      RADIX_RANK_MATCH_EARLY_COUNTS_ANY,
-      BLOCK_SCAN_WARP_SCANS,
-      RADIX_SORT_STORE_DIRECT,
-      ONESWEEP_RADIX_BITS>;
-
-    // Scan policy
-    using ScanPolicy =
-      AgentScanPolicy<1024, 4, OffsetT, BLOCK_LOAD_VECTORIZE, LOAD_DEFAULT, BLOCK_STORE_VECTORIZE, BLOCK_SCAN_WARP_SCANS>;
-
-    // Keys-only downsweep policies
-    using DownsweepPolicyKeys = AgentRadixSortDownsweepPolicy<
-      128,
-      9,
-      DominantT,
-      BLOCK_LOAD_WARP_TRANSPOSE,
-      LOAD_LDG,
-      RADIX_RANK_MATCH,
-      BLOCK_SCAN_WARP_SCANS,
-      PRIMARY_RADIX_BITS>;
-    using AltDownsweepPolicyKeys = AgentRadixSortDownsweepPolicy<
-      64,
-      18,
-      DominantT,
-      BLOCK_LOAD_DIRECT,
-      LOAD_LDG,
-      RADIX_RANK_MEMOIZE,
-      BLOCK_SCAN_WARP_SCANS,
-      PRIMARY_RADIX_BITS - 1>;
-
-    // Key-value pairs downsweep policies
-    using DownsweepPolicyPairs    = DownsweepPolicyKeys;
-    using AltDownsweepPolicyPairs = AgentRadixSortDownsweepPolicy<
-      128,
-      15,
-      DominantT,
-      BLOCK_LOAD_DIRECT,
-      LOAD_LDG,
-      RADIX_RANK_MEMOIZE,
-      BLOCK_SCAN_WARP_SCANS,
-      PRIMARY_RADIX_BITS - 1>;
-
-    // Downsweep policies
-    using DownsweepPolicy = ::cuda::std::_If<KEYS_ONLY, DownsweepPolicyKeys, DownsweepPolicyPairs>;
-
-    using AltDownsweepPolicy = ::cuda::std::_If<KEYS_ONLY, AltDownsweepPolicyKeys, AltDownsweepPolicyPairs>;
-
-    // Upsweep policies
-    using UpsweepPolicy    = DownsweepPolicy;
-    using AltUpsweepPolicy = AltDownsweepPolicy;
-
-    // Single-tile policy
-    using SingleTilePolicy = DownsweepPolicy;
-
-    // Segmented policies
-    using SegmentedPolicy    = DownsweepPolicy;
-    using AltSegmentedPolicy = AltDownsweepPolicy;
-  };
-
   /// SM50
-  struct Policy500 : ChainedPolicy<500, Policy500, Policy350>
+  struct Policy500 : ChainedPolicy<500, Policy500, Policy500>
   {
     enum
     {
diff --git a/cub/cub/device/dispatch/tuning/tuning_reduce.cuh b/cub/cub/device/dispatch/tuning/tuning_reduce.cuh
index a87b6b9d6d6..d4719820752 100644
--- a/cub/cub/device/dispatch/tuning/tuning_reduce.cuh
+++ b/cub/cub/device/dispatch/tuning/tuning_reduce.cuh
@@ -79,26 +79,7 @@ CUB_RUNTIME_FUNCTION ReducePolicyWrapper<PolicyT> MakeReducePolicyWrapper(Policy
 template <typename AccumT, typename OffsetT, typename ReductionOpT>
 struct policy_hub
 {
-  struct Policy300 : ChainedPolicy<300, Policy300, Policy300>
-  {
-    static constexpr int threads_per_block  = 256;
-    static constexpr int items_per_thread   = 20;
-    static constexpr int items_per_vec_load = 2;
-
-    // ReducePolicy (GTX670: 154.0 @ 48M 4B items)
-    using ReducePolicy =
-      AgentReducePolicy<threads_per_block,
-                        items_per_thread,
-                        AccumT,
-                        items_per_vec_load,
-                        BLOCK_REDUCE_WARP_REDUCTIONS,
-                        LOAD_DEFAULT>;
-
-    using SingleTilePolicy      = ReducePolicy;
-    using SegmentedReducePolicy = ReducePolicy;
-  };
-
-  struct Policy350 : ChainedPolicy<350, Policy350, Policy300>
+  struct Policy500 : ChainedPolicy<500, Policy500, Policy500>
   {
     static constexpr int threads_per_block  = 256;
     static constexpr int items_per_thread   = 20;
@@ -117,7 +98,7 @@ struct policy_hub
     using SegmentedReducePolicy = ReducePolicy;
   };
 
-  struct Policy600 : ChainedPolicy<600, Policy600, Policy350>
+  struct Policy600 : ChainedPolicy<600, Policy600, Policy500>
   {
     static constexpr int threads_per_block  = 256;
     static constexpr int items_per_thread   = 16;
diff --git a/cub/cub/device/dispatch/tuning/tuning_reduce_by_key.cuh b/cub/cub/device/dispatch/tuning/tuning_reduce_by_key.cuh
index 41fbb2c49a4..a5ad19df8cc 100644
--- a/cub/cub/device/dispatch/tuning/tuning_reduce_by_key.cuh
+++ b/cub/cub/device/dispatch/tuning/tuning_reduce_by_key.cuh
@@ -633,9 +633,9 @@ struct policy_hub
                              default_reduce_by_key_delay_constructor_t<AccumT, int>>;
   };
 
-  struct Policy350
+  struct Policy500
       : DefaultPolicy<LOAD_LDG>
-      , ChainedPolicy<350, Policy350, Policy350>
+      , ChainedPolicy<500, Policy500, Policy500>
   {};
 
   // Use values from tuning if a specialization exists, otherwise pick DefaultPolicy
@@ -651,7 +651,7 @@ struct policy_hub
   template <typename Tuning>
   static auto select_agent_policy(long) -> typename DefaultPolicy<LOAD_DEFAULT>::ReduceByKeyPolicyT;
 
-  struct Policy800 : ChainedPolicy<800, Policy800, Policy350>
+  struct Policy800 : ChainedPolicy<800, Policy800, Policy500>
   {
     using ReduceByKeyPolicyT =
       decltype(select_agent_policy<sm80_tuning<KeyT, AccumT, is_primitive_op<ReductionOpT>()>>(0));
diff --git a/cub/cub/device/dispatch/tuning/tuning_run_length_encode.cuh b/cub/cub/device/dispatch/tuning/tuning_run_length_encode.cuh
index 87631d1199e..d938209dcf2 100644
--- a/cub/cub/device/dispatch/tuning/tuning_run_length_encode.cuh
+++ b/cub/cub/device/dispatch/tuning/tuning_run_length_encode.cuh
@@ -258,10 +258,10 @@ struct policy_hub
                              default_reduce_by_key_delay_constructor_t<LengthT, int>>;
   };
 
-  // SM35
-  struct Policy350
+  // SM50
+  struct Policy500
       : DefaultPolicy<LOAD_LDG>
-      , ChainedPolicy<350, Policy350, Policy350>
+      , ChainedPolicy<500, Policy500, Policy500>
   {};
 
   // Use values from tuning if a specialization exists, otherwise pick the default
@@ -277,7 +277,7 @@ struct policy_hub
   static auto select_agent_policy(long) -> typename DefaultPolicy<LOAD_DEFAULT>::ReduceByKeyPolicyT;
 
   // SM80
-  struct Policy800 : ChainedPolicy<800, Policy800, Policy350>
+  struct Policy800 : ChainedPolicy<800, Policy800, Policy500>
   {
     using ReduceByKeyPolicyT = decltype(select_agent_policy<encode::sm80_tuning<LengthT, KeyT>>(0));
   };
@@ -451,10 +451,10 @@ struct policy_hub
                      default_reduce_by_key_delay_constructor_t<DelayConstructorKey, int>>;
   };
 
-  // SM35
-  struct Policy350
+  // SM50
+  struct Policy500
       : DefaultPolicy<BLOCK_LOAD_DIRECT, int, LOAD_LDG> // TODO(bgruber): I think we want `LengthT` instead of `int`
-      , ChainedPolicy<350, Policy350, Policy350>
+      , ChainedPolicy<500, Policy500, Policy500>
   {};
 
   // Use values from tuning if a specialization exists, otherwise pick the default
@@ -472,7 +472,7 @@ struct policy_hub
     typename DefaultPolicy<BLOCK_LOAD_WARP_TRANSPOSE, LengthT, LOAD_DEFAULT>::RleSweepPolicyT;
 
   // SM80
-  struct Policy800 : ChainedPolicy<800, Policy800, Policy350>
+  struct Policy800 : ChainedPolicy<800, Policy800, Policy500>
   {
     using RleSweepPolicyT = decltype(select_agent_policy<non_trivial_runs::sm80_tuning<LengthT, KeyT>>(0));
   };
diff --git a/cub/cub/device/dispatch/tuning/tuning_scan.cuh b/cub/cub/device/dispatch/tuning/tuning_scan.cuh
index ae0d34ede32..7b076507341 100644
--- a/cub/cub/device/dispatch/tuning/tuning_scan.cuh
+++ b/cub/cub/device/dispatch/tuning/tuning_scan.cuh
@@ -273,13 +273,13 @@ struct policy_hub
   static constexpr BlockStoreAlgorithm scan_transposed_store =
     large_values ? BLOCK_STORE_WARP_TRANSPOSE_TIMESLICED : BLOCK_STORE_WARP_TRANSPOSE;
 
-  struct Policy350 : ChainedPolicy<350, Policy350, Policy350>
+  struct Policy500 : ChainedPolicy<500, Policy500, Policy500>
   {
     // GTX Titan: 29.5B items/s (232.4 GB/s) @ 48M 32-bit T
     using ScanPolicyT =
       AgentScanPolicy<128, 12, AccumT, BLOCK_LOAD_DIRECT, LOAD_CA, BLOCK_STORE_WARP_TRANSPOSE_TIMESLICED, BLOCK_SCAN_RAKING>;
   };
-  struct Policy520 : ChainedPolicy<520, Policy520, Policy350>
+  struct Policy520 : ChainedPolicy<520, Policy520, Policy500>
   {
     // Titan X: 32.47B items/s @ 48M 32-bit T
     using ScanPolicyT =
diff --git a/cub/cub/device/dispatch/tuning/tuning_scan_by_key.cuh b/cub/cub/device/dispatch/tuning/tuning_scan_by_key.cuh
index cdd2468dc38..f8e29201eea 100644
--- a/cub/cub/device/dispatch/tuning/tuning_scan_by_key.cuh
+++ b/cub/cub/device/dispatch/tuning/tuning_scan_by_key.cuh
@@ -717,7 +717,7 @@ struct policy_hub
   static constexpr int max_input_bytes      = static_cast<int>((::cuda::std::max)(sizeof(key_t), sizeof(AccumT)));
   static constexpr int combined_input_bytes = static_cast<int>(sizeof(key_t) + sizeof(AccumT));
 
-  struct Policy350 : ChainedPolicy<350, Policy350, Policy350>
+  struct Policy500 : ChainedPolicy<500, Policy500, Policy500>
   {
     static constexpr int nominal_4b_items_per_thread = 6;
     static constexpr int items_per_thread =
@@ -752,7 +752,7 @@ struct policy_hub
 
   struct Policy520
       : DefaultPolicy<LOAD_CA, AccumT>
-      , ChainedPolicy<520, Policy520, Policy350>
+      , ChainedPolicy<520, Policy520, Policy500>
   {};
 
   // Use values from tuning if a specialization exists, otherwise pick the default
diff --git a/cub/cub/device/dispatch/tuning/tuning_segmented_sort.cuh b/cub/cub/device/dispatch/tuning/tuning_segmented_sort.cuh
index fc442a4f982..308949d0916 100644
--- a/cub/cub/device/dispatch/tuning/tuning_segmented_sort.cuh
+++ b/cub/cub/device/dispatch/tuning/tuning_segmented_sort.cuh
@@ -53,33 +53,7 @@ struct policy_hub
   using DominantT                = ::cuda::std::_If<(sizeof(ValueT) > sizeof(KeyT)), ValueT, KeyT>;
   static constexpr int KEYS_ONLY = ::cuda::std::is_same<ValueT, NullType>::value;
 
-  struct Policy350 : ChainedPolicy<350, Policy350, Policy350>
-  {
-    static constexpr int BLOCK_THREADS          = 128;
-    static constexpr int RADIX_BITS             = sizeof(KeyT) > 1 ? 6 : 4;
-    static constexpr int PARTITIONING_THRESHOLD = 300;
-
-    using LargeSegmentPolicy = AgentRadixSortDownsweepPolicy<
-      BLOCK_THREADS,
-      9,
-      DominantT,
-      BLOCK_LOAD_WARP_TRANSPOSE,
-      LOAD_DEFAULT,
-      RADIX_RANK_MATCH,
-      BLOCK_SCAN_WARP_SCANS,
-      RADIX_BITS>;
-
-    static constexpr int ITEMS_PER_SMALL_THREAD  = Nominal4BItemsToItems<DominantT>(5);
-    static constexpr int ITEMS_PER_MEDIUM_THREAD = Nominal4BItemsToItems<DominantT>(5);
-    using SmallAndMediumSegmentedSortPolicyT     = AgentSmallAndMediumSegmentedSortPolicy<
-          BLOCK_THREADS,
-          // Small policy
-          AgentSubWarpMergeSortPolicy<4, ITEMS_PER_SMALL_THREAD, WARP_LOAD_DIRECT, LOAD_DEFAULT>,
-          // Medium policy
-          AgentSubWarpMergeSortPolicy<32, ITEMS_PER_MEDIUM_THREAD, WARP_LOAD_DIRECT, LOAD_DEFAULT>>;
-  };
-
-  struct Policy500 : ChainedPolicy<500, Policy500, Policy350>
+  struct Policy500 : ChainedPolicy<500, Policy500, Policy500>
   {
     static constexpr int BLOCK_THREADS          = 256;
     static constexpr int RADIX_BITS             = sizeof(KeyT) > 1 ? 6 : 4;
diff --git a/cub/cub/device/dispatch/tuning/tuning_select_if.cuh b/cub/cub/device/dispatch/tuning/tuning_select_if.cuh
index 792b1669fa1..10d22286068 100644
--- a/cub/cub/device/dispatch/tuning/tuning_select_if.cuh
+++ b/cub/cub/device/dispatch/tuning/tuning_select_if.cuh
@@ -566,12 +566,12 @@ struct policy_hub
                           detail::fixed_delay_constructor_t<350, 450>>;
   };
 
-  struct Policy350
+  struct Policy500
       : DefaultPolicy<MayAlias ? LOAD_CA : LOAD_LDG>
-      , ChainedPolicy<350, Policy350, Policy350>
+      , ChainedPolicy<500, Policy500, Policy500>
   {};
 
-  struct Policy800 : ChainedPolicy<800, Policy800, Policy350>
+  struct Policy800 : ChainedPolicy<800, Policy800, Policy500>
   {
     // Use values from tuning if a specialization exists, otherwise pick the default
     template <typename Tuning>
diff --git a/cub/cub/device/dispatch/tuning/tuning_three_way_partition.cuh b/cub/cub/device/dispatch/tuning/tuning_three_way_partition.cuh
index 3645e4b9ed7..08364fe381d 100644
--- a/cub/cub/device/dispatch/tuning/tuning_three_way_partition.cuh
+++ b/cub/cub/device/dispatch/tuning/tuning_three_way_partition.cuh
@@ -239,9 +239,9 @@ struct policy_hub
                                    DelayConstructor>;
   };
 
-  struct Policy350
+  struct Policy500
       : DefaultPolicy<fixed_delay_constructor_t<350, 450>>
-      , ChainedPolicy<350, Policy350, Policy350>
+      , ChainedPolicy<500, Policy500, Policy500>
   {};
 
   // Use values from tuning if a specialization exists, otherwise pick DefaultPolicy
@@ -258,7 +258,7 @@ struct policy_hub
   static auto select_agent_policy(long) -> typename DefaultPolicy<
     default_delay_constructor_t<typename accumulator_pack_t<OffsetT>::pack_t>>::ThreeWayPartitionPolicy;
 
-  struct Policy800 : ChainedPolicy<800, Policy800, Policy350>
+  struct Policy800 : ChainedPolicy<800, Policy800, Policy500>
   {
     using ThreeWayPartitionPolicy = decltype(select_agent_policy<sm80_tuning<InputT, OffsetT>>(0));
   };
diff --git a/cub/cub/device/dispatch/tuning/tuning_unique_by_key.cuh b/cub/cub/device/dispatch/tuning/tuning_unique_by_key.cuh
index f988d6fb29e..0c6b717de2c 100644
--- a/cub/cub/device/dispatch/tuning/tuning_unique_by_key.cuh
+++ b/cub/cub/device/dispatch/tuning/tuning_unique_by_key.cuh
@@ -538,9 +538,9 @@ struct policy_hub
                              detail::default_delay_constructor_t<int>>;
   };
 
-  struct Policy350
+  struct Policy500
       : DefaultPolicy<9, 128>
-      , ChainedPolicy<350, Policy350, Policy350>
+      , ChainedPolicy<500, Policy500, Policy500>
   {};
 
   // Use values from tuning if a specialization exists, otherwise pick the default
@@ -557,7 +557,7 @@ struct policy_hub
 
   struct Policy520
       : DefaultPolicy<11, 64>
-      , ChainedPolicy<520, Policy520, Policy350>
+      , ChainedPolicy<520, Policy520, Policy500>
   {};
 
   struct Policy800 : ChainedPolicy<800, Policy800, Policy520>
diff --git a/cub/test/catch2_test_device_run_length_encode_non_trivial_runs.cu b/cub/test/catch2_test_device_run_length_encode_non_trivial_runs.cu
index db655b73404..12f0467d12b 100644
--- a/cub/test/catch2_test_device_run_length_encode_non_trivial_runs.cu
+++ b/cub/test/catch2_test_device_run_length_encode_non_trivial_runs.cu
@@ -258,13 +258,13 @@ struct device_rle_policy_hub
   static constexpr int threads = 96;
   static constexpr int items   = 15;
 
-  struct Policy350 : cub::ChainedPolicy<350, Policy350, Policy350>
+  struct Policy500 : cub::ChainedPolicy<500, Policy500, Policy500>
   {
     using RleSweepPolicyT = cub::
       AgentRlePolicy<threads, items, cub::BLOCK_LOAD_DIRECT, cub::LOAD_DEFAULT, TimeSlicing, cub::BLOCK_SCAN_WARP_SCANS>;
   };
 
-  using MaxPolicy = Policy350;
+  using MaxPolicy = Policy500;
 };
 
 struct CustomDeviceRunLengthEncode
diff --git a/cub/test/catch2_test_util_device.cu b/cub/test/catch2_test_util_device.cu
index 4c4d10a2ff1..da0eea09eba 100644
--- a/cub/test/catch2_test_util_device.cu
+++ b/cub/test/catch2_test_util_device.cu
@@ -125,9 +125,7 @@ C2H_TEST("PtxVersion returns a value from __CUDA_ARCH_LIST__/NV_TARGET_SM_INTEGE
 struct policy_hub_all
 {
   // for the list of supported architectures, see libcudacxx/include/nv/target
-  GEN_POLICY(350, 350);
-  GEN_POLICY(370, 350);
-  GEN_POLICY(500, 370);
+  GEN_POLICY(500, 500);
   GEN_POLICY(520, 500);
   GEN_POLICY(530, 520);
   GEN_POLICY(600, 530);
@@ -258,8 +256,7 @@ DECLARE_TMPL_LAUNCH_WRAPPER(check_chained_policy_selects_correct_policy,
 
 struct policy_hub_some
 {
-  GEN_POLICY(350, 350);
-  GEN_POLICY(500, 350);
+  GEN_POLICY(500, 500);
   GEN_POLICY(700, 500);
   GEN_POLICY(900, 700);
   GEN_POLICY(2000, 900); // non-existing architecture, just to test
@@ -268,30 +265,30 @@ struct policy_hub_some
 
 struct policy_hub_few
 {
-  GEN_POLICY(350, 350);
-  GEN_POLICY(860, 350);
+  GEN_POLICY(500, 500);
+  GEN_POLICY(860, 500);
   GEN_POLICY(2000, 860); // non-existing architecture, just to test
   using max_policy = policy2000;
 };
 
 struct policy_hub_minimal
 {
-  GEN_POLICY(350, 350);
-  using max_policy = policy350;
+  GEN_POLICY(500, 500);
+  using max_policy = policy500;
 };
 
 C2H_TEST("ChainedPolicy invokes correct policy", "[util][dispatch]")
 {
   SECTION("policy_hub_some")
   {
-    check_wrapper_some<policy_hub_some, 5>(::cuda::std::array<int, 5>{350, 500, 700, 900, 2000});
+    check_wrapper_some<policy_hub_some, 4>(::cuda::std::array<int, 4>{500, 700, 900, 2000});
   }
   SECTION("policy_hub_few")
   {
-    check_wrapper_some<policy_hub_few, 3>(::cuda::std::array<int, 3>{350, 860, 2000});
+    check_wrapper_some<policy_hub_few, 3>(::cuda::std::array<int, 3>{500, 860, 2000});
   }
   SECTION("policy_hub_minimal")
   {
-    check_wrapper_some<policy_hub_minimal, 1>(::cuda::std::array<int, 1>{350});
+    check_wrapper_some<policy_hub_minimal, 1>(::cuda::std::array<int, 1>{500});
   }
 }
diff --git a/cub/test/catch2_test_vsmem.cu b/cub/test/catch2_test_vsmem.cu
index 6b16bde7fa9..557f2c152d0 100644
--- a/cub/test/catch2_test_vsmem.cu
+++ b/cub/test/catch2_test_vsmem.cu
@@ -198,7 +198,7 @@ struct device_dummy_algorithm_policy_t
 
   static constexpr int FALLBACK_BLOCK_THREADS = 64;
 
-  struct policy_350 : cub::ChainedPolicy<350, policy_350, policy_350>
+  struct policy_500 : cub::ChainedPolicy<500, policy_500, policy_500>
   {
     using DummyAlgorithmPolicy = agent_dummy_algorithm_policy_t<256, cub::Nominal4BItemsToItems<item_t>(17)>;
 
@@ -208,7 +208,7 @@ struct device_dummy_algorithm_policy_t
   };
 
   /// MaxPolicy
-  using max_policy_t = policy_350;
+  using max_policy_t = policy_500;
 };
 
 //----------------------------------------------------------------------------
@@ -422,9 +422,9 @@ C2H_TEST("Virtual shared memory works within algorithms", "[util][vsmem]", type_
   c2h::gen(C2H_SEED(1), in);
 
   // Query default and fallback policies and agents so we can confirm vsmem
-  using default_policy_t  = typename device_dummy_algorithm_policy_t<item_t*>::policy_350::DummyAlgorithmPolicy;
+  using default_policy_t  = typename device_dummy_algorithm_policy_t<item_t*>::policy_500::DummyAlgorithmPolicy;
   using default_agent_t   = agent_dummy_algorithm_t<default_policy_t, item_t*, item_t*, offset_t>;
-  using fallback_policy_t = typename device_dummy_algorithm_policy_t<item_t*>::policy_350::FallbackDummyAlgorithmPolicy;
+  using fallback_policy_t = typename device_dummy_algorithm_policy_t<item_t*>::policy_500::FallbackDummyAlgorithmPolicy;
   using fallback_agent_t  = agent_dummy_algorithm_t<fallback_policy_t, item_t*, item_t*, offset_t>;
 
   // Get the information as it is expected from the vsmem helper to work as expected
diff --git a/docs/cub/developer_overview.rst b/docs/cub/developer_overview.rst
index 4cc639e27fb..8b31dab6283 100644
--- a/docs/cub/developer_overview.rst
+++ b/docs/cub/developer_overview.rst
@@ -625,14 +625,14 @@ Finally, the tuning policy hub looks like:
     struct policy_hub {
       // TuningRelevantParams... could be used for decision making, like element types used, iterator category, etc.
 
-      // for SM35
-      struct Policy350 : ChainedPolicy<350, Policy350, Policy300> {
+      // for SM50
+      struct Policy500 : ChainedPolicy<500, Policy500, Policy500> {
         using AlgorithmPolicy = AgentAlgorithmPolicy<256, 20, BLOCK_LOAD_DIRECT, LOAD_LDG>;
         // ... additional policies may exist, often one per agent
       };
 
       // for SM60
-      struct Policy600 : ChainedPolicy<600, Policy600, Policy350> {
+      struct Policy600 : ChainedPolicy<600, Policy600, Policy500> {
         using AlgorithmPolicy = AgentAlgorithmPolicy<256, 16, BLOCK_LOAD_DIRECT, LOAD_LDG>;
       };
 
diff --git a/docs/repo.toml b/docs/repo.toml
index 999d62a8f20..7ff29fd6eba 100644
--- a/docs/repo.toml
+++ b/docs/repo.toml
@@ -115,7 +115,7 @@ doxygen_aliases = [
   "smemstorage{1}=The operations exposed by \\1 require a temporary memory allocation of this nested type for thread communication. This opaque storage can be allocated directly using the ``__shared__`` keyword. Alternatively, it can be aliased to externally allocated memory (shared or global) or ``union``'d with other storage allocation types to facilitate memory reuse.",
   "granularity=Efficiency is increased with increased granularity ``ITEMS_PER_THREAD``. Performance is also typically increased until the additional register pressure or shared memory allocation size causes SM occupancy to fall too low. Consider variants of ``cub::BlockLoad`` for efficiently gathering a :ref:`blocked arrangement <flexible-data-arrangement>` of elements across threads.",
   "blocksize=The number of threads in the block is a multiple of the architecture's warp size",
-  "ptxversion=The PTX compute capability for which to to specialize this collective, formatted as per the ``__CUDA_ARCH__`` macro (e.g., 350 for sm_35). Useful for determining the collective's storage requirements for a given device from the host. (Default: the value of ``__CUDA_ARCH__`` during the current compiler pass)",
+  "ptxversion=The PTX compute capability for which to to specialize this collective, formatted as per the ``__CUDA_ARCH__`` macro (e.g., 750 for sm_75). Useful for determining the collective's storage requirements for a given device from the host. (Default: the value of ``__CUDA_ARCH__`` during the current compiler pass)",
   "blockcollective{1}=Every thread in the block uses the \\1 class by first specializing the \\1 type, then instantiating an instance with parameters for communication, and finally invoking one or more collective member functions.",
   "warpcollective{1}=Every thread in the warp uses the \\1 class by first specializing the \\1 type, then instantiating an instance with parameters for communication, and finally invoking or more collective member functions.",
   "devicestorage=When ``d_temp_storage`` is ``nullptr``, no work is done and the required allocation size is returned in ``temp_storage_bytes``.",
diff --git a/libcudacxx/test/libcudacxx/cuda/test_platform.pass.cpp b/libcudacxx/test/libcudacxx/cuda/test_platform.pass.cpp
index 499c57a9a7e..25181f48a33 100644
--- a/libcudacxx/test/libcudacxx/cuda/test_platform.pass.cpp
+++ b/libcudacxx/test/libcudacxx/cuda/test_platform.pass.cpp
@@ -65,10 +65,6 @@ __host__ __device__ void test()
     (static_assert(arch_val >= 520, "cuda arch expected 520");),
     NV_PROVIDES_SM_50,
     (static_assert(arch_val >= 500, "cuda arch expected 500");),
-    NV_PROVIDES_SM_37,
-    (static_assert(arch_val >= 370, "cuda arch expected 370");),
-    NV_PROVIDES_SM_35,
-    (static_assert(arch_val >= 350, "cuda arch expected 350");),
     NV_IS_HOST,
     (static_assert(arch_val == 0, "cuda arch expected 0");))
 
@@ -98,10 +94,6 @@ __host__ __device__ void test()
     (static_assert(arch_val == 520, "cuda arch expected 520");),
     NV_IS_EXACTLY_SM_50,
     (static_assert(arch_val == 500, "cuda arch expected 500");),
-    NV_IS_EXACTLY_SM_37,
-    (static_assert(arch_val == 370, "cuda arch expected 370");),
-    NV_IS_EXACTLY_SM_35,
-    (static_assert(arch_val == 350, "cuda arch expected 350");),
     NV_IS_HOST,
     (static_assert(arch_val == 0, "cuda arch expected 0");))
 
@@ -158,10 +150,6 @@ __host__ __device__ void test()
     (invoke_count += 1; invoke_count += threadIdx.x;),
     NV_PROVIDES_SM_50,
     (invoke_count += 1; invoke_count += threadIdx.x;),
-    NV_PROVIDES_SM_37,
-    (invoke_count += 1; invoke_count += threadIdx.x;),
-    NV_PROVIDES_SM_35,
-    (invoke_count += 1; invoke_count += threadIdx.x;),
     NV_IS_HOST,
     (invoke_count += 1;))
 
@@ -188,10 +176,6 @@ __host__ __device__ void test()
     (invoke_count += 1; invoke_count += threadIdx.x;),
     NV_IS_EXACTLY_SM_50,
     (invoke_count += 1; invoke_count += threadIdx.x;),
-    NV_IS_EXACTLY_SM_37,
-    (invoke_count += 1; invoke_count += threadIdx.x;),
-    NV_IS_EXACTLY_SM_35,
-    (invoke_count += 1; invoke_count += threadIdx.x;),
     NV_IS_HOST,
     (invoke_count += 1;))
 
@@ -252,10 +236,6 @@ void test()
     (static_assert(arch_val == 520, "cuda arch expected 520");),
     NV_PROVIDES_SM_50,
     (static_assert(arch_val == 500, "cuda arch expected 500");),
-    NV_PROVIDES_SM_37,
-    (static_assert(arch_val == 370, "cuda arch expected 370");),
-    NV_PROVIDES_SM_35,
-    (static_assert(arch_val == 350, "cuda arch expected 350");),
     NV_IS_HOST,
     (static_assert(arch_val == 0, "cuda arch expected 0");))
 
@@ -281,10 +261,6 @@ void test()
     (static_assert(arch_val == 520, "cuda arch expected 520");),
     NV_IS_EXACTLY_SM_50,
     (static_assert(arch_val == 500, "cuda arch expected 500");),
-    NV_IS_EXACTLY_SM_37,
-    (static_assert(arch_val == 370, "cuda arch expected 370");),
-    NV_IS_EXACTLY_SM_35,
-    (static_assert(arch_val == 350, "cuda arch expected 350");),
     NV_IS_HOST,
     (static_assert(arch_val == 0, "cuda arch expected 0");))
 
diff --git a/libcudacxx/test/support/concurrent_agents.h b/libcudacxx/test/support/concurrent_agents.h
index 6b57b3531a0..6419613a5d8 100644
--- a/libcudacxx/test/support/concurrent_agents.h
+++ b/libcudacxx/test/support/concurrent_agents.h
@@ -13,10 +13,6 @@
 
 #ifndef __CUDA_ARCH__
 #  include <thread>
-#else
-#  if __CUDA_ARCH__ < 350
-#    error "This test requires CUDA dynamic parallelism to work."
-#  endif
 #endif
 
 #include <cuda/std/cassert>
diff --git a/thrust/thrust/system/cuda/detail/core/util.h b/thrust/thrust/system/cuda/detail/core/util.h
index a3c8994d777..94a7e750aeb 100644
--- a/thrust/thrust/system/cuda/detail/core/util.h
+++ b/thrust/thrust/system/cuda/detail/core/util.h
@@ -64,32 +64,17 @@ namespace core
 #  if (__NVCOMPILER_CUDA_ARCH__ >= 600)
 // deprecated [since 2.8]
 #    define THRUST_TUNING_ARCH sm60
-#  elif (__NVCOMPILER_CUDA_ARCH__ >= 520)
-// deprecated [since 2.8]
-#    define THRUST_TUNING_ARCH sm52
-#  elif (__NVCOMPILER_CUDA_ARCH__ >= 350)
-// deprecated [since 2.8]
-#    define THRUST_TUNING_ARCH sm35
 #  else
 // deprecated [since 2.8]
-#    define THRUST_TUNING_ARCH sm30
+#    define THRUST_TUNING_ARCH sm52
 #  endif
 #else
 #  if (__CUDA_ARCH__ >= 600)
 // deprecated [since 2.8]
 #    define THRUST_TUNING_ARCH sm60
-#  elif (__CUDA_ARCH__ >= 520)
+#  else
 // deprecated [since 2.8]
 #    define THRUST_TUNING_ARCH sm52
-#  elif (__CUDA_ARCH__ >= 350)
-// deprecated [since 2.8]
-#    define THRUST_TUNING_ARCH sm35
-#  elif (__CUDA_ARCH__ >= 300)
-// deprecated [since 2.8]
-#    define THRUST_TUNING_ARCH sm30
-#  elif !defined(__CUDA_ARCH__)
-// deprecated [since 2.8]
-#    define THRUST_TUNING_ARCH sm30
 #  endif
 #endif
 
@@ -101,22 +86,7 @@ struct typelist;
 
 // supported SM arch
 // ---------------------
-struct sm30
-{
-  enum
-  {
-    ver      = 300,
-    warpSize = 32
-  };
-};
-struct sm35
-{
-  enum
-  {
-    ver      = 350,
-    warpSize = 32
-  };
-};
+
 struct sm52
 {
   enum
@@ -137,7 +107,7 @@ struct sm60
 // list of sm, checked from left to right order
 // the rightmost is the lowest sm arch supported
 // --------------------------------------------
-using sm_list = typelist<sm60, sm52, sm35, sm30>;
+using sm_list = typelist<sm60, sm52>;
 
 // lowest supported SM arch
 // --------------------------------------------------------------------------
@@ -784,8 +754,6 @@ THRUST_RUNTIME_FUNCTION cudaError_t alias_storage(
 }
 
 } // namespace core
-using core::sm30;
-using core::sm35;
 using core::sm52;
 using core::sm60;
 } // namespace cuda_cub
diff --git a/thrust/thrust/system/cuda/detail/reduce.h b/thrust/thrust/system/cuda/detail/reduce.h
index 443063fb3b4..3787ab62367 100644
--- a/thrust/thrust/system/cuda/detail/reduce.h
+++ b/thrust/thrust/system/cuda/detail/reduce.h
@@ -109,7 +109,7 @@ template <class, class>
 struct Tuning;
 
 template <class T>
-struct Tuning<sm30, T>
+struct Tuning<sm52, T>
 {
   enum
   {
@@ -119,18 +119,6 @@ struct Tuning<sm30, T>
     SCALE_FACTOR_1B = sizeof(T),
   };
 
-  using type =
-    PtxPolicy<256,
-              (((20 / SCALE_FACTOR_4B) > (1)) ? (20 / SCALE_FACTOR_4B) : (1)),
-              2,
-              cub::BLOCK_REDUCE_WARP_REDUCTIONS,
-              cub::LOAD_DEFAULT,
-              cub::GRID_MAPPING_RAKE>;
-}; // Tuning sm30
-
-template <class T>
-struct Tuning<sm35, T> : Tuning<sm30, T>
-{
   // ReducePolicy1B (GTX Titan: 228.7 GB/s @ 192M 1B items)
   using ReducePolicy1B =
     PtxPolicy<128,
@@ -150,7 +138,7 @@ struct Tuning<sm35, T> : Tuning<sm30, T>
               cub::GRID_MAPPING_DYNAMIC>;
 
   using type = ::cuda::std::conditional_t<(sizeof(T) < 4), ReducePolicy1B, ReducePolicy4B>;
-}; // Tuning sm35
+}; // Tuning sm52
 
 template <class InputIt, class OutputIt, class T, class Size, class ReductionOp>
 struct ReduceAgent
diff --git a/thrust/thrust/system/cuda/detail/reduce_by_key.h b/thrust/thrust/system/cuda/detail/reduce_by_key.h
index cc59c98ab2c..ae1f0ffab96 100644
--- a/thrust/thrust/system/cuda/detail/reduce_by_key.h
+++ b/thrust/thrust/system/cuda/detail/reduce_by_key.h
@@ -115,54 +115,7 @@ template <class Arch, class Key, class Value>
 struct Tuning;
 
 template <class Key, class Value>
-struct Tuning<sm30, Key, Value>
-{
-  enum
-  {
-    MAX_INPUT_BYTES      = mpl::max<size_t, sizeof(Key), sizeof(Value)>::value,
-    COMBINED_INPUT_BYTES = sizeof(Key) + sizeof(Value),
-
-    NOMINAL_4B_ITEMS_PER_THREAD = 6,
-
-    ITEMS_PER_THREAD =
-      mpl::min<int,
-               NOMINAL_4B_ITEMS_PER_THREAD,
-               mpl::max<int,
-                        1,
-                        static_cast<int>(((NOMINAL_4B_ITEMS_PER_THREAD * 8) + COMBINED_INPUT_BYTES - 1)
-                                         / COMBINED_INPUT_BYTES)>::value>::value,
-  };
-
-  using type =
-    PtxPolicy<128, ITEMS_PER_THREAD, cub::BLOCK_LOAD_WARP_TRANSPOSE, cub::LOAD_DEFAULT, cub::BLOCK_SCAN_WARP_SCANS>;
-}; // Tuning sm30
-
-template <class Key, class Value>
-struct Tuning<sm35, Key, Value> : Tuning<sm30, Key, Value>
-{
-  enum
-  {
-    MAX_INPUT_BYTES      = mpl::max<size_t, sizeof(Key), sizeof(Value)>::value,
-    COMBINED_INPUT_BYTES = sizeof(Key) + sizeof(Value),
-
-    NOMINAL_4B_ITEMS_PER_THREAD = 6,
-
-    ITEMS_PER_THREAD =
-      (MAX_INPUT_BYTES <= 8)
-        ? 6
-        : mpl::min<
-            int,
-            NOMINAL_4B_ITEMS_PER_THREAD,
-            mpl::max<int, 1, ((NOMINAL_4B_ITEMS_PER_THREAD * 8) + COMBINED_INPUT_BYTES - 1) / COMBINED_INPUT_BYTES>::
-              value>::value,
-  };
-
-  using type =
-    PtxPolicy<128, ITEMS_PER_THREAD, cub::BLOCK_LOAD_WARP_TRANSPOSE, cub::LOAD_LDG, cub::BLOCK_SCAN_WARP_SCANS>;
-}; // Tuning sm35
-
-template <class Key, class Value>
-struct Tuning<sm52, Key, Value> : Tuning<sm30, Key, Value>
+struct Tuning<sm52, Key, Value>
 {
   enum
   {
diff --git a/thrust/thrust/system/cuda/detail/set_operations.h b/thrust/thrust/system/cuda/detail/set_operations.h
index 0ef80c0fb2d..7a267080bf8 100644
--- a/thrust/thrust/system/cuda/detail/set_operations.h
+++ b/thrust/thrust/system/cuda/detail/set_operations.h
@@ -221,27 +221,6 @@ struct Tuning;
 
 namespace mpl = thrust::detail::mpl::math;
 
-template <class T, class U>
-struct Tuning<sm30, T, U>
-{
-  enum
-  {
-    MAX_INPUT_BYTES             = mpl::max<size_t, sizeof(T), sizeof(U)>::value,
-    COMBINED_INPUT_BYTES        = sizeof(T), // + sizeof(Value),
-    NOMINAL_4B_ITEMS_PER_THREAD = 7,
-    ITEMS_PER_THREAD =
-      mpl::min<int,
-               NOMINAL_4B_ITEMS_PER_THREAD,
-               mpl::max<int,
-                        1,
-                        static_cast<int>(((NOMINAL_4B_ITEMS_PER_THREAD * 4) + COMBINED_INPUT_BYTES - 1)
-                                         / COMBINED_INPUT_BYTES)>::value>::value,
-  };
-
-  using type =
-    PtxPolicy<128, ITEMS_PER_THREAD, cub::BLOCK_LOAD_WARP_TRANSPOSE, cub::LOAD_DEFAULT, cub::BLOCK_SCAN_WARP_SCANS>;
-}; // tuning sm30
-
 template <class T, class U>
 struct Tuning<sm52, T, U>
 {
diff --git a/thrust/thrust/system/cuda/detail/unique.h b/thrust/thrust/system/cuda/detail/unique.h
index b8e408254cb..ac94017758b 100644
--- a/thrust/thrust/system/cuda/detail/unique.h
+++ b/thrust/thrust/system/cuda/detail/unique.h
@@ -137,36 +137,6 @@ struct Tuning<sm52, T>
     PtxPolicy<64, ITEMS_PER_THREAD, cub::BLOCK_LOAD_WARP_TRANSPOSE, cub::LOAD_LDG, cub::BLOCK_SCAN_WARP_SCANS>;
 }; // Tuning for sm52
 
-template <class T>
-struct Tuning<sm35, T>
-{
-  const static int INPUT_SIZE = sizeof(T);
-  enum
-  {
-    NOMINAL_4B_ITEMS_PER_THREAD = 9,
-    //
-    ITEMS_PER_THREAD = items_per_thread<T, NOMINAL_4B_ITEMS_PER_THREAD>::value
-  };
-
-  using type =
-    PtxPolicy<128, ITEMS_PER_THREAD, cub::BLOCK_LOAD_WARP_TRANSPOSE, cub::LOAD_LDG, cub::BLOCK_SCAN_WARP_SCANS>;
-}; // Tuning for sm35
-
-template <class T>
-struct Tuning<sm30, T>
-{
-  const static int INPUT_SIZE = sizeof(T);
-  enum
-  {
-    NOMINAL_4B_ITEMS_PER_THREAD = 7,
-    //
-    ITEMS_PER_THREAD = items_per_thread<T, NOMINAL_4B_ITEMS_PER_THREAD>::value
-  };
-
-  using type =
-    PtxPolicy<128, ITEMS_PER_THREAD, cub::BLOCK_LOAD_WARP_TRANSPOSE, cub::LOAD_DEFAULT, cub::BLOCK_SCAN_WARP_SCANS>;
-}; // Tuning for sm30
-
 template <class ItemsIt, class ItemsOutputIt, class BinaryPred, class Size, class NumSelectedOutIt>
 struct UniqueAgent
 {

From d21e0c9804ad63d23950c8b0a2462e5b7ebc8701 Mon Sep 17 00:00:00 2001
From: Bernhard Manfred Gruber <bernhardmgruber@gmail.com>
Date: Wed, 29 Jan 2025 22:52:12 +0100
Subject: [PATCH 09/33] PTX: Update generated files with Blackwell instructions
 (#3568)

* ptx: Update existing instructions
* ptx: Add new instructions
* Fix returning error out values
See:
- https://gitlab-master.nvidia.com/CCCL/libcuda-ptx/-/merge_requests/74
- https://gitlab-master.nvidia.com/CCCL/libcuda-ptx/-/merge_requests/73
* ptx: Fix out var declaration
See  https://gitlab-master.nvidia.com/CCCL/libcuda-ptx/-/merge_requests/75
* mbarrier.{test,try}_wait: Fix test. Wrong files were included.
* docs: Fix special registers include
* Allow non-included documentation pages
* Workaround NVRTC

Co-authored-by: Allard Hendriksen <ahendriksen@nvidia.com>
---
 .../generated/barrier_cluster_aligned.rst     |   63 +
 .../generated/clusterlaunchcontrol.rst        |   68 +
 .../instructions/generated/cp_async_bulk.rst  |   38 +-
 .../generated/cp_async_bulk_multicast.rst     |    2 +-
 .../generated/cp_async_bulk_tensor.rst        |  280 +-
 .../cp_async_bulk_tensor_gather_scatter.rst   |  124 +
 .../cp_async_bulk_tensor_multicast.rst        |  200 +-
 .../generated/cp_async_mbarrier_arrive.rst    |   11 +
 .../cp_async_mbarrier_arrive_noinc.rst        |   11 +
 .../generated/cp_reduce_async_bulk.rst        |    6 +-
 .../ptx/instructions/generated/elect_sync.rst |   11 +
 .../ptx/instructions/generated/fence.rst      |  170 +-
 .../generated/fence_proxy_async.rst           |    6 +-
 ...ence_proxy_async_generic_sync_restrict.rst |   30 +
 .../generated/fence_sync_restrict.rst         |   30 +
 .../{special_registers.rst => get_sreg.rst}   |   99 +-
 .../ptx/instructions/generated/getctarank.rst |    2 +-
 .../ptx/instructions/generated/mapa.rst       |   14 +
 .../generated/mbarrier_arrive.rst             |  105 +-
 .../generated/mbarrier_arrive_expect_tx.rst   |   54 +-
 .../generated/mbarrier_test_wait.rst          |   34 +-
 .../generated/mbarrier_test_wait_parity.rst   |   34 +-
 .../generated/mbarrier_try_wait.rst           |   70 +-
 .../generated/mbarrier_try_wait_parity.rst    |   70 +-
 .../generated/multimem_ld_reduce.rst          | 2396 ++++++
 .../instructions/generated/multimem_red.rst   | 2306 ++++++
 .../instructions/generated/multimem_st.rst    |  250 +
 .../ptx/instructions/generated/red_async.rst  |   32 +-
 .../ptx/instructions/generated/st_async.rst   |   10 +-
 .../ptx/instructions/generated/st_bulk.rst    |   13 +
 .../instructions/generated/tcgen05_alloc.rst  |   70 +
 .../instructions/generated/tcgen05_commit.rst |   48 +
 .../ptx/instructions/generated/tcgen05_cp.rst |  434 ++
 .../instructions/generated/tcgen05_fence.rst  |   18 +
 .../ptx/instructions/generated/tcgen05_ld.rst |  758 ++
 .../instructions/generated/tcgen05_mma.rst    | 2378 ++++++
 .../instructions/generated/tcgen05_mma_ws.rst | 4482 ++++++++++++
 .../instructions/generated/tcgen05_shift.rst  |   24 +
 .../ptx/instructions/generated/tcgen05_st.rst |  758 ++
 .../instructions/generated/tcgen05_wait.rst   |   18 +
 .../generated/tensormap_replace.rst           |  114 +-
 .../ptx/instructions/special_registers.rst    |    2 +-
 docs/repo.toml                                |    2 +-
 .../instructions/generated/barrier_cluster.h  |   66 +-
 .../generated/barrier_cluster_aligned.h       |  130 +
 .../generated/clusterlaunchcontrol.h          |  240 +
 .../instructions/generated/cp_async_bulk.h    |  153 +-
 .../generated/cp_async_bulk_commit_group.h    |   12 +-
 .../generated/cp_async_bulk_multicast.h       |   35 +-
 .../generated/cp_async_bulk_tensor.h          |  849 ++-
 .../cp_async_bulk_tensor_gather_scatter.h     |  288 +
 .../cp_async_bulk_tensor_multicast.h          |  515 +-
 .../generated/cp_async_bulk_wait_group.h      |   24 +-
 .../generated/cp_async_mbarrier_arrive.h      |   26 +
 .../cp_async_mbarrier_arrive_noinc.h          |   26 +
 .../generated/cp_reduce_async_bulk.h          |  944 +--
 .../generated/cp_reduce_async_bulk_bf16.h     |   78 +-
 .../generated/cp_reduce_async_bulk_f16.h      |   78 +-
 .../generated/cp_reduce_async_bulk_tensor.h   |  788 +-
 .../__ptx/instructions/generated/elect_sync.h |   36 +
 .../cuda/__ptx/instructions/generated/fence.h |  224 +-
 .../generated/fence_mbarrier_init.h           |   16 +-
 .../generated/fence_proxy_alias.h             |   12 +-
 .../generated/fence_proxy_async.h             |   44 +-
 .../fence_proxy_async_generic_sync_restrict.h |   62 +
 .../generated/fence_proxy_tensormap_generic.h |   96 +-
 .../generated/fence_sync_restrict.h           |   62 +
 .../__ptx/instructions/generated/get_sreg.h   |  506 +-
 .../__ptx/instructions/generated/getctarank.h |   21 +-
 .../cuda/__ptx/instructions/generated/mapa.h  |   33 +
 .../instructions/generated/mbarrier_arrive.h  |  338 +-
 .../generated/mbarrier_arrive_expect_tx.h     |  153 +-
 .../generated/mbarrier_arrive_no_complete.h   |   22 +-
 .../generated/mbarrier_expect_tx.h            |   94 +
 .../instructions/generated/mbarrier_init.h    |   12 +-
 .../generated/mbarrier_test_wait.h            |  133 +-
 .../generated/mbarrier_test_wait_parity.h     |  132 +-
 .../generated/mbarrier_try_wait.h             |  278 +-
 .../generated/mbarrier_try_wait_parity.h      |  278 +-
 .../generated/multimem_ld_reduce.h            | 2148 ++++++
 .../instructions/generated/multimem_red.h     | 1272 ++++
 .../instructions/generated/multimem_st.h      |  186 +
 .../__ptx/instructions/generated/red_async.h  |  335 +-
 .../__ptx/instructions/generated/st_async.h   |  118 +-
 .../__ptx/instructions/generated/st_bulk.h    |   31 +
 .../instructions/generated/tcgen05_alloc.h    |  105 +
 .../instructions/generated/tcgen05_commit.h   |   81 +
 .../__ptx/instructions/generated/tcgen05_cp.h |  612 ++
 .../instructions/generated/tcgen05_fence.h    |   44 +
 .../__ptx/instructions/generated/tcgen05_ld.h | 4446 ++++++++++++
 .../instructions/generated/tcgen05_mma.h      | 3842 ++++++++++
 .../instructions/generated/tcgen05_mma_ws.h   | 6438 +++++++++++++++++
 .../instructions/generated/tcgen05_shift.h    |   36 +
 .../__ptx/instructions/generated/tcgen05_st.h | 4554 ++++++++++++
 .../instructions/generated/tcgen05_wait.h     |   44 +
 .../generated/tensormap_cp_fenceproxy.h       |   68 +-
 .../generated/tensormap_replace.h             |  630 +-
 .../ptx/generated/barrier_cluster_aligned.h   |   61 +
 .../cuda/ptx/generated/clusterlaunchcontrol.h |   84 +
 .../cuda/ptx/generated/cp_async_bulk.h        |   29 +-
 .../ptx/generated/cp_async_bulk_multicast.h   |   28 +-
 .../cuda/ptx/generated/cp_async_bulk_tensor.h |  325 +-
 .../cp_async_bulk_tensor_gather_scatter.h     |  180 +
 .../cp_async_bulk_tensor_multicast.h          |  405 +-
 .../ptx/generated/cp_async_mbarrier_arrive.h  |   26 +
 .../cp_async_mbarrier_arrive_noinc.h          |   26 +
 .../cuda/ptx/generated/elect_sync.h           |   26 +
 .../libcudacxx/cuda/ptx/generated/fence.h     |   64 +-
 .../fence_proxy_async_generic_sync_restrict.h |   38 +
 .../cuda/ptx/generated/fence_sync_restrict.h  |   38 +
 .../test/libcudacxx/cuda/ptx/generated/mapa.h |   27 +
 .../cuda/ptx/generated/mbarrier_arrive.h      |   56 +
 .../ptx/generated/mbarrier_arrive_expect_tx.h |   29 +
 .../cuda/ptx/generated/mbarrier_expect_tx.h   |   50 +
 .../cuda/ptx/generated/mbarrier_test_wait.h   |   55 +
 .../ptx/generated/mbarrier_test_wait_parity.h |   55 +
 .../cuda/ptx/generated/mbarrier_try_wait.h    |   31 +
 .../ptx/generated/mbarrier_try_wait_parity.h  |   32 +
 .../cuda/ptx/generated/mbarrier_wait.h        |   24 -
 .../cuda/ptx/generated/mbarrier_wait_parity.h |   24 -
 .../cuda/ptx/generated/multimem_ld_reduce.h   | 1020 +++
 .../cuda/ptx/generated/multimem_red.h         |  840 +++
 .../cuda/ptx/generated/multimem_st.h          |  110 +
 .../libcudacxx/cuda/ptx/generated/st_bulk.h   |   26 +
 .../cuda/ptx/generated/tcgen05_alloc.h        |   81 +
 .../cuda/ptx/generated/tcgen05_commit.h       |   62 +
 .../cuda/ptx/generated/tcgen05_cp.h           |  396 +
 .../cuda/ptx/generated/tcgen05_fence.h        |   44 +
 .../cuda/ptx/generated/tcgen05_ld.h           | 1012 +++
 .../cuda/ptx/generated/tcgen05_mma.h          | 2928 ++++++++
 .../cuda/ptx/generated/tcgen05_mma_ws.h       | 3570 +++++++++
 .../cuda/ptx/generated/tcgen05_shift.h        |   39 +
 .../cuda/ptx/generated/tcgen05_st.h           | 1012 +++
 .../cuda/ptx/generated/tcgen05_wait.h         |   40 +
 .../cuda/ptx/generated/tensormap_replace.h    |  390 +-
 .../libcudacxx/cuda/ptx/nvrtc_workaround.h    |   34 +
 .../ptx/ptx.barrier.cluster.compile.pass.cpp  |    2 +
 ...p.async.bulk.commit_group.compile.pass.cpp |    2 +
 .../ptx/ptx.cp.async.bulk.compile.pass.cpp    |    2 +
 ...x.cp.async.bulk.multicast.compile.pass.cpp |    2 +
 .../ptx.cp.async.bulk.tensor.compile.pass.cpp |    2 +
 ...ync.bulk.tensor.multicast.compile.pass.cpp |    2 +
 ....cp.async.bulk.wait_group.compile.pass.cpp |    2 +
 .../ptx.cp.reduce.async.bulk.compile.pass.cpp |    2 +
 ....reduce.async.bulk.tensor.compile.pass.cpp |    2 +
 .../cuda/ptx/ptx.fence.compile.pass.cpp       |    2 +
 .../cuda/ptx/ptx.get_sreg.compile.pass.cpp    |    2 +
 .../cuda/ptx/ptx.getctarank.compile.pass.cpp  |    2 +
 .../ptx/ptx.mbarrier.arrive.compile.pass.cpp  |    2 +
 .../ptx/ptx.mbarrier.init.compile.pass.cpp    |    2 +
 .../ptx/ptx.mbarrier.wait.compile.pass.cpp    |    6 +-
 .../cuda/ptx/ptx.red.async.compile.pass.cpp   |    2 +
 .../cuda/ptx/ptx.st.async.compile.pass.cpp    |    2 +
 ...x.tensormap.cp_fenceproxy.compile.pass.cpp |    2 +
 .../ptx.tensormap.replace.compile.pass.cpp    |    2 +
 155 files changed, 58115 insertions(+), 2683 deletions(-)
 create mode 100644 docs/libcudacxx/ptx/instructions/generated/barrier_cluster_aligned.rst
 create mode 100644 docs/libcudacxx/ptx/instructions/generated/clusterlaunchcontrol.rst
 create mode 100644 docs/libcudacxx/ptx/instructions/generated/cp_async_bulk_tensor_gather_scatter.rst
 create mode 100644 docs/libcudacxx/ptx/instructions/generated/cp_async_mbarrier_arrive.rst
 create mode 100644 docs/libcudacxx/ptx/instructions/generated/cp_async_mbarrier_arrive_noinc.rst
 create mode 100644 docs/libcudacxx/ptx/instructions/generated/elect_sync.rst
 create mode 100644 docs/libcudacxx/ptx/instructions/generated/fence_proxy_async_generic_sync_restrict.rst
 create mode 100644 docs/libcudacxx/ptx/instructions/generated/fence_sync_restrict.rst
 rename docs/libcudacxx/ptx/instructions/generated/{special_registers.rst => get_sreg.rst} (83%)
 create mode 100644 docs/libcudacxx/ptx/instructions/generated/mapa.rst
 create mode 100644 docs/libcudacxx/ptx/instructions/generated/multimem_ld_reduce.rst
 create mode 100644 docs/libcudacxx/ptx/instructions/generated/multimem_red.rst
 create mode 100644 docs/libcudacxx/ptx/instructions/generated/multimem_st.rst
 create mode 100644 docs/libcudacxx/ptx/instructions/generated/st_bulk.rst
 create mode 100644 docs/libcudacxx/ptx/instructions/generated/tcgen05_alloc.rst
 create mode 100644 docs/libcudacxx/ptx/instructions/generated/tcgen05_commit.rst
 create mode 100644 docs/libcudacxx/ptx/instructions/generated/tcgen05_cp.rst
 create mode 100644 docs/libcudacxx/ptx/instructions/generated/tcgen05_fence.rst
 create mode 100644 docs/libcudacxx/ptx/instructions/generated/tcgen05_ld.rst
 create mode 100644 docs/libcudacxx/ptx/instructions/generated/tcgen05_mma.rst
 create mode 100644 docs/libcudacxx/ptx/instructions/generated/tcgen05_mma_ws.rst
 create mode 100644 docs/libcudacxx/ptx/instructions/generated/tcgen05_shift.rst
 create mode 100644 docs/libcudacxx/ptx/instructions/generated/tcgen05_st.rst
 create mode 100644 docs/libcudacxx/ptx/instructions/generated/tcgen05_wait.rst
 create mode 100644 libcudacxx/include/cuda/__ptx/instructions/generated/barrier_cluster_aligned.h
 create mode 100644 libcudacxx/include/cuda/__ptx/instructions/generated/clusterlaunchcontrol.h
 create mode 100644 libcudacxx/include/cuda/__ptx/instructions/generated/cp_async_bulk_tensor_gather_scatter.h
 create mode 100644 libcudacxx/include/cuda/__ptx/instructions/generated/cp_async_mbarrier_arrive.h
 create mode 100644 libcudacxx/include/cuda/__ptx/instructions/generated/cp_async_mbarrier_arrive_noinc.h
 create mode 100644 libcudacxx/include/cuda/__ptx/instructions/generated/elect_sync.h
 create mode 100644 libcudacxx/include/cuda/__ptx/instructions/generated/fence_proxy_async_generic_sync_restrict.h
 create mode 100644 libcudacxx/include/cuda/__ptx/instructions/generated/fence_sync_restrict.h
 create mode 100644 libcudacxx/include/cuda/__ptx/instructions/generated/mapa.h
 create mode 100644 libcudacxx/include/cuda/__ptx/instructions/generated/mbarrier_expect_tx.h
 create mode 100644 libcudacxx/include/cuda/__ptx/instructions/generated/multimem_ld_reduce.h
 create mode 100644 libcudacxx/include/cuda/__ptx/instructions/generated/multimem_red.h
 create mode 100644 libcudacxx/include/cuda/__ptx/instructions/generated/multimem_st.h
 create mode 100644 libcudacxx/include/cuda/__ptx/instructions/generated/st_bulk.h
 create mode 100644 libcudacxx/include/cuda/__ptx/instructions/generated/tcgen05_alloc.h
 create mode 100644 libcudacxx/include/cuda/__ptx/instructions/generated/tcgen05_commit.h
 create mode 100644 libcudacxx/include/cuda/__ptx/instructions/generated/tcgen05_cp.h
 create mode 100644 libcudacxx/include/cuda/__ptx/instructions/generated/tcgen05_fence.h
 create mode 100644 libcudacxx/include/cuda/__ptx/instructions/generated/tcgen05_ld.h
 create mode 100644 libcudacxx/include/cuda/__ptx/instructions/generated/tcgen05_mma.h
 create mode 100644 libcudacxx/include/cuda/__ptx/instructions/generated/tcgen05_mma_ws.h
 create mode 100644 libcudacxx/include/cuda/__ptx/instructions/generated/tcgen05_shift.h
 create mode 100644 libcudacxx/include/cuda/__ptx/instructions/generated/tcgen05_st.h
 create mode 100644 libcudacxx/include/cuda/__ptx/instructions/generated/tcgen05_wait.h
 create mode 100644 libcudacxx/test/libcudacxx/cuda/ptx/generated/barrier_cluster_aligned.h
 create mode 100644 libcudacxx/test/libcudacxx/cuda/ptx/generated/clusterlaunchcontrol.h
 create mode 100644 libcudacxx/test/libcudacxx/cuda/ptx/generated/cp_async_bulk_tensor_gather_scatter.h
 create mode 100644 libcudacxx/test/libcudacxx/cuda/ptx/generated/cp_async_mbarrier_arrive.h
 create mode 100644 libcudacxx/test/libcudacxx/cuda/ptx/generated/cp_async_mbarrier_arrive_noinc.h
 create mode 100644 libcudacxx/test/libcudacxx/cuda/ptx/generated/elect_sync.h
 create mode 100644 libcudacxx/test/libcudacxx/cuda/ptx/generated/fence_proxy_async_generic_sync_restrict.h
 create mode 100644 libcudacxx/test/libcudacxx/cuda/ptx/generated/fence_sync_restrict.h
 create mode 100644 libcudacxx/test/libcudacxx/cuda/ptx/generated/mapa.h
 create mode 100644 libcudacxx/test/libcudacxx/cuda/ptx/generated/mbarrier_expect_tx.h
 create mode 100644 libcudacxx/test/libcudacxx/cuda/ptx/generated/mbarrier_test_wait.h
 create mode 100644 libcudacxx/test/libcudacxx/cuda/ptx/generated/mbarrier_test_wait_parity.h
 delete mode 100644 libcudacxx/test/libcudacxx/cuda/ptx/generated/mbarrier_wait.h
 delete mode 100644 libcudacxx/test/libcudacxx/cuda/ptx/generated/mbarrier_wait_parity.h
 create mode 100644 libcudacxx/test/libcudacxx/cuda/ptx/generated/multimem_ld_reduce.h
 create mode 100644 libcudacxx/test/libcudacxx/cuda/ptx/generated/multimem_red.h
 create mode 100644 libcudacxx/test/libcudacxx/cuda/ptx/generated/multimem_st.h
 create mode 100644 libcudacxx/test/libcudacxx/cuda/ptx/generated/st_bulk.h
 create mode 100644 libcudacxx/test/libcudacxx/cuda/ptx/generated/tcgen05_alloc.h
 create mode 100644 libcudacxx/test/libcudacxx/cuda/ptx/generated/tcgen05_commit.h
 create mode 100644 libcudacxx/test/libcudacxx/cuda/ptx/generated/tcgen05_cp.h
 create mode 100644 libcudacxx/test/libcudacxx/cuda/ptx/generated/tcgen05_fence.h
 create mode 100644 libcudacxx/test/libcudacxx/cuda/ptx/generated/tcgen05_ld.h
 create mode 100644 libcudacxx/test/libcudacxx/cuda/ptx/generated/tcgen05_mma.h
 create mode 100644 libcudacxx/test/libcudacxx/cuda/ptx/generated/tcgen05_mma_ws.h
 create mode 100644 libcudacxx/test/libcudacxx/cuda/ptx/generated/tcgen05_shift.h
 create mode 100644 libcudacxx/test/libcudacxx/cuda/ptx/generated/tcgen05_st.h
 create mode 100644 libcudacxx/test/libcudacxx/cuda/ptx/generated/tcgen05_wait.h
 create mode 100644 libcudacxx/test/libcudacxx/cuda/ptx/nvrtc_workaround.h

diff --git a/docs/libcudacxx/ptx/instructions/generated/barrier_cluster_aligned.rst b/docs/libcudacxx/ptx/instructions/generated/barrier_cluster_aligned.rst
new file mode 100644
index 00000000000..a24093ac7b6
--- /dev/null
+++ b/docs/libcudacxx/ptx/instructions/generated/barrier_cluster_aligned.rst
@@ -0,0 +1,63 @@
+..
+   This file was automatically generated. Do not edit.
+
+barrier.cluster.arrive.aligned
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // barrier.cluster.arrive.aligned; // PTX ISA 78, SM_90
+   // .aligned   = { .aligned }
+   // Marked volatile and as clobbering memory
+   template <typename = void>
+   __device__ static inline void barrier_cluster_arrive(
+     cuda::ptx::dot_aligned_t);
+
+barrier.cluster.wait.aligned
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // barrier.cluster.wait.aligned; // PTX ISA 78, SM_90
+   // .aligned   = { .aligned }
+   // Marked volatile and as clobbering memory
+   template <typename = void>
+   __device__ static inline void barrier_cluster_wait(
+     cuda::ptx::dot_aligned_t);
+
+barrier.cluster.arrive.release.aligned
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // barrier.cluster.arrive.sem.aligned; // PTX ISA 80, SM_90
+   // .sem       = { .release }
+   // .aligned   = { .aligned }
+   // Marked volatile and as clobbering memory
+   template <typename = void>
+   __device__ static inline void barrier_cluster_arrive(
+     cuda::ptx::sem_release_t,
+     cuda::ptx::dot_aligned_t);
+
+barrier.cluster.arrive.relaxed.aligned
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // barrier.cluster.arrive.sem.aligned; // PTX ISA 80, SM_90
+   // .sem       = { .relaxed }
+   // .aligned   = { .aligned }
+   // Marked volatile
+   template <typename = void>
+   __device__ static inline void barrier_cluster_arrive(
+     cuda::ptx::sem_relaxed_t,
+     cuda::ptx::dot_aligned_t);
+
+barrier.cluster.wait.acquire.aligned
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // barrier.cluster.wait.sem.aligned; // PTX ISA 80, SM_90
+   // .sem       = { .acquire }
+   // .aligned   = { .aligned }
+   // Marked volatile and as clobbering memory
+   template <typename = void>
+   __device__ static inline void barrier_cluster_wait(
+     cuda::ptx::sem_acquire_t,
+     cuda::ptx::dot_aligned_t);
diff --git a/docs/libcudacxx/ptx/instructions/generated/clusterlaunchcontrol.rst b/docs/libcudacxx/ptx/instructions/generated/clusterlaunchcontrol.rst
new file mode 100644
index 00000000000..b372c5bf33e
--- /dev/null
+++ b/docs/libcudacxx/ptx/instructions/generated/clusterlaunchcontrol.rst
@@ -0,0 +1,68 @@
+..
+   This file was automatically generated. Do not edit.
+
+clusterlaunchcontrol.try_cancel.async.shared::cta.mbarrier::complete_tx::bytes.b128
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // clusterlaunchcontrol.try_cancel.async.shared::cta.mbarrier::complete_tx::bytes.b128 [addr], [smem_bar]; // PTX ISA 86, SM_100
+   template <typename = void>
+   __device__ static inline void clusterlaunchcontrol_try_cancel(
+     void* addr,
+     uint64_t* smem_bar);
+
+clusterlaunchcontrol.try_cancel.async.shared::cta.mbarrier::complete_tx::bytes.multicast::cluster::all.b128
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // clusterlaunchcontrol.try_cancel.async.shared::cta.mbarrier::complete_tx::bytes.multicast::cluster::all.b128 [addr], [smem_bar]; // PTX ISA 86, SM_100a, SM_101a
+   template <typename = void>
+   __device__ static inline void clusterlaunchcontrol_try_cancel_multicast(
+     void* addr,
+     uint64_t* smem_bar);
+
+clusterlaunchcontrol.query_cancel.is_canceled.pred.b128
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // clusterlaunchcontrol.query_cancel.is_canceled.pred.b128 pred_is_canceled, try_cancel_response; // PTX ISA 86, SM_100
+   template <typename B128, enable_if_t<sizeof(B128) == 16, bool> = true>
+   __device__ static inline bool clusterlaunchcontrol_query_cancel_is_canceled(
+     B128 try_cancel_response);
+
+clusterlaunchcontrol.query_cancel.get_first_ctaid::x.b32.b128
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // clusterlaunchcontrol.query_cancel.get_first_ctaid::x.b32.b128 ret_dim, try_cancel_response; // PTX ISA 86, SM_100
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true, typename B128, enable_if_t<sizeof(B128) == 16, bool> = true>
+   __device__ static inline B32 clusterlaunchcontrol_query_cancel_get_first_ctaid_x(
+     B128 try_cancel_response);
+
+clusterlaunchcontrol.query_cancel.get_first_ctaid::y.b32.b128
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // clusterlaunchcontrol.query_cancel.get_first_ctaid::y.b32.b128 ret_dim, try_cancel_response; // PTX ISA 86, SM_100
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true, typename B128, enable_if_t<sizeof(B128) == 16, bool> = true>
+   __device__ static inline B32 clusterlaunchcontrol_query_cancel_get_first_ctaid_y(
+     B128 try_cancel_response);
+
+clusterlaunchcontrol.query_cancel.get_first_ctaid::z.b32.b128
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // clusterlaunchcontrol.query_cancel.get_first_ctaid::z.b32.b128 ret_dim, try_cancel_response; // PTX ISA 86, SM_100
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true, typename B128, enable_if_t<sizeof(B128) == 16, bool> = true>
+   __device__ static inline B32 clusterlaunchcontrol_query_cancel_get_first_ctaid_z(
+     B128 try_cancel_response);
+
+clusterlaunchcontrol.query_cancel.get_first_ctaid.v4.b32.b128
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // clusterlaunchcontrol.query_cancel.get_first_ctaid.v4.b32.b128 block_dim, try_cancel_response; // PTX ISA 86, SM_100
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true, typename B128, enable_if_t<sizeof(B128) == 16, bool> = true>
+   __device__ static inline void clusterlaunchcontrol_query_cancel_get_first_ctaid(
+     B32 (&block_dim)[4],
+     B128 try_cancel_response);
diff --git a/docs/libcudacxx/ptx/instructions/generated/cp_async_bulk.rst b/docs/libcudacxx/ptx/instructions/generated/cp_async_bulk.rst
index 4883d8495eb..2bb334f1971 100644
--- a/docs/libcudacxx/ptx/instructions/generated/cp_async_bulk.rst
+++ b/docs/libcudacxx/ptx/instructions/generated/cp_async_bulk.rst
@@ -5,7 +5,7 @@ cp.async.bulk.shared::cluster.global.mbarrier::complete_tx::bytes
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 .. code:: cuda
 
-   // cp.async.bulk.dst.src.mbarrier::complete_tx::bytes [dstMem], [srcMem], size, [smem_bar]; // 1a. unicast PTX ISA 80, SM_90
+   // cp.async.bulk.dst.src.mbarrier::complete_tx::bytes [dstMem], [srcMem], size, [smem_bar]; // PTX ISA 80, SM_90
    // .dst       = { .shared::cluster }
    // .src       = { .global }
    template <typename = void>
@@ -17,11 +17,27 @@ cp.async.bulk.shared::cluster.global.mbarrier::complete_tx::bytes
      const uint32_t& size,
      uint64_t* smem_bar);
 
+cp.async.bulk.shared::cta.global.mbarrier::complete_tx::bytes
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // cp.async.bulk.dst.src.mbarrier::complete_tx::bytes [dstMem], [srcMem], size, [smem_bar]; // PTX ISA 86, SM_90
+   // .dst       = { .shared::cta }
+   // .src       = { .global }
+   template <typename = void>
+   __device__ static inline void cp_async_bulk(
+     cuda::ptx::space_shared_t,
+     cuda::ptx::space_global_t,
+     void* dstMem,
+     const void* srcMem,
+     const uint32_t& size,
+     uint64_t* smem_bar);
+
 cp.async.bulk.shared::cluster.shared::cta.mbarrier::complete_tx::bytes
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 .. code:: cuda
 
-   // cp.async.bulk.dst.src.mbarrier::complete_tx::bytes [dstMem], [srcMem], size, [rdsmem_bar]; // 2.  PTX ISA 80, SM_90
+   // cp.async.bulk.dst.src.mbarrier::complete_tx::bytes [dstMem], [srcMem], size, [rdsmem_bar]; // PTX ISA 80, SM_90
    // .dst       = { .shared::cluster }
    // .src       = { .shared::cta }
    template <typename = void>
@@ -37,7 +53,7 @@ cp.async.bulk.global.shared::cta.bulk_group
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 .. code:: cuda
 
-   // cp.async.bulk.dst.src.bulk_group [dstMem], [srcMem], size; // 3.  PTX ISA 80, SM_90
+   // cp.async.bulk.dst.src.bulk_group [dstMem], [srcMem], size; // PTX ISA 80, SM_90
    // .dst       = { .global }
    // .src       = { .shared::cta }
    template <typename = void>
@@ -47,3 +63,19 @@ cp.async.bulk.global.shared::cta.bulk_group
      void* dstMem,
      const void* srcMem,
      const uint32_t& size);
+
+cp.async.bulk.global.shared::cta.bulk_group.cp_mask
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // cp.async.bulk.dst.src.bulk_group.cp_mask [dstMem], [srcMem], size, byteMask; // PTX ISA 86, SM_100
+   // .dst       = { .global }
+   // .src       = { .shared::cta }
+   template <typename = void>
+   __device__ static inline void cp_async_bulk_cp_mask(
+     cuda::ptx::space_global_t,
+     cuda::ptx::space_shared_t,
+     void* dstMem,
+     const void* srcMem,
+     const uint32_t& size,
+     const uint16_t& byteMask);
diff --git a/docs/libcudacxx/ptx/instructions/generated/cp_async_bulk_multicast.rst b/docs/libcudacxx/ptx/instructions/generated/cp_async_bulk_multicast.rst
index af027c0b623..396a04e468b 100644
--- a/docs/libcudacxx/ptx/instructions/generated/cp_async_bulk_multicast.rst
+++ b/docs/libcudacxx/ptx/instructions/generated/cp_async_bulk_multicast.rst
@@ -5,7 +5,7 @@ cp.async.bulk.shared::cluster.global.mbarrier::complete_tx::bytes.multicast::clu
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 .. code:: cuda
 
-   // cp.async.bulk{.dst}{.src}.mbarrier::complete_tx::bytes.multicast::cluster [dstMem], [srcMem], size, [smem_bar], ctaMask; // 1.  PTX ISA 80, SM_90a
+   // cp.async.bulk.dst.src.mbarrier::complete_tx::bytes.multicast::cluster [dstMem], [srcMem], size, [smem_bar], ctaMask; // PTX ISA 80, SM_90a, SM_100a, SM_101a
    // .dst       = { .shared::cluster }
    // .src       = { .global }
    template <typename = void>
diff --git a/docs/libcudacxx/ptx/instructions/generated/cp_async_bulk_tensor.rst b/docs/libcudacxx/ptx/instructions/generated/cp_async_bulk_tensor.rst
index 1c21efdd0a3..9d44a10800b 100644
--- a/docs/libcudacxx/ptx/instructions/generated/cp_async_bulk_tensor.rst
+++ b/docs/libcudacxx/ptx/instructions/generated/cp_async_bulk_tensor.rst
@@ -5,7 +5,7 @@ cp.async.bulk.tensor.1d.shared::cluster.global.tile.mbarrier::complete_tx::bytes
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 .. code:: cuda
 
-   // cp.async.bulk.tensor.1d.dst.src.tile.mbarrier::complete_tx::bytes [dstMem], [tensorMap, tensorCoords], [smem_bar];// 1a. PTX ISA 80, SM_90
+   // cp.async.bulk.tensor.1d.dst.src.tile.mbarrier::complete_tx::bytes [dstMem], [tensorMap, tensorCoords], [smem_bar]; // PTX ISA 80, SM_90
    // .dst       = { .shared::cluster }
    // .src       = { .global }
    template <typename = void>
@@ -17,11 +17,63 @@ cp.async.bulk.tensor.1d.shared::cluster.global.tile.mbarrier::complete_tx::bytes
      const int32_t (&tensorCoords)[1],
      uint64_t* smem_bar);
 
+cp.async.bulk.tensor.1d.shared::cta.global.tile.mbarrier::complete_tx::bytes
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // cp.async.bulk.tensor.1d.dst.src.tile.mbarrier::complete_tx::bytes [dstMem], [tensorMap, tensorCoords], [smem_bar]; // PTX ISA 86, SM_90
+   // .dst       = { .shared::cta }
+   // .src       = { .global }
+   template <typename = void>
+   __device__ static inline void cp_async_bulk_tensor(
+     cuda::ptx::space_shared_t,
+     cuda::ptx::space_global_t,
+     void* dstMem,
+     const void* tensorMap,
+     const int32_t (&tensorCoords)[1],
+     uint64_t* smem_bar);
+
+cp.async.bulk.tensor.1d.shared::cta.global.tile.mbarrier::complete_tx::bytes.cta_group::1
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // cp.async.bulk.tensor.1d.dst.src.tile.mbarrier::complete_tx::bytes.cta_group [dstMem], [tensorMap, tensorCoords], [smem_bar]; // PTX ISA 86, SM_100a, SM_101a
+   // .dst       = { .shared::cta }
+   // .src       = { .global }
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void cp_async_bulk_tensor(
+     cuda::ptx::space_shared_t,
+     cuda::ptx::space_global_t,
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     void* dstMem,
+     const void* tensorMap,
+     const int32_t (&tensorCoords)[1],
+     uint64_t* smem_bar);
+
+cp.async.bulk.tensor.1d.shared::cta.global.tile.mbarrier::complete_tx::bytes.cta_group::2
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // cp.async.bulk.tensor.1d.dst.src.tile.mbarrier::complete_tx::bytes.cta_group [dstMem], [tensorMap, tensorCoords], [smem_bar]; // PTX ISA 86, SM_100a, SM_101a
+   // .dst       = { .shared::cta }
+   // .src       = { .global }
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void cp_async_bulk_tensor(
+     cuda::ptx::space_shared_t,
+     cuda::ptx::space_global_t,
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     void* dstMem,
+     const void* tensorMap,
+     const int32_t (&tensorCoords)[1],
+     uint64_t* smem_bar);
+
 cp.async.bulk.tensor.1d.global.shared::cta.tile.bulk_group
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 .. code:: cuda
 
-   // cp.async.bulk.tensor.1d.dst.src.tile.bulk_group [tensorMap, tensorCoords], [srcMem]; // 3a. PTX ISA 80, SM_90
+   // cp.async.bulk.tensor.1d.dst.src.tile.bulk_group [tensorMap, tensorCoords], [srcMem]; // PTX ISA 80, SM_90
    // .dst       = { .global }
    // .src       = { .shared::cta }
    template <typename = void>
@@ -36,7 +88,7 @@ cp.async.bulk.tensor.2d.shared::cluster.global.tile.mbarrier::complete_tx::bytes
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 .. code:: cuda
 
-   // cp.async.bulk.tensor.2d.dst.src.tile.mbarrier::complete_tx::bytes [dstMem], [tensorMap, tensorCoords], [smem_bar];// 1b. PTX ISA 80, SM_90
+   // cp.async.bulk.tensor.2d.dst.src.tile.mbarrier::complete_tx::bytes [dstMem], [tensorMap, tensorCoords], [smem_bar]; // PTX ISA 80, SM_90
    // .dst       = { .shared::cluster }
    // .src       = { .global }
    template <typename = void>
@@ -48,11 +100,63 @@ cp.async.bulk.tensor.2d.shared::cluster.global.tile.mbarrier::complete_tx::bytes
      const int32_t (&tensorCoords)[2],
      uint64_t* smem_bar);
 
+cp.async.bulk.tensor.2d.shared::cta.global.tile.mbarrier::complete_tx::bytes
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // cp.async.bulk.tensor.2d.dst.src.tile.mbarrier::complete_tx::bytes [dstMem], [tensorMap, tensorCoords], [smem_bar]; // PTX ISA 86, SM_90
+   // .dst       = { .shared::cta }
+   // .src       = { .global }
+   template <typename = void>
+   __device__ static inline void cp_async_bulk_tensor(
+     cuda::ptx::space_shared_t,
+     cuda::ptx::space_global_t,
+     void* dstMem,
+     const void* tensorMap,
+     const int32_t (&tensorCoords)[2],
+     uint64_t* smem_bar);
+
+cp.async.bulk.tensor.2d.shared::cta.global.tile.mbarrier::complete_tx::bytes.cta_group::1
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // cp.async.bulk.tensor.2d.dst.src.tile.mbarrier::complete_tx::bytes.cta_group [dstMem], [tensorMap, tensorCoords], [smem_bar]; // PTX ISA 86, SM_100a, SM_101a
+   // .dst       = { .shared::cta }
+   // .src       = { .global }
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void cp_async_bulk_tensor(
+     cuda::ptx::space_shared_t,
+     cuda::ptx::space_global_t,
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     void* dstMem,
+     const void* tensorMap,
+     const int32_t (&tensorCoords)[2],
+     uint64_t* smem_bar);
+
+cp.async.bulk.tensor.2d.shared::cta.global.tile.mbarrier::complete_tx::bytes.cta_group::2
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // cp.async.bulk.tensor.2d.dst.src.tile.mbarrier::complete_tx::bytes.cta_group [dstMem], [tensorMap, tensorCoords], [smem_bar]; // PTX ISA 86, SM_100a, SM_101a
+   // .dst       = { .shared::cta }
+   // .src       = { .global }
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void cp_async_bulk_tensor(
+     cuda::ptx::space_shared_t,
+     cuda::ptx::space_global_t,
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     void* dstMem,
+     const void* tensorMap,
+     const int32_t (&tensorCoords)[2],
+     uint64_t* smem_bar);
+
 cp.async.bulk.tensor.2d.global.shared::cta.tile.bulk_group
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 .. code:: cuda
 
-   // cp.async.bulk.tensor.2d.dst.src.tile.bulk_group [tensorMap, tensorCoords], [srcMem]; // 3b. PTX ISA 80, SM_90
+   // cp.async.bulk.tensor.2d.dst.src.tile.bulk_group [tensorMap, tensorCoords], [srcMem]; // PTX ISA 80, SM_90
    // .dst       = { .global }
    // .src       = { .shared::cta }
    template <typename = void>
@@ -67,7 +171,7 @@ cp.async.bulk.tensor.3d.shared::cluster.global.tile.mbarrier::complete_tx::bytes
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 .. code:: cuda
 
-   // cp.async.bulk.tensor.3d.dst.src.tile.mbarrier::complete_tx::bytes [dstMem], [tensorMap, tensorCoords], [smem_bar];// 1c. PTX ISA 80, SM_90
+   // cp.async.bulk.tensor.3d.dst.src.tile.mbarrier::complete_tx::bytes [dstMem], [tensorMap, tensorCoords], [smem_bar]; // PTX ISA 80, SM_90
    // .dst       = { .shared::cluster }
    // .src       = { .global }
    template <typename = void>
@@ -79,11 +183,63 @@ cp.async.bulk.tensor.3d.shared::cluster.global.tile.mbarrier::complete_tx::bytes
      const int32_t (&tensorCoords)[3],
      uint64_t* smem_bar);
 
+cp.async.bulk.tensor.3d.shared::cta.global.tile.mbarrier::complete_tx::bytes
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // cp.async.bulk.tensor.3d.dst.src.tile.mbarrier::complete_tx::bytes [dstMem], [tensorMap, tensorCoords], [smem_bar]; // PTX ISA 86, SM_90
+   // .dst       = { .shared::cta }
+   // .src       = { .global }
+   template <typename = void>
+   __device__ static inline void cp_async_bulk_tensor(
+     cuda::ptx::space_shared_t,
+     cuda::ptx::space_global_t,
+     void* dstMem,
+     const void* tensorMap,
+     const int32_t (&tensorCoords)[3],
+     uint64_t* smem_bar);
+
+cp.async.bulk.tensor.3d.shared::cta.global.tile.mbarrier::complete_tx::bytes.cta_group::1
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // cp.async.bulk.tensor.3d.dst.src.tile.mbarrier::complete_tx::bytes.cta_group [dstMem], [tensorMap, tensorCoords], [smem_bar]; // PTX ISA 86, SM_100a, SM_101a
+   // .dst       = { .shared::cta }
+   // .src       = { .global }
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void cp_async_bulk_tensor(
+     cuda::ptx::space_shared_t,
+     cuda::ptx::space_global_t,
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     void* dstMem,
+     const void* tensorMap,
+     const int32_t (&tensorCoords)[3],
+     uint64_t* smem_bar);
+
+cp.async.bulk.tensor.3d.shared::cta.global.tile.mbarrier::complete_tx::bytes.cta_group::2
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // cp.async.bulk.tensor.3d.dst.src.tile.mbarrier::complete_tx::bytes.cta_group [dstMem], [tensorMap, tensorCoords], [smem_bar]; // PTX ISA 86, SM_100a, SM_101a
+   // .dst       = { .shared::cta }
+   // .src       = { .global }
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void cp_async_bulk_tensor(
+     cuda::ptx::space_shared_t,
+     cuda::ptx::space_global_t,
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     void* dstMem,
+     const void* tensorMap,
+     const int32_t (&tensorCoords)[3],
+     uint64_t* smem_bar);
+
 cp.async.bulk.tensor.3d.global.shared::cta.tile.bulk_group
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 .. code:: cuda
 
-   // cp.async.bulk.tensor.3d.dst.src.tile.bulk_group [tensorMap, tensorCoords], [srcMem]; // 3c. PTX ISA 80, SM_90
+   // cp.async.bulk.tensor.3d.dst.src.tile.bulk_group [tensorMap, tensorCoords], [srcMem]; // PTX ISA 80, SM_90
    // .dst       = { .global }
    // .src       = { .shared::cta }
    template <typename = void>
@@ -98,7 +254,7 @@ cp.async.bulk.tensor.4d.shared::cluster.global.tile.mbarrier::complete_tx::bytes
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 .. code:: cuda
 
-   // cp.async.bulk.tensor.4d.dst.src.tile.mbarrier::complete_tx::bytes [dstMem], [tensorMap, tensorCoords], [smem_bar];// 1d. PTX ISA 80, SM_90
+   // cp.async.bulk.tensor.4d.dst.src.tile.mbarrier::complete_tx::bytes [dstMem], [tensorMap, tensorCoords], [smem_bar]; // PTX ISA 80, SM_90
    // .dst       = { .shared::cluster }
    // .src       = { .global }
    template <typename = void>
@@ -110,11 +266,63 @@ cp.async.bulk.tensor.4d.shared::cluster.global.tile.mbarrier::complete_tx::bytes
      const int32_t (&tensorCoords)[4],
      uint64_t* smem_bar);
 
+cp.async.bulk.tensor.4d.shared::cta.global.tile.mbarrier::complete_tx::bytes
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // cp.async.bulk.tensor.4d.dst.src.tile.mbarrier::complete_tx::bytes [dstMem], [tensorMap, tensorCoords], [smem_bar]; // PTX ISA 86, SM_90
+   // .dst       = { .shared::cta }
+   // .src       = { .global }
+   template <typename = void>
+   __device__ static inline void cp_async_bulk_tensor(
+     cuda::ptx::space_shared_t,
+     cuda::ptx::space_global_t,
+     void* dstMem,
+     const void* tensorMap,
+     const int32_t (&tensorCoords)[4],
+     uint64_t* smem_bar);
+
+cp.async.bulk.tensor.4d.shared::cta.global.tile.mbarrier::complete_tx::bytes.cta_group::1
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // cp.async.bulk.tensor.4d.dst.src.tile.mbarrier::complete_tx::bytes.cta_group [dstMem], [tensorMap, tensorCoords], [smem_bar]; // PTX ISA 86, SM_100a, SM_101a
+   // .dst       = { .shared::cta }
+   // .src       = { .global }
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void cp_async_bulk_tensor(
+     cuda::ptx::space_shared_t,
+     cuda::ptx::space_global_t,
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     void* dstMem,
+     const void* tensorMap,
+     const int32_t (&tensorCoords)[4],
+     uint64_t* smem_bar);
+
+cp.async.bulk.tensor.4d.shared::cta.global.tile.mbarrier::complete_tx::bytes.cta_group::2
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // cp.async.bulk.tensor.4d.dst.src.tile.mbarrier::complete_tx::bytes.cta_group [dstMem], [tensorMap, tensorCoords], [smem_bar]; // PTX ISA 86, SM_100a, SM_101a
+   // .dst       = { .shared::cta }
+   // .src       = { .global }
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void cp_async_bulk_tensor(
+     cuda::ptx::space_shared_t,
+     cuda::ptx::space_global_t,
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     void* dstMem,
+     const void* tensorMap,
+     const int32_t (&tensorCoords)[4],
+     uint64_t* smem_bar);
+
 cp.async.bulk.tensor.4d.global.shared::cta.tile.bulk_group
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 .. code:: cuda
 
-   // cp.async.bulk.tensor.4d.dst.src.tile.bulk_group [tensorMap, tensorCoords], [srcMem]; // 3d. PTX ISA 80, SM_90
+   // cp.async.bulk.tensor.4d.dst.src.tile.bulk_group [tensorMap, tensorCoords], [srcMem]; // PTX ISA 80, SM_90
    // .dst       = { .global }
    // .src       = { .shared::cta }
    template <typename = void>
@@ -129,7 +337,7 @@ cp.async.bulk.tensor.5d.shared::cluster.global.tile.mbarrier::complete_tx::bytes
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 .. code:: cuda
 
-   // cp.async.bulk.tensor.5d.dst.src.tile.mbarrier::complete_tx::bytes [dstMem], [tensorMap, tensorCoords], [smem_bar];// 1e. PTX ISA 80, SM_90
+   // cp.async.bulk.tensor.5d.dst.src.tile.mbarrier::complete_tx::bytes [dstMem], [tensorMap, tensorCoords], [smem_bar]; // PTX ISA 80, SM_90
    // .dst       = { .shared::cluster }
    // .src       = { .global }
    template <typename = void>
@@ -141,11 +349,63 @@ cp.async.bulk.tensor.5d.shared::cluster.global.tile.mbarrier::complete_tx::bytes
      const int32_t (&tensorCoords)[5],
      uint64_t* smem_bar);
 
+cp.async.bulk.tensor.5d.shared::cta.global.tile.mbarrier::complete_tx::bytes
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // cp.async.bulk.tensor.5d.dst.src.tile.mbarrier::complete_tx::bytes [dstMem], [tensorMap, tensorCoords], [smem_bar]; // PTX ISA 86, SM_90
+   // .dst       = { .shared::cta }
+   // .src       = { .global }
+   template <typename = void>
+   __device__ static inline void cp_async_bulk_tensor(
+     cuda::ptx::space_shared_t,
+     cuda::ptx::space_global_t,
+     void* dstMem,
+     const void* tensorMap,
+     const int32_t (&tensorCoords)[5],
+     uint64_t* smem_bar);
+
+cp.async.bulk.tensor.5d.shared::cta.global.tile.mbarrier::complete_tx::bytes.cta_group::1
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // cp.async.bulk.tensor.5d.dst.src.tile.mbarrier::complete_tx::bytes.cta_group [dstMem], [tensorMap, tensorCoords], [smem_bar]; // PTX ISA 86, SM_100a, SM_101a
+   // .dst       = { .shared::cta }
+   // .src       = { .global }
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void cp_async_bulk_tensor(
+     cuda::ptx::space_shared_t,
+     cuda::ptx::space_global_t,
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     void* dstMem,
+     const void* tensorMap,
+     const int32_t (&tensorCoords)[5],
+     uint64_t* smem_bar);
+
+cp.async.bulk.tensor.5d.shared::cta.global.tile.mbarrier::complete_tx::bytes.cta_group::2
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // cp.async.bulk.tensor.5d.dst.src.tile.mbarrier::complete_tx::bytes.cta_group [dstMem], [tensorMap, tensorCoords], [smem_bar]; // PTX ISA 86, SM_100a, SM_101a
+   // .dst       = { .shared::cta }
+   // .src       = { .global }
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void cp_async_bulk_tensor(
+     cuda::ptx::space_shared_t,
+     cuda::ptx::space_global_t,
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     void* dstMem,
+     const void* tensorMap,
+     const int32_t (&tensorCoords)[5],
+     uint64_t* smem_bar);
+
 cp.async.bulk.tensor.5d.global.shared::cta.tile.bulk_group
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 .. code:: cuda
 
-   // cp.async.bulk.tensor.5d.dst.src.tile.bulk_group [tensorMap, tensorCoords], [srcMem]; // 3e. PTX ISA 80, SM_90
+   // cp.async.bulk.tensor.5d.dst.src.tile.bulk_group [tensorMap, tensorCoords], [srcMem]; // PTX ISA 80, SM_90
    // .dst       = { .global }
    // .src       = { .shared::cta }
    template <typename = void>
diff --git a/docs/libcudacxx/ptx/instructions/generated/cp_async_bulk_tensor_gather_scatter.rst b/docs/libcudacxx/ptx/instructions/generated/cp_async_bulk_tensor_gather_scatter.rst
new file mode 100644
index 00000000000..971f0213cb0
--- /dev/null
+++ b/docs/libcudacxx/ptx/instructions/generated/cp_async_bulk_tensor_gather_scatter.rst
@@ -0,0 +1,124 @@
+..
+   This file was automatically generated. Do not edit.
+
+cp.async.bulk.tensor.2d.shared::cta.global.tile::gather4.mbarrier::complete_tx::bytes
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // cp.async.bulk.tensor.2d.dst.src.tile::gather4.mbarrier::complete_tx::bytes [dstMem], [tensorMap, tensorCoords], [smem_bar]; // PTX ISA 86, SM_100
+   // .dst       = { .shared::cta }
+   // .src       = { .global }
+   template <typename = void>
+   __device__ static inline void cp_async_bulk_tensor_tile_gather4(
+     cuda::ptx::space_shared_t,
+     cuda::ptx::space_global_t,
+     void* dstMem,
+     const void* tensorMap,
+     const int32_t (&tensorCoords)[5],
+     uint64_t* smem_bar);
+
+cp.async.bulk.tensor.2d.shared::cta.global.tile::gather4.mbarrier::complete_tx::bytes.cta_group::1
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // cp.async.bulk.tensor.2d.dst.src.tile::gather4.mbarrier::complete_tx::bytes.cta_group [dstMem], [tensorMap, tensorCoords], [smem_bar]; // PTX ISA 86, SM_100a, SM_101a
+   // .dst       = { .shared::cta }
+   // .src       = { .global }
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void cp_async_bulk_tensor_tile_gather4(
+     cuda::ptx::space_shared_t,
+     cuda::ptx::space_global_t,
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     void* dstMem,
+     const void* tensorMap,
+     const int32_t (&tensorCoords)[5],
+     uint64_t* smem_bar);
+
+cp.async.bulk.tensor.2d.shared::cta.global.tile::gather4.mbarrier::complete_tx::bytes.cta_group::2
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // cp.async.bulk.tensor.2d.dst.src.tile::gather4.mbarrier::complete_tx::bytes.cta_group [dstMem], [tensorMap, tensorCoords], [smem_bar]; // PTX ISA 86, SM_100a, SM_101a
+   // .dst       = { .shared::cta }
+   // .src       = { .global }
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void cp_async_bulk_tensor_tile_gather4(
+     cuda::ptx::space_shared_t,
+     cuda::ptx::space_global_t,
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     void* dstMem,
+     const void* tensorMap,
+     const int32_t (&tensorCoords)[5],
+     uint64_t* smem_bar);
+
+cp.async.bulk.tensor.2d.shared::cluster.global.tile::gather4.mbarrier::complete_tx::bytes.multicast::cluster
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // cp.async.bulk.tensor.2d.dst.src.tile::gather4.mbarrier::complete_tx::bytes.multicast::cluster [dstMem], [tensorMap, tensorCoords], [smem_bar], ctaMask; // PTX ISA 86, SM_100a, SM_101a
+   // .dst       = { .shared::cluster }
+   // .src       = { .global }
+   template <typename = void>
+   __device__ static inline void cp_async_bulk_tensor_tile_gather4(
+     cuda::ptx::space_cluster_t,
+     cuda::ptx::space_global_t,
+     void* dstMem,
+     const void* tensorMap,
+     const int32_t (&tensorCoords)[5],
+     uint64_t* smem_bar,
+     const uint16_t& ctaMask);
+
+cp.async.bulk.tensor.2d.shared::cluster.global.tile::gather4.mbarrier::complete_tx::bytes.multicast::cluster.cta_group::1
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // cp.async.bulk.tensor.2d.dst.src.tile::gather4.mbarrier::complete_tx::bytes.multicast::cluster.cta_group [dstMem], [tensorMap, tensorCoords], [smem_bar], ctaMask; // PTX ISA 86, SM_100a, SM_101a
+   // .dst       = { .shared::cluster }
+   // .src       = { .global }
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void cp_async_bulk_tensor_tile_gather4(
+     cuda::ptx::space_cluster_t,
+     cuda::ptx::space_global_t,
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     void* dstMem,
+     const void* tensorMap,
+     const int32_t (&tensorCoords)[5],
+     uint64_t* smem_bar,
+     const uint16_t& ctaMask);
+
+cp.async.bulk.tensor.2d.shared::cluster.global.tile::gather4.mbarrier::complete_tx::bytes.multicast::cluster.cta_group::2
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // cp.async.bulk.tensor.2d.dst.src.tile::gather4.mbarrier::complete_tx::bytes.multicast::cluster.cta_group [dstMem], [tensorMap, tensorCoords], [smem_bar], ctaMask; // PTX ISA 86, SM_100a, SM_101a
+   // .dst       = { .shared::cluster }
+   // .src       = { .global }
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void cp_async_bulk_tensor_tile_gather4(
+     cuda::ptx::space_cluster_t,
+     cuda::ptx::space_global_t,
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     void* dstMem,
+     const void* tensorMap,
+     const int32_t (&tensorCoords)[5],
+     uint64_t* smem_bar,
+     const uint16_t& ctaMask);
+
+cp.async.bulk.tensor.2d.global.shared::cta.tile::scatter4.bulk_group
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // cp.async.bulk.tensor.2d.dst.src.tile::scatter4.bulk_group [tensorMap, tensorCoords], [srcMem]; // PTX ISA 80, SM_100a, SM_101a
+   // .dst       = { .global }
+   // .src       = { .shared::cta }
+   template <typename = void>
+   __device__ static inline void cp_async_bulk_tensor_tile_scatter4(
+     cuda::ptx::space_global_t,
+     cuda::ptx::space_shared_t,
+     const void* tensorMap,
+     const int32_t (&tensorCoords)[5],
+     const void* srcMem);
diff --git a/docs/libcudacxx/ptx/instructions/generated/cp_async_bulk_tensor_multicast.rst b/docs/libcudacxx/ptx/instructions/generated/cp_async_bulk_tensor_multicast.rst
index ac33a05b69f..8ea38a2e0ad 100644
--- a/docs/libcudacxx/ptx/instructions/generated/cp_async_bulk_tensor_multicast.rst
+++ b/docs/libcudacxx/ptx/instructions/generated/cp_async_bulk_tensor_multicast.rst
@@ -5,7 +5,7 @@ cp.async.bulk.tensor.1d.shared::cluster.global.tile.mbarrier::complete_tx::bytes
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 .. code:: cuda
 
-   // cp.async.bulk.tensor.1d.dst.src.tile.mbarrier::complete_tx::bytes.multicast::cluster [dstMem], [tensorMap, tensorCoords], [smem_bar], ctaMask; // 2a. PTX ISA 80, SM_90a
+   // cp.async.bulk.tensor.1d.dst.src.tile.mbarrier::complete_tx::bytes.multicast::cluster [dstMem], [tensorMap, tensorCoords], [smem_bar], ctaMask; // PTX ISA 80, SM_90a, SM_100a, SM_101a
    // .dst       = { .shared::cluster }
    // .src       = { .global }
    template <typename = void>
@@ -18,11 +18,49 @@ cp.async.bulk.tensor.1d.shared::cluster.global.tile.mbarrier::complete_tx::bytes
      uint64_t* smem_bar,
      const uint16_t& ctaMask);
 
+cp.async.bulk.tensor.1d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.multicast::cluster.cta_group::1
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // cp.async.bulk.tensor.1d.dst.src.tile.mbarrier::complete_tx::bytes.multicast::cluster.cta_group [dstMem], [tensorMap, tensorCoords], [smem_bar], ctaMask; // PTX ISA 80, SM_100a, SM_101a
+   // .dst       = { .shared::cluster }
+   // .src       = { .global }
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void cp_async_bulk_tensor(
+     cuda::ptx::space_cluster_t,
+     cuda::ptx::space_global_t,
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     void* dstMem,
+     const void* tensorMap,
+     const int32_t (&tensorCoords)[1],
+     uint64_t* smem_bar,
+     const uint16_t& ctaMask);
+
+cp.async.bulk.tensor.1d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.multicast::cluster.cta_group::2
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // cp.async.bulk.tensor.1d.dst.src.tile.mbarrier::complete_tx::bytes.multicast::cluster.cta_group [dstMem], [tensorMap, tensorCoords], [smem_bar], ctaMask; // PTX ISA 80, SM_100a, SM_101a
+   // .dst       = { .shared::cluster }
+   // .src       = { .global }
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void cp_async_bulk_tensor(
+     cuda::ptx::space_cluster_t,
+     cuda::ptx::space_global_t,
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     void* dstMem,
+     const void* tensorMap,
+     const int32_t (&tensorCoords)[1],
+     uint64_t* smem_bar,
+     const uint16_t& ctaMask);
+
 cp.async.bulk.tensor.2d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.multicast::cluster
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 .. code:: cuda
 
-   // cp.async.bulk.tensor.2d.dst.src.tile.mbarrier::complete_tx::bytes.multicast::cluster [dstMem], [tensorMap, tensorCoords], [smem_bar], ctaMask; // 2b. PTX ISA 80, SM_90a
+   // cp.async.bulk.tensor.2d.dst.src.tile.mbarrier::complete_tx::bytes.multicast::cluster [dstMem], [tensorMap, tensorCoords], [smem_bar], ctaMask; // PTX ISA 80, SM_90a, SM_100a, SM_101a
    // .dst       = { .shared::cluster }
    // .src       = { .global }
    template <typename = void>
@@ -35,11 +73,49 @@ cp.async.bulk.tensor.2d.shared::cluster.global.tile.mbarrier::complete_tx::bytes
      uint64_t* smem_bar,
      const uint16_t& ctaMask);
 
+cp.async.bulk.tensor.2d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.multicast::cluster.cta_group::1
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // cp.async.bulk.tensor.2d.dst.src.tile.mbarrier::complete_tx::bytes.multicast::cluster.cta_group [dstMem], [tensorMap, tensorCoords], [smem_bar], ctaMask; // PTX ISA 80, SM_100a, SM_101a
+   // .dst       = { .shared::cluster }
+   // .src       = { .global }
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void cp_async_bulk_tensor(
+     cuda::ptx::space_cluster_t,
+     cuda::ptx::space_global_t,
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     void* dstMem,
+     const void* tensorMap,
+     const int32_t (&tensorCoords)[2],
+     uint64_t* smem_bar,
+     const uint16_t& ctaMask);
+
+cp.async.bulk.tensor.2d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.multicast::cluster.cta_group::2
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // cp.async.bulk.tensor.2d.dst.src.tile.mbarrier::complete_tx::bytes.multicast::cluster.cta_group [dstMem], [tensorMap, tensorCoords], [smem_bar], ctaMask; // PTX ISA 80, SM_100a, SM_101a
+   // .dst       = { .shared::cluster }
+   // .src       = { .global }
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void cp_async_bulk_tensor(
+     cuda::ptx::space_cluster_t,
+     cuda::ptx::space_global_t,
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     void* dstMem,
+     const void* tensorMap,
+     const int32_t (&tensorCoords)[2],
+     uint64_t* smem_bar,
+     const uint16_t& ctaMask);
+
 cp.async.bulk.tensor.3d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.multicast::cluster
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 .. code:: cuda
 
-   // cp.async.bulk.tensor.3d.dst.src.tile.mbarrier::complete_tx::bytes.multicast::cluster [dstMem], [tensorMap, tensorCoords], [smem_bar], ctaMask; // 2c. PTX ISA 80, SM_90a
+   // cp.async.bulk.tensor.3d.dst.src.tile.mbarrier::complete_tx::bytes.multicast::cluster [dstMem], [tensorMap, tensorCoords], [smem_bar], ctaMask; // PTX ISA 80, SM_90a, SM_100a, SM_101a
    // .dst       = { .shared::cluster }
    // .src       = { .global }
    template <typename = void>
@@ -52,11 +128,49 @@ cp.async.bulk.tensor.3d.shared::cluster.global.tile.mbarrier::complete_tx::bytes
      uint64_t* smem_bar,
      const uint16_t& ctaMask);
 
+cp.async.bulk.tensor.3d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.multicast::cluster.cta_group::1
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // cp.async.bulk.tensor.3d.dst.src.tile.mbarrier::complete_tx::bytes.multicast::cluster.cta_group [dstMem], [tensorMap, tensorCoords], [smem_bar], ctaMask; // PTX ISA 80, SM_100a, SM_101a
+   // .dst       = { .shared::cluster }
+   // .src       = { .global }
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void cp_async_bulk_tensor(
+     cuda::ptx::space_cluster_t,
+     cuda::ptx::space_global_t,
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     void* dstMem,
+     const void* tensorMap,
+     const int32_t (&tensorCoords)[3],
+     uint64_t* smem_bar,
+     const uint16_t& ctaMask);
+
+cp.async.bulk.tensor.3d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.multicast::cluster.cta_group::2
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // cp.async.bulk.tensor.3d.dst.src.tile.mbarrier::complete_tx::bytes.multicast::cluster.cta_group [dstMem], [tensorMap, tensorCoords], [smem_bar], ctaMask; // PTX ISA 80, SM_100a, SM_101a
+   // .dst       = { .shared::cluster }
+   // .src       = { .global }
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void cp_async_bulk_tensor(
+     cuda::ptx::space_cluster_t,
+     cuda::ptx::space_global_t,
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     void* dstMem,
+     const void* tensorMap,
+     const int32_t (&tensorCoords)[3],
+     uint64_t* smem_bar,
+     const uint16_t& ctaMask);
+
 cp.async.bulk.tensor.4d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.multicast::cluster
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 .. code:: cuda
 
-   // cp.async.bulk.tensor.4d.dst.src.tile.mbarrier::complete_tx::bytes.multicast::cluster [dstMem], [tensorMap, tensorCoords], [smem_bar], ctaMask; // 2d. PTX ISA 80, SM_90a
+   // cp.async.bulk.tensor.4d.dst.src.tile.mbarrier::complete_tx::bytes.multicast::cluster [dstMem], [tensorMap, tensorCoords], [smem_bar], ctaMask; // PTX ISA 80, SM_90a, SM_100a, SM_101a
    // .dst       = { .shared::cluster }
    // .src       = { .global }
    template <typename = void>
@@ -69,11 +183,49 @@ cp.async.bulk.tensor.4d.shared::cluster.global.tile.mbarrier::complete_tx::bytes
      uint64_t* smem_bar,
      const uint16_t& ctaMask);
 
+cp.async.bulk.tensor.4d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.multicast::cluster.cta_group::1
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // cp.async.bulk.tensor.4d.dst.src.tile.mbarrier::complete_tx::bytes.multicast::cluster.cta_group [dstMem], [tensorMap, tensorCoords], [smem_bar], ctaMask; // PTX ISA 80, SM_100a, SM_101a
+   // .dst       = { .shared::cluster }
+   // .src       = { .global }
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void cp_async_bulk_tensor(
+     cuda::ptx::space_cluster_t,
+     cuda::ptx::space_global_t,
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     void* dstMem,
+     const void* tensorMap,
+     const int32_t (&tensorCoords)[4],
+     uint64_t* smem_bar,
+     const uint16_t& ctaMask);
+
+cp.async.bulk.tensor.4d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.multicast::cluster.cta_group::2
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // cp.async.bulk.tensor.4d.dst.src.tile.mbarrier::complete_tx::bytes.multicast::cluster.cta_group [dstMem], [tensorMap, tensorCoords], [smem_bar], ctaMask; // PTX ISA 80, SM_100a, SM_101a
+   // .dst       = { .shared::cluster }
+   // .src       = { .global }
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void cp_async_bulk_tensor(
+     cuda::ptx::space_cluster_t,
+     cuda::ptx::space_global_t,
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     void* dstMem,
+     const void* tensorMap,
+     const int32_t (&tensorCoords)[4],
+     uint64_t* smem_bar,
+     const uint16_t& ctaMask);
+
 cp.async.bulk.tensor.5d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.multicast::cluster
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 .. code:: cuda
 
-   // cp.async.bulk.tensor.5d.dst.src.tile.mbarrier::complete_tx::bytes.multicast::cluster [dstMem], [tensorMap, tensorCoords], [smem_bar], ctaMask; // 2e. PTX ISA 80, SM_90a
+   // cp.async.bulk.tensor.5d.dst.src.tile.mbarrier::complete_tx::bytes.multicast::cluster [dstMem], [tensorMap, tensorCoords], [smem_bar], ctaMask; // PTX ISA 80, SM_90a, SM_100a, SM_101a
    // .dst       = { .shared::cluster }
    // .src       = { .global }
    template <typename = void>
@@ -85,3 +237,41 @@ cp.async.bulk.tensor.5d.shared::cluster.global.tile.mbarrier::complete_tx::bytes
      const int32_t (&tensorCoords)[5],
      uint64_t* smem_bar,
      const uint16_t& ctaMask);
+
+cp.async.bulk.tensor.5d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.multicast::cluster.cta_group::1
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // cp.async.bulk.tensor.5d.dst.src.tile.mbarrier::complete_tx::bytes.multicast::cluster.cta_group [dstMem], [tensorMap, tensorCoords], [smem_bar], ctaMask; // PTX ISA 80, SM_100a, SM_101a
+   // .dst       = { .shared::cluster }
+   // .src       = { .global }
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void cp_async_bulk_tensor(
+     cuda::ptx::space_cluster_t,
+     cuda::ptx::space_global_t,
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     void* dstMem,
+     const void* tensorMap,
+     const int32_t (&tensorCoords)[5],
+     uint64_t* smem_bar,
+     const uint16_t& ctaMask);
+
+cp.async.bulk.tensor.5d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.multicast::cluster.cta_group::2
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // cp.async.bulk.tensor.5d.dst.src.tile.mbarrier::complete_tx::bytes.multicast::cluster.cta_group [dstMem], [tensorMap, tensorCoords], [smem_bar], ctaMask; // PTX ISA 80, SM_100a, SM_101a
+   // .dst       = { .shared::cluster }
+   // .src       = { .global }
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void cp_async_bulk_tensor(
+     cuda::ptx::space_cluster_t,
+     cuda::ptx::space_global_t,
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     void* dstMem,
+     const void* tensorMap,
+     const int32_t (&tensorCoords)[5],
+     uint64_t* smem_bar,
+     const uint16_t& ctaMask);
diff --git a/docs/libcudacxx/ptx/instructions/generated/cp_async_mbarrier_arrive.rst b/docs/libcudacxx/ptx/instructions/generated/cp_async_mbarrier_arrive.rst
new file mode 100644
index 00000000000..73ce222a9ec
--- /dev/null
+++ b/docs/libcudacxx/ptx/instructions/generated/cp_async_mbarrier_arrive.rst
@@ -0,0 +1,11 @@
+..
+   This file was automatically generated. Do not edit.
+
+cp.async.mbarrier.arrive.b64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // cp.async.mbarrier.arrive.b64 [addr]; // PTX ISA 70, SM_80
+   template <typename = void>
+   __device__ static inline void cp_async_mbarrier_arrive(
+     uint64_t* addr);
diff --git a/docs/libcudacxx/ptx/instructions/generated/cp_async_mbarrier_arrive_noinc.rst b/docs/libcudacxx/ptx/instructions/generated/cp_async_mbarrier_arrive_noinc.rst
new file mode 100644
index 00000000000..31b7a2e5a2b
--- /dev/null
+++ b/docs/libcudacxx/ptx/instructions/generated/cp_async_mbarrier_arrive_noinc.rst
@@ -0,0 +1,11 @@
+..
+   This file was automatically generated. Do not edit.
+
+cp.async.mbarrier.arrive.noinc.b64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // cp.async.mbarrier.arrive.noinc.b64 [addr]; // PTX ISA 70, SM_80
+   template <typename = void>
+   __device__ static inline void cp_async_mbarrier_arrive_noinc(
+     uint64_t* addr);
diff --git a/docs/libcudacxx/ptx/instructions/generated/cp_reduce_async_bulk.rst b/docs/libcudacxx/ptx/instructions/generated/cp_reduce_async_bulk.rst
index b043eb9f456..8228b69ed41 100644
--- a/docs/libcudacxx/ptx/instructions/generated/cp_reduce_async_bulk.rst
+++ b/docs/libcudacxx/ptx/instructions/generated/cp_reduce_async_bulk.rst
@@ -10,7 +10,7 @@ cp.reduce.async.bulk.shared::cluster.shared::cta.mbarrier::complete_tx::bytes.an
    // .src       = { .shared::cta }
    // .type      = { .b32 }
    // .op        = { .and }
-   template <typename B32>
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
    __device__ static inline void cp_reduce_async_bulk(
      cuda::ptx::space_cluster_t,
      cuda::ptx::space_shared_t,
@@ -29,7 +29,7 @@ cp.reduce.async.bulk.shared::cluster.shared::cta.mbarrier::complete_tx::bytes.or
    // .src       = { .shared::cta }
    // .type      = { .b32 }
    // .op        = { .or }
-   template <typename B32>
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
    __device__ static inline void cp_reduce_async_bulk(
      cuda::ptx::space_cluster_t,
      cuda::ptx::space_shared_t,
@@ -48,7 +48,7 @@ cp.reduce.async.bulk.shared::cluster.shared::cta.mbarrier::complete_tx::bytes.xo
    // .src       = { .shared::cta }
    // .type      = { .b32 }
    // .op        = { .xor }
-   template <typename B32>
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
    __device__ static inline void cp_reduce_async_bulk(
      cuda::ptx::space_cluster_t,
      cuda::ptx::space_shared_t,
diff --git a/docs/libcudacxx/ptx/instructions/generated/elect_sync.rst b/docs/libcudacxx/ptx/instructions/generated/elect_sync.rst
new file mode 100644
index 00000000000..bc909c54319
--- /dev/null
+++ b/docs/libcudacxx/ptx/instructions/generated/elect_sync.rst
@@ -0,0 +1,11 @@
+..
+   This file was automatically generated. Do not edit.
+
+elect.sync
+^^^^^^^^^^
+.. code:: cuda
+
+   // elect.sync _|is_elected, membermask; // PTX ISA 80, SM_90
+   template <typename = void>
+   __device__ static inline bool elect_sync(
+     const uint32_t& membermask);
diff --git a/docs/libcudacxx/ptx/instructions/generated/fence.rst b/docs/libcudacxx/ptx/instructions/generated/fence.rst
index ed21fa80b6e..50137394587 100644
--- a/docs/libcudacxx/ptx/instructions/generated/fence.rst
+++ b/docs/libcudacxx/ptx/instructions/generated/fence.rst
@@ -5,94 +5,190 @@ fence.sc.cta
 ^^^^^^^^^^^^
 .. code:: cuda
 
-   // fence{.sem}.scope; // 1. PTX ISA 60, SM_70
-   // .sem       = { .sc, .acq_rel }
+   // fence.sem.scope; // 1. PTX ISA 60, SM_70
+   // .sem       = { .sc }
    // .scope     = { .cta, .gpu, .sys }
-   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   template <cuda::ptx::dot_scope Scope>
    __device__ static inline void fence(
-     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::sem_sc_t,
      cuda::ptx::scope_t<Scope> scope);
 
 fence.sc.gpu
 ^^^^^^^^^^^^
 .. code:: cuda
 
-   // fence{.sem}.scope; // 1. PTX ISA 60, SM_70
-   // .sem       = { .sc, .acq_rel }
+   // fence.sem.scope; // 1. PTX ISA 60, SM_70
+   // .sem       = { .sc }
    // .scope     = { .cta, .gpu, .sys }
-   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   template <cuda::ptx::dot_scope Scope>
    __device__ static inline void fence(
-     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::sem_sc_t,
      cuda::ptx::scope_t<Scope> scope);
 
 fence.sc.sys
 ^^^^^^^^^^^^
 .. code:: cuda
 
-   // fence{.sem}.scope; // 1. PTX ISA 60, SM_70
-   // .sem       = { .sc, .acq_rel }
+   // fence.sem.scope; // 1. PTX ISA 60, SM_70
+   // .sem       = { .sc }
    // .scope     = { .cta, .gpu, .sys }
-   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   template <cuda::ptx::dot_scope Scope>
    __device__ static inline void fence(
-     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::sem_sc_t,
      cuda::ptx::scope_t<Scope> scope);
 
+fence.sc.cluster
+^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // fence.sem.scope; // 2. PTX ISA 78, SM_90
+   // .sem       = { .sc }
+   // .scope     = { .cluster }
+   template <typename = void>
+   __device__ static inline void fence(
+     cuda::ptx::sem_sc_t,
+     cuda::ptx::scope_cluster_t);
+
 fence.acq_rel.cta
 ^^^^^^^^^^^^^^^^^
 .. code:: cuda
 
-   // fence{.sem}.scope; // 1. PTX ISA 60, SM_70
-   // .sem       = { .sc, .acq_rel }
+   // fence.sem.scope; // 1. PTX ISA 60, SM_70
+   // .sem       = { .acq_rel }
    // .scope     = { .cta, .gpu, .sys }
-   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   template <cuda::ptx::dot_scope Scope>
    __device__ static inline void fence(
-     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::sem_acq_rel_t,
      cuda::ptx::scope_t<Scope> scope);
 
 fence.acq_rel.gpu
 ^^^^^^^^^^^^^^^^^
 .. code:: cuda
 
-   // fence{.sem}.scope; // 1. PTX ISA 60, SM_70
-   // .sem       = { .sc, .acq_rel }
+   // fence.sem.scope; // 1. PTX ISA 60, SM_70
+   // .sem       = { .acq_rel }
    // .scope     = { .cta, .gpu, .sys }
-   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   template <cuda::ptx::dot_scope Scope>
    __device__ static inline void fence(
-     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::sem_acq_rel_t,
      cuda::ptx::scope_t<Scope> scope);
 
 fence.acq_rel.sys
 ^^^^^^^^^^^^^^^^^
 .. code:: cuda
 
-   // fence{.sem}.scope; // 1. PTX ISA 60, SM_70
-   // .sem       = { .sc, .acq_rel }
+   // fence.sem.scope; // 1. PTX ISA 60, SM_70
+   // .sem       = { .acq_rel }
    // .scope     = { .cta, .gpu, .sys }
-   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   template <cuda::ptx::dot_scope Scope>
    __device__ static inline void fence(
-     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::sem_acq_rel_t,
      cuda::ptx::scope_t<Scope> scope);
 
-fence.sc.cluster
-^^^^^^^^^^^^^^^^
+fence.acq_rel.cluster
+^^^^^^^^^^^^^^^^^^^^^
 .. code:: cuda
 
-   // fence{.sem}.scope; // 2. PTX ISA 78, SM_90
-   // .sem       = { .sc, .acq_rel }
+   // fence.sem.scope; // 2. PTX ISA 78, SM_90
+   // .sem       = { .acq_rel }
    // .scope     = { .cluster }
-   template <cuda::ptx::dot_sem Sem>
+   template <typename = void>
    __device__ static inline void fence(
-     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::sem_acq_rel_t,
      cuda::ptx::scope_cluster_t);
 
-fence.acq_rel.cluster
+fence.acquire.cta
+^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // fence.sem.scope; // PTX ISA 86, SM_90
+   // .sem       = { .acquire }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   template <cuda::ptx::dot_scope Scope>
+   __device__ static inline void fence(
+     cuda::ptx::sem_acquire_t,
+     cuda::ptx::scope_t<Scope> scope);
+
+fence.acquire.cluster
 ^^^^^^^^^^^^^^^^^^^^^
 .. code:: cuda
 
-   // fence{.sem}.scope; // 2. PTX ISA 78, SM_90
-   // .sem       = { .sc, .acq_rel }
-   // .scope     = { .cluster }
-   template <cuda::ptx::dot_sem Sem>
+   // fence.sem.scope; // PTX ISA 86, SM_90
+   // .sem       = { .acquire }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   template <cuda::ptx::dot_scope Scope>
    __device__ static inline void fence(
-     cuda::ptx::sem_t<Sem> sem,
-     cuda::ptx::scope_cluster_t);
+     cuda::ptx::sem_acquire_t,
+     cuda::ptx::scope_t<Scope> scope);
+
+fence.acquire.gpu
+^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // fence.sem.scope; // PTX ISA 86, SM_90
+   // .sem       = { .acquire }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   template <cuda::ptx::dot_scope Scope>
+   __device__ static inline void fence(
+     cuda::ptx::sem_acquire_t,
+     cuda::ptx::scope_t<Scope> scope);
+
+fence.acquire.sys
+^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // fence.sem.scope; // PTX ISA 86, SM_90
+   // .sem       = { .acquire }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   template <cuda::ptx::dot_scope Scope>
+   __device__ static inline void fence(
+     cuda::ptx::sem_acquire_t,
+     cuda::ptx::scope_t<Scope> scope);
+
+fence.release.cta
+^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // fence.sem.scope; // PTX ISA 86, SM_90
+   // .sem       = { .release }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   template <cuda::ptx::dot_scope Scope>
+   __device__ static inline void fence(
+     cuda::ptx::sem_release_t,
+     cuda::ptx::scope_t<Scope> scope);
+
+fence.release.cluster
+^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // fence.sem.scope; // PTX ISA 86, SM_90
+   // .sem       = { .release }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   template <cuda::ptx::dot_scope Scope>
+   __device__ static inline void fence(
+     cuda::ptx::sem_release_t,
+     cuda::ptx::scope_t<Scope> scope);
+
+fence.release.gpu
+^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // fence.sem.scope; // PTX ISA 86, SM_90
+   // .sem       = { .release }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   template <cuda::ptx::dot_scope Scope>
+   __device__ static inline void fence(
+     cuda::ptx::sem_release_t,
+     cuda::ptx::scope_t<Scope> scope);
+
+fence.release.sys
+^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // fence.sem.scope; // PTX ISA 86, SM_90
+   // .sem       = { .release }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   template <cuda::ptx::dot_scope Scope>
+   __device__ static inline void fence(
+     cuda::ptx::sem_release_t,
+     cuda::ptx::scope_t<Scope> scope);
diff --git a/docs/libcudacxx/ptx/instructions/generated/fence_proxy_async.rst b/docs/libcudacxx/ptx/instructions/generated/fence_proxy_async.rst
index 8376e96ce6b..9f4000b675e 100644
--- a/docs/libcudacxx/ptx/instructions/generated/fence_proxy_async.rst
+++ b/docs/libcudacxx/ptx/instructions/generated/fence_proxy_async.rst
@@ -13,7 +13,7 @@ fence.proxy.async.global
 ^^^^^^^^^^^^^^^^^^^^^^^^
 .. code:: cuda
 
-   // fence.proxy.async{.space}; // 6. PTX ISA 80, SM_90
+   // fence.proxy.async.space; // 6. PTX ISA 80, SM_90
    // .space     = { .global, .shared::cluster, .shared::cta }
    template <cuda::ptx::dot_space Space>
    __device__ static inline void fence_proxy_async(
@@ -23,7 +23,7 @@ fence.proxy.async.shared::cluster
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 .. code:: cuda
 
-   // fence.proxy.async{.space}; // 6. PTX ISA 80, SM_90
+   // fence.proxy.async.space; // 6. PTX ISA 80, SM_90
    // .space     = { .global, .shared::cluster, .shared::cta }
    template <cuda::ptx::dot_space Space>
    __device__ static inline void fence_proxy_async(
@@ -33,7 +33,7 @@ fence.proxy.async.shared::cta
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 .. code:: cuda
 
-   // fence.proxy.async{.space}; // 6. PTX ISA 80, SM_90
+   // fence.proxy.async.space; // 6. PTX ISA 80, SM_90
    // .space     = { .global, .shared::cluster, .shared::cta }
    template <cuda::ptx::dot_space Space>
    __device__ static inline void fence_proxy_async(
diff --git a/docs/libcudacxx/ptx/instructions/generated/fence_proxy_async_generic_sync_restrict.rst b/docs/libcudacxx/ptx/instructions/generated/fence_proxy_async_generic_sync_restrict.rst
new file mode 100644
index 00000000000..e67c4852355
--- /dev/null
+++ b/docs/libcudacxx/ptx/instructions/generated/fence_proxy_async_generic_sync_restrict.rst
@@ -0,0 +1,30 @@
+..
+   This file was automatically generated. Do not edit.
+
+fence.proxy.async::generic.acquire.sync_restrict::shared::cluster.cluster
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // fence.proxy.async::generic.sem.sync_restrict::space.scope; // PTX ISA 86, SM_90
+   // .sem       = { .acquire }
+   // .space     = { .shared::cluster }
+   // .scope     = { .cluster }
+   template <typename = void>
+   __device__ static inline void fence_proxy_async_generic_sync_restrict(
+     cuda::ptx::sem_acquire_t,
+     cuda::ptx::space_cluster_t,
+     cuda::ptx::scope_cluster_t);
+
+fence.proxy.async::generic.release.sync_restrict::shared::cta.cluster
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // fence.proxy.async::generic.sem.sync_restrict::space.scope; // PTX ISA 86, SM_90
+   // .sem       = { .release }
+   // .space     = { .shared::cta }
+   // .scope     = { .cluster }
+   template <typename = void>
+   __device__ static inline void fence_proxy_async_generic_sync_restrict(
+     cuda::ptx::sem_release_t,
+     cuda::ptx::space_shared_t,
+     cuda::ptx::scope_cluster_t);
diff --git a/docs/libcudacxx/ptx/instructions/generated/fence_sync_restrict.rst b/docs/libcudacxx/ptx/instructions/generated/fence_sync_restrict.rst
new file mode 100644
index 00000000000..bae82190e25
--- /dev/null
+++ b/docs/libcudacxx/ptx/instructions/generated/fence_sync_restrict.rst
@@ -0,0 +1,30 @@
+..
+   This file was automatically generated. Do not edit.
+
+fence.acquire.sync_restrict::shared::cluster.cluster
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // fence.sem.sync_restrict::space.scope; // PTX ISA 86, SM_90
+   // .sem       = { .acquire }
+   // .space     = { .shared::cluster }
+   // .scope     = { .cluster }
+   template <typename = void>
+   __device__ static inline void fence_sync_restrict(
+     cuda::ptx::sem_acquire_t,
+     cuda::ptx::space_cluster_t,
+     cuda::ptx::scope_cluster_t);
+
+fence.release.sync_restrict::shared::cta.cluster
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // fence.sem.sync_restrict::space.scope; // PTX ISA 86, SM_90
+   // .sem       = { .release }
+   // .space     = { .shared::cta }
+   // .scope     = { .cluster }
+   template <typename = void>
+   __device__ static inline void fence_sync_restrict(
+     cuda::ptx::sem_release_t,
+     cuda::ptx::space_shared_t,
+     cuda::ptx::scope_cluster_t);
diff --git a/docs/libcudacxx/ptx/instructions/generated/special_registers.rst b/docs/libcudacxx/ptx/instructions/generated/get_sreg.rst
similarity index 83%
rename from docs/libcudacxx/ptx/instructions/generated/special_registers.rst
rename to docs/libcudacxx/ptx/instructions/generated/get_sreg.rst
index aa1add84781..9582c4384ff 100644
--- a/docs/libcudacxx/ptx/instructions/generated/special_registers.rst
+++ b/docs/libcudacxx/ptx/instructions/generated/get_sreg.rst
@@ -1,9 +1,12 @@
+..
+   This file was automatically generated. Do not edit.
+
 tid.x
 ^^^^^
 .. code:: cuda
 
    // mov.u32 sreg_value, %%tid.x; // PTX ISA 20
-   template <typename=void>
+   template <typename = void>
    __device__ static inline uint32_t get_sreg_tid_x();
 
 tid.y
@@ -11,7 +14,7 @@ tid.y
 .. code:: cuda
 
    // mov.u32 sreg_value, %%tid.y; // PTX ISA 20
-   template <typename=void>
+   template <typename = void>
    __device__ static inline uint32_t get_sreg_tid_y();
 
 tid.z
@@ -19,7 +22,7 @@ tid.z
 .. code:: cuda
 
    // mov.u32 sreg_value, %%tid.z; // PTX ISA 20
-   template <typename=void>
+   template <typename = void>
    __device__ static inline uint32_t get_sreg_tid_z();
 
 ntid.x
@@ -27,7 +30,7 @@ ntid.x
 .. code:: cuda
 
    // mov.u32 sreg_value, %%ntid.x; // PTX ISA 20
-   template <typename=void>
+   template <typename = void>
    __device__ static inline uint32_t get_sreg_ntid_x();
 
 ntid.y
@@ -35,7 +38,7 @@ ntid.y
 .. code:: cuda
 
    // mov.u32 sreg_value, %%ntid.y; // PTX ISA 20
-   template <typename=void>
+   template <typename = void>
    __device__ static inline uint32_t get_sreg_ntid_y();
 
 ntid.z
@@ -43,7 +46,7 @@ ntid.z
 .. code:: cuda
 
    // mov.u32 sreg_value, %%ntid.z; // PTX ISA 20
-   template <typename=void>
+   template <typename = void>
    __device__ static inline uint32_t get_sreg_ntid_z();
 
 laneid
@@ -51,7 +54,7 @@ laneid
 .. code:: cuda
 
    // mov.u32 sreg_value, %%laneid; // PTX ISA 13
-   template <typename=void>
+   template <typename = void>
    __device__ static inline uint32_t get_sreg_laneid();
 
 warpid
@@ -59,7 +62,7 @@ warpid
 .. code:: cuda
 
    // mov.u32 sreg_value, %%warpid; // PTX ISA 13
-   template <typename=void>
+   template <typename = void>
    __device__ static inline uint32_t get_sreg_warpid();
 
 nwarpid
@@ -67,7 +70,7 @@ nwarpid
 .. code:: cuda
 
    // mov.u32 sreg_value, %%nwarpid; // PTX ISA 20, SM_35
-   template <typename=void>
+   template <typename = void>
    __device__ static inline uint32_t get_sreg_nwarpid();
 
 ctaid.x
@@ -75,7 +78,7 @@ ctaid.x
 .. code:: cuda
 
    // mov.u32 sreg_value, %%ctaid.x; // PTX ISA 20
-   template <typename=void>
+   template <typename = void>
    __device__ static inline uint32_t get_sreg_ctaid_x();
 
 ctaid.y
@@ -83,7 +86,7 @@ ctaid.y
 .. code:: cuda
 
    // mov.u32 sreg_value, %%ctaid.y; // PTX ISA 20
-   template <typename=void>
+   template <typename = void>
    __device__ static inline uint32_t get_sreg_ctaid_y();
 
 ctaid.z
@@ -91,7 +94,7 @@ ctaid.z
 .. code:: cuda
 
    // mov.u32 sreg_value, %%ctaid.z; // PTX ISA 20
-   template <typename=void>
+   template <typename = void>
    __device__ static inline uint32_t get_sreg_ctaid_z();
 
 nctaid.x
@@ -99,7 +102,7 @@ nctaid.x
 .. code:: cuda
 
    // mov.u32 sreg_value, %%nctaid.x; // PTX ISA 20
-   template <typename=void>
+   template <typename = void>
    __device__ static inline uint32_t get_sreg_nctaid_x();
 
 nctaid.y
@@ -107,7 +110,7 @@ nctaid.y
 .. code:: cuda
 
    // mov.u32 sreg_value, %%nctaid.y; // PTX ISA 20
-   template <typename=void>
+   template <typename = void>
    __device__ static inline uint32_t get_sreg_nctaid_y();
 
 nctaid.z
@@ -115,7 +118,7 @@ nctaid.z
 .. code:: cuda
 
    // mov.u32 sreg_value, %%nctaid.z; // PTX ISA 20
-   template <typename=void>
+   template <typename = void>
    __device__ static inline uint32_t get_sreg_nctaid_z();
 
 smid
@@ -123,7 +126,7 @@ smid
 .. code:: cuda
 
    // mov.u32 sreg_value, %%smid; // PTX ISA 13
-   template <typename=void>
+   template <typename = void>
    __device__ static inline uint32_t get_sreg_smid();
 
 nsmid
@@ -131,7 +134,7 @@ nsmid
 .. code:: cuda
 
    // mov.u32 sreg_value, %%nsmid; // PTX ISA 20, SM_35
-   template <typename=void>
+   template <typename = void>
    __device__ static inline uint32_t get_sreg_nsmid();
 
 gridid
@@ -139,7 +142,7 @@ gridid
 .. code:: cuda
 
    // mov.u64 sreg_value, %%gridid; // PTX ISA 30
-   template <typename=void>
+   template <typename = void>
    __device__ static inline uint64_t get_sreg_gridid();
 
 is_explicit_cluster
@@ -147,7 +150,7 @@ is_explicit_cluster
 .. code:: cuda
 
    // mov.pred sreg_value, %%is_explicit_cluster; // PTX ISA 78, SM_90
-   template <typename=void>
+   template <typename = void>
    __device__ static inline bool get_sreg_is_explicit_cluster();
 
 clusterid.x
@@ -155,7 +158,7 @@ clusterid.x
 .. code:: cuda
 
    // mov.u32 sreg_value, %%clusterid.x; // PTX ISA 78, SM_90
-   template <typename=void>
+   template <typename = void>
    __device__ static inline uint32_t get_sreg_clusterid_x();
 
 clusterid.y
@@ -163,7 +166,7 @@ clusterid.y
 .. code:: cuda
 
    // mov.u32 sreg_value, %%clusterid.y; // PTX ISA 78, SM_90
-   template <typename=void>
+   template <typename = void>
    __device__ static inline uint32_t get_sreg_clusterid_y();
 
 clusterid.z
@@ -171,7 +174,7 @@ clusterid.z
 .. code:: cuda
 
    // mov.u32 sreg_value, %%clusterid.z; // PTX ISA 78, SM_90
-   template <typename=void>
+   template <typename = void>
    __device__ static inline uint32_t get_sreg_clusterid_z();
 
 nclusterid.x
@@ -179,7 +182,7 @@ nclusterid.x
 .. code:: cuda
 
    // mov.u32 sreg_value, %%nclusterid.x; // PTX ISA 78, SM_90
-   template <typename=void>
+   template <typename = void>
    __device__ static inline uint32_t get_sreg_nclusterid_x();
 
 nclusterid.y
@@ -187,7 +190,7 @@ nclusterid.y
 .. code:: cuda
 
    // mov.u32 sreg_value, %%nclusterid.y; // PTX ISA 78, SM_90
-   template <typename=void>
+   template <typename = void>
    __device__ static inline uint32_t get_sreg_nclusterid_y();
 
 nclusterid.z
@@ -195,7 +198,7 @@ nclusterid.z
 .. code:: cuda
 
    // mov.u32 sreg_value, %%nclusterid.z; // PTX ISA 78, SM_90
-   template <typename=void>
+   template <typename = void>
    __device__ static inline uint32_t get_sreg_nclusterid_z();
 
 cluster_ctaid.x
@@ -203,7 +206,7 @@ cluster_ctaid.x
 .. code:: cuda
 
    // mov.u32 sreg_value, %%cluster_ctaid.x; // PTX ISA 78, SM_90
-   template <typename=void>
+   template <typename = void>
    __device__ static inline uint32_t get_sreg_cluster_ctaid_x();
 
 cluster_ctaid.y
@@ -211,7 +214,7 @@ cluster_ctaid.y
 .. code:: cuda
 
    // mov.u32 sreg_value, %%cluster_ctaid.y; // PTX ISA 78, SM_90
-   template <typename=void>
+   template <typename = void>
    __device__ static inline uint32_t get_sreg_cluster_ctaid_y();
 
 cluster_ctaid.z
@@ -219,7 +222,7 @@ cluster_ctaid.z
 .. code:: cuda
 
    // mov.u32 sreg_value, %%cluster_ctaid.z; // PTX ISA 78, SM_90
-   template <typename=void>
+   template <typename = void>
    __device__ static inline uint32_t get_sreg_cluster_ctaid_z();
 
 cluster_nctaid.x
@@ -227,7 +230,7 @@ cluster_nctaid.x
 .. code:: cuda
 
    // mov.u32 sreg_value, %%cluster_nctaid.x; // PTX ISA 78, SM_90
-   template <typename=void>
+   template <typename = void>
    __device__ static inline uint32_t get_sreg_cluster_nctaid_x();
 
 cluster_nctaid.y
@@ -235,7 +238,7 @@ cluster_nctaid.y
 .. code:: cuda
 
    // mov.u32 sreg_value, %%cluster_nctaid.y; // PTX ISA 78, SM_90
-   template <typename=void>
+   template <typename = void>
    __device__ static inline uint32_t get_sreg_cluster_nctaid_y();
 
 cluster_nctaid.z
@@ -243,7 +246,7 @@ cluster_nctaid.z
 .. code:: cuda
 
    // mov.u32 sreg_value, %%cluster_nctaid.z; // PTX ISA 78, SM_90
-   template <typename=void>
+   template <typename = void>
    __device__ static inline uint32_t get_sreg_cluster_nctaid_z();
 
 cluster_ctarank
@@ -251,7 +254,7 @@ cluster_ctarank
 .. code:: cuda
 
    // mov.u32 sreg_value, %%cluster_ctarank; // PTX ISA 78, SM_90
-   template <typename=void>
+   template <typename = void>
    __device__ static inline uint32_t get_sreg_cluster_ctarank();
 
 cluster_nctarank
@@ -259,7 +262,7 @@ cluster_nctarank
 .. code:: cuda
 
    // mov.u32 sreg_value, %%cluster_nctarank; // PTX ISA 78, SM_90
-   template <typename=void>
+   template <typename = void>
    __device__ static inline uint32_t get_sreg_cluster_nctarank();
 
 lanemask_eq
@@ -267,7 +270,7 @@ lanemask_eq
 .. code:: cuda
 
    // mov.u32 sreg_value, %%lanemask_eq; // PTX ISA 20, SM_35
-   template <typename=void>
+   template <typename = void>
    __device__ static inline uint32_t get_sreg_lanemask_eq();
 
 lanemask_le
@@ -275,7 +278,7 @@ lanemask_le
 .. code:: cuda
 
    // mov.u32 sreg_value, %%lanemask_le; // PTX ISA 20, SM_35
-   template <typename=void>
+   template <typename = void>
    __device__ static inline uint32_t get_sreg_lanemask_le();
 
 lanemask_lt
@@ -283,7 +286,7 @@ lanemask_lt
 .. code:: cuda
 
    // mov.u32 sreg_value, %%lanemask_lt; // PTX ISA 20, SM_35
-   template <typename=void>
+   template <typename = void>
    __device__ static inline uint32_t get_sreg_lanemask_lt();
 
 lanemask_ge
@@ -291,7 +294,7 @@ lanemask_ge
 .. code:: cuda
 
    // mov.u32 sreg_value, %%lanemask_ge; // PTX ISA 20, SM_35
-   template <typename=void>
+   template <typename = void>
    __device__ static inline uint32_t get_sreg_lanemask_ge();
 
 lanemask_gt
@@ -299,7 +302,7 @@ lanemask_gt
 .. code:: cuda
 
    // mov.u32 sreg_value, %%lanemask_gt; // PTX ISA 20, SM_35
-   template <typename=void>
+   template <typename = void>
    __device__ static inline uint32_t get_sreg_lanemask_gt();
 
 clock
@@ -307,7 +310,7 @@ clock
 .. code:: cuda
 
    // mov.u32 sreg_value, %%clock; // PTX ISA 10
-   template <typename=void>
+   template <typename = void>
    __device__ static inline uint32_t get_sreg_clock();
 
 clock_hi
@@ -315,7 +318,7 @@ clock_hi
 .. code:: cuda
 
    // mov.u32 sreg_value, %%clock_hi; // PTX ISA 50, SM_35
-   template <typename=void>
+   template <typename = void>
    __device__ static inline uint32_t get_sreg_clock_hi();
 
 clock64
@@ -323,7 +326,7 @@ clock64
 .. code:: cuda
 
    // mov.u64 sreg_value, %%clock64; // PTX ISA 20, SM_35
-   template <typename=void>
+   template <typename = void>
    __device__ static inline uint64_t get_sreg_clock64();
 
 globaltimer
@@ -331,7 +334,7 @@ globaltimer
 .. code:: cuda
 
    // mov.u64 sreg_value, %%globaltimer; // PTX ISA 31, SM_35
-   template <typename=void>
+   template <typename = void>
    __device__ static inline uint64_t get_sreg_globaltimer();
 
 globaltimer_lo
@@ -339,7 +342,7 @@ globaltimer_lo
 .. code:: cuda
 
    // mov.u32 sreg_value, %%globaltimer_lo; // PTX ISA 31, SM_35
-   template <typename=void>
+   template <typename = void>
    __device__ static inline uint32_t get_sreg_globaltimer_lo();
 
 globaltimer_hi
@@ -347,7 +350,7 @@ globaltimer_hi
 .. code:: cuda
 
    // mov.u32 sreg_value, %%globaltimer_hi; // PTX ISA 31, SM_35
-   template <typename=void>
+   template <typename = void>
    __device__ static inline uint32_t get_sreg_globaltimer_hi();
 
 total_smem_size
@@ -355,7 +358,7 @@ total_smem_size
 .. code:: cuda
 
    // mov.u32 sreg_value, %%total_smem_size; // PTX ISA 41, SM_35
-   template <typename=void>
+   template <typename = void>
    __device__ static inline uint32_t get_sreg_total_smem_size();
 
 aggr_smem_size
@@ -363,7 +366,7 @@ aggr_smem_size
 .. code:: cuda
 
    // mov.u32 sreg_value, %%aggr_smem_size; // PTX ISA 81, SM_90
-   template <typename=void>
+   template <typename = void>
    __device__ static inline uint32_t get_sreg_aggr_smem_size();
 
 dynamic_smem_size
@@ -371,7 +374,7 @@ dynamic_smem_size
 .. code:: cuda
 
    // mov.u32 sreg_value, %%dynamic_smem_size; // PTX ISA 41, SM_35
-   template <typename=void>
+   template <typename = void>
    __device__ static inline uint32_t get_sreg_dynamic_smem_size();
 
 current_graph_exec
@@ -379,5 +382,5 @@ current_graph_exec
 .. code:: cuda
 
    // mov.u64 sreg_value, %%current_graph_exec; // PTX ISA 80, SM_50
-   template <typename=void>
+   template <typename = void>
    __device__ static inline uint64_t get_sreg_current_graph_exec();
diff --git a/docs/libcudacxx/ptx/instructions/generated/getctarank.rst b/docs/libcudacxx/ptx/instructions/generated/getctarank.rst
index 374c182576f..19b3783086c 100644
--- a/docs/libcudacxx/ptx/instructions/generated/getctarank.rst
+++ b/docs/libcudacxx/ptx/instructions/generated/getctarank.rst
@@ -5,7 +5,7 @@ getctarank.shared::cluster.u32
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 .. code:: cuda
 
-   // getctarank{.space}.u32 dest, addr; // PTX ISA 78, SM_90
+   // getctarank.space.u32 dest, addr; // PTX ISA 78, SM_90
    // .space     = { .shared::cluster }
    template <typename = void>
    __device__ static inline uint32_t getctarank(
diff --git a/docs/libcudacxx/ptx/instructions/generated/mapa.rst b/docs/libcudacxx/ptx/instructions/generated/mapa.rst
new file mode 100644
index 00000000000..4ffc70d85d9
--- /dev/null
+++ b/docs/libcudacxx/ptx/instructions/generated/mapa.rst
@@ -0,0 +1,14 @@
+..
+   This file was automatically generated. Do not edit.
+
+mapa.shared::cluster.u32
+^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // mapa.space.u32  dest, addr, target_cta; // PTX ISA 78, SM_90
+   // .space     = { .shared::cluster }
+   template <typename Tp>
+   __device__ static inline Tp* mapa(
+     cuda::ptx::space_cluster_t,
+     const Tp* addr,
+     uint32_t target_cta);
diff --git a/docs/libcudacxx/ptx/instructions/generated/mbarrier_arrive.rst b/docs/libcudacxx/ptx/instructions/generated/mbarrier_arrive.rst
index 21436e2b3ca..fea199e4747 100644
--- a/docs/libcudacxx/ptx/instructions/generated/mbarrier_arrive.rst
+++ b/docs/libcudacxx/ptx/instructions/generated/mbarrier_arrive.rst
@@ -24,7 +24,7 @@ mbarrier.arrive.release.cta.shared::cta.b64
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 .. code:: cuda
 
-   // mbarrier.arrive{.sem}{.scope}{.space}.b64                   state,  [addr];           // 3a.  PTX ISA 80, SM_90
+   // mbarrier.arrive.sem.scope.space.b64                   state,  [addr];           // 3a.  PTX ISA 80, SM_90
    // .sem       = { .release }
    // .scope     = { .cta, .cluster }
    // .space     = { .shared::cta }
@@ -39,7 +39,7 @@ mbarrier.arrive.release.cluster.shared::cta.b64
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 .. code:: cuda
 
-   // mbarrier.arrive{.sem}{.scope}{.space}.b64                   state,  [addr];           // 3a.  PTX ISA 80, SM_90
+   // mbarrier.arrive.sem.scope.space.b64                   state,  [addr];           // 3a.  PTX ISA 80, SM_90
    // .sem       = { .release }
    // .scope     = { .cta, .cluster }
    // .space     = { .shared::cta }
@@ -54,7 +54,7 @@ mbarrier.arrive.release.cta.shared::cta.b64
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 .. code:: cuda
 
-   // mbarrier.arrive{.sem}{.scope}{.space}.b64                   state,  [addr], count;    // 3b.  PTX ISA 80, SM_90
+   // mbarrier.arrive.sem.scope.space.b64                   state,  [addr], count;    // 3b.  PTX ISA 80, SM_90
    // .sem       = { .release }
    // .scope     = { .cta, .cluster }
    // .space     = { .shared::cta }
@@ -70,7 +70,7 @@ mbarrier.arrive.release.cluster.shared::cta.b64
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 .. code:: cuda
 
-   // mbarrier.arrive{.sem}{.scope}{.space}.b64                   state,  [addr], count;    // 3b.  PTX ISA 80, SM_90
+   // mbarrier.arrive.sem.scope.space.b64                   state,  [addr], count;    // 3b.  PTX ISA 80, SM_90
    // .sem       = { .release }
    // .scope     = { .cta, .cluster }
    // .space     = { .shared::cta }
@@ -86,7 +86,7 @@ mbarrier.arrive.release.cluster.shared::cluster.b64
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 .. code:: cuda
 
-   // mbarrier.arrive{.sem}{.scope}{.space}.b64                   _, [addr];                // 4a.  PTX ISA 80, SM_90
+   // mbarrier.arrive.sem.scope.space.b64                   _, [addr];                // 4a.  PTX ISA 80, SM_90
    // .sem       = { .release }
    // .scope     = { .cluster }
    // .space     = { .shared::cluster }
@@ -101,7 +101,7 @@ mbarrier.arrive.release.cluster.shared::cluster.b64
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 .. code:: cuda
 
-   // mbarrier.arrive{.sem}{.scope}{.space}.b64                   _, [addr], count;         // 4b.  PTX ISA 80, SM_90
+   // mbarrier.arrive.sem.scope.space.b64                   _, [addr], count;         // 4b.  PTX ISA 80, SM_90
    // .sem       = { .release }
    // .scope     = { .cluster }
    // .space     = { .shared::cluster }
@@ -112,3 +112,96 @@ mbarrier.arrive.release.cluster.shared::cluster.b64
      cuda::ptx::space_cluster_t,
      uint64_t* addr,
      const uint32_t& count);
+
+mbarrier.arrive.relaxed.cta.shared::cta.b64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // mbarrier.arrive.sem.scope.space.b64 state, [addr], count; // PTX ISA 86, SM_90
+   // .space     = { .shared::cta }
+   // .sem       = { .relaxed }
+   // .scope     = { .cta, .cluster }
+   template <cuda::ptx::dot_scope Scope>
+   __device__ static inline uint64_t mbarrier_arrive(
+     cuda::ptx::space_shared_t,
+     cuda::ptx::sem_relaxed_t,
+     cuda::ptx::scope_t<Scope> scope,
+     uint64_t* addr,
+     const uint32_t& count);
+
+mbarrier.arrive.relaxed.cluster.shared::cta.b64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // mbarrier.arrive.sem.scope.space.b64 state, [addr], count; // PTX ISA 86, SM_90
+   // .space     = { .shared::cta }
+   // .sem       = { .relaxed }
+   // .scope     = { .cta, .cluster }
+   template <cuda::ptx::dot_scope Scope>
+   __device__ static inline uint64_t mbarrier_arrive(
+     cuda::ptx::space_shared_t,
+     cuda::ptx::sem_relaxed_t,
+     cuda::ptx::scope_t<Scope> scope,
+     uint64_t* addr,
+     const uint32_t& count);
+
+mbarrier.arrive.relaxed.cta.shared::cta.b64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // mbarrier.arrive.sem.scope.space.b64 state, [addr]; // PTX ISA 86, SM_90
+   // .space     = { .shared::cta }
+   // .sem       = { .relaxed }
+   // .scope     = { .cta, .cluster }
+   template <cuda::ptx::dot_scope Scope>
+   __device__ static inline uint64_t mbarrier_arrive(
+     cuda::ptx::space_shared_t,
+     cuda::ptx::sem_relaxed_t,
+     cuda::ptx::scope_t<Scope> scope,
+     uint64_t* addr);
+
+mbarrier.arrive.relaxed.cluster.shared::cta.b64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // mbarrier.arrive.sem.scope.space.b64 state, [addr]; // PTX ISA 86, SM_90
+   // .space     = { .shared::cta }
+   // .sem       = { .relaxed }
+   // .scope     = { .cta, .cluster }
+   template <cuda::ptx::dot_scope Scope>
+   __device__ static inline uint64_t mbarrier_arrive(
+     cuda::ptx::space_shared_t,
+     cuda::ptx::sem_relaxed_t,
+     cuda::ptx::scope_t<Scope> scope,
+     uint64_t* addr);
+
+mbarrier.arrive.relaxed.cluster.shared::cluster.b64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // mbarrier.arrive.sem.scope.space.b64 _, [addr], count; // PTX ISA 86, SM_90
+   // .space     = { .shared::cluster }
+   // .sem       = { .relaxed }
+   // .scope     = { .cluster }
+   template <typename = void>
+   __device__ static inline void mbarrier_arrive(
+     cuda::ptx::space_cluster_t,
+     cuda::ptx::sem_relaxed_t,
+     cuda::ptx::scope_cluster_t,
+     uint64_t* addr,
+     const uint32_t& count);
+
+mbarrier.arrive.relaxed.cluster.shared::cluster.b64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // mbarrier.arrive.sem.scope.space.b64 _, [addr]; // PTX ISA 86, SM_90
+   // .space     = { .shared::cluster }
+   // .sem       = { .relaxed }
+   // .scope     = { .cluster }
+   template <typename = void>
+   __device__ static inline void mbarrier_arrive(
+     cuda::ptx::space_cluster_t,
+     cuda::ptx::sem_relaxed_t,
+     cuda::ptx::scope_cluster_t,
+     uint64_t* addr);
diff --git a/docs/libcudacxx/ptx/instructions/generated/mbarrier_arrive_expect_tx.rst b/docs/libcudacxx/ptx/instructions/generated/mbarrier_arrive_expect_tx.rst
index 47c56eca31a..318a7eb5b98 100644
--- a/docs/libcudacxx/ptx/instructions/generated/mbarrier_arrive_expect_tx.rst
+++ b/docs/libcudacxx/ptx/instructions/generated/mbarrier_arrive_expect_tx.rst
@@ -5,7 +5,7 @@ mbarrier.arrive.expect_tx.release.cta.shared::cta.b64
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 .. code:: cuda
 
-   // mbarrier.arrive.expect_tx{.sem}{.scope}{.space}.b64 state, [addr], tx_count; // 8.  PTX ISA 80, SM_90
+   // mbarrier.arrive.expect_tx.sem.scope.space.b64 state, [addr], tx_count; // 8.  PTX ISA 80, SM_90
    // .sem       = { .release }
    // .scope     = { .cta, .cluster }
    // .space     = { .shared::cta }
@@ -21,7 +21,7 @@ mbarrier.arrive.expect_tx.release.cluster.shared::cta.b64
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 .. code:: cuda
 
-   // mbarrier.arrive.expect_tx{.sem}{.scope}{.space}.b64 state, [addr], tx_count; // 8.  PTX ISA 80, SM_90
+   // mbarrier.arrive.expect_tx.sem.scope.space.b64 state, [addr], tx_count; // 8.  PTX ISA 80, SM_90
    // .sem       = { .release }
    // .scope     = { .cta, .cluster }
    // .space     = { .shared::cta }
@@ -37,7 +37,7 @@ mbarrier.arrive.expect_tx.release.cluster.shared::cluster.b64
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 .. code:: cuda
 
-   // mbarrier.arrive.expect_tx{.sem}{.scope}{.space}.b64   _, [addr], tx_count; // 9.  PTX ISA 80, SM_90
+   // mbarrier.arrive.expect_tx.sem.scope.space.b64   _, [addr], tx_count; // 9.  PTX ISA 80, SM_90
    // .sem       = { .release }
    // .scope     = { .cluster }
    // .space     = { .shared::cluster }
@@ -48,3 +48,51 @@ mbarrier.arrive.expect_tx.release.cluster.shared::cluster.b64
      cuda::ptx::space_cluster_t,
      uint64_t* addr,
      const uint32_t& tx_count);
+
+mbarrier.arrive.expect_tx.relaxed.cta.shared::cta.b64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // mbarrier.arrive.expect_tx.sem.scope.space.b64 state, [addr], txCount; // PTX ISA 86, SM_90
+   // .space     = { .shared::cta }
+   // .sem       = { .relaxed }
+   // .scope     = { .cta, .cluster }
+   template <cuda::ptx::dot_scope Scope>
+   __device__ static inline uint64_t mbarrier_arrive_expect_tx(
+     cuda::ptx::space_shared_t,
+     cuda::ptx::sem_relaxed_t,
+     cuda::ptx::scope_t<Scope> scope,
+     uint64_t* addr,
+     const uint32_t& txCount);
+
+mbarrier.arrive.expect_tx.relaxed.cluster.shared::cta.b64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // mbarrier.arrive.expect_tx.sem.scope.space.b64 state, [addr], txCount; // PTX ISA 86, SM_90
+   // .space     = { .shared::cta }
+   // .sem       = { .relaxed }
+   // .scope     = { .cta, .cluster }
+   template <cuda::ptx::dot_scope Scope>
+   __device__ static inline uint64_t mbarrier_arrive_expect_tx(
+     cuda::ptx::space_shared_t,
+     cuda::ptx::sem_relaxed_t,
+     cuda::ptx::scope_t<Scope> scope,
+     uint64_t* addr,
+     const uint32_t& txCount);
+
+mbarrier.arrive.expect_tx.relaxed.cluster.shared::cluster.b64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // mbarrier.arrive.expect_tx.sem.scope.space.b64 _, [addr], txCount; // PTX ISA 86, SM_90
+   // .space     = { .shared::cluster }
+   // .sem       = { .relaxed }
+   // .scope     = { .cluster }
+   template <typename = void>
+   __device__ static inline void mbarrier_arrive_expect_tx(
+     cuda::ptx::space_cluster_t,
+     cuda::ptx::sem_relaxed_t,
+     cuda::ptx::scope_cluster_t,
+     uint64_t* addr,
+     const uint32_t& txCount);
diff --git a/docs/libcudacxx/ptx/instructions/generated/mbarrier_test_wait.rst b/docs/libcudacxx/ptx/instructions/generated/mbarrier_test_wait.rst
index d16b2ac07ac..88ec36b43ac 100644
--- a/docs/libcudacxx/ptx/instructions/generated/mbarrier_test_wait.rst
+++ b/docs/libcudacxx/ptx/instructions/generated/mbarrier_test_wait.rst
@@ -15,7 +15,7 @@ mbarrier.test_wait.acquire.cta.shared::cta.b64
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 .. code:: cuda
 
-   // mbarrier.test_wait{.sem}{.scope}.shared::cta.b64        waitComplete, [addr], state;                        // 2.   PTX ISA 80, SM_90
+   // mbarrier.test_wait.sem.scope.shared::cta.b64        waitComplete, [addr], state;                        // 2.   PTX ISA 80, SM_90
    // .sem       = { .acquire }
    // .scope     = { .cta, .cluster }
    template <cuda::ptx::dot_scope Scope>
@@ -29,7 +29,7 @@ mbarrier.test_wait.acquire.cluster.shared::cta.b64
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 .. code:: cuda
 
-   // mbarrier.test_wait{.sem}{.scope}.shared::cta.b64        waitComplete, [addr], state;                        // 2.   PTX ISA 80, SM_90
+   // mbarrier.test_wait.sem.scope.shared::cta.b64        waitComplete, [addr], state;                        // 2.   PTX ISA 80, SM_90
    // .sem       = { .acquire }
    // .scope     = { .cta, .cluster }
    template <cuda::ptx::dot_scope Scope>
@@ -38,3 +38,33 @@ mbarrier.test_wait.acquire.cluster.shared::cta.b64
      cuda::ptx::scope_t<Scope> scope,
      uint64_t* addr,
      const uint64_t& state);
+
+mbarrier.test_wait.relaxed.cta.shared::cta.b64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // mbarrier.test_wait.sem.scope.shared::cta.b64 waitComplete, [addr], state; // PTX ISA 86, SM_90
+   // .sem       = { .relaxed }
+   // .scope     = { .cta, .cluster }
+   template <cuda::ptx::dot_scope Scope>
+   __device__ static inline void mbarrier_test_wait(
+     cuda::ptx::sem_relaxed_t,
+     cuda::ptx::scope_t<Scope> scope,
+     bool waitComplete,
+     uint64_t* addr,
+     const uint64_t& state);
+
+mbarrier.test_wait.relaxed.cluster.shared::cta.b64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // mbarrier.test_wait.sem.scope.shared::cta.b64 waitComplete, [addr], state; // PTX ISA 86, SM_90
+   // .sem       = { .relaxed }
+   // .scope     = { .cta, .cluster }
+   template <cuda::ptx::dot_scope Scope>
+   __device__ static inline void mbarrier_test_wait(
+     cuda::ptx::sem_relaxed_t,
+     cuda::ptx::scope_t<Scope> scope,
+     bool waitComplete,
+     uint64_t* addr,
+     const uint64_t& state);
diff --git a/docs/libcudacxx/ptx/instructions/generated/mbarrier_test_wait_parity.rst b/docs/libcudacxx/ptx/instructions/generated/mbarrier_test_wait_parity.rst
index ec464b3398b..1496d6cbccb 100644
--- a/docs/libcudacxx/ptx/instructions/generated/mbarrier_test_wait_parity.rst
+++ b/docs/libcudacxx/ptx/instructions/generated/mbarrier_test_wait_parity.rst
@@ -15,7 +15,7 @@ mbarrier.test_wait.parity.acquire.cta.shared::cta.b64
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 .. code:: cuda
 
-   // mbarrier.test_wait.parity{.sem}{.scope}.shared::cta.b64 waitComplete, [addr], phaseParity;                  // 4.  PTX ISA 80, SM_90
+   // mbarrier.test_wait.parity.sem.scope.shared::cta.b64 waitComplete, [addr], phaseParity;                  // 4.  PTX ISA 80, SM_90
    // .sem       = { .acquire }
    // .scope     = { .cta, .cluster }
    template <cuda::ptx::dot_scope Scope>
@@ -29,7 +29,7 @@ mbarrier.test_wait.parity.acquire.cluster.shared::cta.b64
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 .. code:: cuda
 
-   // mbarrier.test_wait.parity{.sem}{.scope}.shared::cta.b64 waitComplete, [addr], phaseParity;                  // 4.  PTX ISA 80, SM_90
+   // mbarrier.test_wait.parity.sem.scope.shared::cta.b64 waitComplete, [addr], phaseParity;                  // 4.  PTX ISA 80, SM_90
    // .sem       = { .acquire }
    // .scope     = { .cta, .cluster }
    template <cuda::ptx::dot_scope Scope>
@@ -38,3 +38,33 @@ mbarrier.test_wait.parity.acquire.cluster.shared::cta.b64
      cuda::ptx::scope_t<Scope> scope,
      uint64_t* addr,
      const uint32_t& phaseParity);
+
+mbarrier.test_wait.parity.relaxed.cta.shared::cta.b64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // mbarrier.test_wait.parity.sem.scope.shared::cta.b64 waitComplete, [addr], phaseParity; // PTX ISA 86, SM_90
+   // .sem       = { .relaxed }
+   // .scope     = { .cta, .cluster }
+   template <cuda::ptx::dot_scope Scope>
+   __device__ static inline void mbarrier_test_wait_parity(
+     cuda::ptx::sem_relaxed_t,
+     cuda::ptx::scope_t<Scope> scope,
+     bool waitComplete,
+     uint64_t* addr,
+     const uint32_t& phaseParity);
+
+mbarrier.test_wait.parity.relaxed.cluster.shared::cta.b64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // mbarrier.test_wait.parity.sem.scope.shared::cta.b64 waitComplete, [addr], phaseParity; // PTX ISA 86, SM_90
+   // .sem       = { .relaxed }
+   // .scope     = { .cta, .cluster }
+   template <cuda::ptx::dot_scope Scope>
+   __device__ static inline void mbarrier_test_wait_parity(
+     cuda::ptx::sem_relaxed_t,
+     cuda::ptx::scope_t<Scope> scope,
+     bool waitComplete,
+     uint64_t* addr,
+     const uint32_t& phaseParity);
diff --git a/docs/libcudacxx/ptx/instructions/generated/mbarrier_try_wait.rst b/docs/libcudacxx/ptx/instructions/generated/mbarrier_try_wait.rst
index 3dfdba46861..4d319a5b1e3 100644
--- a/docs/libcudacxx/ptx/instructions/generated/mbarrier_try_wait.rst
+++ b/docs/libcudacxx/ptx/instructions/generated/mbarrier_try_wait.rst
@@ -26,7 +26,7 @@ mbarrier.try_wait.acquire.cta.shared::cta.b64
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 .. code:: cuda
 
-   // mbarrier.try_wait{.sem}{.scope}.shared::cta.b64         waitComplete, [addr], state;                        // 6a.  PTX ISA 80, SM_90
+   // mbarrier.try_wait.sem.scope.shared::cta.b64         waitComplete, [addr], state;                        // 6a.  PTX ISA 80, SM_90
    // .sem       = { .acquire }
    // .scope     = { .cta, .cluster }
    template <cuda::ptx::dot_scope Scope>
@@ -40,7 +40,7 @@ mbarrier.try_wait.acquire.cluster.shared::cta.b64
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 .. code:: cuda
 
-   // mbarrier.try_wait{.sem}{.scope}.shared::cta.b64         waitComplete, [addr], state;                        // 6a.  PTX ISA 80, SM_90
+   // mbarrier.try_wait.sem.scope.shared::cta.b64         waitComplete, [addr], state;                        // 6a.  PTX ISA 80, SM_90
    // .sem       = { .acquire }
    // .scope     = { .cta, .cluster }
    template <cuda::ptx::dot_scope Scope>
@@ -54,7 +54,7 @@ mbarrier.try_wait.acquire.cta.shared::cta.b64
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 .. code:: cuda
 
-   // mbarrier.try_wait{.sem}{.scope}.shared::cta.b64         waitComplete, [addr], state , suspendTimeHint;      // 6b.  PTX ISA 80, SM_90
+   // mbarrier.try_wait.sem.scope.shared::cta.b64         waitComplete, [addr], state , suspendTimeHint;      // 6b.  PTX ISA 80, SM_90
    // .sem       = { .acquire }
    // .scope     = { .cta, .cluster }
    template <cuda::ptx::dot_scope Scope>
@@ -69,7 +69,7 @@ mbarrier.try_wait.acquire.cluster.shared::cta.b64
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 .. code:: cuda
 
-   // mbarrier.try_wait{.sem}{.scope}.shared::cta.b64         waitComplete, [addr], state , suspendTimeHint;      // 6b.  PTX ISA 80, SM_90
+   // mbarrier.try_wait.sem.scope.shared::cta.b64         waitComplete, [addr], state , suspendTimeHint;      // 6b.  PTX ISA 80, SM_90
    // .sem       = { .acquire }
    // .scope     = { .cta, .cluster }
    template <cuda::ptx::dot_scope Scope>
@@ -79,3 +79,65 @@ mbarrier.try_wait.acquire.cluster.shared::cta.b64
      uint64_t* addr,
      const uint64_t& state,
      const uint32_t& suspendTimeHint);
+
+mbarrier.try_wait.relaxed.cta.shared::cta.b64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // mbarrier.try_wait.sem.scope.shared::cta.b64 waitComplete, [addr], state, suspendTimeHint; // PTX ISA 86, SM_90
+   // .sem       = { .relaxed }
+   // .scope     = { .cta, .cluster }
+   template <cuda::ptx::dot_scope Scope>
+   __device__ static inline void mbarrier_try_wait(
+     cuda::ptx::sem_relaxed_t,
+     cuda::ptx::scope_t<Scope> scope,
+     bool waitComplete,
+     uint64_t* addr,
+     const uint64_t& state,
+     const uint32_t& suspendTimeHint);
+
+mbarrier.try_wait.relaxed.cluster.shared::cta.b64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // mbarrier.try_wait.sem.scope.shared::cta.b64 waitComplete, [addr], state, suspendTimeHint; // PTX ISA 86, SM_90
+   // .sem       = { .relaxed }
+   // .scope     = { .cta, .cluster }
+   template <cuda::ptx::dot_scope Scope>
+   __device__ static inline void mbarrier_try_wait(
+     cuda::ptx::sem_relaxed_t,
+     cuda::ptx::scope_t<Scope> scope,
+     bool waitComplete,
+     uint64_t* addr,
+     const uint64_t& state,
+     const uint32_t& suspendTimeHint);
+
+mbarrier.try_wait.relaxed.cta.shared::cta.b64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // mbarrier.try_wait.sem.scope.shared::cta.b64 waitComplete, [addr], state; // PTX ISA 86, SM_90
+   // .sem       = { .relaxed }
+   // .scope     = { .cta, .cluster }
+   template <cuda::ptx::dot_scope Scope>
+   __device__ static inline void mbarrier_try_wait(
+     cuda::ptx::sem_relaxed_t,
+     cuda::ptx::scope_t<Scope> scope,
+     bool waitComplete,
+     uint64_t* addr,
+     const uint64_t& state);
+
+mbarrier.try_wait.relaxed.cluster.shared::cta.b64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // mbarrier.try_wait.sem.scope.shared::cta.b64 waitComplete, [addr], state; // PTX ISA 86, SM_90
+   // .sem       = { .relaxed }
+   // .scope     = { .cta, .cluster }
+   template <cuda::ptx::dot_scope Scope>
+   __device__ static inline void mbarrier_try_wait(
+     cuda::ptx::sem_relaxed_t,
+     cuda::ptx::scope_t<Scope> scope,
+     bool waitComplete,
+     uint64_t* addr,
+     const uint64_t& state);
diff --git a/docs/libcudacxx/ptx/instructions/generated/mbarrier_try_wait_parity.rst b/docs/libcudacxx/ptx/instructions/generated/mbarrier_try_wait_parity.rst
index 4e7af4bace5..6a51704cab4 100644
--- a/docs/libcudacxx/ptx/instructions/generated/mbarrier_try_wait_parity.rst
+++ b/docs/libcudacxx/ptx/instructions/generated/mbarrier_try_wait_parity.rst
@@ -26,7 +26,7 @@ mbarrier.try_wait.parity.acquire.cta.shared::cta.b64
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 .. code:: cuda
 
-   // mbarrier.try_wait.parity{.sem}{.scope}.shared::cta.b64  waitComplete, [addr], phaseParity;                  // 8a.  PTX ISA 80, SM_90
+   // mbarrier.try_wait.parity.sem.scope.shared::cta.b64  waitComplete, [addr], phaseParity;                  // 8a.  PTX ISA 80, SM_90
    // .sem       = { .acquire }
    // .scope     = { .cta, .cluster }
    template <cuda::ptx::dot_scope Scope>
@@ -40,7 +40,7 @@ mbarrier.try_wait.parity.acquire.cluster.shared::cta.b64
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 .. code:: cuda
 
-   // mbarrier.try_wait.parity{.sem}{.scope}.shared::cta.b64  waitComplete, [addr], phaseParity;                  // 8a.  PTX ISA 80, SM_90
+   // mbarrier.try_wait.parity.sem.scope.shared::cta.b64  waitComplete, [addr], phaseParity;                  // 8a.  PTX ISA 80, SM_90
    // .sem       = { .acquire }
    // .scope     = { .cta, .cluster }
    template <cuda::ptx::dot_scope Scope>
@@ -54,7 +54,7 @@ mbarrier.try_wait.parity.acquire.cta.shared::cta.b64
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 .. code:: cuda
 
-   // mbarrier.try_wait.parity{.sem}{.scope}.shared::cta.b64  waitComplete, [addr], phaseParity, suspendTimeHint; // 8b.  PTX ISA 80, SM_90
+   // mbarrier.try_wait.parity.sem.scope.shared::cta.b64  waitComplete, [addr], phaseParity, suspendTimeHint; // 8b.  PTX ISA 80, SM_90
    // .sem       = { .acquire }
    // .scope     = { .cta, .cluster }
    template <cuda::ptx::dot_scope Scope>
@@ -69,7 +69,7 @@ mbarrier.try_wait.parity.acquire.cluster.shared::cta.b64
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 .. code:: cuda
 
-   // mbarrier.try_wait.parity{.sem}{.scope}.shared::cta.b64  waitComplete, [addr], phaseParity, suspendTimeHint; // 8b.  PTX ISA 80, SM_90
+   // mbarrier.try_wait.parity.sem.scope.shared::cta.b64  waitComplete, [addr], phaseParity, suspendTimeHint; // 8b.  PTX ISA 80, SM_90
    // .sem       = { .acquire }
    // .scope     = { .cta, .cluster }
    template <cuda::ptx::dot_scope Scope>
@@ -79,3 +79,65 @@ mbarrier.try_wait.parity.acquire.cluster.shared::cta.b64
      uint64_t* addr,
      const uint32_t& phaseParity,
      const uint32_t& suspendTimeHint);
+
+mbarrier.try_wait.parity.relaxed.cta.shared::cta.b64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // mbarrier.try_wait.parity.sem.scope.shared::cta.b64 waitComplete, [addr], phaseParity, suspendTimeHint; // PTX ISA 86, SM_90
+   // .sem       = { .relaxed }
+   // .scope     = { .cta, .cluster }
+   template <cuda::ptx::dot_scope Scope>
+   __device__ static inline void mbarrier_try_wait_parity(
+     cuda::ptx::sem_relaxed_t,
+     cuda::ptx::scope_t<Scope> scope,
+     bool waitComplete,
+     uint64_t* addr,
+     const uint32_t& phaseParity,
+     const uint32_t& suspendTimeHint);
+
+mbarrier.try_wait.parity.relaxed.cluster.shared::cta.b64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // mbarrier.try_wait.parity.sem.scope.shared::cta.b64 waitComplete, [addr], phaseParity, suspendTimeHint; // PTX ISA 86, SM_90
+   // .sem       = { .relaxed }
+   // .scope     = { .cta, .cluster }
+   template <cuda::ptx::dot_scope Scope>
+   __device__ static inline void mbarrier_try_wait_parity(
+     cuda::ptx::sem_relaxed_t,
+     cuda::ptx::scope_t<Scope> scope,
+     bool waitComplete,
+     uint64_t* addr,
+     const uint32_t& phaseParity,
+     const uint32_t& suspendTimeHint);
+
+mbarrier.try_wait.parity.relaxed.cta.shared::cta.b64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // mbarrier.try_wait.parity.sem.scope.shared::cta.b64 waitComplete, [addr], phaseParity; // PTX ISA 86, SM_90
+   // .sem       = { .relaxed }
+   // .scope     = { .cta, .cluster }
+   template <cuda::ptx::dot_scope Scope>
+   __device__ static inline void mbarrier_try_wait_parity(
+     cuda::ptx::sem_relaxed_t,
+     cuda::ptx::scope_t<Scope> scope,
+     bool waitComplete,
+     uint64_t* addr,
+     const uint32_t& phaseParity);
+
+mbarrier.try_wait.parity.relaxed.cluster.shared::cta.b64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // mbarrier.try_wait.parity.sem.scope.shared::cta.b64 waitComplete, [addr], phaseParity; // PTX ISA 86, SM_90
+   // .sem       = { .relaxed }
+   // .scope     = { .cta, .cluster }
+   template <cuda::ptx::dot_scope Scope>
+   __device__ static inline void mbarrier_try_wait_parity(
+     cuda::ptx::sem_relaxed_t,
+     cuda::ptx::scope_t<Scope> scope,
+     bool waitComplete,
+     uint64_t* addr,
+     const uint32_t& phaseParity);
diff --git a/docs/libcudacxx/ptx/instructions/generated/multimem_ld_reduce.rst b/docs/libcudacxx/ptx/instructions/generated/multimem_ld_reduce.rst
new file mode 100644
index 00000000000..cd9f32bf5f0
--- /dev/null
+++ b/docs/libcudacxx/ptx/instructions/generated/multimem_ld_reduce.rst
@@ -0,0 +1,2396 @@
+..
+   This file was automatically generated. Do not edit.
+
+multimem.ld_reduce.weak.global.min.u32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.ld_reduce.sem.global.op.u32 dest, [addr]; // PTX ISA 81, SM_90
+   // .sem       = { .weak }
+   // .op        = { .min }
+   template <typename = void>
+   __device__ static inline uint32_t multimem_ld_reduce(
+     cuda::ptx::sem_weak_t,
+     cuda::ptx::op_min_t,
+     const uint32_t* addr);
+
+multimem.ld_reduce.relaxed.cta.global.min.u32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.ld_reduce.sem.scope.global.op.u32 dest, [addr]; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .acquire }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .min }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline uint32_t multimem_ld_reduce(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_min_t,
+     const uint32_t* addr);
+
+multimem.ld_reduce.relaxed.cluster.global.min.u32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.ld_reduce.sem.scope.global.op.u32 dest, [addr]; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .acquire }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .min }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline uint32_t multimem_ld_reduce(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_min_t,
+     const uint32_t* addr);
+
+multimem.ld_reduce.relaxed.gpu.global.min.u32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.ld_reduce.sem.scope.global.op.u32 dest, [addr]; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .acquire }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .min }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline uint32_t multimem_ld_reduce(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_min_t,
+     const uint32_t* addr);
+
+multimem.ld_reduce.relaxed.sys.global.min.u32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.ld_reduce.sem.scope.global.op.u32 dest, [addr]; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .acquire }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .min }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline uint32_t multimem_ld_reduce(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_min_t,
+     const uint32_t* addr);
+
+multimem.ld_reduce.acquire.cta.global.min.u32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.ld_reduce.sem.scope.global.op.u32 dest, [addr]; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .acquire }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .min }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline uint32_t multimem_ld_reduce(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_min_t,
+     const uint32_t* addr);
+
+multimem.ld_reduce.acquire.cluster.global.min.u32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.ld_reduce.sem.scope.global.op.u32 dest, [addr]; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .acquire }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .min }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline uint32_t multimem_ld_reduce(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_min_t,
+     const uint32_t* addr);
+
+multimem.ld_reduce.acquire.gpu.global.min.u32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.ld_reduce.sem.scope.global.op.u32 dest, [addr]; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .acquire }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .min }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline uint32_t multimem_ld_reduce(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_min_t,
+     const uint32_t* addr);
+
+multimem.ld_reduce.acquire.sys.global.min.u32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.ld_reduce.sem.scope.global.op.u32 dest, [addr]; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .acquire }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .min }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline uint32_t multimem_ld_reduce(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_min_t,
+     const uint32_t* addr);
+
+multimem.ld_reduce.weak.global.min.u64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.ld_reduce.sem.global.op.u64 dest, [addr]; // PTX ISA 81, SM_90
+   // .sem       = { .weak }
+   // .op        = { .min }
+   template <typename = void>
+   __device__ static inline uint64_t multimem_ld_reduce(
+     cuda::ptx::sem_weak_t,
+     cuda::ptx::op_min_t,
+     const uint64_t* addr);
+
+multimem.ld_reduce.relaxed.cta.global.min.u64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.ld_reduce.sem.scope.global.op.u64 dest, [addr]; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .acquire }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .min }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline uint64_t multimem_ld_reduce(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_min_t,
+     const uint64_t* addr);
+
+multimem.ld_reduce.relaxed.cluster.global.min.u64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.ld_reduce.sem.scope.global.op.u64 dest, [addr]; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .acquire }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .min }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline uint64_t multimem_ld_reduce(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_min_t,
+     const uint64_t* addr);
+
+multimem.ld_reduce.relaxed.gpu.global.min.u64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.ld_reduce.sem.scope.global.op.u64 dest, [addr]; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .acquire }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .min }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline uint64_t multimem_ld_reduce(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_min_t,
+     const uint64_t* addr);
+
+multimem.ld_reduce.relaxed.sys.global.min.u64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.ld_reduce.sem.scope.global.op.u64 dest, [addr]; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .acquire }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .min }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline uint64_t multimem_ld_reduce(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_min_t,
+     const uint64_t* addr);
+
+multimem.ld_reduce.acquire.cta.global.min.u64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.ld_reduce.sem.scope.global.op.u64 dest, [addr]; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .acquire }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .min }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline uint64_t multimem_ld_reduce(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_min_t,
+     const uint64_t* addr);
+
+multimem.ld_reduce.acquire.cluster.global.min.u64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.ld_reduce.sem.scope.global.op.u64 dest, [addr]; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .acquire }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .min }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline uint64_t multimem_ld_reduce(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_min_t,
+     const uint64_t* addr);
+
+multimem.ld_reduce.acquire.gpu.global.min.u64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.ld_reduce.sem.scope.global.op.u64 dest, [addr]; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .acquire }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .min }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline uint64_t multimem_ld_reduce(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_min_t,
+     const uint64_t* addr);
+
+multimem.ld_reduce.acquire.sys.global.min.u64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.ld_reduce.sem.scope.global.op.u64 dest, [addr]; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .acquire }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .min }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline uint64_t multimem_ld_reduce(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_min_t,
+     const uint64_t* addr);
+
+multimem.ld_reduce.weak.global.min.s32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.ld_reduce.sem.global.op.s32 dest, [addr]; // PTX ISA 81, SM_90
+   // .sem       = { .weak }
+   // .op        = { .min }
+   template <typename = void>
+   __device__ static inline int32_t multimem_ld_reduce(
+     cuda::ptx::sem_weak_t,
+     cuda::ptx::op_min_t,
+     const int32_t* addr);
+
+multimem.ld_reduce.relaxed.cta.global.min.s32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.ld_reduce.sem.scope.global.op.s32 dest, [addr]; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .acquire }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .min }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline int32_t multimem_ld_reduce(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_min_t,
+     const int32_t* addr);
+
+multimem.ld_reduce.relaxed.cluster.global.min.s32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.ld_reduce.sem.scope.global.op.s32 dest, [addr]; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .acquire }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .min }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline int32_t multimem_ld_reduce(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_min_t,
+     const int32_t* addr);
+
+multimem.ld_reduce.relaxed.gpu.global.min.s32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.ld_reduce.sem.scope.global.op.s32 dest, [addr]; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .acquire }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .min }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline int32_t multimem_ld_reduce(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_min_t,
+     const int32_t* addr);
+
+multimem.ld_reduce.relaxed.sys.global.min.s32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.ld_reduce.sem.scope.global.op.s32 dest, [addr]; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .acquire }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .min }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline int32_t multimem_ld_reduce(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_min_t,
+     const int32_t* addr);
+
+multimem.ld_reduce.acquire.cta.global.min.s32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.ld_reduce.sem.scope.global.op.s32 dest, [addr]; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .acquire }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .min }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline int32_t multimem_ld_reduce(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_min_t,
+     const int32_t* addr);
+
+multimem.ld_reduce.acquire.cluster.global.min.s32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.ld_reduce.sem.scope.global.op.s32 dest, [addr]; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .acquire }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .min }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline int32_t multimem_ld_reduce(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_min_t,
+     const int32_t* addr);
+
+multimem.ld_reduce.acquire.gpu.global.min.s32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.ld_reduce.sem.scope.global.op.s32 dest, [addr]; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .acquire }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .min }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline int32_t multimem_ld_reduce(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_min_t,
+     const int32_t* addr);
+
+multimem.ld_reduce.acquire.sys.global.min.s32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.ld_reduce.sem.scope.global.op.s32 dest, [addr]; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .acquire }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .min }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline int32_t multimem_ld_reduce(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_min_t,
+     const int32_t* addr);
+
+multimem.ld_reduce.weak.global.min.s64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.ld_reduce.sem.global.op.s64 dest, [addr]; // PTX ISA 81, SM_90
+   // .sem       = { .weak }
+   // .op        = { .min }
+   template <typename = void>
+   __device__ static inline int64_t multimem_ld_reduce(
+     cuda::ptx::sem_weak_t,
+     cuda::ptx::op_min_t,
+     const int64_t* addr);
+
+multimem.ld_reduce.relaxed.cta.global.min.s64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.ld_reduce.sem.scope.global.op.s64 dest, [addr]; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .acquire }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .min }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline int64_t multimem_ld_reduce(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_min_t,
+     const int64_t* addr);
+
+multimem.ld_reduce.relaxed.cluster.global.min.s64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.ld_reduce.sem.scope.global.op.s64 dest, [addr]; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .acquire }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .min }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline int64_t multimem_ld_reduce(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_min_t,
+     const int64_t* addr);
+
+multimem.ld_reduce.relaxed.gpu.global.min.s64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.ld_reduce.sem.scope.global.op.s64 dest, [addr]; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .acquire }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .min }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline int64_t multimem_ld_reduce(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_min_t,
+     const int64_t* addr);
+
+multimem.ld_reduce.relaxed.sys.global.min.s64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.ld_reduce.sem.scope.global.op.s64 dest, [addr]; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .acquire }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .min }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline int64_t multimem_ld_reduce(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_min_t,
+     const int64_t* addr);
+
+multimem.ld_reduce.acquire.cta.global.min.s64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.ld_reduce.sem.scope.global.op.s64 dest, [addr]; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .acquire }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .min }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline int64_t multimem_ld_reduce(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_min_t,
+     const int64_t* addr);
+
+multimem.ld_reduce.acquire.cluster.global.min.s64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.ld_reduce.sem.scope.global.op.s64 dest, [addr]; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .acquire }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .min }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline int64_t multimem_ld_reduce(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_min_t,
+     const int64_t* addr);
+
+multimem.ld_reduce.acquire.gpu.global.min.s64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.ld_reduce.sem.scope.global.op.s64 dest, [addr]; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .acquire }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .min }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline int64_t multimem_ld_reduce(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_min_t,
+     const int64_t* addr);
+
+multimem.ld_reduce.acquire.sys.global.min.s64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.ld_reduce.sem.scope.global.op.s64 dest, [addr]; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .acquire }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .min }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline int64_t multimem_ld_reduce(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_min_t,
+     const int64_t* addr);
+
+multimem.ld_reduce.weak.global.max.u32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.ld_reduce.sem.global.op.u32 dest, [addr]; // PTX ISA 81, SM_90
+   // .sem       = { .weak }
+   // .op        = { .max }
+   template <typename = void>
+   __device__ static inline uint32_t multimem_ld_reduce(
+     cuda::ptx::sem_weak_t,
+     cuda::ptx::op_max_t,
+     const uint32_t* addr);
+
+multimem.ld_reduce.relaxed.cta.global.max.u32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.ld_reduce.sem.scope.global.op.u32 dest, [addr]; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .acquire }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .max }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline uint32_t multimem_ld_reduce(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_max_t,
+     const uint32_t* addr);
+
+multimem.ld_reduce.relaxed.cluster.global.max.u32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.ld_reduce.sem.scope.global.op.u32 dest, [addr]; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .acquire }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .max }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline uint32_t multimem_ld_reduce(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_max_t,
+     const uint32_t* addr);
+
+multimem.ld_reduce.relaxed.gpu.global.max.u32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.ld_reduce.sem.scope.global.op.u32 dest, [addr]; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .acquire }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .max }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline uint32_t multimem_ld_reduce(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_max_t,
+     const uint32_t* addr);
+
+multimem.ld_reduce.relaxed.sys.global.max.u32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.ld_reduce.sem.scope.global.op.u32 dest, [addr]; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .acquire }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .max }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline uint32_t multimem_ld_reduce(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_max_t,
+     const uint32_t* addr);
+
+multimem.ld_reduce.acquire.cta.global.max.u32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.ld_reduce.sem.scope.global.op.u32 dest, [addr]; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .acquire }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .max }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline uint32_t multimem_ld_reduce(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_max_t,
+     const uint32_t* addr);
+
+multimem.ld_reduce.acquire.cluster.global.max.u32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.ld_reduce.sem.scope.global.op.u32 dest, [addr]; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .acquire }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .max }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline uint32_t multimem_ld_reduce(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_max_t,
+     const uint32_t* addr);
+
+multimem.ld_reduce.acquire.gpu.global.max.u32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.ld_reduce.sem.scope.global.op.u32 dest, [addr]; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .acquire }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .max }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline uint32_t multimem_ld_reduce(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_max_t,
+     const uint32_t* addr);
+
+multimem.ld_reduce.acquire.sys.global.max.u32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.ld_reduce.sem.scope.global.op.u32 dest, [addr]; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .acquire }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .max }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline uint32_t multimem_ld_reduce(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_max_t,
+     const uint32_t* addr);
+
+multimem.ld_reduce.weak.global.max.u64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.ld_reduce.sem.global.op.u64 dest, [addr]; // PTX ISA 81, SM_90
+   // .sem       = { .weak }
+   // .op        = { .max }
+   template <typename = void>
+   __device__ static inline uint64_t multimem_ld_reduce(
+     cuda::ptx::sem_weak_t,
+     cuda::ptx::op_max_t,
+     const uint64_t* addr);
+
+multimem.ld_reduce.relaxed.cta.global.max.u64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.ld_reduce.sem.scope.global.op.u64 dest, [addr]; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .acquire }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .max }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline uint64_t multimem_ld_reduce(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_max_t,
+     const uint64_t* addr);
+
+multimem.ld_reduce.relaxed.cluster.global.max.u64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.ld_reduce.sem.scope.global.op.u64 dest, [addr]; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .acquire }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .max }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline uint64_t multimem_ld_reduce(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_max_t,
+     const uint64_t* addr);
+
+multimem.ld_reduce.relaxed.gpu.global.max.u64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.ld_reduce.sem.scope.global.op.u64 dest, [addr]; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .acquire }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .max }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline uint64_t multimem_ld_reduce(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_max_t,
+     const uint64_t* addr);
+
+multimem.ld_reduce.relaxed.sys.global.max.u64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.ld_reduce.sem.scope.global.op.u64 dest, [addr]; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .acquire }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .max }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline uint64_t multimem_ld_reduce(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_max_t,
+     const uint64_t* addr);
+
+multimem.ld_reduce.acquire.cta.global.max.u64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.ld_reduce.sem.scope.global.op.u64 dest, [addr]; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .acquire }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .max }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline uint64_t multimem_ld_reduce(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_max_t,
+     const uint64_t* addr);
+
+multimem.ld_reduce.acquire.cluster.global.max.u64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.ld_reduce.sem.scope.global.op.u64 dest, [addr]; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .acquire }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .max }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline uint64_t multimem_ld_reduce(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_max_t,
+     const uint64_t* addr);
+
+multimem.ld_reduce.acquire.gpu.global.max.u64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.ld_reduce.sem.scope.global.op.u64 dest, [addr]; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .acquire }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .max }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline uint64_t multimem_ld_reduce(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_max_t,
+     const uint64_t* addr);
+
+multimem.ld_reduce.acquire.sys.global.max.u64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.ld_reduce.sem.scope.global.op.u64 dest, [addr]; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .acquire }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .max }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline uint64_t multimem_ld_reduce(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_max_t,
+     const uint64_t* addr);
+
+multimem.ld_reduce.weak.global.max.s32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.ld_reduce.sem.global.op.s32 dest, [addr]; // PTX ISA 81, SM_90
+   // .sem       = { .weak }
+   // .op        = { .max }
+   template <typename = void>
+   __device__ static inline int32_t multimem_ld_reduce(
+     cuda::ptx::sem_weak_t,
+     cuda::ptx::op_max_t,
+     const int32_t* addr);
+
+multimem.ld_reduce.relaxed.cta.global.max.s32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.ld_reduce.sem.scope.global.op.s32 dest, [addr]; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .acquire }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .max }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline int32_t multimem_ld_reduce(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_max_t,
+     const int32_t* addr);
+
+multimem.ld_reduce.relaxed.cluster.global.max.s32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.ld_reduce.sem.scope.global.op.s32 dest, [addr]; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .acquire }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .max }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline int32_t multimem_ld_reduce(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_max_t,
+     const int32_t* addr);
+
+multimem.ld_reduce.relaxed.gpu.global.max.s32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.ld_reduce.sem.scope.global.op.s32 dest, [addr]; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .acquire }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .max }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline int32_t multimem_ld_reduce(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_max_t,
+     const int32_t* addr);
+
+multimem.ld_reduce.relaxed.sys.global.max.s32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.ld_reduce.sem.scope.global.op.s32 dest, [addr]; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .acquire }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .max }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline int32_t multimem_ld_reduce(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_max_t,
+     const int32_t* addr);
+
+multimem.ld_reduce.acquire.cta.global.max.s32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.ld_reduce.sem.scope.global.op.s32 dest, [addr]; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .acquire }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .max }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline int32_t multimem_ld_reduce(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_max_t,
+     const int32_t* addr);
+
+multimem.ld_reduce.acquire.cluster.global.max.s32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.ld_reduce.sem.scope.global.op.s32 dest, [addr]; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .acquire }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .max }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline int32_t multimem_ld_reduce(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_max_t,
+     const int32_t* addr);
+
+multimem.ld_reduce.acquire.gpu.global.max.s32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.ld_reduce.sem.scope.global.op.s32 dest, [addr]; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .acquire }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .max }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline int32_t multimem_ld_reduce(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_max_t,
+     const int32_t* addr);
+
+multimem.ld_reduce.acquire.sys.global.max.s32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.ld_reduce.sem.scope.global.op.s32 dest, [addr]; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .acquire }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .max }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline int32_t multimem_ld_reduce(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_max_t,
+     const int32_t* addr);
+
+multimem.ld_reduce.weak.global.max.s64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.ld_reduce.sem.global.op.s64 dest, [addr]; // PTX ISA 81, SM_90
+   // .sem       = { .weak }
+   // .op        = { .max }
+   template <typename = void>
+   __device__ static inline int64_t multimem_ld_reduce(
+     cuda::ptx::sem_weak_t,
+     cuda::ptx::op_max_t,
+     const int64_t* addr);
+
+multimem.ld_reduce.relaxed.cta.global.max.s64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.ld_reduce.sem.scope.global.op.s64 dest, [addr]; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .acquire }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .max }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline int64_t multimem_ld_reduce(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_max_t,
+     const int64_t* addr);
+
+multimem.ld_reduce.relaxed.cluster.global.max.s64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.ld_reduce.sem.scope.global.op.s64 dest, [addr]; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .acquire }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .max }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline int64_t multimem_ld_reduce(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_max_t,
+     const int64_t* addr);
+
+multimem.ld_reduce.relaxed.gpu.global.max.s64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.ld_reduce.sem.scope.global.op.s64 dest, [addr]; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .acquire }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .max }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline int64_t multimem_ld_reduce(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_max_t,
+     const int64_t* addr);
+
+multimem.ld_reduce.relaxed.sys.global.max.s64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.ld_reduce.sem.scope.global.op.s64 dest, [addr]; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .acquire }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .max }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline int64_t multimem_ld_reduce(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_max_t,
+     const int64_t* addr);
+
+multimem.ld_reduce.acquire.cta.global.max.s64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.ld_reduce.sem.scope.global.op.s64 dest, [addr]; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .acquire }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .max }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline int64_t multimem_ld_reduce(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_max_t,
+     const int64_t* addr);
+
+multimem.ld_reduce.acquire.cluster.global.max.s64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.ld_reduce.sem.scope.global.op.s64 dest, [addr]; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .acquire }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .max }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline int64_t multimem_ld_reduce(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_max_t,
+     const int64_t* addr);
+
+multimem.ld_reduce.acquire.gpu.global.max.s64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.ld_reduce.sem.scope.global.op.s64 dest, [addr]; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .acquire }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .max }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline int64_t multimem_ld_reduce(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_max_t,
+     const int64_t* addr);
+
+multimem.ld_reduce.acquire.sys.global.max.s64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.ld_reduce.sem.scope.global.op.s64 dest, [addr]; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .acquire }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .max }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline int64_t multimem_ld_reduce(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_max_t,
+     const int64_t* addr);
+
+multimem.ld_reduce.weak.global.add.u32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.ld_reduce.sem.global.op.u32 dest, [addr]; // PTX ISA 81, SM_90
+   // .sem       = { .weak }
+   // .op        = { .add }
+   template <typename = void>
+   __device__ static inline uint32_t multimem_ld_reduce(
+     cuda::ptx::sem_weak_t,
+     cuda::ptx::op_add_t,
+     const uint32_t* addr);
+
+multimem.ld_reduce.relaxed.cta.global.add.u32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.ld_reduce.sem.scope.global.op.u32 dest, [addr]; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .acquire }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .add }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline uint32_t multimem_ld_reduce(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_add_t,
+     const uint32_t* addr);
+
+multimem.ld_reduce.relaxed.cluster.global.add.u32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.ld_reduce.sem.scope.global.op.u32 dest, [addr]; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .acquire }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .add }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline uint32_t multimem_ld_reduce(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_add_t,
+     const uint32_t* addr);
+
+multimem.ld_reduce.relaxed.gpu.global.add.u32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.ld_reduce.sem.scope.global.op.u32 dest, [addr]; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .acquire }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .add }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline uint32_t multimem_ld_reduce(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_add_t,
+     const uint32_t* addr);
+
+multimem.ld_reduce.relaxed.sys.global.add.u32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.ld_reduce.sem.scope.global.op.u32 dest, [addr]; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .acquire }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .add }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline uint32_t multimem_ld_reduce(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_add_t,
+     const uint32_t* addr);
+
+multimem.ld_reduce.acquire.cta.global.add.u32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.ld_reduce.sem.scope.global.op.u32 dest, [addr]; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .acquire }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .add }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline uint32_t multimem_ld_reduce(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_add_t,
+     const uint32_t* addr);
+
+multimem.ld_reduce.acquire.cluster.global.add.u32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.ld_reduce.sem.scope.global.op.u32 dest, [addr]; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .acquire }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .add }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline uint32_t multimem_ld_reduce(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_add_t,
+     const uint32_t* addr);
+
+multimem.ld_reduce.acquire.gpu.global.add.u32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.ld_reduce.sem.scope.global.op.u32 dest, [addr]; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .acquire }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .add }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline uint32_t multimem_ld_reduce(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_add_t,
+     const uint32_t* addr);
+
+multimem.ld_reduce.acquire.sys.global.add.u32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.ld_reduce.sem.scope.global.op.u32 dest, [addr]; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .acquire }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .add }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline uint32_t multimem_ld_reduce(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_add_t,
+     const uint32_t* addr);
+
+multimem.ld_reduce.weak.global.add.u64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.ld_reduce.sem.global.op.u64 dest, [addr]; // PTX ISA 81, SM_90
+   // .sem       = { .weak }
+   // .op        = { .add }
+   template <typename = void>
+   __device__ static inline uint64_t multimem_ld_reduce(
+     cuda::ptx::sem_weak_t,
+     cuda::ptx::op_add_t,
+     const uint64_t* addr);
+
+multimem.ld_reduce.relaxed.cta.global.add.u64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.ld_reduce.sem.scope.global.op.u64 dest, [addr]; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .acquire }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .add }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline uint64_t multimem_ld_reduce(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_add_t,
+     const uint64_t* addr);
+
+multimem.ld_reduce.relaxed.cluster.global.add.u64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.ld_reduce.sem.scope.global.op.u64 dest, [addr]; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .acquire }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .add }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline uint64_t multimem_ld_reduce(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_add_t,
+     const uint64_t* addr);
+
+multimem.ld_reduce.relaxed.gpu.global.add.u64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.ld_reduce.sem.scope.global.op.u64 dest, [addr]; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .acquire }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .add }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline uint64_t multimem_ld_reduce(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_add_t,
+     const uint64_t* addr);
+
+multimem.ld_reduce.relaxed.sys.global.add.u64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.ld_reduce.sem.scope.global.op.u64 dest, [addr]; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .acquire }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .add }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline uint64_t multimem_ld_reduce(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_add_t,
+     const uint64_t* addr);
+
+multimem.ld_reduce.acquire.cta.global.add.u64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.ld_reduce.sem.scope.global.op.u64 dest, [addr]; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .acquire }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .add }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline uint64_t multimem_ld_reduce(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_add_t,
+     const uint64_t* addr);
+
+multimem.ld_reduce.acquire.cluster.global.add.u64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.ld_reduce.sem.scope.global.op.u64 dest, [addr]; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .acquire }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .add }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline uint64_t multimem_ld_reduce(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_add_t,
+     const uint64_t* addr);
+
+multimem.ld_reduce.acquire.gpu.global.add.u64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.ld_reduce.sem.scope.global.op.u64 dest, [addr]; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .acquire }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .add }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline uint64_t multimem_ld_reduce(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_add_t,
+     const uint64_t* addr);
+
+multimem.ld_reduce.acquire.sys.global.add.u64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.ld_reduce.sem.scope.global.op.u64 dest, [addr]; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .acquire }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .add }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline uint64_t multimem_ld_reduce(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_add_t,
+     const uint64_t* addr);
+
+multimem.ld_reduce.weak.global.add.s32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.ld_reduce.sem.global.op.s32 dest, [addr]; // PTX ISA 81, SM_90
+   // .sem       = { .weak }
+   // .op        = { .add }
+   template <typename = void>
+   __device__ static inline int32_t multimem_ld_reduce(
+     cuda::ptx::sem_weak_t,
+     cuda::ptx::op_add_t,
+     const int32_t* addr);
+
+multimem.ld_reduce.relaxed.cta.global.add.s32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.ld_reduce.sem.scope.global.op.s32 dest, [addr]; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .acquire }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .add }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline int32_t multimem_ld_reduce(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_add_t,
+     const int32_t* addr);
+
+multimem.ld_reduce.relaxed.cluster.global.add.s32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.ld_reduce.sem.scope.global.op.s32 dest, [addr]; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .acquire }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .add }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline int32_t multimem_ld_reduce(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_add_t,
+     const int32_t* addr);
+
+multimem.ld_reduce.relaxed.gpu.global.add.s32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.ld_reduce.sem.scope.global.op.s32 dest, [addr]; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .acquire }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .add }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline int32_t multimem_ld_reduce(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_add_t,
+     const int32_t* addr);
+
+multimem.ld_reduce.relaxed.sys.global.add.s32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.ld_reduce.sem.scope.global.op.s32 dest, [addr]; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .acquire }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .add }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline int32_t multimem_ld_reduce(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_add_t,
+     const int32_t* addr);
+
+multimem.ld_reduce.acquire.cta.global.add.s32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.ld_reduce.sem.scope.global.op.s32 dest, [addr]; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .acquire }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .add }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline int32_t multimem_ld_reduce(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_add_t,
+     const int32_t* addr);
+
+multimem.ld_reduce.acquire.cluster.global.add.s32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.ld_reduce.sem.scope.global.op.s32 dest, [addr]; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .acquire }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .add }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline int32_t multimem_ld_reduce(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_add_t,
+     const int32_t* addr);
+
+multimem.ld_reduce.acquire.gpu.global.add.s32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.ld_reduce.sem.scope.global.op.s32 dest, [addr]; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .acquire }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .add }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline int32_t multimem_ld_reduce(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_add_t,
+     const int32_t* addr);
+
+multimem.ld_reduce.acquire.sys.global.add.s32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.ld_reduce.sem.scope.global.op.s32 dest, [addr]; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .acquire }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .add }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline int32_t multimem_ld_reduce(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_add_t,
+     const int32_t* addr);
+
+multimem.ld_reduce.weak.global.add.u64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.ld_reduce.sem.global.op.u64 dest, [addr]; // PTX ISA 81, SM_90
+   // .sem       = { .weak }
+   // .op        = { .add }
+   template <typename = void>
+   __device__ static inline int64_t multimem_ld_reduce(
+     cuda::ptx::sem_weak_t,
+     cuda::ptx::op_add_t,
+     const int64_t* addr);
+
+multimem.ld_reduce.relaxed.cta.global.add.u64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.ld_reduce.sem.scope.global.op.u64 dest, [addr]; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .acquire }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .add }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline int64_t multimem_ld_reduce(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_add_t,
+     const int64_t* addr);
+
+multimem.ld_reduce.relaxed.cluster.global.add.u64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.ld_reduce.sem.scope.global.op.u64 dest, [addr]; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .acquire }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .add }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline int64_t multimem_ld_reduce(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_add_t,
+     const int64_t* addr);
+
+multimem.ld_reduce.relaxed.gpu.global.add.u64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.ld_reduce.sem.scope.global.op.u64 dest, [addr]; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .acquire }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .add }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline int64_t multimem_ld_reduce(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_add_t,
+     const int64_t* addr);
+
+multimem.ld_reduce.relaxed.sys.global.add.u64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.ld_reduce.sem.scope.global.op.u64 dest, [addr]; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .acquire }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .add }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline int64_t multimem_ld_reduce(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_add_t,
+     const int64_t* addr);
+
+multimem.ld_reduce.acquire.cta.global.add.u64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.ld_reduce.sem.scope.global.op.u64 dest, [addr]; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .acquire }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .add }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline int64_t multimem_ld_reduce(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_add_t,
+     const int64_t* addr);
+
+multimem.ld_reduce.acquire.cluster.global.add.u64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.ld_reduce.sem.scope.global.op.u64 dest, [addr]; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .acquire }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .add }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline int64_t multimem_ld_reduce(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_add_t,
+     const int64_t* addr);
+
+multimem.ld_reduce.acquire.gpu.global.add.u64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.ld_reduce.sem.scope.global.op.u64 dest, [addr]; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .acquire }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .add }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline int64_t multimem_ld_reduce(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_add_t,
+     const int64_t* addr);
+
+multimem.ld_reduce.acquire.sys.global.add.u64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.ld_reduce.sem.scope.global.op.u64 dest, [addr]; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .acquire }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .add }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline int64_t multimem_ld_reduce(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_add_t,
+     const int64_t* addr);
+
+multimem.ld_reduce.weak.global.and.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.ld_reduce.sem.global.op.b32 dest, [addr]; // PTX ISA 81, SM_90
+   // .sem       = { .weak }
+   // .op        = { .and }
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+   __device__ static inline B32 multimem_ld_reduce(
+     cuda::ptx::sem_weak_t,
+     cuda::ptx::op_and_op_t,
+     const B32* addr);
+
+multimem.ld_reduce.relaxed.cta.global.and.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.ld_reduce.sem.scope.global.op.b32 dest, [addr]; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .acquire }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .and }
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true, cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline B32 multimem_ld_reduce(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_and_op_t,
+     const B32* addr);
+
+multimem.ld_reduce.relaxed.cluster.global.and.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.ld_reduce.sem.scope.global.op.b32 dest, [addr]; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .acquire }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .and }
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true, cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline B32 multimem_ld_reduce(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_and_op_t,
+     const B32* addr);
+
+multimem.ld_reduce.relaxed.gpu.global.and.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.ld_reduce.sem.scope.global.op.b32 dest, [addr]; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .acquire }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .and }
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true, cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline B32 multimem_ld_reduce(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_and_op_t,
+     const B32* addr);
+
+multimem.ld_reduce.relaxed.sys.global.and.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.ld_reduce.sem.scope.global.op.b32 dest, [addr]; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .acquire }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .and }
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true, cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline B32 multimem_ld_reduce(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_and_op_t,
+     const B32* addr);
+
+multimem.ld_reduce.acquire.cta.global.and.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.ld_reduce.sem.scope.global.op.b32 dest, [addr]; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .acquire }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .and }
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true, cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline B32 multimem_ld_reduce(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_and_op_t,
+     const B32* addr);
+
+multimem.ld_reduce.acquire.cluster.global.and.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.ld_reduce.sem.scope.global.op.b32 dest, [addr]; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .acquire }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .and }
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true, cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline B32 multimem_ld_reduce(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_and_op_t,
+     const B32* addr);
+
+multimem.ld_reduce.acquire.gpu.global.and.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.ld_reduce.sem.scope.global.op.b32 dest, [addr]; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .acquire }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .and }
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true, cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline B32 multimem_ld_reduce(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_and_op_t,
+     const B32* addr);
+
+multimem.ld_reduce.acquire.sys.global.and.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.ld_reduce.sem.scope.global.op.b32 dest, [addr]; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .acquire }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .and }
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true, cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline B32 multimem_ld_reduce(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_and_op_t,
+     const B32* addr);
+
+multimem.ld_reduce.weak.global.or.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.ld_reduce.sem.global.op.b32 dest, [addr]; // PTX ISA 81, SM_90
+   // .sem       = { .weak }
+   // .op        = { .or }
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+   __device__ static inline B32 multimem_ld_reduce(
+     cuda::ptx::sem_weak_t,
+     cuda::ptx::op_or_op_t,
+     const B32* addr);
+
+multimem.ld_reduce.relaxed.cta.global.or.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.ld_reduce.sem.scope.global.op.b32 dest, [addr]; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .acquire }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .or }
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true, cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline B32 multimem_ld_reduce(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_or_op_t,
+     const B32* addr);
+
+multimem.ld_reduce.relaxed.cluster.global.or.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.ld_reduce.sem.scope.global.op.b32 dest, [addr]; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .acquire }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .or }
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true, cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline B32 multimem_ld_reduce(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_or_op_t,
+     const B32* addr);
+
+multimem.ld_reduce.relaxed.gpu.global.or.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.ld_reduce.sem.scope.global.op.b32 dest, [addr]; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .acquire }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .or }
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true, cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline B32 multimem_ld_reduce(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_or_op_t,
+     const B32* addr);
+
+multimem.ld_reduce.relaxed.sys.global.or.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.ld_reduce.sem.scope.global.op.b32 dest, [addr]; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .acquire }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .or }
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true, cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline B32 multimem_ld_reduce(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_or_op_t,
+     const B32* addr);
+
+multimem.ld_reduce.acquire.cta.global.or.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.ld_reduce.sem.scope.global.op.b32 dest, [addr]; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .acquire }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .or }
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true, cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline B32 multimem_ld_reduce(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_or_op_t,
+     const B32* addr);
+
+multimem.ld_reduce.acquire.cluster.global.or.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.ld_reduce.sem.scope.global.op.b32 dest, [addr]; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .acquire }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .or }
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true, cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline B32 multimem_ld_reduce(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_or_op_t,
+     const B32* addr);
+
+multimem.ld_reduce.acquire.gpu.global.or.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.ld_reduce.sem.scope.global.op.b32 dest, [addr]; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .acquire }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .or }
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true, cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline B32 multimem_ld_reduce(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_or_op_t,
+     const B32* addr);
+
+multimem.ld_reduce.acquire.sys.global.or.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.ld_reduce.sem.scope.global.op.b32 dest, [addr]; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .acquire }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .or }
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true, cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline B32 multimem_ld_reduce(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_or_op_t,
+     const B32* addr);
+
+multimem.ld_reduce.weak.global.xor.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.ld_reduce.sem.global.op.b32 dest, [addr]; // PTX ISA 81, SM_90
+   // .sem       = { .weak }
+   // .op        = { .xor }
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+   __device__ static inline B32 multimem_ld_reduce(
+     cuda::ptx::sem_weak_t,
+     cuda::ptx::op_xor_op_t,
+     const B32* addr);
+
+multimem.ld_reduce.relaxed.cta.global.xor.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.ld_reduce.sem.scope.global.op.b32 dest, [addr]; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .acquire }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .xor }
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true, cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline B32 multimem_ld_reduce(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_xor_op_t,
+     const B32* addr);
+
+multimem.ld_reduce.relaxed.cluster.global.xor.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.ld_reduce.sem.scope.global.op.b32 dest, [addr]; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .acquire }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .xor }
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true, cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline B32 multimem_ld_reduce(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_xor_op_t,
+     const B32* addr);
+
+multimem.ld_reduce.relaxed.gpu.global.xor.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.ld_reduce.sem.scope.global.op.b32 dest, [addr]; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .acquire }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .xor }
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true, cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline B32 multimem_ld_reduce(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_xor_op_t,
+     const B32* addr);
+
+multimem.ld_reduce.relaxed.sys.global.xor.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.ld_reduce.sem.scope.global.op.b32 dest, [addr]; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .acquire }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .xor }
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true, cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline B32 multimem_ld_reduce(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_xor_op_t,
+     const B32* addr);
+
+multimem.ld_reduce.acquire.cta.global.xor.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.ld_reduce.sem.scope.global.op.b32 dest, [addr]; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .acquire }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .xor }
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true, cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline B32 multimem_ld_reduce(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_xor_op_t,
+     const B32* addr);
+
+multimem.ld_reduce.acquire.cluster.global.xor.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.ld_reduce.sem.scope.global.op.b32 dest, [addr]; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .acquire }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .xor }
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true, cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline B32 multimem_ld_reduce(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_xor_op_t,
+     const B32* addr);
+
+multimem.ld_reduce.acquire.gpu.global.xor.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.ld_reduce.sem.scope.global.op.b32 dest, [addr]; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .acquire }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .xor }
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true, cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline B32 multimem_ld_reduce(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_xor_op_t,
+     const B32* addr);
+
+multimem.ld_reduce.acquire.sys.global.xor.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.ld_reduce.sem.scope.global.op.b32 dest, [addr]; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .acquire }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .xor }
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true, cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline B32 multimem_ld_reduce(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_xor_op_t,
+     const B32* addr);
+
+multimem.ld_reduce.weak.global.and.b64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.ld_reduce.sem.global.op.b64 dest, [addr]; // PTX ISA 81, SM_90
+   // .sem       = { .weak }
+   // .op        = { .and }
+   template <typename B64, enable_if_t<sizeof(B64) == 8, bool> = true>
+   __device__ static inline B64 multimem_ld_reduce(
+     cuda::ptx::sem_weak_t,
+     cuda::ptx::op_and_op_t,
+     const B64* addr);
+
+multimem.ld_reduce.relaxed.cta.global.and.b64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.ld_reduce.sem.scope.global.op.b64 dest, [addr]; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .acquire }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .and }
+   template <typename B64, enable_if_t<sizeof(B64) == 8, bool> = true, cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline B64 multimem_ld_reduce(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_and_op_t,
+     const B64* addr);
+
+multimem.ld_reduce.relaxed.cluster.global.and.b64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.ld_reduce.sem.scope.global.op.b64 dest, [addr]; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .acquire }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .and }
+   template <typename B64, enable_if_t<sizeof(B64) == 8, bool> = true, cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline B64 multimem_ld_reduce(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_and_op_t,
+     const B64* addr);
+
+multimem.ld_reduce.relaxed.gpu.global.and.b64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.ld_reduce.sem.scope.global.op.b64 dest, [addr]; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .acquire }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .and }
+   template <typename B64, enable_if_t<sizeof(B64) == 8, bool> = true, cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline B64 multimem_ld_reduce(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_and_op_t,
+     const B64* addr);
+
+multimem.ld_reduce.relaxed.sys.global.and.b64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.ld_reduce.sem.scope.global.op.b64 dest, [addr]; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .acquire }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .and }
+   template <typename B64, enable_if_t<sizeof(B64) == 8, bool> = true, cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline B64 multimem_ld_reduce(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_and_op_t,
+     const B64* addr);
+
+multimem.ld_reduce.acquire.cta.global.and.b64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.ld_reduce.sem.scope.global.op.b64 dest, [addr]; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .acquire }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .and }
+   template <typename B64, enable_if_t<sizeof(B64) == 8, bool> = true, cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline B64 multimem_ld_reduce(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_and_op_t,
+     const B64* addr);
+
+multimem.ld_reduce.acquire.cluster.global.and.b64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.ld_reduce.sem.scope.global.op.b64 dest, [addr]; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .acquire }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .and }
+   template <typename B64, enable_if_t<sizeof(B64) == 8, bool> = true, cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline B64 multimem_ld_reduce(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_and_op_t,
+     const B64* addr);
+
+multimem.ld_reduce.acquire.gpu.global.and.b64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.ld_reduce.sem.scope.global.op.b64 dest, [addr]; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .acquire }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .and }
+   template <typename B64, enable_if_t<sizeof(B64) == 8, bool> = true, cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline B64 multimem_ld_reduce(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_and_op_t,
+     const B64* addr);
+
+multimem.ld_reduce.acquire.sys.global.and.b64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.ld_reduce.sem.scope.global.op.b64 dest, [addr]; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .acquire }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .and }
+   template <typename B64, enable_if_t<sizeof(B64) == 8, bool> = true, cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline B64 multimem_ld_reduce(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_and_op_t,
+     const B64* addr);
+
+multimem.ld_reduce.weak.global.or.b64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.ld_reduce.sem.global.op.b64 dest, [addr]; // PTX ISA 81, SM_90
+   // .sem       = { .weak }
+   // .op        = { .or }
+   template <typename B64, enable_if_t<sizeof(B64) == 8, bool> = true>
+   __device__ static inline B64 multimem_ld_reduce(
+     cuda::ptx::sem_weak_t,
+     cuda::ptx::op_or_op_t,
+     const B64* addr);
+
+multimem.ld_reduce.relaxed.cta.global.or.b64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.ld_reduce.sem.scope.global.op.b64 dest, [addr]; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .acquire }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .or }
+   template <typename B64, enable_if_t<sizeof(B64) == 8, bool> = true, cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline B64 multimem_ld_reduce(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_or_op_t,
+     const B64* addr);
+
+multimem.ld_reduce.relaxed.cluster.global.or.b64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.ld_reduce.sem.scope.global.op.b64 dest, [addr]; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .acquire }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .or }
+   template <typename B64, enable_if_t<sizeof(B64) == 8, bool> = true, cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline B64 multimem_ld_reduce(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_or_op_t,
+     const B64* addr);
+
+multimem.ld_reduce.relaxed.gpu.global.or.b64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.ld_reduce.sem.scope.global.op.b64 dest, [addr]; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .acquire }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .or }
+   template <typename B64, enable_if_t<sizeof(B64) == 8, bool> = true, cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline B64 multimem_ld_reduce(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_or_op_t,
+     const B64* addr);
+
+multimem.ld_reduce.relaxed.sys.global.or.b64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.ld_reduce.sem.scope.global.op.b64 dest, [addr]; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .acquire }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .or }
+   template <typename B64, enable_if_t<sizeof(B64) == 8, bool> = true, cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline B64 multimem_ld_reduce(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_or_op_t,
+     const B64* addr);
+
+multimem.ld_reduce.acquire.cta.global.or.b64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.ld_reduce.sem.scope.global.op.b64 dest, [addr]; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .acquire }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .or }
+   template <typename B64, enable_if_t<sizeof(B64) == 8, bool> = true, cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline B64 multimem_ld_reduce(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_or_op_t,
+     const B64* addr);
+
+multimem.ld_reduce.acquire.cluster.global.or.b64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.ld_reduce.sem.scope.global.op.b64 dest, [addr]; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .acquire }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .or }
+   template <typename B64, enable_if_t<sizeof(B64) == 8, bool> = true, cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline B64 multimem_ld_reduce(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_or_op_t,
+     const B64* addr);
+
+multimem.ld_reduce.acquire.gpu.global.or.b64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.ld_reduce.sem.scope.global.op.b64 dest, [addr]; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .acquire }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .or }
+   template <typename B64, enable_if_t<sizeof(B64) == 8, bool> = true, cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline B64 multimem_ld_reduce(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_or_op_t,
+     const B64* addr);
+
+multimem.ld_reduce.acquire.sys.global.or.b64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.ld_reduce.sem.scope.global.op.b64 dest, [addr]; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .acquire }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .or }
+   template <typename B64, enable_if_t<sizeof(B64) == 8, bool> = true, cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline B64 multimem_ld_reduce(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_or_op_t,
+     const B64* addr);
+
+multimem.ld_reduce.weak.global.xor.b64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.ld_reduce.sem.global.op.b64 dest, [addr]; // PTX ISA 81, SM_90
+   // .sem       = { .weak }
+   // .op        = { .xor }
+   template <typename B64, enable_if_t<sizeof(B64) == 8, bool> = true>
+   __device__ static inline B64 multimem_ld_reduce(
+     cuda::ptx::sem_weak_t,
+     cuda::ptx::op_xor_op_t,
+     const B64* addr);
+
+multimem.ld_reduce.relaxed.cta.global.xor.b64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.ld_reduce.sem.scope.global.op.b64 dest, [addr]; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .acquire }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .xor }
+   template <typename B64, enable_if_t<sizeof(B64) == 8, bool> = true, cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline B64 multimem_ld_reduce(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_xor_op_t,
+     const B64* addr);
+
+multimem.ld_reduce.relaxed.cluster.global.xor.b64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.ld_reduce.sem.scope.global.op.b64 dest, [addr]; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .acquire }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .xor }
+   template <typename B64, enable_if_t<sizeof(B64) == 8, bool> = true, cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline B64 multimem_ld_reduce(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_xor_op_t,
+     const B64* addr);
+
+multimem.ld_reduce.relaxed.gpu.global.xor.b64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.ld_reduce.sem.scope.global.op.b64 dest, [addr]; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .acquire }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .xor }
+   template <typename B64, enable_if_t<sizeof(B64) == 8, bool> = true, cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline B64 multimem_ld_reduce(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_xor_op_t,
+     const B64* addr);
+
+multimem.ld_reduce.relaxed.sys.global.xor.b64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.ld_reduce.sem.scope.global.op.b64 dest, [addr]; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .acquire }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .xor }
+   template <typename B64, enable_if_t<sizeof(B64) == 8, bool> = true, cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline B64 multimem_ld_reduce(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_xor_op_t,
+     const B64* addr);
+
+multimem.ld_reduce.acquire.cta.global.xor.b64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.ld_reduce.sem.scope.global.op.b64 dest, [addr]; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .acquire }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .xor }
+   template <typename B64, enable_if_t<sizeof(B64) == 8, bool> = true, cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline B64 multimem_ld_reduce(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_xor_op_t,
+     const B64* addr);
+
+multimem.ld_reduce.acquire.cluster.global.xor.b64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.ld_reduce.sem.scope.global.op.b64 dest, [addr]; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .acquire }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .xor }
+   template <typename B64, enable_if_t<sizeof(B64) == 8, bool> = true, cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline B64 multimem_ld_reduce(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_xor_op_t,
+     const B64* addr);
+
+multimem.ld_reduce.acquire.gpu.global.xor.b64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.ld_reduce.sem.scope.global.op.b64 dest, [addr]; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .acquire }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .xor }
+   template <typename B64, enable_if_t<sizeof(B64) == 8, bool> = true, cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline B64 multimem_ld_reduce(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_xor_op_t,
+     const B64* addr);
+
+multimem.ld_reduce.acquire.sys.global.xor.b64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.ld_reduce.sem.scope.global.op.b64 dest, [addr]; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .acquire }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .xor }
+   template <typename B64, enable_if_t<sizeof(B64) == 8, bool> = true, cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline B64 multimem_ld_reduce(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_xor_op_t,
+     const B64* addr);
diff --git a/docs/libcudacxx/ptx/instructions/generated/multimem_red.rst b/docs/libcudacxx/ptx/instructions/generated/multimem_red.rst
new file mode 100644
index 00000000000..095efaef45c
--- /dev/null
+++ b/docs/libcudacxx/ptx/instructions/generated/multimem_red.rst
@@ -0,0 +1,2306 @@
+..
+   This file was automatically generated. Do not edit.
+
+multimem.red.relaxed.cta.global.min.u32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.red.sem.scope.global.op.u32 [addr], val; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .release }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .min }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline void multimem_red(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_min_t,
+     uint32_t* addr,
+     uint32_t val);
+
+multimem.red.relaxed.cluster.global.min.u32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.red.sem.scope.global.op.u32 [addr], val; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .release }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .min }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline void multimem_red(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_min_t,
+     uint32_t* addr,
+     uint32_t val);
+
+multimem.red.relaxed.gpu.global.min.u32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.red.sem.scope.global.op.u32 [addr], val; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .release }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .min }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline void multimem_red(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_min_t,
+     uint32_t* addr,
+     uint32_t val);
+
+multimem.red.relaxed.sys.global.min.u32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.red.sem.scope.global.op.u32 [addr], val; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .release }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .min }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline void multimem_red(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_min_t,
+     uint32_t* addr,
+     uint32_t val);
+
+multimem.red.release.cta.global.min.u32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.red.sem.scope.global.op.u32 [addr], val; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .release }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .min }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline void multimem_red(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_min_t,
+     uint32_t* addr,
+     uint32_t val);
+
+multimem.red.release.cluster.global.min.u32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.red.sem.scope.global.op.u32 [addr], val; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .release }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .min }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline void multimem_red(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_min_t,
+     uint32_t* addr,
+     uint32_t val);
+
+multimem.red.release.gpu.global.min.u32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.red.sem.scope.global.op.u32 [addr], val; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .release }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .min }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline void multimem_red(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_min_t,
+     uint32_t* addr,
+     uint32_t val);
+
+multimem.red.release.sys.global.min.u32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.red.sem.scope.global.op.u32 [addr], val; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .release }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .min }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline void multimem_red(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_min_t,
+     uint32_t* addr,
+     uint32_t val);
+
+multimem.red.relaxed.cta.global.min.u64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.red.sem.scope.global.op.u64 [addr], val; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .release }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .min }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline void multimem_red(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_min_t,
+     uint64_t* addr,
+     uint64_t val);
+
+multimem.red.relaxed.cluster.global.min.u64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.red.sem.scope.global.op.u64 [addr], val; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .release }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .min }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline void multimem_red(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_min_t,
+     uint64_t* addr,
+     uint64_t val);
+
+multimem.red.relaxed.gpu.global.min.u64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.red.sem.scope.global.op.u64 [addr], val; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .release }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .min }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline void multimem_red(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_min_t,
+     uint64_t* addr,
+     uint64_t val);
+
+multimem.red.relaxed.sys.global.min.u64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.red.sem.scope.global.op.u64 [addr], val; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .release }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .min }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline void multimem_red(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_min_t,
+     uint64_t* addr,
+     uint64_t val);
+
+multimem.red.release.cta.global.min.u64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.red.sem.scope.global.op.u64 [addr], val; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .release }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .min }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline void multimem_red(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_min_t,
+     uint64_t* addr,
+     uint64_t val);
+
+multimem.red.release.cluster.global.min.u64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.red.sem.scope.global.op.u64 [addr], val; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .release }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .min }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline void multimem_red(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_min_t,
+     uint64_t* addr,
+     uint64_t val);
+
+multimem.red.release.gpu.global.min.u64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.red.sem.scope.global.op.u64 [addr], val; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .release }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .min }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline void multimem_red(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_min_t,
+     uint64_t* addr,
+     uint64_t val);
+
+multimem.red.release.sys.global.min.u64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.red.sem.scope.global.op.u64 [addr], val; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .release }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .min }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline void multimem_red(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_min_t,
+     uint64_t* addr,
+     uint64_t val);
+
+multimem.red.relaxed.cta.global.min.s32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.red.sem.scope.global.op.s32 [addr], val; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .release }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .min }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline void multimem_red(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_min_t,
+     int32_t* addr,
+     int32_t val);
+
+multimem.red.relaxed.cluster.global.min.s32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.red.sem.scope.global.op.s32 [addr], val; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .release }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .min }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline void multimem_red(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_min_t,
+     int32_t* addr,
+     int32_t val);
+
+multimem.red.relaxed.gpu.global.min.s32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.red.sem.scope.global.op.s32 [addr], val; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .release }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .min }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline void multimem_red(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_min_t,
+     int32_t* addr,
+     int32_t val);
+
+multimem.red.relaxed.sys.global.min.s32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.red.sem.scope.global.op.s32 [addr], val; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .release }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .min }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline void multimem_red(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_min_t,
+     int32_t* addr,
+     int32_t val);
+
+multimem.red.release.cta.global.min.s32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.red.sem.scope.global.op.s32 [addr], val; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .release }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .min }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline void multimem_red(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_min_t,
+     int32_t* addr,
+     int32_t val);
+
+multimem.red.release.cluster.global.min.s32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.red.sem.scope.global.op.s32 [addr], val; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .release }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .min }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline void multimem_red(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_min_t,
+     int32_t* addr,
+     int32_t val);
+
+multimem.red.release.gpu.global.min.s32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.red.sem.scope.global.op.s32 [addr], val; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .release }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .min }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline void multimem_red(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_min_t,
+     int32_t* addr,
+     int32_t val);
+
+multimem.red.release.sys.global.min.s32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.red.sem.scope.global.op.s32 [addr], val; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .release }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .min }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline void multimem_red(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_min_t,
+     int32_t* addr,
+     int32_t val);
+
+multimem.red.relaxed.cta.global.min.s64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.red.sem.scope.global.op.s64 [addr], val; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .release }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .min }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline void multimem_red(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_min_t,
+     int64_t* addr,
+     int64_t val);
+
+multimem.red.relaxed.cluster.global.min.s64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.red.sem.scope.global.op.s64 [addr], val; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .release }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .min }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline void multimem_red(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_min_t,
+     int64_t* addr,
+     int64_t val);
+
+multimem.red.relaxed.gpu.global.min.s64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.red.sem.scope.global.op.s64 [addr], val; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .release }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .min }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline void multimem_red(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_min_t,
+     int64_t* addr,
+     int64_t val);
+
+multimem.red.relaxed.sys.global.min.s64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.red.sem.scope.global.op.s64 [addr], val; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .release }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .min }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline void multimem_red(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_min_t,
+     int64_t* addr,
+     int64_t val);
+
+multimem.red.release.cta.global.min.s64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.red.sem.scope.global.op.s64 [addr], val; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .release }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .min }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline void multimem_red(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_min_t,
+     int64_t* addr,
+     int64_t val);
+
+multimem.red.release.cluster.global.min.s64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.red.sem.scope.global.op.s64 [addr], val; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .release }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .min }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline void multimem_red(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_min_t,
+     int64_t* addr,
+     int64_t val);
+
+multimem.red.release.gpu.global.min.s64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.red.sem.scope.global.op.s64 [addr], val; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .release }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .min }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline void multimem_red(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_min_t,
+     int64_t* addr,
+     int64_t val);
+
+multimem.red.release.sys.global.min.s64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.red.sem.scope.global.op.s64 [addr], val; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .release }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .min }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline void multimem_red(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_min_t,
+     int64_t* addr,
+     int64_t val);
+
+multimem.red.relaxed.cta.global.max.u32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.red.sem.scope.global.op.u32 [addr], val; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .release }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .max }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline void multimem_red(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_max_t,
+     uint32_t* addr,
+     uint32_t val);
+
+multimem.red.relaxed.cluster.global.max.u32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.red.sem.scope.global.op.u32 [addr], val; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .release }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .max }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline void multimem_red(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_max_t,
+     uint32_t* addr,
+     uint32_t val);
+
+multimem.red.relaxed.gpu.global.max.u32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.red.sem.scope.global.op.u32 [addr], val; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .release }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .max }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline void multimem_red(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_max_t,
+     uint32_t* addr,
+     uint32_t val);
+
+multimem.red.relaxed.sys.global.max.u32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.red.sem.scope.global.op.u32 [addr], val; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .release }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .max }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline void multimem_red(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_max_t,
+     uint32_t* addr,
+     uint32_t val);
+
+multimem.red.release.cta.global.max.u32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.red.sem.scope.global.op.u32 [addr], val; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .release }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .max }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline void multimem_red(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_max_t,
+     uint32_t* addr,
+     uint32_t val);
+
+multimem.red.release.cluster.global.max.u32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.red.sem.scope.global.op.u32 [addr], val; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .release }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .max }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline void multimem_red(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_max_t,
+     uint32_t* addr,
+     uint32_t val);
+
+multimem.red.release.gpu.global.max.u32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.red.sem.scope.global.op.u32 [addr], val; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .release }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .max }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline void multimem_red(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_max_t,
+     uint32_t* addr,
+     uint32_t val);
+
+multimem.red.release.sys.global.max.u32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.red.sem.scope.global.op.u32 [addr], val; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .release }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .max }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline void multimem_red(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_max_t,
+     uint32_t* addr,
+     uint32_t val);
+
+multimem.red.relaxed.cta.global.max.u64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.red.sem.scope.global.op.u64 [addr], val; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .release }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .max }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline void multimem_red(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_max_t,
+     uint64_t* addr,
+     uint64_t val);
+
+multimem.red.relaxed.cluster.global.max.u64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.red.sem.scope.global.op.u64 [addr], val; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .release }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .max }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline void multimem_red(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_max_t,
+     uint64_t* addr,
+     uint64_t val);
+
+multimem.red.relaxed.gpu.global.max.u64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.red.sem.scope.global.op.u64 [addr], val; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .release }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .max }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline void multimem_red(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_max_t,
+     uint64_t* addr,
+     uint64_t val);
+
+multimem.red.relaxed.sys.global.max.u64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.red.sem.scope.global.op.u64 [addr], val; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .release }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .max }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline void multimem_red(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_max_t,
+     uint64_t* addr,
+     uint64_t val);
+
+multimem.red.release.cta.global.max.u64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.red.sem.scope.global.op.u64 [addr], val; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .release }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .max }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline void multimem_red(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_max_t,
+     uint64_t* addr,
+     uint64_t val);
+
+multimem.red.release.cluster.global.max.u64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.red.sem.scope.global.op.u64 [addr], val; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .release }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .max }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline void multimem_red(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_max_t,
+     uint64_t* addr,
+     uint64_t val);
+
+multimem.red.release.gpu.global.max.u64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.red.sem.scope.global.op.u64 [addr], val; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .release }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .max }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline void multimem_red(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_max_t,
+     uint64_t* addr,
+     uint64_t val);
+
+multimem.red.release.sys.global.max.u64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.red.sem.scope.global.op.u64 [addr], val; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .release }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .max }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline void multimem_red(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_max_t,
+     uint64_t* addr,
+     uint64_t val);
+
+multimem.red.relaxed.cta.global.max.s32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.red.sem.scope.global.op.s32 [addr], val; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .release }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .max }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline void multimem_red(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_max_t,
+     int32_t* addr,
+     int32_t val);
+
+multimem.red.relaxed.cluster.global.max.s32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.red.sem.scope.global.op.s32 [addr], val; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .release }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .max }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline void multimem_red(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_max_t,
+     int32_t* addr,
+     int32_t val);
+
+multimem.red.relaxed.gpu.global.max.s32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.red.sem.scope.global.op.s32 [addr], val; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .release }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .max }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline void multimem_red(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_max_t,
+     int32_t* addr,
+     int32_t val);
+
+multimem.red.relaxed.sys.global.max.s32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.red.sem.scope.global.op.s32 [addr], val; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .release }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .max }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline void multimem_red(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_max_t,
+     int32_t* addr,
+     int32_t val);
+
+multimem.red.release.cta.global.max.s32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.red.sem.scope.global.op.s32 [addr], val; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .release }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .max }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline void multimem_red(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_max_t,
+     int32_t* addr,
+     int32_t val);
+
+multimem.red.release.cluster.global.max.s32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.red.sem.scope.global.op.s32 [addr], val; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .release }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .max }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline void multimem_red(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_max_t,
+     int32_t* addr,
+     int32_t val);
+
+multimem.red.release.gpu.global.max.s32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.red.sem.scope.global.op.s32 [addr], val; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .release }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .max }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline void multimem_red(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_max_t,
+     int32_t* addr,
+     int32_t val);
+
+multimem.red.release.sys.global.max.s32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.red.sem.scope.global.op.s32 [addr], val; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .release }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .max }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline void multimem_red(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_max_t,
+     int32_t* addr,
+     int32_t val);
+
+multimem.red.relaxed.cta.global.max.s64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.red.sem.scope.global.op.s64 [addr], val; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .release }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .max }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline void multimem_red(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_max_t,
+     int64_t* addr,
+     int64_t val);
+
+multimem.red.relaxed.cluster.global.max.s64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.red.sem.scope.global.op.s64 [addr], val; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .release }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .max }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline void multimem_red(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_max_t,
+     int64_t* addr,
+     int64_t val);
+
+multimem.red.relaxed.gpu.global.max.s64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.red.sem.scope.global.op.s64 [addr], val; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .release }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .max }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline void multimem_red(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_max_t,
+     int64_t* addr,
+     int64_t val);
+
+multimem.red.relaxed.sys.global.max.s64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.red.sem.scope.global.op.s64 [addr], val; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .release }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .max }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline void multimem_red(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_max_t,
+     int64_t* addr,
+     int64_t val);
+
+multimem.red.release.cta.global.max.s64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.red.sem.scope.global.op.s64 [addr], val; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .release }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .max }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline void multimem_red(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_max_t,
+     int64_t* addr,
+     int64_t val);
+
+multimem.red.release.cluster.global.max.s64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.red.sem.scope.global.op.s64 [addr], val; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .release }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .max }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline void multimem_red(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_max_t,
+     int64_t* addr,
+     int64_t val);
+
+multimem.red.release.gpu.global.max.s64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.red.sem.scope.global.op.s64 [addr], val; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .release }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .max }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline void multimem_red(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_max_t,
+     int64_t* addr,
+     int64_t val);
+
+multimem.red.release.sys.global.max.s64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.red.sem.scope.global.op.s64 [addr], val; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .release }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .max }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline void multimem_red(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_max_t,
+     int64_t* addr,
+     int64_t val);
+
+multimem.red.relaxed.cta.global.add.u32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.red.sem.scope.global.op.u32 [addr], val; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .release }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .add }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline void multimem_red(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_add_t,
+     uint32_t* addr,
+     uint32_t val);
+
+multimem.red.relaxed.cluster.global.add.u32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.red.sem.scope.global.op.u32 [addr], val; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .release }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .add }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline void multimem_red(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_add_t,
+     uint32_t* addr,
+     uint32_t val);
+
+multimem.red.relaxed.gpu.global.add.u32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.red.sem.scope.global.op.u32 [addr], val; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .release }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .add }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline void multimem_red(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_add_t,
+     uint32_t* addr,
+     uint32_t val);
+
+multimem.red.relaxed.sys.global.add.u32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.red.sem.scope.global.op.u32 [addr], val; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .release }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .add }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline void multimem_red(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_add_t,
+     uint32_t* addr,
+     uint32_t val);
+
+multimem.red.release.cta.global.add.u32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.red.sem.scope.global.op.u32 [addr], val; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .release }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .add }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline void multimem_red(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_add_t,
+     uint32_t* addr,
+     uint32_t val);
+
+multimem.red.release.cluster.global.add.u32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.red.sem.scope.global.op.u32 [addr], val; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .release }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .add }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline void multimem_red(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_add_t,
+     uint32_t* addr,
+     uint32_t val);
+
+multimem.red.release.gpu.global.add.u32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.red.sem.scope.global.op.u32 [addr], val; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .release }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .add }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline void multimem_red(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_add_t,
+     uint32_t* addr,
+     uint32_t val);
+
+multimem.red.release.sys.global.add.u32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.red.sem.scope.global.op.u32 [addr], val; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .release }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .add }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline void multimem_red(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_add_t,
+     uint32_t* addr,
+     uint32_t val);
+
+multimem.red.relaxed.cta.global.add.u64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.red.sem.scope.global.op.u64 [addr], val; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .release }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .add }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline void multimem_red(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_add_t,
+     uint64_t* addr,
+     uint64_t val);
+
+multimem.red.relaxed.cluster.global.add.u64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.red.sem.scope.global.op.u64 [addr], val; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .release }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .add }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline void multimem_red(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_add_t,
+     uint64_t* addr,
+     uint64_t val);
+
+multimem.red.relaxed.gpu.global.add.u64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.red.sem.scope.global.op.u64 [addr], val; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .release }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .add }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline void multimem_red(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_add_t,
+     uint64_t* addr,
+     uint64_t val);
+
+multimem.red.relaxed.sys.global.add.u64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.red.sem.scope.global.op.u64 [addr], val; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .release }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .add }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline void multimem_red(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_add_t,
+     uint64_t* addr,
+     uint64_t val);
+
+multimem.red.release.cta.global.add.u64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.red.sem.scope.global.op.u64 [addr], val; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .release }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .add }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline void multimem_red(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_add_t,
+     uint64_t* addr,
+     uint64_t val);
+
+multimem.red.release.cluster.global.add.u64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.red.sem.scope.global.op.u64 [addr], val; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .release }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .add }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline void multimem_red(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_add_t,
+     uint64_t* addr,
+     uint64_t val);
+
+multimem.red.release.gpu.global.add.u64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.red.sem.scope.global.op.u64 [addr], val; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .release }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .add }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline void multimem_red(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_add_t,
+     uint64_t* addr,
+     uint64_t val);
+
+multimem.red.release.sys.global.add.u64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.red.sem.scope.global.op.u64 [addr], val; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .release }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .add }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline void multimem_red(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_add_t,
+     uint64_t* addr,
+     uint64_t val);
+
+multimem.red.relaxed.cta.global.add.s32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.red.sem.scope.global.op.s32 [addr], val; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .release }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .add }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline void multimem_red(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_add_t,
+     int32_t* addr,
+     int32_t val);
+
+multimem.red.relaxed.cluster.global.add.s32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.red.sem.scope.global.op.s32 [addr], val; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .release }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .add }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline void multimem_red(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_add_t,
+     int32_t* addr,
+     int32_t val);
+
+multimem.red.relaxed.gpu.global.add.s32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.red.sem.scope.global.op.s32 [addr], val; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .release }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .add }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline void multimem_red(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_add_t,
+     int32_t* addr,
+     int32_t val);
+
+multimem.red.relaxed.sys.global.add.s32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.red.sem.scope.global.op.s32 [addr], val; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .release }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .add }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline void multimem_red(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_add_t,
+     int32_t* addr,
+     int32_t val);
+
+multimem.red.release.cta.global.add.s32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.red.sem.scope.global.op.s32 [addr], val; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .release }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .add }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline void multimem_red(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_add_t,
+     int32_t* addr,
+     int32_t val);
+
+multimem.red.release.cluster.global.add.s32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.red.sem.scope.global.op.s32 [addr], val; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .release }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .add }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline void multimem_red(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_add_t,
+     int32_t* addr,
+     int32_t val);
+
+multimem.red.release.gpu.global.add.s32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.red.sem.scope.global.op.s32 [addr], val; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .release }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .add }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline void multimem_red(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_add_t,
+     int32_t* addr,
+     int32_t val);
+
+multimem.red.release.sys.global.add.s32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.red.sem.scope.global.op.s32 [addr], val; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .release }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .add }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline void multimem_red(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_add_t,
+     int32_t* addr,
+     int32_t val);
+
+multimem.red.relaxed.cta.global.add.u64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.red.sem.scope.global.op.u64 [addr], val; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .release }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .add }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline void multimem_red(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_add_t,
+     int64_t* addr,
+     int64_t val);
+
+multimem.red.relaxed.cluster.global.add.u64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.red.sem.scope.global.op.u64 [addr], val; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .release }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .add }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline void multimem_red(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_add_t,
+     int64_t* addr,
+     int64_t val);
+
+multimem.red.relaxed.gpu.global.add.u64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.red.sem.scope.global.op.u64 [addr], val; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .release }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .add }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline void multimem_red(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_add_t,
+     int64_t* addr,
+     int64_t val);
+
+multimem.red.relaxed.sys.global.add.u64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.red.sem.scope.global.op.u64 [addr], val; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .release }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .add }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline void multimem_red(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_add_t,
+     int64_t* addr,
+     int64_t val);
+
+multimem.red.release.cta.global.add.u64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.red.sem.scope.global.op.u64 [addr], val; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .release }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .add }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline void multimem_red(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_add_t,
+     int64_t* addr,
+     int64_t val);
+
+multimem.red.release.cluster.global.add.u64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.red.sem.scope.global.op.u64 [addr], val; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .release }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .add }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline void multimem_red(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_add_t,
+     int64_t* addr,
+     int64_t val);
+
+multimem.red.release.gpu.global.add.u64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.red.sem.scope.global.op.u64 [addr], val; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .release }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .add }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline void multimem_red(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_add_t,
+     int64_t* addr,
+     int64_t val);
+
+multimem.red.release.sys.global.add.u64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.red.sem.scope.global.op.u64 [addr], val; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .release }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .add }
+   template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline void multimem_red(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_add_t,
+     int64_t* addr,
+     int64_t val);
+
+multimem.red.relaxed.cta.global.and.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.red.sem.scope.global.op.b32 [addr], val; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .release }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .and }
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true, cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline void multimem_red(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_and_op_t,
+     B32* addr,
+     B32 val);
+
+multimem.red.relaxed.cluster.global.and.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.red.sem.scope.global.op.b32 [addr], val; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .release }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .and }
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true, cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline void multimem_red(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_and_op_t,
+     B32* addr,
+     B32 val);
+
+multimem.red.relaxed.gpu.global.and.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.red.sem.scope.global.op.b32 [addr], val; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .release }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .and }
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true, cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline void multimem_red(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_and_op_t,
+     B32* addr,
+     B32 val);
+
+multimem.red.relaxed.sys.global.and.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.red.sem.scope.global.op.b32 [addr], val; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .release }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .and }
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true, cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline void multimem_red(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_and_op_t,
+     B32* addr,
+     B32 val);
+
+multimem.red.release.cta.global.and.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.red.sem.scope.global.op.b32 [addr], val; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .release }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .and }
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true, cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline void multimem_red(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_and_op_t,
+     B32* addr,
+     B32 val);
+
+multimem.red.release.cluster.global.and.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.red.sem.scope.global.op.b32 [addr], val; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .release }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .and }
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true, cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline void multimem_red(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_and_op_t,
+     B32* addr,
+     B32 val);
+
+multimem.red.release.gpu.global.and.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.red.sem.scope.global.op.b32 [addr], val; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .release }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .and }
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true, cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline void multimem_red(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_and_op_t,
+     B32* addr,
+     B32 val);
+
+multimem.red.release.sys.global.and.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.red.sem.scope.global.op.b32 [addr], val; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .release }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .and }
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true, cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline void multimem_red(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_and_op_t,
+     B32* addr,
+     B32 val);
+
+multimem.red.relaxed.cta.global.or.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.red.sem.scope.global.op.b32 [addr], val; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .release }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .or }
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true, cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline void multimem_red(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_or_op_t,
+     B32* addr,
+     B32 val);
+
+multimem.red.relaxed.cluster.global.or.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.red.sem.scope.global.op.b32 [addr], val; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .release }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .or }
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true, cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline void multimem_red(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_or_op_t,
+     B32* addr,
+     B32 val);
+
+multimem.red.relaxed.gpu.global.or.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.red.sem.scope.global.op.b32 [addr], val; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .release }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .or }
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true, cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline void multimem_red(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_or_op_t,
+     B32* addr,
+     B32 val);
+
+multimem.red.relaxed.sys.global.or.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.red.sem.scope.global.op.b32 [addr], val; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .release }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .or }
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true, cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline void multimem_red(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_or_op_t,
+     B32* addr,
+     B32 val);
+
+multimem.red.release.cta.global.or.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.red.sem.scope.global.op.b32 [addr], val; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .release }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .or }
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true, cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline void multimem_red(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_or_op_t,
+     B32* addr,
+     B32 val);
+
+multimem.red.release.cluster.global.or.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.red.sem.scope.global.op.b32 [addr], val; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .release }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .or }
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true, cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline void multimem_red(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_or_op_t,
+     B32* addr,
+     B32 val);
+
+multimem.red.release.gpu.global.or.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.red.sem.scope.global.op.b32 [addr], val; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .release }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .or }
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true, cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline void multimem_red(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_or_op_t,
+     B32* addr,
+     B32 val);
+
+multimem.red.release.sys.global.or.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.red.sem.scope.global.op.b32 [addr], val; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .release }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .or }
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true, cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline void multimem_red(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_or_op_t,
+     B32* addr,
+     B32 val);
+
+multimem.red.relaxed.cta.global.xor.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.red.sem.scope.global.op.b32 [addr], val; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .release }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .xor }
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true, cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline void multimem_red(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_xor_op_t,
+     B32* addr,
+     B32 val);
+
+multimem.red.relaxed.cluster.global.xor.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.red.sem.scope.global.op.b32 [addr], val; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .release }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .xor }
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true, cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline void multimem_red(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_xor_op_t,
+     B32* addr,
+     B32 val);
+
+multimem.red.relaxed.gpu.global.xor.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.red.sem.scope.global.op.b32 [addr], val; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .release }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .xor }
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true, cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline void multimem_red(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_xor_op_t,
+     B32* addr,
+     B32 val);
+
+multimem.red.relaxed.sys.global.xor.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.red.sem.scope.global.op.b32 [addr], val; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .release }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .xor }
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true, cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline void multimem_red(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_xor_op_t,
+     B32* addr,
+     B32 val);
+
+multimem.red.release.cta.global.xor.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.red.sem.scope.global.op.b32 [addr], val; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .release }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .xor }
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true, cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline void multimem_red(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_xor_op_t,
+     B32* addr,
+     B32 val);
+
+multimem.red.release.cluster.global.xor.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.red.sem.scope.global.op.b32 [addr], val; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .release }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .xor }
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true, cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline void multimem_red(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_xor_op_t,
+     B32* addr,
+     B32 val);
+
+multimem.red.release.gpu.global.xor.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.red.sem.scope.global.op.b32 [addr], val; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .release }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .xor }
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true, cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline void multimem_red(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_xor_op_t,
+     B32* addr,
+     B32 val);
+
+multimem.red.release.sys.global.xor.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.red.sem.scope.global.op.b32 [addr], val; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .release }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .xor }
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true, cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline void multimem_red(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_xor_op_t,
+     B32* addr,
+     B32 val);
+
+multimem.red.relaxed.cta.global.and.b64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.red.sem.scope.global.op.b64 [addr], val; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .release }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .and }
+   template <typename B64, enable_if_t<sizeof(B64) == 8, bool> = true, cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline void multimem_red(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_and_op_t,
+     B64* addr,
+     B64 val);
+
+multimem.red.relaxed.cluster.global.and.b64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.red.sem.scope.global.op.b64 [addr], val; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .release }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .and }
+   template <typename B64, enable_if_t<sizeof(B64) == 8, bool> = true, cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline void multimem_red(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_and_op_t,
+     B64* addr,
+     B64 val);
+
+multimem.red.relaxed.gpu.global.and.b64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.red.sem.scope.global.op.b64 [addr], val; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .release }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .and }
+   template <typename B64, enable_if_t<sizeof(B64) == 8, bool> = true, cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline void multimem_red(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_and_op_t,
+     B64* addr,
+     B64 val);
+
+multimem.red.relaxed.sys.global.and.b64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.red.sem.scope.global.op.b64 [addr], val; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .release }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .and }
+   template <typename B64, enable_if_t<sizeof(B64) == 8, bool> = true, cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline void multimem_red(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_and_op_t,
+     B64* addr,
+     B64 val);
+
+multimem.red.release.cta.global.and.b64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.red.sem.scope.global.op.b64 [addr], val; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .release }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .and }
+   template <typename B64, enable_if_t<sizeof(B64) == 8, bool> = true, cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline void multimem_red(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_and_op_t,
+     B64* addr,
+     B64 val);
+
+multimem.red.release.cluster.global.and.b64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.red.sem.scope.global.op.b64 [addr], val; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .release }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .and }
+   template <typename B64, enable_if_t<sizeof(B64) == 8, bool> = true, cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline void multimem_red(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_and_op_t,
+     B64* addr,
+     B64 val);
+
+multimem.red.release.gpu.global.and.b64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.red.sem.scope.global.op.b64 [addr], val; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .release }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .and }
+   template <typename B64, enable_if_t<sizeof(B64) == 8, bool> = true, cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline void multimem_red(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_and_op_t,
+     B64* addr,
+     B64 val);
+
+multimem.red.release.sys.global.and.b64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.red.sem.scope.global.op.b64 [addr], val; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .release }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .and }
+   template <typename B64, enable_if_t<sizeof(B64) == 8, bool> = true, cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline void multimem_red(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_and_op_t,
+     B64* addr,
+     B64 val);
+
+multimem.red.relaxed.cta.global.or.b64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.red.sem.scope.global.op.b64 [addr], val; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .release }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .or }
+   template <typename B64, enable_if_t<sizeof(B64) == 8, bool> = true, cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline void multimem_red(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_or_op_t,
+     B64* addr,
+     B64 val);
+
+multimem.red.relaxed.cluster.global.or.b64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.red.sem.scope.global.op.b64 [addr], val; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .release }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .or }
+   template <typename B64, enable_if_t<sizeof(B64) == 8, bool> = true, cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline void multimem_red(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_or_op_t,
+     B64* addr,
+     B64 val);
+
+multimem.red.relaxed.gpu.global.or.b64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.red.sem.scope.global.op.b64 [addr], val; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .release }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .or }
+   template <typename B64, enable_if_t<sizeof(B64) == 8, bool> = true, cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline void multimem_red(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_or_op_t,
+     B64* addr,
+     B64 val);
+
+multimem.red.relaxed.sys.global.or.b64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.red.sem.scope.global.op.b64 [addr], val; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .release }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .or }
+   template <typename B64, enable_if_t<sizeof(B64) == 8, bool> = true, cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline void multimem_red(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_or_op_t,
+     B64* addr,
+     B64 val);
+
+multimem.red.release.cta.global.or.b64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.red.sem.scope.global.op.b64 [addr], val; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .release }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .or }
+   template <typename B64, enable_if_t<sizeof(B64) == 8, bool> = true, cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline void multimem_red(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_or_op_t,
+     B64* addr,
+     B64 val);
+
+multimem.red.release.cluster.global.or.b64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.red.sem.scope.global.op.b64 [addr], val; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .release }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .or }
+   template <typename B64, enable_if_t<sizeof(B64) == 8, bool> = true, cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline void multimem_red(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_or_op_t,
+     B64* addr,
+     B64 val);
+
+multimem.red.release.gpu.global.or.b64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.red.sem.scope.global.op.b64 [addr], val; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .release }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .or }
+   template <typename B64, enable_if_t<sizeof(B64) == 8, bool> = true, cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline void multimem_red(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_or_op_t,
+     B64* addr,
+     B64 val);
+
+multimem.red.release.sys.global.or.b64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.red.sem.scope.global.op.b64 [addr], val; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .release }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .or }
+   template <typename B64, enable_if_t<sizeof(B64) == 8, bool> = true, cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline void multimem_red(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_or_op_t,
+     B64* addr,
+     B64 val);
+
+multimem.red.relaxed.cta.global.xor.b64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.red.sem.scope.global.op.b64 [addr], val; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .release }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .xor }
+   template <typename B64, enable_if_t<sizeof(B64) == 8, bool> = true, cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline void multimem_red(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_xor_op_t,
+     B64* addr,
+     B64 val);
+
+multimem.red.relaxed.cluster.global.xor.b64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.red.sem.scope.global.op.b64 [addr], val; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .release }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .xor }
+   template <typename B64, enable_if_t<sizeof(B64) == 8, bool> = true, cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline void multimem_red(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_xor_op_t,
+     B64* addr,
+     B64 val);
+
+multimem.red.relaxed.gpu.global.xor.b64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.red.sem.scope.global.op.b64 [addr], val; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .release }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .xor }
+   template <typename B64, enable_if_t<sizeof(B64) == 8, bool> = true, cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline void multimem_red(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_xor_op_t,
+     B64* addr,
+     B64 val);
+
+multimem.red.relaxed.sys.global.xor.b64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.red.sem.scope.global.op.b64 [addr], val; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .release }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .xor }
+   template <typename B64, enable_if_t<sizeof(B64) == 8, bool> = true, cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline void multimem_red(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_xor_op_t,
+     B64* addr,
+     B64 val);
+
+multimem.red.release.cta.global.xor.b64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.red.sem.scope.global.op.b64 [addr], val; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .release }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .xor }
+   template <typename B64, enable_if_t<sizeof(B64) == 8, bool> = true, cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline void multimem_red(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_xor_op_t,
+     B64* addr,
+     B64 val);
+
+multimem.red.release.cluster.global.xor.b64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.red.sem.scope.global.op.b64 [addr], val; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .release }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .xor }
+   template <typename B64, enable_if_t<sizeof(B64) == 8, bool> = true, cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline void multimem_red(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_xor_op_t,
+     B64* addr,
+     B64 val);
+
+multimem.red.release.gpu.global.xor.b64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.red.sem.scope.global.op.b64 [addr], val; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .release }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .xor }
+   template <typename B64, enable_if_t<sizeof(B64) == 8, bool> = true, cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline void multimem_red(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_xor_op_t,
+     B64* addr,
+     B64 val);
+
+multimem.red.release.sys.global.xor.b64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.red.sem.scope.global.op.b64 [addr], val; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .release }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   // .op        = { .xor }
+   template <typename B64, enable_if_t<sizeof(B64) == 8, bool> = true, cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline void multimem_red(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     cuda::ptx::op_xor_op_t,
+     B64* addr,
+     B64 val);
diff --git a/docs/libcudacxx/ptx/instructions/generated/multimem_st.rst b/docs/libcudacxx/ptx/instructions/generated/multimem_st.rst
new file mode 100644
index 00000000000..00695328b76
--- /dev/null
+++ b/docs/libcudacxx/ptx/instructions/generated/multimem_st.rst
@@ -0,0 +1,250 @@
+..
+   This file was automatically generated. Do not edit.
+
+multimem.st.weak.global.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.st.sem.global.b32 [addr], val; // PTX ISA 81, SM_90
+   // .sem       = { .weak }
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+   __device__ static inline void multimem_st(
+     cuda::ptx::sem_weak_t,
+     B32* addr,
+     B32 val);
+
+multimem.st.relaxed.cta.global.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.st.sem.scope.global.b32 [addr], val; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .release }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true, cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline void multimem_st(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     B32* addr,
+     B32 val);
+
+multimem.st.relaxed.cluster.global.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.st.sem.scope.global.b32 [addr], val; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .release }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true, cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline void multimem_st(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     B32* addr,
+     B32 val);
+
+multimem.st.relaxed.gpu.global.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.st.sem.scope.global.b32 [addr], val; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .release }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true, cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline void multimem_st(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     B32* addr,
+     B32 val);
+
+multimem.st.relaxed.sys.global.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.st.sem.scope.global.b32 [addr], val; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .release }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true, cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline void multimem_st(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     B32* addr,
+     B32 val);
+
+multimem.st.release.cta.global.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.st.sem.scope.global.b32 [addr], val; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .release }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true, cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline void multimem_st(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     B32* addr,
+     B32 val);
+
+multimem.st.release.cluster.global.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.st.sem.scope.global.b32 [addr], val; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .release }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true, cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline void multimem_st(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     B32* addr,
+     B32 val);
+
+multimem.st.release.gpu.global.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.st.sem.scope.global.b32 [addr], val; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .release }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true, cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline void multimem_st(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     B32* addr,
+     B32 val);
+
+multimem.st.release.sys.global.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.st.sem.scope.global.b32 [addr], val; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .release }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true, cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline void multimem_st(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     B32* addr,
+     B32 val);
+
+multimem.st.weak.global.b64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.st.sem.global.b64 [addr], val; // PTX ISA 81, SM_90
+   // .sem       = { .weak }
+   template <typename B64, enable_if_t<sizeof(B64) == 8, bool> = true>
+   __device__ static inline void multimem_st(
+     cuda::ptx::sem_weak_t,
+     B64* addr,
+     B64 val);
+
+multimem.st.relaxed.cta.global.b64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.st.sem.scope.global.b64 [addr], val; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .release }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   template <typename B64, enable_if_t<sizeof(B64) == 8, bool> = true, cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline void multimem_st(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     B64* addr,
+     B64 val);
+
+multimem.st.relaxed.cluster.global.b64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.st.sem.scope.global.b64 [addr], val; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .release }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   template <typename B64, enable_if_t<sizeof(B64) == 8, bool> = true, cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline void multimem_st(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     B64* addr,
+     B64 val);
+
+multimem.st.relaxed.gpu.global.b64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.st.sem.scope.global.b64 [addr], val; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .release }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   template <typename B64, enable_if_t<sizeof(B64) == 8, bool> = true, cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline void multimem_st(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     B64* addr,
+     B64 val);
+
+multimem.st.relaxed.sys.global.b64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.st.sem.scope.global.b64 [addr], val; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .release }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   template <typename B64, enable_if_t<sizeof(B64) == 8, bool> = true, cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline void multimem_st(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     B64* addr,
+     B64 val);
+
+multimem.st.release.cta.global.b64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.st.sem.scope.global.b64 [addr], val; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .release }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   template <typename B64, enable_if_t<sizeof(B64) == 8, bool> = true, cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline void multimem_st(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     B64* addr,
+     B64 val);
+
+multimem.st.release.cluster.global.b64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.st.sem.scope.global.b64 [addr], val; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .release }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   template <typename B64, enable_if_t<sizeof(B64) == 8, bool> = true, cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline void multimem_st(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     B64* addr,
+     B64 val);
+
+multimem.st.release.gpu.global.b64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.st.sem.scope.global.b64 [addr], val; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .release }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   template <typename B64, enable_if_t<sizeof(B64) == 8, bool> = true, cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline void multimem_st(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     B64* addr,
+     B64 val);
+
+multimem.st.release.sys.global.b64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // multimem.st.sem.scope.global.b64 [addr], val; // PTX ISA 81, SM_90
+   // .sem       = { .relaxed, .release }
+   // .scope     = { .cta, .cluster, .gpu, .sys }
+   template <typename B64, enable_if_t<sizeof(B64) == 8, bool> = true, cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+   __device__ static inline void multimem_st(
+     cuda::ptx::sem_t<Sem> sem,
+     cuda::ptx::scope_t<Scope> scope,
+     B64* addr,
+     B64 val);
diff --git a/docs/libcudacxx/ptx/instructions/generated/red_async.rst b/docs/libcudacxx/ptx/instructions/generated/red_async.rst
index 658fe0a8f44..c575b808401 100644
--- a/docs/libcudacxx/ptx/instructions/generated/red_async.rst
+++ b/docs/libcudacxx/ptx/instructions/generated/red_async.rst
@@ -5,7 +5,7 @@ red.async.relaxed.cluster.shared::cluster.mbarrier::complete_tx::bytes.inc.u32
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 .. code:: cuda
 
-   // red.async.relaxed.cluster.shared::cluster.mbarrier::complete_tx::bytes{.op}{.type}  [dest], value, [remote_bar];  // PTX ISA 81, SM_90
+   // red.async.relaxed.cluster.shared::cluster.mbarrier::complete_tx::bytes.op.type  [dest], value, [remote_bar];  // PTX ISA 81, SM_90
    // .type      = { .u32 }
    // .op        = { .inc }
    template <typename = void>
@@ -19,7 +19,7 @@ red.async.relaxed.cluster.shared::cluster.mbarrier::complete_tx::bytes.dec.u32
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 .. code:: cuda
 
-   // red.async.relaxed.cluster.shared::cluster.mbarrier::complete_tx::bytes{.op}{.type}  [dest], value, [remote_bar];  // PTX ISA 81, SM_90
+   // red.async.relaxed.cluster.shared::cluster.mbarrier::complete_tx::bytes.op.type  [dest], value, [remote_bar];  // PTX ISA 81, SM_90
    // .type      = { .u32 }
    // .op        = { .dec }
    template <typename = void>
@@ -33,7 +33,7 @@ red.async.relaxed.cluster.shared::cluster.mbarrier::complete_tx::bytes.min.u32
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 .. code:: cuda
 
-   // red.async.relaxed.cluster.shared::cluster.mbarrier::complete_tx::bytes{.op}{.type}  [dest], value, [remote_bar];  // PTX ISA 81, SM_90
+   // red.async.relaxed.cluster.shared::cluster.mbarrier::complete_tx::bytes.op.type  [dest], value, [remote_bar];  // PTX ISA 81, SM_90
    // .type      = { .u32 }
    // .op        = { .min }
    template <typename = void>
@@ -47,7 +47,7 @@ red.async.relaxed.cluster.shared::cluster.mbarrier::complete_tx::bytes.max.u32
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 .. code:: cuda
 
-   // red.async.relaxed.cluster.shared::cluster.mbarrier::complete_tx::bytes{.op}{.type}  [dest], value, [remote_bar];  // PTX ISA 81, SM_90
+   // red.async.relaxed.cluster.shared::cluster.mbarrier::complete_tx::bytes.op.type  [dest], value, [remote_bar];  // PTX ISA 81, SM_90
    // .type      = { .u32 }
    // .op        = { .max }
    template <typename = void>
@@ -61,7 +61,7 @@ red.async.relaxed.cluster.shared::cluster.mbarrier::complete_tx::bytes.add.u32
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 .. code:: cuda
 
-   // red.async.relaxed.cluster.shared::cluster.mbarrier::complete_tx::bytes{.op}{.type}  [dest], value, [remote_bar];  // PTX ISA 81, SM_90
+   // red.async.relaxed.cluster.shared::cluster.mbarrier::complete_tx::bytes.op.type  [dest], value, [remote_bar];  // PTX ISA 81, SM_90
    // .type      = { .u32 }
    // .op        = { .add }
    template <typename = void>
@@ -75,7 +75,7 @@ red.async.relaxed.cluster.shared::cluster.mbarrier::complete_tx::bytes.min.s32
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 .. code:: cuda
 
-   // red.async.relaxed.cluster.shared::cluster.mbarrier::complete_tx::bytes{.op}{.type}  [dest], value, [remote_bar];  // PTX ISA 81, SM_90
+   // red.async.relaxed.cluster.shared::cluster.mbarrier::complete_tx::bytes.op.type  [dest], value, [remote_bar];  // PTX ISA 81, SM_90
    // .type      = { .s32 }
    // .op        = { .min }
    template <typename = void>
@@ -89,7 +89,7 @@ red.async.relaxed.cluster.shared::cluster.mbarrier::complete_tx::bytes.max.s32
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 .. code:: cuda
 
-   // red.async.relaxed.cluster.shared::cluster.mbarrier::complete_tx::bytes{.op}{.type}  [dest], value, [remote_bar];  // PTX ISA 81, SM_90
+   // red.async.relaxed.cluster.shared::cluster.mbarrier::complete_tx::bytes.op.type  [dest], value, [remote_bar];  // PTX ISA 81, SM_90
    // .type      = { .s32 }
    // .op        = { .max }
    template <typename = void>
@@ -103,7 +103,7 @@ red.async.relaxed.cluster.shared::cluster.mbarrier::complete_tx::bytes.add.s32
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 .. code:: cuda
 
-   // red.async.relaxed.cluster.shared::cluster.mbarrier::complete_tx::bytes{.op}{.type}  [dest], value, [remote_bar];  // PTX ISA 81, SM_90
+   // red.async.relaxed.cluster.shared::cluster.mbarrier::complete_tx::bytes.op.type  [dest], value, [remote_bar];  // PTX ISA 81, SM_90
    // .type      = { .s32 }
    // .op        = { .add }
    template <typename = void>
@@ -117,10 +117,10 @@ red.async.relaxed.cluster.shared::cluster.mbarrier::complete_tx::bytes.and.b32
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 .. code:: cuda
 
-   // red.async.relaxed.cluster.shared::cluster.mbarrier::complete_tx::bytes{.op}{.type}  [dest], value, [remote_bar];  // PTX ISA 81, SM_90
+   // red.async.relaxed.cluster.shared::cluster.mbarrier::complete_tx::bytes.op.type  [dest], value, [remote_bar];  // PTX ISA 81, SM_90
    // .type      = { .b32 }
    // .op        = { .and }
-   template <typename B32>
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
    __device__ static inline void red_async(
      cuda::ptx::op_and_op_t,
      B32* dest,
@@ -131,10 +131,10 @@ red.async.relaxed.cluster.shared::cluster.mbarrier::complete_tx::bytes.or.b32
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 .. code:: cuda
 
-   // red.async.relaxed.cluster.shared::cluster.mbarrier::complete_tx::bytes{.op}{.type}  [dest], value, [remote_bar];  // PTX ISA 81, SM_90
+   // red.async.relaxed.cluster.shared::cluster.mbarrier::complete_tx::bytes.op.type  [dest], value, [remote_bar];  // PTX ISA 81, SM_90
    // .type      = { .b32 }
    // .op        = { .or }
-   template <typename B32>
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
    __device__ static inline void red_async(
      cuda::ptx::op_or_op_t,
      B32* dest,
@@ -145,10 +145,10 @@ red.async.relaxed.cluster.shared::cluster.mbarrier::complete_tx::bytes.xor.b32
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 .. code:: cuda
 
-   // red.async.relaxed.cluster.shared::cluster.mbarrier::complete_tx::bytes{.op}{.type}  [dest], value, [remote_bar];  // PTX ISA 81, SM_90
+   // red.async.relaxed.cluster.shared::cluster.mbarrier::complete_tx::bytes.op.type  [dest], value, [remote_bar];  // PTX ISA 81, SM_90
    // .type      = { .b32 }
    // .op        = { .xor }
-   template <typename B32>
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
    __device__ static inline void red_async(
      cuda::ptx::op_xor_op_t,
      B32* dest,
@@ -159,7 +159,7 @@ red.async.relaxed.cluster.shared::cluster.mbarrier::complete_tx::bytes.add.u64
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 .. code:: cuda
 
-   // red.async.relaxed.cluster.shared::cluster.mbarrier::complete_tx::bytes{.op}{.type}  [dest], value, [remote_bar];  // PTX ISA 81, SM_90
+   // red.async.relaxed.cluster.shared::cluster.mbarrier::complete_tx::bytes.op.type  [dest], value, [remote_bar];  // PTX ISA 81, SM_90
    // .type      = { .u64 }
    // .op        = { .add }
    template <typename = void>
@@ -173,7 +173,7 @@ red.async.relaxed.cluster.shared::cluster.mbarrier::complete_tx::bytes.add.u64
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 .. code:: cuda
 
-   // red.async.relaxed.cluster.shared::cluster.mbarrier::complete_tx::bytes{.op}.u64  [dest], value, [remote_bar]; // .u64 intentional PTX ISA 81, SM_90
+   // red.async.relaxed.cluster.shared::cluster.mbarrier::complete_tx::bytes.op.u64  [dest], value, [remote_bar]; // .u64 intentional PTX ISA 81, SM_90
    // .op        = { .add }
    template <typename = void>
    __device__ static inline void red_async(
diff --git a/docs/libcudacxx/ptx/instructions/generated/st_async.rst b/docs/libcudacxx/ptx/instructions/generated/st_async.rst
index d00a152cf29..8cfc21ba0b5 100644
--- a/docs/libcudacxx/ptx/instructions/generated/st_async.rst
+++ b/docs/libcudacxx/ptx/instructions/generated/st_async.rst
@@ -5,7 +5,7 @@ st.async.weak.shared::cluster.mbarrier::complete_tx::bytes.b32
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 .. code:: cuda
 
-   // st.async.weak.shared::cluster.mbarrier::complete_tx::bytes{.type} [addr], value, [remote_bar];    // 1.  PTX ISA 81, SM_90
+   // st.async.weak.shared::cluster.mbarrier::complete_tx::bytes.type [addr], value, [remote_bar];    // 1.  PTX ISA 81, SM_90
    // .type      = { .b32, .b64 }
    template <typename Type>
    __device__ static inline void st_async(
@@ -17,7 +17,7 @@ st.async.weak.shared::cluster.mbarrier::complete_tx::bytes.b64
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 .. code:: cuda
 
-   // st.async.weak.shared::cluster.mbarrier::complete_tx::bytes{.type} [addr], value, [remote_bar];    // 1.  PTX ISA 81, SM_90
+   // st.async.weak.shared::cluster.mbarrier::complete_tx::bytes.type [addr], value, [remote_bar];    // 1.  PTX ISA 81, SM_90
    // .type      = { .b32, .b64 }
    template <typename Type>
    __device__ static inline void st_async(
@@ -29,7 +29,7 @@ st.async.weak.shared::cluster.mbarrier::complete_tx::bytes.v2.b32
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 .. code:: cuda
 
-   // st.async.weak.shared::cluster.mbarrier::complete_tx::bytes.v2{.type} [addr], value, [remote_bar]; // 2.  PTX ISA 81, SM_90
+   // st.async.weak.shared::cluster.mbarrier::complete_tx::bytes.v2.type [addr], value, [remote_bar]; // 2.  PTX ISA 81, SM_90
    // .type      = { .b32, .b64 }
    template <typename Type>
    __device__ static inline void st_async(
@@ -41,7 +41,7 @@ st.async.weak.shared::cluster.mbarrier::complete_tx::bytes.v2.b64
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 .. code:: cuda
 
-   // st.async.weak.shared::cluster.mbarrier::complete_tx::bytes.v2{.type} [addr], value, [remote_bar]; // 2.  PTX ISA 81, SM_90
+   // st.async.weak.shared::cluster.mbarrier::complete_tx::bytes.v2.type [addr], value, [remote_bar]; // 2.  PTX ISA 81, SM_90
    // .type      = { .b32, .b64 }
    template <typename Type>
    __device__ static inline void st_async(
@@ -54,7 +54,7 @@ st.async.weak.shared::cluster.mbarrier::complete_tx::bytes.v4.b32
 .. code:: cuda
 
    // st.async.weak.shared::cluster.mbarrier::complete_tx::bytes.v4.b32 [addr], value, [remote_bar];    // 3.  PTX ISA 81, SM_90
-   template <typename B32>
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
    __device__ static inline void st_async(
      B32* addr,
      const B32 (&value)[4],
diff --git a/docs/libcudacxx/ptx/instructions/generated/st_bulk.rst b/docs/libcudacxx/ptx/instructions/generated/st_bulk.rst
new file mode 100644
index 00000000000..817d3875fdc
--- /dev/null
+++ b/docs/libcudacxx/ptx/instructions/generated/st_bulk.rst
@@ -0,0 +1,13 @@
+..
+   This file was automatically generated. Do not edit.
+
+st.bulk.weak.shared::cta
+^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // st.bulk.weak.shared::cta [addr], size, initval; // PTX ISA 86, SM_100
+   template <int N32>
+   __device__ static inline void st_bulk(
+     void* addr,
+     uint64_t size,
+     cuda::ptx::n32_t<N32> initval);
diff --git a/docs/libcudacxx/ptx/instructions/generated/tcgen05_alloc.rst b/docs/libcudacxx/ptx/instructions/generated/tcgen05_alloc.rst
new file mode 100644
index 00000000000..3bfb60fca71
--- /dev/null
+++ b/docs/libcudacxx/ptx/instructions/generated/tcgen05_alloc.rst
@@ -0,0 +1,70 @@
+..
+   This file was automatically generated. Do not edit.
+
+tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.alloc.cta_group.sync.aligned.shared::cta.b32 [dst], nCols; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void tcgen05_alloc(
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     uint32_t* dst,
+     const uint32_t& nCols);
+
+tcgen05.alloc.cta_group::2.sync.aligned.shared::cta.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.alloc.cta_group.sync.aligned.shared::cta.b32 [dst], nCols; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void tcgen05_alloc(
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     uint32_t* dst,
+     const uint32_t& nCols);
+
+tcgen05.dealloc.cta_group::1.sync.aligned.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.dealloc.cta_group.sync.aligned.b32 taddr, nCols; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void tcgen05_dealloc(
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     uint32_t taddr,
+     const uint32_t& nCols);
+
+tcgen05.dealloc.cta_group::2.sync.aligned.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.dealloc.cta_group.sync.aligned.b32 taddr, nCols; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void tcgen05_dealloc(
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     uint32_t taddr,
+     const uint32_t& nCols);
+
+tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.relinquish_alloc_permit.cta_group.sync.aligned; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void tcgen05_relinquish_alloc_permit(
+     cuda::ptx::cta_group_t<Cta_Group> cta_group);
+
+tcgen05.relinquish_alloc_permit.cta_group::2.sync.aligned
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.relinquish_alloc_permit.cta_group.sync.aligned; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void tcgen05_relinquish_alloc_permit(
+     cuda::ptx::cta_group_t<Cta_Group> cta_group);
diff --git a/docs/libcudacxx/ptx/instructions/generated/tcgen05_commit.rst b/docs/libcudacxx/ptx/instructions/generated/tcgen05_commit.rst
new file mode 100644
index 00000000000..d5546fed3e5
--- /dev/null
+++ b/docs/libcudacxx/ptx/instructions/generated/tcgen05_commit.rst
@@ -0,0 +1,48 @@
+..
+   This file was automatically generated. Do not edit.
+
+tcgen05.commit.cta_group::1.mbarrier::arrive::one.shared::cluster.b64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.commit.cta_group.mbarrier::arrive::one.shared::cluster.b64 [smem_bar]; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void tcgen05_commit(
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     uint64_t* smem_bar);
+
+tcgen05.commit.cta_group::2.mbarrier::arrive::one.shared::cluster.b64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.commit.cta_group.mbarrier::arrive::one.shared::cluster.b64 [smem_bar]; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void tcgen05_commit(
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     uint64_t* smem_bar);
+
+tcgen05.commit.cta_group::1.mbarrier::arrive::one.shared::cluster.multicast::cluster.b64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.commit.cta_group.mbarrier::arrive::one.shared::cluster.multicast::cluster.b64 [smem_bar], ctaMask; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void tcgen05_commit_multicast(
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     uint64_t* smem_bar,
+     uint16_t ctaMask);
+
+tcgen05.commit.cta_group::2.mbarrier::arrive::one.shared::cluster.multicast::cluster.b64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.commit.cta_group.mbarrier::arrive::one.shared::cluster.multicast::cluster.b64 [smem_bar], ctaMask; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void tcgen05_commit_multicast(
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     uint64_t* smem_bar,
+     uint16_t ctaMask);
diff --git a/docs/libcudacxx/ptx/instructions/generated/tcgen05_cp.rst b/docs/libcudacxx/ptx/instructions/generated/tcgen05_cp.rst
new file mode 100644
index 00000000000..b0195c5b28e
--- /dev/null
+++ b/docs/libcudacxx/ptx/instructions/generated/tcgen05_cp.rst
@@ -0,0 +1,434 @@
+..
+   This file was automatically generated. Do not edit.
+
+tcgen05.cp.cta_group::1.128x256b
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.cp.cta_group.128x256b [taddr], s_desc; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void tcgen05_cp_128x256b(
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     uint32_t taddr,
+     uint64_t s_desc);
+
+tcgen05.cp.cta_group::2.128x256b
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.cp.cta_group.128x256b [taddr], s_desc; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void tcgen05_cp_128x256b(
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     uint32_t taddr,
+     uint64_t s_desc);
+
+tcgen05.cp.cta_group::1.4x256b
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.cp.cta_group.4x256b [taddr], s_desc; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void tcgen05_cp_4x256b(
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     uint32_t taddr,
+     uint64_t s_desc);
+
+tcgen05.cp.cta_group::2.4x256b
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.cp.cta_group.4x256b [taddr], s_desc; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void tcgen05_cp_4x256b(
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     uint32_t taddr,
+     uint64_t s_desc);
+
+tcgen05.cp.cta_group::1.128x128b
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.cp.cta_group.128x128b [taddr], s_desc; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void tcgen05_cp_128x128b(
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     uint32_t taddr,
+     uint64_t s_desc);
+
+tcgen05.cp.cta_group::2.128x128b
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.cp.cta_group.128x128b [taddr], s_desc; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void tcgen05_cp_128x128b(
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     uint32_t taddr,
+     uint64_t s_desc);
+
+tcgen05.cp.cta_group::1.64x128b.warpx2::02_13
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.cp.cta_group.64x128b.warpx2::02_13 [taddr], s_desc; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void tcgen05_cp_64x128b_warpx2_02_13(
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     uint32_t taddr,
+     uint64_t s_desc);
+
+tcgen05.cp.cta_group::2.64x128b.warpx2::02_13
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.cp.cta_group.64x128b.warpx2::02_13 [taddr], s_desc; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void tcgen05_cp_64x128b_warpx2_02_13(
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     uint32_t taddr,
+     uint64_t s_desc);
+
+tcgen05.cp.cta_group::1.64x128b.warpx2::01_23
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.cp.cta_group.64x128b.warpx2::01_23 [taddr], s_desc; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void tcgen05_cp_64x128b_warpx2_01_23(
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     uint32_t taddr,
+     uint64_t s_desc);
+
+tcgen05.cp.cta_group::2.64x128b.warpx2::01_23
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.cp.cta_group.64x128b.warpx2::01_23 [taddr], s_desc; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void tcgen05_cp_64x128b_warpx2_01_23(
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     uint32_t taddr,
+     uint64_t s_desc);
+
+tcgen05.cp.cta_group::1.32x128b.warpx4
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.cp.cta_group.32x128b.warpx4 [taddr], s_desc; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void tcgen05_cp_32x128b_warpx4(
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     uint32_t taddr,
+     uint64_t s_desc);
+
+tcgen05.cp.cta_group::2.32x128b.warpx4
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.cp.cta_group.32x128b.warpx4 [taddr], s_desc; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void tcgen05_cp_32x128b_warpx4(
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     uint32_t taddr,
+     uint64_t s_desc);
+
+tcgen05.cp.cta_group::1.128x256b.b8x16.b6x16_p32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.cp.cta_group.128x256b.b8x16.b6x16_p32 [taddr], s_desc; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void tcgen05_cp_128x256b_b8x16_b6x16_p32(
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     uint32_t taddr,
+     uint64_t s_desc);
+
+tcgen05.cp.cta_group::2.128x256b.b8x16.b6x16_p32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.cp.cta_group.128x256b.b8x16.b6x16_p32 [taddr], s_desc; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void tcgen05_cp_128x256b_b8x16_b6x16_p32(
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     uint32_t taddr,
+     uint64_t s_desc);
+
+tcgen05.cp.cta_group::1.4x256b.b8x16.b6x16_p32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.cp.cta_group.4x256b.b8x16.b6x16_p32 [taddr], s_desc; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void tcgen05_cp_4x256b_b8x16_b6x16_p32(
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     uint32_t taddr,
+     uint64_t s_desc);
+
+tcgen05.cp.cta_group::2.4x256b.b8x16.b6x16_p32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.cp.cta_group.4x256b.b8x16.b6x16_p32 [taddr], s_desc; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void tcgen05_cp_4x256b_b8x16_b6x16_p32(
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     uint32_t taddr,
+     uint64_t s_desc);
+
+tcgen05.cp.cta_group::1.128x128b.b8x16.b6x16_p32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.cp.cta_group.128x128b.b8x16.b6x16_p32 [taddr], s_desc; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void tcgen05_cp_128x128b_b8x16_b6x16_p32(
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     uint32_t taddr,
+     uint64_t s_desc);
+
+tcgen05.cp.cta_group::2.128x128b.b8x16.b6x16_p32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.cp.cta_group.128x128b.b8x16.b6x16_p32 [taddr], s_desc; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void tcgen05_cp_128x128b_b8x16_b6x16_p32(
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     uint32_t taddr,
+     uint64_t s_desc);
+
+tcgen05.cp.cta_group::1.64x128b.warpx2::02_13.b8x16.b6x16_p32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.cp.cta_group.64x128b.warpx2::02_13.b8x16.b6x16_p32 [taddr], s_desc; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void tcgen05_cp_64x128b_warpx2_02_13_b8x16_b6x16_p32(
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     uint32_t taddr,
+     uint64_t s_desc);
+
+tcgen05.cp.cta_group::2.64x128b.warpx2::02_13.b8x16.b6x16_p32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.cp.cta_group.64x128b.warpx2::02_13.b8x16.b6x16_p32 [taddr], s_desc; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void tcgen05_cp_64x128b_warpx2_02_13_b8x16_b6x16_p32(
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     uint32_t taddr,
+     uint64_t s_desc);
+
+tcgen05.cp.cta_group::1.64x128b.warpx2::01_23.b8x16.b6x16_p32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.cp.cta_group.64x128b.warpx2::01_23.b8x16.b6x16_p32 [taddr], s_desc; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void tcgen05_cp_64x128b_warpx2_01_23_b8x16_b6x16_p32(
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     uint32_t taddr,
+     uint64_t s_desc);
+
+tcgen05.cp.cta_group::2.64x128b.warpx2::01_23.b8x16.b6x16_p32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.cp.cta_group.64x128b.warpx2::01_23.b8x16.b6x16_p32 [taddr], s_desc; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void tcgen05_cp_64x128b_warpx2_01_23_b8x16_b6x16_p32(
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     uint32_t taddr,
+     uint64_t s_desc);
+
+tcgen05.cp.cta_group::1.32x128b.warpx4.b8x16.b6x16_p32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.cp.cta_group.32x128b.warpx4.b8x16.b6x16_p32 [taddr], s_desc; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void tcgen05_cp_32x128b_warpx4_b8x16_b6x16_p32(
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     uint32_t taddr,
+     uint64_t s_desc);
+
+tcgen05.cp.cta_group::2.32x128b.warpx4.b8x16.b6x16_p32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.cp.cta_group.32x128b.warpx4.b8x16.b6x16_p32 [taddr], s_desc; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void tcgen05_cp_32x128b_warpx4_b8x16_b6x16_p32(
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     uint32_t taddr,
+     uint64_t s_desc);
+
+tcgen05.cp.cta_group::1.128x256b.b8x16.b4x16_p64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.cp.cta_group.128x256b.b8x16.b4x16_p64 [taddr], s_desc; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void tcgen05_cp_128x256b_b8x16_b4x16_p64(
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     uint32_t taddr,
+     uint64_t s_desc);
+
+tcgen05.cp.cta_group::2.128x256b.b8x16.b4x16_p64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.cp.cta_group.128x256b.b8x16.b4x16_p64 [taddr], s_desc; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void tcgen05_cp_128x256b_b8x16_b4x16_p64(
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     uint32_t taddr,
+     uint64_t s_desc);
+
+tcgen05.cp.cta_group::1.4x256b.b8x16.b4x16_p64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.cp.cta_group.4x256b.b8x16.b4x16_p64 [taddr], s_desc; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void tcgen05_cp_4x256b_b8x16_b4x16_p64(
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     uint32_t taddr,
+     uint64_t s_desc);
+
+tcgen05.cp.cta_group::2.4x256b.b8x16.b4x16_p64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.cp.cta_group.4x256b.b8x16.b4x16_p64 [taddr], s_desc; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void tcgen05_cp_4x256b_b8x16_b4x16_p64(
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     uint32_t taddr,
+     uint64_t s_desc);
+
+tcgen05.cp.cta_group::1.128x128b.b8x16.b4x16_p64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.cp.cta_group.128x128b.b8x16.b4x16_p64 [taddr], s_desc; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void tcgen05_cp_128x128b_b8x16_b4x16_p64(
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     uint32_t taddr,
+     uint64_t s_desc);
+
+tcgen05.cp.cta_group::2.128x128b.b8x16.b4x16_p64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.cp.cta_group.128x128b.b8x16.b4x16_p64 [taddr], s_desc; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void tcgen05_cp_128x128b_b8x16_b4x16_p64(
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     uint32_t taddr,
+     uint64_t s_desc);
+
+tcgen05.cp.cta_group::1.64x128b.warpx2::02_13.b8x16.b4x16_p64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.cp.cta_group.64x128b.warpx2::02_13.b8x16.b4x16_p64 [taddr], s_desc; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void tcgen05_cp_64x128b_warpx2_02_13_b8x16_b4x16_p64(
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     uint32_t taddr,
+     uint64_t s_desc);
+
+tcgen05.cp.cta_group::2.64x128b.warpx2::02_13.b8x16.b4x16_p64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.cp.cta_group.64x128b.warpx2::02_13.b8x16.b4x16_p64 [taddr], s_desc; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void tcgen05_cp_64x128b_warpx2_02_13_b8x16_b4x16_p64(
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     uint32_t taddr,
+     uint64_t s_desc);
+
+tcgen05.cp.cta_group::1.64x128b.warpx2::01_23.b8x16.b4x16_p64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.cp.cta_group.64x128b.warpx2::01_23.b8x16.b4x16_p64 [taddr], s_desc; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void tcgen05_cp_64x128b_warpx2_01_23_b8x16_b4x16_p64(
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     uint32_t taddr,
+     uint64_t s_desc);
+
+tcgen05.cp.cta_group::2.64x128b.warpx2::01_23.b8x16.b4x16_p64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.cp.cta_group.64x128b.warpx2::01_23.b8x16.b4x16_p64 [taddr], s_desc; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void tcgen05_cp_64x128b_warpx2_01_23_b8x16_b4x16_p64(
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     uint32_t taddr,
+     uint64_t s_desc);
+
+tcgen05.cp.cta_group::1.32x128b.warpx4.b8x16.b4x16_p64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.cp.cta_group.32x128b.warpx4.b8x16.b4x16_p64 [taddr], s_desc; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void tcgen05_cp_32x128b_warpx4_b8x16_b4x16_p64(
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     uint32_t taddr,
+     uint64_t s_desc);
+
+tcgen05.cp.cta_group::2.32x128b.warpx4.b8x16.b4x16_p64
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.cp.cta_group.32x128b.warpx4.b8x16.b4x16_p64 [taddr], s_desc; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void tcgen05_cp_32x128b_warpx4_b8x16_b4x16_p64(
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     uint32_t taddr,
+     uint64_t s_desc);
diff --git a/docs/libcudacxx/ptx/instructions/generated/tcgen05_fence.rst b/docs/libcudacxx/ptx/instructions/generated/tcgen05_fence.rst
new file mode 100644
index 00000000000..ee287ea8860
--- /dev/null
+++ b/docs/libcudacxx/ptx/instructions/generated/tcgen05_fence.rst
@@ -0,0 +1,18 @@
+..
+   This file was automatically generated. Do not edit.
+
+tcgen05.fence::before_thread_sync
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.fence::before_thread_sync; // PTX ISA 86, SM_100a, SM_101a
+   template <typename = void>
+   __device__ static inline void tcgen05_fence_before_thread_sync();
+
+tcgen05.fence::after_thread_sync
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.fence::after_thread_sync; // PTX ISA 86, SM_100a, SM_101a
+   template <typename = void>
+   __device__ static inline void tcgen05_fence_after_thread_sync();
diff --git a/docs/libcudacxx/ptx/instructions/generated/tcgen05_ld.rst b/docs/libcudacxx/ptx/instructions/generated/tcgen05_ld.rst
new file mode 100644
index 00000000000..0bb6bdbb5f5
--- /dev/null
+++ b/docs/libcudacxx/ptx/instructions/generated/tcgen05_ld.rst
@@ -0,0 +1,758 @@
+..
+   This file was automatically generated. Do not edit.
+
+tcgen05.ld.sync.aligned.16x64b.x1.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.ld.sync.aligned.16x64b.x1.b32 out, [taddr]; // PTX ISA 86, SM_100a, SM_101a
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+   __device__ static inline void tcgen05_ld_16x64b(
+     B32 (&out)[1],
+     uint32_t taddr);
+
+tcgen05.ld.sync.aligned.16x64b.x1.pack::16b.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.ld.sync.aligned.16x64b.x1.pack::16b.b32 out, [taddr]; // PTX ISA 86, SM_100a, SM_101a
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+   __device__ static inline void tcgen05_ld_16x64b_pack_16b(
+     B32 (&out)[1],
+     uint32_t taddr);
+
+tcgen05.ld.sync.aligned.16x64b.x2.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.ld.sync.aligned.16x64b.x2.b32 out, [taddr]; // PTX ISA 86, SM_100a, SM_101a
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+   __device__ static inline void tcgen05_ld_16x64b(
+     B32 (&out)[2],
+     uint32_t taddr);
+
+tcgen05.ld.sync.aligned.16x64b.x2.pack::16b.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.ld.sync.aligned.16x64b.x2.pack::16b.b32 out, [taddr]; // PTX ISA 86, SM_100a, SM_101a
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+   __device__ static inline void tcgen05_ld_16x64b_pack_16b(
+     B32 (&out)[2],
+     uint32_t taddr);
+
+tcgen05.ld.sync.aligned.16x64b.x4.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.ld.sync.aligned.16x64b.x4.b32 out, [taddr]; // PTX ISA 86, SM_100a, SM_101a
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+   __device__ static inline void tcgen05_ld_16x64b(
+     B32 (&out)[4],
+     uint32_t taddr);
+
+tcgen05.ld.sync.aligned.16x64b.x4.pack::16b.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.ld.sync.aligned.16x64b.x4.pack::16b.b32 out, [taddr]; // PTX ISA 86, SM_100a, SM_101a
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+   __device__ static inline void tcgen05_ld_16x64b_pack_16b(
+     B32 (&out)[4],
+     uint32_t taddr);
+
+tcgen05.ld.sync.aligned.16x64b.x8.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.ld.sync.aligned.16x64b.x8.b32 out, [taddr]; // PTX ISA 86, SM_100a, SM_101a
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+   __device__ static inline void tcgen05_ld_16x64b(
+     B32 (&out)[8],
+     uint32_t taddr);
+
+tcgen05.ld.sync.aligned.16x64b.x8.pack::16b.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.ld.sync.aligned.16x64b.x8.pack::16b.b32 out, [taddr]; // PTX ISA 86, SM_100a, SM_101a
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+   __device__ static inline void tcgen05_ld_16x64b_pack_16b(
+     B32 (&out)[8],
+     uint32_t taddr);
+
+tcgen05.ld.sync.aligned.16x64b.x16.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.ld.sync.aligned.16x64b.x16.b32 out, [taddr]; // PTX ISA 86, SM_100a, SM_101a
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+   __device__ static inline void tcgen05_ld_16x64b(
+     B32 (&out)[16],
+     uint32_t taddr);
+
+tcgen05.ld.sync.aligned.16x64b.x16.pack::16b.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.ld.sync.aligned.16x64b.x16.pack::16b.b32 out, [taddr]; // PTX ISA 86, SM_100a, SM_101a
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+   __device__ static inline void tcgen05_ld_16x64b_pack_16b(
+     B32 (&out)[16],
+     uint32_t taddr);
+
+tcgen05.ld.sync.aligned.16x64b.x32.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.ld.sync.aligned.16x64b.x32.b32 out, [taddr]; // PTX ISA 86, SM_100a, SM_101a
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+   __device__ static inline void tcgen05_ld_16x64b(
+     B32 (&out)[32],
+     uint32_t taddr);
+
+tcgen05.ld.sync.aligned.16x64b.x32.pack::16b.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.ld.sync.aligned.16x64b.x32.pack::16b.b32 out, [taddr]; // PTX ISA 86, SM_100a, SM_101a
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+   __device__ static inline void tcgen05_ld_16x64b_pack_16b(
+     B32 (&out)[32],
+     uint32_t taddr);
+
+tcgen05.ld.sync.aligned.16x64b.x64.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.ld.sync.aligned.16x64b.x64.b32 out, [taddr]; // PTX ISA 86, SM_100a, SM_101a
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+   __device__ static inline void tcgen05_ld_16x64b(
+     B32 (&out)[64],
+     uint32_t taddr);
+
+tcgen05.ld.sync.aligned.16x64b.x64.pack::16b.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.ld.sync.aligned.16x64b.x64.pack::16b.b32 out, [taddr]; // PTX ISA 86, SM_100a, SM_101a
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+   __device__ static inline void tcgen05_ld_16x64b_pack_16b(
+     B32 (&out)[64],
+     uint32_t taddr);
+
+tcgen05.ld.sync.aligned.16x64b.x128.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.ld.sync.aligned.16x64b.x128.b32 out, [taddr]; // PTX ISA 86, SM_100a, SM_101a
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+   __device__ static inline void tcgen05_ld_16x64b(
+     B32 (&out)[128],
+     uint32_t taddr);
+
+tcgen05.ld.sync.aligned.16x64b.x128.pack::16b.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.ld.sync.aligned.16x64b.x128.pack::16b.b32 out, [taddr]; // PTX ISA 86, SM_100a, SM_101a
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+   __device__ static inline void tcgen05_ld_16x64b_pack_16b(
+     B32 (&out)[128],
+     uint32_t taddr);
+
+tcgen05.ld.sync.aligned.16x128b.x1.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.ld.sync.aligned.16x128b.x1.b32 out, [taddr]; // PTX ISA 86, SM_100a, SM_101a
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+   __device__ static inline void tcgen05_ld_16x128b(
+     B32 (&out)[2],
+     uint32_t taddr);
+
+tcgen05.ld.sync.aligned.16x128b.x1.pack::16b.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.ld.sync.aligned.16x128b.x1.pack::16b.b32 out, [taddr]; // PTX ISA 86, SM_100a, SM_101a
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+   __device__ static inline void tcgen05_ld_16x128b_pack_16b(
+     B32 (&out)[2],
+     uint32_t taddr);
+
+tcgen05.ld.sync.aligned.16x128b.x2.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.ld.sync.aligned.16x128b.x2.b32 out, [taddr]; // PTX ISA 86, SM_100a, SM_101a
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+   __device__ static inline void tcgen05_ld_16x128b(
+     B32 (&out)[4],
+     uint32_t taddr);
+
+tcgen05.ld.sync.aligned.16x128b.x2.pack::16b.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.ld.sync.aligned.16x128b.x2.pack::16b.b32 out, [taddr]; // PTX ISA 86, SM_100a, SM_101a
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+   __device__ static inline void tcgen05_ld_16x128b_pack_16b(
+     B32 (&out)[4],
+     uint32_t taddr);
+
+tcgen05.ld.sync.aligned.16x128b.x4.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.ld.sync.aligned.16x128b.x4.b32 out, [taddr]; // PTX ISA 86, SM_100a, SM_101a
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+   __device__ static inline void tcgen05_ld_16x128b(
+     B32 (&out)[8],
+     uint32_t taddr);
+
+tcgen05.ld.sync.aligned.16x128b.x4.pack::16b.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.ld.sync.aligned.16x128b.x4.pack::16b.b32 out, [taddr]; // PTX ISA 86, SM_100a, SM_101a
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+   __device__ static inline void tcgen05_ld_16x128b_pack_16b(
+     B32 (&out)[8],
+     uint32_t taddr);
+
+tcgen05.ld.sync.aligned.16x128b.x8.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.ld.sync.aligned.16x128b.x8.b32 out, [taddr]; // PTX ISA 86, SM_100a, SM_101a
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+   __device__ static inline void tcgen05_ld_16x128b(
+     B32 (&out)[16],
+     uint32_t taddr);
+
+tcgen05.ld.sync.aligned.16x128b.x8.pack::16b.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.ld.sync.aligned.16x128b.x8.pack::16b.b32 out, [taddr]; // PTX ISA 86, SM_100a, SM_101a
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+   __device__ static inline void tcgen05_ld_16x128b_pack_16b(
+     B32 (&out)[16],
+     uint32_t taddr);
+
+tcgen05.ld.sync.aligned.16x128b.x16.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.ld.sync.aligned.16x128b.x16.b32 out, [taddr]; // PTX ISA 86, SM_100a, SM_101a
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+   __device__ static inline void tcgen05_ld_16x128b(
+     B32 (&out)[32],
+     uint32_t taddr);
+
+tcgen05.ld.sync.aligned.16x128b.x16.pack::16b.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.ld.sync.aligned.16x128b.x16.pack::16b.b32 out, [taddr]; // PTX ISA 86, SM_100a, SM_101a
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+   __device__ static inline void tcgen05_ld_16x128b_pack_16b(
+     B32 (&out)[32],
+     uint32_t taddr);
+
+tcgen05.ld.sync.aligned.16x128b.x32.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.ld.sync.aligned.16x128b.x32.b32 out, [taddr]; // PTX ISA 86, SM_100a, SM_101a
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+   __device__ static inline void tcgen05_ld_16x128b(
+     B32 (&out)[64],
+     uint32_t taddr);
+
+tcgen05.ld.sync.aligned.16x128b.x32.pack::16b.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.ld.sync.aligned.16x128b.x32.pack::16b.b32 out, [taddr]; // PTX ISA 86, SM_100a, SM_101a
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+   __device__ static inline void tcgen05_ld_16x128b_pack_16b(
+     B32 (&out)[64],
+     uint32_t taddr);
+
+tcgen05.ld.sync.aligned.16x128b.x64.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.ld.sync.aligned.16x128b.x64.b32 out, [taddr]; // PTX ISA 86, SM_100a, SM_101a
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+   __device__ static inline void tcgen05_ld_16x128b(
+     B32 (&out)[128],
+     uint32_t taddr);
+
+tcgen05.ld.sync.aligned.16x128b.x64.pack::16b.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.ld.sync.aligned.16x128b.x64.pack::16b.b32 out, [taddr]; // PTX ISA 86, SM_100a, SM_101a
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+   __device__ static inline void tcgen05_ld_16x128b_pack_16b(
+     B32 (&out)[128],
+     uint32_t taddr);
+
+tcgen05.ld.sync.aligned.16x256b.x1.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.ld.sync.aligned.16x256b.x1.b32 out, [taddr]; // PTX ISA 86, SM_100a, SM_101a
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+   __device__ static inline void tcgen05_ld_16x256b(
+     B32 (&out)[4],
+     uint32_t taddr);
+
+tcgen05.ld.sync.aligned.16x256b.x1.pack::16b.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.ld.sync.aligned.16x256b.x1.pack::16b.b32 out, [taddr]; // PTX ISA 86, SM_100a, SM_101a
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+   __device__ static inline void tcgen05_ld_16x256b_pack_16b(
+     B32 (&out)[4],
+     uint32_t taddr);
+
+tcgen05.ld.sync.aligned.16x256b.x2.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.ld.sync.aligned.16x256b.x2.b32 out, [taddr]; // PTX ISA 86, SM_100a, SM_101a
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+   __device__ static inline void tcgen05_ld_16x256b(
+     B32 (&out)[8],
+     uint32_t taddr);
+
+tcgen05.ld.sync.aligned.16x256b.x2.pack::16b.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.ld.sync.aligned.16x256b.x2.pack::16b.b32 out, [taddr]; // PTX ISA 86, SM_100a, SM_101a
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+   __device__ static inline void tcgen05_ld_16x256b_pack_16b(
+     B32 (&out)[8],
+     uint32_t taddr);
+
+tcgen05.ld.sync.aligned.16x256b.x4.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.ld.sync.aligned.16x256b.x4.b32 out, [taddr]; // PTX ISA 86, SM_100a, SM_101a
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+   __device__ static inline void tcgen05_ld_16x256b(
+     B32 (&out)[16],
+     uint32_t taddr);
+
+tcgen05.ld.sync.aligned.16x256b.x4.pack::16b.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.ld.sync.aligned.16x256b.x4.pack::16b.b32 out, [taddr]; // PTX ISA 86, SM_100a, SM_101a
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+   __device__ static inline void tcgen05_ld_16x256b_pack_16b(
+     B32 (&out)[16],
+     uint32_t taddr);
+
+tcgen05.ld.sync.aligned.16x256b.x8.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.ld.sync.aligned.16x256b.x8.b32 out, [taddr]; // PTX ISA 86, SM_100a, SM_101a
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+   __device__ static inline void tcgen05_ld_16x256b(
+     B32 (&out)[32],
+     uint32_t taddr);
+
+tcgen05.ld.sync.aligned.16x256b.x8.pack::16b.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.ld.sync.aligned.16x256b.x8.pack::16b.b32 out, [taddr]; // PTX ISA 86, SM_100a, SM_101a
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+   __device__ static inline void tcgen05_ld_16x256b_pack_16b(
+     B32 (&out)[32],
+     uint32_t taddr);
+
+tcgen05.ld.sync.aligned.16x256b.x16.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.ld.sync.aligned.16x256b.x16.b32 out, [taddr]; // PTX ISA 86, SM_100a, SM_101a
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+   __device__ static inline void tcgen05_ld_16x256b(
+     B32 (&out)[64],
+     uint32_t taddr);
+
+tcgen05.ld.sync.aligned.16x256b.x16.pack::16b.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.ld.sync.aligned.16x256b.x16.pack::16b.b32 out, [taddr]; // PTX ISA 86, SM_100a, SM_101a
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+   __device__ static inline void tcgen05_ld_16x256b_pack_16b(
+     B32 (&out)[64],
+     uint32_t taddr);
+
+tcgen05.ld.sync.aligned.16x256b.x32.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.ld.sync.aligned.16x256b.x32.b32 out, [taddr]; // PTX ISA 86, SM_100a, SM_101a
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+   __device__ static inline void tcgen05_ld_16x256b(
+     B32 (&out)[128],
+     uint32_t taddr);
+
+tcgen05.ld.sync.aligned.16x256b.x32.pack::16b.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.ld.sync.aligned.16x256b.x32.pack::16b.b32 out, [taddr]; // PTX ISA 86, SM_100a, SM_101a
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+   __device__ static inline void tcgen05_ld_16x256b_pack_16b(
+     B32 (&out)[128],
+     uint32_t taddr);
+
+tcgen05.ld.sync.aligned.32x32b.x1.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.ld.sync.aligned.32x32b.x1.b32 out, [taddr]; // PTX ISA 86, SM_100a, SM_101a
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+   __device__ static inline void tcgen05_ld_32x32b(
+     B32 (&out)[1],
+     uint32_t taddr);
+
+tcgen05.ld.sync.aligned.32x32b.x1.pack::16b.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.ld.sync.aligned.32x32b.x1.pack::16b.b32 out, [taddr]; // PTX ISA 86, SM_100a, SM_101a
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+   __device__ static inline void tcgen05_ld_32x32b_pack_16b(
+     B32 (&out)[1],
+     uint32_t taddr);
+
+tcgen05.ld.sync.aligned.32x32b.x2.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.ld.sync.aligned.32x32b.x2.b32 out, [taddr]; // PTX ISA 86, SM_100a, SM_101a
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+   __device__ static inline void tcgen05_ld_32x32b(
+     B32 (&out)[2],
+     uint32_t taddr);
+
+tcgen05.ld.sync.aligned.32x32b.x2.pack::16b.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.ld.sync.aligned.32x32b.x2.pack::16b.b32 out, [taddr]; // PTX ISA 86, SM_100a, SM_101a
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+   __device__ static inline void tcgen05_ld_32x32b_pack_16b(
+     B32 (&out)[2],
+     uint32_t taddr);
+
+tcgen05.ld.sync.aligned.32x32b.x4.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.ld.sync.aligned.32x32b.x4.b32 out, [taddr]; // PTX ISA 86, SM_100a, SM_101a
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+   __device__ static inline void tcgen05_ld_32x32b(
+     B32 (&out)[4],
+     uint32_t taddr);
+
+tcgen05.ld.sync.aligned.32x32b.x4.pack::16b.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.ld.sync.aligned.32x32b.x4.pack::16b.b32 out, [taddr]; // PTX ISA 86, SM_100a, SM_101a
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+   __device__ static inline void tcgen05_ld_32x32b_pack_16b(
+     B32 (&out)[4],
+     uint32_t taddr);
+
+tcgen05.ld.sync.aligned.32x32b.x8.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.ld.sync.aligned.32x32b.x8.b32 out, [taddr]; // PTX ISA 86, SM_100a, SM_101a
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+   __device__ static inline void tcgen05_ld_32x32b(
+     B32 (&out)[8],
+     uint32_t taddr);
+
+tcgen05.ld.sync.aligned.32x32b.x8.pack::16b.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.ld.sync.aligned.32x32b.x8.pack::16b.b32 out, [taddr]; // PTX ISA 86, SM_100a, SM_101a
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+   __device__ static inline void tcgen05_ld_32x32b_pack_16b(
+     B32 (&out)[8],
+     uint32_t taddr);
+
+tcgen05.ld.sync.aligned.32x32b.x16.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.ld.sync.aligned.32x32b.x16.b32 out, [taddr]; // PTX ISA 86, SM_100a, SM_101a
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+   __device__ static inline void tcgen05_ld_32x32b(
+     B32 (&out)[16],
+     uint32_t taddr);
+
+tcgen05.ld.sync.aligned.32x32b.x16.pack::16b.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.ld.sync.aligned.32x32b.x16.pack::16b.b32 out, [taddr]; // PTX ISA 86, SM_100a, SM_101a
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+   __device__ static inline void tcgen05_ld_32x32b_pack_16b(
+     B32 (&out)[16],
+     uint32_t taddr);
+
+tcgen05.ld.sync.aligned.32x32b.x32.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.ld.sync.aligned.32x32b.x32.b32 out, [taddr]; // PTX ISA 86, SM_100a, SM_101a
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+   __device__ static inline void tcgen05_ld_32x32b(
+     B32 (&out)[32],
+     uint32_t taddr);
+
+tcgen05.ld.sync.aligned.32x32b.x32.pack::16b.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.ld.sync.aligned.32x32b.x32.pack::16b.b32 out, [taddr]; // PTX ISA 86, SM_100a, SM_101a
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+   __device__ static inline void tcgen05_ld_32x32b_pack_16b(
+     B32 (&out)[32],
+     uint32_t taddr);
+
+tcgen05.ld.sync.aligned.32x32b.x64.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.ld.sync.aligned.32x32b.x64.b32 out, [taddr]; // PTX ISA 86, SM_100a, SM_101a
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+   __device__ static inline void tcgen05_ld_32x32b(
+     B32 (&out)[64],
+     uint32_t taddr);
+
+tcgen05.ld.sync.aligned.32x32b.x64.pack::16b.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.ld.sync.aligned.32x32b.x64.pack::16b.b32 out, [taddr]; // PTX ISA 86, SM_100a, SM_101a
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+   __device__ static inline void tcgen05_ld_32x32b_pack_16b(
+     B32 (&out)[64],
+     uint32_t taddr);
+
+tcgen05.ld.sync.aligned.32x32b.x128.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.ld.sync.aligned.32x32b.x128.b32 out, [taddr]; // PTX ISA 86, SM_100a, SM_101a
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+   __device__ static inline void tcgen05_ld_32x32b(
+     B32 (&out)[128],
+     uint32_t taddr);
+
+tcgen05.ld.sync.aligned.32x32b.x128.pack::16b.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.ld.sync.aligned.32x32b.x128.pack::16b.b32 out, [taddr]; // PTX ISA 86, SM_100a, SM_101a
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+   __device__ static inline void tcgen05_ld_32x32b_pack_16b(
+     B32 (&out)[128],
+     uint32_t taddr);
+
+tcgen05.ld.sync.aligned.16x32bx2.x1.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.ld.sync.aligned.16x32bx2.x1.b32 out, [taddr], immHalfSplitoff; // PTX ISA 86, SM_100a, SM_101a
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true, int N32>
+   __device__ static inline void tcgen05_ld_16x32bx2(
+     B32 (&out)[1],
+     uint32_t taddr,
+     cuda::ptx::n32_t<N32> immHalfSplitoff);
+
+tcgen05.ld.sync.aligned.16x32bx2.x1.pack::16b.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.ld.sync.aligned.16x32bx2.x1.pack::16b.b32 out, [taddr], immHalfSplitoff; // PTX ISA 86, SM_100a, SM_101a
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true, int N32>
+   __device__ static inline void tcgen05_ld_16x32bx2_pack_16b(
+     B32 (&out)[1],
+     uint32_t taddr,
+     cuda::ptx::n32_t<N32> immHalfSplitoff);
+
+tcgen05.ld.sync.aligned.16x32bx2.x2.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.ld.sync.aligned.16x32bx2.x2.b32 out, [taddr], immHalfSplitoff; // PTX ISA 86, SM_100a, SM_101a
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true, int N32>
+   __device__ static inline void tcgen05_ld_16x32bx2(
+     B32 (&out)[2],
+     uint32_t taddr,
+     cuda::ptx::n32_t<N32> immHalfSplitoff);
+
+tcgen05.ld.sync.aligned.16x32bx2.x2.pack::16b.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.ld.sync.aligned.16x32bx2.x2.pack::16b.b32 out, [taddr], immHalfSplitoff; // PTX ISA 86, SM_100a, SM_101a
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true, int N32>
+   __device__ static inline void tcgen05_ld_16x32bx2_pack_16b(
+     B32 (&out)[2],
+     uint32_t taddr,
+     cuda::ptx::n32_t<N32> immHalfSplitoff);
+
+tcgen05.ld.sync.aligned.16x32bx2.x4.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.ld.sync.aligned.16x32bx2.x4.b32 out, [taddr], immHalfSplitoff; // PTX ISA 86, SM_100a, SM_101a
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true, int N32>
+   __device__ static inline void tcgen05_ld_16x32bx2(
+     B32 (&out)[4],
+     uint32_t taddr,
+     cuda::ptx::n32_t<N32> immHalfSplitoff);
+
+tcgen05.ld.sync.aligned.16x32bx2.x4.pack::16b.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.ld.sync.aligned.16x32bx2.x4.pack::16b.b32 out, [taddr], immHalfSplitoff; // PTX ISA 86, SM_100a, SM_101a
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true, int N32>
+   __device__ static inline void tcgen05_ld_16x32bx2_pack_16b(
+     B32 (&out)[4],
+     uint32_t taddr,
+     cuda::ptx::n32_t<N32> immHalfSplitoff);
+
+tcgen05.ld.sync.aligned.16x32bx2.x8.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.ld.sync.aligned.16x32bx2.x8.b32 out, [taddr], immHalfSplitoff; // PTX ISA 86, SM_100a, SM_101a
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true, int N32>
+   __device__ static inline void tcgen05_ld_16x32bx2(
+     B32 (&out)[8],
+     uint32_t taddr,
+     cuda::ptx::n32_t<N32> immHalfSplitoff);
+
+tcgen05.ld.sync.aligned.16x32bx2.x8.pack::16b.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.ld.sync.aligned.16x32bx2.x8.pack::16b.b32 out, [taddr], immHalfSplitoff; // PTX ISA 86, SM_100a, SM_101a
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true, int N32>
+   __device__ static inline void tcgen05_ld_16x32bx2_pack_16b(
+     B32 (&out)[8],
+     uint32_t taddr,
+     cuda::ptx::n32_t<N32> immHalfSplitoff);
+
+tcgen05.ld.sync.aligned.16x32bx2.x16.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.ld.sync.aligned.16x32bx2.x16.b32 out, [taddr], immHalfSplitoff; // PTX ISA 86, SM_100a, SM_101a
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true, int N32>
+   __device__ static inline void tcgen05_ld_16x32bx2(
+     B32 (&out)[16],
+     uint32_t taddr,
+     cuda::ptx::n32_t<N32> immHalfSplitoff);
+
+tcgen05.ld.sync.aligned.16x32bx2.x16.pack::16b.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.ld.sync.aligned.16x32bx2.x16.pack::16b.b32 out, [taddr], immHalfSplitoff; // PTX ISA 86, SM_100a, SM_101a
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true, int N32>
+   __device__ static inline void tcgen05_ld_16x32bx2_pack_16b(
+     B32 (&out)[16],
+     uint32_t taddr,
+     cuda::ptx::n32_t<N32> immHalfSplitoff);
+
+tcgen05.ld.sync.aligned.16x32bx2.x32.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.ld.sync.aligned.16x32bx2.x32.b32 out, [taddr], immHalfSplitoff; // PTX ISA 86, SM_100a, SM_101a
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true, int N32>
+   __device__ static inline void tcgen05_ld_16x32bx2(
+     B32 (&out)[32],
+     uint32_t taddr,
+     cuda::ptx::n32_t<N32> immHalfSplitoff);
+
+tcgen05.ld.sync.aligned.16x32bx2.x32.pack::16b.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.ld.sync.aligned.16x32bx2.x32.pack::16b.b32 out, [taddr], immHalfSplitoff; // PTX ISA 86, SM_100a, SM_101a
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true, int N32>
+   __device__ static inline void tcgen05_ld_16x32bx2_pack_16b(
+     B32 (&out)[32],
+     uint32_t taddr,
+     cuda::ptx::n32_t<N32> immHalfSplitoff);
+
+tcgen05.ld.sync.aligned.16x32bx2.x64.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.ld.sync.aligned.16x32bx2.x64.b32 out, [taddr], immHalfSplitoff; // PTX ISA 86, SM_100a, SM_101a
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true, int N32>
+   __device__ static inline void tcgen05_ld_16x32bx2(
+     B32 (&out)[64],
+     uint32_t taddr,
+     cuda::ptx::n32_t<N32> immHalfSplitoff);
+
+tcgen05.ld.sync.aligned.16x32bx2.x64.pack::16b.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.ld.sync.aligned.16x32bx2.x64.pack::16b.b32 out, [taddr], immHalfSplitoff; // PTX ISA 86, SM_100a, SM_101a
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true, int N32>
+   __device__ static inline void tcgen05_ld_16x32bx2_pack_16b(
+     B32 (&out)[64],
+     uint32_t taddr,
+     cuda::ptx::n32_t<N32> immHalfSplitoff);
+
+tcgen05.ld.sync.aligned.16x32bx2.x128.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.ld.sync.aligned.16x32bx2.x128.b32 out, [taddr], immHalfSplitoff; // PTX ISA 86, SM_100a, SM_101a
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true, int N32>
+   __device__ static inline void tcgen05_ld_16x32bx2(
+     B32 (&out)[128],
+     uint32_t taddr,
+     cuda::ptx::n32_t<N32> immHalfSplitoff);
+
+tcgen05.ld.sync.aligned.16x32bx2.x128.pack::16b.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.ld.sync.aligned.16x32bx2.x128.pack::16b.b32 out, [taddr], immHalfSplitoff; // PTX ISA 86, SM_100a, SM_101a
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true, int N32>
+   __device__ static inline void tcgen05_ld_16x32bx2_pack_16b(
+     B32 (&out)[128],
+     uint32_t taddr,
+     cuda::ptx::n32_t<N32> immHalfSplitoff);
diff --git a/docs/libcudacxx/ptx/instructions/generated/tcgen05_mma.rst b/docs/libcudacxx/ptx/instructions/generated/tcgen05_mma.rst
new file mode 100644
index 00000000000..aa5a1675193
--- /dev/null
+++ b/docs/libcudacxx/ptx/instructions/generated/tcgen05_mma.rst
@@ -0,0 +1,2378 @@
+..
+   This file was automatically generated. Do not edit.
+
+tcgen05.mma.cta_group::1.kind::f16
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.cta_group.kind [d_tmem], a_desc, b_desc, idesc, disable_output_lane, enable_input_d, scale_input_d; // PTX ISA 86, SM_100a
+   // .kind      = { .kind::f16, .kind::tf32 }
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <int N32, cuda::ptx::dot_kind Kind, cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void tcgen05_mma(
+     cuda::ptx::kind_t<Kind> kind,
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     const uint32_t (&disable_output_lane)[4],
+     bool enable_input_d,
+     cuda::ptx::n32_t<N32> scale_input_d);
+
+tcgen05.mma.cta_group::2.kind::f16
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.cta_group.kind [d_tmem], a_desc, b_desc, idesc, disable_output_lane, enable_input_d, scale_input_d; // PTX ISA 86, SM_100a
+   // .kind      = { .kind::f16, .kind::tf32 }
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <int N32, cuda::ptx::dot_kind Kind, cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void tcgen05_mma(
+     cuda::ptx::kind_t<Kind> kind,
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     const uint32_t (&disable_output_lane)[4],
+     bool enable_input_d,
+     cuda::ptx::n32_t<N32> scale_input_d);
+
+tcgen05.mma.cta_group::1.kind::tf32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.cta_group.kind [d_tmem], a_desc, b_desc, idesc, disable_output_lane, enable_input_d, scale_input_d; // PTX ISA 86, SM_100a
+   // .kind      = { .kind::f16, .kind::tf32 }
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <int N32, cuda::ptx::dot_kind Kind, cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void tcgen05_mma(
+     cuda::ptx::kind_t<Kind> kind,
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     const uint32_t (&disable_output_lane)[4],
+     bool enable_input_d,
+     cuda::ptx::n32_t<N32> scale_input_d);
+
+tcgen05.mma.cta_group::2.kind::tf32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.cta_group.kind [d_tmem], a_desc, b_desc, idesc, disable_output_lane, enable_input_d, scale_input_d; // PTX ISA 86, SM_100a
+   // .kind      = { .kind::f16, .kind::tf32 }
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <int N32, cuda::ptx::dot_kind Kind, cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void tcgen05_mma(
+     cuda::ptx::kind_t<Kind> kind,
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     const uint32_t (&disable_output_lane)[4],
+     bool enable_input_d,
+     cuda::ptx::n32_t<N32> scale_input_d);
+
+tcgen05.mma.cta_group::1.kind::f16
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.cta_group.kind [d_tmem], a_desc, b_desc, idesc, disable_output_lane, enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_kind Kind, cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void tcgen05_mma(
+     cuda::ptx::kind_t<Kind> kind,
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     const uint32_t (&disable_output_lane)[4],
+     bool enable_input_d);
+
+tcgen05.mma.cta_group::2.kind::f16
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.cta_group.kind [d_tmem], a_desc, b_desc, idesc, disable_output_lane, enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_kind Kind, cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void tcgen05_mma(
+     cuda::ptx::kind_t<Kind> kind,
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     const uint32_t (&disable_output_lane)[4],
+     bool enable_input_d);
+
+tcgen05.mma.cta_group::1.kind::tf32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.cta_group.kind [d_tmem], a_desc, b_desc, idesc, disable_output_lane, enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_kind Kind, cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void tcgen05_mma(
+     cuda::ptx::kind_t<Kind> kind,
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     const uint32_t (&disable_output_lane)[4],
+     bool enable_input_d);
+
+tcgen05.mma.cta_group::2.kind::tf32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.cta_group.kind [d_tmem], a_desc, b_desc, idesc, disable_output_lane, enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_kind Kind, cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void tcgen05_mma(
+     cuda::ptx::kind_t<Kind> kind,
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     const uint32_t (&disable_output_lane)[4],
+     bool enable_input_d);
+
+tcgen05.mma.cta_group::1.kind::f8f6f4
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.cta_group.kind [d_tmem], a_desc, b_desc, idesc, disable_output_lane, enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_kind Kind, cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void tcgen05_mma(
+     cuda::ptx::kind_t<Kind> kind,
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     const uint32_t (&disable_output_lane)[4],
+     bool enable_input_d);
+
+tcgen05.mma.cta_group::2.kind::f8f6f4
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.cta_group.kind [d_tmem], a_desc, b_desc, idesc, disable_output_lane, enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_kind Kind, cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void tcgen05_mma(
+     cuda::ptx::kind_t<Kind> kind,
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     const uint32_t (&disable_output_lane)[4],
+     bool enable_input_d);
+
+tcgen05.mma.cta_group::1.kind::i8
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.cta_group.kind [d_tmem], a_desc, b_desc, idesc, disable_output_lane, enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_kind Kind, cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void tcgen05_mma(
+     cuda::ptx::kind_t<Kind> kind,
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     const uint32_t (&disable_output_lane)[4],
+     bool enable_input_d);
+
+tcgen05.mma.cta_group::2.kind::i8
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.cta_group.kind [d_tmem], a_desc, b_desc, idesc, disable_output_lane, enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_kind Kind, cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void tcgen05_mma(
+     cuda::ptx::kind_t<Kind> kind,
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     const uint32_t (&disable_output_lane)[4],
+     bool enable_input_d);
+
+tcgen05.mma.cta_group::1.kind::f16
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.cta_group.kind [d_tmem], a_desc, b_desc, idesc, enable_input_d, scale_input_d; // PTX ISA 86, SM_100a
+   // .kind      = { .kind::f16, .kind::tf32 }
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <int N32, cuda::ptx::dot_kind Kind, cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void tcgen05_mma(
+     cuda::ptx::kind_t<Kind> kind,
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d,
+     cuda::ptx::n32_t<N32> scale_input_d);
+
+tcgen05.mma.cta_group::2.kind::f16
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.cta_group.kind [d_tmem], a_desc, b_desc, idesc, enable_input_d, scale_input_d; // PTX ISA 86, SM_100a
+   // .kind      = { .kind::f16, .kind::tf32 }
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <int N32, cuda::ptx::dot_kind Kind, cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void tcgen05_mma(
+     cuda::ptx::kind_t<Kind> kind,
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d,
+     cuda::ptx::n32_t<N32> scale_input_d);
+
+tcgen05.mma.cta_group::1.kind::tf32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.cta_group.kind [d_tmem], a_desc, b_desc, idesc, enable_input_d, scale_input_d; // PTX ISA 86, SM_100a
+   // .kind      = { .kind::f16, .kind::tf32 }
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <int N32, cuda::ptx::dot_kind Kind, cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void tcgen05_mma(
+     cuda::ptx::kind_t<Kind> kind,
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d,
+     cuda::ptx::n32_t<N32> scale_input_d);
+
+tcgen05.mma.cta_group::2.kind::tf32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.cta_group.kind [d_tmem], a_desc, b_desc, idesc, enable_input_d, scale_input_d; // PTX ISA 86, SM_100a
+   // .kind      = { .kind::f16, .kind::tf32 }
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <int N32, cuda::ptx::dot_kind Kind, cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void tcgen05_mma(
+     cuda::ptx::kind_t<Kind> kind,
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d,
+     cuda::ptx::n32_t<N32> scale_input_d);
+
+tcgen05.mma.cta_group::1.kind::f16
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.cta_group.kind [d_tmem], a_desc, b_desc, idesc, enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_kind Kind, cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void tcgen05_mma(
+     cuda::ptx::kind_t<Kind> kind,
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d);
+
+tcgen05.mma.cta_group::2.kind::f16
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.cta_group.kind [d_tmem], a_desc, b_desc, idesc, enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_kind Kind, cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void tcgen05_mma(
+     cuda::ptx::kind_t<Kind> kind,
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d);
+
+tcgen05.mma.cta_group::1.kind::tf32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.cta_group.kind [d_tmem], a_desc, b_desc, idesc, enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_kind Kind, cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void tcgen05_mma(
+     cuda::ptx::kind_t<Kind> kind,
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d);
+
+tcgen05.mma.cta_group::2.kind::tf32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.cta_group.kind [d_tmem], a_desc, b_desc, idesc, enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_kind Kind, cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void tcgen05_mma(
+     cuda::ptx::kind_t<Kind> kind,
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d);
+
+tcgen05.mma.cta_group::1.kind::f8f6f4
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.cta_group.kind [d_tmem], a_desc, b_desc, idesc, enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_kind Kind, cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void tcgen05_mma(
+     cuda::ptx::kind_t<Kind> kind,
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d);
+
+tcgen05.mma.cta_group::2.kind::f8f6f4
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.cta_group.kind [d_tmem], a_desc, b_desc, idesc, enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_kind Kind, cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void tcgen05_mma(
+     cuda::ptx::kind_t<Kind> kind,
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d);
+
+tcgen05.mma.cta_group::1.kind::i8
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.cta_group.kind [d_tmem], a_desc, b_desc, idesc, enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_kind Kind, cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void tcgen05_mma(
+     cuda::ptx::kind_t<Kind> kind,
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d);
+
+tcgen05.mma.cta_group::2.kind::i8
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.cta_group.kind [d_tmem], a_desc, b_desc, idesc, enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_kind Kind, cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void tcgen05_mma(
+     cuda::ptx::kind_t<Kind> kind,
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d);
+
+tcgen05.mma.cta_group::1.kind::f16
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.cta_group.kind [d_tmem], [a_tmem], b_desc, idesc, disable_output_lane, enable_input_d, scale_input_d; // PTX ISA 86, SM_100a
+   // .kind      = { .kind::f16, .kind::tf32 }
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <int N32, cuda::ptx::dot_kind Kind, cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void tcgen05_mma_tmem_a(
+     cuda::ptx::kind_t<Kind> kind,
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     uint32_t d_tmem,
+     uint32_t a_tmem,
+     uint64_t b_desc,
+     uint32_t idesc,
+     const uint32_t (&disable_output_lane)[4],
+     bool enable_input_d,
+     cuda::ptx::n32_t<N32> scale_input_d);
+
+tcgen05.mma.cta_group::2.kind::f16
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.cta_group.kind [d_tmem], [a_tmem], b_desc, idesc, disable_output_lane, enable_input_d, scale_input_d; // PTX ISA 86, SM_100a
+   // .kind      = { .kind::f16, .kind::tf32 }
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <int N32, cuda::ptx::dot_kind Kind, cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void tcgen05_mma_tmem_a(
+     cuda::ptx::kind_t<Kind> kind,
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     uint32_t d_tmem,
+     uint32_t a_tmem,
+     uint64_t b_desc,
+     uint32_t idesc,
+     const uint32_t (&disable_output_lane)[4],
+     bool enable_input_d,
+     cuda::ptx::n32_t<N32> scale_input_d);
+
+tcgen05.mma.cta_group::1.kind::tf32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.cta_group.kind [d_tmem], [a_tmem], b_desc, idesc, disable_output_lane, enable_input_d, scale_input_d; // PTX ISA 86, SM_100a
+   // .kind      = { .kind::f16, .kind::tf32 }
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <int N32, cuda::ptx::dot_kind Kind, cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void tcgen05_mma_tmem_a(
+     cuda::ptx::kind_t<Kind> kind,
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     uint32_t d_tmem,
+     uint32_t a_tmem,
+     uint64_t b_desc,
+     uint32_t idesc,
+     const uint32_t (&disable_output_lane)[4],
+     bool enable_input_d,
+     cuda::ptx::n32_t<N32> scale_input_d);
+
+tcgen05.mma.cta_group::2.kind::tf32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.cta_group.kind [d_tmem], [a_tmem], b_desc, idesc, disable_output_lane, enable_input_d, scale_input_d; // PTX ISA 86, SM_100a
+   // .kind      = { .kind::f16, .kind::tf32 }
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <int N32, cuda::ptx::dot_kind Kind, cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void tcgen05_mma_tmem_a(
+     cuda::ptx::kind_t<Kind> kind,
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     uint32_t d_tmem,
+     uint32_t a_tmem,
+     uint64_t b_desc,
+     uint32_t idesc,
+     const uint32_t (&disable_output_lane)[4],
+     bool enable_input_d,
+     cuda::ptx::n32_t<N32> scale_input_d);
+
+tcgen05.mma.cta_group::1.kind::f16
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.cta_group.kind [d_tmem], [a_tmem], b_desc, idesc, disable_output_lane, enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_kind Kind, cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void tcgen05_mma_tmem_a(
+     cuda::ptx::kind_t<Kind> kind,
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     uint32_t d_tmem,
+     uint32_t a_tmem,
+     uint64_t b_desc,
+     uint32_t idesc,
+     const uint32_t (&disable_output_lane)[4],
+     bool enable_input_d);
+
+tcgen05.mma.cta_group::2.kind::f16
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.cta_group.kind [d_tmem], [a_tmem], b_desc, idesc, disable_output_lane, enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_kind Kind, cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void tcgen05_mma_tmem_a(
+     cuda::ptx::kind_t<Kind> kind,
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     uint32_t d_tmem,
+     uint32_t a_tmem,
+     uint64_t b_desc,
+     uint32_t idesc,
+     const uint32_t (&disable_output_lane)[4],
+     bool enable_input_d);
+
+tcgen05.mma.cta_group::1.kind::tf32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.cta_group.kind [d_tmem], [a_tmem], b_desc, idesc, disable_output_lane, enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_kind Kind, cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void tcgen05_mma_tmem_a(
+     cuda::ptx::kind_t<Kind> kind,
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     uint32_t d_tmem,
+     uint32_t a_tmem,
+     uint64_t b_desc,
+     uint32_t idesc,
+     const uint32_t (&disable_output_lane)[4],
+     bool enable_input_d);
+
+tcgen05.mma.cta_group::2.kind::tf32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.cta_group.kind [d_tmem], [a_tmem], b_desc, idesc, disable_output_lane, enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_kind Kind, cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void tcgen05_mma_tmem_a(
+     cuda::ptx::kind_t<Kind> kind,
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     uint32_t d_tmem,
+     uint32_t a_tmem,
+     uint64_t b_desc,
+     uint32_t idesc,
+     const uint32_t (&disable_output_lane)[4],
+     bool enable_input_d);
+
+tcgen05.mma.cta_group::1.kind::f8f6f4
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.cta_group.kind [d_tmem], [a_tmem], b_desc, idesc, disable_output_lane, enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_kind Kind, cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void tcgen05_mma_tmem_a(
+     cuda::ptx::kind_t<Kind> kind,
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     uint32_t d_tmem,
+     uint32_t a_tmem,
+     uint64_t b_desc,
+     uint32_t idesc,
+     const uint32_t (&disable_output_lane)[4],
+     bool enable_input_d);
+
+tcgen05.mma.cta_group::2.kind::f8f6f4
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.cta_group.kind [d_tmem], [a_tmem], b_desc, idesc, disable_output_lane, enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_kind Kind, cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void tcgen05_mma_tmem_a(
+     cuda::ptx::kind_t<Kind> kind,
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     uint32_t d_tmem,
+     uint32_t a_tmem,
+     uint64_t b_desc,
+     uint32_t idesc,
+     const uint32_t (&disable_output_lane)[4],
+     bool enable_input_d);
+
+tcgen05.mma.cta_group::1.kind::i8
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.cta_group.kind [d_tmem], [a_tmem], b_desc, idesc, disable_output_lane, enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_kind Kind, cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void tcgen05_mma_tmem_a(
+     cuda::ptx::kind_t<Kind> kind,
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     uint32_t d_tmem,
+     uint32_t a_tmem,
+     uint64_t b_desc,
+     uint32_t idesc,
+     const uint32_t (&disable_output_lane)[4],
+     bool enable_input_d);
+
+tcgen05.mma.cta_group::2.kind::i8
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.cta_group.kind [d_tmem], [a_tmem], b_desc, idesc, disable_output_lane, enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_kind Kind, cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void tcgen05_mma_tmem_a(
+     cuda::ptx::kind_t<Kind> kind,
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     uint32_t d_tmem,
+     uint32_t a_tmem,
+     uint64_t b_desc,
+     uint32_t idesc,
+     const uint32_t (&disable_output_lane)[4],
+     bool enable_input_d);
+
+tcgen05.mma.cta_group::1.kind::f16
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.cta_group.kind [d_tmem], [a_tmem], b_desc, idesc, enable_input_d, scale_input_d; // PTX ISA 86, SM_100a
+   // .kind      = { .kind::f16, .kind::tf32 }
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <int N32, cuda::ptx::dot_kind Kind, cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void tcgen05_mma_tmem_a(
+     cuda::ptx::kind_t<Kind> kind,
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     uint32_t d_tmem,
+     uint32_t a_tmem,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d,
+     cuda::ptx::n32_t<N32> scale_input_d);
+
+tcgen05.mma.cta_group::2.kind::f16
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.cta_group.kind [d_tmem], [a_tmem], b_desc, idesc, enable_input_d, scale_input_d; // PTX ISA 86, SM_100a
+   // .kind      = { .kind::f16, .kind::tf32 }
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <int N32, cuda::ptx::dot_kind Kind, cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void tcgen05_mma_tmem_a(
+     cuda::ptx::kind_t<Kind> kind,
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     uint32_t d_tmem,
+     uint32_t a_tmem,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d,
+     cuda::ptx::n32_t<N32> scale_input_d);
+
+tcgen05.mma.cta_group::1.kind::tf32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.cta_group.kind [d_tmem], [a_tmem], b_desc, idesc, enable_input_d, scale_input_d; // PTX ISA 86, SM_100a
+   // .kind      = { .kind::f16, .kind::tf32 }
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <int N32, cuda::ptx::dot_kind Kind, cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void tcgen05_mma_tmem_a(
+     cuda::ptx::kind_t<Kind> kind,
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     uint32_t d_tmem,
+     uint32_t a_tmem,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d,
+     cuda::ptx::n32_t<N32> scale_input_d);
+
+tcgen05.mma.cta_group::2.kind::tf32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.cta_group.kind [d_tmem], [a_tmem], b_desc, idesc, enable_input_d, scale_input_d; // PTX ISA 86, SM_100a
+   // .kind      = { .kind::f16, .kind::tf32 }
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <int N32, cuda::ptx::dot_kind Kind, cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void tcgen05_mma_tmem_a(
+     cuda::ptx::kind_t<Kind> kind,
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     uint32_t d_tmem,
+     uint32_t a_tmem,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d,
+     cuda::ptx::n32_t<N32> scale_input_d);
+
+tcgen05.mma.cta_group::1.kind::f16
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.cta_group.kind [d_tmem], [a_tmem], b_desc, idesc, enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_kind Kind, cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void tcgen05_mma_tmem_a(
+     cuda::ptx::kind_t<Kind> kind,
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     uint32_t d_tmem,
+     uint32_t a_tmem,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d);
+
+tcgen05.mma.cta_group::2.kind::f16
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.cta_group.kind [d_tmem], [a_tmem], b_desc, idesc, enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_kind Kind, cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void tcgen05_mma_tmem_a(
+     cuda::ptx::kind_t<Kind> kind,
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     uint32_t d_tmem,
+     uint32_t a_tmem,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d);
+
+tcgen05.mma.cta_group::1.kind::tf32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.cta_group.kind [d_tmem], [a_tmem], b_desc, idesc, enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_kind Kind, cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void tcgen05_mma_tmem_a(
+     cuda::ptx::kind_t<Kind> kind,
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     uint32_t d_tmem,
+     uint32_t a_tmem,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d);
+
+tcgen05.mma.cta_group::2.kind::tf32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.cta_group.kind [d_tmem], [a_tmem], b_desc, idesc, enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_kind Kind, cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void tcgen05_mma_tmem_a(
+     cuda::ptx::kind_t<Kind> kind,
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     uint32_t d_tmem,
+     uint32_t a_tmem,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d);
+
+tcgen05.mma.cta_group::1.kind::f8f6f4
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.cta_group.kind [d_tmem], [a_tmem], b_desc, idesc, enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_kind Kind, cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void tcgen05_mma_tmem_a(
+     cuda::ptx::kind_t<Kind> kind,
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     uint32_t d_tmem,
+     uint32_t a_tmem,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d);
+
+tcgen05.mma.cta_group::2.kind::f8f6f4
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.cta_group.kind [d_tmem], [a_tmem], b_desc, idesc, enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_kind Kind, cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void tcgen05_mma_tmem_a(
+     cuda::ptx::kind_t<Kind> kind,
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     uint32_t d_tmem,
+     uint32_t a_tmem,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d);
+
+tcgen05.mma.cta_group::1.kind::i8
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.cta_group.kind [d_tmem], [a_tmem], b_desc, idesc, enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_kind Kind, cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void tcgen05_mma_tmem_a(
+     cuda::ptx::kind_t<Kind> kind,
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     uint32_t d_tmem,
+     uint32_t a_tmem,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d);
+
+tcgen05.mma.cta_group::2.kind::i8
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.cta_group.kind [d_tmem], [a_tmem], b_desc, idesc, enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_kind Kind, cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void tcgen05_mma_tmem_a(
+     cuda::ptx::kind_t<Kind> kind,
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     uint32_t d_tmem,
+     uint32_t a_tmem,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d);
+
+tcgen05.mma.cta_group::1.kind::mxf8f6f4.block_scale.scale_vec::1X
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.cta_group.kind.block_scale.scale_vec::1X [d_tmem], a_desc, b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .kind      = { .kind::mxf8f6f4 }
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void tcgen05_mma_block_scale_vec_1x(
+     cuda::ptx::kind_mxf8f6f4_t,
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     uint32_t scale_A_tmem,
+     uint32_t scale_B_tmem,
+     bool enable_input_d);
+
+tcgen05.mma.cta_group::2.kind::mxf8f6f4.block_scale.scale_vec::1X
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.cta_group.kind.block_scale.scale_vec::1X [d_tmem], a_desc, b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .kind      = { .kind::mxf8f6f4 }
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void tcgen05_mma_block_scale_vec_1x(
+     cuda::ptx::kind_mxf8f6f4_t,
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     uint32_t scale_A_tmem,
+     uint32_t scale_B_tmem,
+     bool enable_input_d);
+
+tcgen05.mma.cta_group::1.kind::mxf4.block_scale.scale_vec::2X
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.cta_group.kind.block_scale.scale_vec::2X [d_tmem], a_desc, b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .kind      = { .kind::mxf4, .kind::mxf4nvf4 }
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_kind Kind, cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void tcgen05_mma_block_scale_vec_2x(
+     cuda::ptx::kind_t<Kind> kind,
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     uint32_t scale_A_tmem,
+     uint32_t scale_B_tmem,
+     bool enable_input_d);
+
+tcgen05.mma.cta_group::2.kind::mxf4.block_scale.scale_vec::2X
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.cta_group.kind.block_scale.scale_vec::2X [d_tmem], a_desc, b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .kind      = { .kind::mxf4, .kind::mxf4nvf4 }
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_kind Kind, cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void tcgen05_mma_block_scale_vec_2x(
+     cuda::ptx::kind_t<Kind> kind,
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     uint32_t scale_A_tmem,
+     uint32_t scale_B_tmem,
+     bool enable_input_d);
+
+tcgen05.mma.cta_group::1.kind::mxf4nvf4.block_scale.scale_vec::2X
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.cta_group.kind.block_scale.scale_vec::2X [d_tmem], a_desc, b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .kind      = { .kind::mxf4, .kind::mxf4nvf4 }
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_kind Kind, cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void tcgen05_mma_block_scale_vec_2x(
+     cuda::ptx::kind_t<Kind> kind,
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     uint32_t scale_A_tmem,
+     uint32_t scale_B_tmem,
+     bool enable_input_d);
+
+tcgen05.mma.cta_group::2.kind::mxf4nvf4.block_scale.scale_vec::2X
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.cta_group.kind.block_scale.scale_vec::2X [d_tmem], a_desc, b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .kind      = { .kind::mxf4, .kind::mxf4nvf4 }
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_kind Kind, cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void tcgen05_mma_block_scale_vec_2x(
+     cuda::ptx::kind_t<Kind> kind,
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     uint32_t scale_A_tmem,
+     uint32_t scale_B_tmem,
+     bool enable_input_d);
+
+tcgen05.mma.cta_group::1.kind::mxf4nvf4.block_scale.scale_vec::4X
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.cta_group.kind.block_scale.scale_vec::4X [d_tmem], a_desc, b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .kind      = { .kind::mxf4nvf4 }
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void tcgen05_mma_block_scale_vec_4x(
+     cuda::ptx::kind_mxf4nvf4_t,
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     uint32_t scale_A_tmem,
+     uint32_t scale_B_tmem,
+     bool enable_input_d);
+
+tcgen05.mma.cta_group::2.kind::mxf4nvf4.block_scale.scale_vec::4X
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.cta_group.kind.block_scale.scale_vec::4X [d_tmem], a_desc, b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .kind      = { .kind::mxf4nvf4 }
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void tcgen05_mma_block_scale_vec_4x(
+     cuda::ptx::kind_mxf4nvf4_t,
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     uint32_t scale_A_tmem,
+     uint32_t scale_B_tmem,
+     bool enable_input_d);
+
+tcgen05.mma.cta_group::1.kind::mxf8f6f4.block_scale.scale_vec::1X
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.cta_group.kind.block_scale.scale_vec::1X [d_tmem], a_desc, b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .kind      = { .kind::mxf8f6f4 }
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void tcgen05_mma_block_scale_vec_1x_tmem_a(
+     cuda::ptx::kind_mxf8f6f4_t,
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     uint32_t scale_A_tmem,
+     uint32_t scale_B_tmem,
+     bool enable_input_d);
+
+tcgen05.mma.cta_group::2.kind::mxf8f6f4.block_scale.scale_vec::1X
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.cta_group.kind.block_scale.scale_vec::1X [d_tmem], a_desc, b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .kind      = { .kind::mxf8f6f4 }
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void tcgen05_mma_block_scale_vec_1x_tmem_a(
+     cuda::ptx::kind_mxf8f6f4_t,
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     uint32_t scale_A_tmem,
+     uint32_t scale_B_tmem,
+     bool enable_input_d);
+
+tcgen05.mma.cta_group::1.kind::mxf4.block_scale.scale_vec::2X
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.cta_group.kind.block_scale.scale_vec::2X [d_tmem], a_desc, b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .kind      = { .kind::mxf4, .kind::mxf4nvf4 }
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_kind Kind, cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void tcgen05_mma_block_scale_vec_2_tmem_a(
+     cuda::ptx::kind_t<Kind> kind,
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     uint32_t scale_A_tmem,
+     uint32_t scale_B_tmem,
+     bool enable_input_d);
+
+tcgen05.mma.cta_group::2.kind::mxf4.block_scale.scale_vec::2X
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.cta_group.kind.block_scale.scale_vec::2X [d_tmem], a_desc, b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .kind      = { .kind::mxf4, .kind::mxf4nvf4 }
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_kind Kind, cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void tcgen05_mma_block_scale_vec_2_tmem_a(
+     cuda::ptx::kind_t<Kind> kind,
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     uint32_t scale_A_tmem,
+     uint32_t scale_B_tmem,
+     bool enable_input_d);
+
+tcgen05.mma.cta_group::1.kind::mxf4nvf4.block_scale.scale_vec::2X
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.cta_group.kind.block_scale.scale_vec::2X [d_tmem], a_desc, b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .kind      = { .kind::mxf4, .kind::mxf4nvf4 }
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_kind Kind, cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void tcgen05_mma_block_scale_vec_2_tmem_a(
+     cuda::ptx::kind_t<Kind> kind,
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     uint32_t scale_A_tmem,
+     uint32_t scale_B_tmem,
+     bool enable_input_d);
+
+tcgen05.mma.cta_group::2.kind::mxf4nvf4.block_scale.scale_vec::2X
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.cta_group.kind.block_scale.scale_vec::2X [d_tmem], a_desc, b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .kind      = { .kind::mxf4, .kind::mxf4nvf4 }
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_kind Kind, cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void tcgen05_mma_block_scale_vec_2_tmem_a(
+     cuda::ptx::kind_t<Kind> kind,
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     uint32_t scale_A_tmem,
+     uint32_t scale_B_tmem,
+     bool enable_input_d);
+
+tcgen05.mma.cta_group::1.kind::mxf4nvf4.block_scale.scale_vec::4X
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.cta_group.kind.block_scale.scale_vec::4X [d_tmem], a_desc, b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .kind      = { .kind::mxf4nvf4 }
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void tcgen05_mma_block_scale_vec_4x_tmem_a(
+     cuda::ptx::kind_mxf4nvf4_t,
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     uint32_t scale_A_tmem,
+     uint32_t scale_B_tmem,
+     bool enable_input_d);
+
+tcgen05.mma.cta_group::2.kind::mxf4nvf4.block_scale.scale_vec::4X
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.cta_group.kind.block_scale.scale_vec::4X [d_tmem], a_desc, b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .kind      = { .kind::mxf4nvf4 }
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void tcgen05_mma_block_scale_vec_4x_tmem_a(
+     cuda::ptx::kind_mxf4nvf4_t,
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     uint32_t scale_A_tmem,
+     uint32_t scale_B_tmem,
+     bool enable_input_d);
+
+tcgen05.mma.cta_group::1.kind::mxf8f6f4.block_scale.scale_vec::1X.collector::a::fill
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.cta_group.kind.block_scale.scale_vec::1X.collector::a::fill [d_tmem], a_desc, b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .kind      = { .kind::mxf8f6f4 }
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void tcgen05_mma_block_scale_vec_1x_collector_a_fill(
+     cuda::ptx::kind_mxf8f6f4_t,
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     uint32_t scale_A_tmem,
+     uint32_t scale_B_tmem,
+     bool enable_input_d);
+
+tcgen05.mma.cta_group::2.kind::mxf8f6f4.block_scale.scale_vec::1X.collector::a::fill
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.cta_group.kind.block_scale.scale_vec::1X.collector::a::fill [d_tmem], a_desc, b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .kind      = { .kind::mxf8f6f4 }
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void tcgen05_mma_block_scale_vec_1x_collector_a_fill(
+     cuda::ptx::kind_mxf8f6f4_t,
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     uint32_t scale_A_tmem,
+     uint32_t scale_B_tmem,
+     bool enable_input_d);
+
+tcgen05.mma.cta_group::1.kind::mxf4.block_scale.scale_vec::2X.collector::a::fill
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.cta_group.kind.block_scale.scale_vec::2X.collector::a::fill [d_tmem], a_desc, b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .kind      = { .kind::mxf4, .kind::mxf4nvf4 }
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_kind Kind, cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void tcgen05_mma_block_scale_vec_2x_collector_a_fill(
+     cuda::ptx::kind_t<Kind> kind,
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     uint32_t scale_A_tmem,
+     uint32_t scale_B_tmem,
+     bool enable_input_d);
+
+tcgen05.mma.cta_group::2.kind::mxf4.block_scale.scale_vec::2X.collector::a::fill
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.cta_group.kind.block_scale.scale_vec::2X.collector::a::fill [d_tmem], a_desc, b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .kind      = { .kind::mxf4, .kind::mxf4nvf4 }
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_kind Kind, cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void tcgen05_mma_block_scale_vec_2x_collector_a_fill(
+     cuda::ptx::kind_t<Kind> kind,
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     uint32_t scale_A_tmem,
+     uint32_t scale_B_tmem,
+     bool enable_input_d);
+
+tcgen05.mma.cta_group::1.kind::mxf4nvf4.block_scale.scale_vec::2X.collector::a::fill
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.cta_group.kind.block_scale.scale_vec::2X.collector::a::fill [d_tmem], a_desc, b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .kind      = { .kind::mxf4, .kind::mxf4nvf4 }
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_kind Kind, cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void tcgen05_mma_block_scale_vec_2x_collector_a_fill(
+     cuda::ptx::kind_t<Kind> kind,
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     uint32_t scale_A_tmem,
+     uint32_t scale_B_tmem,
+     bool enable_input_d);
+
+tcgen05.mma.cta_group::2.kind::mxf4nvf4.block_scale.scale_vec::2X.collector::a::fill
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.cta_group.kind.block_scale.scale_vec::2X.collector::a::fill [d_tmem], a_desc, b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .kind      = { .kind::mxf4, .kind::mxf4nvf4 }
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_kind Kind, cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void tcgen05_mma_block_scale_vec_2x_collector_a_fill(
+     cuda::ptx::kind_t<Kind> kind,
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     uint32_t scale_A_tmem,
+     uint32_t scale_B_tmem,
+     bool enable_input_d);
+
+tcgen05.mma.cta_group::1.kind::mxf4nvf4.block_scale.scale_vec::4X.collector::a::fill
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.cta_group.kind.block_scale.scale_vec::4X.collector::a::fill [d_tmem], a_desc, b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .kind      = { .kind::mxf4nvf4 }
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void tcgen05_mma_block_scale_vec_4x_collector_a_fill(
+     cuda::ptx::kind_mxf4nvf4_t,
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     uint32_t scale_A_tmem,
+     uint32_t scale_B_tmem,
+     bool enable_input_d);
+
+tcgen05.mma.cta_group::2.kind::mxf4nvf4.block_scale.scale_vec::4X.collector::a::fill
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.cta_group.kind.block_scale.scale_vec::4X.collector::a::fill [d_tmem], a_desc, b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .kind      = { .kind::mxf4nvf4 }
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void tcgen05_mma_block_scale_vec_4x_collector_a_fill(
+     cuda::ptx::kind_mxf4nvf4_t,
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     uint32_t scale_A_tmem,
+     uint32_t scale_B_tmem,
+     bool enable_input_d);
+
+tcgen05.mma.cta_group::1.kind::mxf8f6f4.block_scale.scale_vec::1X.collector::a::fill
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.cta_group.kind.block_scale.scale_vec::1X.collector::a::fill [d_tmem], a_desc, b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .kind      = { .kind::mxf8f6f4 }
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void tcgen05_mma_block_scale_vec_1x_tmem_a_collector_a_fill(
+     cuda::ptx::kind_mxf8f6f4_t,
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     uint32_t scale_A_tmem,
+     uint32_t scale_B_tmem,
+     bool enable_input_d);
+
+tcgen05.mma.cta_group::2.kind::mxf8f6f4.block_scale.scale_vec::1X.collector::a::fill
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.cta_group.kind.block_scale.scale_vec::1X.collector::a::fill [d_tmem], a_desc, b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .kind      = { .kind::mxf8f6f4 }
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void tcgen05_mma_block_scale_vec_1x_tmem_a_collector_a_fill(
+     cuda::ptx::kind_mxf8f6f4_t,
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     uint32_t scale_A_tmem,
+     uint32_t scale_B_tmem,
+     bool enable_input_d);
+
+tcgen05.mma.cta_group::1.kind::mxf4.block_scale.scale_vec::2X.collector::a::fill
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.cta_group.kind.block_scale.scale_vec::2X.collector::a::fill [d_tmem], a_desc, b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .kind      = { .kind::mxf4, .kind::mxf4nvf4 }
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_kind Kind, cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void tcgen05_mma_block_scale_vec_2_tmem_a_collector_a_fill(
+     cuda::ptx::kind_t<Kind> kind,
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     uint32_t scale_A_tmem,
+     uint32_t scale_B_tmem,
+     bool enable_input_d);
+
+tcgen05.mma.cta_group::2.kind::mxf4.block_scale.scale_vec::2X.collector::a::fill
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.cta_group.kind.block_scale.scale_vec::2X.collector::a::fill [d_tmem], a_desc, b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .kind      = { .kind::mxf4, .kind::mxf4nvf4 }
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_kind Kind, cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void tcgen05_mma_block_scale_vec_2_tmem_a_collector_a_fill(
+     cuda::ptx::kind_t<Kind> kind,
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     uint32_t scale_A_tmem,
+     uint32_t scale_B_tmem,
+     bool enable_input_d);
+
+tcgen05.mma.cta_group::1.kind::mxf4nvf4.block_scale.scale_vec::2X.collector::a::fill
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.cta_group.kind.block_scale.scale_vec::2X.collector::a::fill [d_tmem], a_desc, b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .kind      = { .kind::mxf4, .kind::mxf4nvf4 }
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_kind Kind, cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void tcgen05_mma_block_scale_vec_2_tmem_a_collector_a_fill(
+     cuda::ptx::kind_t<Kind> kind,
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     uint32_t scale_A_tmem,
+     uint32_t scale_B_tmem,
+     bool enable_input_d);
+
+tcgen05.mma.cta_group::2.kind::mxf4nvf4.block_scale.scale_vec::2X.collector::a::fill
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.cta_group.kind.block_scale.scale_vec::2X.collector::a::fill [d_tmem], a_desc, b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .kind      = { .kind::mxf4, .kind::mxf4nvf4 }
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_kind Kind, cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void tcgen05_mma_block_scale_vec_2_tmem_a_collector_a_fill(
+     cuda::ptx::kind_t<Kind> kind,
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     uint32_t scale_A_tmem,
+     uint32_t scale_B_tmem,
+     bool enable_input_d);
+
+tcgen05.mma.cta_group::1.kind::mxf4nvf4.block_scale.scale_vec::4X.collector::a::fill
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.cta_group.kind.block_scale.scale_vec::4X.collector::a::fill [d_tmem], a_desc, b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .kind      = { .kind::mxf4nvf4 }
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void tcgen05_mma_block_scale_vec_4x_tmem_a_collector_a_fill(
+     cuda::ptx::kind_mxf4nvf4_t,
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     uint32_t scale_A_tmem,
+     uint32_t scale_B_tmem,
+     bool enable_input_d);
+
+tcgen05.mma.cta_group::2.kind::mxf4nvf4.block_scale.scale_vec::4X.collector::a::fill
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.cta_group.kind.block_scale.scale_vec::4X.collector::a::fill [d_tmem], a_desc, b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .kind      = { .kind::mxf4nvf4 }
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void tcgen05_mma_block_scale_vec_4x_tmem_a_collector_a_fill(
+     cuda::ptx::kind_mxf4nvf4_t,
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     uint32_t scale_A_tmem,
+     uint32_t scale_B_tmem,
+     bool enable_input_d);
+
+tcgen05.mma.cta_group::1.kind::mxf8f6f4.block_scale.scale_vec::1X.collector::a::use
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.cta_group.kind.block_scale.scale_vec::1X.collector::a::use [d_tmem], a_desc, b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .kind      = { .kind::mxf8f6f4 }
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void tcgen05_mma_block_scale_vec_1x_collector_a_use(
+     cuda::ptx::kind_mxf8f6f4_t,
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     uint32_t scale_A_tmem,
+     uint32_t scale_B_tmem,
+     bool enable_input_d);
+
+tcgen05.mma.cta_group::2.kind::mxf8f6f4.block_scale.scale_vec::1X.collector::a::use
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.cta_group.kind.block_scale.scale_vec::1X.collector::a::use [d_tmem], a_desc, b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .kind      = { .kind::mxf8f6f4 }
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void tcgen05_mma_block_scale_vec_1x_collector_a_use(
+     cuda::ptx::kind_mxf8f6f4_t,
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     uint32_t scale_A_tmem,
+     uint32_t scale_B_tmem,
+     bool enable_input_d);
+
+tcgen05.mma.cta_group::1.kind::mxf4.block_scale.scale_vec::2X.collector::a::use
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.cta_group.kind.block_scale.scale_vec::2X.collector::a::use [d_tmem], a_desc, b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .kind      = { .kind::mxf4, .kind::mxf4nvf4 }
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_kind Kind, cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void tcgen05_mma_block_scale_vec_2x_collector_a_use(
+     cuda::ptx::kind_t<Kind> kind,
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     uint32_t scale_A_tmem,
+     uint32_t scale_B_tmem,
+     bool enable_input_d);
+
+tcgen05.mma.cta_group::2.kind::mxf4.block_scale.scale_vec::2X.collector::a::use
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.cta_group.kind.block_scale.scale_vec::2X.collector::a::use [d_tmem], a_desc, b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .kind      = { .kind::mxf4, .kind::mxf4nvf4 }
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_kind Kind, cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void tcgen05_mma_block_scale_vec_2x_collector_a_use(
+     cuda::ptx::kind_t<Kind> kind,
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     uint32_t scale_A_tmem,
+     uint32_t scale_B_tmem,
+     bool enable_input_d);
+
+tcgen05.mma.cta_group::1.kind::mxf4nvf4.block_scale.scale_vec::2X.collector::a::use
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.cta_group.kind.block_scale.scale_vec::2X.collector::a::use [d_tmem], a_desc, b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .kind      = { .kind::mxf4, .kind::mxf4nvf4 }
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_kind Kind, cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void tcgen05_mma_block_scale_vec_2x_collector_a_use(
+     cuda::ptx::kind_t<Kind> kind,
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     uint32_t scale_A_tmem,
+     uint32_t scale_B_tmem,
+     bool enable_input_d);
+
+tcgen05.mma.cta_group::2.kind::mxf4nvf4.block_scale.scale_vec::2X.collector::a::use
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.cta_group.kind.block_scale.scale_vec::2X.collector::a::use [d_tmem], a_desc, b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .kind      = { .kind::mxf4, .kind::mxf4nvf4 }
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_kind Kind, cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void tcgen05_mma_block_scale_vec_2x_collector_a_use(
+     cuda::ptx::kind_t<Kind> kind,
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     uint32_t scale_A_tmem,
+     uint32_t scale_B_tmem,
+     bool enable_input_d);
+
+tcgen05.mma.cta_group::1.kind::mxf4nvf4.block_scale.scale_vec::4X.collector::a::use
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.cta_group.kind.block_scale.scale_vec::4X.collector::a::use [d_tmem], a_desc, b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .kind      = { .kind::mxf4nvf4 }
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void tcgen05_mma_block_scale_vec_4x_collector_a_use(
+     cuda::ptx::kind_mxf4nvf4_t,
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     uint32_t scale_A_tmem,
+     uint32_t scale_B_tmem,
+     bool enable_input_d);
+
+tcgen05.mma.cta_group::2.kind::mxf4nvf4.block_scale.scale_vec::4X.collector::a::use
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.cta_group.kind.block_scale.scale_vec::4X.collector::a::use [d_tmem], a_desc, b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .kind      = { .kind::mxf4nvf4 }
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void tcgen05_mma_block_scale_vec_4x_collector_a_use(
+     cuda::ptx::kind_mxf4nvf4_t,
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     uint32_t scale_A_tmem,
+     uint32_t scale_B_tmem,
+     bool enable_input_d);
+
+tcgen05.mma.cta_group::1.kind::mxf8f6f4.block_scale.scale_vec::1X.collector::a::use
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.cta_group.kind.block_scale.scale_vec::1X.collector::a::use [d_tmem], a_desc, b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .kind      = { .kind::mxf8f6f4 }
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void tcgen05_mma_block_scale_vec_1x_tmem_a_collector_a_use(
+     cuda::ptx::kind_mxf8f6f4_t,
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     uint32_t scale_A_tmem,
+     uint32_t scale_B_tmem,
+     bool enable_input_d);
+
+tcgen05.mma.cta_group::2.kind::mxf8f6f4.block_scale.scale_vec::1X.collector::a::use
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.cta_group.kind.block_scale.scale_vec::1X.collector::a::use [d_tmem], a_desc, b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .kind      = { .kind::mxf8f6f4 }
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void tcgen05_mma_block_scale_vec_1x_tmem_a_collector_a_use(
+     cuda::ptx::kind_mxf8f6f4_t,
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     uint32_t scale_A_tmem,
+     uint32_t scale_B_tmem,
+     bool enable_input_d);
+
+tcgen05.mma.cta_group::1.kind::mxf4.block_scale.scale_vec::2X.collector::a::use
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.cta_group.kind.block_scale.scale_vec::2X.collector::a::use [d_tmem], a_desc, b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .kind      = { .kind::mxf4, .kind::mxf4nvf4 }
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_kind Kind, cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void tcgen05_mma_block_scale_vec_2_tmem_a_collector_a_use(
+     cuda::ptx::kind_t<Kind> kind,
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     uint32_t scale_A_tmem,
+     uint32_t scale_B_tmem,
+     bool enable_input_d);
+
+tcgen05.mma.cta_group::2.kind::mxf4.block_scale.scale_vec::2X.collector::a::use
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.cta_group.kind.block_scale.scale_vec::2X.collector::a::use [d_tmem], a_desc, b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .kind      = { .kind::mxf4, .kind::mxf4nvf4 }
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_kind Kind, cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void tcgen05_mma_block_scale_vec_2_tmem_a_collector_a_use(
+     cuda::ptx::kind_t<Kind> kind,
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     uint32_t scale_A_tmem,
+     uint32_t scale_B_tmem,
+     bool enable_input_d);
+
+tcgen05.mma.cta_group::1.kind::mxf4nvf4.block_scale.scale_vec::2X.collector::a::use
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.cta_group.kind.block_scale.scale_vec::2X.collector::a::use [d_tmem], a_desc, b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .kind      = { .kind::mxf4, .kind::mxf4nvf4 }
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_kind Kind, cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void tcgen05_mma_block_scale_vec_2_tmem_a_collector_a_use(
+     cuda::ptx::kind_t<Kind> kind,
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     uint32_t scale_A_tmem,
+     uint32_t scale_B_tmem,
+     bool enable_input_d);
+
+tcgen05.mma.cta_group::2.kind::mxf4nvf4.block_scale.scale_vec::2X.collector::a::use
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.cta_group.kind.block_scale.scale_vec::2X.collector::a::use [d_tmem], a_desc, b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .kind      = { .kind::mxf4, .kind::mxf4nvf4 }
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_kind Kind, cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void tcgen05_mma_block_scale_vec_2_tmem_a_collector_a_use(
+     cuda::ptx::kind_t<Kind> kind,
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     uint32_t scale_A_tmem,
+     uint32_t scale_B_tmem,
+     bool enable_input_d);
+
+tcgen05.mma.cta_group::1.kind::mxf4nvf4.block_scale.scale_vec::4X.collector::a::use
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.cta_group.kind.block_scale.scale_vec::4X.collector::a::use [d_tmem], a_desc, b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .kind      = { .kind::mxf4nvf4 }
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void tcgen05_mma_block_scale_vec_4x_tmem_a_collector_a_use(
+     cuda::ptx::kind_mxf4nvf4_t,
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     uint32_t scale_A_tmem,
+     uint32_t scale_B_tmem,
+     bool enable_input_d);
+
+tcgen05.mma.cta_group::2.kind::mxf4nvf4.block_scale.scale_vec::4X.collector::a::use
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.cta_group.kind.block_scale.scale_vec::4X.collector::a::use [d_tmem], a_desc, b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .kind      = { .kind::mxf4nvf4 }
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void tcgen05_mma_block_scale_vec_4x_tmem_a_collector_a_use(
+     cuda::ptx::kind_mxf4nvf4_t,
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     uint32_t scale_A_tmem,
+     uint32_t scale_B_tmem,
+     bool enable_input_d);
+
+tcgen05.mma.cta_group::1.kind::mxf8f6f4.block_scale.scale_vec::1X.collector::a::lastuse
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.cta_group.kind.block_scale.scale_vec::1X.collector::a::lastuse [d_tmem], a_desc, b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .kind      = { .kind::mxf8f6f4 }
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void tcgen05_mma_block_scale_vec_1x_collector_a_lastuse(
+     cuda::ptx::kind_mxf8f6f4_t,
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     uint32_t scale_A_tmem,
+     uint32_t scale_B_tmem,
+     bool enable_input_d);
+
+tcgen05.mma.cta_group::2.kind::mxf8f6f4.block_scale.scale_vec::1X.collector::a::lastuse
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.cta_group.kind.block_scale.scale_vec::1X.collector::a::lastuse [d_tmem], a_desc, b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .kind      = { .kind::mxf8f6f4 }
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void tcgen05_mma_block_scale_vec_1x_collector_a_lastuse(
+     cuda::ptx::kind_mxf8f6f4_t,
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     uint32_t scale_A_tmem,
+     uint32_t scale_B_tmem,
+     bool enable_input_d);
+
+tcgen05.mma.cta_group::1.kind::mxf4.block_scale.scale_vec::2X.collector::a::lastuse
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.cta_group.kind.block_scale.scale_vec::2X.collector::a::lastuse [d_tmem], a_desc, b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .kind      = { .kind::mxf4, .kind::mxf4nvf4 }
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_kind Kind, cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void tcgen05_mma_block_scale_vec_2x_collector_a_lastuse(
+     cuda::ptx::kind_t<Kind> kind,
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     uint32_t scale_A_tmem,
+     uint32_t scale_B_tmem,
+     bool enable_input_d);
+
+tcgen05.mma.cta_group::2.kind::mxf4.block_scale.scale_vec::2X.collector::a::lastuse
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.cta_group.kind.block_scale.scale_vec::2X.collector::a::lastuse [d_tmem], a_desc, b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .kind      = { .kind::mxf4, .kind::mxf4nvf4 }
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_kind Kind, cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void tcgen05_mma_block_scale_vec_2x_collector_a_lastuse(
+     cuda::ptx::kind_t<Kind> kind,
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     uint32_t scale_A_tmem,
+     uint32_t scale_B_tmem,
+     bool enable_input_d);
+
+tcgen05.mma.cta_group::1.kind::mxf4nvf4.block_scale.scale_vec::2X.collector::a::lastuse
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.cta_group.kind.block_scale.scale_vec::2X.collector::a::lastuse [d_tmem], a_desc, b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .kind      = { .kind::mxf4, .kind::mxf4nvf4 }
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_kind Kind, cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void tcgen05_mma_block_scale_vec_2x_collector_a_lastuse(
+     cuda::ptx::kind_t<Kind> kind,
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     uint32_t scale_A_tmem,
+     uint32_t scale_B_tmem,
+     bool enable_input_d);
+
+tcgen05.mma.cta_group::2.kind::mxf4nvf4.block_scale.scale_vec::2X.collector::a::lastuse
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.cta_group.kind.block_scale.scale_vec::2X.collector::a::lastuse [d_tmem], a_desc, b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .kind      = { .kind::mxf4, .kind::mxf4nvf4 }
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_kind Kind, cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void tcgen05_mma_block_scale_vec_2x_collector_a_lastuse(
+     cuda::ptx::kind_t<Kind> kind,
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     uint32_t scale_A_tmem,
+     uint32_t scale_B_tmem,
+     bool enable_input_d);
+
+tcgen05.mma.cta_group::1.kind::mxf4nvf4.block_scale.scale_vec::4X.collector::a::lastuse
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.cta_group.kind.block_scale.scale_vec::4X.collector::a::lastuse [d_tmem], a_desc, b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .kind      = { .kind::mxf4nvf4 }
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void tcgen05_mma_block_scale_vec_4x_collector_a_lastuse(
+     cuda::ptx::kind_mxf4nvf4_t,
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     uint32_t scale_A_tmem,
+     uint32_t scale_B_tmem,
+     bool enable_input_d);
+
+tcgen05.mma.cta_group::2.kind::mxf4nvf4.block_scale.scale_vec::4X.collector::a::lastuse
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.cta_group.kind.block_scale.scale_vec::4X.collector::a::lastuse [d_tmem], a_desc, b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .kind      = { .kind::mxf4nvf4 }
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void tcgen05_mma_block_scale_vec_4x_collector_a_lastuse(
+     cuda::ptx::kind_mxf4nvf4_t,
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     uint32_t scale_A_tmem,
+     uint32_t scale_B_tmem,
+     bool enable_input_d);
+
+tcgen05.mma.cta_group::1.kind::mxf8f6f4.block_scale.scale_vec::1X.collector::a::lastuse
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.cta_group.kind.block_scale.scale_vec::1X.collector::a::lastuse [d_tmem], a_desc, b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .kind      = { .kind::mxf8f6f4 }
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void tcgen05_mma_block_scale_vec_1x_tmem_a_collector_a_lastuse(
+     cuda::ptx::kind_mxf8f6f4_t,
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     uint32_t scale_A_tmem,
+     uint32_t scale_B_tmem,
+     bool enable_input_d);
+
+tcgen05.mma.cta_group::2.kind::mxf8f6f4.block_scale.scale_vec::1X.collector::a::lastuse
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.cta_group.kind.block_scale.scale_vec::1X.collector::a::lastuse [d_tmem], a_desc, b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .kind      = { .kind::mxf8f6f4 }
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void tcgen05_mma_block_scale_vec_1x_tmem_a_collector_a_lastuse(
+     cuda::ptx::kind_mxf8f6f4_t,
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     uint32_t scale_A_tmem,
+     uint32_t scale_B_tmem,
+     bool enable_input_d);
+
+tcgen05.mma.cta_group::1.kind::mxf4.block_scale.scale_vec::2X.collector::a::lastuse
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.cta_group.kind.block_scale.scale_vec::2X.collector::a::lastuse [d_tmem], a_desc, b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .kind      = { .kind::mxf4, .kind::mxf4nvf4 }
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_kind Kind, cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void tcgen05_mma_block_scale_vec_2_tmem_a_collector_a_lastuse(
+     cuda::ptx::kind_t<Kind> kind,
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     uint32_t scale_A_tmem,
+     uint32_t scale_B_tmem,
+     bool enable_input_d);
+
+tcgen05.mma.cta_group::2.kind::mxf4.block_scale.scale_vec::2X.collector::a::lastuse
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.cta_group.kind.block_scale.scale_vec::2X.collector::a::lastuse [d_tmem], a_desc, b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .kind      = { .kind::mxf4, .kind::mxf4nvf4 }
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_kind Kind, cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void tcgen05_mma_block_scale_vec_2_tmem_a_collector_a_lastuse(
+     cuda::ptx::kind_t<Kind> kind,
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     uint32_t scale_A_tmem,
+     uint32_t scale_B_tmem,
+     bool enable_input_d);
+
+tcgen05.mma.cta_group::1.kind::mxf4nvf4.block_scale.scale_vec::2X.collector::a::lastuse
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.cta_group.kind.block_scale.scale_vec::2X.collector::a::lastuse [d_tmem], a_desc, b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .kind      = { .kind::mxf4, .kind::mxf4nvf4 }
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_kind Kind, cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void tcgen05_mma_block_scale_vec_2_tmem_a_collector_a_lastuse(
+     cuda::ptx::kind_t<Kind> kind,
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     uint32_t scale_A_tmem,
+     uint32_t scale_B_tmem,
+     bool enable_input_d);
+
+tcgen05.mma.cta_group::2.kind::mxf4nvf4.block_scale.scale_vec::2X.collector::a::lastuse
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.cta_group.kind.block_scale.scale_vec::2X.collector::a::lastuse [d_tmem], a_desc, b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .kind      = { .kind::mxf4, .kind::mxf4nvf4 }
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_kind Kind, cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void tcgen05_mma_block_scale_vec_2_tmem_a_collector_a_lastuse(
+     cuda::ptx::kind_t<Kind> kind,
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     uint32_t scale_A_tmem,
+     uint32_t scale_B_tmem,
+     bool enable_input_d);
+
+tcgen05.mma.cta_group::1.kind::mxf4nvf4.block_scale.scale_vec::4X.collector::a::lastuse
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.cta_group.kind.block_scale.scale_vec::4X.collector::a::lastuse [d_tmem], a_desc, b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .kind      = { .kind::mxf4nvf4 }
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void tcgen05_mma_block_scale_vec_4x_tmem_a_collector_a_lastuse(
+     cuda::ptx::kind_mxf4nvf4_t,
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     uint32_t scale_A_tmem,
+     uint32_t scale_B_tmem,
+     bool enable_input_d);
+
+tcgen05.mma.cta_group::2.kind::mxf4nvf4.block_scale.scale_vec::4X.collector::a::lastuse
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.cta_group.kind.block_scale.scale_vec::4X.collector::a::lastuse [d_tmem], a_desc, b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .kind      = { .kind::mxf4nvf4 }
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void tcgen05_mma_block_scale_vec_4x_tmem_a_collector_a_lastuse(
+     cuda::ptx::kind_mxf4nvf4_t,
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     uint32_t scale_A_tmem,
+     uint32_t scale_B_tmem,
+     bool enable_input_d);
+
+tcgen05.mma.cta_group::1.kind::mxf8f6f4.block_scale.scale_vec::1X.collector::a::discard
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.cta_group.kind.block_scale.scale_vec::1X.collector::a::discard [d_tmem], a_desc, b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .kind      = { .kind::mxf8f6f4 }
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void tcgen05_mma_block_scale_vec_1x_collector_a_discard(
+     cuda::ptx::kind_mxf8f6f4_t,
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     uint32_t scale_A_tmem,
+     uint32_t scale_B_tmem,
+     bool enable_input_d);
+
+tcgen05.mma.cta_group::2.kind::mxf8f6f4.block_scale.scale_vec::1X.collector::a::discard
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.cta_group.kind.block_scale.scale_vec::1X.collector::a::discard [d_tmem], a_desc, b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .kind      = { .kind::mxf8f6f4 }
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void tcgen05_mma_block_scale_vec_1x_collector_a_discard(
+     cuda::ptx::kind_mxf8f6f4_t,
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     uint32_t scale_A_tmem,
+     uint32_t scale_B_tmem,
+     bool enable_input_d);
+
+tcgen05.mma.cta_group::1.kind::mxf4.block_scale.scale_vec::2X.collector::a::discard
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.cta_group.kind.block_scale.scale_vec::2X.collector::a::discard [d_tmem], a_desc, b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .kind      = { .kind::mxf4, .kind::mxf4nvf4 }
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_kind Kind, cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void tcgen05_mma_block_scale_vec_2x_collector_a_discard(
+     cuda::ptx::kind_t<Kind> kind,
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     uint32_t scale_A_tmem,
+     uint32_t scale_B_tmem,
+     bool enable_input_d);
+
+tcgen05.mma.cta_group::2.kind::mxf4.block_scale.scale_vec::2X.collector::a::discard
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.cta_group.kind.block_scale.scale_vec::2X.collector::a::discard [d_tmem], a_desc, b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .kind      = { .kind::mxf4, .kind::mxf4nvf4 }
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_kind Kind, cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void tcgen05_mma_block_scale_vec_2x_collector_a_discard(
+     cuda::ptx::kind_t<Kind> kind,
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     uint32_t scale_A_tmem,
+     uint32_t scale_B_tmem,
+     bool enable_input_d);
+
+tcgen05.mma.cta_group::1.kind::mxf4nvf4.block_scale.scale_vec::2X.collector::a::discard
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.cta_group.kind.block_scale.scale_vec::2X.collector::a::discard [d_tmem], a_desc, b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .kind      = { .kind::mxf4, .kind::mxf4nvf4 }
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_kind Kind, cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void tcgen05_mma_block_scale_vec_2x_collector_a_discard(
+     cuda::ptx::kind_t<Kind> kind,
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     uint32_t scale_A_tmem,
+     uint32_t scale_B_tmem,
+     bool enable_input_d);
+
+tcgen05.mma.cta_group::2.kind::mxf4nvf4.block_scale.scale_vec::2X.collector::a::discard
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.cta_group.kind.block_scale.scale_vec::2X.collector::a::discard [d_tmem], a_desc, b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .kind      = { .kind::mxf4, .kind::mxf4nvf4 }
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_kind Kind, cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void tcgen05_mma_block_scale_vec_2x_collector_a_discard(
+     cuda::ptx::kind_t<Kind> kind,
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     uint32_t scale_A_tmem,
+     uint32_t scale_B_tmem,
+     bool enable_input_d);
+
+tcgen05.mma.cta_group::1.kind::mxf4nvf4.block_scale.scale_vec::4X.collector::a::discard
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.cta_group.kind.block_scale.scale_vec::4X.collector::a::discard [d_tmem], a_desc, b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .kind      = { .kind::mxf4nvf4 }
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void tcgen05_mma_block_scale_vec_4x_collector_a_discard(
+     cuda::ptx::kind_mxf4nvf4_t,
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     uint32_t scale_A_tmem,
+     uint32_t scale_B_tmem,
+     bool enable_input_d);
+
+tcgen05.mma.cta_group::2.kind::mxf4nvf4.block_scale.scale_vec::4X.collector::a::discard
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.cta_group.kind.block_scale.scale_vec::4X.collector::a::discard [d_tmem], a_desc, b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .kind      = { .kind::mxf4nvf4 }
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void tcgen05_mma_block_scale_vec_4x_collector_a_discard(
+     cuda::ptx::kind_mxf4nvf4_t,
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     uint32_t scale_A_tmem,
+     uint32_t scale_B_tmem,
+     bool enable_input_d);
+
+tcgen05.mma.cta_group::1.kind::mxf8f6f4.block_scale.scale_vec::1X.collector::a::discard
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.cta_group.kind.block_scale.scale_vec::1X.collector::a::discard [d_tmem], a_desc, b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .kind      = { .kind::mxf8f6f4 }
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void tcgen05_mma_block_scale_vec_1x_tmem_a_collector_a_discard(
+     cuda::ptx::kind_mxf8f6f4_t,
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     uint32_t scale_A_tmem,
+     uint32_t scale_B_tmem,
+     bool enable_input_d);
+
+tcgen05.mma.cta_group::2.kind::mxf8f6f4.block_scale.scale_vec::1X.collector::a::discard
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.cta_group.kind.block_scale.scale_vec::1X.collector::a::discard [d_tmem], a_desc, b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .kind      = { .kind::mxf8f6f4 }
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void tcgen05_mma_block_scale_vec_1x_tmem_a_collector_a_discard(
+     cuda::ptx::kind_mxf8f6f4_t,
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     uint32_t scale_A_tmem,
+     uint32_t scale_B_tmem,
+     bool enable_input_d);
+
+tcgen05.mma.cta_group::1.kind::mxf4.block_scale.scale_vec::2X.collector::a::discard
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.cta_group.kind.block_scale.scale_vec::2X.collector::a::discard [d_tmem], a_desc, b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .kind      = { .kind::mxf4, .kind::mxf4nvf4 }
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_kind Kind, cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void tcgen05_mma_block_scale_vec_2_tmem_a_collector_a_discard(
+     cuda::ptx::kind_t<Kind> kind,
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     uint32_t scale_A_tmem,
+     uint32_t scale_B_tmem,
+     bool enable_input_d);
+
+tcgen05.mma.cta_group::2.kind::mxf4.block_scale.scale_vec::2X.collector::a::discard
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.cta_group.kind.block_scale.scale_vec::2X.collector::a::discard [d_tmem], a_desc, b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .kind      = { .kind::mxf4, .kind::mxf4nvf4 }
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_kind Kind, cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void tcgen05_mma_block_scale_vec_2_tmem_a_collector_a_discard(
+     cuda::ptx::kind_t<Kind> kind,
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     uint32_t scale_A_tmem,
+     uint32_t scale_B_tmem,
+     bool enable_input_d);
+
+tcgen05.mma.cta_group::1.kind::mxf4nvf4.block_scale.scale_vec::2X.collector::a::discard
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.cta_group.kind.block_scale.scale_vec::2X.collector::a::discard [d_tmem], a_desc, b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .kind      = { .kind::mxf4, .kind::mxf4nvf4 }
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_kind Kind, cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void tcgen05_mma_block_scale_vec_2_tmem_a_collector_a_discard(
+     cuda::ptx::kind_t<Kind> kind,
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     uint32_t scale_A_tmem,
+     uint32_t scale_B_tmem,
+     bool enable_input_d);
+
+tcgen05.mma.cta_group::2.kind::mxf4nvf4.block_scale.scale_vec::2X.collector::a::discard
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.cta_group.kind.block_scale.scale_vec::2X.collector::a::discard [d_tmem], a_desc, b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .kind      = { .kind::mxf4, .kind::mxf4nvf4 }
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_kind Kind, cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void tcgen05_mma_block_scale_vec_2_tmem_a_collector_a_discard(
+     cuda::ptx::kind_t<Kind> kind,
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     uint32_t scale_A_tmem,
+     uint32_t scale_B_tmem,
+     bool enable_input_d);
+
+tcgen05.mma.cta_group::1.kind::mxf4nvf4.block_scale.scale_vec::4X.collector::a::discard
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.cta_group.kind.block_scale.scale_vec::4X.collector::a::discard [d_tmem], a_desc, b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .kind      = { .kind::mxf4nvf4 }
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void tcgen05_mma_block_scale_vec_4x_tmem_a_collector_a_discard(
+     cuda::ptx::kind_mxf4nvf4_t,
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     uint32_t scale_A_tmem,
+     uint32_t scale_B_tmem,
+     bool enable_input_d);
+
+tcgen05.mma.cta_group::2.kind::mxf4nvf4.block_scale.scale_vec::4X.collector::a::discard
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.cta_group.kind.block_scale.scale_vec::4X.collector::a::discard [d_tmem], a_desc, b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .kind      = { .kind::mxf4nvf4 }
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void tcgen05_mma_block_scale_vec_4x_tmem_a_collector_a_discard(
+     cuda::ptx::kind_mxf4nvf4_t,
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     uint32_t scale_A_tmem,
+     uint32_t scale_B_tmem,
+     bool enable_input_d);
diff --git a/docs/libcudacxx/ptx/instructions/generated/tcgen05_mma_ws.rst b/docs/libcudacxx/ptx/instructions/generated/tcgen05_mma_ws.rst
new file mode 100644
index 00000000000..cb900a0ec40
--- /dev/null
+++ b/docs/libcudacxx/ptx/instructions/generated/tcgen05_mma_ws.rst
@@ -0,0 +1,4482 @@
+..
+   This file was automatically generated. Do not edit.
+
+tcgen05.mma.ws.cta_group::1.kind::f16.collector::b0::fill
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b0::fill [d_tmem], a_desc, b_desc, idesc, enable_input_d, zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_collector_b0_fill(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d,
+     uint64_t zero_column_mask_desc);
+
+tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b0::fill
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b0::fill [d_tmem], a_desc, b_desc, idesc, enable_input_d, zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_collector_b0_fill(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d,
+     uint64_t zero_column_mask_desc);
+
+tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b0::fill
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b0::fill [d_tmem], a_desc, b_desc, idesc, enable_input_d, zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_collector_b0_fill(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d,
+     uint64_t zero_column_mask_desc);
+
+tcgen05.mma.ws.cta_group::1.kind::i8.collector::b0::fill
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b0::fill [d_tmem], a_desc, b_desc, idesc, enable_input_d, zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_collector_b0_fill(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d,
+     uint64_t zero_column_mask_desc);
+
+tcgen05.mma.ws.cta_group::1.kind::f16.collector::b0::fill
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b0::fill [d_tmem], a_desc, b_desc, idesc, enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_collector_b0_fill(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d);
+
+tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b0::fill
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b0::fill [d_tmem], a_desc, b_desc, idesc, enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_collector_b0_fill(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d);
+
+tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b0::fill
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b0::fill [d_tmem], a_desc, b_desc, idesc, enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_collector_b0_fill(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d);
+
+tcgen05.mma.ws.cta_group::1.kind::i8.collector::b0::fill
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b0::fill [d_tmem], a_desc, b_desc, idesc, enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_collector_b0_fill(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d);
+
+tcgen05.mma.ws.cta_group::1.kind::f16.collector::b0::fill
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b0::fill [d_tmem], [a_tmem], b_desc, idesc, enable_input_d, zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_tmem_a_collector_b0_fill(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint32_t a_tmem,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d,
+     uint64_t zero_column_mask_desc);
+
+tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b0::fill
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b0::fill [d_tmem], [a_tmem], b_desc, idesc, enable_input_d, zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_tmem_a_collector_b0_fill(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint32_t a_tmem,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d,
+     uint64_t zero_column_mask_desc);
+
+tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b0::fill
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b0::fill [d_tmem], [a_tmem], b_desc, idesc, enable_input_d, zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_tmem_a_collector_b0_fill(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint32_t a_tmem,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d,
+     uint64_t zero_column_mask_desc);
+
+tcgen05.mma.ws.cta_group::1.kind::i8.collector::b0::fill
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b0::fill [d_tmem], [a_tmem], b_desc, idesc, enable_input_d, zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_tmem_a_collector_b0_fill(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint32_t a_tmem,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d,
+     uint64_t zero_column_mask_desc);
+
+tcgen05.mma.ws.cta_group::1.kind::f16.collector::b0::fill
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b0::fill [d_tmem], [a_tmem], b_desc, idesc, enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_tmem_a_collector_b0_fill(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint32_t a_tmem,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d);
+
+tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b0::fill
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b0::fill [d_tmem], [a_tmem], b_desc, idesc, enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_tmem_a_collector_b0_fill(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint32_t a_tmem,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d);
+
+tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b0::fill
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b0::fill [d_tmem], [a_tmem], b_desc, idesc, enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_tmem_a_collector_b0_fill(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint32_t a_tmem,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d);
+
+tcgen05.mma.ws.cta_group::1.kind::i8.collector::b0::fill
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b0::fill [d_tmem], [a_tmem], b_desc, idesc, enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_tmem_a_collector_b0_fill(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint32_t a_tmem,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d);
+
+tcgen05.mma.ws.cta_group::1.kind::f16.collector::b0::use
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b0::use [d_tmem], a_desc, b_desc, idesc, enable_input_d, zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_collector_b0_use(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d,
+     uint64_t zero_column_mask_desc);
+
+tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b0::use
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b0::use [d_tmem], a_desc, b_desc, idesc, enable_input_d, zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_collector_b0_use(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d,
+     uint64_t zero_column_mask_desc);
+
+tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b0::use
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b0::use [d_tmem], a_desc, b_desc, idesc, enable_input_d, zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_collector_b0_use(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d,
+     uint64_t zero_column_mask_desc);
+
+tcgen05.mma.ws.cta_group::1.kind::i8.collector::b0::use
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b0::use [d_tmem], a_desc, b_desc, idesc, enable_input_d, zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_collector_b0_use(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d,
+     uint64_t zero_column_mask_desc);
+
+tcgen05.mma.ws.cta_group::1.kind::f16.collector::b0::use
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b0::use [d_tmem], a_desc, b_desc, idesc, enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_collector_b0_use(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d);
+
+tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b0::use
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b0::use [d_tmem], a_desc, b_desc, idesc, enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_collector_b0_use(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d);
+
+tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b0::use
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b0::use [d_tmem], a_desc, b_desc, idesc, enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_collector_b0_use(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d);
+
+tcgen05.mma.ws.cta_group::1.kind::i8.collector::b0::use
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b0::use [d_tmem], a_desc, b_desc, idesc, enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_collector_b0_use(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d);
+
+tcgen05.mma.ws.cta_group::1.kind::f16.collector::b0::use
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b0::use [d_tmem], [a_tmem], b_desc, idesc, enable_input_d, zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_tmem_a_collector_b0_use(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint32_t a_tmem,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d,
+     uint64_t zero_column_mask_desc);
+
+tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b0::use
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b0::use [d_tmem], [a_tmem], b_desc, idesc, enable_input_d, zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_tmem_a_collector_b0_use(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint32_t a_tmem,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d,
+     uint64_t zero_column_mask_desc);
+
+tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b0::use
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b0::use [d_tmem], [a_tmem], b_desc, idesc, enable_input_d, zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_tmem_a_collector_b0_use(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint32_t a_tmem,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d,
+     uint64_t zero_column_mask_desc);
+
+tcgen05.mma.ws.cta_group::1.kind::i8.collector::b0::use
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b0::use [d_tmem], [a_tmem], b_desc, idesc, enable_input_d, zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_tmem_a_collector_b0_use(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint32_t a_tmem,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d,
+     uint64_t zero_column_mask_desc);
+
+tcgen05.mma.ws.cta_group::1.kind::f16.collector::b0::use
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b0::use [d_tmem], [a_tmem], b_desc, idesc, enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_tmem_a_collector_b0_use(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint32_t a_tmem,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d);
+
+tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b0::use
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b0::use [d_tmem], [a_tmem], b_desc, idesc, enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_tmem_a_collector_b0_use(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint32_t a_tmem,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d);
+
+tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b0::use
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b0::use [d_tmem], [a_tmem], b_desc, idesc, enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_tmem_a_collector_b0_use(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint32_t a_tmem,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d);
+
+tcgen05.mma.ws.cta_group::1.kind::i8.collector::b0::use
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b0::use [d_tmem], [a_tmem], b_desc, idesc, enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_tmem_a_collector_b0_use(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint32_t a_tmem,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d);
+
+tcgen05.mma.ws.cta_group::1.kind::f16.collector::b0::lastuse
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b0::lastuse [d_tmem], a_desc, b_desc, idesc, enable_input_d, zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_collector_b0_lastuse(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d,
+     uint64_t zero_column_mask_desc);
+
+tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b0::lastuse
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b0::lastuse [d_tmem], a_desc, b_desc, idesc, enable_input_d, zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_collector_b0_lastuse(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d,
+     uint64_t zero_column_mask_desc);
+
+tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b0::lastuse
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b0::lastuse [d_tmem], a_desc, b_desc, idesc, enable_input_d, zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_collector_b0_lastuse(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d,
+     uint64_t zero_column_mask_desc);
+
+tcgen05.mma.ws.cta_group::1.kind::i8.collector::b0::lastuse
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b0::lastuse [d_tmem], a_desc, b_desc, idesc, enable_input_d, zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_collector_b0_lastuse(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d,
+     uint64_t zero_column_mask_desc);
+
+tcgen05.mma.ws.cta_group::1.kind::f16.collector::b0::lastuse
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b0::lastuse [d_tmem], a_desc, b_desc, idesc, enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_collector_b0_lastuse(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d);
+
+tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b0::lastuse
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b0::lastuse [d_tmem], a_desc, b_desc, idesc, enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_collector_b0_lastuse(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d);
+
+tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b0::lastuse
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b0::lastuse [d_tmem], a_desc, b_desc, idesc, enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_collector_b0_lastuse(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d);
+
+tcgen05.mma.ws.cta_group::1.kind::i8.collector::b0::lastuse
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b0::lastuse [d_tmem], a_desc, b_desc, idesc, enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_collector_b0_lastuse(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d);
+
+tcgen05.mma.ws.cta_group::1.kind::f16.collector::b0::lastuse
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b0::lastuse [d_tmem], [a_tmem], b_desc, idesc, enable_input_d, zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_tmem_a_collector_b0_lastuse(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint32_t a_tmem,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d,
+     uint64_t zero_column_mask_desc);
+
+tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b0::lastuse
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b0::lastuse [d_tmem], [a_tmem], b_desc, idesc, enable_input_d, zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_tmem_a_collector_b0_lastuse(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint32_t a_tmem,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d,
+     uint64_t zero_column_mask_desc);
+
+tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b0::lastuse
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b0::lastuse [d_tmem], [a_tmem], b_desc, idesc, enable_input_d, zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_tmem_a_collector_b0_lastuse(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint32_t a_tmem,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d,
+     uint64_t zero_column_mask_desc);
+
+tcgen05.mma.ws.cta_group::1.kind::i8.collector::b0::lastuse
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b0::lastuse [d_tmem], [a_tmem], b_desc, idesc, enable_input_d, zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_tmem_a_collector_b0_lastuse(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint32_t a_tmem,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d,
+     uint64_t zero_column_mask_desc);
+
+tcgen05.mma.ws.cta_group::1.kind::f16.collector::b0::lastuse
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b0::lastuse [d_tmem], [a_tmem], b_desc, idesc, enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_tmem_a_collector_b0_lastuse(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint32_t a_tmem,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d);
+
+tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b0::lastuse
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b0::lastuse [d_tmem], [a_tmem], b_desc, idesc, enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_tmem_a_collector_b0_lastuse(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint32_t a_tmem,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d);
+
+tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b0::lastuse
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b0::lastuse [d_tmem], [a_tmem], b_desc, idesc, enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_tmem_a_collector_b0_lastuse(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint32_t a_tmem,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d);
+
+tcgen05.mma.ws.cta_group::1.kind::i8.collector::b0::lastuse
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b0::lastuse [d_tmem], [a_tmem], b_desc, idesc, enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_tmem_a_collector_b0_lastuse(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint32_t a_tmem,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d);
+
+tcgen05.mma.ws.cta_group::1.kind::f16.collector::b0::discard
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b0::discard [d_tmem], a_desc, b_desc, idesc, enable_input_d, zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_collector_b0_discard(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d,
+     uint64_t zero_column_mask_desc);
+
+tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b0::discard
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b0::discard [d_tmem], a_desc, b_desc, idesc, enable_input_d, zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_collector_b0_discard(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d,
+     uint64_t zero_column_mask_desc);
+
+tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b0::discard
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b0::discard [d_tmem], a_desc, b_desc, idesc, enable_input_d, zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_collector_b0_discard(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d,
+     uint64_t zero_column_mask_desc);
+
+tcgen05.mma.ws.cta_group::1.kind::i8.collector::b0::discard
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b0::discard [d_tmem], a_desc, b_desc, idesc, enable_input_d, zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_collector_b0_discard(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d,
+     uint64_t zero_column_mask_desc);
+
+tcgen05.mma.ws.cta_group::1.kind::f16.collector::b0::discard
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b0::discard [d_tmem], a_desc, b_desc, idesc, enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_collector_b0_discard(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d);
+
+tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b0::discard
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b0::discard [d_tmem], a_desc, b_desc, idesc, enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_collector_b0_discard(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d);
+
+tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b0::discard
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b0::discard [d_tmem], a_desc, b_desc, idesc, enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_collector_b0_discard(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d);
+
+tcgen05.mma.ws.cta_group::1.kind::i8.collector::b0::discard
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b0::discard [d_tmem], a_desc, b_desc, idesc, enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_collector_b0_discard(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d);
+
+tcgen05.mma.ws.cta_group::1.kind::f16.collector::b0::discard
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b0::discard [d_tmem], [a_tmem], b_desc, idesc, enable_input_d, zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_tmem_a_collector_b0_discard(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint32_t a_tmem,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d,
+     uint64_t zero_column_mask_desc);
+
+tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b0::discard
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b0::discard [d_tmem], [a_tmem], b_desc, idesc, enable_input_d, zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_tmem_a_collector_b0_discard(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint32_t a_tmem,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d,
+     uint64_t zero_column_mask_desc);
+
+tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b0::discard
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b0::discard [d_tmem], [a_tmem], b_desc, idesc, enable_input_d, zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_tmem_a_collector_b0_discard(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint32_t a_tmem,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d,
+     uint64_t zero_column_mask_desc);
+
+tcgen05.mma.ws.cta_group::1.kind::i8.collector::b0::discard
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b0::discard [d_tmem], [a_tmem], b_desc, idesc, enable_input_d, zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_tmem_a_collector_b0_discard(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint32_t a_tmem,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d,
+     uint64_t zero_column_mask_desc);
+
+tcgen05.mma.ws.cta_group::1.kind::f16.collector::b0::discard
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b0::discard [d_tmem], [a_tmem], b_desc, idesc, enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_tmem_a_collector_b0_discard(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint32_t a_tmem,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d);
+
+tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b0::discard
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b0::discard [d_tmem], [a_tmem], b_desc, idesc, enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_tmem_a_collector_b0_discard(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint32_t a_tmem,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d);
+
+tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b0::discard
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b0::discard [d_tmem], [a_tmem], b_desc, idesc, enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_tmem_a_collector_b0_discard(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint32_t a_tmem,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d);
+
+tcgen05.mma.ws.cta_group::1.kind::i8.collector::b0::discard
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b0::discard [d_tmem], [a_tmem], b_desc, idesc, enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_tmem_a_collector_b0_discard(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint32_t a_tmem,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d);
+
+tcgen05.mma.ws.cta_group::1.kind::f16.collector::b1::fill
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b1::fill [d_tmem], a_desc, b_desc, idesc, enable_input_d, zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_collector_b1_fill(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d,
+     uint64_t zero_column_mask_desc);
+
+tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b1::fill
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b1::fill [d_tmem], a_desc, b_desc, idesc, enable_input_d, zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_collector_b1_fill(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d,
+     uint64_t zero_column_mask_desc);
+
+tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b1::fill
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b1::fill [d_tmem], a_desc, b_desc, idesc, enable_input_d, zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_collector_b1_fill(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d,
+     uint64_t zero_column_mask_desc);
+
+tcgen05.mma.ws.cta_group::1.kind::i8.collector::b1::fill
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b1::fill [d_tmem], a_desc, b_desc, idesc, enable_input_d, zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_collector_b1_fill(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d,
+     uint64_t zero_column_mask_desc);
+
+tcgen05.mma.ws.cta_group::1.kind::f16.collector::b1::fill
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b1::fill [d_tmem], a_desc, b_desc, idesc, enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_collector_b1_fill(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d);
+
+tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b1::fill
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b1::fill [d_tmem], a_desc, b_desc, idesc, enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_collector_b1_fill(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d);
+
+tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b1::fill
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b1::fill [d_tmem], a_desc, b_desc, idesc, enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_collector_b1_fill(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d);
+
+tcgen05.mma.ws.cta_group::1.kind::i8.collector::b1::fill
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b1::fill [d_tmem], a_desc, b_desc, idesc, enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_collector_b1_fill(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d);
+
+tcgen05.mma.ws.cta_group::1.kind::f16.collector::b1::fill
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b1::fill [d_tmem], [a_tmem], b_desc, idesc, enable_input_d, zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_tmem_a_collector_b1_fill(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint32_t a_tmem,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d,
+     uint64_t zero_column_mask_desc);
+
+tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b1::fill
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b1::fill [d_tmem], [a_tmem], b_desc, idesc, enable_input_d, zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_tmem_a_collector_b1_fill(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint32_t a_tmem,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d,
+     uint64_t zero_column_mask_desc);
+
+tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b1::fill
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b1::fill [d_tmem], [a_tmem], b_desc, idesc, enable_input_d, zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_tmem_a_collector_b1_fill(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint32_t a_tmem,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d,
+     uint64_t zero_column_mask_desc);
+
+tcgen05.mma.ws.cta_group::1.kind::i8.collector::b1::fill
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b1::fill [d_tmem], [a_tmem], b_desc, idesc, enable_input_d, zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_tmem_a_collector_b1_fill(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint32_t a_tmem,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d,
+     uint64_t zero_column_mask_desc);
+
+tcgen05.mma.ws.cta_group::1.kind::f16.collector::b1::fill
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b1::fill [d_tmem], [a_tmem], b_desc, idesc, enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_tmem_a_collector_b1_fill(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint32_t a_tmem,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d);
+
+tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b1::fill
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b1::fill [d_tmem], [a_tmem], b_desc, idesc, enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_tmem_a_collector_b1_fill(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint32_t a_tmem,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d);
+
+tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b1::fill
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b1::fill [d_tmem], [a_tmem], b_desc, idesc, enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_tmem_a_collector_b1_fill(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint32_t a_tmem,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d);
+
+tcgen05.mma.ws.cta_group::1.kind::i8.collector::b1::fill
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b1::fill [d_tmem], [a_tmem], b_desc, idesc, enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_tmem_a_collector_b1_fill(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint32_t a_tmem,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d);
+
+tcgen05.mma.ws.cta_group::1.kind::f16.collector::b1::use
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b1::use [d_tmem], a_desc, b_desc, idesc, enable_input_d, zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_collector_b1_use(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d,
+     uint64_t zero_column_mask_desc);
+
+tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b1::use
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b1::use [d_tmem], a_desc, b_desc, idesc, enable_input_d, zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_collector_b1_use(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d,
+     uint64_t zero_column_mask_desc);
+
+tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b1::use
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b1::use [d_tmem], a_desc, b_desc, idesc, enable_input_d, zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_collector_b1_use(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d,
+     uint64_t zero_column_mask_desc);
+
+tcgen05.mma.ws.cta_group::1.kind::i8.collector::b1::use
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b1::use [d_tmem], a_desc, b_desc, idesc, enable_input_d, zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_collector_b1_use(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d,
+     uint64_t zero_column_mask_desc);
+
+tcgen05.mma.ws.cta_group::1.kind::f16.collector::b1::use
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b1::use [d_tmem], a_desc, b_desc, idesc, enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_collector_b1_use(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d);
+
+tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b1::use
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b1::use [d_tmem], a_desc, b_desc, idesc, enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_collector_b1_use(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d);
+
+tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b1::use
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b1::use [d_tmem], a_desc, b_desc, idesc, enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_collector_b1_use(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d);
+
+tcgen05.mma.ws.cta_group::1.kind::i8.collector::b1::use
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b1::use [d_tmem], a_desc, b_desc, idesc, enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_collector_b1_use(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d);
+
+tcgen05.mma.ws.cta_group::1.kind::f16.collector::b1::use
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b1::use [d_tmem], [a_tmem], b_desc, idesc, enable_input_d, zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_tmem_a_collector_b1_use(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint32_t a_tmem,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d,
+     uint64_t zero_column_mask_desc);
+
+tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b1::use
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b1::use [d_tmem], [a_tmem], b_desc, idesc, enable_input_d, zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_tmem_a_collector_b1_use(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint32_t a_tmem,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d,
+     uint64_t zero_column_mask_desc);
+
+tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b1::use
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b1::use [d_tmem], [a_tmem], b_desc, idesc, enable_input_d, zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_tmem_a_collector_b1_use(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint32_t a_tmem,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d,
+     uint64_t zero_column_mask_desc);
+
+tcgen05.mma.ws.cta_group::1.kind::i8.collector::b1::use
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b1::use [d_tmem], [a_tmem], b_desc, idesc, enable_input_d, zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_tmem_a_collector_b1_use(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint32_t a_tmem,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d,
+     uint64_t zero_column_mask_desc);
+
+tcgen05.mma.ws.cta_group::1.kind::f16.collector::b1::use
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b1::use [d_tmem], [a_tmem], b_desc, idesc, enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_tmem_a_collector_b1_use(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint32_t a_tmem,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d);
+
+tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b1::use
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b1::use [d_tmem], [a_tmem], b_desc, idesc, enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_tmem_a_collector_b1_use(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint32_t a_tmem,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d);
+
+tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b1::use
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b1::use [d_tmem], [a_tmem], b_desc, idesc, enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_tmem_a_collector_b1_use(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint32_t a_tmem,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d);
+
+tcgen05.mma.ws.cta_group::1.kind::i8.collector::b1::use
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b1::use [d_tmem], [a_tmem], b_desc, idesc, enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_tmem_a_collector_b1_use(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint32_t a_tmem,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d);
+
+tcgen05.mma.ws.cta_group::1.kind::f16.collector::b1::lastuse
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b1::lastuse [d_tmem], a_desc, b_desc, idesc, enable_input_d, zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_collector_b1_lastuse(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d,
+     uint64_t zero_column_mask_desc);
+
+tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b1::lastuse
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b1::lastuse [d_tmem], a_desc, b_desc, idesc, enable_input_d, zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_collector_b1_lastuse(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d,
+     uint64_t zero_column_mask_desc);
+
+tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b1::lastuse
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b1::lastuse [d_tmem], a_desc, b_desc, idesc, enable_input_d, zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_collector_b1_lastuse(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d,
+     uint64_t zero_column_mask_desc);
+
+tcgen05.mma.ws.cta_group::1.kind::i8.collector::b1::lastuse
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b1::lastuse [d_tmem], a_desc, b_desc, idesc, enable_input_d, zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_collector_b1_lastuse(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d,
+     uint64_t zero_column_mask_desc);
+
+tcgen05.mma.ws.cta_group::1.kind::f16.collector::b1::lastuse
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b1::lastuse [d_tmem], a_desc, b_desc, idesc, enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_collector_b1_lastuse(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d);
+
+tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b1::lastuse
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b1::lastuse [d_tmem], a_desc, b_desc, idesc, enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_collector_b1_lastuse(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d);
+
+tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b1::lastuse
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b1::lastuse [d_tmem], a_desc, b_desc, idesc, enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_collector_b1_lastuse(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d);
+
+tcgen05.mma.ws.cta_group::1.kind::i8.collector::b1::lastuse
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b1::lastuse [d_tmem], a_desc, b_desc, idesc, enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_collector_b1_lastuse(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d);
+
+tcgen05.mma.ws.cta_group::1.kind::f16.collector::b1::lastuse
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b1::lastuse [d_tmem], [a_tmem], b_desc, idesc, enable_input_d, zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_tmem_a_collector_b1_lastuse(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint32_t a_tmem,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d,
+     uint64_t zero_column_mask_desc);
+
+tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b1::lastuse
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b1::lastuse [d_tmem], [a_tmem], b_desc, idesc, enable_input_d, zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_tmem_a_collector_b1_lastuse(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint32_t a_tmem,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d,
+     uint64_t zero_column_mask_desc);
+
+tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b1::lastuse
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b1::lastuse [d_tmem], [a_tmem], b_desc, idesc, enable_input_d, zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_tmem_a_collector_b1_lastuse(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint32_t a_tmem,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d,
+     uint64_t zero_column_mask_desc);
+
+tcgen05.mma.ws.cta_group::1.kind::i8.collector::b1::lastuse
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b1::lastuse [d_tmem], [a_tmem], b_desc, idesc, enable_input_d, zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_tmem_a_collector_b1_lastuse(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint32_t a_tmem,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d,
+     uint64_t zero_column_mask_desc);
+
+tcgen05.mma.ws.cta_group::1.kind::f16.collector::b1::lastuse
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b1::lastuse [d_tmem], [a_tmem], b_desc, idesc, enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_tmem_a_collector_b1_lastuse(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint32_t a_tmem,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d);
+
+tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b1::lastuse
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b1::lastuse [d_tmem], [a_tmem], b_desc, idesc, enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_tmem_a_collector_b1_lastuse(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint32_t a_tmem,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d);
+
+tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b1::lastuse
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b1::lastuse [d_tmem], [a_tmem], b_desc, idesc, enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_tmem_a_collector_b1_lastuse(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint32_t a_tmem,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d);
+
+tcgen05.mma.ws.cta_group::1.kind::i8.collector::b1::lastuse
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b1::lastuse [d_tmem], [a_tmem], b_desc, idesc, enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_tmem_a_collector_b1_lastuse(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint32_t a_tmem,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d);
+
+tcgen05.mma.ws.cta_group::1.kind::f16.collector::b1::discard
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b1::discard [d_tmem], a_desc, b_desc, idesc, enable_input_d, zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_collector_b1_discard(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d,
+     uint64_t zero_column_mask_desc);
+
+tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b1::discard
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b1::discard [d_tmem], a_desc, b_desc, idesc, enable_input_d, zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_collector_b1_discard(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d,
+     uint64_t zero_column_mask_desc);
+
+tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b1::discard
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b1::discard [d_tmem], a_desc, b_desc, idesc, enable_input_d, zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_collector_b1_discard(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d,
+     uint64_t zero_column_mask_desc);
+
+tcgen05.mma.ws.cta_group::1.kind::i8.collector::b1::discard
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b1::discard [d_tmem], a_desc, b_desc, idesc, enable_input_d, zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_collector_b1_discard(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d,
+     uint64_t zero_column_mask_desc);
+
+tcgen05.mma.ws.cta_group::1.kind::f16.collector::b1::discard
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b1::discard [d_tmem], a_desc, b_desc, idesc, enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_collector_b1_discard(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d);
+
+tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b1::discard
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b1::discard [d_tmem], a_desc, b_desc, idesc, enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_collector_b1_discard(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d);
+
+tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b1::discard
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b1::discard [d_tmem], a_desc, b_desc, idesc, enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_collector_b1_discard(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d);
+
+tcgen05.mma.ws.cta_group::1.kind::i8.collector::b1::discard
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b1::discard [d_tmem], a_desc, b_desc, idesc, enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_collector_b1_discard(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d);
+
+tcgen05.mma.ws.cta_group::1.kind::f16.collector::b1::discard
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b1::discard [d_tmem], [a_tmem], b_desc, idesc, enable_input_d, zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_tmem_a_collector_b1_discard(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint32_t a_tmem,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d,
+     uint64_t zero_column_mask_desc);
+
+tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b1::discard
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b1::discard [d_tmem], [a_tmem], b_desc, idesc, enable_input_d, zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_tmem_a_collector_b1_discard(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint32_t a_tmem,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d,
+     uint64_t zero_column_mask_desc);
+
+tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b1::discard
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b1::discard [d_tmem], [a_tmem], b_desc, idesc, enable_input_d, zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_tmem_a_collector_b1_discard(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint32_t a_tmem,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d,
+     uint64_t zero_column_mask_desc);
+
+tcgen05.mma.ws.cta_group::1.kind::i8.collector::b1::discard
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b1::discard [d_tmem], [a_tmem], b_desc, idesc, enable_input_d, zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_tmem_a_collector_b1_discard(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint32_t a_tmem,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d,
+     uint64_t zero_column_mask_desc);
+
+tcgen05.mma.ws.cta_group::1.kind::f16.collector::b1::discard
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b1::discard [d_tmem], [a_tmem], b_desc, idesc, enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_tmem_a_collector_b1_discard(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint32_t a_tmem,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d);
+
+tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b1::discard
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b1::discard [d_tmem], [a_tmem], b_desc, idesc, enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_tmem_a_collector_b1_discard(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint32_t a_tmem,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d);
+
+tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b1::discard
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b1::discard [d_tmem], [a_tmem], b_desc, idesc, enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_tmem_a_collector_b1_discard(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint32_t a_tmem,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d);
+
+tcgen05.mma.ws.cta_group::1.kind::i8.collector::b1::discard
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b1::discard [d_tmem], [a_tmem], b_desc, idesc, enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_tmem_a_collector_b1_discard(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint32_t a_tmem,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d);
+
+tcgen05.mma.ws.cta_group::1.kind::f16.collector::b2::fill
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b2::fill [d_tmem], a_desc, b_desc, idesc, enable_input_d, zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_collector_b2_fill(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d,
+     uint64_t zero_column_mask_desc);
+
+tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b2::fill
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b2::fill [d_tmem], a_desc, b_desc, idesc, enable_input_d, zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_collector_b2_fill(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d,
+     uint64_t zero_column_mask_desc);
+
+tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b2::fill
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b2::fill [d_tmem], a_desc, b_desc, idesc, enable_input_d, zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_collector_b2_fill(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d,
+     uint64_t zero_column_mask_desc);
+
+tcgen05.mma.ws.cta_group::1.kind::i8.collector::b2::fill
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b2::fill [d_tmem], a_desc, b_desc, idesc, enable_input_d, zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_collector_b2_fill(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d,
+     uint64_t zero_column_mask_desc);
+
+tcgen05.mma.ws.cta_group::1.kind::f16.collector::b2::fill
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b2::fill [d_tmem], a_desc, b_desc, idesc, enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_collector_b2_fill(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d);
+
+tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b2::fill
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b2::fill [d_tmem], a_desc, b_desc, idesc, enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_collector_b2_fill(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d);
+
+tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b2::fill
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b2::fill [d_tmem], a_desc, b_desc, idesc, enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_collector_b2_fill(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d);
+
+tcgen05.mma.ws.cta_group::1.kind::i8.collector::b2::fill
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b2::fill [d_tmem], a_desc, b_desc, idesc, enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_collector_b2_fill(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d);
+
+tcgen05.mma.ws.cta_group::1.kind::f16.collector::b2::fill
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b2::fill [d_tmem], [a_tmem], b_desc, idesc, enable_input_d, zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_tmem_a_collector_b2_fill(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint32_t a_tmem,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d,
+     uint64_t zero_column_mask_desc);
+
+tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b2::fill
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b2::fill [d_tmem], [a_tmem], b_desc, idesc, enable_input_d, zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_tmem_a_collector_b2_fill(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint32_t a_tmem,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d,
+     uint64_t zero_column_mask_desc);
+
+tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b2::fill
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b2::fill [d_tmem], [a_tmem], b_desc, idesc, enable_input_d, zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_tmem_a_collector_b2_fill(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint32_t a_tmem,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d,
+     uint64_t zero_column_mask_desc);
+
+tcgen05.mma.ws.cta_group::1.kind::i8.collector::b2::fill
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b2::fill [d_tmem], [a_tmem], b_desc, idesc, enable_input_d, zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_tmem_a_collector_b2_fill(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint32_t a_tmem,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d,
+     uint64_t zero_column_mask_desc);
+
+tcgen05.mma.ws.cta_group::1.kind::f16.collector::b2::fill
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b2::fill [d_tmem], [a_tmem], b_desc, idesc, enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_tmem_a_collector_b2_fill(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint32_t a_tmem,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d);
+
+tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b2::fill
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b2::fill [d_tmem], [a_tmem], b_desc, idesc, enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_tmem_a_collector_b2_fill(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint32_t a_tmem,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d);
+
+tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b2::fill
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b2::fill [d_tmem], [a_tmem], b_desc, idesc, enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_tmem_a_collector_b2_fill(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint32_t a_tmem,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d);
+
+tcgen05.mma.ws.cta_group::1.kind::i8.collector::b2::fill
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b2::fill [d_tmem], [a_tmem], b_desc, idesc, enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_tmem_a_collector_b2_fill(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint32_t a_tmem,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d);
+
+tcgen05.mma.ws.cta_group::1.kind::f16.collector::b2::use
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b2::use [d_tmem], a_desc, b_desc, idesc, enable_input_d, zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_collector_b2_use(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d,
+     uint64_t zero_column_mask_desc);
+
+tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b2::use
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b2::use [d_tmem], a_desc, b_desc, idesc, enable_input_d, zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_collector_b2_use(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d,
+     uint64_t zero_column_mask_desc);
+
+tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b2::use
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b2::use [d_tmem], a_desc, b_desc, idesc, enable_input_d, zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_collector_b2_use(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d,
+     uint64_t zero_column_mask_desc);
+
+tcgen05.mma.ws.cta_group::1.kind::i8.collector::b2::use
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b2::use [d_tmem], a_desc, b_desc, idesc, enable_input_d, zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_collector_b2_use(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d,
+     uint64_t zero_column_mask_desc);
+
+tcgen05.mma.ws.cta_group::1.kind::f16.collector::b2::use
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b2::use [d_tmem], a_desc, b_desc, idesc, enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_collector_b2_use(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d);
+
+tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b2::use
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b2::use [d_tmem], a_desc, b_desc, idesc, enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_collector_b2_use(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d);
+
+tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b2::use
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b2::use [d_tmem], a_desc, b_desc, idesc, enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_collector_b2_use(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d);
+
+tcgen05.mma.ws.cta_group::1.kind::i8.collector::b2::use
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b2::use [d_tmem], a_desc, b_desc, idesc, enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_collector_b2_use(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d);
+
+tcgen05.mma.ws.cta_group::1.kind::f16.collector::b2::use
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b2::use [d_tmem], [a_tmem], b_desc, idesc, enable_input_d, zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_tmem_a_collector_b2_use(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint32_t a_tmem,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d,
+     uint64_t zero_column_mask_desc);
+
+tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b2::use
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b2::use [d_tmem], [a_tmem], b_desc, idesc, enable_input_d, zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_tmem_a_collector_b2_use(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint32_t a_tmem,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d,
+     uint64_t zero_column_mask_desc);
+
+tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b2::use
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b2::use [d_tmem], [a_tmem], b_desc, idesc, enable_input_d, zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_tmem_a_collector_b2_use(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint32_t a_tmem,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d,
+     uint64_t zero_column_mask_desc);
+
+tcgen05.mma.ws.cta_group::1.kind::i8.collector::b2::use
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b2::use [d_tmem], [a_tmem], b_desc, idesc, enable_input_d, zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_tmem_a_collector_b2_use(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint32_t a_tmem,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d,
+     uint64_t zero_column_mask_desc);
+
+tcgen05.mma.ws.cta_group::1.kind::f16.collector::b2::use
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b2::use [d_tmem], [a_tmem], b_desc, idesc, enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_tmem_a_collector_b2_use(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint32_t a_tmem,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d);
+
+tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b2::use
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b2::use [d_tmem], [a_tmem], b_desc, idesc, enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_tmem_a_collector_b2_use(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint32_t a_tmem,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d);
+
+tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b2::use
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b2::use [d_tmem], [a_tmem], b_desc, idesc, enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_tmem_a_collector_b2_use(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint32_t a_tmem,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d);
+
+tcgen05.mma.ws.cta_group::1.kind::i8.collector::b2::use
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b2::use [d_tmem], [a_tmem], b_desc, idesc, enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_tmem_a_collector_b2_use(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint32_t a_tmem,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d);
+
+tcgen05.mma.ws.cta_group::1.kind::f16.collector::b2::lastuse
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b2::lastuse [d_tmem], a_desc, b_desc, idesc, enable_input_d, zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_collector_b2_lastuse(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d,
+     uint64_t zero_column_mask_desc);
+
+tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b2::lastuse
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b2::lastuse [d_tmem], a_desc, b_desc, idesc, enable_input_d, zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_collector_b2_lastuse(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d,
+     uint64_t zero_column_mask_desc);
+
+tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b2::lastuse
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b2::lastuse [d_tmem], a_desc, b_desc, idesc, enable_input_d, zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_collector_b2_lastuse(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d,
+     uint64_t zero_column_mask_desc);
+
+tcgen05.mma.ws.cta_group::1.kind::i8.collector::b2::lastuse
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b2::lastuse [d_tmem], a_desc, b_desc, idesc, enable_input_d, zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_collector_b2_lastuse(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d,
+     uint64_t zero_column_mask_desc);
+
+tcgen05.mma.ws.cta_group::1.kind::f16.collector::b2::lastuse
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b2::lastuse [d_tmem], a_desc, b_desc, idesc, enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_collector_b2_lastuse(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d);
+
+tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b2::lastuse
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b2::lastuse [d_tmem], a_desc, b_desc, idesc, enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_collector_b2_lastuse(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d);
+
+tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b2::lastuse
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b2::lastuse [d_tmem], a_desc, b_desc, idesc, enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_collector_b2_lastuse(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d);
+
+tcgen05.mma.ws.cta_group::1.kind::i8.collector::b2::lastuse
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b2::lastuse [d_tmem], a_desc, b_desc, idesc, enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_collector_b2_lastuse(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d);
+
+tcgen05.mma.ws.cta_group::1.kind::f16.collector::b2::lastuse
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b2::lastuse [d_tmem], [a_tmem], b_desc, idesc, enable_input_d, zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_tmem_a_collector_b2_lastuse(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint32_t a_tmem,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d,
+     uint64_t zero_column_mask_desc);
+
+tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b2::lastuse
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b2::lastuse [d_tmem], [a_tmem], b_desc, idesc, enable_input_d, zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_tmem_a_collector_b2_lastuse(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint32_t a_tmem,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d,
+     uint64_t zero_column_mask_desc);
+
+tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b2::lastuse
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b2::lastuse [d_tmem], [a_tmem], b_desc, idesc, enable_input_d, zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_tmem_a_collector_b2_lastuse(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint32_t a_tmem,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d,
+     uint64_t zero_column_mask_desc);
+
+tcgen05.mma.ws.cta_group::1.kind::i8.collector::b2::lastuse
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b2::lastuse [d_tmem], [a_tmem], b_desc, idesc, enable_input_d, zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_tmem_a_collector_b2_lastuse(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint32_t a_tmem,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d,
+     uint64_t zero_column_mask_desc);
+
+tcgen05.mma.ws.cta_group::1.kind::f16.collector::b2::lastuse
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b2::lastuse [d_tmem], [a_tmem], b_desc, idesc, enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_tmem_a_collector_b2_lastuse(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint32_t a_tmem,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d);
+
+tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b2::lastuse
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b2::lastuse [d_tmem], [a_tmem], b_desc, idesc, enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_tmem_a_collector_b2_lastuse(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint32_t a_tmem,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d);
+
+tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b2::lastuse
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b2::lastuse [d_tmem], [a_tmem], b_desc, idesc, enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_tmem_a_collector_b2_lastuse(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint32_t a_tmem,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d);
+
+tcgen05.mma.ws.cta_group::1.kind::i8.collector::b2::lastuse
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b2::lastuse [d_tmem], [a_tmem], b_desc, idesc, enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_tmem_a_collector_b2_lastuse(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint32_t a_tmem,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d);
+
+tcgen05.mma.ws.cta_group::1.kind::f16.collector::b2::discard
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b2::discard [d_tmem], a_desc, b_desc, idesc, enable_input_d, zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_collector_b2_discard(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d,
+     uint64_t zero_column_mask_desc);
+
+tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b2::discard
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b2::discard [d_tmem], a_desc, b_desc, idesc, enable_input_d, zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_collector_b2_discard(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d,
+     uint64_t zero_column_mask_desc);
+
+tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b2::discard
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b2::discard [d_tmem], a_desc, b_desc, idesc, enable_input_d, zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_collector_b2_discard(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d,
+     uint64_t zero_column_mask_desc);
+
+tcgen05.mma.ws.cta_group::1.kind::i8.collector::b2::discard
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b2::discard [d_tmem], a_desc, b_desc, idesc, enable_input_d, zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_collector_b2_discard(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d,
+     uint64_t zero_column_mask_desc);
+
+tcgen05.mma.ws.cta_group::1.kind::f16.collector::b2::discard
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b2::discard [d_tmem], a_desc, b_desc, idesc, enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_collector_b2_discard(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d);
+
+tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b2::discard
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b2::discard [d_tmem], a_desc, b_desc, idesc, enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_collector_b2_discard(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d);
+
+tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b2::discard
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b2::discard [d_tmem], a_desc, b_desc, idesc, enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_collector_b2_discard(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d);
+
+tcgen05.mma.ws.cta_group::1.kind::i8.collector::b2::discard
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b2::discard [d_tmem], a_desc, b_desc, idesc, enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_collector_b2_discard(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d);
+
+tcgen05.mma.ws.cta_group::1.kind::f16.collector::b2::discard
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b2::discard [d_tmem], [a_tmem], b_desc, idesc, enable_input_d, zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_tmem_a_collector_b2_discard(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint32_t a_tmem,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d,
+     uint64_t zero_column_mask_desc);
+
+tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b2::discard
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b2::discard [d_tmem], [a_tmem], b_desc, idesc, enable_input_d, zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_tmem_a_collector_b2_discard(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint32_t a_tmem,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d,
+     uint64_t zero_column_mask_desc);
+
+tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b2::discard
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b2::discard [d_tmem], [a_tmem], b_desc, idesc, enable_input_d, zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_tmem_a_collector_b2_discard(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint32_t a_tmem,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d,
+     uint64_t zero_column_mask_desc);
+
+tcgen05.mma.ws.cta_group::1.kind::i8.collector::b2::discard
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b2::discard [d_tmem], [a_tmem], b_desc, idesc, enable_input_d, zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_tmem_a_collector_b2_discard(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint32_t a_tmem,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d,
+     uint64_t zero_column_mask_desc);
+
+tcgen05.mma.ws.cta_group::1.kind::f16.collector::b2::discard
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b2::discard [d_tmem], [a_tmem], b_desc, idesc, enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_tmem_a_collector_b2_discard(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint32_t a_tmem,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d);
+
+tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b2::discard
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b2::discard [d_tmem], [a_tmem], b_desc, idesc, enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_tmem_a_collector_b2_discard(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint32_t a_tmem,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d);
+
+tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b2::discard
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b2::discard [d_tmem], [a_tmem], b_desc, idesc, enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_tmem_a_collector_b2_discard(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint32_t a_tmem,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d);
+
+tcgen05.mma.ws.cta_group::1.kind::i8.collector::b2::discard
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b2::discard [d_tmem], [a_tmem], b_desc, idesc, enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_tmem_a_collector_b2_discard(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint32_t a_tmem,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d);
+
+tcgen05.mma.ws.cta_group::1.kind::f16.collector::b3::fill
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b3::fill [d_tmem], a_desc, b_desc, idesc, enable_input_d, zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_collector_b3_fill(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d,
+     uint64_t zero_column_mask_desc);
+
+tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b3::fill
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b3::fill [d_tmem], a_desc, b_desc, idesc, enable_input_d, zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_collector_b3_fill(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d,
+     uint64_t zero_column_mask_desc);
+
+tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b3::fill
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b3::fill [d_tmem], a_desc, b_desc, idesc, enable_input_d, zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_collector_b3_fill(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d,
+     uint64_t zero_column_mask_desc);
+
+tcgen05.mma.ws.cta_group::1.kind::i8.collector::b3::fill
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b3::fill [d_tmem], a_desc, b_desc, idesc, enable_input_d, zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_collector_b3_fill(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d,
+     uint64_t zero_column_mask_desc);
+
+tcgen05.mma.ws.cta_group::1.kind::f16.collector::b3::fill
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b3::fill [d_tmem], a_desc, b_desc, idesc, enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_collector_b3_fill(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d);
+
+tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b3::fill
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b3::fill [d_tmem], a_desc, b_desc, idesc, enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_collector_b3_fill(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d);
+
+tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b3::fill
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b3::fill [d_tmem], a_desc, b_desc, idesc, enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_collector_b3_fill(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d);
+
+tcgen05.mma.ws.cta_group::1.kind::i8.collector::b3::fill
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b3::fill [d_tmem], a_desc, b_desc, idesc, enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_collector_b3_fill(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d);
+
+tcgen05.mma.ws.cta_group::1.kind::f16.collector::b3::fill
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b3::fill [d_tmem], [a_tmem], b_desc, idesc, enable_input_d, zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_tmem_a_collector_b3_fill(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint32_t a_tmem,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d,
+     uint64_t zero_column_mask_desc);
+
+tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b3::fill
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b3::fill [d_tmem], [a_tmem], b_desc, idesc, enable_input_d, zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_tmem_a_collector_b3_fill(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint32_t a_tmem,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d,
+     uint64_t zero_column_mask_desc);
+
+tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b3::fill
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b3::fill [d_tmem], [a_tmem], b_desc, idesc, enable_input_d, zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_tmem_a_collector_b3_fill(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint32_t a_tmem,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d,
+     uint64_t zero_column_mask_desc);
+
+tcgen05.mma.ws.cta_group::1.kind::i8.collector::b3::fill
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b3::fill [d_tmem], [a_tmem], b_desc, idesc, enable_input_d, zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_tmem_a_collector_b3_fill(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint32_t a_tmem,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d,
+     uint64_t zero_column_mask_desc);
+
+tcgen05.mma.ws.cta_group::1.kind::f16.collector::b3::fill
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b3::fill [d_tmem], [a_tmem], b_desc, idesc, enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_tmem_a_collector_b3_fill(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint32_t a_tmem,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d);
+
+tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b3::fill
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b3::fill [d_tmem], [a_tmem], b_desc, idesc, enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_tmem_a_collector_b3_fill(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint32_t a_tmem,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d);
+
+tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b3::fill
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b3::fill [d_tmem], [a_tmem], b_desc, idesc, enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_tmem_a_collector_b3_fill(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint32_t a_tmem,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d);
+
+tcgen05.mma.ws.cta_group::1.kind::i8.collector::b3::fill
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b3::fill [d_tmem], [a_tmem], b_desc, idesc, enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_tmem_a_collector_b3_fill(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint32_t a_tmem,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d);
+
+tcgen05.mma.ws.cta_group::1.kind::f16.collector::b3::use
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b3::use [d_tmem], a_desc, b_desc, idesc, enable_input_d, zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_collector_b3_use(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d,
+     uint64_t zero_column_mask_desc);
+
+tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b3::use
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b3::use [d_tmem], a_desc, b_desc, idesc, enable_input_d, zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_collector_b3_use(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d,
+     uint64_t zero_column_mask_desc);
+
+tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b3::use
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b3::use [d_tmem], a_desc, b_desc, idesc, enable_input_d, zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_collector_b3_use(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d,
+     uint64_t zero_column_mask_desc);
+
+tcgen05.mma.ws.cta_group::1.kind::i8.collector::b3::use
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b3::use [d_tmem], a_desc, b_desc, idesc, enable_input_d, zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_collector_b3_use(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d,
+     uint64_t zero_column_mask_desc);
+
+tcgen05.mma.ws.cta_group::1.kind::f16.collector::b3::use
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b3::use [d_tmem], a_desc, b_desc, idesc, enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_collector_b3_use(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d);
+
+tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b3::use
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b3::use [d_tmem], a_desc, b_desc, idesc, enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_collector_b3_use(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d);
+
+tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b3::use
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b3::use [d_tmem], a_desc, b_desc, idesc, enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_collector_b3_use(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d);
+
+tcgen05.mma.ws.cta_group::1.kind::i8.collector::b3::use
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b3::use [d_tmem], a_desc, b_desc, idesc, enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_collector_b3_use(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d);
+
+tcgen05.mma.ws.cta_group::1.kind::f16.collector::b3::use
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b3::use [d_tmem], [a_tmem], b_desc, idesc, enable_input_d, zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_tmem_a_collector_b3_use(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint32_t a_tmem,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d,
+     uint64_t zero_column_mask_desc);
+
+tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b3::use
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b3::use [d_tmem], [a_tmem], b_desc, idesc, enable_input_d, zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_tmem_a_collector_b3_use(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint32_t a_tmem,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d,
+     uint64_t zero_column_mask_desc);
+
+tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b3::use
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b3::use [d_tmem], [a_tmem], b_desc, idesc, enable_input_d, zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_tmem_a_collector_b3_use(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint32_t a_tmem,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d,
+     uint64_t zero_column_mask_desc);
+
+tcgen05.mma.ws.cta_group::1.kind::i8.collector::b3::use
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b3::use [d_tmem], [a_tmem], b_desc, idesc, enable_input_d, zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_tmem_a_collector_b3_use(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint32_t a_tmem,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d,
+     uint64_t zero_column_mask_desc);
+
+tcgen05.mma.ws.cta_group::1.kind::f16.collector::b3::use
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b3::use [d_tmem], [a_tmem], b_desc, idesc, enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_tmem_a_collector_b3_use(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint32_t a_tmem,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d);
+
+tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b3::use
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b3::use [d_tmem], [a_tmem], b_desc, idesc, enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_tmem_a_collector_b3_use(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint32_t a_tmem,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d);
+
+tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b3::use
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b3::use [d_tmem], [a_tmem], b_desc, idesc, enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_tmem_a_collector_b3_use(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint32_t a_tmem,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d);
+
+tcgen05.mma.ws.cta_group::1.kind::i8.collector::b3::use
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b3::use [d_tmem], [a_tmem], b_desc, idesc, enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_tmem_a_collector_b3_use(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint32_t a_tmem,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d);
+
+tcgen05.mma.ws.cta_group::1.kind::f16.collector::b3::lastuse
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b3::lastuse [d_tmem], a_desc, b_desc, idesc, enable_input_d, zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_collector_b3_lastuse(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d,
+     uint64_t zero_column_mask_desc);
+
+tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b3::lastuse
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b3::lastuse [d_tmem], a_desc, b_desc, idesc, enable_input_d, zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_collector_b3_lastuse(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d,
+     uint64_t zero_column_mask_desc);
+
+tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b3::lastuse
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b3::lastuse [d_tmem], a_desc, b_desc, idesc, enable_input_d, zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_collector_b3_lastuse(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d,
+     uint64_t zero_column_mask_desc);
+
+tcgen05.mma.ws.cta_group::1.kind::i8.collector::b3::lastuse
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b3::lastuse [d_tmem], a_desc, b_desc, idesc, enable_input_d, zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_collector_b3_lastuse(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d,
+     uint64_t zero_column_mask_desc);
+
+tcgen05.mma.ws.cta_group::1.kind::f16.collector::b3::lastuse
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b3::lastuse [d_tmem], a_desc, b_desc, idesc, enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_collector_b3_lastuse(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d);
+
+tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b3::lastuse
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b3::lastuse [d_tmem], a_desc, b_desc, idesc, enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_collector_b3_lastuse(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d);
+
+tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b3::lastuse
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b3::lastuse [d_tmem], a_desc, b_desc, idesc, enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_collector_b3_lastuse(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d);
+
+tcgen05.mma.ws.cta_group::1.kind::i8.collector::b3::lastuse
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b3::lastuse [d_tmem], a_desc, b_desc, idesc, enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_collector_b3_lastuse(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d);
+
+tcgen05.mma.ws.cta_group::1.kind::f16.collector::b3::lastuse
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b3::lastuse [d_tmem], [a_tmem], b_desc, idesc, enable_input_d, zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_tmem_a_collector_b3_lastuse(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint32_t a_tmem,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d,
+     uint64_t zero_column_mask_desc);
+
+tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b3::lastuse
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b3::lastuse [d_tmem], [a_tmem], b_desc, idesc, enable_input_d, zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_tmem_a_collector_b3_lastuse(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint32_t a_tmem,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d,
+     uint64_t zero_column_mask_desc);
+
+tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b3::lastuse
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b3::lastuse [d_tmem], [a_tmem], b_desc, idesc, enable_input_d, zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_tmem_a_collector_b3_lastuse(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint32_t a_tmem,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d,
+     uint64_t zero_column_mask_desc);
+
+tcgen05.mma.ws.cta_group::1.kind::i8.collector::b3::lastuse
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b3::lastuse [d_tmem], [a_tmem], b_desc, idesc, enable_input_d, zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_tmem_a_collector_b3_lastuse(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint32_t a_tmem,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d,
+     uint64_t zero_column_mask_desc);
+
+tcgen05.mma.ws.cta_group::1.kind::f16.collector::b3::lastuse
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b3::lastuse [d_tmem], [a_tmem], b_desc, idesc, enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_tmem_a_collector_b3_lastuse(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint32_t a_tmem,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d);
+
+tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b3::lastuse
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b3::lastuse [d_tmem], [a_tmem], b_desc, idesc, enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_tmem_a_collector_b3_lastuse(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint32_t a_tmem,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d);
+
+tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b3::lastuse
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b3::lastuse [d_tmem], [a_tmem], b_desc, idesc, enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_tmem_a_collector_b3_lastuse(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint32_t a_tmem,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d);
+
+tcgen05.mma.ws.cta_group::1.kind::i8.collector::b3::lastuse
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b3::lastuse [d_tmem], [a_tmem], b_desc, idesc, enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_tmem_a_collector_b3_lastuse(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint32_t a_tmem,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d);
+
+tcgen05.mma.ws.cta_group::1.kind::f16.collector::b3::discard
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b3::discard [d_tmem], a_desc, b_desc, idesc, enable_input_d, zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_collector_b3_discard(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d,
+     uint64_t zero_column_mask_desc);
+
+tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b3::discard
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b3::discard [d_tmem], a_desc, b_desc, idesc, enable_input_d, zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_collector_b3_discard(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d,
+     uint64_t zero_column_mask_desc);
+
+tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b3::discard
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b3::discard [d_tmem], a_desc, b_desc, idesc, enable_input_d, zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_collector_b3_discard(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d,
+     uint64_t zero_column_mask_desc);
+
+tcgen05.mma.ws.cta_group::1.kind::i8.collector::b3::discard
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b3::discard [d_tmem], a_desc, b_desc, idesc, enable_input_d, zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_collector_b3_discard(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d,
+     uint64_t zero_column_mask_desc);
+
+tcgen05.mma.ws.cta_group::1.kind::f16.collector::b3::discard
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b3::discard [d_tmem], a_desc, b_desc, idesc, enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_collector_b3_discard(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d);
+
+tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b3::discard
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b3::discard [d_tmem], a_desc, b_desc, idesc, enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_collector_b3_discard(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d);
+
+tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b3::discard
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b3::discard [d_tmem], a_desc, b_desc, idesc, enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_collector_b3_discard(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d);
+
+tcgen05.mma.ws.cta_group::1.kind::i8.collector::b3::discard
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b3::discard [d_tmem], a_desc, b_desc, idesc, enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_collector_b3_discard(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint64_t a_desc,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d);
+
+tcgen05.mma.ws.cta_group::1.kind::f16.collector::b3::discard
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b3::discard [d_tmem], [a_tmem], b_desc, idesc, enable_input_d, zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_tmem_a_collector_b3_discard(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint32_t a_tmem,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d,
+     uint64_t zero_column_mask_desc);
+
+tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b3::discard
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b3::discard [d_tmem], [a_tmem], b_desc, idesc, enable_input_d, zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_tmem_a_collector_b3_discard(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint32_t a_tmem,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d,
+     uint64_t zero_column_mask_desc);
+
+tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b3::discard
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b3::discard [d_tmem], [a_tmem], b_desc, idesc, enable_input_d, zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_tmem_a_collector_b3_discard(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint32_t a_tmem,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d,
+     uint64_t zero_column_mask_desc);
+
+tcgen05.mma.ws.cta_group::1.kind::i8.collector::b3::discard
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b3::discard [d_tmem], [a_tmem], b_desc, idesc, enable_input_d, zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_tmem_a_collector_b3_discard(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint32_t a_tmem,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d,
+     uint64_t zero_column_mask_desc);
+
+tcgen05.mma.ws.cta_group::1.kind::f16.collector::b3::discard
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b3::discard [d_tmem], [a_tmem], b_desc, idesc, enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_tmem_a_collector_b3_discard(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint32_t a_tmem,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d);
+
+tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b3::discard
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b3::discard [d_tmem], [a_tmem], b_desc, idesc, enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_tmem_a_collector_b3_discard(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint32_t a_tmem,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d);
+
+tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b3::discard
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b3::discard [d_tmem], [a_tmem], b_desc, idesc, enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_tmem_a_collector_b3_discard(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint32_t a_tmem,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d);
+
+tcgen05.mma.ws.cta_group::1.kind::i8.collector::b3::discard
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.mma.ws.cta_group.kind.collector::b3::discard [d_tmem], [a_tmem], b_desc, idesc, enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1 }
+   // .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+   template <cuda::ptx::dot_kind Kind>
+   __device__ static inline void tcgen05_mma_ws_tmem_a_collector_b3_discard(
+     cuda::ptx::cta_group_1_t,
+     cuda::ptx::kind_t<Kind> kind,
+     uint32_t d_tmem,
+     uint32_t a_tmem,
+     uint64_t b_desc,
+     uint32_t idesc,
+     bool enable_input_d);
diff --git a/docs/libcudacxx/ptx/instructions/generated/tcgen05_shift.rst b/docs/libcudacxx/ptx/instructions/generated/tcgen05_shift.rst
new file mode 100644
index 00000000000..54e665ed3cc
--- /dev/null
+++ b/docs/libcudacxx/ptx/instructions/generated/tcgen05_shift.rst
@@ -0,0 +1,24 @@
+..
+   This file was automatically generated. Do not edit.
+
+tcgen05.shift.cta_group::1.down
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.shift.cta_group.down [taddr]; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void tcgen05_shift_down(
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     uint32_t taddr);
+
+tcgen05.shift.cta_group::2.down
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.shift.cta_group.down [taddr]; // PTX ISA 86, SM_100a, SM_101a
+   // .cta_group = { .cta_group::1, .cta_group::2 }
+   template <cuda::ptx::dot_cta_group Cta_Group>
+   __device__ static inline void tcgen05_shift_down(
+     cuda::ptx::cta_group_t<Cta_Group> cta_group,
+     uint32_t taddr);
diff --git a/docs/libcudacxx/ptx/instructions/generated/tcgen05_st.rst b/docs/libcudacxx/ptx/instructions/generated/tcgen05_st.rst
new file mode 100644
index 00000000000..3147a1757d8
--- /dev/null
+++ b/docs/libcudacxx/ptx/instructions/generated/tcgen05_st.rst
@@ -0,0 +1,758 @@
+..
+   This file was automatically generated. Do not edit.
+
+tcgen05.st.sync.aligned.16x64b.x1.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.st.sync.aligned.16x64b.x1.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_101a
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+   __device__ static inline void tcgen05_st_16x64b(
+     uint32_t taddr,
+     const B32 (&values)[1]);
+
+tcgen05.st.sync.aligned.16x64b.x1.unpack::16b.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.st.sync.aligned.16x64b.x1.unpack::16b.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_101a
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+   __device__ static inline void tcgen05_st_16x64b_unpack_16b(
+     uint32_t taddr,
+     const B32 (&values)[1]);
+
+tcgen05.st.sync.aligned.16x64b.x2.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.st.sync.aligned.16x64b.x2.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_101a
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+   __device__ static inline void tcgen05_st_16x64b(
+     uint32_t taddr,
+     const B32 (&values)[2]);
+
+tcgen05.st.sync.aligned.16x64b.x2.unpack::16b.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.st.sync.aligned.16x64b.x2.unpack::16b.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_101a
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+   __device__ static inline void tcgen05_st_16x64b_unpack_16b(
+     uint32_t taddr,
+     const B32 (&values)[2]);
+
+tcgen05.st.sync.aligned.16x64b.x4.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.st.sync.aligned.16x64b.x4.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_101a
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+   __device__ static inline void tcgen05_st_16x64b(
+     uint32_t taddr,
+     const B32 (&values)[4]);
+
+tcgen05.st.sync.aligned.16x64b.x4.unpack::16b.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.st.sync.aligned.16x64b.x4.unpack::16b.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_101a
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+   __device__ static inline void tcgen05_st_16x64b_unpack_16b(
+     uint32_t taddr,
+     const B32 (&values)[4]);
+
+tcgen05.st.sync.aligned.16x64b.x8.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.st.sync.aligned.16x64b.x8.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_101a
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+   __device__ static inline void tcgen05_st_16x64b(
+     uint32_t taddr,
+     const B32 (&values)[8]);
+
+tcgen05.st.sync.aligned.16x64b.x8.unpack::16b.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.st.sync.aligned.16x64b.x8.unpack::16b.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_101a
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+   __device__ static inline void tcgen05_st_16x64b_unpack_16b(
+     uint32_t taddr,
+     const B32 (&values)[8]);
+
+tcgen05.st.sync.aligned.16x64b.x16.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.st.sync.aligned.16x64b.x16.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_101a
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+   __device__ static inline void tcgen05_st_16x64b(
+     uint32_t taddr,
+     const B32 (&values)[16]);
+
+tcgen05.st.sync.aligned.16x64b.x16.unpack::16b.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.st.sync.aligned.16x64b.x16.unpack::16b.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_101a
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+   __device__ static inline void tcgen05_st_16x64b_unpack_16b(
+     uint32_t taddr,
+     const B32 (&values)[16]);
+
+tcgen05.st.sync.aligned.16x64b.x32.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.st.sync.aligned.16x64b.x32.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_101a
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+   __device__ static inline void tcgen05_st_16x64b(
+     uint32_t taddr,
+     const B32 (&values)[32]);
+
+tcgen05.st.sync.aligned.16x64b.x32.unpack::16b.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.st.sync.aligned.16x64b.x32.unpack::16b.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_101a
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+   __device__ static inline void tcgen05_st_16x64b_unpack_16b(
+     uint32_t taddr,
+     const B32 (&values)[32]);
+
+tcgen05.st.sync.aligned.16x64b.x64.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.st.sync.aligned.16x64b.x64.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_101a
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+   __device__ static inline void tcgen05_st_16x64b(
+     uint32_t taddr,
+     const B32 (&values)[64]);
+
+tcgen05.st.sync.aligned.16x64b.x64.unpack::16b.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.st.sync.aligned.16x64b.x64.unpack::16b.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_101a
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+   __device__ static inline void tcgen05_st_16x64b_unpack_16b(
+     uint32_t taddr,
+     const B32 (&values)[64]);
+
+tcgen05.st.sync.aligned.16x64b.x128.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.st.sync.aligned.16x64b.x128.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_101a
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+   __device__ static inline void tcgen05_st_16x64b(
+     uint32_t taddr,
+     const B32 (&values)[128]);
+
+tcgen05.st.sync.aligned.16x64b.x128.unpack::16b.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.st.sync.aligned.16x64b.x128.unpack::16b.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_101a
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+   __device__ static inline void tcgen05_st_16x64b_unpack_16b(
+     uint32_t taddr,
+     const B32 (&values)[128]);
+
+tcgen05.st.sync.aligned.16x128b.x1.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.st.sync.aligned.16x128b.x1.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_101a
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+   __device__ static inline void tcgen05_st_16x128b(
+     uint32_t taddr,
+     const B32 (&values)[2]);
+
+tcgen05.st.sync.aligned.16x128b.x1.unpack::16b.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.st.sync.aligned.16x128b.x1.unpack::16b.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_101a
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+   __device__ static inline void tcgen05_st_16x128b_unpack_16b(
+     uint32_t taddr,
+     const B32 (&values)[2]);
+
+tcgen05.st.sync.aligned.16x128b.x2.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.st.sync.aligned.16x128b.x2.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_101a
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+   __device__ static inline void tcgen05_st_16x128b(
+     uint32_t taddr,
+     const B32 (&values)[4]);
+
+tcgen05.st.sync.aligned.16x128b.x2.unpack::16b.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.st.sync.aligned.16x128b.x2.unpack::16b.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_101a
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+   __device__ static inline void tcgen05_st_16x128b_unpack_16b(
+     uint32_t taddr,
+     const B32 (&values)[4]);
+
+tcgen05.st.sync.aligned.16x128b.x4.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.st.sync.aligned.16x128b.x4.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_101a
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+   __device__ static inline void tcgen05_st_16x128b(
+     uint32_t taddr,
+     const B32 (&values)[8]);
+
+tcgen05.st.sync.aligned.16x128b.x4.unpack::16b.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.st.sync.aligned.16x128b.x4.unpack::16b.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_101a
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+   __device__ static inline void tcgen05_st_16x128b_unpack_16b(
+     uint32_t taddr,
+     const B32 (&values)[8]);
+
+tcgen05.st.sync.aligned.16x128b.x8.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.st.sync.aligned.16x128b.x8.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_101a
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+   __device__ static inline void tcgen05_st_16x128b(
+     uint32_t taddr,
+     const B32 (&values)[16]);
+
+tcgen05.st.sync.aligned.16x128b.x8.unpack::16b.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.st.sync.aligned.16x128b.x8.unpack::16b.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_101a
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+   __device__ static inline void tcgen05_st_16x128b_unpack_16b(
+     uint32_t taddr,
+     const B32 (&values)[16]);
+
+tcgen05.st.sync.aligned.16x128b.x16.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.st.sync.aligned.16x128b.x16.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_101a
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+   __device__ static inline void tcgen05_st_16x128b(
+     uint32_t taddr,
+     const B32 (&values)[32]);
+
+tcgen05.st.sync.aligned.16x128b.x16.unpack::16b.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.st.sync.aligned.16x128b.x16.unpack::16b.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_101a
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+   __device__ static inline void tcgen05_st_16x128b_unpack_16b(
+     uint32_t taddr,
+     const B32 (&values)[32]);
+
+tcgen05.st.sync.aligned.16x128b.x32.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.st.sync.aligned.16x128b.x32.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_101a
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+   __device__ static inline void tcgen05_st_16x128b(
+     uint32_t taddr,
+     const B32 (&values)[64]);
+
+tcgen05.st.sync.aligned.16x128b.x32.unpack::16b.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.st.sync.aligned.16x128b.x32.unpack::16b.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_101a
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+   __device__ static inline void tcgen05_st_16x128b_unpack_16b(
+     uint32_t taddr,
+     const B32 (&values)[64]);
+
+tcgen05.st.sync.aligned.16x128b.x64.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.st.sync.aligned.16x128b.x64.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_101a
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+   __device__ static inline void tcgen05_st_16x128b(
+     uint32_t taddr,
+     const B32 (&values)[128]);
+
+tcgen05.st.sync.aligned.16x128b.x64.unpack::16b.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.st.sync.aligned.16x128b.x64.unpack::16b.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_101a
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+   __device__ static inline void tcgen05_st_16x128b_unpack_16b(
+     uint32_t taddr,
+     const B32 (&values)[128]);
+
+tcgen05.st.sync.aligned.16x256b.x1.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.st.sync.aligned.16x256b.x1.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_101a
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+   __device__ static inline void tcgen05_st_16x256b(
+     uint32_t taddr,
+     const B32 (&values)[4]);
+
+tcgen05.st.sync.aligned.16x256b.x1.unpack::16b.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.st.sync.aligned.16x256b.x1.unpack::16b.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_101a
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+   __device__ static inline void tcgen05_st_16x256b_unpack_16b(
+     uint32_t taddr,
+     const B32 (&values)[4]);
+
+tcgen05.st.sync.aligned.16x256b.x2.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.st.sync.aligned.16x256b.x2.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_101a
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+   __device__ static inline void tcgen05_st_16x256b(
+     uint32_t taddr,
+     const B32 (&values)[8]);
+
+tcgen05.st.sync.aligned.16x256b.x2.unpack::16b.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.st.sync.aligned.16x256b.x2.unpack::16b.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_101a
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+   __device__ static inline void tcgen05_st_16x256b_unpack_16b(
+     uint32_t taddr,
+     const B32 (&values)[8]);
+
+tcgen05.st.sync.aligned.16x256b.x4.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.st.sync.aligned.16x256b.x4.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_101a
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+   __device__ static inline void tcgen05_st_16x256b(
+     uint32_t taddr,
+     const B32 (&values)[16]);
+
+tcgen05.st.sync.aligned.16x256b.x4.unpack::16b.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.st.sync.aligned.16x256b.x4.unpack::16b.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_101a
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+   __device__ static inline void tcgen05_st_16x256b_unpack_16b(
+     uint32_t taddr,
+     const B32 (&values)[16]);
+
+tcgen05.st.sync.aligned.16x256b.x8.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.st.sync.aligned.16x256b.x8.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_101a
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+   __device__ static inline void tcgen05_st_16x256b(
+     uint32_t taddr,
+     const B32 (&values)[32]);
+
+tcgen05.st.sync.aligned.16x256b.x8.unpack::16b.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.st.sync.aligned.16x256b.x8.unpack::16b.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_101a
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+   __device__ static inline void tcgen05_st_16x256b_unpack_16b(
+     uint32_t taddr,
+     const B32 (&values)[32]);
+
+tcgen05.st.sync.aligned.16x256b.x16.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.st.sync.aligned.16x256b.x16.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_101a
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+   __device__ static inline void tcgen05_st_16x256b(
+     uint32_t taddr,
+     const B32 (&values)[64]);
+
+tcgen05.st.sync.aligned.16x256b.x16.unpack::16b.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.st.sync.aligned.16x256b.x16.unpack::16b.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_101a
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+   __device__ static inline void tcgen05_st_16x256b_unpack_16b(
+     uint32_t taddr,
+     const B32 (&values)[64]);
+
+tcgen05.st.sync.aligned.16x256b.x32.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.st.sync.aligned.16x256b.x32.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_101a
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+   __device__ static inline void tcgen05_st_16x256b(
+     uint32_t taddr,
+     const B32 (&values)[128]);
+
+tcgen05.st.sync.aligned.16x256b.x32.unpack::16b.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.st.sync.aligned.16x256b.x32.unpack::16b.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_101a
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+   __device__ static inline void tcgen05_st_16x256b_unpack_16b(
+     uint32_t taddr,
+     const B32 (&values)[128]);
+
+tcgen05.st.sync.aligned.32x32b.x1.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.st.sync.aligned.32x32b.x1.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_101a
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+   __device__ static inline void tcgen05_st_32x32b(
+     uint32_t taddr,
+     const B32 (&values)[1]);
+
+tcgen05.st.sync.aligned.32x32b.x1.unpack::16b.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.st.sync.aligned.32x32b.x1.unpack::16b.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_101a
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+   __device__ static inline void tcgen05_st_32x32b_unpack_16b(
+     uint32_t taddr,
+     const B32 (&values)[1]);
+
+tcgen05.st.sync.aligned.32x32b.x2.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.st.sync.aligned.32x32b.x2.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_101a
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+   __device__ static inline void tcgen05_st_32x32b(
+     uint32_t taddr,
+     const B32 (&values)[2]);
+
+tcgen05.st.sync.aligned.32x32b.x2.unpack::16b.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.st.sync.aligned.32x32b.x2.unpack::16b.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_101a
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+   __device__ static inline void tcgen05_st_32x32b_unpack_16b(
+     uint32_t taddr,
+     const B32 (&values)[2]);
+
+tcgen05.st.sync.aligned.32x32b.x4.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.st.sync.aligned.32x32b.x4.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_101a
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+   __device__ static inline void tcgen05_st_32x32b(
+     uint32_t taddr,
+     const B32 (&values)[4]);
+
+tcgen05.st.sync.aligned.32x32b.x4.unpack::16b.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.st.sync.aligned.32x32b.x4.unpack::16b.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_101a
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+   __device__ static inline void tcgen05_st_32x32b_unpack_16b(
+     uint32_t taddr,
+     const B32 (&values)[4]);
+
+tcgen05.st.sync.aligned.32x32b.x8.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.st.sync.aligned.32x32b.x8.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_101a
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+   __device__ static inline void tcgen05_st_32x32b(
+     uint32_t taddr,
+     const B32 (&values)[8]);
+
+tcgen05.st.sync.aligned.32x32b.x8.unpack::16b.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.st.sync.aligned.32x32b.x8.unpack::16b.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_101a
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+   __device__ static inline void tcgen05_st_32x32b_unpack_16b(
+     uint32_t taddr,
+     const B32 (&values)[8]);
+
+tcgen05.st.sync.aligned.32x32b.x16.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.st.sync.aligned.32x32b.x16.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_101a
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+   __device__ static inline void tcgen05_st_32x32b(
+     uint32_t taddr,
+     const B32 (&values)[16]);
+
+tcgen05.st.sync.aligned.32x32b.x16.unpack::16b.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.st.sync.aligned.32x32b.x16.unpack::16b.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_101a
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+   __device__ static inline void tcgen05_st_32x32b_unpack_16b(
+     uint32_t taddr,
+     const B32 (&values)[16]);
+
+tcgen05.st.sync.aligned.32x32b.x32.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.st.sync.aligned.32x32b.x32.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_101a
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+   __device__ static inline void tcgen05_st_32x32b(
+     uint32_t taddr,
+     const B32 (&values)[32]);
+
+tcgen05.st.sync.aligned.32x32b.x32.unpack::16b.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.st.sync.aligned.32x32b.x32.unpack::16b.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_101a
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+   __device__ static inline void tcgen05_st_32x32b_unpack_16b(
+     uint32_t taddr,
+     const B32 (&values)[32]);
+
+tcgen05.st.sync.aligned.32x32b.x64.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.st.sync.aligned.32x32b.x64.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_101a
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+   __device__ static inline void tcgen05_st_32x32b(
+     uint32_t taddr,
+     const B32 (&values)[64]);
+
+tcgen05.st.sync.aligned.32x32b.x64.unpack::16b.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.st.sync.aligned.32x32b.x64.unpack::16b.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_101a
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+   __device__ static inline void tcgen05_st_32x32b_unpack_16b(
+     uint32_t taddr,
+     const B32 (&values)[64]);
+
+tcgen05.st.sync.aligned.32x32b.x128.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.st.sync.aligned.32x32b.x128.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_101a
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+   __device__ static inline void tcgen05_st_32x32b(
+     uint32_t taddr,
+     const B32 (&values)[128]);
+
+tcgen05.st.sync.aligned.32x32b.x128.unpack::16b.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.st.sync.aligned.32x32b.x128.unpack::16b.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_101a
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+   __device__ static inline void tcgen05_st_32x32b_unpack_16b(
+     uint32_t taddr,
+     const B32 (&values)[128]);
+
+tcgen05.st.sync.aligned.16x32bx2.x1.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.st.sync.aligned.16x32bx2.x1.b32 [taddr], immHalfSplitoff, values; // PTX ISA 86, SM_100a, SM_101a
+   template <int N32, typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+   __device__ static inline void tcgen05_st_16x32bx2(
+     uint32_t taddr,
+     cuda::ptx::n32_t<N32> immHalfSplitoff,
+     const B32 (&values)[1]);
+
+tcgen05.st.sync.aligned.16x32bx2.x1.unpack::16b.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.st.sync.aligned.16x32bx2.x1.unpack::16b.b32 [taddr], immHalfSplitoff, values; // PTX ISA 86, SM_100a, SM_101a
+   template <int N32, typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+   __device__ static inline void tcgen05_st_16x32bx2_unpack_16b(
+     uint32_t taddr,
+     cuda::ptx::n32_t<N32> immHalfSplitoff,
+     const B32 (&values)[1]);
+
+tcgen05.st.sync.aligned.16x32bx2.x2.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.st.sync.aligned.16x32bx2.x2.b32 [taddr], immHalfSplitoff, values; // PTX ISA 86, SM_100a, SM_101a
+   template <int N32, typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+   __device__ static inline void tcgen05_st_16x32bx2(
+     uint32_t taddr,
+     cuda::ptx::n32_t<N32> immHalfSplitoff,
+     const B32 (&values)[2]);
+
+tcgen05.st.sync.aligned.16x32bx2.x2.unpack::16b.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.st.sync.aligned.16x32bx2.x2.unpack::16b.b32 [taddr], immHalfSplitoff, values; // PTX ISA 86, SM_100a, SM_101a
+   template <int N32, typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+   __device__ static inline void tcgen05_st_16x32bx2_unpack_16b(
+     uint32_t taddr,
+     cuda::ptx::n32_t<N32> immHalfSplitoff,
+     const B32 (&values)[2]);
+
+tcgen05.st.sync.aligned.16x32bx2.x4.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.st.sync.aligned.16x32bx2.x4.b32 [taddr], immHalfSplitoff, values; // PTX ISA 86, SM_100a, SM_101a
+   template <int N32, typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+   __device__ static inline void tcgen05_st_16x32bx2(
+     uint32_t taddr,
+     cuda::ptx::n32_t<N32> immHalfSplitoff,
+     const B32 (&values)[4]);
+
+tcgen05.st.sync.aligned.16x32bx2.x4.unpack::16b.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.st.sync.aligned.16x32bx2.x4.unpack::16b.b32 [taddr], immHalfSplitoff, values; // PTX ISA 86, SM_100a, SM_101a
+   template <int N32, typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+   __device__ static inline void tcgen05_st_16x32bx2_unpack_16b(
+     uint32_t taddr,
+     cuda::ptx::n32_t<N32> immHalfSplitoff,
+     const B32 (&values)[4]);
+
+tcgen05.st.sync.aligned.16x32bx2.x8.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.st.sync.aligned.16x32bx2.x8.b32 [taddr], immHalfSplitoff, values; // PTX ISA 86, SM_100a, SM_101a
+   template <int N32, typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+   __device__ static inline void tcgen05_st_16x32bx2(
+     uint32_t taddr,
+     cuda::ptx::n32_t<N32> immHalfSplitoff,
+     const B32 (&values)[8]);
+
+tcgen05.st.sync.aligned.16x32bx2.x8.unpack::16b.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.st.sync.aligned.16x32bx2.x8.unpack::16b.b32 [taddr], immHalfSplitoff, values; // PTX ISA 86, SM_100a, SM_101a
+   template <int N32, typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+   __device__ static inline void tcgen05_st_16x32bx2_unpack_16b(
+     uint32_t taddr,
+     cuda::ptx::n32_t<N32> immHalfSplitoff,
+     const B32 (&values)[8]);
+
+tcgen05.st.sync.aligned.16x32bx2.x16.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.st.sync.aligned.16x32bx2.x16.b32 [taddr], immHalfSplitoff, values; // PTX ISA 86, SM_100a, SM_101a
+   template <int N32, typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+   __device__ static inline void tcgen05_st_16x32bx2(
+     uint32_t taddr,
+     cuda::ptx::n32_t<N32> immHalfSplitoff,
+     const B32 (&values)[16]);
+
+tcgen05.st.sync.aligned.16x32bx2.x16.unpack::16b.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.st.sync.aligned.16x32bx2.x16.unpack::16b.b32 [taddr], immHalfSplitoff, values; // PTX ISA 86, SM_100a, SM_101a
+   template <int N32, typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+   __device__ static inline void tcgen05_st_16x32bx2_unpack_16b(
+     uint32_t taddr,
+     cuda::ptx::n32_t<N32> immHalfSplitoff,
+     const B32 (&values)[16]);
+
+tcgen05.st.sync.aligned.16x32bx2.x32.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.st.sync.aligned.16x32bx2.x32.b32 [taddr], immHalfSplitoff, values; // PTX ISA 86, SM_100a, SM_101a
+   template <int N32, typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+   __device__ static inline void tcgen05_st_16x32bx2(
+     uint32_t taddr,
+     cuda::ptx::n32_t<N32> immHalfSplitoff,
+     const B32 (&values)[32]);
+
+tcgen05.st.sync.aligned.16x32bx2.x32.unpack::16b.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.st.sync.aligned.16x32bx2.x32.unpack::16b.b32 [taddr], immHalfSplitoff, values; // PTX ISA 86, SM_100a, SM_101a
+   template <int N32, typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+   __device__ static inline void tcgen05_st_16x32bx2_unpack_16b(
+     uint32_t taddr,
+     cuda::ptx::n32_t<N32> immHalfSplitoff,
+     const B32 (&values)[32]);
+
+tcgen05.st.sync.aligned.16x32bx2.x64.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.st.sync.aligned.16x32bx2.x64.b32 [taddr], immHalfSplitoff, values; // PTX ISA 86, SM_100a, SM_101a
+   template <int N32, typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+   __device__ static inline void tcgen05_st_16x32bx2(
+     uint32_t taddr,
+     cuda::ptx::n32_t<N32> immHalfSplitoff,
+     const B32 (&values)[64]);
+
+tcgen05.st.sync.aligned.16x32bx2.x64.unpack::16b.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.st.sync.aligned.16x32bx2.x64.unpack::16b.b32 [taddr], immHalfSplitoff, values; // PTX ISA 86, SM_100a, SM_101a
+   template <int N32, typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+   __device__ static inline void tcgen05_st_16x32bx2_unpack_16b(
+     uint32_t taddr,
+     cuda::ptx::n32_t<N32> immHalfSplitoff,
+     const B32 (&values)[64]);
+
+tcgen05.st.sync.aligned.16x32bx2.x128.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.st.sync.aligned.16x32bx2.x128.b32 [taddr], immHalfSplitoff, values; // PTX ISA 86, SM_100a, SM_101a
+   template <int N32, typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+   __device__ static inline void tcgen05_st_16x32bx2(
+     uint32_t taddr,
+     cuda::ptx::n32_t<N32> immHalfSplitoff,
+     const B32 (&values)[128]);
+
+tcgen05.st.sync.aligned.16x32bx2.x128.unpack::16b.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.st.sync.aligned.16x32bx2.x128.unpack::16b.b32 [taddr], immHalfSplitoff, values; // PTX ISA 86, SM_100a, SM_101a
+   template <int N32, typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+   __device__ static inline void tcgen05_st_16x32bx2_unpack_16b(
+     uint32_t taddr,
+     cuda::ptx::n32_t<N32> immHalfSplitoff,
+     const B32 (&values)[128]);
diff --git a/docs/libcudacxx/ptx/instructions/generated/tcgen05_wait.rst b/docs/libcudacxx/ptx/instructions/generated/tcgen05_wait.rst
new file mode 100644
index 00000000000..ec48818eecc
--- /dev/null
+++ b/docs/libcudacxx/ptx/instructions/generated/tcgen05_wait.rst
@@ -0,0 +1,18 @@
+..
+   This file was automatically generated. Do not edit.
+
+tcgen05.wait::ld.sync.aligned
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.wait::ld.sync.aligned; // PTX ISA 86, SM_100a, SM_101a
+   template <typename = void>
+   __device__ static inline void tcgen05_wait_ld();
+
+tcgen05.wait::st.sync.aligned
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tcgen05.wait::st.sync.aligned; // PTX ISA 86, SM_100a, SM_101a
+   template <typename = void>
+   __device__ static inline void tcgen05_wait_st();
diff --git a/docs/libcudacxx/ptx/instructions/generated/tensormap_replace.rst b/docs/libcudacxx/ptx/instructions/generated/tensormap_replace.rst
index a8c4a260782..fbf010d6009 100644
--- a/docs/libcudacxx/ptx/instructions/generated/tensormap_replace.rst
+++ b/docs/libcudacxx/ptx/instructions/generated/tensormap_replace.rst
@@ -5,9 +5,9 @@ tensormap.replace.tile.global_address.global.b1024.b64
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 .. code:: cuda
 
-   // tensormap.replace.tile.global_address.space.b1024.b64    [tm_addr], new_val; // PTX ISA 83, SM_90a
+   // tensormap.replace.tile.global_address.space.b1024.b64 [tm_addr], new_val; // PTX ISA 83, SM_90a, SM_100a, SM_101a
    // .space     = { .global }
-   template <typename B64>
+   template <typename B64, enable_if_t<sizeof(B64) == 8, bool> = true>
    __device__ static inline void tensormap_replace_global_address(
      cuda::ptx::space_global_t,
      void* tm_addr,
@@ -17,9 +17,9 @@ tensormap.replace.tile.global_address.shared::cta.b1024.b64
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 .. code:: cuda
 
-   // tensormap.replace.tile.global_address.space.b1024.b64    [tm_addr], new_val; // PTX ISA 83, SM_90a
+   // tensormap.replace.tile.global_address.space.b1024.b64 [tm_addr], new_val; // PTX ISA 83, SM_90a, SM_100a, SM_101a
    // .space     = { .shared::cta }
-   template <typename B64>
+   template <typename B64, enable_if_t<sizeof(B64) == 8, bool> = true>
    __device__ static inline void tensormap_replace_global_address(
      cuda::ptx::space_shared_t,
      void* tm_addr,
@@ -29,9 +29,9 @@ tensormap.replace.tile.rank.global.b1024.b32
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 .. code:: cuda
 
-   // tensormap.replace.tile.rank.space.b1024.b32              [tm_addr], new_val; // PTX ISA 83, SM_90a
+   // tensormap.replace.tile.rank.space.b1024.b32 [tm_addr], new_val; // PTX ISA 83, SM_90a, SM_100a, SM_101a
    // .space     = { .global }
-   template <typename B32>
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
    __device__ static inline void tensormap_replace_rank(
      cuda::ptx::space_global_t,
      void* tm_addr,
@@ -41,9 +41,9 @@ tensormap.replace.tile.rank.shared::cta.b1024.b32
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 .. code:: cuda
 
-   // tensormap.replace.tile.rank.space.b1024.b32              [tm_addr], new_val; // PTX ISA 83, SM_90a
+   // tensormap.replace.tile.rank.space.b1024.b32 [tm_addr], new_val; // PTX ISA 83, SM_90a, SM_100a, SM_101a
    // .space     = { .shared::cta }
-   template <typename B32>
+   template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
    __device__ static inline void tensormap_replace_rank(
      cuda::ptx::space_shared_t,
      void* tm_addr,
@@ -53,9 +53,9 @@ tensormap.replace.tile.box_dim.global.b1024.b32
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 .. code:: cuda
 
-   // tensormap.replace.tile.box_dim.space.b1024.b32           [tm_addr], ord, new_val; // PTX ISA 83, SM_90a
+   // tensormap.replace.tile.box_dim.space.b1024.b32 [tm_addr], ord, new_val; // PTX ISA 83, SM_90a, SM_100a, SM_101a
    // .space     = { .global }
-   template <int N32, typename B32>
+   template <int N32, typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
    __device__ static inline void tensormap_replace_box_dim(
      cuda::ptx::space_global_t,
      void* tm_addr,
@@ -66,9 +66,9 @@ tensormap.replace.tile.box_dim.shared::cta.b1024.b32
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 .. code:: cuda
 
-   // tensormap.replace.tile.box_dim.space.b1024.b32           [tm_addr], ord, new_val; // PTX ISA 83, SM_90a
+   // tensormap.replace.tile.box_dim.space.b1024.b32 [tm_addr], ord, new_val; // PTX ISA 83, SM_90a, SM_100a, SM_101a
    // .space     = { .shared::cta }
-   template <int N32, typename B32>
+   template <int N32, typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
    __device__ static inline void tensormap_replace_box_dim(
      cuda::ptx::space_shared_t,
      void* tm_addr,
@@ -79,9 +79,9 @@ tensormap.replace.tile.global_dim.global.b1024.b32
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 .. code:: cuda
 
-   // tensormap.replace.tile.global_dim.space.b1024.b32        [tm_addr], ord, new_val; // PTX ISA 83, SM_90a
+   // tensormap.replace.tile.global_dim.space.b1024.b32 [tm_addr], ord, new_val; // PTX ISA 83, SM_90a, SM_100a, SM_101a
    // .space     = { .global }
-   template <int N32, typename B32>
+   template <int N32, typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
    __device__ static inline void tensormap_replace_global_dim(
      cuda::ptx::space_global_t,
      void* tm_addr,
@@ -92,9 +92,9 @@ tensormap.replace.tile.global_dim.shared::cta.b1024.b32
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 .. code:: cuda
 
-   // tensormap.replace.tile.global_dim.space.b1024.b32        [tm_addr], ord, new_val; // PTX ISA 83, SM_90a
+   // tensormap.replace.tile.global_dim.space.b1024.b32 [tm_addr], ord, new_val; // PTX ISA 83, SM_90a, SM_100a, SM_101a
    // .space     = { .shared::cta }
-   template <int N32, typename B32>
+   template <int N32, typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
    __device__ static inline void tensormap_replace_global_dim(
      cuda::ptx::space_shared_t,
      void* tm_addr,
@@ -105,9 +105,9 @@ tensormap.replace.tile.global_stride.global.b1024.b64
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 .. code:: cuda
 
-   // tensormap.replace.tile.global_stride.space.b1024.b64     [tm_addr], ord, new_val; // PTX ISA 83, SM_90a
+   // tensormap.replace.tile.global_stride.space.b1024.b64 [tm_addr], ord, new_val; // PTX ISA 83, SM_90a, SM_100a, SM_101a
    // .space     = { .global }
-   template <int N32, typename B64>
+   template <int N32, typename B64, enable_if_t<sizeof(B64) == 8, bool> = true>
    __device__ static inline void tensormap_replace_global_stride(
      cuda::ptx::space_global_t,
      void* tm_addr,
@@ -118,9 +118,9 @@ tensormap.replace.tile.global_stride.shared::cta.b1024.b64
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 .. code:: cuda
 
-   // tensormap.replace.tile.global_stride.space.b1024.b64     [tm_addr], ord, new_val; // PTX ISA 83, SM_90a
+   // tensormap.replace.tile.global_stride.space.b1024.b64 [tm_addr], ord, new_val; // PTX ISA 83, SM_90a, SM_100a, SM_101a
    // .space     = { .shared::cta }
-   template <int N32, typename B64>
+   template <int N32, typename B64, enable_if_t<sizeof(B64) == 8, bool> = true>
    __device__ static inline void tensormap_replace_global_stride(
      cuda::ptx::space_shared_t,
      void* tm_addr,
@@ -131,9 +131,35 @@ tensormap.replace.tile.element_stride.global.b1024.b32
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 .. code:: cuda
 
-   // tensormap.replace.tile.element_stride.space.b1024.b32    [tm_addr], ord, new_val; // PTX ISA 83, SM_90a
+   // tensormap.replace.tile.element_stride.space.b1024.b32 [tm_addr], ord, new_val; // PTX ISA 83, SM_90a, SM_100a, SM_101a
    // .space     = { .global }
-   template <int N32, typename B32>
+   template <int N32, typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+   __device__ static inline void tensormap_replace_element_stride(
+     cuda::ptx::space_global_t,
+     void* tm_addr,
+     cuda::ptx::n32_t<N32> ord,
+     B32 new_val);
+
+tensormap.replace.tile.element_stride.shared::cta.b1024.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tensormap.replace.tile.element_stride.space.b1024.b32 [tm_addr], ord, new_val; // PTX ISA 83, SM_90a, SM_100a, SM_101a
+   // .space     = { .shared::cta }
+   template <int N32, typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+   __device__ static inline void tensormap_replace_element_stride(
+     cuda::ptx::space_shared_t,
+     void* tm_addr,
+     cuda::ptx::n32_t<N32> ord,
+     B32 new_val);
+
+tensormap.replace.tile.element_stride.global.b1024.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tensormap.replace.tile.element_stride.space.b1024.b32 [tm_addr], ord, new_val; // PTX ISA 83, SM_90a, SM_100a, SM_101a
+   // .space     = { .global }
+   template <int N32, typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
    __device__ static inline void tensormap_replace_element_size(
      cuda::ptx::space_global_t,
      void* tm_addr,
@@ -144,9 +170,9 @@ tensormap.replace.tile.element_stride.shared::cta.b1024.b32
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 .. code:: cuda
 
-   // tensormap.replace.tile.element_stride.space.b1024.b32    [tm_addr], ord, new_val; // PTX ISA 83, SM_90a
+   // tensormap.replace.tile.element_stride.space.b1024.b32 [tm_addr], ord, new_val; // PTX ISA 83, SM_90a, SM_100a, SM_101a
    // .space     = { .shared::cta }
-   template <int N32, typename B32>
+   template <int N32, typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
    __device__ static inline void tensormap_replace_element_size(
      cuda::ptx::space_shared_t,
      void* tm_addr,
@@ -157,7 +183,7 @@ tensormap.replace.tile.elemtype.global.b1024.b32
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 .. code:: cuda
 
-   // tensormap.replace.tile.elemtype.space.b1024.b32          [tm_addr], new_val; // PTX ISA 83, SM_90a
+   // tensormap.replace.tile.elemtype.space.b1024.b32 [tm_addr], new_val; // PTX ISA 83, SM_90a, SM_100a, SM_101a
    // .space     = { .global }
    template <int N32>
    __device__ static inline void tensormap_replace_elemtype(
@@ -169,7 +195,7 @@ tensormap.replace.tile.elemtype.shared::cta.b1024.b32
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 .. code:: cuda
 
-   // tensormap.replace.tile.elemtype.space.b1024.b32          [tm_addr], new_val; // PTX ISA 83, SM_90a
+   // tensormap.replace.tile.elemtype.space.b1024.b32 [tm_addr], new_val; // PTX ISA 83, SM_90a, SM_100a, SM_101a
    // .space     = { .shared::cta }
    template <int N32>
    __device__ static inline void tensormap_replace_elemtype(
@@ -181,7 +207,7 @@ tensormap.replace.tile.interleave_layout.global.b1024.b32
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 .. code:: cuda
 
-   // tensormap.replace.tile.interleave_layout.space.b1024.b32 [tm_addr], new_val; // PTX ISA 83, SM_90a
+   // tensormap.replace.tile.interleave_layout.space.b1024.b32 [tm_addr], new_val; // PTX ISA 83, SM_90a, SM_100a, SM_101a
    // .space     = { .global }
    template <int N32>
    __device__ static inline void tensormap_replace_interleave_layout(
@@ -193,7 +219,7 @@ tensormap.replace.tile.interleave_layout.shared::cta.b1024.b32
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 .. code:: cuda
 
-   // tensormap.replace.tile.interleave_layout.space.b1024.b32 [tm_addr], new_val; // PTX ISA 83, SM_90a
+   // tensormap.replace.tile.interleave_layout.space.b1024.b32 [tm_addr], new_val; // PTX ISA 83, SM_90a, SM_100a, SM_101a
    // .space     = { .shared::cta }
    template <int N32>
    __device__ static inline void tensormap_replace_interleave_layout(
@@ -205,7 +231,7 @@ tensormap.replace.tile.swizzle_mode.global.b1024.b32
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 .. code:: cuda
 
-   // tensormap.replace.tile.swizzle_mode.space.b1024.b32      [tm_addr], new_val; // PTX ISA 83, SM_90a
+   // tensormap.replace.tile.swizzle_mode.space.b1024.b32 [tm_addr], new_val; // PTX ISA 83, SM_90a, SM_100a, SM_101a
    // .space     = { .global }
    template <int N32>
    __device__ static inline void tensormap_replace_swizzle_mode(
@@ -217,7 +243,7 @@ tensormap.replace.tile.swizzle_mode.shared::cta.b1024.b32
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 .. code:: cuda
 
-   // tensormap.replace.tile.swizzle_mode.space.b1024.b32      [tm_addr], new_val; // PTX ISA 83, SM_90a
+   // tensormap.replace.tile.swizzle_mode.space.b1024.b32 [tm_addr], new_val; // PTX ISA 83, SM_90a, SM_100a, SM_101a
    // .space     = { .shared::cta }
    template <int N32>
    __device__ static inline void tensormap_replace_swizzle_mode(
@@ -229,7 +255,7 @@ tensormap.replace.tile.fill_mode.global.b1024.b32
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 .. code:: cuda
 
-   // tensormap.replace.tile.fill_mode.space.b1024.b32         [tm_addr], new_val; // PTX ISA 83, SM_90a
+   // tensormap.replace.tile.fill_mode.space.b1024.b32 [tm_addr], new_val; // PTX ISA 83, SM_90a, SM_100a, SM_101a
    // .space     = { .global }
    template <int N32>
    __device__ static inline void tensormap_replace_fill_mode(
@@ -241,10 +267,34 @@ tensormap.replace.tile.fill_mode.shared::cta.b1024.b32
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 .. code:: cuda
 
-   // tensormap.replace.tile.fill_mode.space.b1024.b32         [tm_addr], new_val; // PTX ISA 83, SM_90a
+   // tensormap.replace.tile.fill_mode.space.b1024.b32 [tm_addr], new_val; // PTX ISA 83, SM_90a, SM_100a, SM_101a
    // .space     = { .shared::cta }
    template <int N32>
    __device__ static inline void tensormap_replace_fill_mode(
      cuda::ptx::space_shared_t,
      void* tm_addr,
      cuda::ptx::n32_t<N32> new_val);
+
+tensormap.replace.tile.swizzle_atomicity.global.b1024.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tensormap.replace.tile.swizzle_atomicity.space.b1024.b32 [tm_addr], new_val; // PTX ISA 86, SM_100a, SM_101a
+   // .space     = { .global }
+   template <int N32>
+   __device__ static inline void tensormap_replace_swizzle_atomicity(
+     cuda::ptx::space_global_t,
+     void* tm_addr,
+     cuda::ptx::n32_t<N32> new_val);
+
+tensormap.replace.tile.swizzle_atomicity.shared::cta.b1024.b32
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code:: cuda
+
+   // tensormap.replace.tile.swizzle_atomicity.space.b1024.b32 [tm_addr], new_val; // PTX ISA 86, SM_100a, SM_101a
+   // .space     = { .shared::cta }
+   template <int N32>
+   __device__ static inline void tensormap_replace_swizzle_atomicity(
+     cuda::ptx::space_shared_t,
+     void* tm_addr,
+     cuda::ptx::n32_t<N32> new_val);
diff --git a/docs/libcudacxx/ptx/instructions/special_registers.rst b/docs/libcudacxx/ptx/instructions/special_registers.rst
index 1e9597fa726..1981f7fb908 100644
--- a/docs/libcudacxx/ptx/instructions/special_registers.rst
+++ b/docs/libcudacxx/ptx/instructions/special_registers.rst
@@ -6,4 +6,4 @@ Special registers
 -  PTX ISA:
    `Special Register <https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#special-registers>`__
 
-.. include:: generated/special_registers.rst
+.. include:: generated/get_sreg.rst
diff --git a/docs/repo.toml b/docs/repo.toml
index 7ff29fd6eba..08ce4e58775 100644
--- a/docs/repo.toml
+++ b/docs/repo.toml
@@ -54,7 +54,7 @@ api_output_directory = "api"
 use_fast_doxygen_conversion = true
 sphinx_generate_doxygen_groups = true
 sphinx_generate_doxygen_pages = true
-sphinx_exclude_patterns = []
+sphinx_exclude_patterns = ['ptx/instructions/generated']
 
 [repo_docs.projects.cub]
 name = "CUB"
diff --git a/libcudacxx/include/cuda/__ptx/instructions/generated/barrier_cluster.h b/libcudacxx/include/cuda/__ptx/instructions/generated/barrier_cluster.h
index c8ce41c0a20..75a72db7024 100644
--- a/libcudacxx/include/cuda/__ptx/instructions/generated/barrier_cluster.h
+++ b/libcudacxx/include/cuda/__ptx/instructions/generated/barrier_cluster.h
@@ -14,12 +14,12 @@ extern "C" _CCCL_DEVICE void __cuda_ptx_barrier_cluster_arrive_is_not_supported_
 template <typename = void>
 _CCCL_DEVICE static inline void barrier_cluster_arrive()
 {
-  NV_IF_ELSE_TARGET(
-    NV_PROVIDES_SM_90,
-    (asm volatile("barrier.cluster.arrive;" : : : "memory");),
-    (
-      // Unsupported architectures will have a linker error with a semi-decent error message
-      __cuda_ptx_barrier_cluster_arrive_is_not_supported_before_SM_90__();));
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  asm volatile("barrier.cluster.arrive;" : : : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_barrier_cluster_arrive_is_not_supported_before_SM_90__();
+#  endif
 }
 #endif // __cccl_ptx_isa >= 780
 
@@ -34,12 +34,12 @@ extern "C" _CCCL_DEVICE void __cuda_ptx_barrier_cluster_wait_is_not_supported_be
 template <typename = void>
 _CCCL_DEVICE static inline void barrier_cluster_wait()
 {
-  NV_IF_ELSE_TARGET(
-    NV_PROVIDES_SM_90,
-    (asm volatile("barrier.cluster.wait;" : : : "memory");),
-    (
-      // Unsupported architectures will have a linker error with a semi-decent error message
-      __cuda_ptx_barrier_cluster_wait_is_not_supported_before_SM_90__();));
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  asm volatile("barrier.cluster.wait;" : : : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_barrier_cluster_wait_is_not_supported_before_SM_90__();
+#  endif
 }
 #endif // __cccl_ptx_isa >= 780
 
@@ -56,13 +56,13 @@ extern "C" _CCCL_DEVICE void __cuda_ptx_barrier_cluster_arrive_is_not_supported_
 template <typename = void>
 _CCCL_DEVICE static inline void barrier_cluster_arrive(sem_release_t)
 {
-  // __sem == sem_release (due to parameter type constraint)
-  NV_IF_ELSE_TARGET(
-    NV_PROVIDES_SM_90,
-    (asm volatile("barrier.cluster.arrive.release;" : : : "memory");),
-    (
-      // Unsupported architectures will have a linker error with a semi-decent error message
-      __cuda_ptx_barrier_cluster_arrive_is_not_supported_before_SM_90__();));
+// __sem == sem_release (due to parameter type constraint)
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  asm volatile("barrier.cluster.arrive.release;" : : : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_barrier_cluster_arrive_is_not_supported_before_SM_90__();
+#  endif
 }
 #endif // __cccl_ptx_isa >= 800
 
@@ -79,13 +79,13 @@ extern "C" _CCCL_DEVICE void __cuda_ptx_barrier_cluster_arrive_is_not_supported_
 template <typename = void>
 _CCCL_DEVICE static inline void barrier_cluster_arrive(sem_relaxed_t)
 {
-  // __sem == sem_relaxed (due to parameter type constraint)
-  NV_IF_ELSE_TARGET(
-    NV_PROVIDES_SM_90,
-    (asm volatile("barrier.cluster.arrive.relaxed;" : : :);),
-    (
-      // Unsupported architectures will have a linker error with a semi-decent error message
-      __cuda_ptx_barrier_cluster_arrive_is_not_supported_before_SM_90__();));
+// __sem == sem_relaxed (due to parameter type constraint)
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  asm volatile("barrier.cluster.arrive.relaxed;" : : :);
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_barrier_cluster_arrive_is_not_supported_before_SM_90__();
+#  endif
 }
 #endif // __cccl_ptx_isa >= 800
 
@@ -102,13 +102,13 @@ extern "C" _CCCL_DEVICE void __cuda_ptx_barrier_cluster_wait_is_not_supported_be
 template <typename = void>
 _CCCL_DEVICE static inline void barrier_cluster_wait(sem_acquire_t)
 {
-  // __sem == sem_acquire (due to parameter type constraint)
-  NV_IF_ELSE_TARGET(
-    NV_PROVIDES_SM_90,
-    (asm volatile("barrier.cluster.wait.acquire;" : : : "memory");),
-    (
-      // Unsupported architectures will have a linker error with a semi-decent error message
-      __cuda_ptx_barrier_cluster_wait_is_not_supported_before_SM_90__();));
+// __sem == sem_acquire (due to parameter type constraint)
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  asm volatile("barrier.cluster.wait.acquire;" : : : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_barrier_cluster_wait_is_not_supported_before_SM_90__();
+#  endif
 }
 #endif // __cccl_ptx_isa >= 800
 
diff --git a/libcudacxx/include/cuda/__ptx/instructions/generated/barrier_cluster_aligned.h b/libcudacxx/include/cuda/__ptx/instructions/generated/barrier_cluster_aligned.h
new file mode 100644
index 00000000000..80fe3796e69
--- /dev/null
+++ b/libcudacxx/include/cuda/__ptx/instructions/generated/barrier_cluster_aligned.h
@@ -0,0 +1,130 @@
+// This file was automatically generated. Do not edit.
+
+#ifndef _CUDA_PTX_GENERATED_BARRIER_CLUSTER_ALIGNED_H_
+#define _CUDA_PTX_GENERATED_BARRIER_CLUSTER_ALIGNED_H_
+
+/*
+// barrier.cluster.arrive.aligned; // PTX ISA 78, SM_90
+// .aligned   = { .aligned }
+// Marked volatile and as clobbering memory
+template <typename = void>
+__device__ static inline void barrier_cluster_arrive(
+  cuda::ptx::dot_aligned_t);
+*/
+#if __cccl_ptx_isa >= 780
+extern "C" _CCCL_DEVICE void __cuda_ptx_barrier_cluster_arrive_is_not_supported_before_SM_90__();
+template <typename = void>
+_CCCL_DEVICE static inline void barrier_cluster_arrive(dot_aligned_t)
+{
+// __aligned == aligned (due to parameter type constraint)
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  asm volatile("barrier.cluster.arrive.aligned;" : : : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_barrier_cluster_arrive_is_not_supported_before_SM_90__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 780
+
+/*
+// barrier.cluster.wait.aligned; // PTX ISA 78, SM_90
+// .aligned   = { .aligned }
+// Marked volatile and as clobbering memory
+template <typename = void>
+__device__ static inline void barrier_cluster_wait(
+  cuda::ptx::dot_aligned_t);
+*/
+#if __cccl_ptx_isa >= 780
+extern "C" _CCCL_DEVICE void __cuda_ptx_barrier_cluster_wait_is_not_supported_before_SM_90__();
+template <typename = void>
+_CCCL_DEVICE static inline void barrier_cluster_wait(dot_aligned_t)
+{
+// __aligned == aligned (due to parameter type constraint)
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  asm volatile("barrier.cluster.wait.aligned;" : : : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_barrier_cluster_wait_is_not_supported_before_SM_90__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 780
+
+/*
+// barrier.cluster.arrive.sem.aligned; // PTX ISA 80, SM_90
+// .sem       = { .release }
+// .aligned   = { .aligned }
+// Marked volatile and as clobbering memory
+template <typename = void>
+__device__ static inline void barrier_cluster_arrive(
+  cuda::ptx::sem_release_t,
+  cuda::ptx::dot_aligned_t);
+*/
+#if __cccl_ptx_isa >= 800
+extern "C" _CCCL_DEVICE void __cuda_ptx_barrier_cluster_arrive_is_not_supported_before_SM_90__();
+template <typename = void>
+_CCCL_DEVICE static inline void barrier_cluster_arrive(sem_release_t, dot_aligned_t)
+{
+// __sem == sem_release (due to parameter type constraint)
+// __aligned == aligned (due to parameter type constraint)
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  asm volatile("barrier.cluster.arrive.release.aligned;" : : : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_barrier_cluster_arrive_is_not_supported_before_SM_90__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 800
+
+/*
+// barrier.cluster.arrive.sem.aligned; // PTX ISA 80, SM_90
+// .sem       = { .relaxed }
+// .aligned   = { .aligned }
+// Marked volatile
+template <typename = void>
+__device__ static inline void barrier_cluster_arrive(
+  cuda::ptx::sem_relaxed_t,
+  cuda::ptx::dot_aligned_t);
+*/
+#if __cccl_ptx_isa >= 800
+extern "C" _CCCL_DEVICE void __cuda_ptx_barrier_cluster_arrive_is_not_supported_before_SM_90__();
+template <typename = void>
+_CCCL_DEVICE static inline void barrier_cluster_arrive(sem_relaxed_t, dot_aligned_t)
+{
+// __sem == sem_relaxed (due to parameter type constraint)
+// __aligned == aligned (due to parameter type constraint)
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  asm volatile("barrier.cluster.arrive.relaxed.aligned;" : : :);
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_barrier_cluster_arrive_is_not_supported_before_SM_90__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 800
+
+/*
+// barrier.cluster.wait.sem.aligned; // PTX ISA 80, SM_90
+// .sem       = { .acquire }
+// .aligned   = { .aligned }
+// Marked volatile and as clobbering memory
+template <typename = void>
+__device__ static inline void barrier_cluster_wait(
+  cuda::ptx::sem_acquire_t,
+  cuda::ptx::dot_aligned_t);
+*/
+#if __cccl_ptx_isa >= 800
+extern "C" _CCCL_DEVICE void __cuda_ptx_barrier_cluster_wait_is_not_supported_before_SM_90__();
+template <typename = void>
+_CCCL_DEVICE static inline void barrier_cluster_wait(sem_acquire_t, dot_aligned_t)
+{
+// __sem == sem_acquire (due to parameter type constraint)
+// __aligned == aligned (due to parameter type constraint)
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  asm volatile("barrier.cluster.wait.acquire.aligned;" : : : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_barrier_cluster_wait_is_not_supported_before_SM_90__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 800
+
+#endif // _CUDA_PTX_GENERATED_BARRIER_CLUSTER_ALIGNED_H_
diff --git a/libcudacxx/include/cuda/__ptx/instructions/generated/clusterlaunchcontrol.h b/libcudacxx/include/cuda/__ptx/instructions/generated/clusterlaunchcontrol.h
new file mode 100644
index 00000000000..19e3f92bd13
--- /dev/null
+++ b/libcudacxx/include/cuda/__ptx/instructions/generated/clusterlaunchcontrol.h
@@ -0,0 +1,240 @@
+// This file was automatically generated. Do not edit.
+
+#ifndef _CUDA_PTX_GENERATED_CLUSTERLAUNCHCONTROL_H_
+#define _CUDA_PTX_GENERATED_CLUSTERLAUNCHCONTROL_H_
+
+/*
+// clusterlaunchcontrol.try_cancel.async.shared::cta.mbarrier::complete_tx::bytes.b128 [addr], [smem_bar]; // PTX ISA
+86, SM_100 template <typename = void>
+__device__ static inline void clusterlaunchcontrol_try_cancel(
+  void* addr,
+  uint64_t* smem_bar);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_clusterlaunchcontrol_try_cancel_is_not_supported_before_SM_100__();
+template <typename = void>
+_CCCL_DEVICE static inline void clusterlaunchcontrol_try_cancel(void* __addr, _CUDA_VSTD::uint64_t* __smem_bar)
+{
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 1000
+  asm("clusterlaunchcontrol.try_cancel.async.shared::cta.mbarrier::complete_tx::bytes.b128 [%0], [%1];"
+      :
+      : "r"(__as_ptr_smem(__addr)), "r"(__as_ptr_smem(__smem_bar))
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_clusterlaunchcontrol_try_cancel_is_not_supported_before_SM_100__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// clusterlaunchcontrol.try_cancel.async.shared::cta.mbarrier::complete_tx::bytes.multicast::cluster::all.b128 [addr],
+[smem_bar]; // PTX ISA 86, SM_100a, SM_101a template <typename = void>
+__device__ static inline void clusterlaunchcontrol_try_cancel_multicast(
+  void* addr,
+  uint64_t* smem_bar);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void
+__cuda_ptx_clusterlaunchcontrol_try_cancel_multicast_is_not_supported_before_SM_100a_SM_101a__();
+template <typename = void>
+_CCCL_DEVICE static inline void clusterlaunchcontrol_try_cancel_multicast(void* __addr, _CUDA_VSTD::uint64_t* __smem_bar)
+{
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  asm("clusterlaunchcontrol.try_cancel.async.shared::cta.mbarrier::complete_tx::bytes.multicast::cluster::all.b128 "
+      "[%0], [%1];"
+      :
+      : "r"(__as_ptr_smem(__addr)), "r"(__as_ptr_smem(__smem_bar))
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_clusterlaunchcontrol_try_cancel_multicast_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// clusterlaunchcontrol.query_cancel.is_canceled.pred.b128 pred_is_canceled, try_cancel_response; // PTX ISA 86, SM_100
+template <typename B128, enable_if_t<sizeof(B128) == 16, bool> = true>
+__device__ static inline bool clusterlaunchcontrol_query_cancel_is_canceled(
+  B128 try_cancel_response);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_clusterlaunchcontrol_query_cancel_is_canceled_is_not_supported_before_SM_100__();
+template <typename _B128, _CUDA_VSTD::enable_if_t<sizeof(_B128) == 16, bool> = true>
+_CCCL_DEVICE static inline bool clusterlaunchcontrol_query_cancel_is_canceled(_B128 __try_cancel_response)
+{
+  static_assert(sizeof(_B128) == 16, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 1000
+  _CUDA_VSTD::uint32_t __pred_is_canceled;
+  asm("{\n\t .reg .b128 B128_try_cancel_response; \n\t"
+      "mov.b128 B128_try_cancel_response, {%1, %2}; \n"
+      "{\n\t .reg .pred P_OUT; \n\t"
+      "clusterlaunchcontrol.query_cancel.is_canceled.pred.b128 P_OUT, B128_try_cancel_response;\n\t"
+      "selp.b32 %0, 1, 0, P_OUT; \n"
+      "}\n\t"
+      "}"
+      : "=r"(__pred_is_canceled)
+      : "l"((*reinterpret_cast<long2*>(&__try_cancel_response)).x),
+        "l"((*reinterpret_cast<long2*>(&__try_cancel_response)).y)
+      :);
+  return static_cast<bool>(__pred_is_canceled);
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_clusterlaunchcontrol_query_cancel_is_canceled_is_not_supported_before_SM_100__();
+  return false;
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// clusterlaunchcontrol.query_cancel.get_first_ctaid::x.b32.b128 ret_dim, try_cancel_response; // PTX ISA 86, SM_100
+template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true, typename B128, enable_if_t<sizeof(B128) == 16, bool>
+= true>
+__device__ static inline B32 clusterlaunchcontrol_query_cancel_get_first_ctaid_x(
+  B128 try_cancel_response);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void
+__cuda_ptx_clusterlaunchcontrol_query_cancel_get_first_ctaid_x_is_not_supported_before_SM_100__();
+template <typename _B32,
+          _CUDA_VSTD::enable_if_t<sizeof(_B32) == 4, bool> = true,
+          typename _B128,
+          _CUDA_VSTD::enable_if_t<sizeof(_B128) == 16, bool> = true>
+_CCCL_DEVICE static inline _B32 clusterlaunchcontrol_query_cancel_get_first_ctaid_x(_B128 __try_cancel_response)
+{
+  static_assert(sizeof(_B32) == 4, "");
+  static_assert(sizeof(_B128) == 16, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 1000
+  _CUDA_VSTD::uint32_t __ret_dim;
+  asm("{\n\t .reg .b128 B128_try_cancel_response; \n\t"
+      "mov.b128 B128_try_cancel_response, {%1, %2}; \n"
+      "clusterlaunchcontrol.query_cancel.get_first_ctaid::x.b32.b128 %0, B128_try_cancel_response;\n\t"
+      "}"
+      : "=r"(__ret_dim)
+      : "l"((*reinterpret_cast<long2*>(&__try_cancel_response)).x),
+        "l"((*reinterpret_cast<long2*>(&__try_cancel_response)).y)
+      :);
+  return *reinterpret_cast<_B32*>(&__ret_dim);
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_clusterlaunchcontrol_query_cancel_get_first_ctaid_x_is_not_supported_before_SM_100__();
+  _CUDA_VSTD::uint32_t __err_out_var = 0;
+  return *reinterpret_cast<_B32*>(&__err_out_var);
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// clusterlaunchcontrol.query_cancel.get_first_ctaid::y.b32.b128 ret_dim, try_cancel_response; // PTX ISA 86, SM_100
+template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true, typename B128, enable_if_t<sizeof(B128) == 16, bool>
+= true>
+__device__ static inline B32 clusterlaunchcontrol_query_cancel_get_first_ctaid_y(
+  B128 try_cancel_response);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void
+__cuda_ptx_clusterlaunchcontrol_query_cancel_get_first_ctaid_y_is_not_supported_before_SM_100__();
+template <typename _B32,
+          _CUDA_VSTD::enable_if_t<sizeof(_B32) == 4, bool> = true,
+          typename _B128,
+          _CUDA_VSTD::enable_if_t<sizeof(_B128) == 16, bool> = true>
+_CCCL_DEVICE static inline _B32 clusterlaunchcontrol_query_cancel_get_first_ctaid_y(_B128 __try_cancel_response)
+{
+  static_assert(sizeof(_B32) == 4, "");
+  static_assert(sizeof(_B128) == 16, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 1000
+  _CUDA_VSTD::uint32_t __ret_dim;
+  asm("{\n\t .reg .b128 B128_try_cancel_response; \n\t"
+      "mov.b128 B128_try_cancel_response, {%1, %2}; \n"
+      "clusterlaunchcontrol.query_cancel.get_first_ctaid::y.b32.b128 %0, B128_try_cancel_response;\n\t"
+      "}"
+      : "=r"(__ret_dim)
+      : "l"((*reinterpret_cast<long2*>(&__try_cancel_response)).x),
+        "l"((*reinterpret_cast<long2*>(&__try_cancel_response)).y)
+      :);
+  return *reinterpret_cast<_B32*>(&__ret_dim);
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_clusterlaunchcontrol_query_cancel_get_first_ctaid_y_is_not_supported_before_SM_100__();
+  _CUDA_VSTD::uint32_t __err_out_var = 0;
+  return *reinterpret_cast<_B32*>(&__err_out_var);
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// clusterlaunchcontrol.query_cancel.get_first_ctaid::z.b32.b128 ret_dim, try_cancel_response; // PTX ISA 86, SM_100
+template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true, typename B128, enable_if_t<sizeof(B128) == 16, bool>
+= true>
+__device__ static inline B32 clusterlaunchcontrol_query_cancel_get_first_ctaid_z(
+  B128 try_cancel_response);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void
+__cuda_ptx_clusterlaunchcontrol_query_cancel_get_first_ctaid_z_is_not_supported_before_SM_100__();
+template <typename _B32,
+          _CUDA_VSTD::enable_if_t<sizeof(_B32) == 4, bool> = true,
+          typename _B128,
+          _CUDA_VSTD::enable_if_t<sizeof(_B128) == 16, bool> = true>
+_CCCL_DEVICE static inline _B32 clusterlaunchcontrol_query_cancel_get_first_ctaid_z(_B128 __try_cancel_response)
+{
+  static_assert(sizeof(_B32) == 4, "");
+  static_assert(sizeof(_B128) == 16, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 1000
+  _CUDA_VSTD::uint32_t __ret_dim;
+  asm("{\n\t .reg .b128 B128_try_cancel_response; \n\t"
+      "mov.b128 B128_try_cancel_response, {%1, %2}; \n"
+      "clusterlaunchcontrol.query_cancel.get_first_ctaid::z.b32.b128 %0, B128_try_cancel_response;\n\t"
+      "}"
+      : "=r"(__ret_dim)
+      : "l"((*reinterpret_cast<long2*>(&__try_cancel_response)).x),
+        "l"((*reinterpret_cast<long2*>(&__try_cancel_response)).y)
+      :);
+  return *reinterpret_cast<_B32*>(&__ret_dim);
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_clusterlaunchcontrol_query_cancel_get_first_ctaid_z_is_not_supported_before_SM_100__();
+  _CUDA_VSTD::uint32_t __err_out_var = 0;
+  return *reinterpret_cast<_B32*>(&__err_out_var);
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// clusterlaunchcontrol.query_cancel.get_first_ctaid.v4.b32.b128 block_dim, try_cancel_response; // PTX ISA 86, SM_100
+template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true, typename B128, enable_if_t<sizeof(B128) == 16, bool>
+= true>
+__device__ static inline void clusterlaunchcontrol_query_cancel_get_first_ctaid(
+  B32 (&block_dim)[4],
+  B128 try_cancel_response);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void
+__cuda_ptx_clusterlaunchcontrol_query_cancel_get_first_ctaid_is_not_supported_before_SM_100__();
+template <typename _B32,
+          _CUDA_VSTD::enable_if_t<sizeof(_B32) == 4, bool> = true,
+          typename _B128,
+          _CUDA_VSTD::enable_if_t<sizeof(_B128) == 16, bool> = true>
+_CCCL_DEVICE static inline void
+clusterlaunchcontrol_query_cancel_get_first_ctaid(_B32 (&__block_dim)[4], _B128 __try_cancel_response)
+{
+  static_assert(sizeof(_B32) == 4, "");
+  static_assert(sizeof(_B128) == 16, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 1000
+  asm("{\n\t .reg .b128 B128_try_cancel_response; \n\t"
+      "mov.b128 B128_try_cancel_response, {%4, %5}; \n"
+      "clusterlaunchcontrol.query_cancel.get_first_ctaid.v4.b32.b128 {%0, %1, %2, %3}, B128_try_cancel_response;\n\t"
+      "}"
+      : "=r"(__block_dim[0]), "=r"(__block_dim[1]), "=r"(__block_dim[2]), "=r"(__block_dim[3])
+      : "l"((*reinterpret_cast<long2*>(&__try_cancel_response)).x),
+        "l"((*reinterpret_cast<long2*>(&__try_cancel_response)).y)
+      :);
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_clusterlaunchcontrol_query_cancel_get_first_ctaid_is_not_supported_before_SM_100__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+#endif // _CUDA_PTX_GENERATED_CLUSTERLAUNCHCONTROL_H_
diff --git a/libcudacxx/include/cuda/__ptx/instructions/generated/cp_async_bulk.h b/libcudacxx/include/cuda/__ptx/instructions/generated/cp_async_bulk.h
index d2196402e7a..a9aa3534611 100644
--- a/libcudacxx/include/cuda/__ptx/instructions/generated/cp_async_bulk.h
+++ b/libcudacxx/include/cuda/__ptx/instructions/generated/cp_async_bulk.h
@@ -4,8 +4,7 @@
 #define _CUDA_PTX_GENERATED_CP_ASYNC_BULK_H_
 
 /*
-// cp.async.bulk.dst.src.mbarrier::complete_tx::bytes [dstMem], [srcMem], size, [smem_bar]; // 1a. unicast PTX ISA 80,
-SM_90
+// cp.async.bulk.dst.src.mbarrier::complete_tx::bytes [dstMem], [srcMem], size, [smem_bar]; // PTX ISA 80, SM_90
 // .dst       = { .shared::cluster }
 // .src       = { .global }
 template <typename = void>
@@ -28,23 +27,60 @@ _CCCL_DEVICE static inline void cp_async_bulk(
   const _CUDA_VSTD::uint32_t& __size,
   _CUDA_VSTD::uint64_t* __smem_bar)
 {
-  // __space == space_cluster (due to parameter type constraint)
-  // __space == space_global (due to parameter type constraint)
-  NV_IF_ELSE_TARGET(
-    NV_PROVIDES_SM_90,
-    (asm("cp.async.bulk.shared::cluster.global.mbarrier::complete_tx::bytes [%0], [%1], %2, [%3]; // "
-         "1a. unicast" : : "r"(__as_ptr_smem(__dstMem)),
-         "l"(__as_ptr_gmem(__srcMem)),
-         "r"(__size),
-         "r"(__as_ptr_smem(__smem_bar)) : "memory");),
-    (
-      // Unsupported architectures will have a linker error with a semi-decent error message
-      __cuda_ptx_cp_async_bulk_is_not_supported_before_SM_90__();));
+// __space == space_cluster (due to parameter type constraint)
+// __space == space_global (due to parameter type constraint)
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  asm("cp.async.bulk.shared::cluster.global.mbarrier::complete_tx::bytes [%0], [%1], %2, [%3];"
+      :
+      : "r"(__as_ptr_smem(__dstMem)), "l"(__as_ptr_gmem(__srcMem)), "r"(__size), "r"(__as_ptr_smem(__smem_bar))
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_cp_async_bulk_is_not_supported_before_SM_90__();
+#  endif
 }
 #endif // __cccl_ptx_isa >= 800
 
 /*
-// cp.async.bulk.dst.src.mbarrier::complete_tx::bytes [dstMem], [srcMem], size, [rdsmem_bar]; // 2.  PTX ISA 80, SM_90
+// cp.async.bulk.dst.src.mbarrier::complete_tx::bytes [dstMem], [srcMem], size, [smem_bar]; // PTX ISA 86, SM_90
+// .dst       = { .shared::cta }
+// .src       = { .global }
+template <typename = void>
+__device__ static inline void cp_async_bulk(
+  cuda::ptx::space_shared_t,
+  cuda::ptx::space_global_t,
+  void* dstMem,
+  const void* srcMem,
+  const uint32_t& size,
+  uint64_t* smem_bar);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_cp_async_bulk_is_not_supported_before_SM_90__();
+template <typename = void>
+_CCCL_DEVICE static inline void cp_async_bulk(
+  space_shared_t,
+  space_global_t,
+  void* __dstMem,
+  const void* __srcMem,
+  const _CUDA_VSTD::uint32_t& __size,
+  _CUDA_VSTD::uint64_t* __smem_bar)
+{
+// __space == space_shared (due to parameter type constraint)
+// __space == space_global (due to parameter type constraint)
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  asm("cp.async.bulk.shared::cta.global.mbarrier::complete_tx::bytes [%0], [%1], %2, [%3];"
+      :
+      : "r"(__as_ptr_smem(__dstMem)), "l"(__as_ptr_gmem(__srcMem)), "r"(__size), "r"(__as_ptr_smem(__smem_bar))
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_cp_async_bulk_is_not_supported_before_SM_90__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// cp.async.bulk.dst.src.mbarrier::complete_tx::bytes [dstMem], [srcMem], size, [rdsmem_bar]; // PTX ISA 80, SM_90
 // .dst       = { .shared::cluster }
 // .src       = { .shared::cta }
 template <typename = void>
@@ -67,23 +103,25 @@ _CCCL_DEVICE static inline void cp_async_bulk(
   const _CUDA_VSTD::uint32_t& __size,
   _CUDA_VSTD::uint64_t* __rdsmem_bar)
 {
-  // __space == space_cluster (due to parameter type constraint)
-  // __space == space_shared (due to parameter type constraint)
-  NV_IF_ELSE_TARGET(
-    NV_PROVIDES_SM_90,
-    (asm("cp.async.bulk.shared::cluster.shared::cta.mbarrier::complete_tx::bytes [%0], [%1], %2, [%3]; // 2. " : : "r"(
-           __as_ptr_remote_dsmem(__dstMem)),
-         "r"(__as_ptr_smem(__srcMem)),
-         "r"(__size),
-         "r"(__as_ptr_remote_dsmem(__rdsmem_bar)) : "memory");),
-    (
-      // Unsupported architectures will have a linker error with a semi-decent error message
-      __cuda_ptx_cp_async_bulk_is_not_supported_before_SM_90__();));
+// __space == space_cluster (due to parameter type constraint)
+// __space == space_shared (due to parameter type constraint)
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  asm("cp.async.bulk.shared::cluster.shared::cta.mbarrier::complete_tx::bytes [%0], [%1], %2, [%3];"
+      :
+      : "r"(__as_ptr_remote_dsmem(__dstMem)),
+        "r"(__as_ptr_smem(__srcMem)),
+        "r"(__size),
+        "r"(__as_ptr_remote_dsmem(__rdsmem_bar))
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_cp_async_bulk_is_not_supported_before_SM_90__();
+#  endif
 }
 #endif // __cccl_ptx_isa >= 800
 
 /*
-// cp.async.bulk.dst.src.bulk_group [dstMem], [srcMem], size; // 3.  PTX ISA 80, SM_90
+// cp.async.bulk.dst.src.bulk_group [dstMem], [srcMem], size; // PTX ISA 80, SM_90
 // .dst       = { .global }
 // .src       = { .shared::cta }
 template <typename = void>
@@ -100,17 +138,56 @@ template <typename = void>
 _CCCL_DEVICE static inline void
 cp_async_bulk(space_global_t, space_shared_t, void* __dstMem, const void* __srcMem, const _CUDA_VSTD::uint32_t& __size)
 {
-  // __space == space_global (due to parameter type constraint)
-  // __space == space_shared (due to parameter type constraint)
-  NV_IF_ELSE_TARGET(
-    NV_PROVIDES_SM_90,
-    (asm("cp.async.bulk.global.shared::cta.bulk_group [%0], [%1], %2; // 3. " : : "l"(__as_ptr_gmem(__dstMem)),
-         "r"(__as_ptr_smem(__srcMem)),
-         "r"(__size) : "memory");),
-    (
-      // Unsupported architectures will have a linker error with a semi-decent error message
-      __cuda_ptx_cp_async_bulk_is_not_supported_before_SM_90__();));
+// __space == space_global (due to parameter type constraint)
+// __space == space_shared (due to parameter type constraint)
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  asm("cp.async.bulk.global.shared::cta.bulk_group [%0], [%1], %2;"
+      :
+      : "l"(__as_ptr_gmem(__dstMem)), "r"(__as_ptr_smem(__srcMem)), "r"(__size)
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_cp_async_bulk_is_not_supported_before_SM_90__();
+#  endif
 }
 #endif // __cccl_ptx_isa >= 800
 
+/*
+// cp.async.bulk.dst.src.bulk_group.cp_mask [dstMem], [srcMem], size, byteMask; // PTX ISA 86, SM_100
+// .dst       = { .global }
+// .src       = { .shared::cta }
+template <typename = void>
+__device__ static inline void cp_async_bulk_cp_mask(
+  cuda::ptx::space_global_t,
+  cuda::ptx::space_shared_t,
+  void* dstMem,
+  const void* srcMem,
+  const uint32_t& size,
+  const uint16_t& byteMask);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_cp_async_bulk_cp_mask_is_not_supported_before_SM_100__();
+template <typename = void>
+_CCCL_DEVICE static inline void cp_async_bulk_cp_mask(
+  space_global_t,
+  space_shared_t,
+  void* __dstMem,
+  const void* __srcMem,
+  const _CUDA_VSTD::uint32_t& __size,
+  const _CUDA_VSTD::uint16_t& __byteMask)
+{
+// __space == space_global (due to parameter type constraint)
+// __space == space_shared (due to parameter type constraint)
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 1000
+  asm("cp.async.bulk.global.shared::cta.bulk_group.cp_mask [%0], [%1], %2, %3;"
+      :
+      : "l"(__as_ptr_gmem(__dstMem)), "r"(__as_ptr_smem(__srcMem)), "r"(__size), "h"(__byteMask)
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_cp_async_bulk_cp_mask_is_not_supported_before_SM_100__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
 #endif // _CUDA_PTX_GENERATED_CP_ASYNC_BULK_H_
diff --git a/libcudacxx/include/cuda/__ptx/instructions/generated/cp_async_bulk_commit_group.h b/libcudacxx/include/cuda/__ptx/instructions/generated/cp_async_bulk_commit_group.h
index 3c32743e977..3b906fd6922 100644
--- a/libcudacxx/include/cuda/__ptx/instructions/generated/cp_async_bulk_commit_group.h
+++ b/libcudacxx/include/cuda/__ptx/instructions/generated/cp_async_bulk_commit_group.h
@@ -13,12 +13,12 @@ extern "C" _CCCL_DEVICE void __cuda_ptx_cp_async_bulk_commit_group_is_not_suppor
 template <typename = void>
 _CCCL_DEVICE static inline void cp_async_bulk_commit_group()
 {
-  NV_IF_ELSE_TARGET(
-    NV_PROVIDES_SM_90,
-    (asm volatile("cp.async.bulk.commit_group;" : : :);),
-    (
-      // Unsupported architectures will have a linker error with a semi-decent error message
-      __cuda_ptx_cp_async_bulk_commit_group_is_not_supported_before_SM_90__();));
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  asm volatile("cp.async.bulk.commit_group;" : : :);
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_cp_async_bulk_commit_group_is_not_supported_before_SM_90__();
+#  endif
 }
 #endif // __cccl_ptx_isa >= 800
 
diff --git a/libcudacxx/include/cuda/__ptx/instructions/generated/cp_async_bulk_multicast.h b/libcudacxx/include/cuda/__ptx/instructions/generated/cp_async_bulk_multicast.h
index f54bf8bbdeb..7ac386343b9 100644
--- a/libcudacxx/include/cuda/__ptx/instructions/generated/cp_async_bulk_multicast.h
+++ b/libcudacxx/include/cuda/__ptx/instructions/generated/cp_async_bulk_multicast.h
@@ -4,8 +4,8 @@
 #define _CUDA_PTX_GENERATED_CP_ASYNC_BULK_MULTICAST_H_
 
 /*
-// cp.async.bulk{.dst}{.src}.mbarrier::complete_tx::bytes.multicast::cluster [dstMem], [srcMem], size, [smem_bar],
-ctaMask; // 1.  PTX ISA 80, SM_90a
+// cp.async.bulk.dst.src.mbarrier::complete_tx::bytes.multicast::cluster [dstMem], [srcMem], size, [smem_bar], ctaMask;
+// PTX ISA 80, SM_90a, SM_100a, SM_101a
 // .dst       = { .shared::cluster }
 // .src       = { .global }
 template <typename = void>
@@ -19,7 +19,7 @@ __device__ static inline void cp_async_bulk(
   const uint16_t& ctaMask);
 */
 #if __cccl_ptx_isa >= 800
-extern "C" _CCCL_DEVICE void __cuda_ptx_cp_async_bulk_is_not_supported_before_SM_90a__();
+extern "C" _CCCL_DEVICE void __cuda_ptx_cp_async_bulk_is_not_supported_before_SM_90a_SM_100a_SM_101a__();
 template <typename = void>
 _CCCL_DEVICE static inline void cp_async_bulk(
   space_cluster_t,
@@ -30,19 +30,22 @@ _CCCL_DEVICE static inline void cp_async_bulk(
   _CUDA_VSTD::uint64_t* __smem_bar,
   const _CUDA_VSTD::uint16_t& __ctaMask)
 {
-  // __space == space_cluster (due to parameter type constraint)
-  // __space == space_global (due to parameter type constraint)
-  NV_IF_ELSE_TARGET(
-    NV_HAS_FEATURE_SM_90a,
-    (asm("cp.async.bulk.shared::cluster.global.mbarrier::complete_tx::bytes.multicast::cluster [%0], [%1], %2, [%3], "
-         "%4; // 1. " : : "r"(__as_ptr_smem(__dstMem)),
-         "l"(__as_ptr_gmem(__srcMem)),
-         "r"(__size),
-         "r"(__as_ptr_smem(__smem_bar)),
-         "h"(__ctaMask) : "memory");),
-    (
-      // Unsupported architectures will have a linker error with a semi-decent error message
-      __cuda_ptx_cp_async_bulk_is_not_supported_before_SM_90a__();));
+// __space == space_cluster (due to parameter type constraint)
+// __space == space_global (due to parameter type constraint)
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM90_ALL || __CUDA_ARCH_FEAT_SM100_ALL \
+    || __CUDA_ARCH_FEAT_SM101_ALL
+  asm("cp.async.bulk.shared::cluster.global.mbarrier::complete_tx::bytes.multicast::cluster [%0], [%1], %2, [%3], %4;"
+      :
+      : "r"(__as_ptr_smem(__dstMem)),
+        "l"(__as_ptr_gmem(__srcMem)),
+        "r"(__size),
+        "r"(__as_ptr_smem(__smem_bar)),
+        "h"(__ctaMask)
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_cp_async_bulk_is_not_supported_before_SM_90a_SM_100a_SM_101a__();
+#  endif
 }
 #endif // __cccl_ptx_isa >= 800
 
diff --git a/libcudacxx/include/cuda/__ptx/instructions/generated/cp_async_bulk_tensor.h b/libcudacxx/include/cuda/__ptx/instructions/generated/cp_async_bulk_tensor.h
index f7c60bb72f6..2326346f547 100644
--- a/libcudacxx/include/cuda/__ptx/instructions/generated/cp_async_bulk_tensor.h
+++ b/libcudacxx/include/cuda/__ptx/instructions/generated/cp_async_bulk_tensor.h
@@ -4,8 +4,8 @@
 #define _CUDA_PTX_GENERATED_CP_ASYNC_BULK_TENSOR_H_
 
 /*
-// cp.async.bulk.tensor.1d.dst.src.tile.mbarrier::complete_tx::bytes [dstMem], [tensorMap, tensorCoords], [smem_bar];//
-1a. PTX ISA 80, SM_90
+// cp.async.bulk.tensor.1d.dst.src.tile.mbarrier::complete_tx::bytes [dstMem], [tensorMap, tensorCoords], [smem_bar]; //
+PTX ISA 80, SM_90
 // .dst       = { .shared::cluster }
 // .src       = { .global }
 template <typename = void>
@@ -28,23 +28,116 @@ _CCCL_DEVICE static inline void cp_async_bulk_tensor(
   const _CUDA_VSTD::int32_t (&__tensorCoords)[1],
   _CUDA_VSTD::uint64_t* __smem_bar)
 {
-  // __space == space_cluster (due to parameter type constraint)
-  // __space == space_global (due to parameter type constraint)
-  NV_IF_ELSE_TARGET(
-    NV_PROVIDES_SM_90,
-    (asm("cp.async.bulk.tensor.1d.shared::cluster.global.tile.mbarrier::complete_tx::bytes [%0], [%1, {%2}], [%3];// "
-         "1a." : : "r"(__as_ptr_smem(__dstMem)),
-         "l"(__tensorMap),
-         "r"(__tensorCoords[0]),
-         "r"(__as_ptr_smem(__smem_bar)) : "memory");),
-    (
-      // Unsupported architectures will have a linker error with a semi-decent error message
-      __cuda_ptx_cp_async_bulk_tensor_is_not_supported_before_SM_90__();));
+// __space == space_cluster (due to parameter type constraint)
+// __space == space_global (due to parameter type constraint)
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  asm("cp.async.bulk.tensor.1d.shared::cluster.global.tile.mbarrier::complete_tx::bytes [%0], [%1, {%2}], [%3];"
+      :
+      : "r"(__as_ptr_smem(__dstMem)), "l"(__tensorMap), "r"(__tensorCoords[0]), "r"(__as_ptr_smem(__smem_bar))
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_cp_async_bulk_tensor_is_not_supported_before_SM_90__();
+#  endif
 }
 #endif // __cccl_ptx_isa >= 800
 
 /*
-// cp.async.bulk.tensor.1d.dst.src.tile.bulk_group [tensorMap, tensorCoords], [srcMem]; // 3a. PTX ISA 80, SM_90
+// cp.async.bulk.tensor.1d.dst.src.tile.mbarrier::complete_tx::bytes [dstMem], [tensorMap, tensorCoords], [smem_bar]; //
+PTX ISA 86, SM_90
+// .dst       = { .shared::cta }
+// .src       = { .global }
+template <typename = void>
+__device__ static inline void cp_async_bulk_tensor(
+  cuda::ptx::space_shared_t,
+  cuda::ptx::space_global_t,
+  void* dstMem,
+  const void* tensorMap,
+  const int32_t (&tensorCoords)[1],
+  uint64_t* smem_bar);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_cp_async_bulk_tensor_is_not_supported_before_SM_90__();
+template <typename = void>
+_CCCL_DEVICE static inline void cp_async_bulk_tensor(
+  space_shared_t,
+  space_global_t,
+  void* __dstMem,
+  const void* __tensorMap,
+  const _CUDA_VSTD::int32_t (&__tensorCoords)[1],
+  _CUDA_VSTD::uint64_t* __smem_bar)
+{
+// __space == space_shared (due to parameter type constraint)
+// __space == space_global (due to parameter type constraint)
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  asm("cp.async.bulk.tensor.1d.shared::cta.global.tile.mbarrier::complete_tx::bytes [%0], [%1, {%2}], [%3];"
+      :
+      : "r"(__as_ptr_smem(__dstMem)), "l"(__tensorMap), "r"(__tensorCoords[0]), "r"(__as_ptr_smem(__smem_bar))
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_cp_async_bulk_tensor_is_not_supported_before_SM_90__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// cp.async.bulk.tensor.1d.dst.src.tile.mbarrier::complete_tx::bytes.cta_group [dstMem], [tensorMap, tensorCoords],
+[smem_bar]; // PTX ISA 86, SM_100a, SM_101a
+// .dst       = { .shared::cta }
+// .src       = { .global }
+// .cta_group = { .cta_group::1, .cta_group::2 }
+template <cuda::ptx::dot_cta_group Cta_Group>
+__device__ static inline void cp_async_bulk_tensor(
+  cuda::ptx::space_shared_t,
+  cuda::ptx::space_global_t,
+  cuda::ptx::cta_group_t<Cta_Group> cta_group,
+  void* dstMem,
+  const void* tensorMap,
+  const int32_t (&tensorCoords)[1],
+  uint64_t* smem_bar);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_cp_async_bulk_tensor_is_not_supported_before_SM_100a_SM_101a__();
+template <dot_cta_group _Cta_Group>
+_CCCL_DEVICE static inline void cp_async_bulk_tensor(
+  space_shared_t,
+  space_global_t,
+  cta_group_t<_Cta_Group> __cta_group,
+  void* __dstMem,
+  const void* __tensorMap,
+  const _CUDA_VSTD::int32_t (&__tensorCoords)[1],
+  _CUDA_VSTD::uint64_t* __smem_bar)
+{
+  // __space == space_shared (due to parameter type constraint)
+  // __space == space_global (due to parameter type constraint)
+  static_assert(__cta_group == cta_group_1 || __cta_group == cta_group_2, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  _CCCL_IF_CONSTEXPR (__cta_group == cta_group_1)
+  {
+    asm("cp.async.bulk.tensor.1d.shared::cta.global.tile.mbarrier::complete_tx::bytes.cta_group::1 [%0], [%1, {%2}], "
+        "[%3];"
+        :
+        : "r"(__as_ptr_smem(__dstMem)), "l"(__tensorMap), "r"(__tensorCoords[0]), "r"(__as_ptr_smem(__smem_bar))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__cta_group == cta_group_2)
+  {
+    asm("cp.async.bulk.tensor.1d.shared::cta.global.tile.mbarrier::complete_tx::bytes.cta_group::2 [%0], [%1, {%2}], "
+        "[%3];"
+        :
+        : "r"(__as_ptr_smem(__dstMem)), "l"(__tensorMap), "r"(__tensorCoords[0]), "r"(__as_ptr_smem(__smem_bar))
+        : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_cp_async_bulk_tensor_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// cp.async.bulk.tensor.1d.dst.src.tile.bulk_group [tensorMap, tensorCoords], [srcMem]; // PTX ISA 80, SM_90
 // .dst       = { .global }
 // .src       = { .shared::cta }
 template <typename = void>
@@ -65,22 +158,23 @@ _CCCL_DEVICE static inline void cp_async_bulk_tensor(
   const _CUDA_VSTD::int32_t (&__tensorCoords)[1],
   const void* __srcMem)
 {
-  // __space == space_global (due to parameter type constraint)
-  // __space == space_shared (due to parameter type constraint)
-  NV_IF_ELSE_TARGET(
-    NV_PROVIDES_SM_90,
-    (asm("cp.async.bulk.tensor.1d.global.shared::cta.tile.bulk_group [%0, {%1}], [%2]; // 3a." : : "l"(__tensorMap),
-         "r"(__tensorCoords[0]),
-         "r"(__as_ptr_smem(__srcMem)) : "memory");),
-    (
-      // Unsupported architectures will have a linker error with a semi-decent error message
-      __cuda_ptx_cp_async_bulk_tensor_is_not_supported_before_SM_90__();));
+// __space == space_global (due to parameter type constraint)
+// __space == space_shared (due to parameter type constraint)
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  asm("cp.async.bulk.tensor.1d.global.shared::cta.tile.bulk_group [%0, {%1}], [%2];"
+      :
+      : "l"(__tensorMap), "r"(__tensorCoords[0]), "r"(__as_ptr_smem(__srcMem))
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_cp_async_bulk_tensor_is_not_supported_before_SM_90__();
+#  endif
 }
 #endif // __cccl_ptx_isa >= 800
 
 /*
-// cp.async.bulk.tensor.2d.dst.src.tile.mbarrier::complete_tx::bytes [dstMem], [tensorMap, tensorCoords], [smem_bar];//
-1b. PTX ISA 80, SM_90
+// cp.async.bulk.tensor.2d.dst.src.tile.mbarrier::complete_tx::bytes [dstMem], [tensorMap, tensorCoords], [smem_bar]; //
+PTX ISA 80, SM_90
 // .dst       = { .shared::cluster }
 // .src       = { .global }
 template <typename = void>
@@ -103,24 +197,132 @@ _CCCL_DEVICE static inline void cp_async_bulk_tensor(
   const _CUDA_VSTD::int32_t (&__tensorCoords)[2],
   _CUDA_VSTD::uint64_t* __smem_bar)
 {
-  // __space == space_cluster (due to parameter type constraint)
-  // __space == space_global (due to parameter type constraint)
-  NV_IF_ELSE_TARGET(
-    NV_PROVIDES_SM_90,
-    (asm("cp.async.bulk.tensor.2d.shared::cluster.global.tile.mbarrier::complete_tx::bytes [%0], [%1, {%2, %3}], "
-         "[%4];// 1b." : : "r"(__as_ptr_smem(__dstMem)),
-         "l"(__tensorMap),
-         "r"(__tensorCoords[0]),
-         "r"(__tensorCoords[1]),
-         "r"(__as_ptr_smem(__smem_bar)) : "memory");),
-    (
-      // Unsupported architectures will have a linker error with a semi-decent error message
-      __cuda_ptx_cp_async_bulk_tensor_is_not_supported_before_SM_90__();));
+// __space == space_cluster (due to parameter type constraint)
+// __space == space_global (due to parameter type constraint)
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  asm("cp.async.bulk.tensor.2d.shared::cluster.global.tile.mbarrier::complete_tx::bytes [%0], [%1, {%2, %3}], [%4];"
+      :
+      : "r"(__as_ptr_smem(__dstMem)),
+        "l"(__tensorMap),
+        "r"(__tensorCoords[0]),
+        "r"(__tensorCoords[1]),
+        "r"(__as_ptr_smem(__smem_bar))
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_cp_async_bulk_tensor_is_not_supported_before_SM_90__();
+#  endif
 }
 #endif // __cccl_ptx_isa >= 800
 
 /*
-// cp.async.bulk.tensor.2d.dst.src.tile.bulk_group [tensorMap, tensorCoords], [srcMem]; // 3b. PTX ISA 80, SM_90
+// cp.async.bulk.tensor.2d.dst.src.tile.mbarrier::complete_tx::bytes [dstMem], [tensorMap, tensorCoords], [smem_bar]; //
+PTX ISA 86, SM_90
+// .dst       = { .shared::cta }
+// .src       = { .global }
+template <typename = void>
+__device__ static inline void cp_async_bulk_tensor(
+  cuda::ptx::space_shared_t,
+  cuda::ptx::space_global_t,
+  void* dstMem,
+  const void* tensorMap,
+  const int32_t (&tensorCoords)[2],
+  uint64_t* smem_bar);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_cp_async_bulk_tensor_is_not_supported_before_SM_90__();
+template <typename = void>
+_CCCL_DEVICE static inline void cp_async_bulk_tensor(
+  space_shared_t,
+  space_global_t,
+  void* __dstMem,
+  const void* __tensorMap,
+  const _CUDA_VSTD::int32_t (&__tensorCoords)[2],
+  _CUDA_VSTD::uint64_t* __smem_bar)
+{
+// __space == space_shared (due to parameter type constraint)
+// __space == space_global (due to parameter type constraint)
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  asm("cp.async.bulk.tensor.2d.shared::cta.global.tile.mbarrier::complete_tx::bytes [%0], [%1, {%2, %3}], [%4];"
+      :
+      : "r"(__as_ptr_smem(__dstMem)),
+        "l"(__tensorMap),
+        "r"(__tensorCoords[0]),
+        "r"(__tensorCoords[1]),
+        "r"(__as_ptr_smem(__smem_bar))
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_cp_async_bulk_tensor_is_not_supported_before_SM_90__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// cp.async.bulk.tensor.2d.dst.src.tile.mbarrier::complete_tx::bytes.cta_group [dstMem], [tensorMap, tensorCoords],
+[smem_bar]; // PTX ISA 86, SM_100a, SM_101a
+// .dst       = { .shared::cta }
+// .src       = { .global }
+// .cta_group = { .cta_group::1, .cta_group::2 }
+template <cuda::ptx::dot_cta_group Cta_Group>
+__device__ static inline void cp_async_bulk_tensor(
+  cuda::ptx::space_shared_t,
+  cuda::ptx::space_global_t,
+  cuda::ptx::cta_group_t<Cta_Group> cta_group,
+  void* dstMem,
+  const void* tensorMap,
+  const int32_t (&tensorCoords)[2],
+  uint64_t* smem_bar);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_cp_async_bulk_tensor_is_not_supported_before_SM_100a_SM_101a__();
+template <dot_cta_group _Cta_Group>
+_CCCL_DEVICE static inline void cp_async_bulk_tensor(
+  space_shared_t,
+  space_global_t,
+  cta_group_t<_Cta_Group> __cta_group,
+  void* __dstMem,
+  const void* __tensorMap,
+  const _CUDA_VSTD::int32_t (&__tensorCoords)[2],
+  _CUDA_VSTD::uint64_t* __smem_bar)
+{
+  // __space == space_shared (due to parameter type constraint)
+  // __space == space_global (due to parameter type constraint)
+  static_assert(__cta_group == cta_group_1 || __cta_group == cta_group_2, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  _CCCL_IF_CONSTEXPR (__cta_group == cta_group_1)
+  {
+    asm("cp.async.bulk.tensor.2d.shared::cta.global.tile.mbarrier::complete_tx::bytes.cta_group::1 [%0], [%1, {%2, "
+        "%3}], [%4];"
+        :
+        : "r"(__as_ptr_smem(__dstMem)),
+          "l"(__tensorMap),
+          "r"(__tensorCoords[0]),
+          "r"(__tensorCoords[1]),
+          "r"(__as_ptr_smem(__smem_bar))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__cta_group == cta_group_2)
+  {
+    asm("cp.async.bulk.tensor.2d.shared::cta.global.tile.mbarrier::complete_tx::bytes.cta_group::2 [%0], [%1, {%2, "
+        "%3}], [%4];"
+        :
+        : "r"(__as_ptr_smem(__dstMem)),
+          "l"(__tensorMap),
+          "r"(__tensorCoords[0]),
+          "r"(__tensorCoords[1]),
+          "r"(__as_ptr_smem(__smem_bar))
+        : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_cp_async_bulk_tensor_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// cp.async.bulk.tensor.2d.dst.src.tile.bulk_group [tensorMap, tensorCoords], [srcMem]; // PTX ISA 80, SM_90
 // .dst       = { .global }
 // .src       = { .shared::cta }
 template <typename = void>
@@ -141,23 +343,23 @@ _CCCL_DEVICE static inline void cp_async_bulk_tensor(
   const _CUDA_VSTD::int32_t (&__tensorCoords)[2],
   const void* __srcMem)
 {
-  // __space == space_global (due to parameter type constraint)
-  // __space == space_shared (due to parameter type constraint)
-  NV_IF_ELSE_TARGET(
-    NV_PROVIDES_SM_90,
-    (asm("cp.async.bulk.tensor.2d.global.shared::cta.tile.bulk_group [%0, {%1, %2}], [%3]; // 3b." : : "l"(__tensorMap),
-         "r"(__tensorCoords[0]),
-         "r"(__tensorCoords[1]),
-         "r"(__as_ptr_smem(__srcMem)) : "memory");),
-    (
-      // Unsupported architectures will have a linker error with a semi-decent error message
-      __cuda_ptx_cp_async_bulk_tensor_is_not_supported_before_SM_90__();));
+// __space == space_global (due to parameter type constraint)
+// __space == space_shared (due to parameter type constraint)
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  asm("cp.async.bulk.tensor.2d.global.shared::cta.tile.bulk_group [%0, {%1, %2}], [%3];"
+      :
+      : "l"(__tensorMap), "r"(__tensorCoords[0]), "r"(__tensorCoords[1]), "r"(__as_ptr_smem(__srcMem))
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_cp_async_bulk_tensor_is_not_supported_before_SM_90__();
+#  endif
 }
 #endif // __cccl_ptx_isa >= 800
 
 /*
-// cp.async.bulk.tensor.3d.dst.src.tile.mbarrier::complete_tx::bytes [dstMem], [tensorMap, tensorCoords], [smem_bar];//
-1c. PTX ISA 80, SM_90
+// cp.async.bulk.tensor.3d.dst.src.tile.mbarrier::complete_tx::bytes [dstMem], [tensorMap, tensorCoords], [smem_bar]; //
+PTX ISA 80, SM_90
 // .dst       = { .shared::cluster }
 // .src       = { .global }
 template <typename = void>
@@ -180,25 +382,136 @@ _CCCL_DEVICE static inline void cp_async_bulk_tensor(
   const _CUDA_VSTD::int32_t (&__tensorCoords)[3],
   _CUDA_VSTD::uint64_t* __smem_bar)
 {
-  // __space == space_cluster (due to parameter type constraint)
-  // __space == space_global (due to parameter type constraint)
-  NV_IF_ELSE_TARGET(
-    NV_PROVIDES_SM_90,
-    (asm("cp.async.bulk.tensor.3d.shared::cluster.global.tile.mbarrier::complete_tx::bytes [%0], [%1, {%2, %3, %4}], "
-         "[%5];// 1c." : : "r"(__as_ptr_smem(__dstMem)),
-         "l"(__tensorMap),
-         "r"(__tensorCoords[0]),
-         "r"(__tensorCoords[1]),
-         "r"(__tensorCoords[2]),
-         "r"(__as_ptr_smem(__smem_bar)) : "memory");),
-    (
-      // Unsupported architectures will have a linker error with a semi-decent error message
-      __cuda_ptx_cp_async_bulk_tensor_is_not_supported_before_SM_90__();));
+// __space == space_cluster (due to parameter type constraint)
+// __space == space_global (due to parameter type constraint)
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  asm("cp.async.bulk.tensor.3d.shared::cluster.global.tile.mbarrier::complete_tx::bytes [%0], [%1, {%2, %3, %4}], [%5];"
+      :
+      : "r"(__as_ptr_smem(__dstMem)),
+        "l"(__tensorMap),
+        "r"(__tensorCoords[0]),
+        "r"(__tensorCoords[1]),
+        "r"(__tensorCoords[2]),
+        "r"(__as_ptr_smem(__smem_bar))
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_cp_async_bulk_tensor_is_not_supported_before_SM_90__();
+#  endif
 }
 #endif // __cccl_ptx_isa >= 800
 
 /*
-// cp.async.bulk.tensor.3d.dst.src.tile.bulk_group [tensorMap, tensorCoords], [srcMem]; // 3c. PTX ISA 80, SM_90
+// cp.async.bulk.tensor.3d.dst.src.tile.mbarrier::complete_tx::bytes [dstMem], [tensorMap, tensorCoords], [smem_bar]; //
+PTX ISA 86, SM_90
+// .dst       = { .shared::cta }
+// .src       = { .global }
+template <typename = void>
+__device__ static inline void cp_async_bulk_tensor(
+  cuda::ptx::space_shared_t,
+  cuda::ptx::space_global_t,
+  void* dstMem,
+  const void* tensorMap,
+  const int32_t (&tensorCoords)[3],
+  uint64_t* smem_bar);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_cp_async_bulk_tensor_is_not_supported_before_SM_90__();
+template <typename = void>
+_CCCL_DEVICE static inline void cp_async_bulk_tensor(
+  space_shared_t,
+  space_global_t,
+  void* __dstMem,
+  const void* __tensorMap,
+  const _CUDA_VSTD::int32_t (&__tensorCoords)[3],
+  _CUDA_VSTD::uint64_t* __smem_bar)
+{
+// __space == space_shared (due to parameter type constraint)
+// __space == space_global (due to parameter type constraint)
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  asm("cp.async.bulk.tensor.3d.shared::cta.global.tile.mbarrier::complete_tx::bytes [%0], [%1, {%2, %3, %4}], [%5];"
+      :
+      : "r"(__as_ptr_smem(__dstMem)),
+        "l"(__tensorMap),
+        "r"(__tensorCoords[0]),
+        "r"(__tensorCoords[1]),
+        "r"(__tensorCoords[2]),
+        "r"(__as_ptr_smem(__smem_bar))
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_cp_async_bulk_tensor_is_not_supported_before_SM_90__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// cp.async.bulk.tensor.3d.dst.src.tile.mbarrier::complete_tx::bytes.cta_group [dstMem], [tensorMap, tensorCoords],
+[smem_bar]; // PTX ISA 86, SM_100a, SM_101a
+// .dst       = { .shared::cta }
+// .src       = { .global }
+// .cta_group = { .cta_group::1, .cta_group::2 }
+template <cuda::ptx::dot_cta_group Cta_Group>
+__device__ static inline void cp_async_bulk_tensor(
+  cuda::ptx::space_shared_t,
+  cuda::ptx::space_global_t,
+  cuda::ptx::cta_group_t<Cta_Group> cta_group,
+  void* dstMem,
+  const void* tensorMap,
+  const int32_t (&tensorCoords)[3],
+  uint64_t* smem_bar);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_cp_async_bulk_tensor_is_not_supported_before_SM_100a_SM_101a__();
+template <dot_cta_group _Cta_Group>
+_CCCL_DEVICE static inline void cp_async_bulk_tensor(
+  space_shared_t,
+  space_global_t,
+  cta_group_t<_Cta_Group> __cta_group,
+  void* __dstMem,
+  const void* __tensorMap,
+  const _CUDA_VSTD::int32_t (&__tensorCoords)[3],
+  _CUDA_VSTD::uint64_t* __smem_bar)
+{
+  // __space == space_shared (due to parameter type constraint)
+  // __space == space_global (due to parameter type constraint)
+  static_assert(__cta_group == cta_group_1 || __cta_group == cta_group_2, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  _CCCL_IF_CONSTEXPR (__cta_group == cta_group_1)
+  {
+    asm("cp.async.bulk.tensor.3d.shared::cta.global.tile.mbarrier::complete_tx::bytes.cta_group::1 [%0], [%1, {%2, %3, "
+        "%4}], [%5];"
+        :
+        : "r"(__as_ptr_smem(__dstMem)),
+          "l"(__tensorMap),
+          "r"(__tensorCoords[0]),
+          "r"(__tensorCoords[1]),
+          "r"(__tensorCoords[2]),
+          "r"(__as_ptr_smem(__smem_bar))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__cta_group == cta_group_2)
+  {
+    asm("cp.async.bulk.tensor.3d.shared::cta.global.tile.mbarrier::complete_tx::bytes.cta_group::2 [%0], [%1, {%2, %3, "
+        "%4}], [%5];"
+        :
+        : "r"(__as_ptr_smem(__dstMem)),
+          "l"(__tensorMap),
+          "r"(__tensorCoords[0]),
+          "r"(__tensorCoords[1]),
+          "r"(__tensorCoords[2]),
+          "r"(__as_ptr_smem(__smem_bar))
+        : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_cp_async_bulk_tensor_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// cp.async.bulk.tensor.3d.dst.src.tile.bulk_group [tensorMap, tensorCoords], [srcMem]; // PTX ISA 80, SM_90
 // .dst       = { .global }
 // .src       = { .shared::cta }
 template <typename = void>
@@ -219,25 +532,27 @@ _CCCL_DEVICE static inline void cp_async_bulk_tensor(
   const _CUDA_VSTD::int32_t (&__tensorCoords)[3],
   const void* __srcMem)
 {
-  // __space == space_global (due to parameter type constraint)
-  // __space == space_shared (due to parameter type constraint)
-  NV_IF_ELSE_TARGET(
-    NV_PROVIDES_SM_90,
-    (asm("cp.async.bulk.tensor.3d.global.shared::cta.tile.bulk_group [%0, {%1, %2, %3}], [%4]; // 3c." : : "l"(
-           __tensorMap),
-         "r"(__tensorCoords[0]),
-         "r"(__tensorCoords[1]),
-         "r"(__tensorCoords[2]),
-         "r"(__as_ptr_smem(__srcMem)) : "memory");),
-    (
-      // Unsupported architectures will have a linker error with a semi-decent error message
-      __cuda_ptx_cp_async_bulk_tensor_is_not_supported_before_SM_90__();));
+// __space == space_global (due to parameter type constraint)
+// __space == space_shared (due to parameter type constraint)
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  asm("cp.async.bulk.tensor.3d.global.shared::cta.tile.bulk_group [%0, {%1, %2, %3}], [%4];"
+      :
+      : "l"(__tensorMap),
+        "r"(__tensorCoords[0]),
+        "r"(__tensorCoords[1]),
+        "r"(__tensorCoords[2]),
+        "r"(__as_ptr_smem(__srcMem))
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_cp_async_bulk_tensor_is_not_supported_before_SM_90__();
+#  endif
 }
 #endif // __cccl_ptx_isa >= 800
 
 /*
-// cp.async.bulk.tensor.4d.dst.src.tile.mbarrier::complete_tx::bytes [dstMem], [tensorMap, tensorCoords], [smem_bar];//
-1d. PTX ISA 80, SM_90
+// cp.async.bulk.tensor.4d.dst.src.tile.mbarrier::complete_tx::bytes [dstMem], [tensorMap, tensorCoords], [smem_bar]; //
+PTX ISA 80, SM_90
 // .dst       = { .shared::cluster }
 // .src       = { .global }
 template <typename = void>
@@ -260,26 +575,141 @@ _CCCL_DEVICE static inline void cp_async_bulk_tensor(
   const _CUDA_VSTD::int32_t (&__tensorCoords)[4],
   _CUDA_VSTD::uint64_t* __smem_bar)
 {
-  // __space == space_cluster (due to parameter type constraint)
-  // __space == space_global (due to parameter type constraint)
-  NV_IF_ELSE_TARGET(
-    NV_PROVIDES_SM_90,
-    (asm("cp.async.bulk.tensor.4d.shared::cluster.global.tile.mbarrier::complete_tx::bytes [%0], [%1, {%2, %3, %4, "
-         "%5}], [%6];// 1d." : : "r"(__as_ptr_smem(__dstMem)),
-         "l"(__tensorMap),
-         "r"(__tensorCoords[0]),
-         "r"(__tensorCoords[1]),
-         "r"(__tensorCoords[2]),
-         "r"(__tensorCoords[3]),
-         "r"(__as_ptr_smem(__smem_bar)) : "memory");),
-    (
-      // Unsupported architectures will have a linker error with a semi-decent error message
-      __cuda_ptx_cp_async_bulk_tensor_is_not_supported_before_SM_90__();));
+// __space == space_cluster (due to parameter type constraint)
+// __space == space_global (due to parameter type constraint)
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  asm("cp.async.bulk.tensor.4d.shared::cluster.global.tile.mbarrier::complete_tx::bytes [%0], [%1, {%2, %3, %4, %5}], "
+      "[%6];"
+      :
+      : "r"(__as_ptr_smem(__dstMem)),
+        "l"(__tensorMap),
+        "r"(__tensorCoords[0]),
+        "r"(__tensorCoords[1]),
+        "r"(__tensorCoords[2]),
+        "r"(__tensorCoords[3]),
+        "r"(__as_ptr_smem(__smem_bar))
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_cp_async_bulk_tensor_is_not_supported_before_SM_90__();
+#  endif
 }
 #endif // __cccl_ptx_isa >= 800
 
 /*
-// cp.async.bulk.tensor.4d.dst.src.tile.bulk_group [tensorMap, tensorCoords], [srcMem]; // 3d. PTX ISA 80, SM_90
+// cp.async.bulk.tensor.4d.dst.src.tile.mbarrier::complete_tx::bytes [dstMem], [tensorMap, tensorCoords], [smem_bar]; //
+PTX ISA 86, SM_90
+// .dst       = { .shared::cta }
+// .src       = { .global }
+template <typename = void>
+__device__ static inline void cp_async_bulk_tensor(
+  cuda::ptx::space_shared_t,
+  cuda::ptx::space_global_t,
+  void* dstMem,
+  const void* tensorMap,
+  const int32_t (&tensorCoords)[4],
+  uint64_t* smem_bar);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_cp_async_bulk_tensor_is_not_supported_before_SM_90__();
+template <typename = void>
+_CCCL_DEVICE static inline void cp_async_bulk_tensor(
+  space_shared_t,
+  space_global_t,
+  void* __dstMem,
+  const void* __tensorMap,
+  const _CUDA_VSTD::int32_t (&__tensorCoords)[4],
+  _CUDA_VSTD::uint64_t* __smem_bar)
+{
+// __space == space_shared (due to parameter type constraint)
+// __space == space_global (due to parameter type constraint)
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  asm("cp.async.bulk.tensor.4d.shared::cta.global.tile.mbarrier::complete_tx::bytes [%0], [%1, {%2, %3, %4, %5}], [%6];"
+      :
+      : "r"(__as_ptr_smem(__dstMem)),
+        "l"(__tensorMap),
+        "r"(__tensorCoords[0]),
+        "r"(__tensorCoords[1]),
+        "r"(__tensorCoords[2]),
+        "r"(__tensorCoords[3]),
+        "r"(__as_ptr_smem(__smem_bar))
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_cp_async_bulk_tensor_is_not_supported_before_SM_90__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// cp.async.bulk.tensor.4d.dst.src.tile.mbarrier::complete_tx::bytes.cta_group [dstMem], [tensorMap, tensorCoords],
+[smem_bar]; // PTX ISA 86, SM_100a, SM_101a
+// .dst       = { .shared::cta }
+// .src       = { .global }
+// .cta_group = { .cta_group::1, .cta_group::2 }
+template <cuda::ptx::dot_cta_group Cta_Group>
+__device__ static inline void cp_async_bulk_tensor(
+  cuda::ptx::space_shared_t,
+  cuda::ptx::space_global_t,
+  cuda::ptx::cta_group_t<Cta_Group> cta_group,
+  void* dstMem,
+  const void* tensorMap,
+  const int32_t (&tensorCoords)[4],
+  uint64_t* smem_bar);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_cp_async_bulk_tensor_is_not_supported_before_SM_100a_SM_101a__();
+template <dot_cta_group _Cta_Group>
+_CCCL_DEVICE static inline void cp_async_bulk_tensor(
+  space_shared_t,
+  space_global_t,
+  cta_group_t<_Cta_Group> __cta_group,
+  void* __dstMem,
+  const void* __tensorMap,
+  const _CUDA_VSTD::int32_t (&__tensorCoords)[4],
+  _CUDA_VSTD::uint64_t* __smem_bar)
+{
+  // __space == space_shared (due to parameter type constraint)
+  // __space == space_global (due to parameter type constraint)
+  static_assert(__cta_group == cta_group_1 || __cta_group == cta_group_2, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  _CCCL_IF_CONSTEXPR (__cta_group == cta_group_1)
+  {
+    asm("cp.async.bulk.tensor.4d.shared::cta.global.tile.mbarrier::complete_tx::bytes.cta_group::1 [%0], [%1, {%2, %3, "
+        "%4, %5}], [%6];"
+        :
+        : "r"(__as_ptr_smem(__dstMem)),
+          "l"(__tensorMap),
+          "r"(__tensorCoords[0]),
+          "r"(__tensorCoords[1]),
+          "r"(__tensorCoords[2]),
+          "r"(__tensorCoords[3]),
+          "r"(__as_ptr_smem(__smem_bar))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__cta_group == cta_group_2)
+  {
+    asm("cp.async.bulk.tensor.4d.shared::cta.global.tile.mbarrier::complete_tx::bytes.cta_group::2 [%0], [%1, {%2, %3, "
+        "%4, %5}], [%6];"
+        :
+        : "r"(__as_ptr_smem(__dstMem)),
+          "l"(__tensorMap),
+          "r"(__tensorCoords[0]),
+          "r"(__tensorCoords[1]),
+          "r"(__tensorCoords[2]),
+          "r"(__tensorCoords[3]),
+          "r"(__as_ptr_smem(__smem_bar))
+        : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_cp_async_bulk_tensor_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// cp.async.bulk.tensor.4d.dst.src.tile.bulk_group [tensorMap, tensorCoords], [srcMem]; // PTX ISA 80, SM_90
 // .dst       = { .global }
 // .src       = { .shared::cta }
 template <typename = void>
@@ -300,26 +730,28 @@ _CCCL_DEVICE static inline void cp_async_bulk_tensor(
   const _CUDA_VSTD::int32_t (&__tensorCoords)[4],
   const void* __srcMem)
 {
-  // __space == space_global (due to parameter type constraint)
-  // __space == space_shared (due to parameter type constraint)
-  NV_IF_ELSE_TARGET(
-    NV_PROVIDES_SM_90,
-    (asm("cp.async.bulk.tensor.4d.global.shared::cta.tile.bulk_group [%0, {%1, %2, %3, %4}], [%5]; // 3d." : : "l"(
-           __tensorMap),
-         "r"(__tensorCoords[0]),
-         "r"(__tensorCoords[1]),
-         "r"(__tensorCoords[2]),
-         "r"(__tensorCoords[3]),
-         "r"(__as_ptr_smem(__srcMem)) : "memory");),
-    (
-      // Unsupported architectures will have a linker error with a semi-decent error message
-      __cuda_ptx_cp_async_bulk_tensor_is_not_supported_before_SM_90__();));
+// __space == space_global (due to parameter type constraint)
+// __space == space_shared (due to parameter type constraint)
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  asm("cp.async.bulk.tensor.4d.global.shared::cta.tile.bulk_group [%0, {%1, %2, %3, %4}], [%5];"
+      :
+      : "l"(__tensorMap),
+        "r"(__tensorCoords[0]),
+        "r"(__tensorCoords[1]),
+        "r"(__tensorCoords[2]),
+        "r"(__tensorCoords[3]),
+        "r"(__as_ptr_smem(__srcMem))
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_cp_async_bulk_tensor_is_not_supported_before_SM_90__();
+#  endif
 }
 #endif // __cccl_ptx_isa >= 800
 
 /*
-// cp.async.bulk.tensor.5d.dst.src.tile.mbarrier::complete_tx::bytes [dstMem], [tensorMap, tensorCoords], [smem_bar];//
-1e. PTX ISA 80, SM_90
+// cp.async.bulk.tensor.5d.dst.src.tile.mbarrier::complete_tx::bytes [dstMem], [tensorMap, tensorCoords], [smem_bar]; //
+PTX ISA 80, SM_90
 // .dst       = { .shared::cluster }
 // .src       = { .global }
 template <typename = void>
@@ -342,27 +774,146 @@ _CCCL_DEVICE static inline void cp_async_bulk_tensor(
   const _CUDA_VSTD::int32_t (&__tensorCoords)[5],
   _CUDA_VSTD::uint64_t* __smem_bar)
 {
-  // __space == space_cluster (due to parameter type constraint)
-  // __space == space_global (due to parameter type constraint)
-  NV_IF_ELSE_TARGET(
-    NV_PROVIDES_SM_90,
-    (asm("cp.async.bulk.tensor.5d.shared::cluster.global.tile.mbarrier::complete_tx::bytes [%0], [%1, {%2, %3, %4, %5, "
-         "%6}], [%7];// 1e." : : "r"(__as_ptr_smem(__dstMem)),
-         "l"(__tensorMap),
-         "r"(__tensorCoords[0]),
-         "r"(__tensorCoords[1]),
-         "r"(__tensorCoords[2]),
-         "r"(__tensorCoords[3]),
-         "r"(__tensorCoords[4]),
-         "r"(__as_ptr_smem(__smem_bar)) : "memory");),
-    (
-      // Unsupported architectures will have a linker error with a semi-decent error message
-      __cuda_ptx_cp_async_bulk_tensor_is_not_supported_before_SM_90__();));
+// __space == space_cluster (due to parameter type constraint)
+// __space == space_global (due to parameter type constraint)
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  asm("cp.async.bulk.tensor.5d.shared::cluster.global.tile.mbarrier::complete_tx::bytes [%0], [%1, {%2, %3, %4, %5, "
+      "%6}], [%7];"
+      :
+      : "r"(__as_ptr_smem(__dstMem)),
+        "l"(__tensorMap),
+        "r"(__tensorCoords[0]),
+        "r"(__tensorCoords[1]),
+        "r"(__tensorCoords[2]),
+        "r"(__tensorCoords[3]),
+        "r"(__tensorCoords[4]),
+        "r"(__as_ptr_smem(__smem_bar))
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_cp_async_bulk_tensor_is_not_supported_before_SM_90__();
+#  endif
 }
 #endif // __cccl_ptx_isa >= 800
 
 /*
-// cp.async.bulk.tensor.5d.dst.src.tile.bulk_group [tensorMap, tensorCoords], [srcMem]; // 3e. PTX ISA 80, SM_90
+// cp.async.bulk.tensor.5d.dst.src.tile.mbarrier::complete_tx::bytes [dstMem], [tensorMap, tensorCoords], [smem_bar]; //
+PTX ISA 86, SM_90
+// .dst       = { .shared::cta }
+// .src       = { .global }
+template <typename = void>
+__device__ static inline void cp_async_bulk_tensor(
+  cuda::ptx::space_shared_t,
+  cuda::ptx::space_global_t,
+  void* dstMem,
+  const void* tensorMap,
+  const int32_t (&tensorCoords)[5],
+  uint64_t* smem_bar);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_cp_async_bulk_tensor_is_not_supported_before_SM_90__();
+template <typename = void>
+_CCCL_DEVICE static inline void cp_async_bulk_tensor(
+  space_shared_t,
+  space_global_t,
+  void* __dstMem,
+  const void* __tensorMap,
+  const _CUDA_VSTD::int32_t (&__tensorCoords)[5],
+  _CUDA_VSTD::uint64_t* __smem_bar)
+{
+// __space == space_shared (due to parameter type constraint)
+// __space == space_global (due to parameter type constraint)
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  asm("cp.async.bulk.tensor.5d.shared::cta.global.tile.mbarrier::complete_tx::bytes [%0], [%1, {%2, %3, %4, %5, %6}], "
+      "[%7];"
+      :
+      : "r"(__as_ptr_smem(__dstMem)),
+        "l"(__tensorMap),
+        "r"(__tensorCoords[0]),
+        "r"(__tensorCoords[1]),
+        "r"(__tensorCoords[2]),
+        "r"(__tensorCoords[3]),
+        "r"(__tensorCoords[4]),
+        "r"(__as_ptr_smem(__smem_bar))
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_cp_async_bulk_tensor_is_not_supported_before_SM_90__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// cp.async.bulk.tensor.5d.dst.src.tile.mbarrier::complete_tx::bytes.cta_group [dstMem], [tensorMap, tensorCoords],
+[smem_bar]; // PTX ISA 86, SM_100a, SM_101a
+// .dst       = { .shared::cta }
+// .src       = { .global }
+// .cta_group = { .cta_group::1, .cta_group::2 }
+template <cuda::ptx::dot_cta_group Cta_Group>
+__device__ static inline void cp_async_bulk_tensor(
+  cuda::ptx::space_shared_t,
+  cuda::ptx::space_global_t,
+  cuda::ptx::cta_group_t<Cta_Group> cta_group,
+  void* dstMem,
+  const void* tensorMap,
+  const int32_t (&tensorCoords)[5],
+  uint64_t* smem_bar);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_cp_async_bulk_tensor_is_not_supported_before_SM_100a_SM_101a__();
+template <dot_cta_group _Cta_Group>
+_CCCL_DEVICE static inline void cp_async_bulk_tensor(
+  space_shared_t,
+  space_global_t,
+  cta_group_t<_Cta_Group> __cta_group,
+  void* __dstMem,
+  const void* __tensorMap,
+  const _CUDA_VSTD::int32_t (&__tensorCoords)[5],
+  _CUDA_VSTD::uint64_t* __smem_bar)
+{
+  // __space == space_shared (due to parameter type constraint)
+  // __space == space_global (due to parameter type constraint)
+  static_assert(__cta_group == cta_group_1 || __cta_group == cta_group_2, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  _CCCL_IF_CONSTEXPR (__cta_group == cta_group_1)
+  {
+    asm("cp.async.bulk.tensor.5d.shared::cta.global.tile.mbarrier::complete_tx::bytes.cta_group::1 [%0], [%1, {%2, %3, "
+        "%4, %5, %6}], [%7];"
+        :
+        : "r"(__as_ptr_smem(__dstMem)),
+          "l"(__tensorMap),
+          "r"(__tensorCoords[0]),
+          "r"(__tensorCoords[1]),
+          "r"(__tensorCoords[2]),
+          "r"(__tensorCoords[3]),
+          "r"(__tensorCoords[4]),
+          "r"(__as_ptr_smem(__smem_bar))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__cta_group == cta_group_2)
+  {
+    asm("cp.async.bulk.tensor.5d.shared::cta.global.tile.mbarrier::complete_tx::bytes.cta_group::2 [%0], [%1, {%2, %3, "
+        "%4, %5, %6}], [%7];"
+        :
+        : "r"(__as_ptr_smem(__dstMem)),
+          "l"(__tensorMap),
+          "r"(__tensorCoords[0]),
+          "r"(__tensorCoords[1]),
+          "r"(__tensorCoords[2]),
+          "r"(__tensorCoords[3]),
+          "r"(__tensorCoords[4]),
+          "r"(__as_ptr_smem(__smem_bar))
+        : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_cp_async_bulk_tensor_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// cp.async.bulk.tensor.5d.dst.src.tile.bulk_group [tensorMap, tensorCoords], [srcMem]; // PTX ISA 80, SM_90
 // .dst       = { .global }
 // .src       = { .shared::cta }
 template <typename = void>
@@ -383,21 +934,23 @@ _CCCL_DEVICE static inline void cp_async_bulk_tensor(
   const _CUDA_VSTD::int32_t (&__tensorCoords)[5],
   const void* __srcMem)
 {
-  // __space == space_global (due to parameter type constraint)
-  // __space == space_shared (due to parameter type constraint)
-  NV_IF_ELSE_TARGET(
-    NV_PROVIDES_SM_90,
-    (asm("cp.async.bulk.tensor.5d.global.shared::cta.tile.bulk_group [%0, {%1, %2, %3, %4, %5}], [%6]; // 3e." : : "l"(
-           __tensorMap),
-         "r"(__tensorCoords[0]),
-         "r"(__tensorCoords[1]),
-         "r"(__tensorCoords[2]),
-         "r"(__tensorCoords[3]),
-         "r"(__tensorCoords[4]),
-         "r"(__as_ptr_smem(__srcMem)) : "memory");),
-    (
-      // Unsupported architectures will have a linker error with a semi-decent error message
-      __cuda_ptx_cp_async_bulk_tensor_is_not_supported_before_SM_90__();));
+// __space == space_global (due to parameter type constraint)
+// __space == space_shared (due to parameter type constraint)
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  asm("cp.async.bulk.tensor.5d.global.shared::cta.tile.bulk_group [%0, {%1, %2, %3, %4, %5}], [%6];"
+      :
+      : "l"(__tensorMap),
+        "r"(__tensorCoords[0]),
+        "r"(__tensorCoords[1]),
+        "r"(__tensorCoords[2]),
+        "r"(__tensorCoords[3]),
+        "r"(__tensorCoords[4]),
+        "r"(__as_ptr_smem(__srcMem))
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_cp_async_bulk_tensor_is_not_supported_before_SM_90__();
+#  endif
 }
 #endif // __cccl_ptx_isa >= 800
 
diff --git a/libcudacxx/include/cuda/__ptx/instructions/generated/cp_async_bulk_tensor_gather_scatter.h b/libcudacxx/include/cuda/__ptx/instructions/generated/cp_async_bulk_tensor_gather_scatter.h
new file mode 100644
index 00000000000..f376f1b48c3
--- /dev/null
+++ b/libcudacxx/include/cuda/__ptx/instructions/generated/cp_async_bulk_tensor_gather_scatter.h
@@ -0,0 +1,288 @@
+// This file was automatically generated. Do not edit.
+
+#ifndef _CUDA_PTX_GENERATED_CP_ASYNC_BULK_TENSOR_GATHER_SCATTER_H_
+#define _CUDA_PTX_GENERATED_CP_ASYNC_BULK_TENSOR_GATHER_SCATTER_H_
+
+/*
+// cp.async.bulk.tensor.2d.dst.src.tile::gather4.mbarrier::complete_tx::bytes [dstMem], [tensorMap, tensorCoords],
+[smem_bar]; // PTX ISA 86, SM_100
+// .dst       = { .shared::cta }
+// .src       = { .global }
+template <typename = void>
+__device__ static inline void cp_async_bulk_tensor_tile_gather4(
+  cuda::ptx::space_shared_t,
+  cuda::ptx::space_global_t,
+  void* dstMem,
+  const void* tensorMap,
+  const int32_t (&tensorCoords)[5],
+  uint64_t* smem_bar);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_cp_async_bulk_tensor_tile_gather4_is_not_supported_before_SM_100__();
+template <typename = void>
+_CCCL_DEVICE static inline void cp_async_bulk_tensor_tile_gather4(
+  space_shared_t,
+  space_global_t,
+  void* __dstMem,
+  const void* __tensorMap,
+  const _CUDA_VSTD::int32_t (&__tensorCoords)[5],
+  _CUDA_VSTD::uint64_t* __smem_bar)
+{
+// __space == space_shared (due to parameter type constraint)
+// __space == space_global (due to parameter type constraint)
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 1000
+  asm("cp.async.bulk.tensor.2d.shared::cta.global.tile::gather4.mbarrier::complete_tx::bytes [%0], [%1, {%2, %3, %4, "
+      "%5, %6}], [%7];"
+      :
+      : "r"(__as_ptr_smem(__dstMem)),
+        "l"(__tensorMap),
+        "r"(__tensorCoords[0]),
+        "r"(__tensorCoords[1]),
+        "r"(__tensorCoords[2]),
+        "r"(__tensorCoords[3]),
+        "r"(__tensorCoords[4]),
+        "r"(__as_ptr_smem(__smem_bar))
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_cp_async_bulk_tensor_tile_gather4_is_not_supported_before_SM_100__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// cp.async.bulk.tensor.2d.dst.src.tile::gather4.mbarrier::complete_tx::bytes.cta_group [dstMem], [tensorMap,
+tensorCoords], [smem_bar]; // PTX ISA 86, SM_100a, SM_101a
+// .dst       = { .shared::cta }
+// .src       = { .global }
+// .cta_group = { .cta_group::1, .cta_group::2 }
+template <cuda::ptx::dot_cta_group Cta_Group>
+__device__ static inline void cp_async_bulk_tensor_tile_gather4(
+  cuda::ptx::space_shared_t,
+  cuda::ptx::space_global_t,
+  cuda::ptx::cta_group_t<Cta_Group> cta_group,
+  void* dstMem,
+  const void* tensorMap,
+  const int32_t (&tensorCoords)[5],
+  uint64_t* smem_bar);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_cp_async_bulk_tensor_tile_gather4_is_not_supported_before_SM_100a_SM_101a__();
+template <dot_cta_group _Cta_Group>
+_CCCL_DEVICE static inline void cp_async_bulk_tensor_tile_gather4(
+  space_shared_t,
+  space_global_t,
+  cta_group_t<_Cta_Group> __cta_group,
+  void* __dstMem,
+  const void* __tensorMap,
+  const _CUDA_VSTD::int32_t (&__tensorCoords)[5],
+  _CUDA_VSTD::uint64_t* __smem_bar)
+{
+  // __space == space_shared (due to parameter type constraint)
+  // __space == space_global (due to parameter type constraint)
+  static_assert(__cta_group == cta_group_1 || __cta_group == cta_group_2, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  _CCCL_IF_CONSTEXPR (__cta_group == cta_group_1)
+  {
+    asm("cp.async.bulk.tensor.2d.shared::cta.global.tile::gather4.mbarrier::complete_tx::bytes.cta_group::1 [%0], [%1, "
+        "{%2, %3, %4, %5, %6}], [%7];"
+        :
+        : "r"(__as_ptr_smem(__dstMem)),
+          "l"(__tensorMap),
+          "r"(__tensorCoords[0]),
+          "r"(__tensorCoords[1]),
+          "r"(__tensorCoords[2]),
+          "r"(__tensorCoords[3]),
+          "r"(__tensorCoords[4]),
+          "r"(__as_ptr_smem(__smem_bar))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__cta_group == cta_group_2)
+  {
+    asm("cp.async.bulk.tensor.2d.shared::cta.global.tile::gather4.mbarrier::complete_tx::bytes.cta_group::2 [%0], [%1, "
+        "{%2, %3, %4, %5, %6}], [%7];"
+        :
+        : "r"(__as_ptr_smem(__dstMem)),
+          "l"(__tensorMap),
+          "r"(__tensorCoords[0]),
+          "r"(__tensorCoords[1]),
+          "r"(__tensorCoords[2]),
+          "r"(__tensorCoords[3]),
+          "r"(__tensorCoords[4]),
+          "r"(__as_ptr_smem(__smem_bar))
+        : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_cp_async_bulk_tensor_tile_gather4_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// cp.async.bulk.tensor.2d.dst.src.tile::gather4.mbarrier::complete_tx::bytes.multicast::cluster [dstMem], [tensorMap,
+tensorCoords], [smem_bar], ctaMask; // PTX ISA 86, SM_100a, SM_101a
+// .dst       = { .shared::cluster }
+// .src       = { .global }
+template <typename = void>
+__device__ static inline void cp_async_bulk_tensor_tile_gather4(
+  cuda::ptx::space_cluster_t,
+  cuda::ptx::space_global_t,
+  void* dstMem,
+  const void* tensorMap,
+  const int32_t (&tensorCoords)[5],
+  uint64_t* smem_bar,
+  const uint16_t& ctaMask);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_cp_async_bulk_tensor_tile_gather4_is_not_supported_before_SM_100a_SM_101a__();
+template <typename = void>
+_CCCL_DEVICE static inline void cp_async_bulk_tensor_tile_gather4(
+  space_cluster_t,
+  space_global_t,
+  void* __dstMem,
+  const void* __tensorMap,
+  const _CUDA_VSTD::int32_t (&__tensorCoords)[5],
+  _CUDA_VSTD::uint64_t* __smem_bar,
+  const _CUDA_VSTD::uint16_t& __ctaMask)
+{
+// __space == space_cluster (due to parameter type constraint)
+// __space == space_global (due to parameter type constraint)
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  asm("cp.async.bulk.tensor.2d.shared::cluster.global.tile::gather4.mbarrier::complete_tx::bytes.multicast::cluster "
+      "[%0], [%1, {%2, %3, %4, %5, %6}], [%7], %8;"
+      :
+      : "r"(__as_ptr_smem(__dstMem)),
+        "l"(__tensorMap),
+        "r"(__tensorCoords[0]),
+        "r"(__tensorCoords[1]),
+        "r"(__tensorCoords[2]),
+        "r"(__tensorCoords[3]),
+        "r"(__tensorCoords[4]),
+        "r"(__as_ptr_smem(__smem_bar)),
+        "h"(__ctaMask)
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_cp_async_bulk_tensor_tile_gather4_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// cp.async.bulk.tensor.2d.dst.src.tile::gather4.mbarrier::complete_tx::bytes.multicast::cluster.cta_group [dstMem],
+[tensorMap, tensorCoords], [smem_bar], ctaMask; // PTX ISA 86, SM_100a, SM_101a
+// .dst       = { .shared::cluster }
+// .src       = { .global }
+// .cta_group = { .cta_group::1, .cta_group::2 }
+template <cuda::ptx::dot_cta_group Cta_Group>
+__device__ static inline void cp_async_bulk_tensor_tile_gather4(
+  cuda::ptx::space_cluster_t,
+  cuda::ptx::space_global_t,
+  cuda::ptx::cta_group_t<Cta_Group> cta_group,
+  void* dstMem,
+  const void* tensorMap,
+  const int32_t (&tensorCoords)[5],
+  uint64_t* smem_bar,
+  const uint16_t& ctaMask);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_cp_async_bulk_tensor_tile_gather4_is_not_supported_before_SM_100a_SM_101a__();
+template <dot_cta_group _Cta_Group>
+_CCCL_DEVICE static inline void cp_async_bulk_tensor_tile_gather4(
+  space_cluster_t,
+  space_global_t,
+  cta_group_t<_Cta_Group> __cta_group,
+  void* __dstMem,
+  const void* __tensorMap,
+  const _CUDA_VSTD::int32_t (&__tensorCoords)[5],
+  _CUDA_VSTD::uint64_t* __smem_bar,
+  const _CUDA_VSTD::uint16_t& __ctaMask)
+{
+  // __space == space_cluster (due to parameter type constraint)
+  // __space == space_global (due to parameter type constraint)
+  static_assert(__cta_group == cta_group_1 || __cta_group == cta_group_2, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  _CCCL_IF_CONSTEXPR (__cta_group == cta_group_1)
+  {
+    asm("cp.async.bulk.tensor.2d.shared::cluster.global.tile::gather4.mbarrier::complete_tx::bytes.multicast::cluster."
+        "cta_group::1 [%0], [%1, {%2, %3, %4, %5, %6}], [%7], %8;"
+        :
+        : "r"(__as_ptr_smem(__dstMem)),
+          "l"(__tensorMap),
+          "r"(__tensorCoords[0]),
+          "r"(__tensorCoords[1]),
+          "r"(__tensorCoords[2]),
+          "r"(__tensorCoords[3]),
+          "r"(__tensorCoords[4]),
+          "r"(__as_ptr_smem(__smem_bar)),
+          "h"(__ctaMask)
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__cta_group == cta_group_2)
+  {
+    asm("cp.async.bulk.tensor.2d.shared::cluster.global.tile::gather4.mbarrier::complete_tx::bytes.multicast::cluster."
+        "cta_group::2 [%0], [%1, {%2, %3, %4, %5, %6}], [%7], %8;"
+        :
+        : "r"(__as_ptr_smem(__dstMem)),
+          "l"(__tensorMap),
+          "r"(__tensorCoords[0]),
+          "r"(__tensorCoords[1]),
+          "r"(__tensorCoords[2]),
+          "r"(__tensorCoords[3]),
+          "r"(__tensorCoords[4]),
+          "r"(__as_ptr_smem(__smem_bar)),
+          "h"(__ctaMask)
+        : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_cp_async_bulk_tensor_tile_gather4_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// cp.async.bulk.tensor.2d.dst.src.tile::scatter4.bulk_group [tensorMap, tensorCoords], [srcMem]; // PTX ISA 80,
+SM_100a, SM_101a
+// .dst       = { .global }
+// .src       = { .shared::cta }
+template <typename = void>
+__device__ static inline void cp_async_bulk_tensor_tile_scatter4(
+  cuda::ptx::space_global_t,
+  cuda::ptx::space_shared_t,
+  const void* tensorMap,
+  const int32_t (&tensorCoords)[5],
+  const void* srcMem);
+*/
+#if __cccl_ptx_isa >= 800
+extern "C" _CCCL_DEVICE void __cuda_ptx_cp_async_bulk_tensor_tile_scatter4_is_not_supported_before_SM_100a_SM_101a__();
+template <typename = void>
+_CCCL_DEVICE static inline void cp_async_bulk_tensor_tile_scatter4(
+  space_global_t,
+  space_shared_t,
+  const void* __tensorMap,
+  const _CUDA_VSTD::int32_t (&__tensorCoords)[5],
+  const void* __srcMem)
+{
+// __space == space_global (due to parameter type constraint)
+// __space == space_shared (due to parameter type constraint)
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  asm("cp.async.bulk.tensor.2d.global.shared::cta.tile::scatter4.bulk_group [%0, {%1, %2, %3, %4, %5}], [%6];"
+      :
+      : "l"(__tensorMap),
+        "r"(__tensorCoords[0]),
+        "r"(__tensorCoords[1]),
+        "r"(__tensorCoords[2]),
+        "r"(__tensorCoords[3]),
+        "r"(__tensorCoords[4]),
+        "r"(__as_ptr_smem(__srcMem))
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_cp_async_bulk_tensor_tile_scatter4_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 800
+
+#endif // _CUDA_PTX_GENERATED_CP_ASYNC_BULK_TENSOR_GATHER_SCATTER_H_
diff --git a/libcudacxx/include/cuda/__ptx/instructions/generated/cp_async_bulk_tensor_multicast.h b/libcudacxx/include/cuda/__ptx/instructions/generated/cp_async_bulk_tensor_multicast.h
index 56c199d39ff..b0d845b92a0 100644
--- a/libcudacxx/include/cuda/__ptx/instructions/generated/cp_async_bulk_tensor_multicast.h
+++ b/libcudacxx/include/cuda/__ptx/instructions/generated/cp_async_bulk_tensor_multicast.h
@@ -5,7 +5,7 @@
 
 /*
 // cp.async.bulk.tensor.1d.dst.src.tile.mbarrier::complete_tx::bytes.multicast::cluster [dstMem], [tensorMap,
-tensorCoords], [smem_bar], ctaMask; // 2a. PTX ISA 80, SM_90a
+tensorCoords], [smem_bar], ctaMask; // PTX ISA 80, SM_90a, SM_100a, SM_101a
 // .dst       = { .shared::cluster }
 // .src       = { .global }
 template <typename = void>
@@ -19,7 +19,7 @@ __device__ static inline void cp_async_bulk_tensor(
   const uint16_t& ctaMask);
 */
 #if __cccl_ptx_isa >= 800
-extern "C" _CCCL_DEVICE void __cuda_ptx_cp_async_bulk_tensor_is_not_supported_before_SM_90a__();
+extern "C" _CCCL_DEVICE void __cuda_ptx_cp_async_bulk_tensor_is_not_supported_before_SM_90a_SM_100a_SM_101a__();
 template <typename = void>
 _CCCL_DEVICE static inline void cp_async_bulk_tensor(
   space_cluster_t,
@@ -29,26 +29,95 @@ _CCCL_DEVICE static inline void cp_async_bulk_tensor(
   const _CUDA_VSTD::int32_t (&__tensorCoords)[1],
   _CUDA_VSTD::uint64_t* __smem_bar,
   const _CUDA_VSTD::uint16_t& __ctaMask)
+{
+// __space == space_cluster (due to parameter type constraint)
+// __space == space_global (due to parameter type constraint)
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM90_ALL || __CUDA_ARCH_FEAT_SM100_ALL \
+    || __CUDA_ARCH_FEAT_SM101_ALL
+  asm("cp.async.bulk.tensor.1d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.multicast::cluster [%0], [%1, "
+      "{%2}], [%3], %4;"
+      :
+      : "r"(__as_ptr_smem(__dstMem)),
+        "l"(__tensorMap),
+        "r"(__tensorCoords[0]),
+        "r"(__as_ptr_smem(__smem_bar)),
+        "h"(__ctaMask)
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_cp_async_bulk_tensor_is_not_supported_before_SM_90a_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 800
+
+/*
+// cp.async.bulk.tensor.1d.dst.src.tile.mbarrier::complete_tx::bytes.multicast::cluster.cta_group [dstMem], [tensorMap,
+tensorCoords], [smem_bar], ctaMask; // PTX ISA 80, SM_100a, SM_101a
+// .dst       = { .shared::cluster }
+// .src       = { .global }
+// .cta_group = { .cta_group::1, .cta_group::2 }
+template <cuda::ptx::dot_cta_group Cta_Group>
+__device__ static inline void cp_async_bulk_tensor(
+  cuda::ptx::space_cluster_t,
+  cuda::ptx::space_global_t,
+  cuda::ptx::cta_group_t<Cta_Group> cta_group,
+  void* dstMem,
+  const void* tensorMap,
+  const int32_t (&tensorCoords)[1],
+  uint64_t* smem_bar,
+  const uint16_t& ctaMask);
+*/
+#if __cccl_ptx_isa >= 800
+extern "C" _CCCL_DEVICE void __cuda_ptx_cp_async_bulk_tensor_is_not_supported_before_SM_100a_SM_101a__();
+template <dot_cta_group _Cta_Group>
+_CCCL_DEVICE static inline void cp_async_bulk_tensor(
+  space_cluster_t,
+  space_global_t,
+  cta_group_t<_Cta_Group> __cta_group,
+  void* __dstMem,
+  const void* __tensorMap,
+  const _CUDA_VSTD::int32_t (&__tensorCoords)[1],
+  _CUDA_VSTD::uint64_t* __smem_bar,
+  const _CUDA_VSTD::uint16_t& __ctaMask)
 {
   // __space == space_cluster (due to parameter type constraint)
   // __space == space_global (due to parameter type constraint)
-  NV_IF_ELSE_TARGET(
-    NV_HAS_FEATURE_SM_90a,
-    (asm("cp.async.bulk.tensor.1d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.multicast::cluster [%0], "
-         "[%1, {%2}], [%3], %4; // 2a." : : "r"(__as_ptr_smem(__dstMem)),
-         "l"(__tensorMap),
-         "r"(__tensorCoords[0]),
-         "r"(__as_ptr_smem(__smem_bar)),
-         "h"(__ctaMask) : "memory");),
-    (
-      // Unsupported architectures will have a linker error with a semi-decent error message
-      __cuda_ptx_cp_async_bulk_tensor_is_not_supported_before_SM_90a__();));
+  static_assert(__cta_group == cta_group_1 || __cta_group == cta_group_2, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  _CCCL_IF_CONSTEXPR (__cta_group == cta_group_1)
+  {
+    asm("cp.async.bulk.tensor.1d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.multicast::cluster.cta_group:"
+        ":1 [%0], [%1, {%2}], [%3], %4;"
+        :
+        : "r"(__as_ptr_smem(__dstMem)),
+          "l"(__tensorMap),
+          "r"(__tensorCoords[0]),
+          "r"(__as_ptr_smem(__smem_bar)),
+          "h"(__ctaMask)
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__cta_group == cta_group_2)
+  {
+    asm("cp.async.bulk.tensor.1d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.multicast::cluster.cta_group:"
+        ":2 [%0], [%1, {%2}], [%3], %4;"
+        :
+        : "r"(__as_ptr_smem(__dstMem)),
+          "l"(__tensorMap),
+          "r"(__tensorCoords[0]),
+          "r"(__as_ptr_smem(__smem_bar)),
+          "h"(__ctaMask)
+        : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_cp_async_bulk_tensor_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
 }
 #endif // __cccl_ptx_isa >= 800
 
 /*
 // cp.async.bulk.tensor.2d.dst.src.tile.mbarrier::complete_tx::bytes.multicast::cluster [dstMem], [tensorMap,
-tensorCoords], [smem_bar], ctaMask; // 2b. PTX ISA 80, SM_90a
+tensorCoords], [smem_bar], ctaMask; // PTX ISA 80, SM_90a, SM_100a, SM_101a
 // .dst       = { .shared::cluster }
 // .src       = { .global }
 template <typename = void>
@@ -62,7 +131,7 @@ __device__ static inline void cp_async_bulk_tensor(
   const uint16_t& ctaMask);
 */
 #if __cccl_ptx_isa >= 800
-extern "C" _CCCL_DEVICE void __cuda_ptx_cp_async_bulk_tensor_is_not_supported_before_SM_90a__();
+extern "C" _CCCL_DEVICE void __cuda_ptx_cp_async_bulk_tensor_is_not_supported_before_SM_90a_SM_100a_SM_101a__();
 template <typename = void>
 _CCCL_DEVICE static inline void cp_async_bulk_tensor(
   space_cluster_t,
@@ -72,27 +141,98 @@ _CCCL_DEVICE static inline void cp_async_bulk_tensor(
   const _CUDA_VSTD::int32_t (&__tensorCoords)[2],
   _CUDA_VSTD::uint64_t* __smem_bar,
   const _CUDA_VSTD::uint16_t& __ctaMask)
+{
+// __space == space_cluster (due to parameter type constraint)
+// __space == space_global (due to parameter type constraint)
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM90_ALL || __CUDA_ARCH_FEAT_SM100_ALL \
+    || __CUDA_ARCH_FEAT_SM101_ALL
+  asm("cp.async.bulk.tensor.2d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.multicast::cluster [%0], [%1, "
+      "{%2, %3}], [%4], %5;"
+      :
+      : "r"(__as_ptr_smem(__dstMem)),
+        "l"(__tensorMap),
+        "r"(__tensorCoords[0]),
+        "r"(__tensorCoords[1]),
+        "r"(__as_ptr_smem(__smem_bar)),
+        "h"(__ctaMask)
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_cp_async_bulk_tensor_is_not_supported_before_SM_90a_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 800
+
+/*
+// cp.async.bulk.tensor.2d.dst.src.tile.mbarrier::complete_tx::bytes.multicast::cluster.cta_group [dstMem], [tensorMap,
+tensorCoords], [smem_bar], ctaMask; // PTX ISA 80, SM_100a, SM_101a
+// .dst       = { .shared::cluster }
+// .src       = { .global }
+// .cta_group = { .cta_group::1, .cta_group::2 }
+template <cuda::ptx::dot_cta_group Cta_Group>
+__device__ static inline void cp_async_bulk_tensor(
+  cuda::ptx::space_cluster_t,
+  cuda::ptx::space_global_t,
+  cuda::ptx::cta_group_t<Cta_Group> cta_group,
+  void* dstMem,
+  const void* tensorMap,
+  const int32_t (&tensorCoords)[2],
+  uint64_t* smem_bar,
+  const uint16_t& ctaMask);
+*/
+#if __cccl_ptx_isa >= 800
+extern "C" _CCCL_DEVICE void __cuda_ptx_cp_async_bulk_tensor_is_not_supported_before_SM_100a_SM_101a__();
+template <dot_cta_group _Cta_Group>
+_CCCL_DEVICE static inline void cp_async_bulk_tensor(
+  space_cluster_t,
+  space_global_t,
+  cta_group_t<_Cta_Group> __cta_group,
+  void* __dstMem,
+  const void* __tensorMap,
+  const _CUDA_VSTD::int32_t (&__tensorCoords)[2],
+  _CUDA_VSTD::uint64_t* __smem_bar,
+  const _CUDA_VSTD::uint16_t& __ctaMask)
 {
   // __space == space_cluster (due to parameter type constraint)
   // __space == space_global (due to parameter type constraint)
-  NV_IF_ELSE_TARGET(
-    NV_HAS_FEATURE_SM_90a,
-    (asm("cp.async.bulk.tensor.2d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.multicast::cluster [%0], "
-         "[%1, {%2, %3}], [%4], %5; // 2b." : : "r"(__as_ptr_smem(__dstMem)),
-         "l"(__tensorMap),
-         "r"(__tensorCoords[0]),
-         "r"(__tensorCoords[1]),
-         "r"(__as_ptr_smem(__smem_bar)),
-         "h"(__ctaMask) : "memory");),
-    (
-      // Unsupported architectures will have a linker error with a semi-decent error message
-      __cuda_ptx_cp_async_bulk_tensor_is_not_supported_before_SM_90a__();));
+  static_assert(__cta_group == cta_group_1 || __cta_group == cta_group_2, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  _CCCL_IF_CONSTEXPR (__cta_group == cta_group_1)
+  {
+    asm("cp.async.bulk.tensor.2d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.multicast::cluster.cta_group:"
+        ":1 [%0], [%1, {%2, %3}], [%4], %5;"
+        :
+        : "r"(__as_ptr_smem(__dstMem)),
+          "l"(__tensorMap),
+          "r"(__tensorCoords[0]),
+          "r"(__tensorCoords[1]),
+          "r"(__as_ptr_smem(__smem_bar)),
+          "h"(__ctaMask)
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__cta_group == cta_group_2)
+  {
+    asm("cp.async.bulk.tensor.2d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.multicast::cluster.cta_group:"
+        ":2 [%0], [%1, {%2, %3}], [%4], %5;"
+        :
+        : "r"(__as_ptr_smem(__dstMem)),
+          "l"(__tensorMap),
+          "r"(__tensorCoords[0]),
+          "r"(__tensorCoords[1]),
+          "r"(__as_ptr_smem(__smem_bar)),
+          "h"(__ctaMask)
+        : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_cp_async_bulk_tensor_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
 }
 #endif // __cccl_ptx_isa >= 800
 
 /*
 // cp.async.bulk.tensor.3d.dst.src.tile.mbarrier::complete_tx::bytes.multicast::cluster [dstMem], [tensorMap,
-tensorCoords], [smem_bar], ctaMask; // 2c. PTX ISA 80, SM_90a
+tensorCoords], [smem_bar], ctaMask; // PTX ISA 80, SM_90a, SM_100a, SM_101a
 // .dst       = { .shared::cluster }
 // .src       = { .global }
 template <typename = void>
@@ -106,7 +246,7 @@ __device__ static inline void cp_async_bulk_tensor(
   const uint16_t& ctaMask);
 */
 #if __cccl_ptx_isa >= 800
-extern "C" _CCCL_DEVICE void __cuda_ptx_cp_async_bulk_tensor_is_not_supported_before_SM_90a__();
+extern "C" _CCCL_DEVICE void __cuda_ptx_cp_async_bulk_tensor_is_not_supported_before_SM_90a_SM_100a_SM_101a__();
 template <typename = void>
 _CCCL_DEVICE static inline void cp_async_bulk_tensor(
   space_cluster_t,
@@ -116,28 +256,101 @@ _CCCL_DEVICE static inline void cp_async_bulk_tensor(
   const _CUDA_VSTD::int32_t (&__tensorCoords)[3],
   _CUDA_VSTD::uint64_t* __smem_bar,
   const _CUDA_VSTD::uint16_t& __ctaMask)
+{
+// __space == space_cluster (due to parameter type constraint)
+// __space == space_global (due to parameter type constraint)
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM90_ALL || __CUDA_ARCH_FEAT_SM100_ALL \
+    || __CUDA_ARCH_FEAT_SM101_ALL
+  asm("cp.async.bulk.tensor.3d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.multicast::cluster [%0], [%1, "
+      "{%2, %3, %4}], [%5], %6;"
+      :
+      : "r"(__as_ptr_smem(__dstMem)),
+        "l"(__tensorMap),
+        "r"(__tensorCoords[0]),
+        "r"(__tensorCoords[1]),
+        "r"(__tensorCoords[2]),
+        "r"(__as_ptr_smem(__smem_bar)),
+        "h"(__ctaMask)
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_cp_async_bulk_tensor_is_not_supported_before_SM_90a_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 800
+
+/*
+// cp.async.bulk.tensor.3d.dst.src.tile.mbarrier::complete_tx::bytes.multicast::cluster.cta_group [dstMem], [tensorMap,
+tensorCoords], [smem_bar], ctaMask; // PTX ISA 80, SM_100a, SM_101a
+// .dst       = { .shared::cluster }
+// .src       = { .global }
+// .cta_group = { .cta_group::1, .cta_group::2 }
+template <cuda::ptx::dot_cta_group Cta_Group>
+__device__ static inline void cp_async_bulk_tensor(
+  cuda::ptx::space_cluster_t,
+  cuda::ptx::space_global_t,
+  cuda::ptx::cta_group_t<Cta_Group> cta_group,
+  void* dstMem,
+  const void* tensorMap,
+  const int32_t (&tensorCoords)[3],
+  uint64_t* smem_bar,
+  const uint16_t& ctaMask);
+*/
+#if __cccl_ptx_isa >= 800
+extern "C" _CCCL_DEVICE void __cuda_ptx_cp_async_bulk_tensor_is_not_supported_before_SM_100a_SM_101a__();
+template <dot_cta_group _Cta_Group>
+_CCCL_DEVICE static inline void cp_async_bulk_tensor(
+  space_cluster_t,
+  space_global_t,
+  cta_group_t<_Cta_Group> __cta_group,
+  void* __dstMem,
+  const void* __tensorMap,
+  const _CUDA_VSTD::int32_t (&__tensorCoords)[3],
+  _CUDA_VSTD::uint64_t* __smem_bar,
+  const _CUDA_VSTD::uint16_t& __ctaMask)
 {
   // __space == space_cluster (due to parameter type constraint)
   // __space == space_global (due to parameter type constraint)
-  NV_IF_ELSE_TARGET(
-    NV_HAS_FEATURE_SM_90a,
-    (asm("cp.async.bulk.tensor.3d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.multicast::cluster [%0], "
-         "[%1, {%2, %3, %4}], [%5], %6; // 2c." : : "r"(__as_ptr_smem(__dstMem)),
-         "l"(__tensorMap),
-         "r"(__tensorCoords[0]),
-         "r"(__tensorCoords[1]),
-         "r"(__tensorCoords[2]),
-         "r"(__as_ptr_smem(__smem_bar)),
-         "h"(__ctaMask) : "memory");),
-    (
-      // Unsupported architectures will have a linker error with a semi-decent error message
-      __cuda_ptx_cp_async_bulk_tensor_is_not_supported_before_SM_90a__();));
+  static_assert(__cta_group == cta_group_1 || __cta_group == cta_group_2, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  _CCCL_IF_CONSTEXPR (__cta_group == cta_group_1)
+  {
+    asm("cp.async.bulk.tensor.3d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.multicast::cluster.cta_group:"
+        ":1 [%0], [%1, {%2, %3, %4}], [%5], %6;"
+        :
+        : "r"(__as_ptr_smem(__dstMem)),
+          "l"(__tensorMap),
+          "r"(__tensorCoords[0]),
+          "r"(__tensorCoords[1]),
+          "r"(__tensorCoords[2]),
+          "r"(__as_ptr_smem(__smem_bar)),
+          "h"(__ctaMask)
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__cta_group == cta_group_2)
+  {
+    asm("cp.async.bulk.tensor.3d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.multicast::cluster.cta_group:"
+        ":2 [%0], [%1, {%2, %3, %4}], [%5], %6;"
+        :
+        : "r"(__as_ptr_smem(__dstMem)),
+          "l"(__tensorMap),
+          "r"(__tensorCoords[0]),
+          "r"(__tensorCoords[1]),
+          "r"(__tensorCoords[2]),
+          "r"(__as_ptr_smem(__smem_bar)),
+          "h"(__ctaMask)
+        : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_cp_async_bulk_tensor_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
 }
 #endif // __cccl_ptx_isa >= 800
 
 /*
 // cp.async.bulk.tensor.4d.dst.src.tile.mbarrier::complete_tx::bytes.multicast::cluster [dstMem], [tensorMap,
-tensorCoords], [smem_bar], ctaMask; // 2d. PTX ISA 80, SM_90a
+tensorCoords], [smem_bar], ctaMask; // PTX ISA 80, SM_90a, SM_100a, SM_101a
 // .dst       = { .shared::cluster }
 // .src       = { .global }
 template <typename = void>
@@ -151,7 +364,7 @@ __device__ static inline void cp_async_bulk_tensor(
   const uint16_t& ctaMask);
 */
 #if __cccl_ptx_isa >= 800
-extern "C" _CCCL_DEVICE void __cuda_ptx_cp_async_bulk_tensor_is_not_supported_before_SM_90a__();
+extern "C" _CCCL_DEVICE void __cuda_ptx_cp_async_bulk_tensor_is_not_supported_before_SM_90a_SM_100a_SM_101a__();
 template <typename = void>
 _CCCL_DEVICE static inline void cp_async_bulk_tensor(
   space_cluster_t,
@@ -161,29 +374,104 @@ _CCCL_DEVICE static inline void cp_async_bulk_tensor(
   const _CUDA_VSTD::int32_t (&__tensorCoords)[4],
   _CUDA_VSTD::uint64_t* __smem_bar,
   const _CUDA_VSTD::uint16_t& __ctaMask)
+{
+// __space == space_cluster (due to parameter type constraint)
+// __space == space_global (due to parameter type constraint)
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM90_ALL || __CUDA_ARCH_FEAT_SM100_ALL \
+    || __CUDA_ARCH_FEAT_SM101_ALL
+  asm("cp.async.bulk.tensor.4d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.multicast::cluster [%0], [%1, "
+      "{%2, %3, %4, %5}], [%6], %7;"
+      :
+      : "r"(__as_ptr_smem(__dstMem)),
+        "l"(__tensorMap),
+        "r"(__tensorCoords[0]),
+        "r"(__tensorCoords[1]),
+        "r"(__tensorCoords[2]),
+        "r"(__tensorCoords[3]),
+        "r"(__as_ptr_smem(__smem_bar)),
+        "h"(__ctaMask)
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_cp_async_bulk_tensor_is_not_supported_before_SM_90a_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 800
+
+/*
+// cp.async.bulk.tensor.4d.dst.src.tile.mbarrier::complete_tx::bytes.multicast::cluster.cta_group [dstMem], [tensorMap,
+tensorCoords], [smem_bar], ctaMask; // PTX ISA 80, SM_100a, SM_101a
+// .dst       = { .shared::cluster }
+// .src       = { .global }
+// .cta_group = { .cta_group::1, .cta_group::2 }
+template <cuda::ptx::dot_cta_group Cta_Group>
+__device__ static inline void cp_async_bulk_tensor(
+  cuda::ptx::space_cluster_t,
+  cuda::ptx::space_global_t,
+  cuda::ptx::cta_group_t<Cta_Group> cta_group,
+  void* dstMem,
+  const void* tensorMap,
+  const int32_t (&tensorCoords)[4],
+  uint64_t* smem_bar,
+  const uint16_t& ctaMask);
+*/
+#if __cccl_ptx_isa >= 800
+extern "C" _CCCL_DEVICE void __cuda_ptx_cp_async_bulk_tensor_is_not_supported_before_SM_100a_SM_101a__();
+template <dot_cta_group _Cta_Group>
+_CCCL_DEVICE static inline void cp_async_bulk_tensor(
+  space_cluster_t,
+  space_global_t,
+  cta_group_t<_Cta_Group> __cta_group,
+  void* __dstMem,
+  const void* __tensorMap,
+  const _CUDA_VSTD::int32_t (&__tensorCoords)[4],
+  _CUDA_VSTD::uint64_t* __smem_bar,
+  const _CUDA_VSTD::uint16_t& __ctaMask)
 {
   // __space == space_cluster (due to parameter type constraint)
   // __space == space_global (due to parameter type constraint)
-  NV_IF_ELSE_TARGET(
-    NV_HAS_FEATURE_SM_90a,
-    (asm("cp.async.bulk.tensor.4d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.multicast::cluster [%0], "
-         "[%1, {%2, %3, %4, %5}], [%6], %7; // 2d." : : "r"(__as_ptr_smem(__dstMem)),
-         "l"(__tensorMap),
-         "r"(__tensorCoords[0]),
-         "r"(__tensorCoords[1]),
-         "r"(__tensorCoords[2]),
-         "r"(__tensorCoords[3]),
-         "r"(__as_ptr_smem(__smem_bar)),
-         "h"(__ctaMask) : "memory");),
-    (
-      // Unsupported architectures will have a linker error with a semi-decent error message
-      __cuda_ptx_cp_async_bulk_tensor_is_not_supported_before_SM_90a__();));
+  static_assert(__cta_group == cta_group_1 || __cta_group == cta_group_2, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  _CCCL_IF_CONSTEXPR (__cta_group == cta_group_1)
+  {
+    asm("cp.async.bulk.tensor.4d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.multicast::cluster.cta_group:"
+        ":1 [%0], [%1, {%2, %3, %4, %5}], [%6], %7;"
+        :
+        : "r"(__as_ptr_smem(__dstMem)),
+          "l"(__tensorMap),
+          "r"(__tensorCoords[0]),
+          "r"(__tensorCoords[1]),
+          "r"(__tensorCoords[2]),
+          "r"(__tensorCoords[3]),
+          "r"(__as_ptr_smem(__smem_bar)),
+          "h"(__ctaMask)
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__cta_group == cta_group_2)
+  {
+    asm("cp.async.bulk.tensor.4d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.multicast::cluster.cta_group:"
+        ":2 [%0], [%1, {%2, %3, %4, %5}], [%6], %7;"
+        :
+        : "r"(__as_ptr_smem(__dstMem)),
+          "l"(__tensorMap),
+          "r"(__tensorCoords[0]),
+          "r"(__tensorCoords[1]),
+          "r"(__tensorCoords[2]),
+          "r"(__tensorCoords[3]),
+          "r"(__as_ptr_smem(__smem_bar)),
+          "h"(__ctaMask)
+        : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_cp_async_bulk_tensor_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
 }
 #endif // __cccl_ptx_isa >= 800
 
 /*
 // cp.async.bulk.tensor.5d.dst.src.tile.mbarrier::complete_tx::bytes.multicast::cluster [dstMem], [tensorMap,
-tensorCoords], [smem_bar], ctaMask; // 2e. PTX ISA 80, SM_90a
+tensorCoords], [smem_bar], ctaMask; // PTX ISA 80, SM_90a, SM_100a, SM_101a
 // .dst       = { .shared::cluster }
 // .src       = { .global }
 template <typename = void>
@@ -197,7 +485,7 @@ __device__ static inline void cp_async_bulk_tensor(
   const uint16_t& ctaMask);
 */
 #if __cccl_ptx_isa >= 800
-extern "C" _CCCL_DEVICE void __cuda_ptx_cp_async_bulk_tensor_is_not_supported_before_SM_90a__();
+extern "C" _CCCL_DEVICE void __cuda_ptx_cp_async_bulk_tensor_is_not_supported_before_SM_90a_SM_100a_SM_101a__();
 template <typename = void>
 _CCCL_DEVICE static inline void cp_async_bulk_tensor(
   space_cluster_t,
@@ -207,24 +495,101 @@ _CCCL_DEVICE static inline void cp_async_bulk_tensor(
   const _CUDA_VSTD::int32_t (&__tensorCoords)[5],
   _CUDA_VSTD::uint64_t* __smem_bar,
   const _CUDA_VSTD::uint16_t& __ctaMask)
+{
+// __space == space_cluster (due to parameter type constraint)
+// __space == space_global (due to parameter type constraint)
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM90_ALL || __CUDA_ARCH_FEAT_SM100_ALL \
+    || __CUDA_ARCH_FEAT_SM101_ALL
+  asm("cp.async.bulk.tensor.5d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.multicast::cluster [%0], [%1, "
+      "{%2, %3, %4, %5, %6}], [%7], %8;"
+      :
+      : "r"(__as_ptr_smem(__dstMem)),
+        "l"(__tensorMap),
+        "r"(__tensorCoords[0]),
+        "r"(__tensorCoords[1]),
+        "r"(__tensorCoords[2]),
+        "r"(__tensorCoords[3]),
+        "r"(__tensorCoords[4]),
+        "r"(__as_ptr_smem(__smem_bar)),
+        "h"(__ctaMask)
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_cp_async_bulk_tensor_is_not_supported_before_SM_90a_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 800
+
+/*
+// cp.async.bulk.tensor.5d.dst.src.tile.mbarrier::complete_tx::bytes.multicast::cluster.cta_group [dstMem], [tensorMap,
+tensorCoords], [smem_bar], ctaMask; // PTX ISA 80, SM_100a, SM_101a
+// .dst       = { .shared::cluster }
+// .src       = { .global }
+// .cta_group = { .cta_group::1, .cta_group::2 }
+template <cuda::ptx::dot_cta_group Cta_Group>
+__device__ static inline void cp_async_bulk_tensor(
+  cuda::ptx::space_cluster_t,
+  cuda::ptx::space_global_t,
+  cuda::ptx::cta_group_t<Cta_Group> cta_group,
+  void* dstMem,
+  const void* tensorMap,
+  const int32_t (&tensorCoords)[5],
+  uint64_t* smem_bar,
+  const uint16_t& ctaMask);
+*/
+#if __cccl_ptx_isa >= 800
+extern "C" _CCCL_DEVICE void __cuda_ptx_cp_async_bulk_tensor_is_not_supported_before_SM_100a_SM_101a__();
+template <dot_cta_group _Cta_Group>
+_CCCL_DEVICE static inline void cp_async_bulk_tensor(
+  space_cluster_t,
+  space_global_t,
+  cta_group_t<_Cta_Group> __cta_group,
+  void* __dstMem,
+  const void* __tensorMap,
+  const _CUDA_VSTD::int32_t (&__tensorCoords)[5],
+  _CUDA_VSTD::uint64_t* __smem_bar,
+  const _CUDA_VSTD::uint16_t& __ctaMask)
 {
   // __space == space_cluster (due to parameter type constraint)
   // __space == space_global (due to parameter type constraint)
-  NV_IF_ELSE_TARGET(
-    NV_HAS_FEATURE_SM_90a,
-    (asm("cp.async.bulk.tensor.5d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.multicast::cluster [%0], "
-         "[%1, {%2, %3, %4, %5, %6}], [%7], %8; // 2e." : : "r"(__as_ptr_smem(__dstMem)),
-         "l"(__tensorMap),
-         "r"(__tensorCoords[0]),
-         "r"(__tensorCoords[1]),
-         "r"(__tensorCoords[2]),
-         "r"(__tensorCoords[3]),
-         "r"(__tensorCoords[4]),
-         "r"(__as_ptr_smem(__smem_bar)),
-         "h"(__ctaMask) : "memory");),
-    (
-      // Unsupported architectures will have a linker error with a semi-decent error message
-      __cuda_ptx_cp_async_bulk_tensor_is_not_supported_before_SM_90a__();));
+  static_assert(__cta_group == cta_group_1 || __cta_group == cta_group_2, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  _CCCL_IF_CONSTEXPR (__cta_group == cta_group_1)
+  {
+    asm("cp.async.bulk.tensor.5d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.multicast::cluster.cta_group:"
+        ":1 [%0], [%1, {%2, %3, %4, %5, %6}], [%7], %8;"
+        :
+        : "r"(__as_ptr_smem(__dstMem)),
+          "l"(__tensorMap),
+          "r"(__tensorCoords[0]),
+          "r"(__tensorCoords[1]),
+          "r"(__tensorCoords[2]),
+          "r"(__tensorCoords[3]),
+          "r"(__tensorCoords[4]),
+          "r"(__as_ptr_smem(__smem_bar)),
+          "h"(__ctaMask)
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__cta_group == cta_group_2)
+  {
+    asm("cp.async.bulk.tensor.5d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.multicast::cluster.cta_group:"
+        ":2 [%0], [%1, {%2, %3, %4, %5, %6}], [%7], %8;"
+        :
+        : "r"(__as_ptr_smem(__dstMem)),
+          "l"(__tensorMap),
+          "r"(__tensorCoords[0]),
+          "r"(__tensorCoords[1]),
+          "r"(__tensorCoords[2]),
+          "r"(__tensorCoords[3]),
+          "r"(__tensorCoords[4]),
+          "r"(__as_ptr_smem(__smem_bar)),
+          "h"(__ctaMask)
+        : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_cp_async_bulk_tensor_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
 }
 #endif // __cccl_ptx_isa >= 800
 
diff --git a/libcudacxx/include/cuda/__ptx/instructions/generated/cp_async_bulk_wait_group.h b/libcudacxx/include/cuda/__ptx/instructions/generated/cp_async_bulk_wait_group.h
index 85b1507f721..b0373a3e6a7 100644
--- a/libcudacxx/include/cuda/__ptx/instructions/generated/cp_async_bulk_wait_group.h
+++ b/libcudacxx/include/cuda/__ptx/instructions/generated/cp_async_bulk_wait_group.h
@@ -14,12 +14,12 @@ extern "C" _CCCL_DEVICE void __cuda_ptx_cp_async_bulk_wait_group_is_not_supporte
 template <int _N32>
 _CCCL_DEVICE static inline void cp_async_bulk_wait_group(n32_t<_N32> __N)
 {
-  NV_IF_ELSE_TARGET(
-    NV_PROVIDES_SM_90,
-    (asm volatile("cp.async.bulk.wait_group %0;" : : "n"(__N.value) : "memory");),
-    (
-      // Unsupported architectures will have a linker error with a semi-decent error message
-      __cuda_ptx_cp_async_bulk_wait_group_is_not_supported_before_SM_90__();));
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  asm volatile("cp.async.bulk.wait_group %0;" : : "n"(__N.value) : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_cp_async_bulk_wait_group_is_not_supported_before_SM_90__();
+#  endif
 }
 #endif // __cccl_ptx_isa >= 800
 
@@ -34,12 +34,12 @@ extern "C" _CCCL_DEVICE void __cuda_ptx_cp_async_bulk_wait_group_read_is_not_sup
 template <int _N32>
 _CCCL_DEVICE static inline void cp_async_bulk_wait_group_read(n32_t<_N32> __N)
 {
-  NV_IF_ELSE_TARGET(
-    NV_PROVIDES_SM_90,
-    (asm volatile("cp.async.bulk.wait_group.read %0;" : : "n"(__N.value) : "memory");),
-    (
-      // Unsupported architectures will have a linker error with a semi-decent error message
-      __cuda_ptx_cp_async_bulk_wait_group_read_is_not_supported_before_SM_90__();));
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  asm volatile("cp.async.bulk.wait_group.read %0;" : : "n"(__N.value) : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_cp_async_bulk_wait_group_read_is_not_supported_before_SM_90__();
+#  endif
 }
 #endif // __cccl_ptx_isa >= 800
 
diff --git a/libcudacxx/include/cuda/__ptx/instructions/generated/cp_async_mbarrier_arrive.h b/libcudacxx/include/cuda/__ptx/instructions/generated/cp_async_mbarrier_arrive.h
new file mode 100644
index 00000000000..b2bf07247c1
--- /dev/null
+++ b/libcudacxx/include/cuda/__ptx/instructions/generated/cp_async_mbarrier_arrive.h
@@ -0,0 +1,26 @@
+// This file was automatically generated. Do not edit.
+
+#ifndef _CUDA_PTX_GENERATED_CP_ASYNC_MBARRIER_ARRIVE_H_
+#define _CUDA_PTX_GENERATED_CP_ASYNC_MBARRIER_ARRIVE_H_
+
+/*
+// cp.async.mbarrier.arrive.b64 [addr]; // PTX ISA 70, SM_80
+template <typename = void>
+__device__ static inline void cp_async_mbarrier_arrive(
+  uint64_t* addr);
+*/
+#if __cccl_ptx_isa >= 700
+extern "C" _CCCL_DEVICE void __cuda_ptx_cp_async_mbarrier_arrive_is_not_supported_before_SM_80__();
+template <typename = void>
+_CCCL_DEVICE static inline void cp_async_mbarrier_arrive(_CUDA_VSTD::uint64_t* __addr)
+{
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 800
+  asm("cp.async.mbarrier.arrive.b64 [%0];" : : "r"(__as_ptr_smem(__addr)) : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_cp_async_mbarrier_arrive_is_not_supported_before_SM_80__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 700
+
+#endif // _CUDA_PTX_GENERATED_CP_ASYNC_MBARRIER_ARRIVE_H_
diff --git a/libcudacxx/include/cuda/__ptx/instructions/generated/cp_async_mbarrier_arrive_noinc.h b/libcudacxx/include/cuda/__ptx/instructions/generated/cp_async_mbarrier_arrive_noinc.h
new file mode 100644
index 00000000000..816a3fc63b9
--- /dev/null
+++ b/libcudacxx/include/cuda/__ptx/instructions/generated/cp_async_mbarrier_arrive_noinc.h
@@ -0,0 +1,26 @@
+// This file was automatically generated. Do not edit.
+
+#ifndef _CUDA_PTX_GENERATED_CP_ASYNC_MBARRIER_ARRIVE_NOINC_H_
+#define _CUDA_PTX_GENERATED_CP_ASYNC_MBARRIER_ARRIVE_NOINC_H_
+
+/*
+// cp.async.mbarrier.arrive.noinc.b64 [addr]; // PTX ISA 70, SM_80
+template <typename = void>
+__device__ static inline void cp_async_mbarrier_arrive_noinc(
+  uint64_t* addr);
+*/
+#if __cccl_ptx_isa >= 700
+extern "C" _CCCL_DEVICE void __cuda_ptx_cp_async_mbarrier_arrive_noinc_is_not_supported_before_SM_80__();
+template <typename = void>
+_CCCL_DEVICE static inline void cp_async_mbarrier_arrive_noinc(_CUDA_VSTD::uint64_t* __addr)
+{
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 800
+  asm("cp.async.mbarrier.arrive.noinc.b64 [%0];" : : "r"(__as_ptr_smem(__addr)) : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_cp_async_mbarrier_arrive_noinc_is_not_supported_before_SM_80__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 700
+
+#endif // _CUDA_PTX_GENERATED_CP_ASYNC_MBARRIER_ARRIVE_NOINC_H_
diff --git a/libcudacxx/include/cuda/__ptx/instructions/generated/cp_reduce_async_bulk.h b/libcudacxx/include/cuda/__ptx/instructions/generated/cp_reduce_async_bulk.h
index 9b1bf35b290..499fda57c91 100644
--- a/libcudacxx/include/cuda/__ptx/instructions/generated/cp_reduce_async_bulk.h
+++ b/libcudacxx/include/cuda/__ptx/instructions/generated/cp_reduce_async_bulk.h
@@ -10,7 +10,7 @@ ISA 80, SM_90
 // .src       = { .shared::cta }
 // .type      = { .b32 }
 // .op        = { .and }
-template <typename B32>
+template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
 __device__ static inline void cp_reduce_async_bulk(
   cuda::ptx::space_cluster_t,
   cuda::ptx::space_shared_t,
@@ -22,7 +22,7 @@ __device__ static inline void cp_reduce_async_bulk(
 */
 #if __cccl_ptx_isa >= 800
 extern "C" _CCCL_DEVICE void __cuda_ptx_cp_reduce_async_bulk_is_not_supported_before_SM_90__();
-template <typename _B32>
+template <typename _B32, _CUDA_VSTD::enable_if_t<sizeof(_B32) == 4, bool> = true>
 _CCCL_DEVICE static inline void cp_reduce_async_bulk(
   space_cluster_t,
   space_shared_t,
@@ -32,20 +32,23 @@ _CCCL_DEVICE static inline void cp_reduce_async_bulk(
   _CUDA_VSTD::uint32_t __size,
   _CUDA_VSTD::uint64_t* __rdsmem_bar)
 {
-  // __space == space_cluster (due to parameter type constraint)
-  // __space == space_shared (due to parameter type constraint)
-  // __type == type_b32 (due to parameter type constraint)
-  // __op == op_and_op (due to parameter type constraint)
-  NV_IF_ELSE_TARGET(
-    NV_PROVIDES_SM_90,
-    (asm("cp.reduce.async.bulk.shared::cluster.shared::cta.mbarrier::complete_tx::bytes.and.b32 [%0], [%1], %2, [%3]; "
-         "// 1." : : "r"(__as_ptr_remote_dsmem(__dstMem)),
-         "r"(__as_ptr_smem(__srcMem)),
-         "r"(__size),
-         "r"(__as_ptr_remote_dsmem(__rdsmem_bar)) : "memory");),
-    (
-      // Unsupported architectures will have a linker error with a semi-decent error message
-      __cuda_ptx_cp_reduce_async_bulk_is_not_supported_before_SM_90__();));
+// __space == space_cluster (due to parameter type constraint)
+// __space == space_shared (due to parameter type constraint)
+// __type == type_b32 (due to parameter type constraint)
+// __op == op_and_op (due to parameter type constraint)
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  asm("cp.reduce.async.bulk.shared::cluster.shared::cta.mbarrier::complete_tx::bytes.and.b32 [%0], [%1], %2, [%3]; // "
+      "1."
+      :
+      : "r"(__as_ptr_remote_dsmem(__dstMem)),
+        "r"(__as_ptr_smem(__srcMem)),
+        "r"(__size),
+        "r"(__as_ptr_remote_dsmem(__rdsmem_bar))
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_cp_reduce_async_bulk_is_not_supported_before_SM_90__();
+#  endif
 }
 #endif // __cccl_ptx_isa >= 800
 
@@ -56,7 +59,7 @@ ISA 80, SM_90
 // .src       = { .shared::cta }
 // .type      = { .b32 }
 // .op        = { .or }
-template <typename B32>
+template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
 __device__ static inline void cp_reduce_async_bulk(
   cuda::ptx::space_cluster_t,
   cuda::ptx::space_shared_t,
@@ -68,7 +71,7 @@ __device__ static inline void cp_reduce_async_bulk(
 */
 #if __cccl_ptx_isa >= 800
 extern "C" _CCCL_DEVICE void __cuda_ptx_cp_reduce_async_bulk_is_not_supported_before_SM_90__();
-template <typename _B32>
+template <typename _B32, _CUDA_VSTD::enable_if_t<sizeof(_B32) == 4, bool> = true>
 _CCCL_DEVICE static inline void cp_reduce_async_bulk(
   space_cluster_t,
   space_shared_t,
@@ -78,20 +81,22 @@ _CCCL_DEVICE static inline void cp_reduce_async_bulk(
   _CUDA_VSTD::uint32_t __size,
   _CUDA_VSTD::uint64_t* __rdsmem_bar)
 {
-  // __space == space_cluster (due to parameter type constraint)
-  // __space == space_shared (due to parameter type constraint)
-  // __type == type_b32 (due to parameter type constraint)
-  // __op == op_or_op (due to parameter type constraint)
-  NV_IF_ELSE_TARGET(
-    NV_PROVIDES_SM_90,
-    (asm("cp.reduce.async.bulk.shared::cluster.shared::cta.mbarrier::complete_tx::bytes.or.b32 [%0], [%1], %2, [%3]; "
-         "// 1." : : "r"(__as_ptr_remote_dsmem(__dstMem)),
-         "r"(__as_ptr_smem(__srcMem)),
-         "r"(__size),
-         "r"(__as_ptr_remote_dsmem(__rdsmem_bar)) : "memory");),
-    (
-      // Unsupported architectures will have a linker error with a semi-decent error message
-      __cuda_ptx_cp_reduce_async_bulk_is_not_supported_before_SM_90__();));
+// __space == space_cluster (due to parameter type constraint)
+// __space == space_shared (due to parameter type constraint)
+// __type == type_b32 (due to parameter type constraint)
+// __op == op_or_op (due to parameter type constraint)
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  asm("cp.reduce.async.bulk.shared::cluster.shared::cta.mbarrier::complete_tx::bytes.or.b32 [%0], [%1], %2, [%3]; // 1."
+      :
+      : "r"(__as_ptr_remote_dsmem(__dstMem)),
+        "r"(__as_ptr_smem(__srcMem)),
+        "r"(__size),
+        "r"(__as_ptr_remote_dsmem(__rdsmem_bar))
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_cp_reduce_async_bulk_is_not_supported_before_SM_90__();
+#  endif
 }
 #endif // __cccl_ptx_isa >= 800
 
@@ -102,7 +107,7 @@ ISA 80, SM_90
 // .src       = { .shared::cta }
 // .type      = { .b32 }
 // .op        = { .xor }
-template <typename B32>
+template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
 __device__ static inline void cp_reduce_async_bulk(
   cuda::ptx::space_cluster_t,
   cuda::ptx::space_shared_t,
@@ -114,7 +119,7 @@ __device__ static inline void cp_reduce_async_bulk(
 */
 #if __cccl_ptx_isa >= 800
 extern "C" _CCCL_DEVICE void __cuda_ptx_cp_reduce_async_bulk_is_not_supported_before_SM_90__();
-template <typename _B32>
+template <typename _B32, _CUDA_VSTD::enable_if_t<sizeof(_B32) == 4, bool> = true>
 _CCCL_DEVICE static inline void cp_reduce_async_bulk(
   space_cluster_t,
   space_shared_t,
@@ -124,20 +129,23 @@ _CCCL_DEVICE static inline void cp_reduce_async_bulk(
   _CUDA_VSTD::uint32_t __size,
   _CUDA_VSTD::uint64_t* __rdsmem_bar)
 {
-  // __space == space_cluster (due to parameter type constraint)
-  // __space == space_shared (due to parameter type constraint)
-  // __type == type_b32 (due to parameter type constraint)
-  // __op == op_xor_op (due to parameter type constraint)
-  NV_IF_ELSE_TARGET(
-    NV_PROVIDES_SM_90,
-    (asm("cp.reduce.async.bulk.shared::cluster.shared::cta.mbarrier::complete_tx::bytes.xor.b32 [%0], [%1], %2, [%3]; "
-         "// 1." : : "r"(__as_ptr_remote_dsmem(__dstMem)),
-         "r"(__as_ptr_smem(__srcMem)),
-         "r"(__size),
-         "r"(__as_ptr_remote_dsmem(__rdsmem_bar)) : "memory");),
-    (
-      // Unsupported architectures will have a linker error with a semi-decent error message
-      __cuda_ptx_cp_reduce_async_bulk_is_not_supported_before_SM_90__();));
+// __space == space_cluster (due to parameter type constraint)
+// __space == space_shared (due to parameter type constraint)
+// __type == type_b32 (due to parameter type constraint)
+// __op == op_xor_op (due to parameter type constraint)
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  asm("cp.reduce.async.bulk.shared::cluster.shared::cta.mbarrier::complete_tx::bytes.xor.b32 [%0], [%1], %2, [%3]; // "
+      "1."
+      :
+      : "r"(__as_ptr_remote_dsmem(__dstMem)),
+        "r"(__as_ptr_smem(__srcMem)),
+        "r"(__size),
+        "r"(__as_ptr_remote_dsmem(__rdsmem_bar))
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_cp_reduce_async_bulk_is_not_supported_before_SM_90__();
+#  endif
 }
 #endif // __cccl_ptx_isa >= 800
 
@@ -170,20 +178,23 @@ _CCCL_DEVICE static inline void cp_reduce_async_bulk(
   _CUDA_VSTD::uint32_t __size,
   _CUDA_VSTD::uint64_t* __rdsmem_bar)
 {
-  // __space == space_cluster (due to parameter type constraint)
-  // __space == space_shared (due to parameter type constraint)
-  // __type == type_u32 (due to parameter type constraint)
-  // __op == op_min (due to parameter type constraint)
-  NV_IF_ELSE_TARGET(
-    NV_PROVIDES_SM_90,
-    (asm("cp.reduce.async.bulk.shared::cluster.shared::cta.mbarrier::complete_tx::bytes.min.u32 [%0], [%1], %2, [%3]; "
-         "// 1." : : "r"(__as_ptr_remote_dsmem(__dstMem)),
-         "r"(__as_ptr_smem(__srcMem)),
-         "r"(__size),
-         "r"(__as_ptr_remote_dsmem(__rdsmem_bar)) : "memory");),
-    (
-      // Unsupported architectures will have a linker error with a semi-decent error message
-      __cuda_ptx_cp_reduce_async_bulk_is_not_supported_before_SM_90__();));
+// __space == space_cluster (due to parameter type constraint)
+// __space == space_shared (due to parameter type constraint)
+// __type == type_u32 (due to parameter type constraint)
+// __op == op_min (due to parameter type constraint)
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  asm("cp.reduce.async.bulk.shared::cluster.shared::cta.mbarrier::complete_tx::bytes.min.u32 [%0], [%1], %2, [%3]; // "
+      "1."
+      :
+      : "r"(__as_ptr_remote_dsmem(__dstMem)),
+        "r"(__as_ptr_smem(__srcMem)),
+        "r"(__size),
+        "r"(__as_ptr_remote_dsmem(__rdsmem_bar))
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_cp_reduce_async_bulk_is_not_supported_before_SM_90__();
+#  endif
 }
 #endif // __cccl_ptx_isa >= 800
 
@@ -216,20 +227,23 @@ _CCCL_DEVICE static inline void cp_reduce_async_bulk(
   _CUDA_VSTD::uint32_t __size,
   _CUDA_VSTD::uint64_t* __rdsmem_bar)
 {
-  // __space == space_cluster (due to parameter type constraint)
-  // __space == space_shared (due to parameter type constraint)
-  // __type == type_u32 (due to parameter type constraint)
-  // __op == op_max (due to parameter type constraint)
-  NV_IF_ELSE_TARGET(
-    NV_PROVIDES_SM_90,
-    (asm("cp.reduce.async.bulk.shared::cluster.shared::cta.mbarrier::complete_tx::bytes.max.u32 [%0], [%1], %2, [%3]; "
-         "// 1." : : "r"(__as_ptr_remote_dsmem(__dstMem)),
-         "r"(__as_ptr_smem(__srcMem)),
-         "r"(__size),
-         "r"(__as_ptr_remote_dsmem(__rdsmem_bar)) : "memory");),
-    (
-      // Unsupported architectures will have a linker error with a semi-decent error message
-      __cuda_ptx_cp_reduce_async_bulk_is_not_supported_before_SM_90__();));
+// __space == space_cluster (due to parameter type constraint)
+// __space == space_shared (due to parameter type constraint)
+// __type == type_u32 (due to parameter type constraint)
+// __op == op_max (due to parameter type constraint)
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  asm("cp.reduce.async.bulk.shared::cluster.shared::cta.mbarrier::complete_tx::bytes.max.u32 [%0], [%1], %2, [%3]; // "
+      "1."
+      :
+      : "r"(__as_ptr_remote_dsmem(__dstMem)),
+        "r"(__as_ptr_smem(__srcMem)),
+        "r"(__size),
+        "r"(__as_ptr_remote_dsmem(__rdsmem_bar))
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_cp_reduce_async_bulk_is_not_supported_before_SM_90__();
+#  endif
 }
 #endif // __cccl_ptx_isa >= 800
 
@@ -262,20 +276,23 @@ _CCCL_DEVICE static inline void cp_reduce_async_bulk(
   _CUDA_VSTD::uint32_t __size,
   _CUDA_VSTD::uint64_t* __rdsmem_bar)
 {
-  // __space == space_cluster (due to parameter type constraint)
-  // __space == space_shared (due to parameter type constraint)
-  // __type == type_u32 (due to parameter type constraint)
-  // __op == op_add (due to parameter type constraint)
-  NV_IF_ELSE_TARGET(
-    NV_PROVIDES_SM_90,
-    (asm("cp.reduce.async.bulk.shared::cluster.shared::cta.mbarrier::complete_tx::bytes.add.u32 [%0], [%1], %2, [%3]; "
-         "// 1." : : "r"(__as_ptr_remote_dsmem(__dstMem)),
-         "r"(__as_ptr_smem(__srcMem)),
-         "r"(__size),
-         "r"(__as_ptr_remote_dsmem(__rdsmem_bar)) : "memory");),
-    (
-      // Unsupported architectures will have a linker error with a semi-decent error message
-      __cuda_ptx_cp_reduce_async_bulk_is_not_supported_before_SM_90__();));
+// __space == space_cluster (due to parameter type constraint)
+// __space == space_shared (due to parameter type constraint)
+// __type == type_u32 (due to parameter type constraint)
+// __op == op_add (due to parameter type constraint)
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  asm("cp.reduce.async.bulk.shared::cluster.shared::cta.mbarrier::complete_tx::bytes.add.u32 [%0], [%1], %2, [%3]; // "
+      "1."
+      :
+      : "r"(__as_ptr_remote_dsmem(__dstMem)),
+        "r"(__as_ptr_smem(__srcMem)),
+        "r"(__size),
+        "r"(__as_ptr_remote_dsmem(__rdsmem_bar))
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_cp_reduce_async_bulk_is_not_supported_before_SM_90__();
+#  endif
 }
 #endif // __cccl_ptx_isa >= 800
 
@@ -308,20 +325,23 @@ _CCCL_DEVICE static inline void cp_reduce_async_bulk(
   _CUDA_VSTD::uint32_t __size,
   _CUDA_VSTD::uint64_t* __rdsmem_bar)
 {
-  // __space == space_cluster (due to parameter type constraint)
-  // __space == space_shared (due to parameter type constraint)
-  // __type == type_u32 (due to parameter type constraint)
-  // __op == op_inc (due to parameter type constraint)
-  NV_IF_ELSE_TARGET(
-    NV_PROVIDES_SM_90,
-    (asm("cp.reduce.async.bulk.shared::cluster.shared::cta.mbarrier::complete_tx::bytes.inc.u32 [%0], [%1], %2, [%3]; "
-         "// 1." : : "r"(__as_ptr_remote_dsmem(__dstMem)),
-         "r"(__as_ptr_smem(__srcMem)),
-         "r"(__size),
-         "r"(__as_ptr_remote_dsmem(__rdsmem_bar)) : "memory");),
-    (
-      // Unsupported architectures will have a linker error with a semi-decent error message
-      __cuda_ptx_cp_reduce_async_bulk_is_not_supported_before_SM_90__();));
+// __space == space_cluster (due to parameter type constraint)
+// __space == space_shared (due to parameter type constraint)
+// __type == type_u32 (due to parameter type constraint)
+// __op == op_inc (due to parameter type constraint)
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  asm("cp.reduce.async.bulk.shared::cluster.shared::cta.mbarrier::complete_tx::bytes.inc.u32 [%0], [%1], %2, [%3]; // "
+      "1."
+      :
+      : "r"(__as_ptr_remote_dsmem(__dstMem)),
+        "r"(__as_ptr_smem(__srcMem)),
+        "r"(__size),
+        "r"(__as_ptr_remote_dsmem(__rdsmem_bar))
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_cp_reduce_async_bulk_is_not_supported_before_SM_90__();
+#  endif
 }
 #endif // __cccl_ptx_isa >= 800
 
@@ -354,20 +374,23 @@ _CCCL_DEVICE static inline void cp_reduce_async_bulk(
   _CUDA_VSTD::uint32_t __size,
   _CUDA_VSTD::uint64_t* __rdsmem_bar)
 {
-  // __space == space_cluster (due to parameter type constraint)
-  // __space == space_shared (due to parameter type constraint)
-  // __type == type_u32 (due to parameter type constraint)
-  // __op == op_dec (due to parameter type constraint)
-  NV_IF_ELSE_TARGET(
-    NV_PROVIDES_SM_90,
-    (asm("cp.reduce.async.bulk.shared::cluster.shared::cta.mbarrier::complete_tx::bytes.dec.u32 [%0], [%1], %2, [%3]; "
-         "// 1." : : "r"(__as_ptr_remote_dsmem(__dstMem)),
-         "r"(__as_ptr_smem(__srcMem)),
-         "r"(__size),
-         "r"(__as_ptr_remote_dsmem(__rdsmem_bar)) : "memory");),
-    (
-      // Unsupported architectures will have a linker error with a semi-decent error message
-      __cuda_ptx_cp_reduce_async_bulk_is_not_supported_before_SM_90__();));
+// __space == space_cluster (due to parameter type constraint)
+// __space == space_shared (due to parameter type constraint)
+// __type == type_u32 (due to parameter type constraint)
+// __op == op_dec (due to parameter type constraint)
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  asm("cp.reduce.async.bulk.shared::cluster.shared::cta.mbarrier::complete_tx::bytes.dec.u32 [%0], [%1], %2, [%3]; // "
+      "1."
+      :
+      : "r"(__as_ptr_remote_dsmem(__dstMem)),
+        "r"(__as_ptr_smem(__srcMem)),
+        "r"(__size),
+        "r"(__as_ptr_remote_dsmem(__rdsmem_bar))
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_cp_reduce_async_bulk_is_not_supported_before_SM_90__();
+#  endif
 }
 #endif // __cccl_ptx_isa >= 800
 
@@ -400,20 +423,23 @@ _CCCL_DEVICE static inline void cp_reduce_async_bulk(
   _CUDA_VSTD::uint32_t __size,
   _CUDA_VSTD::uint64_t* __rdsmem_bar)
 {
-  // __space == space_cluster (due to parameter type constraint)
-  // __space == space_shared (due to parameter type constraint)
-  // __type == type_s32 (due to parameter type constraint)
-  // __op == op_min (due to parameter type constraint)
-  NV_IF_ELSE_TARGET(
-    NV_PROVIDES_SM_90,
-    (asm("cp.reduce.async.bulk.shared::cluster.shared::cta.mbarrier::complete_tx::bytes.min.s32 [%0], [%1], %2, [%3]; "
-         "// 1." : : "r"(__as_ptr_remote_dsmem(__dstMem)),
-         "r"(__as_ptr_smem(__srcMem)),
-         "r"(__size),
-         "r"(__as_ptr_remote_dsmem(__rdsmem_bar)) : "memory");),
-    (
-      // Unsupported architectures will have a linker error with a semi-decent error message
-      __cuda_ptx_cp_reduce_async_bulk_is_not_supported_before_SM_90__();));
+// __space == space_cluster (due to parameter type constraint)
+// __space == space_shared (due to parameter type constraint)
+// __type == type_s32 (due to parameter type constraint)
+// __op == op_min (due to parameter type constraint)
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  asm("cp.reduce.async.bulk.shared::cluster.shared::cta.mbarrier::complete_tx::bytes.min.s32 [%0], [%1], %2, [%3]; // "
+      "1."
+      :
+      : "r"(__as_ptr_remote_dsmem(__dstMem)),
+        "r"(__as_ptr_smem(__srcMem)),
+        "r"(__size),
+        "r"(__as_ptr_remote_dsmem(__rdsmem_bar))
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_cp_reduce_async_bulk_is_not_supported_before_SM_90__();
+#  endif
 }
 #endif // __cccl_ptx_isa >= 800
 
@@ -446,20 +472,23 @@ _CCCL_DEVICE static inline void cp_reduce_async_bulk(
   _CUDA_VSTD::uint32_t __size,
   _CUDA_VSTD::uint64_t* __rdsmem_bar)
 {
-  // __space == space_cluster (due to parameter type constraint)
-  // __space == space_shared (due to parameter type constraint)
-  // __type == type_s32 (due to parameter type constraint)
-  // __op == op_max (due to parameter type constraint)
-  NV_IF_ELSE_TARGET(
-    NV_PROVIDES_SM_90,
-    (asm("cp.reduce.async.bulk.shared::cluster.shared::cta.mbarrier::complete_tx::bytes.max.s32 [%0], [%1], %2, [%3]; "
-         "// 1." : : "r"(__as_ptr_remote_dsmem(__dstMem)),
-         "r"(__as_ptr_smem(__srcMem)),
-         "r"(__size),
-         "r"(__as_ptr_remote_dsmem(__rdsmem_bar)) : "memory");),
-    (
-      // Unsupported architectures will have a linker error with a semi-decent error message
-      __cuda_ptx_cp_reduce_async_bulk_is_not_supported_before_SM_90__();));
+// __space == space_cluster (due to parameter type constraint)
+// __space == space_shared (due to parameter type constraint)
+// __type == type_s32 (due to parameter type constraint)
+// __op == op_max (due to parameter type constraint)
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  asm("cp.reduce.async.bulk.shared::cluster.shared::cta.mbarrier::complete_tx::bytes.max.s32 [%0], [%1], %2, [%3]; // "
+      "1."
+      :
+      : "r"(__as_ptr_remote_dsmem(__dstMem)),
+        "r"(__as_ptr_smem(__srcMem)),
+        "r"(__size),
+        "r"(__as_ptr_remote_dsmem(__rdsmem_bar))
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_cp_reduce_async_bulk_is_not_supported_before_SM_90__();
+#  endif
 }
 #endif // __cccl_ptx_isa >= 800
 
@@ -492,20 +521,23 @@ _CCCL_DEVICE static inline void cp_reduce_async_bulk(
   _CUDA_VSTD::uint32_t __size,
   _CUDA_VSTD::uint64_t* __rdsmem_bar)
 {
-  // __space == space_cluster (due to parameter type constraint)
-  // __space == space_shared (due to parameter type constraint)
-  // __type == type_s32 (due to parameter type constraint)
-  // __op == op_add (due to parameter type constraint)
-  NV_IF_ELSE_TARGET(
-    NV_PROVIDES_SM_90,
-    (asm("cp.reduce.async.bulk.shared::cluster.shared::cta.mbarrier::complete_tx::bytes.add.s32 [%0], [%1], %2, [%3]; "
-         "// 1." : : "r"(__as_ptr_remote_dsmem(__dstMem)),
-         "r"(__as_ptr_smem(__srcMem)),
-         "r"(__size),
-         "r"(__as_ptr_remote_dsmem(__rdsmem_bar)) : "memory");),
-    (
-      // Unsupported architectures will have a linker error with a semi-decent error message
-      __cuda_ptx_cp_reduce_async_bulk_is_not_supported_before_SM_90__();));
+// __space == space_cluster (due to parameter type constraint)
+// __space == space_shared (due to parameter type constraint)
+// __type == type_s32 (due to parameter type constraint)
+// __op == op_add (due to parameter type constraint)
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  asm("cp.reduce.async.bulk.shared::cluster.shared::cta.mbarrier::complete_tx::bytes.add.s32 [%0], [%1], %2, [%3]; // "
+      "1."
+      :
+      : "r"(__as_ptr_remote_dsmem(__dstMem)),
+        "r"(__as_ptr_smem(__srcMem)),
+        "r"(__size),
+        "r"(__as_ptr_remote_dsmem(__rdsmem_bar))
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_cp_reduce_async_bulk_is_not_supported_before_SM_90__();
+#  endif
 }
 #endif // __cccl_ptx_isa >= 800
 
@@ -538,20 +570,23 @@ _CCCL_DEVICE static inline void cp_reduce_async_bulk(
   _CUDA_VSTD::uint32_t __size,
   _CUDA_VSTD::uint64_t* __rdsmem_bar)
 {
-  // __space == space_cluster (due to parameter type constraint)
-  // __space == space_shared (due to parameter type constraint)
-  // __type == type_u64 (due to parameter type constraint)
-  // __op == op_add (due to parameter type constraint)
-  NV_IF_ELSE_TARGET(
-    NV_PROVIDES_SM_90,
-    (asm("cp.reduce.async.bulk.shared::cluster.shared::cta.mbarrier::complete_tx::bytes.add.u64 [%0], [%1], %2, [%3]; "
-         "// 1." : : "r"(__as_ptr_remote_dsmem(__dstMem)),
-         "r"(__as_ptr_smem(__srcMem)),
-         "r"(__size),
-         "r"(__as_ptr_remote_dsmem(__rdsmem_bar)) : "memory");),
-    (
-      // Unsupported architectures will have a linker error with a semi-decent error message
-      __cuda_ptx_cp_reduce_async_bulk_is_not_supported_before_SM_90__();));
+// __space == space_cluster (due to parameter type constraint)
+// __space == space_shared (due to parameter type constraint)
+// __type == type_u64 (due to parameter type constraint)
+// __op == op_add (due to parameter type constraint)
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  asm("cp.reduce.async.bulk.shared::cluster.shared::cta.mbarrier::complete_tx::bytes.add.u64 [%0], [%1], %2, [%3]; // "
+      "1."
+      :
+      : "r"(__as_ptr_remote_dsmem(__dstMem)),
+        "r"(__as_ptr_smem(__srcMem)),
+        "r"(__size),
+        "r"(__as_ptr_remote_dsmem(__rdsmem_bar))
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_cp_reduce_async_bulk_is_not_supported_before_SM_90__();
+#  endif
 }
 #endif // __cccl_ptx_isa >= 800
 
@@ -584,20 +619,23 @@ _CCCL_DEVICE static inline void cp_reduce_async_bulk(
   _CUDA_VSTD::uint32_t __size,
   _CUDA_VSTD::uint64_t* __rdsmem_bar)
 {
-  // __space == space_cluster (due to parameter type constraint)
-  // __space == space_shared (due to parameter type constraint)
-  // __type == type_s64 (due to parameter type constraint)
-  // __op == op_add (due to parameter type constraint)
-  NV_IF_ELSE_TARGET(
-    NV_PROVIDES_SM_90,
-    (asm("cp.reduce.async.bulk.shared::cluster.shared::cta.mbarrier::complete_tx::bytes.add.u64 [%0], [%1], %2, [%3]; "
-         "// 2." : : "r"(__as_ptr_remote_dsmem(__dstMem)),
-         "r"(__as_ptr_smem(__srcMem)),
-         "r"(__size),
-         "r"(__as_ptr_remote_dsmem(__rdsmem_bar)) : "memory");),
-    (
-      // Unsupported architectures will have a linker error with a semi-decent error message
-      __cuda_ptx_cp_reduce_async_bulk_is_not_supported_before_SM_90__();));
+// __space == space_cluster (due to parameter type constraint)
+// __space == space_shared (due to parameter type constraint)
+// __type == type_s64 (due to parameter type constraint)
+// __op == op_add (due to parameter type constraint)
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  asm("cp.reduce.async.bulk.shared::cluster.shared::cta.mbarrier::complete_tx::bytes.add.u64 [%0], [%1], %2, [%3]; // "
+      "2."
+      :
+      : "r"(__as_ptr_remote_dsmem(__dstMem)),
+        "r"(__as_ptr_smem(__srcMem)),
+        "r"(__size),
+        "r"(__as_ptr_remote_dsmem(__rdsmem_bar))
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_cp_reduce_async_bulk_is_not_supported_before_SM_90__();
+#  endif
 }
 #endif // __cccl_ptx_isa >= 800
 
@@ -625,24 +663,26 @@ _CCCL_DEVICE static inline void cp_reduce_async_bulk(
   // __space == space_global (due to parameter type constraint)
   // __space == space_shared (due to parameter type constraint)
   static_assert(sizeof(_Type) == 4 || sizeof(_Type) == 8, "");
-  // __op == op_and_op (due to parameter type constraint)
-  NV_IF_ELSE_TARGET(
-    NV_PROVIDES_SM_90,
-    (
-      _CCCL_IF_CONSTEXPR (sizeof(_Type) == 4) {
-        asm("cp.reduce.async.bulk.global.shared::cta.bulk_group.and.b32  [%0], [%1], %2; // 3."
-            :
-            : "l"(__as_ptr_gmem(__dstMem)), "r"(__as_ptr_smem(__srcMem)), "r"(__size)
-            : "memory");
-      } else _CCCL_IF_CONSTEXPR (sizeof(_Type) == 8) {
-        asm("cp.reduce.async.bulk.global.shared::cta.bulk_group.and.b64  [%0], [%1], %2; // 3."
-            :
-            : "l"(__as_ptr_gmem(__dstMem)), "r"(__as_ptr_smem(__srcMem)), "r"(__size)
-            : "memory");
-      }),
-    (
-      // Unsupported architectures will have a linker error with a semi-decent error message
-      __cuda_ptx_cp_reduce_async_bulk_is_not_supported_before_SM_90__();));
+// __op == op_and_op (due to parameter type constraint)
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  _CCCL_IF_CONSTEXPR (sizeof(_Type) == 4)
+  {
+    asm("cp.reduce.async.bulk.global.shared::cta.bulk_group.and.b32  [%0], [%1], %2; // 3."
+        :
+        : "l"(__as_ptr_gmem(__dstMem)), "r"(__as_ptr_smem(__srcMem)), "r"(__size)
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (sizeof(_Type) == 8)
+  {
+    asm("cp.reduce.async.bulk.global.shared::cta.bulk_group.and.b64  [%0], [%1], %2; // 3."
+        :
+        : "l"(__as_ptr_gmem(__dstMem)), "r"(__as_ptr_smem(__srcMem)), "r"(__size)
+        : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_cp_reduce_async_bulk_is_not_supported_before_SM_90__();
+#  endif
 }
 #endif // __cccl_ptx_isa >= 800
 
@@ -670,24 +710,26 @@ _CCCL_DEVICE static inline void cp_reduce_async_bulk(
   // __space == space_global (due to parameter type constraint)
   // __space == space_shared (due to parameter type constraint)
   static_assert(sizeof(_Type) == 4 || sizeof(_Type) == 8, "");
-  // __op == op_or_op (due to parameter type constraint)
-  NV_IF_ELSE_TARGET(
-    NV_PROVIDES_SM_90,
-    (
-      _CCCL_IF_CONSTEXPR (sizeof(_Type) == 4) {
-        asm("cp.reduce.async.bulk.global.shared::cta.bulk_group.or.b32  [%0], [%1], %2; // 3."
-            :
-            : "l"(__as_ptr_gmem(__dstMem)), "r"(__as_ptr_smem(__srcMem)), "r"(__size)
-            : "memory");
-      } else _CCCL_IF_CONSTEXPR (sizeof(_Type) == 8) {
-        asm("cp.reduce.async.bulk.global.shared::cta.bulk_group.or.b64  [%0], [%1], %2; // 3."
-            :
-            : "l"(__as_ptr_gmem(__dstMem)), "r"(__as_ptr_smem(__srcMem)), "r"(__size)
-            : "memory");
-      }),
-    (
-      // Unsupported architectures will have a linker error with a semi-decent error message
-      __cuda_ptx_cp_reduce_async_bulk_is_not_supported_before_SM_90__();));
+// __op == op_or_op (due to parameter type constraint)
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  _CCCL_IF_CONSTEXPR (sizeof(_Type) == 4)
+  {
+    asm("cp.reduce.async.bulk.global.shared::cta.bulk_group.or.b32  [%0], [%1], %2; // 3."
+        :
+        : "l"(__as_ptr_gmem(__dstMem)), "r"(__as_ptr_smem(__srcMem)), "r"(__size)
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (sizeof(_Type) == 8)
+  {
+    asm("cp.reduce.async.bulk.global.shared::cta.bulk_group.or.b64  [%0], [%1], %2; // 3."
+        :
+        : "l"(__as_ptr_gmem(__dstMem)), "r"(__as_ptr_smem(__srcMem)), "r"(__size)
+        : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_cp_reduce_async_bulk_is_not_supported_before_SM_90__();
+#  endif
 }
 #endif // __cccl_ptx_isa >= 800
 
@@ -715,24 +757,26 @@ _CCCL_DEVICE static inline void cp_reduce_async_bulk(
   // __space == space_global (due to parameter type constraint)
   // __space == space_shared (due to parameter type constraint)
   static_assert(sizeof(_Type) == 4 || sizeof(_Type) == 8, "");
-  // __op == op_xor_op (due to parameter type constraint)
-  NV_IF_ELSE_TARGET(
-    NV_PROVIDES_SM_90,
-    (
-      _CCCL_IF_CONSTEXPR (sizeof(_Type) == 4) {
-        asm("cp.reduce.async.bulk.global.shared::cta.bulk_group.xor.b32  [%0], [%1], %2; // 3."
-            :
-            : "l"(__as_ptr_gmem(__dstMem)), "r"(__as_ptr_smem(__srcMem)), "r"(__size)
-            : "memory");
-      } else _CCCL_IF_CONSTEXPR (sizeof(_Type) == 8) {
-        asm("cp.reduce.async.bulk.global.shared::cta.bulk_group.xor.b64  [%0], [%1], %2; // 3."
-            :
-            : "l"(__as_ptr_gmem(__dstMem)), "r"(__as_ptr_smem(__srcMem)), "r"(__size)
-            : "memory");
-      }),
-    (
-      // Unsupported architectures will have a linker error with a semi-decent error message
-      __cuda_ptx_cp_reduce_async_bulk_is_not_supported_before_SM_90__();));
+// __op == op_xor_op (due to parameter type constraint)
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  _CCCL_IF_CONSTEXPR (sizeof(_Type) == 4)
+  {
+    asm("cp.reduce.async.bulk.global.shared::cta.bulk_group.xor.b32  [%0], [%1], %2; // 3."
+        :
+        : "l"(__as_ptr_gmem(__dstMem)), "r"(__as_ptr_smem(__srcMem)), "r"(__size)
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (sizeof(_Type) == 8)
+  {
+    asm("cp.reduce.async.bulk.global.shared::cta.bulk_group.xor.b64  [%0], [%1], %2; // 3."
+        :
+        : "l"(__as_ptr_gmem(__dstMem)), "r"(__as_ptr_smem(__srcMem)), "r"(__size)
+        : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_cp_reduce_async_bulk_is_not_supported_before_SM_90__();
+#  endif
 }
 #endif // __cccl_ptx_isa >= 800
 
@@ -762,19 +806,19 @@ _CCCL_DEVICE static inline void cp_reduce_async_bulk(
   const _CUDA_VSTD::uint32_t* __srcMem,
   _CUDA_VSTD::uint32_t __size)
 {
-  // __space == space_global (due to parameter type constraint)
-  // __space == space_shared (due to parameter type constraint)
-  // __type == type_u32 (due to parameter type constraint)
-  // __op == op_min (due to parameter type constraint)
-  NV_IF_ELSE_TARGET(
-    NV_PROVIDES_SM_90,
-    (asm("cp.reduce.async.bulk.global.shared::cta.bulk_group.min.u32  [%0], [%1], %2; // 4." : : "l"(
-           __as_ptr_gmem(__dstMem)),
-         "r"(__as_ptr_smem(__srcMem)),
-         "r"(__size) : "memory");),
-    (
-      // Unsupported architectures will have a linker error with a semi-decent error message
-      __cuda_ptx_cp_reduce_async_bulk_is_not_supported_before_SM_90__();));
+// __space == space_global (due to parameter type constraint)
+// __space == space_shared (due to parameter type constraint)
+// __type == type_u32 (due to parameter type constraint)
+// __op == op_min (due to parameter type constraint)
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  asm("cp.reduce.async.bulk.global.shared::cta.bulk_group.min.u32  [%0], [%1], %2; // 4."
+      :
+      : "l"(__as_ptr_gmem(__dstMem)), "r"(__as_ptr_smem(__srcMem)), "r"(__size)
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_cp_reduce_async_bulk_is_not_supported_before_SM_90__();
+#  endif
 }
 #endif // __cccl_ptx_isa >= 800
 
@@ -804,19 +848,19 @@ _CCCL_DEVICE static inline void cp_reduce_async_bulk(
   const _CUDA_VSTD::uint32_t* __srcMem,
   _CUDA_VSTD::uint32_t __size)
 {
-  // __space == space_global (due to parameter type constraint)
-  // __space == space_shared (due to parameter type constraint)
-  // __type == type_u32 (due to parameter type constraint)
-  // __op == op_max (due to parameter type constraint)
-  NV_IF_ELSE_TARGET(
-    NV_PROVIDES_SM_90,
-    (asm("cp.reduce.async.bulk.global.shared::cta.bulk_group.max.u32  [%0], [%1], %2; // 4." : : "l"(
-           __as_ptr_gmem(__dstMem)),
-         "r"(__as_ptr_smem(__srcMem)),
-         "r"(__size) : "memory");),
-    (
-      // Unsupported architectures will have a linker error with a semi-decent error message
-      __cuda_ptx_cp_reduce_async_bulk_is_not_supported_before_SM_90__();));
+// __space == space_global (due to parameter type constraint)
+// __space == space_shared (due to parameter type constraint)
+// __type == type_u32 (due to parameter type constraint)
+// __op == op_max (due to parameter type constraint)
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  asm("cp.reduce.async.bulk.global.shared::cta.bulk_group.max.u32  [%0], [%1], %2; // 4."
+      :
+      : "l"(__as_ptr_gmem(__dstMem)), "r"(__as_ptr_smem(__srcMem)), "r"(__size)
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_cp_reduce_async_bulk_is_not_supported_before_SM_90__();
+#  endif
 }
 #endif // __cccl_ptx_isa >= 800
 
@@ -846,19 +890,19 @@ _CCCL_DEVICE static inline void cp_reduce_async_bulk(
   const _CUDA_VSTD::uint32_t* __srcMem,
   _CUDA_VSTD::uint32_t __size)
 {
-  // __space == space_global (due to parameter type constraint)
-  // __space == space_shared (due to parameter type constraint)
-  // __type == type_u32 (due to parameter type constraint)
-  // __op == op_add (due to parameter type constraint)
-  NV_IF_ELSE_TARGET(
-    NV_PROVIDES_SM_90,
-    (asm("cp.reduce.async.bulk.global.shared::cta.bulk_group.add.u32  [%0], [%1], %2; // 4." : : "l"(
-           __as_ptr_gmem(__dstMem)),
-         "r"(__as_ptr_smem(__srcMem)),
-         "r"(__size) : "memory");),
-    (
-      // Unsupported architectures will have a linker error with a semi-decent error message
-      __cuda_ptx_cp_reduce_async_bulk_is_not_supported_before_SM_90__();));
+// __space == space_global (due to parameter type constraint)
+// __space == space_shared (due to parameter type constraint)
+// __type == type_u32 (due to parameter type constraint)
+// __op == op_add (due to parameter type constraint)
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  asm("cp.reduce.async.bulk.global.shared::cta.bulk_group.add.u32  [%0], [%1], %2; // 4."
+      :
+      : "l"(__as_ptr_gmem(__dstMem)), "r"(__as_ptr_smem(__srcMem)), "r"(__size)
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_cp_reduce_async_bulk_is_not_supported_before_SM_90__();
+#  endif
 }
 #endif // __cccl_ptx_isa >= 800
 
@@ -888,19 +932,19 @@ _CCCL_DEVICE static inline void cp_reduce_async_bulk(
   const _CUDA_VSTD::uint32_t* __srcMem,
   _CUDA_VSTD::uint32_t __size)
 {
-  // __space == space_global (due to parameter type constraint)
-  // __space == space_shared (due to parameter type constraint)
-  // __type == type_u32 (due to parameter type constraint)
-  // __op == op_inc (due to parameter type constraint)
-  NV_IF_ELSE_TARGET(
-    NV_PROVIDES_SM_90,
-    (asm("cp.reduce.async.bulk.global.shared::cta.bulk_group.inc.u32  [%0], [%1], %2; // 4." : : "l"(
-           __as_ptr_gmem(__dstMem)),
-         "r"(__as_ptr_smem(__srcMem)),
-         "r"(__size) : "memory");),
-    (
-      // Unsupported architectures will have a linker error with a semi-decent error message
-      __cuda_ptx_cp_reduce_async_bulk_is_not_supported_before_SM_90__();));
+// __space == space_global (due to parameter type constraint)
+// __space == space_shared (due to parameter type constraint)
+// __type == type_u32 (due to parameter type constraint)
+// __op == op_inc (due to parameter type constraint)
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  asm("cp.reduce.async.bulk.global.shared::cta.bulk_group.inc.u32  [%0], [%1], %2; // 4."
+      :
+      : "l"(__as_ptr_gmem(__dstMem)), "r"(__as_ptr_smem(__srcMem)), "r"(__size)
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_cp_reduce_async_bulk_is_not_supported_before_SM_90__();
+#  endif
 }
 #endif // __cccl_ptx_isa >= 800
 
@@ -930,19 +974,19 @@ _CCCL_DEVICE static inline void cp_reduce_async_bulk(
   const _CUDA_VSTD::uint32_t* __srcMem,
   _CUDA_VSTD::uint32_t __size)
 {
-  // __space == space_global (due to parameter type constraint)
-  // __space == space_shared (due to parameter type constraint)
-  // __type == type_u32 (due to parameter type constraint)
-  // __op == op_dec (due to parameter type constraint)
-  NV_IF_ELSE_TARGET(
-    NV_PROVIDES_SM_90,
-    (asm("cp.reduce.async.bulk.global.shared::cta.bulk_group.dec.u32  [%0], [%1], %2; // 4." : : "l"(
-           __as_ptr_gmem(__dstMem)),
-         "r"(__as_ptr_smem(__srcMem)),
-         "r"(__size) : "memory");),
-    (
-      // Unsupported architectures will have a linker error with a semi-decent error message
-      __cuda_ptx_cp_reduce_async_bulk_is_not_supported_before_SM_90__();));
+// __space == space_global (due to parameter type constraint)
+// __space == space_shared (due to parameter type constraint)
+// __type == type_u32 (due to parameter type constraint)
+// __op == op_dec (due to parameter type constraint)
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  asm("cp.reduce.async.bulk.global.shared::cta.bulk_group.dec.u32  [%0], [%1], %2; // 4."
+      :
+      : "l"(__as_ptr_gmem(__dstMem)), "r"(__as_ptr_smem(__srcMem)), "r"(__size)
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_cp_reduce_async_bulk_is_not_supported_before_SM_90__();
+#  endif
 }
 #endif // __cccl_ptx_isa >= 800
 
@@ -972,19 +1016,19 @@ _CCCL_DEVICE static inline void cp_reduce_async_bulk(
   const _CUDA_VSTD::int32_t* __srcMem,
   _CUDA_VSTD::uint32_t __size)
 {
-  // __space == space_global (due to parameter type constraint)
-  // __space == space_shared (due to parameter type constraint)
-  // __type == type_s32 (due to parameter type constraint)
-  // __op == op_min (due to parameter type constraint)
-  NV_IF_ELSE_TARGET(
-    NV_PROVIDES_SM_90,
-    (asm("cp.reduce.async.bulk.global.shared::cta.bulk_group.min.s32  [%0], [%1], %2; // 4." : : "l"(
-           __as_ptr_gmem(__dstMem)),
-         "r"(__as_ptr_smem(__srcMem)),
-         "r"(__size) : "memory");),
-    (
-      // Unsupported architectures will have a linker error with a semi-decent error message
-      __cuda_ptx_cp_reduce_async_bulk_is_not_supported_before_SM_90__();));
+// __space == space_global (due to parameter type constraint)
+// __space == space_shared (due to parameter type constraint)
+// __type == type_s32 (due to parameter type constraint)
+// __op == op_min (due to parameter type constraint)
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  asm("cp.reduce.async.bulk.global.shared::cta.bulk_group.min.s32  [%0], [%1], %2; // 4."
+      :
+      : "l"(__as_ptr_gmem(__dstMem)), "r"(__as_ptr_smem(__srcMem)), "r"(__size)
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_cp_reduce_async_bulk_is_not_supported_before_SM_90__();
+#  endif
 }
 #endif // __cccl_ptx_isa >= 800
 
@@ -1014,19 +1058,19 @@ _CCCL_DEVICE static inline void cp_reduce_async_bulk(
   const _CUDA_VSTD::int32_t* __srcMem,
   _CUDA_VSTD::uint32_t __size)
 {
-  // __space == space_global (due to parameter type constraint)
-  // __space == space_shared (due to parameter type constraint)
-  // __type == type_s32 (due to parameter type constraint)
-  // __op == op_max (due to parameter type constraint)
-  NV_IF_ELSE_TARGET(
-    NV_PROVIDES_SM_90,
-    (asm("cp.reduce.async.bulk.global.shared::cta.bulk_group.max.s32  [%0], [%1], %2; // 4." : : "l"(
-           __as_ptr_gmem(__dstMem)),
-         "r"(__as_ptr_smem(__srcMem)),
-         "r"(__size) : "memory");),
-    (
-      // Unsupported architectures will have a linker error with a semi-decent error message
-      __cuda_ptx_cp_reduce_async_bulk_is_not_supported_before_SM_90__();));
+// __space == space_global (due to parameter type constraint)
+// __space == space_shared (due to parameter type constraint)
+// __type == type_s32 (due to parameter type constraint)
+// __op == op_max (due to parameter type constraint)
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  asm("cp.reduce.async.bulk.global.shared::cta.bulk_group.max.s32  [%0], [%1], %2; // 4."
+      :
+      : "l"(__as_ptr_gmem(__dstMem)), "r"(__as_ptr_smem(__srcMem)), "r"(__size)
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_cp_reduce_async_bulk_is_not_supported_before_SM_90__();
+#  endif
 }
 #endif // __cccl_ptx_isa >= 800
 
@@ -1056,19 +1100,19 @@ _CCCL_DEVICE static inline void cp_reduce_async_bulk(
   const _CUDA_VSTD::int32_t* __srcMem,
   _CUDA_VSTD::uint32_t __size)
 {
-  // __space == space_global (due to parameter type constraint)
-  // __space == space_shared (due to parameter type constraint)
-  // __type == type_s32 (due to parameter type constraint)
-  // __op == op_add (due to parameter type constraint)
-  NV_IF_ELSE_TARGET(
-    NV_PROVIDES_SM_90,
-    (asm("cp.reduce.async.bulk.global.shared::cta.bulk_group.add.s32  [%0], [%1], %2; // 4." : : "l"(
-           __as_ptr_gmem(__dstMem)),
-         "r"(__as_ptr_smem(__srcMem)),
-         "r"(__size) : "memory");),
-    (
-      // Unsupported architectures will have a linker error with a semi-decent error message
-      __cuda_ptx_cp_reduce_async_bulk_is_not_supported_before_SM_90__();));
+// __space == space_global (due to parameter type constraint)
+// __space == space_shared (due to parameter type constraint)
+// __type == type_s32 (due to parameter type constraint)
+// __op == op_add (due to parameter type constraint)
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  asm("cp.reduce.async.bulk.global.shared::cta.bulk_group.add.s32  [%0], [%1], %2; // 4."
+      :
+      : "l"(__as_ptr_gmem(__dstMem)), "r"(__as_ptr_smem(__srcMem)), "r"(__size)
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_cp_reduce_async_bulk_is_not_supported_before_SM_90__();
+#  endif
 }
 #endif // __cccl_ptx_isa >= 800
 
@@ -1098,19 +1142,19 @@ _CCCL_DEVICE static inline void cp_reduce_async_bulk(
   const _CUDA_VSTD::uint64_t* __srcMem,
   _CUDA_VSTD::uint32_t __size)
 {
-  // __space == space_global (due to parameter type constraint)
-  // __space == space_shared (due to parameter type constraint)
-  // __type == type_u64 (due to parameter type constraint)
-  // __op == op_min (due to parameter type constraint)
-  NV_IF_ELSE_TARGET(
-    NV_PROVIDES_SM_90,
-    (asm("cp.reduce.async.bulk.global.shared::cta.bulk_group.min.u64  [%0], [%1], %2; // 4." : : "l"(
-           __as_ptr_gmem(__dstMem)),
-         "r"(__as_ptr_smem(__srcMem)),
-         "r"(__size) : "memory");),
-    (
-      // Unsupported architectures will have a linker error with a semi-decent error message
-      __cuda_ptx_cp_reduce_async_bulk_is_not_supported_before_SM_90__();));
+// __space == space_global (due to parameter type constraint)
+// __space == space_shared (due to parameter type constraint)
+// __type == type_u64 (due to parameter type constraint)
+// __op == op_min (due to parameter type constraint)
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  asm("cp.reduce.async.bulk.global.shared::cta.bulk_group.min.u64  [%0], [%1], %2; // 4."
+      :
+      : "l"(__as_ptr_gmem(__dstMem)), "r"(__as_ptr_smem(__srcMem)), "r"(__size)
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_cp_reduce_async_bulk_is_not_supported_before_SM_90__();
+#  endif
 }
 #endif // __cccl_ptx_isa >= 800
 
@@ -1140,19 +1184,19 @@ _CCCL_DEVICE static inline void cp_reduce_async_bulk(
   const _CUDA_VSTD::uint64_t* __srcMem,
   _CUDA_VSTD::uint32_t __size)
 {
-  // __space == space_global (due to parameter type constraint)
-  // __space == space_shared (due to parameter type constraint)
-  // __type == type_u64 (due to parameter type constraint)
-  // __op == op_max (due to parameter type constraint)
-  NV_IF_ELSE_TARGET(
-    NV_PROVIDES_SM_90,
-    (asm("cp.reduce.async.bulk.global.shared::cta.bulk_group.max.u64  [%0], [%1], %2; // 4." : : "l"(
-           __as_ptr_gmem(__dstMem)),
-         "r"(__as_ptr_smem(__srcMem)),
-         "r"(__size) : "memory");),
-    (
-      // Unsupported architectures will have a linker error with a semi-decent error message
-      __cuda_ptx_cp_reduce_async_bulk_is_not_supported_before_SM_90__();));
+// __space == space_global (due to parameter type constraint)
+// __space == space_shared (due to parameter type constraint)
+// __type == type_u64 (due to parameter type constraint)
+// __op == op_max (due to parameter type constraint)
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  asm("cp.reduce.async.bulk.global.shared::cta.bulk_group.max.u64  [%0], [%1], %2; // 4."
+      :
+      : "l"(__as_ptr_gmem(__dstMem)), "r"(__as_ptr_smem(__srcMem)), "r"(__size)
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_cp_reduce_async_bulk_is_not_supported_before_SM_90__();
+#  endif
 }
 #endif // __cccl_ptx_isa >= 800
 
@@ -1182,19 +1226,19 @@ _CCCL_DEVICE static inline void cp_reduce_async_bulk(
   const _CUDA_VSTD::uint64_t* __srcMem,
   _CUDA_VSTD::uint32_t __size)
 {
-  // __space == space_global (due to parameter type constraint)
-  // __space == space_shared (due to parameter type constraint)
-  // __type == type_u64 (due to parameter type constraint)
-  // __op == op_add (due to parameter type constraint)
-  NV_IF_ELSE_TARGET(
-    NV_PROVIDES_SM_90,
-    (asm("cp.reduce.async.bulk.global.shared::cta.bulk_group.add.u64  [%0], [%1], %2; // 4." : : "l"(
-           __as_ptr_gmem(__dstMem)),
-         "r"(__as_ptr_smem(__srcMem)),
-         "r"(__size) : "memory");),
-    (
-      // Unsupported architectures will have a linker error with a semi-decent error message
-      __cuda_ptx_cp_reduce_async_bulk_is_not_supported_before_SM_90__();));
+// __space == space_global (due to parameter type constraint)
+// __space == space_shared (due to parameter type constraint)
+// __type == type_u64 (due to parameter type constraint)
+// __op == op_add (due to parameter type constraint)
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  asm("cp.reduce.async.bulk.global.shared::cta.bulk_group.add.u64  [%0], [%1], %2; // 4."
+      :
+      : "l"(__as_ptr_gmem(__dstMem)), "r"(__as_ptr_smem(__srcMem)), "r"(__size)
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_cp_reduce_async_bulk_is_not_supported_before_SM_90__();
+#  endif
 }
 #endif // __cccl_ptx_isa >= 800
 
@@ -1224,19 +1268,19 @@ _CCCL_DEVICE static inline void cp_reduce_async_bulk(
   const _CUDA_VSTD::int64_t* __srcMem,
   _CUDA_VSTD::uint32_t __size)
 {
-  // __space == space_global (due to parameter type constraint)
-  // __space == space_shared (due to parameter type constraint)
-  // __type == type_s64 (due to parameter type constraint)
-  // __op == op_min (due to parameter type constraint)
-  NV_IF_ELSE_TARGET(
-    NV_PROVIDES_SM_90,
-    (asm("cp.reduce.async.bulk.global.shared::cta.bulk_group.min.s64  [%0], [%1], %2; // 4." : : "l"(
-           __as_ptr_gmem(__dstMem)),
-         "r"(__as_ptr_smem(__srcMem)),
-         "r"(__size) : "memory");),
-    (
-      // Unsupported architectures will have a linker error with a semi-decent error message
-      __cuda_ptx_cp_reduce_async_bulk_is_not_supported_before_SM_90__();));
+// __space == space_global (due to parameter type constraint)
+// __space == space_shared (due to parameter type constraint)
+// __type == type_s64 (due to parameter type constraint)
+// __op == op_min (due to parameter type constraint)
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  asm("cp.reduce.async.bulk.global.shared::cta.bulk_group.min.s64  [%0], [%1], %2; // 4."
+      :
+      : "l"(__as_ptr_gmem(__dstMem)), "r"(__as_ptr_smem(__srcMem)), "r"(__size)
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_cp_reduce_async_bulk_is_not_supported_before_SM_90__();
+#  endif
 }
 #endif // __cccl_ptx_isa >= 800
 
@@ -1266,19 +1310,19 @@ _CCCL_DEVICE static inline void cp_reduce_async_bulk(
   const _CUDA_VSTD::int64_t* __srcMem,
   _CUDA_VSTD::uint32_t __size)
 {
-  // __space == space_global (due to parameter type constraint)
-  // __space == space_shared (due to parameter type constraint)
-  // __type == type_s64 (due to parameter type constraint)
-  // __op == op_max (due to parameter type constraint)
-  NV_IF_ELSE_TARGET(
-    NV_PROVIDES_SM_90,
-    (asm("cp.reduce.async.bulk.global.shared::cta.bulk_group.max.s64  [%0], [%1], %2; // 4." : : "l"(
-           __as_ptr_gmem(__dstMem)),
-         "r"(__as_ptr_smem(__srcMem)),
-         "r"(__size) : "memory");),
-    (
-      // Unsupported architectures will have a linker error with a semi-decent error message
-      __cuda_ptx_cp_reduce_async_bulk_is_not_supported_before_SM_90__();));
+// __space == space_global (due to parameter type constraint)
+// __space == space_shared (due to parameter type constraint)
+// __type == type_s64 (due to parameter type constraint)
+// __op == op_max (due to parameter type constraint)
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  asm("cp.reduce.async.bulk.global.shared::cta.bulk_group.max.s64  [%0], [%1], %2; // 4."
+      :
+      : "l"(__as_ptr_gmem(__dstMem)), "r"(__as_ptr_smem(__srcMem)), "r"(__size)
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_cp_reduce_async_bulk_is_not_supported_before_SM_90__();
+#  endif
 }
 #endif // __cccl_ptx_isa >= 800
 
@@ -1303,19 +1347,19 @@ template <typename = void>
 _CCCL_DEVICE static inline void cp_reduce_async_bulk(
   space_global_t, space_shared_t, op_add_t, float* __dstMem, const float* __srcMem, _CUDA_VSTD::uint32_t __size)
 {
-  // __space == space_global (due to parameter type constraint)
-  // __space == space_shared (due to parameter type constraint)
-  // __type == type_f32 (due to parameter type constraint)
-  // __op == op_add (due to parameter type constraint)
-  NV_IF_ELSE_TARGET(
-    NV_PROVIDES_SM_90,
-    (asm("cp.reduce.async.bulk.global.shared::cta.bulk_group.add.f32  [%0], [%1], %2; // 4." : : "l"(
-           __as_ptr_gmem(__dstMem)),
-         "r"(__as_ptr_smem(__srcMem)),
-         "r"(__size) : "memory");),
-    (
-      // Unsupported architectures will have a linker error with a semi-decent error message
-      __cuda_ptx_cp_reduce_async_bulk_is_not_supported_before_SM_90__();));
+// __space == space_global (due to parameter type constraint)
+// __space == space_shared (due to parameter type constraint)
+// __type == type_f32 (due to parameter type constraint)
+// __op == op_add (due to parameter type constraint)
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  asm("cp.reduce.async.bulk.global.shared::cta.bulk_group.add.f32  [%0], [%1], %2; // 4."
+      :
+      : "l"(__as_ptr_gmem(__dstMem)), "r"(__as_ptr_smem(__srcMem)), "r"(__size)
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_cp_reduce_async_bulk_is_not_supported_before_SM_90__();
+#  endif
 }
 #endif // __cccl_ptx_isa >= 800
 
@@ -1340,19 +1384,19 @@ template <typename = void>
 _CCCL_DEVICE static inline void cp_reduce_async_bulk(
   space_global_t, space_shared_t, op_add_t, double* __dstMem, const double* __srcMem, _CUDA_VSTD::uint32_t __size)
 {
-  // __space == space_global (due to parameter type constraint)
-  // __space == space_shared (due to parameter type constraint)
-  // __type == type_f64 (due to parameter type constraint)
-  // __op == op_add (due to parameter type constraint)
-  NV_IF_ELSE_TARGET(
-    NV_PROVIDES_SM_90,
-    (asm("cp.reduce.async.bulk.global.shared::cta.bulk_group.add.f64  [%0], [%1], %2; // 4." : : "l"(
-           __as_ptr_gmem(__dstMem)),
-         "r"(__as_ptr_smem(__srcMem)),
-         "r"(__size) : "memory");),
-    (
-      // Unsupported architectures will have a linker error with a semi-decent error message
-      __cuda_ptx_cp_reduce_async_bulk_is_not_supported_before_SM_90__();));
+// __space == space_global (due to parameter type constraint)
+// __space == space_shared (due to parameter type constraint)
+// __type == type_f64 (due to parameter type constraint)
+// __op == op_add (due to parameter type constraint)
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  asm("cp.reduce.async.bulk.global.shared::cta.bulk_group.add.f64  [%0], [%1], %2; // 4."
+      :
+      : "l"(__as_ptr_gmem(__dstMem)), "r"(__as_ptr_smem(__srcMem)), "r"(__size)
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_cp_reduce_async_bulk_is_not_supported_before_SM_90__();
+#  endif
 }
 #endif // __cccl_ptx_isa >= 800
 
@@ -1382,19 +1426,19 @@ _CCCL_DEVICE static inline void cp_reduce_async_bulk(
   const _CUDA_VSTD::int64_t* __srcMem,
   _CUDA_VSTD::uint32_t __size)
 {
-  // __space == space_global (due to parameter type constraint)
-  // __space == space_shared (due to parameter type constraint)
-  // __type == type_s64 (due to parameter type constraint)
-  // __op == op_add (due to parameter type constraint)
-  NV_IF_ELSE_TARGET(
-    NV_PROVIDES_SM_90,
-    (asm("cp.reduce.async.bulk.global.shared::cta.bulk_group.add.u64  [%0], [%1], %2; // 6." : : "l"(
-           __as_ptr_gmem(__dstMem)),
-         "r"(__as_ptr_smem(__srcMem)),
-         "r"(__size) : "memory");),
-    (
-      // Unsupported architectures will have a linker error with a semi-decent error message
-      __cuda_ptx_cp_reduce_async_bulk_is_not_supported_before_SM_90__();));
+// __space == space_global (due to parameter type constraint)
+// __space == space_shared (due to parameter type constraint)
+// __type == type_s64 (due to parameter type constraint)
+// __op == op_add (due to parameter type constraint)
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  asm("cp.reduce.async.bulk.global.shared::cta.bulk_group.add.u64  [%0], [%1], %2; // 6."
+      :
+      : "l"(__as_ptr_gmem(__dstMem)), "r"(__as_ptr_smem(__srcMem)), "r"(__size)
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_cp_reduce_async_bulk_is_not_supported_before_SM_90__();
+#  endif
 }
 #endif // __cccl_ptx_isa >= 800
 
diff --git a/libcudacxx/include/cuda/__ptx/instructions/generated/cp_reduce_async_bulk_bf16.h b/libcudacxx/include/cuda/__ptx/instructions/generated/cp_reduce_async_bulk_bf16.h
index da5cdb6bc9b..5c177976468 100644
--- a/libcudacxx/include/cuda/__ptx/instructions/generated/cp_reduce_async_bulk_bf16.h
+++ b/libcudacxx/include/cuda/__ptx/instructions/generated/cp_reduce_async_bulk_bf16.h
@@ -29,19 +29,19 @@ _CCCL_DEVICE static inline void cp_reduce_async_bulk(
   const __nv_bfloat16* __srcMem,
   _CUDA_VSTD::uint32_t __size)
 {
-  // __space == space_global (due to parameter type constraint)
-  // __space == space_shared (due to parameter type constraint)
-  // __type == type_bf16 (due to parameter type constraint)
-  // __op == op_min (due to parameter type constraint)
-  NV_IF_ELSE_TARGET(
-    NV_PROVIDES_SM_90,
-    (asm("cp.reduce.async.bulk.global.shared::cta.bulk_group.min.bf16  [%0], [%1], %2; // 4." : : "l"(
-           __as_ptr_gmem(__dstMem)),
-         "r"(__as_ptr_smem(__srcMem)),
-         "r"(__size) : "memory");),
-    (
-      // Unsupported architectures will have a linker error with a semi-decent error message
-      __cuda_ptx_cp_reduce_async_bulk_is_not_supported_before_SM_90__();));
+// __space == space_global (due to parameter type constraint)
+// __space == space_shared (due to parameter type constraint)
+// __type == type_bf16 (due to parameter type constraint)
+// __op == op_min (due to parameter type constraint)
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  asm("cp.reduce.async.bulk.global.shared::cta.bulk_group.min.bf16  [%0], [%1], %2; // 4."
+      :
+      : "l"(__as_ptr_gmem(__dstMem)), "r"(__as_ptr_smem(__srcMem)), "r"(__size)
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_cp_reduce_async_bulk_is_not_supported_before_SM_90__();
+#  endif
 }
 #endif // __cccl_ptx_isa >= 800
 
@@ -71,19 +71,19 @@ _CCCL_DEVICE static inline void cp_reduce_async_bulk(
   const __nv_bfloat16* __srcMem,
   _CUDA_VSTD::uint32_t __size)
 {
-  // __space == space_global (due to parameter type constraint)
-  // __space == space_shared (due to parameter type constraint)
-  // __type == type_bf16 (due to parameter type constraint)
-  // __op == op_max (due to parameter type constraint)
-  NV_IF_ELSE_TARGET(
-    NV_PROVIDES_SM_90,
-    (asm("cp.reduce.async.bulk.global.shared::cta.bulk_group.max.bf16  [%0], [%1], %2; // 4." : : "l"(
-           __as_ptr_gmem(__dstMem)),
-         "r"(__as_ptr_smem(__srcMem)),
-         "r"(__size) : "memory");),
-    (
-      // Unsupported architectures will have a linker error with a semi-decent error message
-      __cuda_ptx_cp_reduce_async_bulk_is_not_supported_before_SM_90__();));
+// __space == space_global (due to parameter type constraint)
+// __space == space_shared (due to parameter type constraint)
+// __type == type_bf16 (due to parameter type constraint)
+// __op == op_max (due to parameter type constraint)
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  asm("cp.reduce.async.bulk.global.shared::cta.bulk_group.max.bf16  [%0], [%1], %2; // 4."
+      :
+      : "l"(__as_ptr_gmem(__dstMem)), "r"(__as_ptr_smem(__srcMem)), "r"(__size)
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_cp_reduce_async_bulk_is_not_supported_before_SM_90__();
+#  endif
 }
 #endif // __cccl_ptx_isa >= 800
 
@@ -113,19 +113,19 @@ _CCCL_DEVICE static inline void cp_reduce_async_bulk(
   const __nv_bfloat16* __srcMem,
   _CUDA_VSTD::uint32_t __size)
 {
-  // __space == space_global (due to parameter type constraint)
-  // __space == space_shared (due to parameter type constraint)
-  // __type == type_bf16 (due to parameter type constraint)
-  // __op == op_add (due to parameter type constraint)
-  NV_IF_ELSE_TARGET(
-    NV_PROVIDES_SM_90,
-    (asm("cp.reduce.async.bulk.global.shared::cta.bulk_group.add.noftz.bf16  [%0], [%1], %2; // 5." : : "l"(
-           __as_ptr_gmem(__dstMem)),
-         "r"(__as_ptr_smem(__srcMem)),
-         "r"(__size) : "memory");),
-    (
-      // Unsupported architectures will have a linker error with a semi-decent error message
-      __cuda_ptx_cp_reduce_async_bulk_is_not_supported_before_SM_90__();));
+// __space == space_global (due to parameter type constraint)
+// __space == space_shared (due to parameter type constraint)
+// __type == type_bf16 (due to parameter type constraint)
+// __op == op_add (due to parameter type constraint)
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  asm("cp.reduce.async.bulk.global.shared::cta.bulk_group.add.noftz.bf16  [%0], [%1], %2; // 5."
+      :
+      : "l"(__as_ptr_gmem(__dstMem)), "r"(__as_ptr_smem(__srcMem)), "r"(__size)
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_cp_reduce_async_bulk_is_not_supported_before_SM_90__();
+#  endif
 }
 #endif // __cccl_ptx_isa >= 800
 
diff --git a/libcudacxx/include/cuda/__ptx/instructions/generated/cp_reduce_async_bulk_f16.h b/libcudacxx/include/cuda/__ptx/instructions/generated/cp_reduce_async_bulk_f16.h
index 3d9d4520dcb..95d775d09e2 100644
--- a/libcudacxx/include/cuda/__ptx/instructions/generated/cp_reduce_async_bulk_f16.h
+++ b/libcudacxx/include/cuda/__ptx/instructions/generated/cp_reduce_async_bulk_f16.h
@@ -24,19 +24,19 @@ template <typename = void>
 _CCCL_DEVICE static inline void cp_reduce_async_bulk(
   space_global_t, space_shared_t, op_min_t, __half* __dstMem, const __half* __srcMem, _CUDA_VSTD::uint32_t __size)
 {
-  // __space == space_global (due to parameter type constraint)
-  // __space == space_shared (due to parameter type constraint)
-  // __type == type_f16 (due to parameter type constraint)
-  // __op == op_min (due to parameter type constraint)
-  NV_IF_ELSE_TARGET(
-    NV_PROVIDES_SM_90,
-    (asm("cp.reduce.async.bulk.global.shared::cta.bulk_group.min.f16  [%0], [%1], %2; // 4." : : "l"(
-           __as_ptr_gmem(__dstMem)),
-         "r"(__as_ptr_smem(__srcMem)),
-         "r"(__size) : "memory");),
-    (
-      // Unsupported architectures will have a linker error with a semi-decent error message
-      __cuda_ptx_cp_reduce_async_bulk_is_not_supported_before_SM_90__();));
+// __space == space_global (due to parameter type constraint)
+// __space == space_shared (due to parameter type constraint)
+// __type == type_f16 (due to parameter type constraint)
+// __op == op_min (due to parameter type constraint)
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  asm("cp.reduce.async.bulk.global.shared::cta.bulk_group.min.f16  [%0], [%1], %2; // 4."
+      :
+      : "l"(__as_ptr_gmem(__dstMem)), "r"(__as_ptr_smem(__srcMem)), "r"(__size)
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_cp_reduce_async_bulk_is_not_supported_before_SM_90__();
+#  endif
 }
 #endif // __cccl_ptx_isa >= 800
 
@@ -61,19 +61,19 @@ template <typename = void>
 _CCCL_DEVICE static inline void cp_reduce_async_bulk(
   space_global_t, space_shared_t, op_max_t, __half* __dstMem, const __half* __srcMem, _CUDA_VSTD::uint32_t __size)
 {
-  // __space == space_global (due to parameter type constraint)
-  // __space == space_shared (due to parameter type constraint)
-  // __type == type_f16 (due to parameter type constraint)
-  // __op == op_max (due to parameter type constraint)
-  NV_IF_ELSE_TARGET(
-    NV_PROVIDES_SM_90,
-    (asm("cp.reduce.async.bulk.global.shared::cta.bulk_group.max.f16  [%0], [%1], %2; // 4." : : "l"(
-           __as_ptr_gmem(__dstMem)),
-         "r"(__as_ptr_smem(__srcMem)),
-         "r"(__size) : "memory");),
-    (
-      // Unsupported architectures will have a linker error with a semi-decent error message
-      __cuda_ptx_cp_reduce_async_bulk_is_not_supported_before_SM_90__();));
+// __space == space_global (due to parameter type constraint)
+// __space == space_shared (due to parameter type constraint)
+// __type == type_f16 (due to parameter type constraint)
+// __op == op_max (due to parameter type constraint)
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  asm("cp.reduce.async.bulk.global.shared::cta.bulk_group.max.f16  [%0], [%1], %2; // 4."
+      :
+      : "l"(__as_ptr_gmem(__dstMem)), "r"(__as_ptr_smem(__srcMem)), "r"(__size)
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_cp_reduce_async_bulk_is_not_supported_before_SM_90__();
+#  endif
 }
 #endif // __cccl_ptx_isa >= 800
 
@@ -98,19 +98,19 @@ template <typename = void>
 _CCCL_DEVICE static inline void cp_reduce_async_bulk(
   space_global_t, space_shared_t, op_add_t, __half* __dstMem, const __half* __srcMem, _CUDA_VSTD::uint32_t __size)
 {
-  // __space == space_global (due to parameter type constraint)
-  // __space == space_shared (due to parameter type constraint)
-  // __type == type_f16 (due to parameter type constraint)
-  // __op == op_add (due to parameter type constraint)
-  NV_IF_ELSE_TARGET(
-    NV_PROVIDES_SM_90,
-    (asm("cp.reduce.async.bulk.global.shared::cta.bulk_group.add.noftz.f16  [%0], [%1], %2; // 5." : : "l"(
-           __as_ptr_gmem(__dstMem)),
-         "r"(__as_ptr_smem(__srcMem)),
-         "r"(__size) : "memory");),
-    (
-      // Unsupported architectures will have a linker error with a semi-decent error message
-      __cuda_ptx_cp_reduce_async_bulk_is_not_supported_before_SM_90__();));
+// __space == space_global (due to parameter type constraint)
+// __space == space_shared (due to parameter type constraint)
+// __type == type_f16 (due to parameter type constraint)
+// __op == op_add (due to parameter type constraint)
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  asm("cp.reduce.async.bulk.global.shared::cta.bulk_group.add.noftz.f16  [%0], [%1], %2; // 5."
+      :
+      : "l"(__as_ptr_gmem(__dstMem)), "r"(__as_ptr_smem(__srcMem)), "r"(__size)
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_cp_reduce_async_bulk_is_not_supported_before_SM_90__();
+#  endif
 }
 #endif // __cccl_ptx_isa >= 800
 
diff --git a/libcudacxx/include/cuda/__ptx/instructions/generated/cp_reduce_async_bulk_tensor.h b/libcudacxx/include/cuda/__ptx/instructions/generated/cp_reduce_async_bulk_tensor.h
index 9ec5b2443d8..540b0e95ed5 100644
--- a/libcudacxx/include/cuda/__ptx/instructions/generated/cp_reduce_async_bulk_tensor.h
+++ b/libcudacxx/include/cuda/__ptx/instructions/generated/cp_reduce_async_bulk_tensor.h
@@ -34,53 +34,67 @@ _CCCL_DEVICE static inline void cp_reduce_async_bulk_tensor(
   static_assert(__op == op_add || __op == op_min || __op == op_max || __op == op_inc || __op == op_dec
                   || __op == op_and_op || __op == op_or_op || __op == op_xor_op,
                 "");
-  NV_IF_ELSE_TARGET(
-    NV_PROVIDES_SM_90,
-    (
-      _CCCL_IF_CONSTEXPR (__op == op_add) {
-        asm("cp.reduce.async.bulk.tensor.1d.global.shared::cta.add.tile.bulk_group [%0, {%1}], [%2]; // 1a."
-            :
-            : "l"(__tensorMap), "r"(__tensorCoords[0]), "r"(__as_ptr_smem(__srcMem))
-            : "memory");
-      } else _CCCL_IF_CONSTEXPR (__op == op_min) {
-        asm("cp.reduce.async.bulk.tensor.1d.global.shared::cta.min.tile.bulk_group [%0, {%1}], [%2]; // 1a."
-            :
-            : "l"(__tensorMap), "r"(__tensorCoords[0]), "r"(__as_ptr_smem(__srcMem))
-            : "memory");
-      } else _CCCL_IF_CONSTEXPR (__op == op_max) {
-        asm("cp.reduce.async.bulk.tensor.1d.global.shared::cta.max.tile.bulk_group [%0, {%1}], [%2]; // 1a."
-            :
-            : "l"(__tensorMap), "r"(__tensorCoords[0]), "r"(__as_ptr_smem(__srcMem))
-            : "memory");
-      } else _CCCL_IF_CONSTEXPR (__op == op_inc) {
-        asm("cp.reduce.async.bulk.tensor.1d.global.shared::cta.inc.tile.bulk_group [%0, {%1}], [%2]; // 1a."
-            :
-            : "l"(__tensorMap), "r"(__tensorCoords[0]), "r"(__as_ptr_smem(__srcMem))
-            : "memory");
-      } else _CCCL_IF_CONSTEXPR (__op == op_dec) {
-        asm("cp.reduce.async.bulk.tensor.1d.global.shared::cta.dec.tile.bulk_group [%0, {%1}], [%2]; // 1a."
-            :
-            : "l"(__tensorMap), "r"(__tensorCoords[0]), "r"(__as_ptr_smem(__srcMem))
-            : "memory");
-      } else _CCCL_IF_CONSTEXPR (__op == op_and_op) {
-        asm("cp.reduce.async.bulk.tensor.1d.global.shared::cta.and.tile.bulk_group [%0, {%1}], [%2]; // 1a."
-            :
-            : "l"(__tensorMap), "r"(__tensorCoords[0]), "r"(__as_ptr_smem(__srcMem))
-            : "memory");
-      } else _CCCL_IF_CONSTEXPR (__op == op_or_op) {
-        asm("cp.reduce.async.bulk.tensor.1d.global.shared::cta.or.tile.bulk_group [%0, {%1}], [%2]; // 1a."
-            :
-            : "l"(__tensorMap), "r"(__tensorCoords[0]), "r"(__as_ptr_smem(__srcMem))
-            : "memory");
-      } else _CCCL_IF_CONSTEXPR (__op == op_xor_op) {
-        asm("cp.reduce.async.bulk.tensor.1d.global.shared::cta.xor.tile.bulk_group [%0, {%1}], [%2]; // 1a."
-            :
-            : "l"(__tensorMap), "r"(__tensorCoords[0]), "r"(__as_ptr_smem(__srcMem))
-            : "memory");
-      }),
-    (
-      // Unsupported architectures will have a linker error with a semi-decent error message
-      __cuda_ptx_cp_reduce_async_bulk_tensor_is_not_supported_before_SM_90__();));
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  _CCCL_IF_CONSTEXPR (__op == op_add)
+  {
+    asm("cp.reduce.async.bulk.tensor.1d.global.shared::cta.add.tile.bulk_group [%0, {%1}], [%2]; // 1a."
+        :
+        : "l"(__tensorMap), "r"(__tensorCoords[0]), "r"(__as_ptr_smem(__srcMem))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__op == op_min)
+  {
+    asm("cp.reduce.async.bulk.tensor.1d.global.shared::cta.min.tile.bulk_group [%0, {%1}], [%2]; // 1a."
+        :
+        : "l"(__tensorMap), "r"(__tensorCoords[0]), "r"(__as_ptr_smem(__srcMem))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__op == op_max)
+  {
+    asm("cp.reduce.async.bulk.tensor.1d.global.shared::cta.max.tile.bulk_group [%0, {%1}], [%2]; // 1a."
+        :
+        : "l"(__tensorMap), "r"(__tensorCoords[0]), "r"(__as_ptr_smem(__srcMem))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__op == op_inc)
+  {
+    asm("cp.reduce.async.bulk.tensor.1d.global.shared::cta.inc.tile.bulk_group [%0, {%1}], [%2]; // 1a."
+        :
+        : "l"(__tensorMap), "r"(__tensorCoords[0]), "r"(__as_ptr_smem(__srcMem))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__op == op_dec)
+  {
+    asm("cp.reduce.async.bulk.tensor.1d.global.shared::cta.dec.tile.bulk_group [%0, {%1}], [%2]; // 1a."
+        :
+        : "l"(__tensorMap), "r"(__tensorCoords[0]), "r"(__as_ptr_smem(__srcMem))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__op == op_and_op)
+  {
+    asm("cp.reduce.async.bulk.tensor.1d.global.shared::cta.and.tile.bulk_group [%0, {%1}], [%2]; // 1a."
+        :
+        : "l"(__tensorMap), "r"(__tensorCoords[0]), "r"(__as_ptr_smem(__srcMem))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__op == op_or_op)
+  {
+    asm("cp.reduce.async.bulk.tensor.1d.global.shared::cta.or.tile.bulk_group [%0, {%1}], [%2]; // 1a."
+        :
+        : "l"(__tensorMap), "r"(__tensorCoords[0]), "r"(__as_ptr_smem(__srcMem))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__op == op_xor_op)
+  {
+    asm("cp.reduce.async.bulk.tensor.1d.global.shared::cta.xor.tile.bulk_group [%0, {%1}], [%2]; // 1a."
+        :
+        : "l"(__tensorMap), "r"(__tensorCoords[0]), "r"(__as_ptr_smem(__srcMem))
+        : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_cp_reduce_async_bulk_tensor_is_not_supported_before_SM_90__();
+#  endif
 }
 #endif // __cccl_ptx_isa >= 800
 
@@ -115,53 +129,67 @@ _CCCL_DEVICE static inline void cp_reduce_async_bulk_tensor(
   static_assert(__op == op_add || __op == op_min || __op == op_max || __op == op_inc || __op == op_dec
                   || __op == op_and_op || __op == op_or_op || __op == op_xor_op,
                 "");
-  NV_IF_ELSE_TARGET(
-    NV_PROVIDES_SM_90,
-    (
-      _CCCL_IF_CONSTEXPR (__op == op_add) {
-        asm("cp.reduce.async.bulk.tensor.2d.global.shared::cta.add.tile.bulk_group [%0, {%1, %2}], [%3]; // 1b."
-            :
-            : "l"(__tensorMap), "r"(__tensorCoords[0]), "r"(__tensorCoords[1]), "r"(__as_ptr_smem(__srcMem))
-            : "memory");
-      } else _CCCL_IF_CONSTEXPR (__op == op_min) {
-        asm("cp.reduce.async.bulk.tensor.2d.global.shared::cta.min.tile.bulk_group [%0, {%1, %2}], [%3]; // 1b."
-            :
-            : "l"(__tensorMap), "r"(__tensorCoords[0]), "r"(__tensorCoords[1]), "r"(__as_ptr_smem(__srcMem))
-            : "memory");
-      } else _CCCL_IF_CONSTEXPR (__op == op_max) {
-        asm("cp.reduce.async.bulk.tensor.2d.global.shared::cta.max.tile.bulk_group [%0, {%1, %2}], [%3]; // 1b."
-            :
-            : "l"(__tensorMap), "r"(__tensorCoords[0]), "r"(__tensorCoords[1]), "r"(__as_ptr_smem(__srcMem))
-            : "memory");
-      } else _CCCL_IF_CONSTEXPR (__op == op_inc) {
-        asm("cp.reduce.async.bulk.tensor.2d.global.shared::cta.inc.tile.bulk_group [%0, {%1, %2}], [%3]; // 1b."
-            :
-            : "l"(__tensorMap), "r"(__tensorCoords[0]), "r"(__tensorCoords[1]), "r"(__as_ptr_smem(__srcMem))
-            : "memory");
-      } else _CCCL_IF_CONSTEXPR (__op == op_dec) {
-        asm("cp.reduce.async.bulk.tensor.2d.global.shared::cta.dec.tile.bulk_group [%0, {%1, %2}], [%3]; // 1b."
-            :
-            : "l"(__tensorMap), "r"(__tensorCoords[0]), "r"(__tensorCoords[1]), "r"(__as_ptr_smem(__srcMem))
-            : "memory");
-      } else _CCCL_IF_CONSTEXPR (__op == op_and_op) {
-        asm("cp.reduce.async.bulk.tensor.2d.global.shared::cta.and.tile.bulk_group [%0, {%1, %2}], [%3]; // 1b."
-            :
-            : "l"(__tensorMap), "r"(__tensorCoords[0]), "r"(__tensorCoords[1]), "r"(__as_ptr_smem(__srcMem))
-            : "memory");
-      } else _CCCL_IF_CONSTEXPR (__op == op_or_op) {
-        asm("cp.reduce.async.bulk.tensor.2d.global.shared::cta.or.tile.bulk_group [%0, {%1, %2}], [%3]; // 1b."
-            :
-            : "l"(__tensorMap), "r"(__tensorCoords[0]), "r"(__tensorCoords[1]), "r"(__as_ptr_smem(__srcMem))
-            : "memory");
-      } else _CCCL_IF_CONSTEXPR (__op == op_xor_op) {
-        asm("cp.reduce.async.bulk.tensor.2d.global.shared::cta.xor.tile.bulk_group [%0, {%1, %2}], [%3]; // 1b."
-            :
-            : "l"(__tensorMap), "r"(__tensorCoords[0]), "r"(__tensorCoords[1]), "r"(__as_ptr_smem(__srcMem))
-            : "memory");
-      }),
-    (
-      // Unsupported architectures will have a linker error with a semi-decent error message
-      __cuda_ptx_cp_reduce_async_bulk_tensor_is_not_supported_before_SM_90__();));
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  _CCCL_IF_CONSTEXPR (__op == op_add)
+  {
+    asm("cp.reduce.async.bulk.tensor.2d.global.shared::cta.add.tile.bulk_group [%0, {%1, %2}], [%3]; // 1b."
+        :
+        : "l"(__tensorMap), "r"(__tensorCoords[0]), "r"(__tensorCoords[1]), "r"(__as_ptr_smem(__srcMem))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__op == op_min)
+  {
+    asm("cp.reduce.async.bulk.tensor.2d.global.shared::cta.min.tile.bulk_group [%0, {%1, %2}], [%3]; // 1b."
+        :
+        : "l"(__tensorMap), "r"(__tensorCoords[0]), "r"(__tensorCoords[1]), "r"(__as_ptr_smem(__srcMem))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__op == op_max)
+  {
+    asm("cp.reduce.async.bulk.tensor.2d.global.shared::cta.max.tile.bulk_group [%0, {%1, %2}], [%3]; // 1b."
+        :
+        : "l"(__tensorMap), "r"(__tensorCoords[0]), "r"(__tensorCoords[1]), "r"(__as_ptr_smem(__srcMem))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__op == op_inc)
+  {
+    asm("cp.reduce.async.bulk.tensor.2d.global.shared::cta.inc.tile.bulk_group [%0, {%1, %2}], [%3]; // 1b."
+        :
+        : "l"(__tensorMap), "r"(__tensorCoords[0]), "r"(__tensorCoords[1]), "r"(__as_ptr_smem(__srcMem))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__op == op_dec)
+  {
+    asm("cp.reduce.async.bulk.tensor.2d.global.shared::cta.dec.tile.bulk_group [%0, {%1, %2}], [%3]; // 1b."
+        :
+        : "l"(__tensorMap), "r"(__tensorCoords[0]), "r"(__tensorCoords[1]), "r"(__as_ptr_smem(__srcMem))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__op == op_and_op)
+  {
+    asm("cp.reduce.async.bulk.tensor.2d.global.shared::cta.and.tile.bulk_group [%0, {%1, %2}], [%3]; // 1b."
+        :
+        : "l"(__tensorMap), "r"(__tensorCoords[0]), "r"(__tensorCoords[1]), "r"(__as_ptr_smem(__srcMem))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__op == op_or_op)
+  {
+    asm("cp.reduce.async.bulk.tensor.2d.global.shared::cta.or.tile.bulk_group [%0, {%1, %2}], [%3]; // 1b."
+        :
+        : "l"(__tensorMap), "r"(__tensorCoords[0]), "r"(__tensorCoords[1]), "r"(__as_ptr_smem(__srcMem))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__op == op_xor_op)
+  {
+    asm("cp.reduce.async.bulk.tensor.2d.global.shared::cta.xor.tile.bulk_group [%0, {%1, %2}], [%3]; // 1b."
+        :
+        : "l"(__tensorMap), "r"(__tensorCoords[0]), "r"(__tensorCoords[1]), "r"(__as_ptr_smem(__srcMem))
+        : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_cp_reduce_async_bulk_tensor_is_not_supported_before_SM_90__();
+#  endif
 }
 #endif // __cccl_ptx_isa >= 800
 
@@ -196,85 +224,99 @@ _CCCL_DEVICE static inline void cp_reduce_async_bulk_tensor(
   static_assert(__op == op_add || __op == op_min || __op == op_max || __op == op_inc || __op == op_dec
                   || __op == op_and_op || __op == op_or_op || __op == op_xor_op,
                 "");
-  NV_IF_ELSE_TARGET(
-    NV_PROVIDES_SM_90,
-    (
-      _CCCL_IF_CONSTEXPR (__op == op_add) {
-        asm("cp.reduce.async.bulk.tensor.3d.global.shared::cta.add.tile.bulk_group [%0, {%1, %2, %3}], [%4]; // 1c."
-            :
-            : "l"(__tensorMap),
-              "r"(__tensorCoords[0]),
-              "r"(__tensorCoords[1]),
-              "r"(__tensorCoords[2]),
-              "r"(__as_ptr_smem(__srcMem))
-            : "memory");
-      } else _CCCL_IF_CONSTEXPR (__op == op_min) {
-        asm("cp.reduce.async.bulk.tensor.3d.global.shared::cta.min.tile.bulk_group [%0, {%1, %2, %3}], [%4]; // 1c."
-            :
-            : "l"(__tensorMap),
-              "r"(__tensorCoords[0]),
-              "r"(__tensorCoords[1]),
-              "r"(__tensorCoords[2]),
-              "r"(__as_ptr_smem(__srcMem))
-            : "memory");
-      } else _CCCL_IF_CONSTEXPR (__op == op_max) {
-        asm("cp.reduce.async.bulk.tensor.3d.global.shared::cta.max.tile.bulk_group [%0, {%1, %2, %3}], [%4]; // 1c."
-            :
-            : "l"(__tensorMap),
-              "r"(__tensorCoords[0]),
-              "r"(__tensorCoords[1]),
-              "r"(__tensorCoords[2]),
-              "r"(__as_ptr_smem(__srcMem))
-            : "memory");
-      } else _CCCL_IF_CONSTEXPR (__op == op_inc) {
-        asm("cp.reduce.async.bulk.tensor.3d.global.shared::cta.inc.tile.bulk_group [%0, {%1, %2, %3}], [%4]; // 1c."
-            :
-            : "l"(__tensorMap),
-              "r"(__tensorCoords[0]),
-              "r"(__tensorCoords[1]),
-              "r"(__tensorCoords[2]),
-              "r"(__as_ptr_smem(__srcMem))
-            : "memory");
-      } else _CCCL_IF_CONSTEXPR (__op == op_dec) {
-        asm("cp.reduce.async.bulk.tensor.3d.global.shared::cta.dec.tile.bulk_group [%0, {%1, %2, %3}], [%4]; // 1c."
-            :
-            : "l"(__tensorMap),
-              "r"(__tensorCoords[0]),
-              "r"(__tensorCoords[1]),
-              "r"(__tensorCoords[2]),
-              "r"(__as_ptr_smem(__srcMem))
-            : "memory");
-      } else _CCCL_IF_CONSTEXPR (__op == op_and_op) {
-        asm("cp.reduce.async.bulk.tensor.3d.global.shared::cta.and.tile.bulk_group [%0, {%1, %2, %3}], [%4]; // 1c."
-            :
-            : "l"(__tensorMap),
-              "r"(__tensorCoords[0]),
-              "r"(__tensorCoords[1]),
-              "r"(__tensorCoords[2]),
-              "r"(__as_ptr_smem(__srcMem))
-            : "memory");
-      } else _CCCL_IF_CONSTEXPR (__op == op_or_op) {
-        asm("cp.reduce.async.bulk.tensor.3d.global.shared::cta.or.tile.bulk_group [%0, {%1, %2, %3}], [%4]; // 1c."
-            :
-            : "l"(__tensorMap),
-              "r"(__tensorCoords[0]),
-              "r"(__tensorCoords[1]),
-              "r"(__tensorCoords[2]),
-              "r"(__as_ptr_smem(__srcMem))
-            : "memory");
-      } else _CCCL_IF_CONSTEXPR (__op == op_xor_op) {
-        asm("cp.reduce.async.bulk.tensor.3d.global.shared::cta.xor.tile.bulk_group [%0, {%1, %2, %3}], [%4]; // 1c."
-            :
-            : "l"(__tensorMap),
-              "r"(__tensorCoords[0]),
-              "r"(__tensorCoords[1]),
-              "r"(__tensorCoords[2]),
-              "r"(__as_ptr_smem(__srcMem))
-            : "memory");
-      }),
-    (
-      // Unsupported architectures will have a linker error with a semi-decent error message
-      __cuda_ptx_cp_reduce_async_bulk_tensor_is_not_supported_before_SM_90__();));
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  _CCCL_IF_CONSTEXPR (__op == op_add)
+  {
+    asm("cp.reduce.async.bulk.tensor.3d.global.shared::cta.add.tile.bulk_group [%0, {%1, %2, %3}], [%4]; // 1c."
+        :
+        : "l"(__tensorMap),
+          "r"(__tensorCoords[0]),
+          "r"(__tensorCoords[1]),
+          "r"(__tensorCoords[2]),
+          "r"(__as_ptr_smem(__srcMem))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__op == op_min)
+  {
+    asm("cp.reduce.async.bulk.tensor.3d.global.shared::cta.min.tile.bulk_group [%0, {%1, %2, %3}], [%4]; // 1c."
+        :
+        : "l"(__tensorMap),
+          "r"(__tensorCoords[0]),
+          "r"(__tensorCoords[1]),
+          "r"(__tensorCoords[2]),
+          "r"(__as_ptr_smem(__srcMem))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__op == op_max)
+  {
+    asm("cp.reduce.async.bulk.tensor.3d.global.shared::cta.max.tile.bulk_group [%0, {%1, %2, %3}], [%4]; // 1c."
+        :
+        : "l"(__tensorMap),
+          "r"(__tensorCoords[0]),
+          "r"(__tensorCoords[1]),
+          "r"(__tensorCoords[2]),
+          "r"(__as_ptr_smem(__srcMem))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__op == op_inc)
+  {
+    asm("cp.reduce.async.bulk.tensor.3d.global.shared::cta.inc.tile.bulk_group [%0, {%1, %2, %3}], [%4]; // 1c."
+        :
+        : "l"(__tensorMap),
+          "r"(__tensorCoords[0]),
+          "r"(__tensorCoords[1]),
+          "r"(__tensorCoords[2]),
+          "r"(__as_ptr_smem(__srcMem))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__op == op_dec)
+  {
+    asm("cp.reduce.async.bulk.tensor.3d.global.shared::cta.dec.tile.bulk_group [%0, {%1, %2, %3}], [%4]; // 1c."
+        :
+        : "l"(__tensorMap),
+          "r"(__tensorCoords[0]),
+          "r"(__tensorCoords[1]),
+          "r"(__tensorCoords[2]),
+          "r"(__as_ptr_smem(__srcMem))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__op == op_and_op)
+  {
+    asm("cp.reduce.async.bulk.tensor.3d.global.shared::cta.and.tile.bulk_group [%0, {%1, %2, %3}], [%4]; // 1c."
+        :
+        : "l"(__tensorMap),
+          "r"(__tensorCoords[0]),
+          "r"(__tensorCoords[1]),
+          "r"(__tensorCoords[2]),
+          "r"(__as_ptr_smem(__srcMem))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__op == op_or_op)
+  {
+    asm("cp.reduce.async.bulk.tensor.3d.global.shared::cta.or.tile.bulk_group [%0, {%1, %2, %3}], [%4]; // 1c."
+        :
+        : "l"(__tensorMap),
+          "r"(__tensorCoords[0]),
+          "r"(__tensorCoords[1]),
+          "r"(__tensorCoords[2]),
+          "r"(__as_ptr_smem(__srcMem))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__op == op_xor_op)
+  {
+    asm("cp.reduce.async.bulk.tensor.3d.global.shared::cta.xor.tile.bulk_group [%0, {%1, %2, %3}], [%4]; // 1c."
+        :
+        : "l"(__tensorMap),
+          "r"(__tensorCoords[0]),
+          "r"(__tensorCoords[1]),
+          "r"(__tensorCoords[2]),
+          "r"(__as_ptr_smem(__srcMem))
+        : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_cp_reduce_async_bulk_tensor_is_not_supported_before_SM_90__();
+#  endif
 }
 #endif // __cccl_ptx_isa >= 800
 
@@ -309,93 +351,107 @@ _CCCL_DEVICE static inline void cp_reduce_async_bulk_tensor(
   static_assert(__op == op_add || __op == op_min || __op == op_max || __op == op_inc || __op == op_dec
                   || __op == op_and_op || __op == op_or_op || __op == op_xor_op,
                 "");
-  NV_IF_ELSE_TARGET(
-    NV_PROVIDES_SM_90,
-    (
-      _CCCL_IF_CONSTEXPR (__op == op_add) {
-        asm("cp.reduce.async.bulk.tensor.4d.global.shared::cta.add.tile.bulk_group [%0, {%1, %2, %3, %4}], [%5]; // 1d."
-            :
-            : "l"(__tensorMap),
-              "r"(__tensorCoords[0]),
-              "r"(__tensorCoords[1]),
-              "r"(__tensorCoords[2]),
-              "r"(__tensorCoords[3]),
-              "r"(__as_ptr_smem(__srcMem))
-            : "memory");
-      } else _CCCL_IF_CONSTEXPR (__op == op_min) {
-        asm("cp.reduce.async.bulk.tensor.4d.global.shared::cta.min.tile.bulk_group [%0, {%1, %2, %3, %4}], [%5]; // 1d."
-            :
-            : "l"(__tensorMap),
-              "r"(__tensorCoords[0]),
-              "r"(__tensorCoords[1]),
-              "r"(__tensorCoords[2]),
-              "r"(__tensorCoords[3]),
-              "r"(__as_ptr_smem(__srcMem))
-            : "memory");
-      } else _CCCL_IF_CONSTEXPR (__op == op_max) {
-        asm("cp.reduce.async.bulk.tensor.4d.global.shared::cta.max.tile.bulk_group [%0, {%1, %2, %3, %4}], [%5]; // 1d."
-            :
-            : "l"(__tensorMap),
-              "r"(__tensorCoords[0]),
-              "r"(__tensorCoords[1]),
-              "r"(__tensorCoords[2]),
-              "r"(__tensorCoords[3]),
-              "r"(__as_ptr_smem(__srcMem))
-            : "memory");
-      } else _CCCL_IF_CONSTEXPR (__op == op_inc) {
-        asm("cp.reduce.async.bulk.tensor.4d.global.shared::cta.inc.tile.bulk_group [%0, {%1, %2, %3, %4}], [%5]; // 1d."
-            :
-            : "l"(__tensorMap),
-              "r"(__tensorCoords[0]),
-              "r"(__tensorCoords[1]),
-              "r"(__tensorCoords[2]),
-              "r"(__tensorCoords[3]),
-              "r"(__as_ptr_smem(__srcMem))
-            : "memory");
-      } else _CCCL_IF_CONSTEXPR (__op == op_dec) {
-        asm("cp.reduce.async.bulk.tensor.4d.global.shared::cta.dec.tile.bulk_group [%0, {%1, %2, %3, %4}], [%5]; // 1d."
-            :
-            : "l"(__tensorMap),
-              "r"(__tensorCoords[0]),
-              "r"(__tensorCoords[1]),
-              "r"(__tensorCoords[2]),
-              "r"(__tensorCoords[3]),
-              "r"(__as_ptr_smem(__srcMem))
-            : "memory");
-      } else _CCCL_IF_CONSTEXPR (__op == op_and_op) {
-        asm("cp.reduce.async.bulk.tensor.4d.global.shared::cta.and.tile.bulk_group [%0, {%1, %2, %3, %4}], [%5]; // 1d."
-            :
-            : "l"(__tensorMap),
-              "r"(__tensorCoords[0]),
-              "r"(__tensorCoords[1]),
-              "r"(__tensorCoords[2]),
-              "r"(__tensorCoords[3]),
-              "r"(__as_ptr_smem(__srcMem))
-            : "memory");
-      } else _CCCL_IF_CONSTEXPR (__op == op_or_op) {
-        asm("cp.reduce.async.bulk.tensor.4d.global.shared::cta.or.tile.bulk_group [%0, {%1, %2, %3, %4}], [%5]; // 1d."
-            :
-            : "l"(__tensorMap),
-              "r"(__tensorCoords[0]),
-              "r"(__tensorCoords[1]),
-              "r"(__tensorCoords[2]),
-              "r"(__tensorCoords[3]),
-              "r"(__as_ptr_smem(__srcMem))
-            : "memory");
-      } else _CCCL_IF_CONSTEXPR (__op == op_xor_op) {
-        asm("cp.reduce.async.bulk.tensor.4d.global.shared::cta.xor.tile.bulk_group [%0, {%1, %2, %3, %4}], [%5]; // 1d."
-            :
-            : "l"(__tensorMap),
-              "r"(__tensorCoords[0]),
-              "r"(__tensorCoords[1]),
-              "r"(__tensorCoords[2]),
-              "r"(__tensorCoords[3]),
-              "r"(__as_ptr_smem(__srcMem))
-            : "memory");
-      }),
-    (
-      // Unsupported architectures will have a linker error with a semi-decent error message
-      __cuda_ptx_cp_reduce_async_bulk_tensor_is_not_supported_before_SM_90__();));
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  _CCCL_IF_CONSTEXPR (__op == op_add)
+  {
+    asm("cp.reduce.async.bulk.tensor.4d.global.shared::cta.add.tile.bulk_group [%0, {%1, %2, %3, %4}], [%5]; // 1d."
+        :
+        : "l"(__tensorMap),
+          "r"(__tensorCoords[0]),
+          "r"(__tensorCoords[1]),
+          "r"(__tensorCoords[2]),
+          "r"(__tensorCoords[3]),
+          "r"(__as_ptr_smem(__srcMem))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__op == op_min)
+  {
+    asm("cp.reduce.async.bulk.tensor.4d.global.shared::cta.min.tile.bulk_group [%0, {%1, %2, %3, %4}], [%5]; // 1d."
+        :
+        : "l"(__tensorMap),
+          "r"(__tensorCoords[0]),
+          "r"(__tensorCoords[1]),
+          "r"(__tensorCoords[2]),
+          "r"(__tensorCoords[3]),
+          "r"(__as_ptr_smem(__srcMem))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__op == op_max)
+  {
+    asm("cp.reduce.async.bulk.tensor.4d.global.shared::cta.max.tile.bulk_group [%0, {%1, %2, %3, %4}], [%5]; // 1d."
+        :
+        : "l"(__tensorMap),
+          "r"(__tensorCoords[0]),
+          "r"(__tensorCoords[1]),
+          "r"(__tensorCoords[2]),
+          "r"(__tensorCoords[3]),
+          "r"(__as_ptr_smem(__srcMem))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__op == op_inc)
+  {
+    asm("cp.reduce.async.bulk.tensor.4d.global.shared::cta.inc.tile.bulk_group [%0, {%1, %2, %3, %4}], [%5]; // 1d."
+        :
+        : "l"(__tensorMap),
+          "r"(__tensorCoords[0]),
+          "r"(__tensorCoords[1]),
+          "r"(__tensorCoords[2]),
+          "r"(__tensorCoords[3]),
+          "r"(__as_ptr_smem(__srcMem))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__op == op_dec)
+  {
+    asm("cp.reduce.async.bulk.tensor.4d.global.shared::cta.dec.tile.bulk_group [%0, {%1, %2, %3, %4}], [%5]; // 1d."
+        :
+        : "l"(__tensorMap),
+          "r"(__tensorCoords[0]),
+          "r"(__tensorCoords[1]),
+          "r"(__tensorCoords[2]),
+          "r"(__tensorCoords[3]),
+          "r"(__as_ptr_smem(__srcMem))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__op == op_and_op)
+  {
+    asm("cp.reduce.async.bulk.tensor.4d.global.shared::cta.and.tile.bulk_group [%0, {%1, %2, %3, %4}], [%5]; // 1d."
+        :
+        : "l"(__tensorMap),
+          "r"(__tensorCoords[0]),
+          "r"(__tensorCoords[1]),
+          "r"(__tensorCoords[2]),
+          "r"(__tensorCoords[3]),
+          "r"(__as_ptr_smem(__srcMem))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__op == op_or_op)
+  {
+    asm("cp.reduce.async.bulk.tensor.4d.global.shared::cta.or.tile.bulk_group [%0, {%1, %2, %3, %4}], [%5]; // 1d."
+        :
+        : "l"(__tensorMap),
+          "r"(__tensorCoords[0]),
+          "r"(__tensorCoords[1]),
+          "r"(__tensorCoords[2]),
+          "r"(__tensorCoords[3]),
+          "r"(__as_ptr_smem(__srcMem))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__op == op_xor_op)
+  {
+    asm("cp.reduce.async.bulk.tensor.4d.global.shared::cta.xor.tile.bulk_group [%0, {%1, %2, %3, %4}], [%5]; // 1d."
+        :
+        : "l"(__tensorMap),
+          "r"(__tensorCoords[0]),
+          "r"(__tensorCoords[1]),
+          "r"(__tensorCoords[2]),
+          "r"(__tensorCoords[3]),
+          "r"(__as_ptr_smem(__srcMem))
+        : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_cp_reduce_async_bulk_tensor_is_not_supported_before_SM_90__();
+#  endif
 }
 #endif // __cccl_ptx_isa >= 800
 
@@ -430,109 +486,115 @@ _CCCL_DEVICE static inline void cp_reduce_async_bulk_tensor(
   static_assert(__op == op_add || __op == op_min || __op == op_max || __op == op_inc || __op == op_dec
                   || __op == op_and_op || __op == op_or_op || __op == op_xor_op,
                 "");
-  NV_IF_ELSE_TARGET(
-    NV_PROVIDES_SM_90,
-    (
-      _CCCL_IF_CONSTEXPR (__op == op_add) {
-        asm("cp.reduce.async.bulk.tensor.5d.global.shared::cta.add.tile.bulk_group [%0, {%1, %2, %3, %4, %5}], [%6]; "
-            "// 1e."
-            :
-            : "l"(__tensorMap),
-              "r"(__tensorCoords[0]),
-              "r"(__tensorCoords[1]),
-              "r"(__tensorCoords[2]),
-              "r"(__tensorCoords[3]),
-              "r"(__tensorCoords[4]),
-              "r"(__as_ptr_smem(__srcMem))
-            : "memory");
-      } else _CCCL_IF_CONSTEXPR (__op == op_min) {
-        asm("cp.reduce.async.bulk.tensor.5d.global.shared::cta.min.tile.bulk_group [%0, {%1, %2, %3, %4, %5}], [%6]; "
-            "// 1e."
-            :
-            : "l"(__tensorMap),
-              "r"(__tensorCoords[0]),
-              "r"(__tensorCoords[1]),
-              "r"(__tensorCoords[2]),
-              "r"(__tensorCoords[3]),
-              "r"(__tensorCoords[4]),
-              "r"(__as_ptr_smem(__srcMem))
-            : "memory");
-      } else _CCCL_IF_CONSTEXPR (__op == op_max) {
-        asm("cp.reduce.async.bulk.tensor.5d.global.shared::cta.max.tile.bulk_group [%0, {%1, %2, %3, %4, %5}], [%6]; "
-            "// 1e."
-            :
-            : "l"(__tensorMap),
-              "r"(__tensorCoords[0]),
-              "r"(__tensorCoords[1]),
-              "r"(__tensorCoords[2]),
-              "r"(__tensorCoords[3]),
-              "r"(__tensorCoords[4]),
-              "r"(__as_ptr_smem(__srcMem))
-            : "memory");
-      } else _CCCL_IF_CONSTEXPR (__op == op_inc) {
-        asm("cp.reduce.async.bulk.tensor.5d.global.shared::cta.inc.tile.bulk_group [%0, {%1, %2, %3, %4, %5}], [%6]; "
-            "// 1e."
-            :
-            : "l"(__tensorMap),
-              "r"(__tensorCoords[0]),
-              "r"(__tensorCoords[1]),
-              "r"(__tensorCoords[2]),
-              "r"(__tensorCoords[3]),
-              "r"(__tensorCoords[4]),
-              "r"(__as_ptr_smem(__srcMem))
-            : "memory");
-      } else _CCCL_IF_CONSTEXPR (__op == op_dec) {
-        asm("cp.reduce.async.bulk.tensor.5d.global.shared::cta.dec.tile.bulk_group [%0, {%1, %2, %3, %4, %5}], [%6]; "
-            "// 1e."
-            :
-            : "l"(__tensorMap),
-              "r"(__tensorCoords[0]),
-              "r"(__tensorCoords[1]),
-              "r"(__tensorCoords[2]),
-              "r"(__tensorCoords[3]),
-              "r"(__tensorCoords[4]),
-              "r"(__as_ptr_smem(__srcMem))
-            : "memory");
-      } else _CCCL_IF_CONSTEXPR (__op == op_and_op) {
-        asm("cp.reduce.async.bulk.tensor.5d.global.shared::cta.and.tile.bulk_group [%0, {%1, %2, %3, %4, %5}], [%6]; "
-            "// 1e."
-            :
-            : "l"(__tensorMap),
-              "r"(__tensorCoords[0]),
-              "r"(__tensorCoords[1]),
-              "r"(__tensorCoords[2]),
-              "r"(__tensorCoords[3]),
-              "r"(__tensorCoords[4]),
-              "r"(__as_ptr_smem(__srcMem))
-            : "memory");
-      } else _CCCL_IF_CONSTEXPR (__op == op_or_op) {
-        asm("cp.reduce.async.bulk.tensor.5d.global.shared::cta.or.tile.bulk_group [%0, {%1, %2, %3, %4, %5}], [%6]; // "
-            "1e."
-            :
-            : "l"(__tensorMap),
-              "r"(__tensorCoords[0]),
-              "r"(__tensorCoords[1]),
-              "r"(__tensorCoords[2]),
-              "r"(__tensorCoords[3]),
-              "r"(__tensorCoords[4]),
-              "r"(__as_ptr_smem(__srcMem))
-            : "memory");
-      } else _CCCL_IF_CONSTEXPR (__op == op_xor_op) {
-        asm("cp.reduce.async.bulk.tensor.5d.global.shared::cta.xor.tile.bulk_group [%0, {%1, %2, %3, %4, %5}], [%6]; "
-            "// 1e."
-            :
-            : "l"(__tensorMap),
-              "r"(__tensorCoords[0]),
-              "r"(__tensorCoords[1]),
-              "r"(__tensorCoords[2]),
-              "r"(__tensorCoords[3]),
-              "r"(__tensorCoords[4]),
-              "r"(__as_ptr_smem(__srcMem))
-            : "memory");
-      }),
-    (
-      // Unsupported architectures will have a linker error with a semi-decent error message
-      __cuda_ptx_cp_reduce_async_bulk_tensor_is_not_supported_before_SM_90__();));
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  _CCCL_IF_CONSTEXPR (__op == op_add)
+  {
+    asm("cp.reduce.async.bulk.tensor.5d.global.shared::cta.add.tile.bulk_group [%0, {%1, %2, %3, %4, %5}], [%6]; // 1e."
+        :
+        : "l"(__tensorMap),
+          "r"(__tensorCoords[0]),
+          "r"(__tensorCoords[1]),
+          "r"(__tensorCoords[2]),
+          "r"(__tensorCoords[3]),
+          "r"(__tensorCoords[4]),
+          "r"(__as_ptr_smem(__srcMem))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__op == op_min)
+  {
+    asm("cp.reduce.async.bulk.tensor.5d.global.shared::cta.min.tile.bulk_group [%0, {%1, %2, %3, %4, %5}], [%6]; // 1e."
+        :
+        : "l"(__tensorMap),
+          "r"(__tensorCoords[0]),
+          "r"(__tensorCoords[1]),
+          "r"(__tensorCoords[2]),
+          "r"(__tensorCoords[3]),
+          "r"(__tensorCoords[4]),
+          "r"(__as_ptr_smem(__srcMem))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__op == op_max)
+  {
+    asm("cp.reduce.async.bulk.tensor.5d.global.shared::cta.max.tile.bulk_group [%0, {%1, %2, %3, %4, %5}], [%6]; // 1e."
+        :
+        : "l"(__tensorMap),
+          "r"(__tensorCoords[0]),
+          "r"(__tensorCoords[1]),
+          "r"(__tensorCoords[2]),
+          "r"(__tensorCoords[3]),
+          "r"(__tensorCoords[4]),
+          "r"(__as_ptr_smem(__srcMem))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__op == op_inc)
+  {
+    asm("cp.reduce.async.bulk.tensor.5d.global.shared::cta.inc.tile.bulk_group [%0, {%1, %2, %3, %4, %5}], [%6]; // 1e."
+        :
+        : "l"(__tensorMap),
+          "r"(__tensorCoords[0]),
+          "r"(__tensorCoords[1]),
+          "r"(__tensorCoords[2]),
+          "r"(__tensorCoords[3]),
+          "r"(__tensorCoords[4]),
+          "r"(__as_ptr_smem(__srcMem))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__op == op_dec)
+  {
+    asm("cp.reduce.async.bulk.tensor.5d.global.shared::cta.dec.tile.bulk_group [%0, {%1, %2, %3, %4, %5}], [%6]; // 1e."
+        :
+        : "l"(__tensorMap),
+          "r"(__tensorCoords[0]),
+          "r"(__tensorCoords[1]),
+          "r"(__tensorCoords[2]),
+          "r"(__tensorCoords[3]),
+          "r"(__tensorCoords[4]),
+          "r"(__as_ptr_smem(__srcMem))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__op == op_and_op)
+  {
+    asm("cp.reduce.async.bulk.tensor.5d.global.shared::cta.and.tile.bulk_group [%0, {%1, %2, %3, %4, %5}], [%6]; // 1e."
+        :
+        : "l"(__tensorMap),
+          "r"(__tensorCoords[0]),
+          "r"(__tensorCoords[1]),
+          "r"(__tensorCoords[2]),
+          "r"(__tensorCoords[3]),
+          "r"(__tensorCoords[4]),
+          "r"(__as_ptr_smem(__srcMem))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__op == op_or_op)
+  {
+    asm("cp.reduce.async.bulk.tensor.5d.global.shared::cta.or.tile.bulk_group [%0, {%1, %2, %3, %4, %5}], [%6]; // 1e."
+        :
+        : "l"(__tensorMap),
+          "r"(__tensorCoords[0]),
+          "r"(__tensorCoords[1]),
+          "r"(__tensorCoords[2]),
+          "r"(__tensorCoords[3]),
+          "r"(__tensorCoords[4]),
+          "r"(__as_ptr_smem(__srcMem))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__op == op_xor_op)
+  {
+    asm("cp.reduce.async.bulk.tensor.5d.global.shared::cta.xor.tile.bulk_group [%0, {%1, %2, %3, %4, %5}], [%6]; // 1e."
+        :
+        : "l"(__tensorMap),
+          "r"(__tensorCoords[0]),
+          "r"(__tensorCoords[1]),
+          "r"(__tensorCoords[2]),
+          "r"(__tensorCoords[3]),
+          "r"(__tensorCoords[4]),
+          "r"(__as_ptr_smem(__srcMem))
+        : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_cp_reduce_async_bulk_tensor_is_not_supported_before_SM_90__();
+#  endif
 }
 #endif // __cccl_ptx_isa >= 800
 
diff --git a/libcudacxx/include/cuda/__ptx/instructions/generated/elect_sync.h b/libcudacxx/include/cuda/__ptx/instructions/generated/elect_sync.h
new file mode 100644
index 00000000000..e8691178f14
--- /dev/null
+++ b/libcudacxx/include/cuda/__ptx/instructions/generated/elect_sync.h
@@ -0,0 +1,36 @@
+// This file was automatically generated. Do not edit.
+
+#ifndef _CUDA_PTX_GENERATED_ELECT_SYNC_H_
+#define _CUDA_PTX_GENERATED_ELECT_SYNC_H_
+
+/*
+// elect.sync _|is_elected, membermask; // PTX ISA 80, SM_90
+template <typename = void>
+__device__ static inline bool elect_sync(
+  const uint32_t& membermask);
+*/
+#if __cccl_ptx_isa >= 800
+extern "C" _CCCL_DEVICE void __cuda_ptx_elect_sync_is_not_supported_before_SM_90__();
+template <typename = void>
+_CCCL_DEVICE static inline bool elect_sync(const _CUDA_VSTD::uint32_t& __membermask)
+{
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  _CUDA_VSTD::uint32_t __is_elected;
+  asm volatile(
+    "{\n\t .reg .pred P_OUT; \n\t"
+    "elect.sync _|P_OUT, %1;\n\t"
+    "selp.b32 %0, 1, 0, P_OUT; \n"
+    "}"
+    : "=r"(__is_elected)
+    : "r"(__membermask)
+    :);
+  return static_cast<bool>(__is_elected);
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_elect_sync_is_not_supported_before_SM_90__();
+  return false;
+#  endif
+}
+#endif // __cccl_ptx_isa >= 800
+
+#endif // _CUDA_PTX_GENERATED_ELECT_SYNC_H_
diff --git a/libcudacxx/include/cuda/__ptx/instructions/generated/fence.h b/libcudacxx/include/cuda/__ptx/instructions/generated/fence.h
index db00c4d4cba..c0bd9e9a3d2 100644
--- a/libcudacxx/include/cuda/__ptx/instructions/generated/fence.h
+++ b/libcudacxx/include/cuda/__ptx/instructions/generated/fence.h
@@ -4,71 +4,205 @@
 #define _CUDA_PTX_GENERATED_FENCE_H_
 
 /*
-// fence{.sem}.scope; // 1. PTX ISA 60, SM_70
-// .sem       = { .sc, .acq_rel }
+// fence.sem.scope; // 1. PTX ISA 60, SM_70
+// .sem       = { .sc }
 // .scope     = { .cta, .gpu, .sys }
-template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+template <cuda::ptx::dot_scope Scope>
 __device__ static inline void fence(
-  cuda::ptx::sem_t<Sem> sem,
+  cuda::ptx::sem_sc_t,
   cuda::ptx::scope_t<Scope> scope);
 */
 #if __cccl_ptx_isa >= 600
 extern "C" _CCCL_DEVICE void __cuda_ptx_fence_is_not_supported_before_SM_70__();
-template <dot_sem _Sem, dot_scope _Scope>
-_CCCL_DEVICE static inline void fence(sem_t<_Sem> __sem, scope_t<_Scope> __scope)
+template <dot_scope _Scope>
+_CCCL_DEVICE static inline void fence(sem_sc_t, scope_t<_Scope> __scope)
 {
-  static_assert(__sem == sem_sc || __sem == sem_acq_rel, "");
+  // __sem == sem_sc (due to parameter type constraint)
   static_assert(__scope == scope_cta || __scope == scope_gpu || __scope == scope_sys, "");
-  NV_IF_ELSE_TARGET(
-    NV_PROVIDES_SM_70,
-    (
-      _CCCL_IF_CONSTEXPR (__sem == sem_sc && __scope == scope_cta) {
-        asm volatile("fence.sc.cta; // 1." : : : "memory");
-      } else _CCCL_IF_CONSTEXPR (__sem == sem_sc && __scope == scope_gpu) {
-        asm volatile("fence.sc.gpu; // 1." : : : "memory");
-      } else _CCCL_IF_CONSTEXPR (__sem == sem_sc && __scope == scope_sys) {
-        asm volatile("fence.sc.sys; // 1." : : : "memory");
-      } else _CCCL_IF_CONSTEXPR (__sem == sem_acq_rel && __scope == scope_cta) {
-        asm volatile("fence.acq_rel.cta; // 1." : : : "memory");
-      } else _CCCL_IF_CONSTEXPR (__sem == sem_acq_rel && __scope == scope_gpu) {
-        asm volatile("fence.acq_rel.gpu; // 1." : : : "memory");
-      } else _CCCL_IF_CONSTEXPR (__sem == sem_acq_rel && __scope == scope_sys) {
-        asm volatile("fence.acq_rel.sys; // 1." : : : "memory");
-      }),
-    (
-      // Unsupported architectures will have a linker error with a semi-decent error message
-      __cuda_ptx_fence_is_not_supported_before_SM_70__();));
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 700
+  _CCCL_IF_CONSTEXPR (__scope == scope_cta)
+  {
+    asm volatile("fence.sc.cta; // 1." : : : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__scope == scope_gpu)
+  {
+    asm volatile("fence.sc.gpu; // 1." : : : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__scope == scope_sys)
+  {
+    asm volatile("fence.sc.sys; // 1." : : : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_fence_is_not_supported_before_SM_70__();
+#  endif
 }
 #endif // __cccl_ptx_isa >= 600
 
 /*
-// fence{.sem}.scope; // 2. PTX ISA 78, SM_90
-// .sem       = { .sc, .acq_rel }
+// fence.sem.scope; // 2. PTX ISA 78, SM_90
+// .sem       = { .sc }
 // .scope     = { .cluster }
-template <cuda::ptx::dot_sem Sem>
+template <typename = void>
 __device__ static inline void fence(
-  cuda::ptx::sem_t<Sem> sem,
+  cuda::ptx::sem_sc_t,
   cuda::ptx::scope_cluster_t);
 */
 #if __cccl_ptx_isa >= 780
 extern "C" _CCCL_DEVICE void __cuda_ptx_fence_is_not_supported_before_SM_90__();
-template <dot_sem _Sem>
-_CCCL_DEVICE static inline void fence(sem_t<_Sem> __sem, scope_cluster_t)
+template <typename = void>
+_CCCL_DEVICE static inline void fence(sem_sc_t, scope_cluster_t)
 {
-  static_assert(__sem == sem_sc || __sem == sem_acq_rel, "");
-  // __scope == scope_cluster (due to parameter type constraint)
-  NV_IF_ELSE_TARGET(
-    NV_PROVIDES_SM_90,
-    (
-      _CCCL_IF_CONSTEXPR (__sem == sem_sc) {
-        asm volatile("fence.sc.cluster; // 2." : : : "memory");
-      } else _CCCL_IF_CONSTEXPR (__sem == sem_acq_rel) {
-        asm volatile("fence.acq_rel.cluster; // 2." : : : "memory");
-      }),
-    (
-      // Unsupported architectures will have a linker error with a semi-decent error message
-      __cuda_ptx_fence_is_not_supported_before_SM_90__();));
+// __sem == sem_sc (due to parameter type constraint)
+// __scope == scope_cluster (due to parameter type constraint)
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  asm volatile("fence.sc.cluster; // 2." : : : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_fence_is_not_supported_before_SM_90__();
+#  endif
 }
 #endif // __cccl_ptx_isa >= 780
 
+/*
+// fence.sem.scope; // 1. PTX ISA 60, SM_70
+// .sem       = { .acq_rel }
+// .scope     = { .cta, .gpu, .sys }
+template <cuda::ptx::dot_scope Scope>
+__device__ static inline void fence(
+  cuda::ptx::sem_acq_rel_t,
+  cuda::ptx::scope_t<Scope> scope);
+*/
+#if __cccl_ptx_isa >= 600
+extern "C" _CCCL_DEVICE void __cuda_ptx_fence_is_not_supported_before_SM_70__();
+template <dot_scope _Scope>
+_CCCL_DEVICE static inline void fence(sem_acq_rel_t, scope_t<_Scope> __scope)
+{
+  // __sem == sem_acq_rel (due to parameter type constraint)
+  static_assert(__scope == scope_cta || __scope == scope_gpu || __scope == scope_sys, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 700
+  _CCCL_IF_CONSTEXPR (__scope == scope_cta)
+  {
+    asm volatile("fence.acq_rel.cta; // 1." : : : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__scope == scope_gpu)
+  {
+    asm volatile("fence.acq_rel.gpu; // 1." : : : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__scope == scope_sys)
+  {
+    asm volatile("fence.acq_rel.sys; // 1." : : : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_fence_is_not_supported_before_SM_70__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 600
+
+/*
+// fence.sem.scope; // 2. PTX ISA 78, SM_90
+// .sem       = { .acq_rel }
+// .scope     = { .cluster }
+template <typename = void>
+__device__ static inline void fence(
+  cuda::ptx::sem_acq_rel_t,
+  cuda::ptx::scope_cluster_t);
+*/
+#if __cccl_ptx_isa >= 780
+extern "C" _CCCL_DEVICE void __cuda_ptx_fence_is_not_supported_before_SM_90__();
+template <typename = void>
+_CCCL_DEVICE static inline void fence(sem_acq_rel_t, scope_cluster_t)
+{
+// __sem == sem_acq_rel (due to parameter type constraint)
+// __scope == scope_cluster (due to parameter type constraint)
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  asm volatile("fence.acq_rel.cluster; // 2." : : : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_fence_is_not_supported_before_SM_90__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 780
+
+/*
+// fence.sem.scope; // PTX ISA 86, SM_90
+// .sem       = { .acquire }
+// .scope     = { .cta, .cluster, .gpu, .sys }
+template <cuda::ptx::dot_scope Scope>
+__device__ static inline void fence(
+  cuda::ptx::sem_acquire_t,
+  cuda::ptx::scope_t<Scope> scope);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_fence_is_not_supported_before_SM_90__();
+template <dot_scope _Scope>
+_CCCL_DEVICE static inline void fence(sem_acquire_t, scope_t<_Scope> __scope)
+{
+  // __sem == sem_acquire (due to parameter type constraint)
+  static_assert(__scope == scope_cta || __scope == scope_cluster || __scope == scope_gpu || __scope == scope_sys, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  _CCCL_IF_CONSTEXPR (__scope == scope_cta)
+  {
+    asm volatile("fence.acquire.cta;" : : : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__scope == scope_cluster)
+  {
+    asm volatile("fence.acquire.cluster;" : : : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__scope == scope_gpu)
+  {
+    asm volatile("fence.acquire.gpu;" : : : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__scope == scope_sys)
+  {
+    asm volatile("fence.acquire.sys;" : : : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_fence_is_not_supported_before_SM_90__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// fence.sem.scope; // PTX ISA 86, SM_90
+// .sem       = { .release }
+// .scope     = { .cta, .cluster, .gpu, .sys }
+template <cuda::ptx::dot_scope Scope>
+__device__ static inline void fence(
+  cuda::ptx::sem_release_t,
+  cuda::ptx::scope_t<Scope> scope);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_fence_is_not_supported_before_SM_90__();
+template <dot_scope _Scope>
+_CCCL_DEVICE static inline void fence(sem_release_t, scope_t<_Scope> __scope)
+{
+  // __sem == sem_release (due to parameter type constraint)
+  static_assert(__scope == scope_cta || __scope == scope_cluster || __scope == scope_gpu || __scope == scope_sys, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  _CCCL_IF_CONSTEXPR (__scope == scope_cta)
+  {
+    asm volatile("fence.release.cta;" : : : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__scope == scope_cluster)
+  {
+    asm volatile("fence.release.cluster;" : : : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__scope == scope_gpu)
+  {
+    asm volatile("fence.release.gpu;" : : : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__scope == scope_sys)
+  {
+    asm volatile("fence.release.sys;" : : : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_fence_is_not_supported_before_SM_90__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
 #endif // _CUDA_PTX_GENERATED_FENCE_H_
diff --git a/libcudacxx/include/cuda/__ptx/instructions/generated/fence_mbarrier_init.h b/libcudacxx/include/cuda/__ptx/instructions/generated/fence_mbarrier_init.h
index f8c4e6cf476..6b0c8ec161d 100644
--- a/libcudacxx/include/cuda/__ptx/instructions/generated/fence_mbarrier_init.h
+++ b/libcudacxx/include/cuda/__ptx/instructions/generated/fence_mbarrier_init.h
@@ -17,14 +17,14 @@ extern "C" _CCCL_DEVICE void __cuda_ptx_fence_mbarrier_init_is_not_supported_bef
 template <typename = void>
 _CCCL_DEVICE static inline void fence_mbarrier_init(sem_release_t, scope_cluster_t)
 {
-  // __sem == sem_release (due to parameter type constraint)
-  // __scope == scope_cluster (due to parameter type constraint)
-  NV_IF_ELSE_TARGET(
-    NV_PROVIDES_SM_90,
-    (asm volatile("fence.mbarrier_init.release.cluster; // 3." : : : "memory");),
-    (
-      // Unsupported architectures will have a linker error with a semi-decent error message
-      __cuda_ptx_fence_mbarrier_init_is_not_supported_before_SM_90__();));
+// __sem == sem_release (due to parameter type constraint)
+// __scope == scope_cluster (due to parameter type constraint)
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  asm volatile("fence.mbarrier_init.release.cluster; // 3." : : : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_fence_mbarrier_init_is_not_supported_before_SM_90__();
+#  endif
 }
 #endif // __cccl_ptx_isa >= 800
 
diff --git a/libcudacxx/include/cuda/__ptx/instructions/generated/fence_proxy_alias.h b/libcudacxx/include/cuda/__ptx/instructions/generated/fence_proxy_alias.h
index cc413a0f511..e520d99bfaa 100644
--- a/libcudacxx/include/cuda/__ptx/instructions/generated/fence_proxy_alias.h
+++ b/libcudacxx/include/cuda/__ptx/instructions/generated/fence_proxy_alias.h
@@ -13,12 +13,12 @@ extern "C" _CCCL_DEVICE void __cuda_ptx_fence_proxy_alias_is_not_supported_befor
 template <typename = void>
 _CCCL_DEVICE static inline void fence_proxy_alias()
 {
-  NV_IF_ELSE_TARGET(
-    NV_PROVIDES_SM_70,
-    (asm volatile("fence.proxy.alias; // 4." : : : "memory");),
-    (
-      // Unsupported architectures will have a linker error with a semi-decent error message
-      __cuda_ptx_fence_proxy_alias_is_not_supported_before_SM_70__();));
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 700
+  asm volatile("fence.proxy.alias; // 4." : : : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_fence_proxy_alias_is_not_supported_before_SM_70__();
+#  endif
 }
 #endif // __cccl_ptx_isa >= 750
 
diff --git a/libcudacxx/include/cuda/__ptx/instructions/generated/fence_proxy_async.h b/libcudacxx/include/cuda/__ptx/instructions/generated/fence_proxy_async.h
index 176d24ff73f..f8ee49909db 100644
--- a/libcudacxx/include/cuda/__ptx/instructions/generated/fence_proxy_async.h
+++ b/libcudacxx/include/cuda/__ptx/instructions/generated/fence_proxy_async.h
@@ -13,17 +13,17 @@ extern "C" _CCCL_DEVICE void __cuda_ptx_fence_proxy_async_is_not_supported_befor
 template <typename = void>
 _CCCL_DEVICE static inline void fence_proxy_async()
 {
-  NV_IF_ELSE_TARGET(
-    NV_PROVIDES_SM_90,
-    (asm volatile("fence.proxy.async; // 5." : : : "memory");),
-    (
-      // Unsupported architectures will have a linker error with a semi-decent error message
-      __cuda_ptx_fence_proxy_async_is_not_supported_before_SM_90__();));
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  asm volatile("fence.proxy.async; // 5." : : : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_fence_proxy_async_is_not_supported_before_SM_90__();
+#  endif
 }
 #endif // __cccl_ptx_isa >= 800
 
 /*
-// fence.proxy.async{.space}; // 6. PTX ISA 80, SM_90
+// fence.proxy.async.space; // 6. PTX ISA 80, SM_90
 // .space     = { .global, .shared::cluster, .shared::cta }
 template <cuda::ptx::dot_space Space>
 __device__ static inline void fence_proxy_async(
@@ -35,19 +35,23 @@ template <dot_space _Space>
 _CCCL_DEVICE static inline void fence_proxy_async(space_t<_Space> __space)
 {
   static_assert(__space == space_global || __space == space_cluster || __space == space_shared, "");
-  NV_IF_ELSE_TARGET(
-    NV_PROVIDES_SM_90,
-    (
-      _CCCL_IF_CONSTEXPR (__space == space_global) {
-        asm volatile("fence.proxy.async.global; // 6." : : : "memory");
-      } else _CCCL_IF_CONSTEXPR (__space == space_cluster) {
-        asm volatile("fence.proxy.async.shared::cluster; // 6." : : : "memory");
-      } else _CCCL_IF_CONSTEXPR (__space == space_shared) {
-        asm volatile("fence.proxy.async.shared::cta; // 6." : : : "memory");
-      }),
-    (
-      // Unsupported architectures will have a linker error with a semi-decent error message
-      __cuda_ptx_fence_proxy_async_is_not_supported_before_SM_90__();));
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  _CCCL_IF_CONSTEXPR (__space == space_global)
+  {
+    asm volatile("fence.proxy.async.global; // 6." : : : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__space == space_cluster)
+  {
+    asm volatile("fence.proxy.async.shared::cluster; // 6." : : : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__space == space_shared)
+  {
+    asm volatile("fence.proxy.async.shared::cta; // 6." : : : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_fence_proxy_async_is_not_supported_before_SM_90__();
+#  endif
 }
 #endif // __cccl_ptx_isa >= 800
 
diff --git a/libcudacxx/include/cuda/__ptx/instructions/generated/fence_proxy_async_generic_sync_restrict.h b/libcudacxx/include/cuda/__ptx/instructions/generated/fence_proxy_async_generic_sync_restrict.h
new file mode 100644
index 00000000000..93c66063ea3
--- /dev/null
+++ b/libcudacxx/include/cuda/__ptx/instructions/generated/fence_proxy_async_generic_sync_restrict.h
@@ -0,0 +1,62 @@
+// This file was automatically generated. Do not edit.
+
+#ifndef _CUDA_PTX_GENERATED_FENCE_PROXY_ASYNC_GENERIC_SYNC_RESTRICT_H_
+#define _CUDA_PTX_GENERATED_FENCE_PROXY_ASYNC_GENERIC_SYNC_RESTRICT_H_
+
+/*
+// fence.proxy.async::generic.sem.sync_restrict::space.scope; // PTX ISA 86, SM_90
+// .sem       = { .acquire }
+// .space     = { .shared::cluster }
+// .scope     = { .cluster }
+template <typename = void>
+__device__ static inline void fence_proxy_async_generic_sync_restrict(
+  cuda::ptx::sem_acquire_t,
+  cuda::ptx::space_cluster_t,
+  cuda::ptx::scope_cluster_t);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_fence_proxy_async_generic_sync_restrict_is_not_supported_before_SM_90__();
+template <typename = void>
+_CCCL_DEVICE static inline void fence_proxy_async_generic_sync_restrict(sem_acquire_t, space_cluster_t, scope_cluster_t)
+{
+// __sem == sem_acquire (due to parameter type constraint)
+// __space == space_cluster (due to parameter type constraint)
+// __scope == scope_cluster (due to parameter type constraint)
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  asm volatile("fence.proxy.async::generic.acquire.sync_restrict::shared::cluster.cluster;" : : : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_fence_proxy_async_generic_sync_restrict_is_not_supported_before_SM_90__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// fence.proxy.async::generic.sem.sync_restrict::space.scope; // PTX ISA 86, SM_90
+// .sem       = { .release }
+// .space     = { .shared::cta }
+// .scope     = { .cluster }
+template <typename = void>
+__device__ static inline void fence_proxy_async_generic_sync_restrict(
+  cuda::ptx::sem_release_t,
+  cuda::ptx::space_shared_t,
+  cuda::ptx::scope_cluster_t);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_fence_proxy_async_generic_sync_restrict_is_not_supported_before_SM_90__();
+template <typename = void>
+_CCCL_DEVICE static inline void fence_proxy_async_generic_sync_restrict(sem_release_t, space_shared_t, scope_cluster_t)
+{
+// __sem == sem_release (due to parameter type constraint)
+// __space == space_shared (due to parameter type constraint)
+// __scope == scope_cluster (due to parameter type constraint)
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  asm volatile("fence.proxy.async::generic.release.sync_restrict::shared::cta.cluster;" : : : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_fence_proxy_async_generic_sync_restrict_is_not_supported_before_SM_90__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+#endif // _CUDA_PTX_GENERATED_FENCE_PROXY_ASYNC_GENERIC_SYNC_RESTRICT_H_
diff --git a/libcudacxx/include/cuda/__ptx/instructions/generated/fence_proxy_tensormap_generic.h b/libcudacxx/include/cuda/__ptx/instructions/generated/fence_proxy_tensormap_generic.h
index 1e6119ee032..8988292b6d3 100644
--- a/libcudacxx/include/cuda/__ptx/instructions/generated/fence_proxy_tensormap_generic.h
+++ b/libcudacxx/include/cuda/__ptx/instructions/generated/fence_proxy_tensormap_generic.h
@@ -19,21 +19,27 @@ _CCCL_DEVICE static inline void fence_proxy_tensormap_generic(sem_release_t, sco
 {
   // __sem == sem_release (due to parameter type constraint)
   static_assert(__scope == scope_cta || __scope == scope_cluster || __scope == scope_gpu || __scope == scope_sys, "");
-  NV_IF_ELSE_TARGET(
-    NV_PROVIDES_SM_90,
-    (
-      _CCCL_IF_CONSTEXPR (__scope == scope_cta) {
-        asm volatile("fence.proxy.tensormap::generic.release.cta; // 7." : : : "memory");
-      } else _CCCL_IF_CONSTEXPR (__scope == scope_cluster) {
-        asm volatile("fence.proxy.tensormap::generic.release.cluster; // 7." : : : "memory");
-      } else _CCCL_IF_CONSTEXPR (__scope == scope_gpu) {
-        asm volatile("fence.proxy.tensormap::generic.release.gpu; // 7." : : : "memory");
-      } else _CCCL_IF_CONSTEXPR (__scope == scope_sys) {
-        asm volatile("fence.proxy.tensormap::generic.release.sys; // 7." : : : "memory");
-      }),
-    (
-      // Unsupported architectures will have a linker error with a semi-decent error message
-      __cuda_ptx_fence_proxy_tensormap_generic_is_not_supported_before_SM_90__();));
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  _CCCL_IF_CONSTEXPR (__scope == scope_cta)
+  {
+    asm volatile("fence.proxy.tensormap::generic.release.cta; // 7." : : : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__scope == scope_cluster)
+  {
+    asm volatile("fence.proxy.tensormap::generic.release.cluster; // 7." : : : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__scope == scope_gpu)
+  {
+    asm volatile("fence.proxy.tensormap::generic.release.gpu; // 7." : : : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__scope == scope_sys)
+  {
+    asm volatile("fence.proxy.tensormap::generic.release.sys; // 7." : : : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_fence_proxy_tensormap_generic_is_not_supported_before_SM_90__();
+#  endif
 }
 #endif // __cccl_ptx_isa >= 830
 
@@ -56,33 +62,39 @@ fence_proxy_tensormap_generic(sem_acquire_t, scope_t<_Scope> __scope, const void
 {
   // __sem == sem_acquire (due to parameter type constraint)
   static_assert(__scope == scope_cta || __scope == scope_cluster || __scope == scope_gpu || __scope == scope_sys, "");
-  NV_IF_ELSE_TARGET(
-    NV_PROVIDES_SM_90,
-    (
-      _CCCL_IF_CONSTEXPR (__scope == scope_cta) {
-        asm volatile("fence.proxy.tensormap::generic.acquire.cta [%0], %1; // 8."
-                     :
-                     : "l"(__addr), "n"(__size.value)
-                     : "memory");
-      } else _CCCL_IF_CONSTEXPR (__scope == scope_cluster) {
-        asm volatile("fence.proxy.tensormap::generic.acquire.cluster [%0], %1; // 8."
-                     :
-                     : "l"(__addr), "n"(__size.value)
-                     : "memory");
-      } else _CCCL_IF_CONSTEXPR (__scope == scope_gpu) {
-        asm volatile("fence.proxy.tensormap::generic.acquire.gpu [%0], %1; // 8."
-                     :
-                     : "l"(__addr), "n"(__size.value)
-                     : "memory");
-      } else _CCCL_IF_CONSTEXPR (__scope == scope_sys) {
-        asm volatile("fence.proxy.tensormap::generic.acquire.sys [%0], %1; // 8."
-                     :
-                     : "l"(__addr), "n"(__size.value)
-                     : "memory");
-      }),
-    (
-      // Unsupported architectures will have a linker error with a semi-decent error message
-      __cuda_ptx_fence_proxy_tensormap_generic_is_not_supported_before_SM_90__();));
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  _CCCL_IF_CONSTEXPR (__scope == scope_cta)
+  {
+    asm volatile("fence.proxy.tensormap::generic.acquire.cta [%0], %1; // 8."
+                 :
+                 : "l"(__addr), "n"(__size.value)
+                 : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__scope == scope_cluster)
+  {
+    asm volatile("fence.proxy.tensormap::generic.acquire.cluster [%0], %1; // 8."
+                 :
+                 : "l"(__addr), "n"(__size.value)
+                 : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__scope == scope_gpu)
+  {
+    asm volatile("fence.proxy.tensormap::generic.acquire.gpu [%0], %1; // 8."
+                 :
+                 : "l"(__addr), "n"(__size.value)
+                 : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__scope == scope_sys)
+  {
+    asm volatile("fence.proxy.tensormap::generic.acquire.sys [%0], %1; // 8."
+                 :
+                 : "l"(__addr), "n"(__size.value)
+                 : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_fence_proxy_tensormap_generic_is_not_supported_before_SM_90__();
+#  endif
 }
 #endif // __cccl_ptx_isa >= 830
 
diff --git a/libcudacxx/include/cuda/__ptx/instructions/generated/fence_sync_restrict.h b/libcudacxx/include/cuda/__ptx/instructions/generated/fence_sync_restrict.h
new file mode 100644
index 00000000000..4930bec068b
--- /dev/null
+++ b/libcudacxx/include/cuda/__ptx/instructions/generated/fence_sync_restrict.h
@@ -0,0 +1,62 @@
+// This file was automatically generated. Do not edit.
+
+#ifndef _CUDA_PTX_GENERATED_FENCE_SYNC_RESTRICT_H_
+#define _CUDA_PTX_GENERATED_FENCE_SYNC_RESTRICT_H_
+
+/*
+// fence.sem.sync_restrict::space.scope; // PTX ISA 86, SM_90
+// .sem       = { .acquire }
+// .space     = { .shared::cluster }
+// .scope     = { .cluster }
+template <typename = void>
+__device__ static inline void fence_sync_restrict(
+  cuda::ptx::sem_acquire_t,
+  cuda::ptx::space_cluster_t,
+  cuda::ptx::scope_cluster_t);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_fence_sync_restrict_is_not_supported_before_SM_90__();
+template <typename = void>
+_CCCL_DEVICE static inline void fence_sync_restrict(sem_acquire_t, space_cluster_t, scope_cluster_t)
+{
+// __sem == sem_acquire (due to parameter type constraint)
+// __space == space_cluster (due to parameter type constraint)
+// __scope == scope_cluster (due to parameter type constraint)
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  asm volatile("fence.acquire.sync_restrict::shared::cluster.cluster;" : : : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_fence_sync_restrict_is_not_supported_before_SM_90__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// fence.sem.sync_restrict::space.scope; // PTX ISA 86, SM_90
+// .sem       = { .release }
+// .space     = { .shared::cta }
+// .scope     = { .cluster }
+template <typename = void>
+__device__ static inline void fence_sync_restrict(
+  cuda::ptx::sem_release_t,
+  cuda::ptx::space_shared_t,
+  cuda::ptx::scope_cluster_t);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_fence_sync_restrict_is_not_supported_before_SM_90__();
+template <typename = void>
+_CCCL_DEVICE static inline void fence_sync_restrict(sem_release_t, space_shared_t, scope_cluster_t)
+{
+// __sem == sem_release (due to parameter type constraint)
+// __space == space_shared (due to parameter type constraint)
+// __scope == scope_cluster (due to parameter type constraint)
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  asm volatile("fence.release.sync_restrict::shared::cta.cluster;" : : : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_fence_sync_restrict_is_not_supported_before_SM_90__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+#endif // _CUDA_PTX_GENERATED_FENCE_SYNC_RESTRICT_H_
diff --git a/libcudacxx/include/cuda/__ptx/instructions/generated/get_sreg.h b/libcudacxx/include/cuda/__ptx/instructions/generated/get_sreg.h
index da802adb9db..e5c8fa89225 100644
--- a/libcudacxx/include/cuda/__ptx/instructions/generated/get_sreg.h
+++ b/libcudacxx/include/cuda/__ptx/instructions/generated/get_sreg.h
@@ -133,13 +133,15 @@ extern "C" _CCCL_DEVICE void __cuda_ptx_get_sreg_nwarpid_is_not_supported_before
 template <typename = void>
 _CCCL_DEVICE static inline _CUDA_VSTD::uint32_t get_sreg_nwarpid()
 {
-  NV_IF_ELSE_TARGET(
-    NV_PROVIDES_SM_35,
-    (_CUDA_VSTD::uint32_t __sreg_value; asm volatile("mov.u32 %0, %%nwarpid;" : "=r"(__sreg_value) : :);
-     return __sreg_value;),
-    (
-      // Unsupported architectures will have a linker error with a semi-decent error message
-      __cuda_ptx_get_sreg_nwarpid_is_not_supported_before_SM_35__(); return 0;));
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 350
+  _CUDA_VSTD::uint32_t __sreg_value;
+  asm volatile("mov.u32 %0, %%nwarpid;" : "=r"(__sreg_value) : :);
+  return __sreg_value;
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_get_sreg_nwarpid_is_not_supported_before_SM_35__();
+  return 0;
+#  endif
 }
 #endif // __cccl_ptx_isa >= 200
 
@@ -258,13 +260,15 @@ extern "C" _CCCL_DEVICE void __cuda_ptx_get_sreg_nsmid_is_not_supported_before_S
 template <typename = void>
 _CCCL_DEVICE static inline _CUDA_VSTD::uint32_t get_sreg_nsmid()
 {
-  NV_IF_ELSE_TARGET(
-    NV_PROVIDES_SM_35,
-    (_CUDA_VSTD::uint32_t __sreg_value; asm volatile("mov.u32 %0, %%nsmid;" : "=r"(__sreg_value) : :);
-     return __sreg_value;),
-    (
-      // Unsupported architectures will have a linker error with a semi-decent error message
-      __cuda_ptx_get_sreg_nsmid_is_not_supported_before_SM_35__(); return 0;));
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 350
+  _CUDA_VSTD::uint32_t __sreg_value;
+  asm volatile("mov.u32 %0, %%nsmid;" : "=r"(__sreg_value) : :);
+  return __sreg_value;
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_get_sreg_nsmid_is_not_supported_before_SM_35__();
+  return 0;
+#  endif
 }
 #endif // __cccl_ptx_isa >= 200
 
@@ -293,17 +297,21 @@ extern "C" _CCCL_DEVICE void __cuda_ptx_get_sreg_is_explicit_cluster_is_not_supp
 template <typename = void>
 _CCCL_DEVICE static inline bool get_sreg_is_explicit_cluster()
 {
-  NV_IF_ELSE_TARGET(
-    NV_PROVIDES_SM_90,
-    (_CUDA_VSTD::uint32_t __sreg_value;
-     asm("{\n\t .reg .pred P_OUT; \n\t"
-         "mov.pred P_OUT, %%is_explicit_cluster;\n\t"
-         "selp.b32 %0, 1, 0, P_OUT; \n"
-         "}" : "=r"(__sreg_value) : :);
-     return static_cast<bool>(__sreg_value);),
-    (
-      // Unsupported architectures will have a linker error with a semi-decent error message
-      __cuda_ptx_get_sreg_is_explicit_cluster_is_not_supported_before_SM_90__(); return false;));
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  _CUDA_VSTD::uint32_t __sreg_value;
+  asm("{\n\t .reg .pred P_OUT; \n\t"
+      "mov.pred P_OUT, %%is_explicit_cluster;\n\t"
+      "selp.b32 %0, 1, 0, P_OUT; \n"
+      "}"
+      : "=r"(__sreg_value)
+      :
+      :);
+  return static_cast<bool>(__sreg_value);
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_get_sreg_is_explicit_cluster_is_not_supported_before_SM_90__();
+  return false;
+#  endif
 }
 #endif // __cccl_ptx_isa >= 780
 
@@ -317,13 +325,15 @@ extern "C" _CCCL_DEVICE void __cuda_ptx_get_sreg_clusterid_x_is_not_supported_be
 template <typename = void>
 _CCCL_DEVICE static inline _CUDA_VSTD::uint32_t get_sreg_clusterid_x()
 {
-  NV_IF_ELSE_TARGET(
-    NV_PROVIDES_SM_90,
-    (_CUDA_VSTD::uint32_t __sreg_value; asm("mov.u32 %0, %%clusterid.x;" : "=r"(__sreg_value) : :);
-     return __sreg_value;),
-    (
-      // Unsupported architectures will have a linker error with a semi-decent error message
-      __cuda_ptx_get_sreg_clusterid_x_is_not_supported_before_SM_90__(); return 0;));
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  _CUDA_VSTD::uint32_t __sreg_value;
+  asm("mov.u32 %0, %%clusterid.x;" : "=r"(__sreg_value) : :);
+  return __sreg_value;
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_get_sreg_clusterid_x_is_not_supported_before_SM_90__();
+  return 0;
+#  endif
 }
 #endif // __cccl_ptx_isa >= 780
 
@@ -337,13 +347,15 @@ extern "C" _CCCL_DEVICE void __cuda_ptx_get_sreg_clusterid_y_is_not_supported_be
 template <typename = void>
 _CCCL_DEVICE static inline _CUDA_VSTD::uint32_t get_sreg_clusterid_y()
 {
-  NV_IF_ELSE_TARGET(
-    NV_PROVIDES_SM_90,
-    (_CUDA_VSTD::uint32_t __sreg_value; asm("mov.u32 %0, %%clusterid.y;" : "=r"(__sreg_value) : :);
-     return __sreg_value;),
-    (
-      // Unsupported architectures will have a linker error with a semi-decent error message
-      __cuda_ptx_get_sreg_clusterid_y_is_not_supported_before_SM_90__(); return 0;));
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  _CUDA_VSTD::uint32_t __sreg_value;
+  asm("mov.u32 %0, %%clusterid.y;" : "=r"(__sreg_value) : :);
+  return __sreg_value;
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_get_sreg_clusterid_y_is_not_supported_before_SM_90__();
+  return 0;
+#  endif
 }
 #endif // __cccl_ptx_isa >= 780
 
@@ -357,13 +369,15 @@ extern "C" _CCCL_DEVICE void __cuda_ptx_get_sreg_clusterid_z_is_not_supported_be
 template <typename = void>
 _CCCL_DEVICE static inline _CUDA_VSTD::uint32_t get_sreg_clusterid_z()
 {
-  NV_IF_ELSE_TARGET(
-    NV_PROVIDES_SM_90,
-    (_CUDA_VSTD::uint32_t __sreg_value; asm("mov.u32 %0, %%clusterid.z;" : "=r"(__sreg_value) : :);
-     return __sreg_value;),
-    (
-      // Unsupported architectures will have a linker error with a semi-decent error message
-      __cuda_ptx_get_sreg_clusterid_z_is_not_supported_before_SM_90__(); return 0;));
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  _CUDA_VSTD::uint32_t __sreg_value;
+  asm("mov.u32 %0, %%clusterid.z;" : "=r"(__sreg_value) : :);
+  return __sreg_value;
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_get_sreg_clusterid_z_is_not_supported_before_SM_90__();
+  return 0;
+#  endif
 }
 #endif // __cccl_ptx_isa >= 780
 
@@ -377,13 +391,15 @@ extern "C" _CCCL_DEVICE void __cuda_ptx_get_sreg_nclusterid_x_is_not_supported_b
 template <typename = void>
 _CCCL_DEVICE static inline _CUDA_VSTD::uint32_t get_sreg_nclusterid_x()
 {
-  NV_IF_ELSE_TARGET(
-    NV_PROVIDES_SM_90,
-    (_CUDA_VSTD::uint32_t __sreg_value; asm("mov.u32 %0, %%nclusterid.x;" : "=r"(__sreg_value) : :);
-     return __sreg_value;),
-    (
-      // Unsupported architectures will have a linker error with a semi-decent error message
-      __cuda_ptx_get_sreg_nclusterid_x_is_not_supported_before_SM_90__(); return 0;));
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  _CUDA_VSTD::uint32_t __sreg_value;
+  asm("mov.u32 %0, %%nclusterid.x;" : "=r"(__sreg_value) : :);
+  return __sreg_value;
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_get_sreg_nclusterid_x_is_not_supported_before_SM_90__();
+  return 0;
+#  endif
 }
 #endif // __cccl_ptx_isa >= 780
 
@@ -397,13 +413,15 @@ extern "C" _CCCL_DEVICE void __cuda_ptx_get_sreg_nclusterid_y_is_not_supported_b
 template <typename = void>
 _CCCL_DEVICE static inline _CUDA_VSTD::uint32_t get_sreg_nclusterid_y()
 {
-  NV_IF_ELSE_TARGET(
-    NV_PROVIDES_SM_90,
-    (_CUDA_VSTD::uint32_t __sreg_value; asm("mov.u32 %0, %%nclusterid.y;" : "=r"(__sreg_value) : :);
-     return __sreg_value;),
-    (
-      // Unsupported architectures will have a linker error with a semi-decent error message
-      __cuda_ptx_get_sreg_nclusterid_y_is_not_supported_before_SM_90__(); return 0;));
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  _CUDA_VSTD::uint32_t __sreg_value;
+  asm("mov.u32 %0, %%nclusterid.y;" : "=r"(__sreg_value) : :);
+  return __sreg_value;
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_get_sreg_nclusterid_y_is_not_supported_before_SM_90__();
+  return 0;
+#  endif
 }
 #endif // __cccl_ptx_isa >= 780
 
@@ -417,13 +435,15 @@ extern "C" _CCCL_DEVICE void __cuda_ptx_get_sreg_nclusterid_z_is_not_supported_b
 template <typename = void>
 _CCCL_DEVICE static inline _CUDA_VSTD::uint32_t get_sreg_nclusterid_z()
 {
-  NV_IF_ELSE_TARGET(
-    NV_PROVIDES_SM_90,
-    (_CUDA_VSTD::uint32_t __sreg_value; asm("mov.u32 %0, %%nclusterid.z;" : "=r"(__sreg_value) : :);
-     return __sreg_value;),
-    (
-      // Unsupported architectures will have a linker error with a semi-decent error message
-      __cuda_ptx_get_sreg_nclusterid_z_is_not_supported_before_SM_90__(); return 0;));
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  _CUDA_VSTD::uint32_t __sreg_value;
+  asm("mov.u32 %0, %%nclusterid.z;" : "=r"(__sreg_value) : :);
+  return __sreg_value;
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_get_sreg_nclusterid_z_is_not_supported_before_SM_90__();
+  return 0;
+#  endif
 }
 #endif // __cccl_ptx_isa >= 780
 
@@ -437,13 +457,15 @@ extern "C" _CCCL_DEVICE void __cuda_ptx_get_sreg_cluster_ctaid_x_is_not_supporte
 template <typename = void>
 _CCCL_DEVICE static inline _CUDA_VSTD::uint32_t get_sreg_cluster_ctaid_x()
 {
-  NV_IF_ELSE_TARGET(
-    NV_PROVIDES_SM_90,
-    (_CUDA_VSTD::uint32_t __sreg_value; asm("mov.u32 %0, %%cluster_ctaid.x;" : "=r"(__sreg_value) : :);
-     return __sreg_value;),
-    (
-      // Unsupported architectures will have a linker error with a semi-decent error message
-      __cuda_ptx_get_sreg_cluster_ctaid_x_is_not_supported_before_SM_90__(); return 0;));
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  _CUDA_VSTD::uint32_t __sreg_value;
+  asm("mov.u32 %0, %%cluster_ctaid.x;" : "=r"(__sreg_value) : :);
+  return __sreg_value;
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_get_sreg_cluster_ctaid_x_is_not_supported_before_SM_90__();
+  return 0;
+#  endif
 }
 #endif // __cccl_ptx_isa >= 780
 
@@ -457,13 +479,15 @@ extern "C" _CCCL_DEVICE void __cuda_ptx_get_sreg_cluster_ctaid_y_is_not_supporte
 template <typename = void>
 _CCCL_DEVICE static inline _CUDA_VSTD::uint32_t get_sreg_cluster_ctaid_y()
 {
-  NV_IF_ELSE_TARGET(
-    NV_PROVIDES_SM_90,
-    (_CUDA_VSTD::uint32_t __sreg_value; asm("mov.u32 %0, %%cluster_ctaid.y;" : "=r"(__sreg_value) : :);
-     return __sreg_value;),
-    (
-      // Unsupported architectures will have a linker error with a semi-decent error message
-      __cuda_ptx_get_sreg_cluster_ctaid_y_is_not_supported_before_SM_90__(); return 0;));
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  _CUDA_VSTD::uint32_t __sreg_value;
+  asm("mov.u32 %0, %%cluster_ctaid.y;" : "=r"(__sreg_value) : :);
+  return __sreg_value;
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_get_sreg_cluster_ctaid_y_is_not_supported_before_SM_90__();
+  return 0;
+#  endif
 }
 #endif // __cccl_ptx_isa >= 780
 
@@ -477,13 +501,15 @@ extern "C" _CCCL_DEVICE void __cuda_ptx_get_sreg_cluster_ctaid_z_is_not_supporte
 template <typename = void>
 _CCCL_DEVICE static inline _CUDA_VSTD::uint32_t get_sreg_cluster_ctaid_z()
 {
-  NV_IF_ELSE_TARGET(
-    NV_PROVIDES_SM_90,
-    (_CUDA_VSTD::uint32_t __sreg_value; asm("mov.u32 %0, %%cluster_ctaid.z;" : "=r"(__sreg_value) : :);
-     return __sreg_value;),
-    (
-      // Unsupported architectures will have a linker error with a semi-decent error message
-      __cuda_ptx_get_sreg_cluster_ctaid_z_is_not_supported_before_SM_90__(); return 0;));
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  _CUDA_VSTD::uint32_t __sreg_value;
+  asm("mov.u32 %0, %%cluster_ctaid.z;" : "=r"(__sreg_value) : :);
+  return __sreg_value;
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_get_sreg_cluster_ctaid_z_is_not_supported_before_SM_90__();
+  return 0;
+#  endif
 }
 #endif // __cccl_ptx_isa >= 780
 
@@ -497,13 +523,15 @@ extern "C" _CCCL_DEVICE void __cuda_ptx_get_sreg_cluster_nctaid_x_is_not_support
 template <typename = void>
 _CCCL_DEVICE static inline _CUDA_VSTD::uint32_t get_sreg_cluster_nctaid_x()
 {
-  NV_IF_ELSE_TARGET(
-    NV_PROVIDES_SM_90,
-    (_CUDA_VSTD::uint32_t __sreg_value; asm("mov.u32 %0, %%cluster_nctaid.x;" : "=r"(__sreg_value) : :);
-     return __sreg_value;),
-    (
-      // Unsupported architectures will have a linker error with a semi-decent error message
-      __cuda_ptx_get_sreg_cluster_nctaid_x_is_not_supported_before_SM_90__(); return 0;));
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  _CUDA_VSTD::uint32_t __sreg_value;
+  asm("mov.u32 %0, %%cluster_nctaid.x;" : "=r"(__sreg_value) : :);
+  return __sreg_value;
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_get_sreg_cluster_nctaid_x_is_not_supported_before_SM_90__();
+  return 0;
+#  endif
 }
 #endif // __cccl_ptx_isa >= 780
 
@@ -517,13 +545,15 @@ extern "C" _CCCL_DEVICE void __cuda_ptx_get_sreg_cluster_nctaid_y_is_not_support
 template <typename = void>
 _CCCL_DEVICE static inline _CUDA_VSTD::uint32_t get_sreg_cluster_nctaid_y()
 {
-  NV_IF_ELSE_TARGET(
-    NV_PROVIDES_SM_90,
-    (_CUDA_VSTD::uint32_t __sreg_value; asm("mov.u32 %0, %%cluster_nctaid.y;" : "=r"(__sreg_value) : :);
-     return __sreg_value;),
-    (
-      // Unsupported architectures will have a linker error with a semi-decent error message
-      __cuda_ptx_get_sreg_cluster_nctaid_y_is_not_supported_before_SM_90__(); return 0;));
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  _CUDA_VSTD::uint32_t __sreg_value;
+  asm("mov.u32 %0, %%cluster_nctaid.y;" : "=r"(__sreg_value) : :);
+  return __sreg_value;
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_get_sreg_cluster_nctaid_y_is_not_supported_before_SM_90__();
+  return 0;
+#  endif
 }
 #endif // __cccl_ptx_isa >= 780
 
@@ -537,13 +567,15 @@ extern "C" _CCCL_DEVICE void __cuda_ptx_get_sreg_cluster_nctaid_z_is_not_support
 template <typename = void>
 _CCCL_DEVICE static inline _CUDA_VSTD::uint32_t get_sreg_cluster_nctaid_z()
 {
-  NV_IF_ELSE_TARGET(
-    NV_PROVIDES_SM_90,
-    (_CUDA_VSTD::uint32_t __sreg_value; asm("mov.u32 %0, %%cluster_nctaid.z;" : "=r"(__sreg_value) : :);
-     return __sreg_value;),
-    (
-      // Unsupported architectures will have a linker error with a semi-decent error message
-      __cuda_ptx_get_sreg_cluster_nctaid_z_is_not_supported_before_SM_90__(); return 0;));
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  _CUDA_VSTD::uint32_t __sreg_value;
+  asm("mov.u32 %0, %%cluster_nctaid.z;" : "=r"(__sreg_value) : :);
+  return __sreg_value;
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_get_sreg_cluster_nctaid_z_is_not_supported_before_SM_90__();
+  return 0;
+#  endif
 }
 #endif // __cccl_ptx_isa >= 780
 
@@ -557,13 +589,15 @@ extern "C" _CCCL_DEVICE void __cuda_ptx_get_sreg_cluster_ctarank_is_not_supporte
 template <typename = void>
 _CCCL_DEVICE static inline _CUDA_VSTD::uint32_t get_sreg_cluster_ctarank()
 {
-  NV_IF_ELSE_TARGET(
-    NV_PROVIDES_SM_90,
-    (_CUDA_VSTD::uint32_t __sreg_value; asm("mov.u32 %0, %%cluster_ctarank;" : "=r"(__sreg_value) : :);
-     return __sreg_value;),
-    (
-      // Unsupported architectures will have a linker error with a semi-decent error message
-      __cuda_ptx_get_sreg_cluster_ctarank_is_not_supported_before_SM_90__(); return 0;));
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  _CUDA_VSTD::uint32_t __sreg_value;
+  asm("mov.u32 %0, %%cluster_ctarank;" : "=r"(__sreg_value) : :);
+  return __sreg_value;
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_get_sreg_cluster_ctarank_is_not_supported_before_SM_90__();
+  return 0;
+#  endif
 }
 #endif // __cccl_ptx_isa >= 780
 
@@ -577,13 +611,15 @@ extern "C" _CCCL_DEVICE void __cuda_ptx_get_sreg_cluster_nctarank_is_not_support
 template <typename = void>
 _CCCL_DEVICE static inline _CUDA_VSTD::uint32_t get_sreg_cluster_nctarank()
 {
-  NV_IF_ELSE_TARGET(
-    NV_PROVIDES_SM_90,
-    (_CUDA_VSTD::uint32_t __sreg_value; asm("mov.u32 %0, %%cluster_nctarank;" : "=r"(__sreg_value) : :);
-     return __sreg_value;),
-    (
-      // Unsupported architectures will have a linker error with a semi-decent error message
-      __cuda_ptx_get_sreg_cluster_nctarank_is_not_supported_before_SM_90__(); return 0;));
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  _CUDA_VSTD::uint32_t __sreg_value;
+  asm("mov.u32 %0, %%cluster_nctarank;" : "=r"(__sreg_value) : :);
+  return __sreg_value;
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_get_sreg_cluster_nctarank_is_not_supported_before_SM_90__();
+  return 0;
+#  endif
 }
 #endif // __cccl_ptx_isa >= 780
 
@@ -597,13 +633,15 @@ extern "C" _CCCL_DEVICE void __cuda_ptx_get_sreg_lanemask_eq_is_not_supported_be
 template <typename = void>
 _CCCL_DEVICE static inline _CUDA_VSTD::uint32_t get_sreg_lanemask_eq()
 {
-  NV_IF_ELSE_TARGET(
-    NV_PROVIDES_SM_35,
-    (_CUDA_VSTD::uint32_t __sreg_value; asm("mov.u32 %0, %%lanemask_eq;" : "=r"(__sreg_value) : :);
-     return __sreg_value;),
-    (
-      // Unsupported architectures will have a linker error with a semi-decent error message
-      __cuda_ptx_get_sreg_lanemask_eq_is_not_supported_before_SM_35__(); return 0;));
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 350
+  _CUDA_VSTD::uint32_t __sreg_value;
+  asm("mov.u32 %0, %%lanemask_eq;" : "=r"(__sreg_value) : :);
+  return __sreg_value;
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_get_sreg_lanemask_eq_is_not_supported_before_SM_35__();
+  return 0;
+#  endif
 }
 #endif // __cccl_ptx_isa >= 200
 
@@ -617,13 +655,15 @@ extern "C" _CCCL_DEVICE void __cuda_ptx_get_sreg_lanemask_le_is_not_supported_be
 template <typename = void>
 _CCCL_DEVICE static inline _CUDA_VSTD::uint32_t get_sreg_lanemask_le()
 {
-  NV_IF_ELSE_TARGET(
-    NV_PROVIDES_SM_35,
-    (_CUDA_VSTD::uint32_t __sreg_value; asm("mov.u32 %0, %%lanemask_le;" : "=r"(__sreg_value) : :);
-     return __sreg_value;),
-    (
-      // Unsupported architectures will have a linker error with a semi-decent error message
-      __cuda_ptx_get_sreg_lanemask_le_is_not_supported_before_SM_35__(); return 0;));
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 350
+  _CUDA_VSTD::uint32_t __sreg_value;
+  asm("mov.u32 %0, %%lanemask_le;" : "=r"(__sreg_value) : :);
+  return __sreg_value;
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_get_sreg_lanemask_le_is_not_supported_before_SM_35__();
+  return 0;
+#  endif
 }
 #endif // __cccl_ptx_isa >= 200
 
@@ -637,13 +677,15 @@ extern "C" _CCCL_DEVICE void __cuda_ptx_get_sreg_lanemask_lt_is_not_supported_be
 template <typename = void>
 _CCCL_DEVICE static inline _CUDA_VSTD::uint32_t get_sreg_lanemask_lt()
 {
-  NV_IF_ELSE_TARGET(
-    NV_PROVIDES_SM_35,
-    (_CUDA_VSTD::uint32_t __sreg_value; asm("mov.u32 %0, %%lanemask_lt;" : "=r"(__sreg_value) : :);
-     return __sreg_value;),
-    (
-      // Unsupported architectures will have a linker error with a semi-decent error message
-      __cuda_ptx_get_sreg_lanemask_lt_is_not_supported_before_SM_35__(); return 0;));
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 350
+  _CUDA_VSTD::uint32_t __sreg_value;
+  asm("mov.u32 %0, %%lanemask_lt;" : "=r"(__sreg_value) : :);
+  return __sreg_value;
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_get_sreg_lanemask_lt_is_not_supported_before_SM_35__();
+  return 0;
+#  endif
 }
 #endif // __cccl_ptx_isa >= 200
 
@@ -657,13 +699,15 @@ extern "C" _CCCL_DEVICE void __cuda_ptx_get_sreg_lanemask_ge_is_not_supported_be
 template <typename = void>
 _CCCL_DEVICE static inline _CUDA_VSTD::uint32_t get_sreg_lanemask_ge()
 {
-  NV_IF_ELSE_TARGET(
-    NV_PROVIDES_SM_35,
-    (_CUDA_VSTD::uint32_t __sreg_value; asm("mov.u32 %0, %%lanemask_ge;" : "=r"(__sreg_value) : :);
-     return __sreg_value;),
-    (
-      // Unsupported architectures will have a linker error with a semi-decent error message
-      __cuda_ptx_get_sreg_lanemask_ge_is_not_supported_before_SM_35__(); return 0;));
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 350
+  _CUDA_VSTD::uint32_t __sreg_value;
+  asm("mov.u32 %0, %%lanemask_ge;" : "=r"(__sreg_value) : :);
+  return __sreg_value;
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_get_sreg_lanemask_ge_is_not_supported_before_SM_35__();
+  return 0;
+#  endif
 }
 #endif // __cccl_ptx_isa >= 200
 
@@ -677,13 +721,15 @@ extern "C" _CCCL_DEVICE void __cuda_ptx_get_sreg_lanemask_gt_is_not_supported_be
 template <typename = void>
 _CCCL_DEVICE static inline _CUDA_VSTD::uint32_t get_sreg_lanemask_gt()
 {
-  NV_IF_ELSE_TARGET(
-    NV_PROVIDES_SM_35,
-    (_CUDA_VSTD::uint32_t __sreg_value; asm("mov.u32 %0, %%lanemask_gt;" : "=r"(__sreg_value) : :);
-     return __sreg_value;),
-    (
-      // Unsupported architectures will have a linker error with a semi-decent error message
-      __cuda_ptx_get_sreg_lanemask_gt_is_not_supported_before_SM_35__(); return 0;));
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 350
+  _CUDA_VSTD::uint32_t __sreg_value;
+  asm("mov.u32 %0, %%lanemask_gt;" : "=r"(__sreg_value) : :);
+  return __sreg_value;
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_get_sreg_lanemask_gt_is_not_supported_before_SM_35__();
+  return 0;
+#  endif
 }
 #endif // __cccl_ptx_isa >= 200
 
@@ -712,13 +758,15 @@ extern "C" _CCCL_DEVICE void __cuda_ptx_get_sreg_clock_hi_is_not_supported_befor
 template <typename = void>
 _CCCL_DEVICE static inline _CUDA_VSTD::uint32_t get_sreg_clock_hi()
 {
-  NV_IF_ELSE_TARGET(
-    NV_PROVIDES_SM_35,
-    (_CUDA_VSTD::uint32_t __sreg_value; asm volatile("mov.u32 %0, %%clock_hi;" : "=r"(__sreg_value) : :);
-     return __sreg_value;),
-    (
-      // Unsupported architectures will have a linker error with a semi-decent error message
-      __cuda_ptx_get_sreg_clock_hi_is_not_supported_before_SM_35__(); return 0;));
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 350
+  _CUDA_VSTD::uint32_t __sreg_value;
+  asm volatile("mov.u32 %0, %%clock_hi;" : "=r"(__sreg_value) : :);
+  return __sreg_value;
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_get_sreg_clock_hi_is_not_supported_before_SM_35__();
+  return 0;
+#  endif
 }
 #endif // __cccl_ptx_isa >= 500
 
@@ -732,13 +780,15 @@ extern "C" _CCCL_DEVICE void __cuda_ptx_get_sreg_clock64_is_not_supported_before
 template <typename = void>
 _CCCL_DEVICE static inline _CUDA_VSTD::uint64_t get_sreg_clock64()
 {
-  NV_IF_ELSE_TARGET(
-    NV_PROVIDES_SM_35,
-    (_CUDA_VSTD::uint64_t __sreg_value; asm volatile("mov.u64 %0, %%clock64;" : "=l"(__sreg_value) : :);
-     return __sreg_value;),
-    (
-      // Unsupported architectures will have a linker error with a semi-decent error message
-      __cuda_ptx_get_sreg_clock64_is_not_supported_before_SM_35__(); return 0;));
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 350
+  _CUDA_VSTD::uint64_t __sreg_value;
+  asm volatile("mov.u64 %0, %%clock64;" : "=l"(__sreg_value) : :);
+  return __sreg_value;
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_get_sreg_clock64_is_not_supported_before_SM_35__();
+  return 0;
+#  endif
 }
 #endif // __cccl_ptx_isa >= 200
 
@@ -752,13 +802,15 @@ extern "C" _CCCL_DEVICE void __cuda_ptx_get_sreg_globaltimer_is_not_supported_be
 template <typename = void>
 _CCCL_DEVICE static inline _CUDA_VSTD::uint64_t get_sreg_globaltimer()
 {
-  NV_IF_ELSE_TARGET(
-    NV_PROVIDES_SM_35,
-    (_CUDA_VSTD::uint64_t __sreg_value; asm volatile("mov.u64 %0, %%globaltimer;" : "=l"(__sreg_value) : :);
-     return __sreg_value;),
-    (
-      // Unsupported architectures will have a linker error with a semi-decent error message
-      __cuda_ptx_get_sreg_globaltimer_is_not_supported_before_SM_35__(); return 0;));
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 350
+  _CUDA_VSTD::uint64_t __sreg_value;
+  asm volatile("mov.u64 %0, %%globaltimer;" : "=l"(__sreg_value) : :);
+  return __sreg_value;
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_get_sreg_globaltimer_is_not_supported_before_SM_35__();
+  return 0;
+#  endif
 }
 #endif // __cccl_ptx_isa >= 310
 
@@ -772,13 +824,15 @@ extern "C" _CCCL_DEVICE void __cuda_ptx_get_sreg_globaltimer_lo_is_not_supported
 template <typename = void>
 _CCCL_DEVICE static inline _CUDA_VSTD::uint32_t get_sreg_globaltimer_lo()
 {
-  NV_IF_ELSE_TARGET(
-    NV_PROVIDES_SM_35,
-    (_CUDA_VSTD::uint32_t __sreg_value; asm volatile("mov.u32 %0, %%globaltimer_lo;" : "=r"(__sreg_value) : :);
-     return __sreg_value;),
-    (
-      // Unsupported architectures will have a linker error with a semi-decent error message
-      __cuda_ptx_get_sreg_globaltimer_lo_is_not_supported_before_SM_35__(); return 0;));
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 350
+  _CUDA_VSTD::uint32_t __sreg_value;
+  asm volatile("mov.u32 %0, %%globaltimer_lo;" : "=r"(__sreg_value) : :);
+  return __sreg_value;
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_get_sreg_globaltimer_lo_is_not_supported_before_SM_35__();
+  return 0;
+#  endif
 }
 #endif // __cccl_ptx_isa >= 310
 
@@ -792,13 +846,15 @@ extern "C" _CCCL_DEVICE void __cuda_ptx_get_sreg_globaltimer_hi_is_not_supported
 template <typename = void>
 _CCCL_DEVICE static inline _CUDA_VSTD::uint32_t get_sreg_globaltimer_hi()
 {
-  NV_IF_ELSE_TARGET(
-    NV_PROVIDES_SM_35,
-    (_CUDA_VSTD::uint32_t __sreg_value; asm volatile("mov.u32 %0, %%globaltimer_hi;" : "=r"(__sreg_value) : :);
-     return __sreg_value;),
-    (
-      // Unsupported architectures will have a linker error with a semi-decent error message
-      __cuda_ptx_get_sreg_globaltimer_hi_is_not_supported_before_SM_35__(); return 0;));
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 350
+  _CUDA_VSTD::uint32_t __sreg_value;
+  asm volatile("mov.u32 %0, %%globaltimer_hi;" : "=r"(__sreg_value) : :);
+  return __sreg_value;
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_get_sreg_globaltimer_hi_is_not_supported_before_SM_35__();
+  return 0;
+#  endif
 }
 #endif // __cccl_ptx_isa >= 310
 
@@ -812,13 +868,15 @@ extern "C" _CCCL_DEVICE void __cuda_ptx_get_sreg_total_smem_size_is_not_supporte
 template <typename = void>
 _CCCL_DEVICE static inline _CUDA_VSTD::uint32_t get_sreg_total_smem_size()
 {
-  NV_IF_ELSE_TARGET(
-    NV_PROVIDES_SM_35,
-    (_CUDA_VSTD::uint32_t __sreg_value; asm("mov.u32 %0, %%total_smem_size;" : "=r"(__sreg_value) : :);
-     return __sreg_value;),
-    (
-      // Unsupported architectures will have a linker error with a semi-decent error message
-      __cuda_ptx_get_sreg_total_smem_size_is_not_supported_before_SM_35__(); return 0;));
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 350
+  _CUDA_VSTD::uint32_t __sreg_value;
+  asm("mov.u32 %0, %%total_smem_size;" : "=r"(__sreg_value) : :);
+  return __sreg_value;
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_get_sreg_total_smem_size_is_not_supported_before_SM_35__();
+  return 0;
+#  endif
 }
 #endif // __cccl_ptx_isa >= 410
 
@@ -832,13 +890,15 @@ extern "C" _CCCL_DEVICE void __cuda_ptx_get_sreg_aggr_smem_size_is_not_supported
 template <typename = void>
 _CCCL_DEVICE static inline _CUDA_VSTD::uint32_t get_sreg_aggr_smem_size()
 {
-  NV_IF_ELSE_TARGET(
-    NV_PROVIDES_SM_90,
-    (_CUDA_VSTD::uint32_t __sreg_value; asm("mov.u32 %0, %%aggr_smem_size;" : "=r"(__sreg_value) : :);
-     return __sreg_value;),
-    (
-      // Unsupported architectures will have a linker error with a semi-decent error message
-      __cuda_ptx_get_sreg_aggr_smem_size_is_not_supported_before_SM_90__(); return 0;));
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  _CUDA_VSTD::uint32_t __sreg_value;
+  asm("mov.u32 %0, %%aggr_smem_size;" : "=r"(__sreg_value) : :);
+  return __sreg_value;
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_get_sreg_aggr_smem_size_is_not_supported_before_SM_90__();
+  return 0;
+#  endif
 }
 #endif // __cccl_ptx_isa >= 810
 
@@ -852,13 +912,15 @@ extern "C" _CCCL_DEVICE void __cuda_ptx_get_sreg_dynamic_smem_size_is_not_suppor
 template <typename = void>
 _CCCL_DEVICE static inline _CUDA_VSTD::uint32_t get_sreg_dynamic_smem_size()
 {
-  NV_IF_ELSE_TARGET(
-    NV_PROVIDES_SM_35,
-    (_CUDA_VSTD::uint32_t __sreg_value; asm("mov.u32 %0, %%dynamic_smem_size;" : "=r"(__sreg_value) : :);
-     return __sreg_value;),
-    (
-      // Unsupported architectures will have a linker error with a semi-decent error message
-      __cuda_ptx_get_sreg_dynamic_smem_size_is_not_supported_before_SM_35__(); return 0;));
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 350
+  _CUDA_VSTD::uint32_t __sreg_value;
+  asm("mov.u32 %0, %%dynamic_smem_size;" : "=r"(__sreg_value) : :);
+  return __sreg_value;
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_get_sreg_dynamic_smem_size_is_not_supported_before_SM_35__();
+  return 0;
+#  endif
 }
 #endif // __cccl_ptx_isa >= 410
 
@@ -872,13 +934,15 @@ extern "C" _CCCL_DEVICE void __cuda_ptx_get_sreg_current_graph_exec_is_not_suppo
 template <typename = void>
 _CCCL_DEVICE static inline _CUDA_VSTD::uint64_t get_sreg_current_graph_exec()
 {
-  NV_IF_ELSE_TARGET(
-    NV_PROVIDES_SM_50,
-    (_CUDA_VSTD::uint64_t __sreg_value; asm("mov.u64 %0, %%current_graph_exec;" : "=l"(__sreg_value) : :);
-     return __sreg_value;),
-    (
-      // Unsupported architectures will have a linker error with a semi-decent error message
-      __cuda_ptx_get_sreg_current_graph_exec_is_not_supported_before_SM_50__(); return 0;));
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 500
+  _CUDA_VSTD::uint64_t __sreg_value;
+  asm("mov.u64 %0, %%current_graph_exec;" : "=l"(__sreg_value) : :);
+  return __sreg_value;
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_get_sreg_current_graph_exec_is_not_supported_before_SM_50__();
+  return 0;
+#  endif
 }
 #endif // __cccl_ptx_isa >= 800
 
diff --git a/libcudacxx/include/cuda/__ptx/instructions/generated/getctarank.h b/libcudacxx/include/cuda/__ptx/instructions/generated/getctarank.h
index 22bb73180dc..c78637db3e9 100644
--- a/libcudacxx/include/cuda/__ptx/instructions/generated/getctarank.h
+++ b/libcudacxx/include/cuda/__ptx/instructions/generated/getctarank.h
@@ -4,7 +4,7 @@
 #define _CUDA_PTX_GENERATED_GETCTARANK_H_
 
 /*
-// getctarank{.space}.u32 dest, addr; // PTX ISA 78, SM_90
+// getctarank.space.u32 dest, addr; // PTX ISA 78, SM_90
 // .space     = { .shared::cluster }
 template <typename = void>
 __device__ static inline uint32_t getctarank(
@@ -16,15 +16,16 @@ extern "C" _CCCL_DEVICE void __cuda_ptx_getctarank_is_not_supported_before_SM_90
 template <typename = void>
 _CCCL_DEVICE static inline _CUDA_VSTD::uint32_t getctarank(space_cluster_t, const void* __addr)
 {
-  // __space == space_cluster (due to parameter type constraint)
-  NV_IF_ELSE_TARGET(
-    NV_PROVIDES_SM_90,
-    (_CUDA_VSTD::uint32_t __dest;
-     asm("getctarank.shared::cluster.u32 %0, %1;" : "=r"(__dest) : "r"(__as_ptr_smem(__addr)) :);
-     return __dest;),
-    (
-      // Unsupported architectures will have a linker error with a semi-decent error message
-      __cuda_ptx_getctarank_is_not_supported_before_SM_90__(); return 0;));
+// __space == space_cluster (due to parameter type constraint)
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  _CUDA_VSTD::uint32_t __dest;
+  asm("getctarank.shared::cluster.u32 %0, %1;" : "=r"(__dest) : "r"(__as_ptr_smem(__addr)) :);
+  return __dest;
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_getctarank_is_not_supported_before_SM_90__();
+  return 0;
+#  endif
 }
 #endif // __cccl_ptx_isa >= 780
 
diff --git a/libcudacxx/include/cuda/__ptx/instructions/generated/mapa.h b/libcudacxx/include/cuda/__ptx/instructions/generated/mapa.h
new file mode 100644
index 00000000000..f93c8a62157
--- /dev/null
+++ b/libcudacxx/include/cuda/__ptx/instructions/generated/mapa.h
@@ -0,0 +1,33 @@
+// This file was automatically generated. Do not edit.
+
+#ifndef _CUDA_PTX_GENERATED_MAPA_H_
+#define _CUDA_PTX_GENERATED_MAPA_H_
+
+/*
+// mapa.space.u32  dest, addr, target_cta; // PTX ISA 78, SM_90
+// .space     = { .shared::cluster }
+template <typename Tp>
+__device__ static inline Tp* mapa(
+  cuda::ptx::space_cluster_t,
+  const Tp* addr,
+  uint32_t target_cta);
+*/
+#if __cccl_ptx_isa >= 780
+extern "C" _CCCL_DEVICE void __cuda_ptx_mapa_is_not_supported_before_SM_90__();
+template <typename _Tp>
+_CCCL_DEVICE static inline _Tp* mapa(space_cluster_t, const _Tp* __addr, _CUDA_VSTD::uint32_t __target_cta)
+{
+// __space == space_cluster (due to parameter type constraint)
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  _CUDA_VSTD::uint32_t __dest;
+  asm("mapa.shared::cluster.u32  %0, %1, %2;" : "=r"(__dest) : "r"(__as_ptr_smem(__addr)), "r"(__target_cta) :);
+  return __from_ptr_dsmem<_Tp>(__dest);
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_mapa_is_not_supported_before_SM_90__();
+  return __from_ptr_dsmem<_Tp>(0);
+#  endif
+}
+#endif // __cccl_ptx_isa >= 780
+
+#endif // _CUDA_PTX_GENERATED_MAPA_H_
diff --git a/libcudacxx/include/cuda/__ptx/instructions/generated/mbarrier_arrive.h b/libcudacxx/include/cuda/__ptx/instructions/generated/mbarrier_arrive.h
index c7102ebfdb5..5f7b23dbb68 100644
--- a/libcudacxx/include/cuda/__ptx/instructions/generated/mbarrier_arrive.h
+++ b/libcudacxx/include/cuda/__ptx/instructions/generated/mbarrier_arrive.h
@@ -14,14 +14,18 @@ extern "C" _CCCL_DEVICE void __cuda_ptx_mbarrier_arrive_is_not_supported_before_
 template <typename = void>
 _CCCL_DEVICE static inline _CUDA_VSTD::uint64_t mbarrier_arrive(_CUDA_VSTD::uint64_t* __addr)
 {
-  NV_IF_ELSE_TARGET(
-    NV_PROVIDES_SM_80,
-    (_CUDA_VSTD::uint64_t __state; asm("mbarrier.arrive.shared.b64                                  %0,  [%1];         "
-                                       "  // 1. " : "=l"(__state) : "r"(__as_ptr_smem(__addr)) : "memory");
-     return __state;),
-    (
-      // Unsupported architectures will have a linker error with a semi-decent error message
-      __cuda_ptx_mbarrier_arrive_is_not_supported_before_SM_80__(); return 0;));
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 800
+  _CUDA_VSTD::uint64_t __state;
+  asm("mbarrier.arrive.shared.b64                                  %0,  [%1];           // 1. "
+      : "=l"(__state)
+      : "r"(__as_ptr_smem(__addr))
+      : "memory");
+  return __state;
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_mbarrier_arrive_is_not_supported_before_SM_80__();
+  return 0;
+#  endif
 }
 #endif // __cccl_ptx_isa >= 700
 
@@ -38,21 +42,23 @@ template <typename = void>
 _CCCL_DEVICE static inline _CUDA_VSTD::uint64_t
 mbarrier_arrive(_CUDA_VSTD::uint64_t* __addr, const _CUDA_VSTD::uint32_t& __count)
 {
-  NV_IF_ELSE_TARGET(
-    NV_PROVIDES_SM_90,
-    (_CUDA_VSTD::uint64_t __state;
-     asm("mbarrier.arrive.shared::cta.b64                             %0,  [%1], %2;    "
-         "// 2. " : "=l"(__state) : "r"(__as_ptr_smem(__addr)),
-         "r"(__count) : "memory");
-     return __state;),
-    (
-      // Unsupported architectures will have a linker error with a semi-decent error message
-      __cuda_ptx_mbarrier_arrive_is_not_supported_before_SM_90__(); return 0;));
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  _CUDA_VSTD::uint64_t __state;
+  asm("mbarrier.arrive.shared::cta.b64                             %0,  [%1], %2;    // 2. "
+      : "=l"(__state)
+      : "r"(__as_ptr_smem(__addr)), "r"(__count)
+      : "memory");
+  return __state;
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_mbarrier_arrive_is_not_supported_before_SM_90__();
+  return 0;
+#  endif
 }
 #endif // __cccl_ptx_isa >= 780
 
 /*
-// mbarrier.arrive{.sem}{.scope}{.space}.b64                   state,  [addr];           // 3a.  PTX ISA 80, SM_90
+// mbarrier.arrive.sem.scope.space.b64                   state,  [addr];           // 3a.  PTX ISA 80, SM_90
 // .sem       = { .release }
 // .scope     = { .cta, .cluster }
 // .space     = { .shared::cta }
@@ -71,29 +77,34 @@ mbarrier_arrive(sem_release_t, scope_t<_Scope> __scope, space_shared_t, _CUDA_VS
 {
   // __sem == sem_release (due to parameter type constraint)
   static_assert(__scope == scope_cta || __scope == scope_cluster, "");
-  // __space == space_shared (due to parameter type constraint)
-  NV_IF_ELSE_TARGET(
-    NV_PROVIDES_SM_90,
-    (
-      _CUDA_VSTD::uint64_t __state; _CCCL_IF_CONSTEXPR (__scope == scope_cta) {
-        asm("mbarrier.arrive.release.cta.shared::cta.b64                   %0,  [%1];           // 3a. "
-            : "=l"(__state)
-            : "r"(__as_ptr_smem(__addr))
-            : "memory");
-      } else _CCCL_IF_CONSTEXPR (__scope == scope_cluster) {
-        asm("mbarrier.arrive.release.cluster.shared::cta.b64                   %0,  [%1];           // 3a. "
-            : "=l"(__state)
-            : "r"(__as_ptr_smem(__addr))
-            : "memory");
-      } return __state;),
-    (
-      // Unsupported architectures will have a linker error with a semi-decent error message
-      __cuda_ptx_mbarrier_arrive_is_not_supported_before_SM_90__(); return 0;));
+// __space == space_shared (due to parameter type constraint)
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  _CUDA_VSTD::uint64_t __state;
+  _CCCL_IF_CONSTEXPR (__scope == scope_cta)
+  {
+    asm("mbarrier.arrive.release.cta.shared::cta.b64                   %0,  [%1];           // 3a. "
+        : "=l"(__state)
+        : "r"(__as_ptr_smem(__addr))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__scope == scope_cluster)
+  {
+    asm("mbarrier.arrive.release.cluster.shared::cta.b64                   %0,  [%1];           // 3a. "
+        : "=l"(__state)
+        : "r"(__as_ptr_smem(__addr))
+        : "memory");
+  }
+  return __state;
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_mbarrier_arrive_is_not_supported_before_SM_90__();
+  return 0;
+#  endif
 }
 #endif // __cccl_ptx_isa >= 800
 
 /*
-// mbarrier.arrive{.sem}{.scope}{.space}.b64                   state,  [addr], count;    // 3b.  PTX ISA 80, SM_90
+// mbarrier.arrive.sem.scope.space.b64                   state,  [addr], count;    // 3b.  PTX ISA 80, SM_90
 // .sem       = { .release }
 // .scope     = { .cta, .cluster }
 // .space     = { .shared::cta }
@@ -117,29 +128,34 @@ _CCCL_DEVICE static inline _CUDA_VSTD::uint64_t mbarrier_arrive(
 {
   // __sem == sem_release (due to parameter type constraint)
   static_assert(__scope == scope_cta || __scope == scope_cluster, "");
-  // __space == space_shared (due to parameter type constraint)
-  NV_IF_ELSE_TARGET(
-    NV_PROVIDES_SM_90,
-    (
-      _CUDA_VSTD::uint64_t __state; _CCCL_IF_CONSTEXPR (__scope == scope_cta) {
-        asm("mbarrier.arrive.release.cta.shared::cta.b64                   %0,  [%1], %2;    // 3b. "
-            : "=l"(__state)
-            : "r"(__as_ptr_smem(__addr)), "r"(__count)
-            : "memory");
-      } else _CCCL_IF_CONSTEXPR (__scope == scope_cluster) {
-        asm("mbarrier.arrive.release.cluster.shared::cta.b64                   %0,  [%1], %2;    // 3b. "
-            : "=l"(__state)
-            : "r"(__as_ptr_smem(__addr)), "r"(__count)
-            : "memory");
-      } return __state;),
-    (
-      // Unsupported architectures will have a linker error with a semi-decent error message
-      __cuda_ptx_mbarrier_arrive_is_not_supported_before_SM_90__(); return 0;));
+// __space == space_shared (due to parameter type constraint)
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  _CUDA_VSTD::uint64_t __state;
+  _CCCL_IF_CONSTEXPR (__scope == scope_cta)
+  {
+    asm("mbarrier.arrive.release.cta.shared::cta.b64                   %0,  [%1], %2;    // 3b. "
+        : "=l"(__state)
+        : "r"(__as_ptr_smem(__addr)), "r"(__count)
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__scope == scope_cluster)
+  {
+    asm("mbarrier.arrive.release.cluster.shared::cta.b64                   %0,  [%1], %2;    // 3b. "
+        : "=l"(__state)
+        : "r"(__as_ptr_smem(__addr)), "r"(__count)
+        : "memory");
+  }
+  return __state;
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_mbarrier_arrive_is_not_supported_before_SM_90__();
+  return 0;
+#  endif
 }
 #endif // __cccl_ptx_isa >= 800
 
 /*
-// mbarrier.arrive{.sem}{.scope}{.space}.b64                   _, [addr];                // 4a.  PTX ISA 80, SM_90
+// mbarrier.arrive.sem.scope.space.b64                   _, [addr];                // 4a.  PTX ISA 80, SM_90
 // .sem       = { .release }
 // .scope     = { .cluster }
 // .space     = { .shared::cluster }
@@ -156,21 +172,23 @@ template <typename = void>
 _CCCL_DEVICE static inline void
 mbarrier_arrive(sem_release_t, scope_cluster_t, space_cluster_t, _CUDA_VSTD::uint64_t* __addr)
 {
-  // __sem == sem_release (due to parameter type constraint)
-  // __scope == scope_cluster (due to parameter type constraint)
-  // __space == space_cluster (due to parameter type constraint)
-  NV_IF_ELSE_TARGET(
-    NV_PROVIDES_SM_90,
-    (asm("mbarrier.arrive.release.cluster.shared::cluster.b64                   _, [%0];               "
-         " // 4a. " : : "r"(__as_ptr_remote_dsmem(__addr)) : "memory");),
-    (
-      // Unsupported architectures will have a linker error with a semi-decent error message
-      __cuda_ptx_mbarrier_arrive_is_not_supported_before_SM_90__();));
+// __sem == sem_release (due to parameter type constraint)
+// __scope == scope_cluster (due to parameter type constraint)
+// __space == space_cluster (due to parameter type constraint)
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  asm("mbarrier.arrive.release.cluster.shared::cluster.b64                   _, [%0];                // 4a. "
+      :
+      : "r"(__as_ptr_remote_dsmem(__addr))
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_mbarrier_arrive_is_not_supported_before_SM_90__();
+#  endif
 }
 #endif // __cccl_ptx_isa >= 800
 
 /*
-// mbarrier.arrive{.sem}{.scope}{.space}.b64                   _, [addr], count;         // 4b.  PTX ISA 80, SM_90
+// mbarrier.arrive.sem.scope.space.b64                   _, [addr], count;         // 4b.  PTX ISA 80, SM_90
 // .sem       = { .release }
 // .scope     = { .cluster }
 // .space     = { .shared::cluster }
@@ -188,18 +206,180 @@ template <typename = void>
 _CCCL_DEVICE static inline void mbarrier_arrive(
   sem_release_t, scope_cluster_t, space_cluster_t, _CUDA_VSTD::uint64_t* __addr, const _CUDA_VSTD::uint32_t& __count)
 {
-  // __sem == sem_release (due to parameter type constraint)
-  // __scope == scope_cluster (due to parameter type constraint)
-  // __space == space_cluster (due to parameter type constraint)
-  NV_IF_ELSE_TARGET(
-    NV_PROVIDES_SM_90,
-    (asm("mbarrier.arrive.release.cluster.shared::cluster.b64                   _, [%0], %1;         "
-         "// 4b. " : : "r"(__as_ptr_remote_dsmem(__addr)),
-         "r"(__count) : "memory");),
-    (
-      // Unsupported architectures will have a linker error with a semi-decent error message
-      __cuda_ptx_mbarrier_arrive_is_not_supported_before_SM_90__();));
+// __sem == sem_release (due to parameter type constraint)
+// __scope == scope_cluster (due to parameter type constraint)
+// __space == space_cluster (due to parameter type constraint)
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  asm("mbarrier.arrive.release.cluster.shared::cluster.b64                   _, [%0], %1;         // 4b. "
+      :
+      : "r"(__as_ptr_remote_dsmem(__addr)), "r"(__count)
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_mbarrier_arrive_is_not_supported_before_SM_90__();
+#  endif
 }
 #endif // __cccl_ptx_isa >= 800
 
+/*
+// mbarrier.arrive.sem.scope.space.b64 state, [addr], count; // PTX ISA 86, SM_90
+// .space     = { .shared::cta }
+// .sem       = { .relaxed }
+// .scope     = { .cta, .cluster }
+template <cuda::ptx::dot_scope Scope>
+__device__ static inline uint64_t mbarrier_arrive(
+  cuda::ptx::space_shared_t,
+  cuda::ptx::sem_relaxed_t,
+  cuda::ptx::scope_t<Scope> scope,
+  uint64_t* addr,
+  const uint32_t& count);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_mbarrier_arrive_is_not_supported_before_SM_90__();
+template <dot_scope _Scope>
+_CCCL_DEVICE static inline _CUDA_VSTD::uint64_t mbarrier_arrive(
+  space_shared_t,
+  sem_relaxed_t,
+  scope_t<_Scope> __scope,
+  _CUDA_VSTD::uint64_t* __addr,
+  const _CUDA_VSTD::uint32_t& __count)
+{
+  // __space == space_shared (due to parameter type constraint)
+  // __sem == sem_relaxed (due to parameter type constraint)
+  static_assert(__scope == scope_cta || __scope == scope_cluster, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  _CUDA_VSTD::uint64_t __state;
+  _CCCL_IF_CONSTEXPR (__scope == scope_cta)
+  {
+    asm("mbarrier.arrive.relaxed.cta.shared::cta.b64 %0, [%1], %2;"
+        : "=l"(__state)
+        : "r"(__as_ptr_smem(__addr)), "r"(__count)
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__scope == scope_cluster)
+  {
+    asm("mbarrier.arrive.relaxed.cluster.shared::cta.b64 %0, [%1], %2;"
+        : "=l"(__state)
+        : "r"(__as_ptr_smem(__addr)), "r"(__count)
+        : "memory");
+  }
+  return __state;
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_mbarrier_arrive_is_not_supported_before_SM_90__();
+  return 0;
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// mbarrier.arrive.sem.scope.space.b64 state, [addr]; // PTX ISA 86, SM_90
+// .space     = { .shared::cta }
+// .sem       = { .relaxed }
+// .scope     = { .cta, .cluster }
+template <cuda::ptx::dot_scope Scope>
+__device__ static inline uint64_t mbarrier_arrive(
+  cuda::ptx::space_shared_t,
+  cuda::ptx::sem_relaxed_t,
+  cuda::ptx::scope_t<Scope> scope,
+  uint64_t* addr);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_mbarrier_arrive_is_not_supported_before_SM_90__();
+template <dot_scope _Scope>
+_CCCL_DEVICE static inline _CUDA_VSTD::uint64_t
+mbarrier_arrive(space_shared_t, sem_relaxed_t, scope_t<_Scope> __scope, _CUDA_VSTD::uint64_t* __addr)
+{
+  // __space == space_shared (due to parameter type constraint)
+  // __sem == sem_relaxed (due to parameter type constraint)
+  static_assert(__scope == scope_cta || __scope == scope_cluster, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  _CUDA_VSTD::uint64_t __state;
+  _CCCL_IF_CONSTEXPR (__scope == scope_cta)
+  {
+    asm("mbarrier.arrive.relaxed.cta.shared::cta.b64 %0, [%1];"
+        : "=l"(__state)
+        : "r"(__as_ptr_smem(__addr))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__scope == scope_cluster)
+  {
+    asm("mbarrier.arrive.relaxed.cluster.shared::cta.b64 %0, [%1];"
+        : "=l"(__state)
+        : "r"(__as_ptr_smem(__addr))
+        : "memory");
+  }
+  return __state;
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_mbarrier_arrive_is_not_supported_before_SM_90__();
+  return 0;
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// mbarrier.arrive.sem.scope.space.b64 _, [addr], count; // PTX ISA 86, SM_90
+// .space     = { .shared::cluster }
+// .sem       = { .relaxed }
+// .scope     = { .cluster }
+template <typename = void>
+__device__ static inline void mbarrier_arrive(
+  cuda::ptx::space_cluster_t,
+  cuda::ptx::sem_relaxed_t,
+  cuda::ptx::scope_cluster_t,
+  uint64_t* addr,
+  const uint32_t& count);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_mbarrier_arrive_is_not_supported_before_SM_90__();
+template <typename = void>
+_CCCL_DEVICE static inline void mbarrier_arrive(
+  space_cluster_t, sem_relaxed_t, scope_cluster_t, _CUDA_VSTD::uint64_t* __addr, const _CUDA_VSTD::uint32_t& __count)
+{
+// __space == space_cluster (due to parameter type constraint)
+// __sem == sem_relaxed (due to parameter type constraint)
+// __scope == scope_cluster (due to parameter type constraint)
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  asm("mbarrier.arrive.relaxed.cluster.shared::cluster.b64 _, [%0], %1;"
+      :
+      : "r"(__as_ptr_smem(__addr)), "r"(__count)
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_mbarrier_arrive_is_not_supported_before_SM_90__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// mbarrier.arrive.sem.scope.space.b64 _, [addr]; // PTX ISA 86, SM_90
+// .space     = { .shared::cluster }
+// .sem       = { .relaxed }
+// .scope     = { .cluster }
+template <typename = void>
+__device__ static inline void mbarrier_arrive(
+  cuda::ptx::space_cluster_t,
+  cuda::ptx::sem_relaxed_t,
+  cuda::ptx::scope_cluster_t,
+  uint64_t* addr);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_mbarrier_arrive_is_not_supported_before_SM_90__();
+template <typename = void>
+_CCCL_DEVICE static inline void
+mbarrier_arrive(space_cluster_t, sem_relaxed_t, scope_cluster_t, _CUDA_VSTD::uint64_t* __addr)
+{
+// __space == space_cluster (due to parameter type constraint)
+// __sem == sem_relaxed (due to parameter type constraint)
+// __scope == scope_cluster (due to parameter type constraint)
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  asm("mbarrier.arrive.relaxed.cluster.shared::cluster.b64 _, [%0];" : : "r"(__as_ptr_smem(__addr)) : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_mbarrier_arrive_is_not_supported_before_SM_90__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
 #endif // _CUDA_PTX_GENERATED_MBARRIER_ARRIVE_H_
diff --git a/libcudacxx/include/cuda/__ptx/instructions/generated/mbarrier_arrive_expect_tx.h b/libcudacxx/include/cuda/__ptx/instructions/generated/mbarrier_arrive_expect_tx.h
index dc33b212e21..5cbcd4cb3aa 100644
--- a/libcudacxx/include/cuda/__ptx/instructions/generated/mbarrier_arrive_expect_tx.h
+++ b/libcudacxx/include/cuda/__ptx/instructions/generated/mbarrier_arrive_expect_tx.h
@@ -4,7 +4,7 @@
 #define _CUDA_PTX_GENERATED_MBARRIER_ARRIVE_EXPECT_TX_H_
 
 /*
-// mbarrier.arrive.expect_tx{.sem}{.scope}{.space}.b64 state, [addr], tx_count; // 8.  PTX ISA 80, SM_90
+// mbarrier.arrive.expect_tx.sem.scope.space.b64 state, [addr], tx_count; // 8.  PTX ISA 80, SM_90
 // .sem       = { .release }
 // .scope     = { .cta, .cluster }
 // .space     = { .shared::cta }
@@ -28,29 +28,34 @@ _CCCL_DEVICE static inline _CUDA_VSTD::uint64_t mbarrier_arrive_expect_tx(
 {
   // __sem == sem_release (due to parameter type constraint)
   static_assert(__scope == scope_cta || __scope == scope_cluster, "");
-  // __space == space_shared (due to parameter type constraint)
-  NV_IF_ELSE_TARGET(
-    NV_PROVIDES_SM_90,
-    (
-      _CUDA_VSTD::uint64_t __state; _CCCL_IF_CONSTEXPR (__scope == scope_cta) {
-        asm("mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 %0, [%1], %2; // 8. "
-            : "=l"(__state)
-            : "r"(__as_ptr_smem(__addr)), "r"(__tx_count)
-            : "memory");
-      } else _CCCL_IF_CONSTEXPR (__scope == scope_cluster) {
-        asm("mbarrier.arrive.expect_tx.release.cluster.shared::cta.b64 %0, [%1], %2; // 8. "
-            : "=l"(__state)
-            : "r"(__as_ptr_smem(__addr)), "r"(__tx_count)
-            : "memory");
-      } return __state;),
-    (
-      // Unsupported architectures will have a linker error with a semi-decent error message
-      __cuda_ptx_mbarrier_arrive_expect_tx_is_not_supported_before_SM_90__(); return 0;));
+// __space == space_shared (due to parameter type constraint)
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  _CUDA_VSTD::uint64_t __state;
+  _CCCL_IF_CONSTEXPR (__scope == scope_cta)
+  {
+    asm("mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 %0, [%1], %2; // 8. "
+        : "=l"(__state)
+        : "r"(__as_ptr_smem(__addr)), "r"(__tx_count)
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__scope == scope_cluster)
+  {
+    asm("mbarrier.arrive.expect_tx.release.cluster.shared::cta.b64 %0, [%1], %2; // 8. "
+        : "=l"(__state)
+        : "r"(__as_ptr_smem(__addr)), "r"(__tx_count)
+        : "memory");
+  }
+  return __state;
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_mbarrier_arrive_expect_tx_is_not_supported_before_SM_90__();
+  return 0;
+#  endif
 }
 #endif // __cccl_ptx_isa >= 800
 
 /*
-// mbarrier.arrive.expect_tx{.sem}{.scope}{.space}.b64   _, [addr], tx_count; // 9.  PTX ISA 80, SM_90
+// mbarrier.arrive.expect_tx.sem.scope.space.b64   _, [addr], tx_count; // 9.  PTX ISA 80, SM_90
 // .sem       = { .release }
 // .scope     = { .cluster }
 // .space     = { .shared::cluster }
@@ -68,18 +73,104 @@ template <typename = void>
 _CCCL_DEVICE static inline void mbarrier_arrive_expect_tx(
   sem_release_t, scope_cluster_t, space_cluster_t, _CUDA_VSTD::uint64_t* __addr, const _CUDA_VSTD::uint32_t& __tx_count)
 {
-  // __sem == sem_release (due to parameter type constraint)
-  // __scope == scope_cluster (due to parameter type constraint)
-  // __space == space_cluster (due to parameter type constraint)
-  NV_IF_ELSE_TARGET(
-    NV_PROVIDES_SM_90,
-    (asm("mbarrier.arrive.expect_tx.release.cluster.shared::cluster.b64   _, [%0], %1; // 9. " : : "r"(
-           __as_ptr_remote_dsmem(__addr)),
-         "r"(__tx_count) : "memory");),
-    (
-      // Unsupported architectures will have a linker error with a semi-decent error message
-      __cuda_ptx_mbarrier_arrive_expect_tx_is_not_supported_before_SM_90__();));
+// __sem == sem_release (due to parameter type constraint)
+// __scope == scope_cluster (due to parameter type constraint)
+// __space == space_cluster (due to parameter type constraint)
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  asm("mbarrier.arrive.expect_tx.release.cluster.shared::cluster.b64   _, [%0], %1; // 9. "
+      :
+      : "r"(__as_ptr_remote_dsmem(__addr)), "r"(__tx_count)
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_mbarrier_arrive_expect_tx_is_not_supported_before_SM_90__();
+#  endif
 }
 #endif // __cccl_ptx_isa >= 800
 
+/*
+// mbarrier.arrive.expect_tx.sem.scope.space.b64 state, [addr], txCount; // PTX ISA 86, SM_90
+// .space     = { .shared::cta }
+// .sem       = { .relaxed }
+// .scope     = { .cta, .cluster }
+template <cuda::ptx::dot_scope Scope>
+__device__ static inline uint64_t mbarrier_arrive_expect_tx(
+  cuda::ptx::space_shared_t,
+  cuda::ptx::sem_relaxed_t,
+  cuda::ptx::scope_t<Scope> scope,
+  uint64_t* addr,
+  const uint32_t& txCount);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_mbarrier_arrive_expect_tx_is_not_supported_before_SM_90__();
+template <dot_scope _Scope>
+_CCCL_DEVICE static inline _CUDA_VSTD::uint64_t mbarrier_arrive_expect_tx(
+  space_shared_t,
+  sem_relaxed_t,
+  scope_t<_Scope> __scope,
+  _CUDA_VSTD::uint64_t* __addr,
+  const _CUDA_VSTD::uint32_t& __txCount)
+{
+  // __space == space_shared (due to parameter type constraint)
+  // __sem == sem_relaxed (due to parameter type constraint)
+  static_assert(__scope == scope_cta || __scope == scope_cluster, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  _CUDA_VSTD::uint64_t __state;
+  _CCCL_IF_CONSTEXPR (__scope == scope_cta)
+  {
+    asm("mbarrier.arrive.expect_tx.relaxed.cta.shared::cta.b64 %0, [%1], %2;"
+        : "=l"(__state)
+        : "r"(__as_ptr_dsmem(__addr)), "r"(__txCount)
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__scope == scope_cluster)
+  {
+    asm("mbarrier.arrive.expect_tx.relaxed.cluster.shared::cta.b64 %0, [%1], %2;"
+        : "=l"(__state)
+        : "r"(__as_ptr_dsmem(__addr)), "r"(__txCount)
+        : "memory");
+  }
+  return __state;
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_mbarrier_arrive_expect_tx_is_not_supported_before_SM_90__();
+  return 0;
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// mbarrier.arrive.expect_tx.sem.scope.space.b64 _, [addr], txCount; // PTX ISA 86, SM_90
+// .space     = { .shared::cluster }
+// .sem       = { .relaxed }
+// .scope     = { .cluster }
+template <typename = void>
+__device__ static inline void mbarrier_arrive_expect_tx(
+  cuda::ptx::space_cluster_t,
+  cuda::ptx::sem_relaxed_t,
+  cuda::ptx::scope_cluster_t,
+  uint64_t* addr,
+  const uint32_t& txCount);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_mbarrier_arrive_expect_tx_is_not_supported_before_SM_90__();
+template <typename = void>
+_CCCL_DEVICE static inline void mbarrier_arrive_expect_tx(
+  space_cluster_t, sem_relaxed_t, scope_cluster_t, _CUDA_VSTD::uint64_t* __addr, const _CUDA_VSTD::uint32_t& __txCount)
+{
+// __space == space_cluster (due to parameter type constraint)
+// __sem == sem_relaxed (due to parameter type constraint)
+// __scope == scope_cluster (due to parameter type constraint)
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  asm("mbarrier.arrive.expect_tx.relaxed.cluster.shared::cluster.b64 _, [%0], %1;"
+      :
+      : "r"(__as_ptr_dsmem(__addr)), "r"(__txCount)
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_mbarrier_arrive_expect_tx_is_not_supported_before_SM_90__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
 #endif // _CUDA_PTX_GENERATED_MBARRIER_ARRIVE_EXPECT_TX_H_
diff --git a/libcudacxx/include/cuda/__ptx/instructions/generated/mbarrier_arrive_no_complete.h b/libcudacxx/include/cuda/__ptx/instructions/generated/mbarrier_arrive_no_complete.h
index 45c444c5364..2a9ebacf295 100644
--- a/libcudacxx/include/cuda/__ptx/instructions/generated/mbarrier_arrive_no_complete.h
+++ b/libcudacxx/include/cuda/__ptx/instructions/generated/mbarrier_arrive_no_complete.h
@@ -16,16 +16,18 @@ template <typename = void>
 _CCCL_DEVICE static inline _CUDA_VSTD::uint64_t
 mbarrier_arrive_no_complete(_CUDA_VSTD::uint64_t* __addr, const _CUDA_VSTD::uint32_t& __count)
 {
-  NV_IF_ELSE_TARGET(
-    NV_PROVIDES_SM_80,
-    (_CUDA_VSTD::uint64_t __state;
-     asm("mbarrier.arrive.noComplete.shared.b64                       %0,  [%1], %2;    "
-         "// 5. " : "=l"(__state) : "r"(__as_ptr_smem(__addr)),
-         "r"(__count) : "memory");
-     return __state;),
-    (
-      // Unsupported architectures will have a linker error with a semi-decent error message
-      __cuda_ptx_mbarrier_arrive_no_complete_is_not_supported_before_SM_80__(); return 0;));
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 800
+  _CUDA_VSTD::uint64_t __state;
+  asm("mbarrier.arrive.noComplete.shared.b64                       %0,  [%1], %2;    // 5. "
+      : "=l"(__state)
+      : "r"(__as_ptr_smem(__addr)), "r"(__count)
+      : "memory");
+  return __state;
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_mbarrier_arrive_no_complete_is_not_supported_before_SM_80__();
+  return 0;
+#  endif
 }
 #endif // __cccl_ptx_isa >= 700
 
diff --git a/libcudacxx/include/cuda/__ptx/instructions/generated/mbarrier_expect_tx.h b/libcudacxx/include/cuda/__ptx/instructions/generated/mbarrier_expect_tx.h
new file mode 100644
index 00000000000..94d66b79a35
--- /dev/null
+++ b/libcudacxx/include/cuda/__ptx/instructions/generated/mbarrier_expect_tx.h
@@ -0,0 +1,94 @@
+// This file was automatically generated. Do not edit.
+
+#ifndef _CUDA_PTX_GENERATED_MBARRIER_EXPECT_TX_H_
+#define _CUDA_PTX_GENERATED_MBARRIER_EXPECT_TX_H_
+
+/*
+// mbarrier.expect_tx.sem.scope.space.b64 [addr], txCount; // 1. PTX ISA 80, SM_90
+// .sem       = { .relaxed }
+// .scope     = { .cta, .cluster }
+// .space     = { .shared::cta }
+template <cuda::ptx::dot_scope Scope>
+__device__ static inline void mbarrier_expect_tx(
+  cuda::ptx::sem_relaxed_t,
+  cuda::ptx::scope_t<Scope> scope,
+  cuda::ptx::space_shared_t,
+  uint64_t* addr,
+  uint32_t txCount);
+*/
+#if __cccl_ptx_isa >= 800
+extern "C" _CCCL_DEVICE void __cuda_ptx_mbarrier_expect_tx_is_not_supported_before_SM_90__();
+template <dot_scope _Scope>
+_CCCL_DEVICE static inline void mbarrier_expect_tx(
+  sem_relaxed_t, scope_t<_Scope> __scope, space_shared_t, _CUDA_VSTD::uint64_t* __addr, _CUDA_VSTD::uint32_t __txCount)
+{
+  // __sem == sem_relaxed (due to parameter type constraint)
+  static_assert(__scope == scope_cta || __scope == scope_cluster, "");
+// __space == space_shared (due to parameter type constraint)
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  _CCCL_IF_CONSTEXPR (__scope == scope_cta)
+  {
+    asm("mbarrier.expect_tx.relaxed.cta.shared::cta.b64 [%0], %1; // 1."
+        :
+        : "r"(__as_ptr_smem(__addr)), "r"(__txCount)
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__scope == scope_cluster)
+  {
+    asm("mbarrier.expect_tx.relaxed.cluster.shared::cta.b64 [%0], %1; // 1."
+        :
+        : "r"(__as_ptr_smem(__addr)), "r"(__txCount)
+        : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_mbarrier_expect_tx_is_not_supported_before_SM_90__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 800
+
+/*
+// mbarrier.expect_tx.sem.scope.space.b64 [addr], txCount; // 2. PTX ISA 80, SM_90
+// .sem       = { .relaxed }
+// .scope     = { .cta, .cluster }
+// .space     = { .shared::cluster }
+template <cuda::ptx::dot_scope Scope>
+__device__ static inline void mbarrier_expect_tx(
+  cuda::ptx::sem_relaxed_t,
+  cuda::ptx::scope_t<Scope> scope,
+  cuda::ptx::space_cluster_t,
+  uint64_t* addr,
+  uint32_t txCount);
+*/
+#if __cccl_ptx_isa >= 800
+extern "C" _CCCL_DEVICE void __cuda_ptx_mbarrier_expect_tx_is_not_supported_before_SM_90__();
+template <dot_scope _Scope>
+_CCCL_DEVICE static inline void mbarrier_expect_tx(
+  sem_relaxed_t, scope_t<_Scope> __scope, space_cluster_t, _CUDA_VSTD::uint64_t* __addr, _CUDA_VSTD::uint32_t __txCount)
+{
+  // __sem == sem_relaxed (due to parameter type constraint)
+  static_assert(__scope == scope_cta || __scope == scope_cluster, "");
+// __space == space_cluster (due to parameter type constraint)
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  _CCCL_IF_CONSTEXPR (__scope == scope_cta)
+  {
+    asm("mbarrier.expect_tx.relaxed.cta.shared::cluster.b64 [%0], %1; // 2."
+        :
+        : "r"(__as_ptr_dsmem(__addr)), "r"(__txCount)
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__scope == scope_cluster)
+  {
+    asm("mbarrier.expect_tx.relaxed.cluster.shared::cluster.b64 [%0], %1; // 2."
+        :
+        : "r"(__as_ptr_dsmem(__addr)), "r"(__txCount)
+        : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_mbarrier_expect_tx_is_not_supported_before_SM_90__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 800
+
+#endif // _CUDA_PTX_GENERATED_MBARRIER_EXPECT_TX_H_
diff --git a/libcudacxx/include/cuda/__ptx/instructions/generated/mbarrier_init.h b/libcudacxx/include/cuda/__ptx/instructions/generated/mbarrier_init.h
index 6b3041de0d2..9ba345f8ff2 100644
--- a/libcudacxx/include/cuda/__ptx/instructions/generated/mbarrier_init.h
+++ b/libcudacxx/include/cuda/__ptx/instructions/generated/mbarrier_init.h
@@ -15,12 +15,12 @@ extern "C" _CCCL_DEVICE void __cuda_ptx_mbarrier_init_is_not_supported_before_SM
 template <typename = void>
 _CCCL_DEVICE static inline void mbarrier_init(_CUDA_VSTD::uint64_t* __addr, const _CUDA_VSTD::uint32_t& __count)
 {
-  NV_IF_ELSE_TARGET(
-    NV_PROVIDES_SM_80,
-    (asm("mbarrier.init.shared.b64 [%0], %1;" : : "r"(__as_ptr_smem(__addr)), "r"(__count) : "memory");),
-    (
-      // Unsupported architectures will have a linker error with a semi-decent error message
-      __cuda_ptx_mbarrier_init_is_not_supported_before_SM_80__();));
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 800
+  asm("mbarrier.init.shared.b64 [%0], %1;" : : "r"(__as_ptr_smem(__addr)), "r"(__count) : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_mbarrier_init_is_not_supported_before_SM_80__();
+#  endif
 }
 #endif // __cccl_ptx_isa >= 700
 
diff --git a/libcudacxx/include/cuda/__ptx/instructions/generated/mbarrier_test_wait.h b/libcudacxx/include/cuda/__ptx/instructions/generated/mbarrier_test_wait.h
index 9adc677c76d..53263270f0d 100644
--- a/libcudacxx/include/cuda/__ptx/instructions/generated/mbarrier_test_wait.h
+++ b/libcudacxx/include/cuda/__ptx/instructions/generated/mbarrier_test_wait.h
@@ -15,23 +15,26 @@ extern "C" _CCCL_DEVICE void __cuda_ptx_mbarrier_test_wait_is_not_supported_befo
 template <typename = void>
 _CCCL_DEVICE static inline bool mbarrier_test_wait(_CUDA_VSTD::uint64_t* __addr, const _CUDA_VSTD::uint64_t& __state)
 {
-  NV_IF_ELSE_TARGET(
-    NV_PROVIDES_SM_80,
-    (_CUDA_VSTD::uint32_t __waitComplete;
-     asm("{\n\t .reg .pred P_OUT; \n\t"
-         "mbarrier.test_wait.shared.b64 P_OUT, [%1], %2;                                                  // 1. \n\t"
-         "selp.b32 %0, 1, 0, P_OUT; \n"
-         "}" : "=r"(__waitComplete) : "r"(__as_ptr_smem(__addr)),
-         "l"(__state) : "memory");
-     return static_cast<bool>(__waitComplete);),
-    (
-      // Unsupported architectures will have a linker error with a semi-decent error message
-      __cuda_ptx_mbarrier_test_wait_is_not_supported_before_SM_80__(); return false;));
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 800
+  _CUDA_VSTD::uint32_t __waitComplete;
+  asm("{\n\t .reg .pred P_OUT; \n\t"
+      "mbarrier.test_wait.shared.b64 P_OUT, [%1], %2;                                                  // 1. \n\t"
+      "selp.b32 %0, 1, 0, P_OUT; \n"
+      "}"
+      : "=r"(__waitComplete)
+      : "r"(__as_ptr_smem(__addr)), "l"(__state)
+      : "memory");
+  return static_cast<bool>(__waitComplete);
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_mbarrier_test_wait_is_not_supported_before_SM_80__();
+  return false;
+#  endif
 }
 #endif // __cccl_ptx_isa >= 700
 
 /*
-// mbarrier.test_wait{.sem}{.scope}.shared::cta.b64        waitComplete, [addr], state;                        // 2. PTX
+// mbarrier.test_wait.sem.scope.shared::cta.b64        waitComplete, [addr], state;                        // 2.   PTX
 ISA 80, SM_90
 // .sem       = { .acquire }
 // .scope     = { .cta, .cluster }
@@ -50,31 +53,87 @@ _CCCL_DEVICE static inline bool mbarrier_test_wait(
 {
   // __sem == sem_acquire (due to parameter type constraint)
   static_assert(__scope == scope_cta || __scope == scope_cluster, "");
-  NV_IF_ELSE_TARGET(
-    NV_PROVIDES_SM_90,
-    (
-      _CUDA_VSTD::uint32_t __waitComplete; _CCCL_IF_CONSTEXPR (__scope == scope_cta) {
-        asm("{\n\t .reg .pred P_OUT; \n\t"
-            "mbarrier.test_wait.acquire.cta.shared::cta.b64        P_OUT, [%1], %2;                        // 2.  \n\t"
-            "selp.b32 %0, 1, 0, P_OUT; \n"
-            "}"
-            : "=r"(__waitComplete)
-            : "r"(__as_ptr_smem(__addr)), "l"(__state)
-            : "memory");
-      } else _CCCL_IF_CONSTEXPR (__scope == scope_cluster) {
-        asm("{\n\t .reg .pred P_OUT; \n\t"
-            "mbarrier.test_wait.acquire.cluster.shared::cta.b64        P_OUT, [%1], %2;                        // 2.  "
-            "\n\t"
-            "selp.b32 %0, 1, 0, P_OUT; \n"
-            "}"
-            : "=r"(__waitComplete)
-            : "r"(__as_ptr_smem(__addr)), "l"(__state)
-            : "memory");
-      } return static_cast<bool>(__waitComplete);),
-    (
-      // Unsupported architectures will have a linker error with a semi-decent error message
-      __cuda_ptx_mbarrier_test_wait_is_not_supported_before_SM_90__(); return false;));
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  _CUDA_VSTD::uint32_t __waitComplete;
+  _CCCL_IF_CONSTEXPR (__scope == scope_cta)
+  {
+    asm("{\n\t .reg .pred P_OUT; \n\t"
+        "mbarrier.test_wait.acquire.cta.shared::cta.b64        P_OUT, [%1], %2;                        // 2.  \n\t"
+        "selp.b32 %0, 1, 0, P_OUT; \n"
+        "}"
+        : "=r"(__waitComplete)
+        : "r"(__as_ptr_smem(__addr)), "l"(__state)
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__scope == scope_cluster)
+  {
+    asm("{\n\t .reg .pred P_OUT; \n\t"
+        "mbarrier.test_wait.acquire.cluster.shared::cta.b64        P_OUT, [%1], %2;                        // 2.  \n\t"
+        "selp.b32 %0, 1, 0, P_OUT; \n"
+        "}"
+        : "=r"(__waitComplete)
+        : "r"(__as_ptr_smem(__addr)), "l"(__state)
+        : "memory");
+  }
+  return static_cast<bool>(__waitComplete);
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_mbarrier_test_wait_is_not_supported_before_SM_90__();
+  return false;
+#  endif
 }
 #endif // __cccl_ptx_isa >= 800
 
+/*
+// mbarrier.test_wait.sem.scope.shared::cta.b64 waitComplete, [addr], state; // PTX ISA 86, SM_90
+// .sem       = { .relaxed }
+// .scope     = { .cta, .cluster }
+template <cuda::ptx::dot_scope Scope>
+__device__ static inline void mbarrier_test_wait(
+  cuda::ptx::sem_relaxed_t,
+  cuda::ptx::scope_t<Scope> scope,
+  bool waitComplete,
+  uint64_t* addr,
+  const uint64_t& state);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_mbarrier_test_wait_is_not_supported_before_SM_90__();
+template <dot_scope _Scope>
+_CCCL_DEVICE static inline void mbarrier_test_wait(
+  sem_relaxed_t,
+  scope_t<_Scope> __scope,
+  bool __waitComplete,
+  _CUDA_VSTD::uint64_t* __addr,
+  const _CUDA_VSTD::uint64_t& __state)
+{
+  // __sem == sem_relaxed (due to parameter type constraint)
+  static_assert(__scope == scope_cta || __scope == scope_cluster, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  _CCCL_IF_CONSTEXPR (__scope == scope_cta)
+  {
+    asm("{\n\t .reg .pred PRED_waitComplete; \n\t"
+        "setp.ne.b32 PRED_waitComplete, %0, 0;\n\t"
+        "mbarrier.test_wait.relaxed.cta.shared::cta.b64 PRED_waitComplete, [%1], %2;\n\t"
+        "}"
+        :
+        : "r"(static_cast<_CUDA_VSTD::uint32_t>(__waitComplete)), "r"(__as_ptr_smem(__addr)), "l"(__state)
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__scope == scope_cluster)
+  {
+    asm("{\n\t .reg .pred PRED_waitComplete; \n\t"
+        "setp.ne.b32 PRED_waitComplete, %0, 0;\n\t"
+        "mbarrier.test_wait.relaxed.cluster.shared::cta.b64 PRED_waitComplete, [%1], %2;\n\t"
+        "}"
+        :
+        : "r"(static_cast<_CUDA_VSTD::uint32_t>(__waitComplete)), "r"(__as_ptr_smem(__addr)), "l"(__state)
+        : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_mbarrier_test_wait_is_not_supported_before_SM_90__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
 #endif // _CUDA_PTX_GENERATED_MBARRIER_TEST_WAIT_H_
diff --git a/libcudacxx/include/cuda/__ptx/instructions/generated/mbarrier_test_wait_parity.h b/libcudacxx/include/cuda/__ptx/instructions/generated/mbarrier_test_wait_parity.h
index 1166b336d2d..3a281e22087 100644
--- a/libcudacxx/include/cuda/__ptx/instructions/generated/mbarrier_test_wait_parity.h
+++ b/libcudacxx/include/cuda/__ptx/instructions/generated/mbarrier_test_wait_parity.h
@@ -16,23 +16,26 @@ template <typename = void>
 _CCCL_DEVICE static inline bool
 mbarrier_test_wait_parity(_CUDA_VSTD::uint64_t* __addr, const _CUDA_VSTD::uint32_t& __phaseParity)
 {
-  NV_IF_ELSE_TARGET(
-    NV_PROVIDES_SM_80,
-    (_CUDA_VSTD::uint32_t __waitComplete;
-     asm("{\n\t .reg .pred P_OUT; \n\t"
-         "mbarrier.test_wait.parity.shared.b64 P_OUT, [%1], %2;                                     // 3. \n\t"
-         "selp.b32 %0, 1, 0, P_OUT; \n"
-         "}" : "=r"(__waitComplete) : "r"(__as_ptr_smem(__addr)),
-         "r"(__phaseParity) : "memory");
-     return static_cast<bool>(__waitComplete);),
-    (
-      // Unsupported architectures will have a linker error with a semi-decent error message
-      __cuda_ptx_mbarrier_test_wait_parity_is_not_supported_before_SM_80__(); return false;));
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 800
+  _CUDA_VSTD::uint32_t __waitComplete;
+  asm("{\n\t .reg .pred P_OUT; \n\t"
+      "mbarrier.test_wait.parity.shared.b64 P_OUT, [%1], %2;                                     // 3. \n\t"
+      "selp.b32 %0, 1, 0, P_OUT; \n"
+      "}"
+      : "=r"(__waitComplete)
+      : "r"(__as_ptr_smem(__addr)), "r"(__phaseParity)
+      : "memory");
+  return static_cast<bool>(__waitComplete);
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_mbarrier_test_wait_parity_is_not_supported_before_SM_80__();
+  return false;
+#  endif
 }
 #endif // __cccl_ptx_isa >= 710
 
 /*
-// mbarrier.test_wait.parity{.sem}{.scope}.shared::cta.b64 waitComplete, [addr], phaseParity;                  // 4. PTX
+// mbarrier.test_wait.parity.sem.scope.shared::cta.b64 waitComplete, [addr], phaseParity;                  // 4.  PTX
 ISA 80, SM_90
 // .sem       = { .acquire }
 // .scope     = { .cta, .cluster }
@@ -51,30 +54,87 @@ _CCCL_DEVICE static inline bool mbarrier_test_wait_parity(
 {
   // __sem == sem_acquire (due to parameter type constraint)
   static_assert(__scope == scope_cta || __scope == scope_cluster, "");
-  NV_IF_ELSE_TARGET(
-    NV_PROVIDES_SM_90,
-    (
-      _CUDA_VSTD::uint32_t __waitComplete; _CCCL_IF_CONSTEXPR (__scope == scope_cta) {
-        asm("{\n\t .reg .pred P_OUT; \n\t"
-            "mbarrier.test_wait.parity.acquire.cta.shared::cta.b64 P_OUT, [%1], %2;                  // 4. \n\t"
-            "selp.b32 %0, 1, 0, P_OUT; \n"
-            "}"
-            : "=r"(__waitComplete)
-            : "r"(__as_ptr_smem(__addr)), "r"(__phaseParity)
-            : "memory");
-      } else _CCCL_IF_CONSTEXPR (__scope == scope_cluster) {
-        asm("{\n\t .reg .pred P_OUT; \n\t"
-            "mbarrier.test_wait.parity.acquire.cluster.shared::cta.b64 P_OUT, [%1], %2;                  // 4. \n\t"
-            "selp.b32 %0, 1, 0, P_OUT; \n"
-            "}"
-            : "=r"(__waitComplete)
-            : "r"(__as_ptr_smem(__addr)), "r"(__phaseParity)
-            : "memory");
-      } return static_cast<bool>(__waitComplete);),
-    (
-      // Unsupported architectures will have a linker error with a semi-decent error message
-      __cuda_ptx_mbarrier_test_wait_parity_is_not_supported_before_SM_90__(); return false;));
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  _CUDA_VSTD::uint32_t __waitComplete;
+  _CCCL_IF_CONSTEXPR (__scope == scope_cta)
+  {
+    asm("{\n\t .reg .pred P_OUT; \n\t"
+        "mbarrier.test_wait.parity.acquire.cta.shared::cta.b64 P_OUT, [%1], %2;                  // 4. \n\t"
+        "selp.b32 %0, 1, 0, P_OUT; \n"
+        "}"
+        : "=r"(__waitComplete)
+        : "r"(__as_ptr_smem(__addr)), "r"(__phaseParity)
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__scope == scope_cluster)
+  {
+    asm("{\n\t .reg .pred P_OUT; \n\t"
+        "mbarrier.test_wait.parity.acquire.cluster.shared::cta.b64 P_OUT, [%1], %2;                  // 4. \n\t"
+        "selp.b32 %0, 1, 0, P_OUT; \n"
+        "}"
+        : "=r"(__waitComplete)
+        : "r"(__as_ptr_smem(__addr)), "r"(__phaseParity)
+        : "memory");
+  }
+  return static_cast<bool>(__waitComplete);
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_mbarrier_test_wait_parity_is_not_supported_before_SM_90__();
+  return false;
+#  endif
 }
 #endif // __cccl_ptx_isa >= 800
 
+/*
+// mbarrier.test_wait.parity.sem.scope.shared::cta.b64 waitComplete, [addr], phaseParity; // PTX ISA 86, SM_90
+// .sem       = { .relaxed }
+// .scope     = { .cta, .cluster }
+template <cuda::ptx::dot_scope Scope>
+__device__ static inline void mbarrier_test_wait_parity(
+  cuda::ptx::sem_relaxed_t,
+  cuda::ptx::scope_t<Scope> scope,
+  bool waitComplete,
+  uint64_t* addr,
+  const uint32_t& phaseParity);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_mbarrier_test_wait_parity_is_not_supported_before_SM_90__();
+template <dot_scope _Scope>
+_CCCL_DEVICE static inline void mbarrier_test_wait_parity(
+  sem_relaxed_t,
+  scope_t<_Scope> __scope,
+  bool __waitComplete,
+  _CUDA_VSTD::uint64_t* __addr,
+  const _CUDA_VSTD::uint32_t& __phaseParity)
+{
+  // __sem == sem_relaxed (due to parameter type constraint)
+  static_assert(__scope == scope_cta || __scope == scope_cluster, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  _CCCL_IF_CONSTEXPR (__scope == scope_cta)
+  {
+    asm("{\n\t .reg .pred PRED_waitComplete; \n\t"
+        "setp.ne.b32 PRED_waitComplete, %0, 0;\n\t"
+        "mbarrier.test_wait.parity.relaxed.cta.shared::cta.b64 PRED_waitComplete, [%1], %2;\n\t"
+        "}"
+        :
+        : "r"(static_cast<_CUDA_VSTD::uint32_t>(__waitComplete)), "r"(__as_ptr_smem(__addr)), "r"(__phaseParity)
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__scope == scope_cluster)
+  {
+    asm("{\n\t .reg .pred PRED_waitComplete; \n\t"
+        "setp.ne.b32 PRED_waitComplete, %0, 0;\n\t"
+        "mbarrier.test_wait.parity.relaxed.cluster.shared::cta.b64 PRED_waitComplete, [%1], %2;\n\t"
+        "}"
+        :
+        : "r"(static_cast<_CUDA_VSTD::uint32_t>(__waitComplete)), "r"(__as_ptr_smem(__addr)), "r"(__phaseParity)
+        : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_mbarrier_test_wait_parity_is_not_supported_before_SM_90__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
 #endif // _CUDA_PTX_GENERATED_MBARRIER_TEST_WAIT_PARITY_H_
diff --git a/libcudacxx/include/cuda/__ptx/instructions/generated/mbarrier_try_wait.h b/libcudacxx/include/cuda/__ptx/instructions/generated/mbarrier_try_wait.h
index 52fa5a4928a..c048136b87a 100644
--- a/libcudacxx/include/cuda/__ptx/instructions/generated/mbarrier_try_wait.h
+++ b/libcudacxx/include/cuda/__ptx/instructions/generated/mbarrier_try_wait.h
@@ -15,18 +15,21 @@ extern "C" _CCCL_DEVICE void __cuda_ptx_mbarrier_try_wait_is_not_supported_befor
 template <typename = void>
 _CCCL_DEVICE static inline bool mbarrier_try_wait(_CUDA_VSTD::uint64_t* __addr, const _CUDA_VSTD::uint64_t& __state)
 {
-  NV_IF_ELSE_TARGET(
-    NV_PROVIDES_SM_90,
-    (_CUDA_VSTD::uint32_t __waitComplete;
-     asm("{\n\t .reg .pred P_OUT; \n\t"
-         "mbarrier.try_wait.shared::cta.b64         P_OUT, [%1], %2;                                      // 5a. \n\t"
-         "selp.b32 %0, 1, 0, P_OUT; \n"
-         "}" : "=r"(__waitComplete) : "r"(__as_ptr_smem(__addr)),
-         "l"(__state) : "memory");
-     return static_cast<bool>(__waitComplete);),
-    (
-      // Unsupported architectures will have a linker error with a semi-decent error message
-      __cuda_ptx_mbarrier_try_wait_is_not_supported_before_SM_90__(); return false;));
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  _CUDA_VSTD::uint32_t __waitComplete;
+  asm("{\n\t .reg .pred P_OUT; \n\t"
+      "mbarrier.try_wait.shared::cta.b64         P_OUT, [%1], %2;                                      // 5a. \n\t"
+      "selp.b32 %0, 1, 0, P_OUT; \n"
+      "}"
+      : "=r"(__waitComplete)
+      : "r"(__as_ptr_smem(__addr)), "l"(__state)
+      : "memory");
+  return static_cast<bool>(__waitComplete);
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_mbarrier_try_wait_is_not_supported_before_SM_90__();
+  return false;
+#  endif
 }
 #endif // __cccl_ptx_isa >= 780
 
@@ -44,25 +47,27 @@ template <typename = void>
 _CCCL_DEVICE static inline bool mbarrier_try_wait(
   _CUDA_VSTD::uint64_t* __addr, const _CUDA_VSTD::uint64_t& __state, const _CUDA_VSTD::uint32_t& __suspendTimeHint)
 {
-  NV_IF_ELSE_TARGET(
-    NV_PROVIDES_SM_90,
-    (_CUDA_VSTD::uint32_t __waitComplete;
-     asm("{\n\t .reg .pred P_OUT; \n\t"
-         "mbarrier.try_wait.shared::cta.b64         P_OUT, [%1], %2, %3;                    // 5b. \n\t"
-         "selp.b32 %0, 1, 0, P_OUT; \n"
-         "}" : "=r"(__waitComplete) : "r"(__as_ptr_smem(__addr)),
-         "l"(__state),
-         "r"(__suspendTimeHint) : "memory");
-     return static_cast<bool>(__waitComplete);),
-    (
-      // Unsupported architectures will have a linker error with a semi-decent error message
-      __cuda_ptx_mbarrier_try_wait_is_not_supported_before_SM_90__(); return false;));
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  _CUDA_VSTD::uint32_t __waitComplete;
+  asm("{\n\t .reg .pred P_OUT; \n\t"
+      "mbarrier.try_wait.shared::cta.b64         P_OUT, [%1], %2, %3;                    // 5b. \n\t"
+      "selp.b32 %0, 1, 0, P_OUT; \n"
+      "}"
+      : "=r"(__waitComplete)
+      : "r"(__as_ptr_smem(__addr)), "l"(__state), "r"(__suspendTimeHint)
+      : "memory");
+  return static_cast<bool>(__waitComplete);
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_mbarrier_try_wait_is_not_supported_before_SM_90__();
+  return false;
+#  endif
 }
 #endif // __cccl_ptx_isa >= 780
 
 /*
-// mbarrier.try_wait{.sem}{.scope}.shared::cta.b64         waitComplete, [addr], state;                        // 6a.
-PTX ISA 80, SM_90
+// mbarrier.try_wait.sem.scope.shared::cta.b64         waitComplete, [addr], state;                        // 6a.  PTX
+ISA 80, SM_90
 // .sem       = { .acquire }
 // .scope     = { .cta, .cluster }
 template <cuda::ptx::dot_scope Scope>
@@ -80,36 +85,40 @@ _CCCL_DEVICE static inline bool mbarrier_try_wait(
 {
   // __sem == sem_acquire (due to parameter type constraint)
   static_assert(__scope == scope_cta || __scope == scope_cluster, "");
-  NV_IF_ELSE_TARGET(
-    NV_PROVIDES_SM_90,
-    (
-      _CUDA_VSTD::uint32_t __waitComplete; _CCCL_IF_CONSTEXPR (__scope == scope_cta) {
-        asm("{\n\t .reg .pred P_OUT; \n\t"
-            "mbarrier.try_wait.acquire.cta.shared::cta.b64         P_OUT, [%1], %2;                        // 6a. \n\t"
-            "selp.b32 %0, 1, 0, P_OUT; \n"
-            "}"
-            : "=r"(__waitComplete)
-            : "r"(__as_ptr_smem(__addr)), "l"(__state)
-            : "memory");
-      } else _CCCL_IF_CONSTEXPR (__scope == scope_cluster) {
-        asm("{\n\t .reg .pred P_OUT; \n\t"
-            "mbarrier.try_wait.acquire.cluster.shared::cta.b64         P_OUT, [%1], %2;                        // 6a. "
-            "\n\t"
-            "selp.b32 %0, 1, 0, P_OUT; \n"
-            "}"
-            : "=r"(__waitComplete)
-            : "r"(__as_ptr_smem(__addr)), "l"(__state)
-            : "memory");
-      } return static_cast<bool>(__waitComplete);),
-    (
-      // Unsupported architectures will have a linker error with a semi-decent error message
-      __cuda_ptx_mbarrier_try_wait_is_not_supported_before_SM_90__(); return false;));
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  _CUDA_VSTD::uint32_t __waitComplete;
+  _CCCL_IF_CONSTEXPR (__scope == scope_cta)
+  {
+    asm("{\n\t .reg .pred P_OUT; \n\t"
+        "mbarrier.try_wait.acquire.cta.shared::cta.b64         P_OUT, [%1], %2;                        // 6a. \n\t"
+        "selp.b32 %0, 1, 0, P_OUT; \n"
+        "}"
+        : "=r"(__waitComplete)
+        : "r"(__as_ptr_smem(__addr)), "l"(__state)
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__scope == scope_cluster)
+  {
+    asm("{\n\t .reg .pred P_OUT; \n\t"
+        "mbarrier.try_wait.acquire.cluster.shared::cta.b64         P_OUT, [%1], %2;                        // 6a. \n\t"
+        "selp.b32 %0, 1, 0, P_OUT; \n"
+        "}"
+        : "=r"(__waitComplete)
+        : "r"(__as_ptr_smem(__addr)), "l"(__state)
+        : "memory");
+  }
+  return static_cast<bool>(__waitComplete);
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_mbarrier_try_wait_is_not_supported_before_SM_90__();
+  return false;
+#  endif
 }
 #endif // __cccl_ptx_isa >= 800
 
 /*
-// mbarrier.try_wait{.sem}{.scope}.shared::cta.b64         waitComplete, [addr], state , suspendTimeHint;      // 6b.
-PTX ISA 80, SM_90
+// mbarrier.try_wait.sem.scope.shared::cta.b64         waitComplete, [addr], state , suspendTimeHint;      // 6b.  PTX
+ISA 80, SM_90
 // .sem       = { .acquire }
 // .scope     = { .cta, .cluster }
 template <cuda::ptx::dot_scope Scope>
@@ -132,30 +141,147 @@ _CCCL_DEVICE static inline bool mbarrier_try_wait(
 {
   // __sem == sem_acquire (due to parameter type constraint)
   static_assert(__scope == scope_cta || __scope == scope_cluster, "");
-  NV_IF_ELSE_TARGET(
-    NV_PROVIDES_SM_90,
-    (
-      _CUDA_VSTD::uint32_t __waitComplete; _CCCL_IF_CONSTEXPR (__scope == scope_cta) {
-        asm("{\n\t .reg .pred P_OUT; \n\t"
-            "mbarrier.try_wait.acquire.cta.shared::cta.b64         P_OUT, [%1], %2 , %3;      // 6b. \n\t"
-            "selp.b32 %0, 1, 0, P_OUT; \n"
-            "}"
-            : "=r"(__waitComplete)
-            : "r"(__as_ptr_smem(__addr)), "l"(__state), "r"(__suspendTimeHint)
-            : "memory");
-      } else _CCCL_IF_CONSTEXPR (__scope == scope_cluster) {
-        asm("{\n\t .reg .pred P_OUT; \n\t"
-            "mbarrier.try_wait.acquire.cluster.shared::cta.b64         P_OUT, [%1], %2 , %3;      // 6b. \n\t"
-            "selp.b32 %0, 1, 0, P_OUT; \n"
-            "}"
-            : "=r"(__waitComplete)
-            : "r"(__as_ptr_smem(__addr)), "l"(__state), "r"(__suspendTimeHint)
-            : "memory");
-      } return static_cast<bool>(__waitComplete);),
-    (
-      // Unsupported architectures will have a linker error with a semi-decent error message
-      __cuda_ptx_mbarrier_try_wait_is_not_supported_before_SM_90__(); return false;));
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  _CUDA_VSTD::uint32_t __waitComplete;
+  _CCCL_IF_CONSTEXPR (__scope == scope_cta)
+  {
+    asm("{\n\t .reg .pred P_OUT; \n\t"
+        "mbarrier.try_wait.acquire.cta.shared::cta.b64         P_OUT, [%1], %2 , %3;      // 6b. \n\t"
+        "selp.b32 %0, 1, 0, P_OUT; \n"
+        "}"
+        : "=r"(__waitComplete)
+        : "r"(__as_ptr_smem(__addr)), "l"(__state), "r"(__suspendTimeHint)
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__scope == scope_cluster)
+  {
+    asm("{\n\t .reg .pred P_OUT; \n\t"
+        "mbarrier.try_wait.acquire.cluster.shared::cta.b64         P_OUT, [%1], %2 , %3;      // 6b. \n\t"
+        "selp.b32 %0, 1, 0, P_OUT; \n"
+        "}"
+        : "=r"(__waitComplete)
+        : "r"(__as_ptr_smem(__addr)), "l"(__state), "r"(__suspendTimeHint)
+        : "memory");
+  }
+  return static_cast<bool>(__waitComplete);
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_mbarrier_try_wait_is_not_supported_before_SM_90__();
+  return false;
+#  endif
 }
 #endif // __cccl_ptx_isa >= 800
 
+/*
+// mbarrier.try_wait.sem.scope.shared::cta.b64 waitComplete, [addr], state, suspendTimeHint; // PTX ISA 86, SM_90
+// .sem       = { .relaxed }
+// .scope     = { .cta, .cluster }
+template <cuda::ptx::dot_scope Scope>
+__device__ static inline void mbarrier_try_wait(
+  cuda::ptx::sem_relaxed_t,
+  cuda::ptx::scope_t<Scope> scope,
+  bool waitComplete,
+  uint64_t* addr,
+  const uint64_t& state,
+  const uint32_t& suspendTimeHint);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_mbarrier_try_wait_is_not_supported_before_SM_90__();
+template <dot_scope _Scope>
+_CCCL_DEVICE static inline void mbarrier_try_wait(
+  sem_relaxed_t,
+  scope_t<_Scope> __scope,
+  bool __waitComplete,
+  _CUDA_VSTD::uint64_t* __addr,
+  const _CUDA_VSTD::uint64_t& __state,
+  const _CUDA_VSTD::uint32_t& __suspendTimeHint)
+{
+  // __sem == sem_relaxed (due to parameter type constraint)
+  static_assert(__scope == scope_cta || __scope == scope_cluster, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  _CCCL_IF_CONSTEXPR (__scope == scope_cta)
+  {
+    asm("{\n\t .reg .pred PRED_waitComplete; \n\t"
+        "setp.ne.b32 PRED_waitComplete, %0, 0;\n\t"
+        "mbarrier.try_wait.relaxed.cta.shared::cta.b64 PRED_waitComplete, [%1], %2, %3;\n\t"
+        "}"
+        :
+        : "r"(static_cast<_CUDA_VSTD::uint32_t>(__waitComplete)),
+          "r"(__as_ptr_smem(__addr)),
+          "l"(__state),
+          "r"(__suspendTimeHint)
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__scope == scope_cluster)
+  {
+    asm("{\n\t .reg .pred PRED_waitComplete; \n\t"
+        "setp.ne.b32 PRED_waitComplete, %0, 0;\n\t"
+        "mbarrier.try_wait.relaxed.cluster.shared::cta.b64 PRED_waitComplete, [%1], %2, %3;\n\t"
+        "}"
+        :
+        : "r"(static_cast<_CUDA_VSTD::uint32_t>(__waitComplete)),
+          "r"(__as_ptr_smem(__addr)),
+          "l"(__state),
+          "r"(__suspendTimeHint)
+        : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_mbarrier_try_wait_is_not_supported_before_SM_90__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// mbarrier.try_wait.sem.scope.shared::cta.b64 waitComplete, [addr], state; // PTX ISA 86, SM_90
+// .sem       = { .relaxed }
+// .scope     = { .cta, .cluster }
+template <cuda::ptx::dot_scope Scope>
+__device__ static inline void mbarrier_try_wait(
+  cuda::ptx::sem_relaxed_t,
+  cuda::ptx::scope_t<Scope> scope,
+  bool waitComplete,
+  uint64_t* addr,
+  const uint64_t& state);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_mbarrier_try_wait_is_not_supported_before_SM_90__();
+template <dot_scope _Scope>
+_CCCL_DEVICE static inline void mbarrier_try_wait(
+  sem_relaxed_t,
+  scope_t<_Scope> __scope,
+  bool __waitComplete,
+  _CUDA_VSTD::uint64_t* __addr,
+  const _CUDA_VSTD::uint64_t& __state)
+{
+  // __sem == sem_relaxed (due to parameter type constraint)
+  static_assert(__scope == scope_cta || __scope == scope_cluster, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  _CCCL_IF_CONSTEXPR (__scope == scope_cta)
+  {
+    asm("{\n\t .reg .pred PRED_waitComplete; \n\t"
+        "setp.ne.b32 PRED_waitComplete, %0, 0;\n\t"
+        "mbarrier.try_wait.relaxed.cta.shared::cta.b64 PRED_waitComplete, [%1], %2;\n\t"
+        "}"
+        :
+        : "r"(static_cast<_CUDA_VSTD::uint32_t>(__waitComplete)), "r"(__as_ptr_smem(__addr)), "l"(__state)
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__scope == scope_cluster)
+  {
+    asm("{\n\t .reg .pred PRED_waitComplete; \n\t"
+        "setp.ne.b32 PRED_waitComplete, %0, 0;\n\t"
+        "mbarrier.try_wait.relaxed.cluster.shared::cta.b64 PRED_waitComplete, [%1], %2;\n\t"
+        "}"
+        :
+        : "r"(static_cast<_CUDA_VSTD::uint32_t>(__waitComplete)), "r"(__as_ptr_smem(__addr)), "l"(__state)
+        : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_mbarrier_try_wait_is_not_supported_before_SM_90__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
 #endif // _CUDA_PTX_GENERATED_MBARRIER_TRY_WAIT_H_
diff --git a/libcudacxx/include/cuda/__ptx/instructions/generated/mbarrier_try_wait_parity.h b/libcudacxx/include/cuda/__ptx/instructions/generated/mbarrier_try_wait_parity.h
index aa15e255352..0d6f7d3a9df 100644
--- a/libcudacxx/include/cuda/__ptx/instructions/generated/mbarrier_try_wait_parity.h
+++ b/libcudacxx/include/cuda/__ptx/instructions/generated/mbarrier_try_wait_parity.h
@@ -16,18 +16,21 @@ template <typename = void>
 _CCCL_DEVICE static inline bool
 mbarrier_try_wait_parity(_CUDA_VSTD::uint64_t* __addr, const _CUDA_VSTD::uint32_t& __phaseParity)
 {
-  NV_IF_ELSE_TARGET(
-    NV_PROVIDES_SM_90,
-    (_CUDA_VSTD::uint32_t __waitComplete;
-     asm("{\n\t .reg .pred P_OUT; \n\t"
-         "mbarrier.try_wait.parity.shared::cta.b64  P_OUT, [%1], %2;                                // 7a. \n\t"
-         "selp.b32 %0, 1, 0, P_OUT; \n"
-         "}" : "=r"(__waitComplete) : "r"(__as_ptr_smem(__addr)),
-         "r"(__phaseParity) : "memory");
-     return static_cast<bool>(__waitComplete);),
-    (
-      // Unsupported architectures will have a linker error with a semi-decent error message
-      __cuda_ptx_mbarrier_try_wait_parity_is_not_supported_before_SM_90__(); return false;));
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  _CUDA_VSTD::uint32_t __waitComplete;
+  asm("{\n\t .reg .pred P_OUT; \n\t"
+      "mbarrier.try_wait.parity.shared::cta.b64  P_OUT, [%1], %2;                                // 7a. \n\t"
+      "selp.b32 %0, 1, 0, P_OUT; \n"
+      "}"
+      : "=r"(__waitComplete)
+      : "r"(__as_ptr_smem(__addr)), "r"(__phaseParity)
+      : "memory");
+  return static_cast<bool>(__waitComplete);
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_mbarrier_try_wait_parity_is_not_supported_before_SM_90__();
+  return false;
+#  endif
 }
 #endif // __cccl_ptx_isa >= 780
 
@@ -45,25 +48,27 @@ template <typename = void>
 _CCCL_DEVICE static inline bool mbarrier_try_wait_parity(
   _CUDA_VSTD::uint64_t* __addr, const _CUDA_VSTD::uint32_t& __phaseParity, const _CUDA_VSTD::uint32_t& __suspendTimeHint)
 {
-  NV_IF_ELSE_TARGET(
-    NV_PROVIDES_SM_90,
-    (_CUDA_VSTD::uint32_t __waitComplete;
-     asm("{\n\t .reg .pred P_OUT; \n\t"
-         "mbarrier.try_wait.parity.shared::cta.b64  P_OUT, [%1], %2, %3;               // 7b. \n\t"
-         "selp.b32 %0, 1, 0, P_OUT; \n"
-         "}" : "=r"(__waitComplete) : "r"(__as_ptr_smem(__addr)),
-         "r"(__phaseParity),
-         "r"(__suspendTimeHint) : "memory");
-     return static_cast<bool>(__waitComplete);),
-    (
-      // Unsupported architectures will have a linker error with a semi-decent error message
-      __cuda_ptx_mbarrier_try_wait_parity_is_not_supported_before_SM_90__(); return false;));
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  _CUDA_VSTD::uint32_t __waitComplete;
+  asm("{\n\t .reg .pred P_OUT; \n\t"
+      "mbarrier.try_wait.parity.shared::cta.b64  P_OUT, [%1], %2, %3;               // 7b. \n\t"
+      "selp.b32 %0, 1, 0, P_OUT; \n"
+      "}"
+      : "=r"(__waitComplete)
+      : "r"(__as_ptr_smem(__addr)), "r"(__phaseParity), "r"(__suspendTimeHint)
+      : "memory");
+  return static_cast<bool>(__waitComplete);
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_mbarrier_try_wait_parity_is_not_supported_before_SM_90__();
+  return false;
+#  endif
 }
 #endif // __cccl_ptx_isa >= 780
 
 /*
-// mbarrier.try_wait.parity{.sem}{.scope}.shared::cta.b64  waitComplete, [addr], phaseParity;                  // 8a.
-PTX ISA 80, SM_90
+// mbarrier.try_wait.parity.sem.scope.shared::cta.b64  waitComplete, [addr], phaseParity;                  // 8a.  PTX
+ISA 80, SM_90
 // .sem       = { .acquire }
 // .scope     = { .cta, .cluster }
 template <cuda::ptx::dot_scope Scope>
@@ -81,35 +86,40 @@ _CCCL_DEVICE static inline bool mbarrier_try_wait_parity(
 {
   // __sem == sem_acquire (due to parameter type constraint)
   static_assert(__scope == scope_cta || __scope == scope_cluster, "");
-  NV_IF_ELSE_TARGET(
-    NV_PROVIDES_SM_90,
-    (
-      _CUDA_VSTD::uint32_t __waitComplete; _CCCL_IF_CONSTEXPR (__scope == scope_cta) {
-        asm("{\n\t .reg .pred P_OUT; \n\t"
-            "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64  P_OUT, [%1], %2;                  // 8a. \n\t"
-            "selp.b32 %0, 1, 0, P_OUT; \n"
-            "}"
-            : "=r"(__waitComplete)
-            : "r"(__as_ptr_smem(__addr)), "r"(__phaseParity)
-            : "memory");
-      } else _CCCL_IF_CONSTEXPR (__scope == scope_cluster) {
-        asm("{\n\t .reg .pred P_OUT; \n\t"
-            "mbarrier.try_wait.parity.acquire.cluster.shared::cta.b64  P_OUT, [%1], %2;                  // 8a. \n\t"
-            "selp.b32 %0, 1, 0, P_OUT; \n"
-            "}"
-            : "=r"(__waitComplete)
-            : "r"(__as_ptr_smem(__addr)), "r"(__phaseParity)
-            : "memory");
-      } return static_cast<bool>(__waitComplete);),
-    (
-      // Unsupported architectures will have a linker error with a semi-decent error message
-      __cuda_ptx_mbarrier_try_wait_parity_is_not_supported_before_SM_90__(); return false;));
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  _CUDA_VSTD::uint32_t __waitComplete;
+  _CCCL_IF_CONSTEXPR (__scope == scope_cta)
+  {
+    asm("{\n\t .reg .pred P_OUT; \n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64  P_OUT, [%1], %2;                  // 8a. \n\t"
+        "selp.b32 %0, 1, 0, P_OUT; \n"
+        "}"
+        : "=r"(__waitComplete)
+        : "r"(__as_ptr_smem(__addr)), "r"(__phaseParity)
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__scope == scope_cluster)
+  {
+    asm("{\n\t .reg .pred P_OUT; \n\t"
+        "mbarrier.try_wait.parity.acquire.cluster.shared::cta.b64  P_OUT, [%1], %2;                  // 8a. \n\t"
+        "selp.b32 %0, 1, 0, P_OUT; \n"
+        "}"
+        : "=r"(__waitComplete)
+        : "r"(__as_ptr_smem(__addr)), "r"(__phaseParity)
+        : "memory");
+  }
+  return static_cast<bool>(__waitComplete);
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_mbarrier_try_wait_parity_is_not_supported_before_SM_90__();
+  return false;
+#  endif
 }
 #endif // __cccl_ptx_isa >= 800
 
 /*
-// mbarrier.try_wait.parity{.sem}{.scope}.shared::cta.b64  waitComplete, [addr], phaseParity, suspendTimeHint; // 8b.
-PTX ISA 80, SM_90
+// mbarrier.try_wait.parity.sem.scope.shared::cta.b64  waitComplete, [addr], phaseParity, suspendTimeHint; // 8b.  PTX
+ISA 80, SM_90
 // .sem       = { .acquire }
 // .scope     = { .cta, .cluster }
 template <cuda::ptx::dot_scope Scope>
@@ -132,30 +142,148 @@ _CCCL_DEVICE static inline bool mbarrier_try_wait_parity(
 {
   // __sem == sem_acquire (due to parameter type constraint)
   static_assert(__scope == scope_cta || __scope == scope_cluster, "");
-  NV_IF_ELSE_TARGET(
-    NV_PROVIDES_SM_90,
-    (
-      _CUDA_VSTD::uint32_t __waitComplete; _CCCL_IF_CONSTEXPR (__scope == scope_cta) {
-        asm("{\n\t .reg .pred P_OUT; \n\t"
-            "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64  P_OUT, [%1], %2, %3; // 8b. \n\t"
-            "selp.b32 %0, 1, 0, P_OUT; \n"
-            "}"
-            : "=r"(__waitComplete)
-            : "r"(__as_ptr_smem(__addr)), "r"(__phaseParity), "r"(__suspendTimeHint)
-            : "memory");
-      } else _CCCL_IF_CONSTEXPR (__scope == scope_cluster) {
-        asm("{\n\t .reg .pred P_OUT; \n\t"
-            "mbarrier.try_wait.parity.acquire.cluster.shared::cta.b64  P_OUT, [%1], %2, %3; // 8b. \n\t"
-            "selp.b32 %0, 1, 0, P_OUT; \n"
-            "}"
-            : "=r"(__waitComplete)
-            : "r"(__as_ptr_smem(__addr)), "r"(__phaseParity), "r"(__suspendTimeHint)
-            : "memory");
-      } return static_cast<bool>(__waitComplete);),
-    (
-      // Unsupported architectures will have a linker error with a semi-decent error message
-      __cuda_ptx_mbarrier_try_wait_parity_is_not_supported_before_SM_90__(); return false;));
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  _CUDA_VSTD::uint32_t __waitComplete;
+  _CCCL_IF_CONSTEXPR (__scope == scope_cta)
+  {
+    asm("{\n\t .reg .pred P_OUT; \n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64  P_OUT, [%1], %2, %3; // 8b. \n\t"
+        "selp.b32 %0, 1, 0, P_OUT; \n"
+        "}"
+        : "=r"(__waitComplete)
+        : "r"(__as_ptr_smem(__addr)), "r"(__phaseParity), "r"(__suspendTimeHint)
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__scope == scope_cluster)
+  {
+    asm("{\n\t .reg .pred P_OUT; \n\t"
+        "mbarrier.try_wait.parity.acquire.cluster.shared::cta.b64  P_OUT, [%1], %2, %3; // 8b. \n\t"
+        "selp.b32 %0, 1, 0, P_OUT; \n"
+        "}"
+        : "=r"(__waitComplete)
+        : "r"(__as_ptr_smem(__addr)), "r"(__phaseParity), "r"(__suspendTimeHint)
+        : "memory");
+  }
+  return static_cast<bool>(__waitComplete);
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_mbarrier_try_wait_parity_is_not_supported_before_SM_90__();
+  return false;
+#  endif
 }
 #endif // __cccl_ptx_isa >= 800
 
+/*
+// mbarrier.try_wait.parity.sem.scope.shared::cta.b64 waitComplete, [addr], phaseParity, suspendTimeHint; // PTX ISA 86,
+SM_90
+// .sem       = { .relaxed }
+// .scope     = { .cta, .cluster }
+template <cuda::ptx::dot_scope Scope>
+__device__ static inline void mbarrier_try_wait_parity(
+  cuda::ptx::sem_relaxed_t,
+  cuda::ptx::scope_t<Scope> scope,
+  bool waitComplete,
+  uint64_t* addr,
+  const uint32_t& phaseParity,
+  const uint32_t& suspendTimeHint);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_mbarrier_try_wait_parity_is_not_supported_before_SM_90__();
+template <dot_scope _Scope>
+_CCCL_DEVICE static inline void mbarrier_try_wait_parity(
+  sem_relaxed_t,
+  scope_t<_Scope> __scope,
+  bool __waitComplete,
+  _CUDA_VSTD::uint64_t* __addr,
+  const _CUDA_VSTD::uint32_t& __phaseParity,
+  const _CUDA_VSTD::uint32_t& __suspendTimeHint)
+{
+  // __sem == sem_relaxed (due to parameter type constraint)
+  static_assert(__scope == scope_cta || __scope == scope_cluster, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  _CCCL_IF_CONSTEXPR (__scope == scope_cta)
+  {
+    asm("{\n\t .reg .pred PRED_waitComplete; \n\t"
+        "setp.ne.b32 PRED_waitComplete, %0, 0;\n\t"
+        "mbarrier.try_wait.parity.relaxed.cta.shared::cta.b64 PRED_waitComplete, [%1], %2, %3;\n\t"
+        "}"
+        :
+        : "r"(static_cast<_CUDA_VSTD::uint32_t>(__waitComplete)),
+          "r"(__as_ptr_smem(__addr)),
+          "r"(__phaseParity),
+          "r"(__suspendTimeHint)
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__scope == scope_cluster)
+  {
+    asm("{\n\t .reg .pred PRED_waitComplete; \n\t"
+        "setp.ne.b32 PRED_waitComplete, %0, 0;\n\t"
+        "mbarrier.try_wait.parity.relaxed.cluster.shared::cta.b64 PRED_waitComplete, [%1], %2, %3;\n\t"
+        "}"
+        :
+        : "r"(static_cast<_CUDA_VSTD::uint32_t>(__waitComplete)),
+          "r"(__as_ptr_smem(__addr)),
+          "r"(__phaseParity),
+          "r"(__suspendTimeHint)
+        : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_mbarrier_try_wait_parity_is_not_supported_before_SM_90__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// mbarrier.try_wait.parity.sem.scope.shared::cta.b64 waitComplete, [addr], phaseParity; // PTX ISA 86, SM_90
+// .sem       = { .relaxed }
+// .scope     = { .cta, .cluster }
+template <cuda::ptx::dot_scope Scope>
+__device__ static inline void mbarrier_try_wait_parity(
+  cuda::ptx::sem_relaxed_t,
+  cuda::ptx::scope_t<Scope> scope,
+  bool waitComplete,
+  uint64_t* addr,
+  const uint32_t& phaseParity);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_mbarrier_try_wait_parity_is_not_supported_before_SM_90__();
+template <dot_scope _Scope>
+_CCCL_DEVICE static inline void mbarrier_try_wait_parity(
+  sem_relaxed_t,
+  scope_t<_Scope> __scope,
+  bool __waitComplete,
+  _CUDA_VSTD::uint64_t* __addr,
+  const _CUDA_VSTD::uint32_t& __phaseParity)
+{
+  // __sem == sem_relaxed (due to parameter type constraint)
+  static_assert(__scope == scope_cta || __scope == scope_cluster, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  _CCCL_IF_CONSTEXPR (__scope == scope_cta)
+  {
+    asm("{\n\t .reg .pred PRED_waitComplete; \n\t"
+        "setp.ne.b32 PRED_waitComplete, %0, 0;\n\t"
+        "mbarrier.try_wait.parity.relaxed.cta.shared::cta.b64 PRED_waitComplete, [%1], %2;\n\t"
+        "}"
+        :
+        : "r"(static_cast<_CUDA_VSTD::uint32_t>(__waitComplete)), "r"(__as_ptr_smem(__addr)), "r"(__phaseParity)
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__scope == scope_cluster)
+  {
+    asm("{\n\t .reg .pred PRED_waitComplete; \n\t"
+        "setp.ne.b32 PRED_waitComplete, %0, 0;\n\t"
+        "mbarrier.try_wait.parity.relaxed.cluster.shared::cta.b64 PRED_waitComplete, [%1], %2;\n\t"
+        "}"
+        :
+        : "r"(static_cast<_CUDA_VSTD::uint32_t>(__waitComplete)), "r"(__as_ptr_smem(__addr)), "r"(__phaseParity)
+        : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_mbarrier_try_wait_parity_is_not_supported_before_SM_90__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
 #endif // _CUDA_PTX_GENERATED_MBARRIER_TRY_WAIT_PARITY_H_
diff --git a/libcudacxx/include/cuda/__ptx/instructions/generated/multimem_ld_reduce.h b/libcudacxx/include/cuda/__ptx/instructions/generated/multimem_ld_reduce.h
new file mode 100644
index 00000000000..51de5257bba
--- /dev/null
+++ b/libcudacxx/include/cuda/__ptx/instructions/generated/multimem_ld_reduce.h
@@ -0,0 +1,2148 @@
+// This file was automatically generated. Do not edit.
+
+#ifndef _CUDA_PTX_GENERATED_MULTIMEM_LD_REDUCE_H_
+#define _CUDA_PTX_GENERATED_MULTIMEM_LD_REDUCE_H_
+
+/*
+// multimem.ld_reduce.sem.global.op.u32 dest, [addr]; // PTX ISA 81, SM_90
+// .sem       = { .weak }
+// .op        = { .min }
+template <typename = void>
+__device__ static inline uint32_t multimem_ld_reduce(
+  cuda::ptx::sem_weak_t,
+  cuda::ptx::op_min_t,
+  const uint32_t* addr);
+*/
+#if __cccl_ptx_isa >= 810
+extern "C" _CCCL_DEVICE void __cuda_ptx_multimem_ld_reduce_is_not_supported_before_SM_90__();
+template <typename = void>
+_CCCL_DEVICE static inline _CUDA_VSTD::uint32_t
+multimem_ld_reduce(sem_weak_t, op_min_t, const _CUDA_VSTD::uint32_t* __addr)
+{
+// __sem == sem_weak (due to parameter type constraint)
+// __op == op_min (due to parameter type constraint)
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  _CUDA_VSTD::uint32_t __dest;
+  asm("multimem.ld_reduce.weak.global.min.u32 %0, [%1];" : "=r"(__dest) : "l"(__as_ptr_gmem(__addr)) : "memory");
+  return __dest;
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_multimem_ld_reduce_is_not_supported_before_SM_90__();
+  return 0;
+#  endif
+}
+#endif // __cccl_ptx_isa >= 810
+
+/*
+// multimem.ld_reduce.sem.scope.global.op.u32 dest, [addr]; // PTX ISA 81, SM_90
+// .sem       = { .relaxed, .acquire }
+// .scope     = { .cta, .cluster, .gpu, .sys }
+// .op        = { .min }
+template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+__device__ static inline uint32_t multimem_ld_reduce(
+  cuda::ptx::sem_t<Sem> sem,
+  cuda::ptx::scope_t<Scope> scope,
+  cuda::ptx::op_min_t,
+  const uint32_t* addr);
+*/
+#if __cccl_ptx_isa >= 810
+extern "C" _CCCL_DEVICE void __cuda_ptx_multimem_ld_reduce_is_not_supported_before_SM_90__();
+template <dot_sem _Sem, dot_scope _Scope>
+_CCCL_DEVICE static inline _CUDA_VSTD::uint32_t
+multimem_ld_reduce(sem_t<_Sem> __sem, scope_t<_Scope> __scope, op_min_t, const _CUDA_VSTD::uint32_t* __addr)
+{
+  static_assert(__sem == sem_relaxed || __sem == sem_acquire, "");
+  static_assert(__scope == scope_cta || __scope == scope_cluster || __scope == scope_gpu || __scope == scope_sys, "");
+// __op == op_min (due to parameter type constraint)
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  _CUDA_VSTD::uint32_t __dest;
+  _CCCL_IF_CONSTEXPR (__sem == sem_relaxed && __scope == scope_cta)
+  {
+    asm("multimem.ld_reduce.relaxed.cta.global.min.u32 %0, [%1];"
+        : "=r"(__dest)
+        : "l"(__as_ptr_gmem(__addr))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_relaxed && __scope == scope_cluster)
+  {
+    asm("multimem.ld_reduce.relaxed.cluster.global.min.u32 %0, [%1];"
+        : "=r"(__dest)
+        : "l"(__as_ptr_gmem(__addr))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_relaxed && __scope == scope_gpu)
+  {
+    asm("multimem.ld_reduce.relaxed.gpu.global.min.u32 %0, [%1];"
+        : "=r"(__dest)
+        : "l"(__as_ptr_gmem(__addr))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_relaxed && __scope == scope_sys)
+  {
+    asm("multimem.ld_reduce.relaxed.sys.global.min.u32 %0, [%1];"
+        : "=r"(__dest)
+        : "l"(__as_ptr_gmem(__addr))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_acquire && __scope == scope_cta)
+  {
+    asm("multimem.ld_reduce.acquire.cta.global.min.u32 %0, [%1];"
+        : "=r"(__dest)
+        : "l"(__as_ptr_gmem(__addr))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_acquire && __scope == scope_cluster)
+  {
+    asm("multimem.ld_reduce.acquire.cluster.global.min.u32 %0, [%1];"
+        : "=r"(__dest)
+        : "l"(__as_ptr_gmem(__addr))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_acquire && __scope == scope_gpu)
+  {
+    asm("multimem.ld_reduce.acquire.gpu.global.min.u32 %0, [%1];"
+        : "=r"(__dest)
+        : "l"(__as_ptr_gmem(__addr))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_acquire && __scope == scope_sys)
+  {
+    asm("multimem.ld_reduce.acquire.sys.global.min.u32 %0, [%1];"
+        : "=r"(__dest)
+        : "l"(__as_ptr_gmem(__addr))
+        : "memory");
+  }
+  return __dest;
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_multimem_ld_reduce_is_not_supported_before_SM_90__();
+  return 0;
+#  endif
+}
+#endif // __cccl_ptx_isa >= 810
+
+/*
+// multimem.ld_reduce.sem.global.op.u64 dest, [addr]; // PTX ISA 81, SM_90
+// .sem       = { .weak }
+// .op        = { .min }
+template <typename = void>
+__device__ static inline uint64_t multimem_ld_reduce(
+  cuda::ptx::sem_weak_t,
+  cuda::ptx::op_min_t,
+  const uint64_t* addr);
+*/
+#if __cccl_ptx_isa >= 810
+extern "C" _CCCL_DEVICE void __cuda_ptx_multimem_ld_reduce_is_not_supported_before_SM_90__();
+template <typename = void>
+_CCCL_DEVICE static inline _CUDA_VSTD::uint64_t
+multimem_ld_reduce(sem_weak_t, op_min_t, const _CUDA_VSTD::uint64_t* __addr)
+{
+// __sem == sem_weak (due to parameter type constraint)
+// __op == op_min (due to parameter type constraint)
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  _CUDA_VSTD::uint64_t __dest;
+  asm("multimem.ld_reduce.weak.global.min.u64 %0, [%1];" : "=l"(__dest) : "l"(__as_ptr_gmem(__addr)) : "memory");
+  return __dest;
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_multimem_ld_reduce_is_not_supported_before_SM_90__();
+  return 0;
+#  endif
+}
+#endif // __cccl_ptx_isa >= 810
+
+/*
+// multimem.ld_reduce.sem.scope.global.op.u64 dest, [addr]; // PTX ISA 81, SM_90
+// .sem       = { .relaxed, .acquire }
+// .scope     = { .cta, .cluster, .gpu, .sys }
+// .op        = { .min }
+template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+__device__ static inline uint64_t multimem_ld_reduce(
+  cuda::ptx::sem_t<Sem> sem,
+  cuda::ptx::scope_t<Scope> scope,
+  cuda::ptx::op_min_t,
+  const uint64_t* addr);
+*/
+#if __cccl_ptx_isa >= 810
+extern "C" _CCCL_DEVICE void __cuda_ptx_multimem_ld_reduce_is_not_supported_before_SM_90__();
+template <dot_sem _Sem, dot_scope _Scope>
+_CCCL_DEVICE static inline _CUDA_VSTD::uint64_t
+multimem_ld_reduce(sem_t<_Sem> __sem, scope_t<_Scope> __scope, op_min_t, const _CUDA_VSTD::uint64_t* __addr)
+{
+  static_assert(__sem == sem_relaxed || __sem == sem_acquire, "");
+  static_assert(__scope == scope_cta || __scope == scope_cluster || __scope == scope_gpu || __scope == scope_sys, "");
+// __op == op_min (due to parameter type constraint)
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  _CUDA_VSTD::uint64_t __dest;
+  _CCCL_IF_CONSTEXPR (__sem == sem_relaxed && __scope == scope_cta)
+  {
+    asm("multimem.ld_reduce.relaxed.cta.global.min.u64 %0, [%1];"
+        : "=l"(__dest)
+        : "l"(__as_ptr_gmem(__addr))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_relaxed && __scope == scope_cluster)
+  {
+    asm("multimem.ld_reduce.relaxed.cluster.global.min.u64 %0, [%1];"
+        : "=l"(__dest)
+        : "l"(__as_ptr_gmem(__addr))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_relaxed && __scope == scope_gpu)
+  {
+    asm("multimem.ld_reduce.relaxed.gpu.global.min.u64 %0, [%1];"
+        : "=l"(__dest)
+        : "l"(__as_ptr_gmem(__addr))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_relaxed && __scope == scope_sys)
+  {
+    asm("multimem.ld_reduce.relaxed.sys.global.min.u64 %0, [%1];"
+        : "=l"(__dest)
+        : "l"(__as_ptr_gmem(__addr))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_acquire && __scope == scope_cta)
+  {
+    asm("multimem.ld_reduce.acquire.cta.global.min.u64 %0, [%1];"
+        : "=l"(__dest)
+        : "l"(__as_ptr_gmem(__addr))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_acquire && __scope == scope_cluster)
+  {
+    asm("multimem.ld_reduce.acquire.cluster.global.min.u64 %0, [%1];"
+        : "=l"(__dest)
+        : "l"(__as_ptr_gmem(__addr))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_acquire && __scope == scope_gpu)
+  {
+    asm("multimem.ld_reduce.acquire.gpu.global.min.u64 %0, [%1];"
+        : "=l"(__dest)
+        : "l"(__as_ptr_gmem(__addr))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_acquire && __scope == scope_sys)
+  {
+    asm("multimem.ld_reduce.acquire.sys.global.min.u64 %0, [%1];"
+        : "=l"(__dest)
+        : "l"(__as_ptr_gmem(__addr))
+        : "memory");
+  }
+  return __dest;
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_multimem_ld_reduce_is_not_supported_before_SM_90__();
+  return 0;
+#  endif
+}
+#endif // __cccl_ptx_isa >= 810
+
+/*
+// multimem.ld_reduce.sem.global.op.s32 dest, [addr]; // PTX ISA 81, SM_90
+// .sem       = { .weak }
+// .op        = { .min }
+template <typename = void>
+__device__ static inline int32_t multimem_ld_reduce(
+  cuda::ptx::sem_weak_t,
+  cuda::ptx::op_min_t,
+  const int32_t* addr);
+*/
+#if __cccl_ptx_isa >= 810
+extern "C" _CCCL_DEVICE void __cuda_ptx_multimem_ld_reduce_is_not_supported_before_SM_90__();
+template <typename = void>
+_CCCL_DEVICE static inline _CUDA_VSTD::int32_t
+multimem_ld_reduce(sem_weak_t, op_min_t, const _CUDA_VSTD::int32_t* __addr)
+{
+// __sem == sem_weak (due to parameter type constraint)
+// __op == op_min (due to parameter type constraint)
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  _CUDA_VSTD::int32_t __dest;
+  asm("multimem.ld_reduce.weak.global.min.s32 %0, [%1];" : "=r"(__dest) : "l"(__as_ptr_gmem(__addr)) : "memory");
+  return __dest;
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_multimem_ld_reduce_is_not_supported_before_SM_90__();
+  return 0;
+#  endif
+}
+#endif // __cccl_ptx_isa >= 810
+
+/*
+// multimem.ld_reduce.sem.scope.global.op.s32 dest, [addr]; // PTX ISA 81, SM_90
+// .sem       = { .relaxed, .acquire }
+// .scope     = { .cta, .cluster, .gpu, .sys }
+// .op        = { .min }
+template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+__device__ static inline int32_t multimem_ld_reduce(
+  cuda::ptx::sem_t<Sem> sem,
+  cuda::ptx::scope_t<Scope> scope,
+  cuda::ptx::op_min_t,
+  const int32_t* addr);
+*/
+#if __cccl_ptx_isa >= 810
+extern "C" _CCCL_DEVICE void __cuda_ptx_multimem_ld_reduce_is_not_supported_before_SM_90__();
+template <dot_sem _Sem, dot_scope _Scope>
+_CCCL_DEVICE static inline _CUDA_VSTD::int32_t
+multimem_ld_reduce(sem_t<_Sem> __sem, scope_t<_Scope> __scope, op_min_t, const _CUDA_VSTD::int32_t* __addr)
+{
+  static_assert(__sem == sem_relaxed || __sem == sem_acquire, "");
+  static_assert(__scope == scope_cta || __scope == scope_cluster || __scope == scope_gpu || __scope == scope_sys, "");
+// __op == op_min (due to parameter type constraint)
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  _CUDA_VSTD::int32_t __dest;
+  _CCCL_IF_CONSTEXPR (__sem == sem_relaxed && __scope == scope_cta)
+  {
+    asm("multimem.ld_reduce.relaxed.cta.global.min.s32 %0, [%1];"
+        : "=r"(__dest)
+        : "l"(__as_ptr_gmem(__addr))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_relaxed && __scope == scope_cluster)
+  {
+    asm("multimem.ld_reduce.relaxed.cluster.global.min.s32 %0, [%1];"
+        : "=r"(__dest)
+        : "l"(__as_ptr_gmem(__addr))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_relaxed && __scope == scope_gpu)
+  {
+    asm("multimem.ld_reduce.relaxed.gpu.global.min.s32 %0, [%1];"
+        : "=r"(__dest)
+        : "l"(__as_ptr_gmem(__addr))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_relaxed && __scope == scope_sys)
+  {
+    asm("multimem.ld_reduce.relaxed.sys.global.min.s32 %0, [%1];"
+        : "=r"(__dest)
+        : "l"(__as_ptr_gmem(__addr))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_acquire && __scope == scope_cta)
+  {
+    asm("multimem.ld_reduce.acquire.cta.global.min.s32 %0, [%1];"
+        : "=r"(__dest)
+        : "l"(__as_ptr_gmem(__addr))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_acquire && __scope == scope_cluster)
+  {
+    asm("multimem.ld_reduce.acquire.cluster.global.min.s32 %0, [%1];"
+        : "=r"(__dest)
+        : "l"(__as_ptr_gmem(__addr))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_acquire && __scope == scope_gpu)
+  {
+    asm("multimem.ld_reduce.acquire.gpu.global.min.s32 %0, [%1];"
+        : "=r"(__dest)
+        : "l"(__as_ptr_gmem(__addr))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_acquire && __scope == scope_sys)
+  {
+    asm("multimem.ld_reduce.acquire.sys.global.min.s32 %0, [%1];"
+        : "=r"(__dest)
+        : "l"(__as_ptr_gmem(__addr))
+        : "memory");
+  }
+  return __dest;
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_multimem_ld_reduce_is_not_supported_before_SM_90__();
+  return 0;
+#  endif
+}
+#endif // __cccl_ptx_isa >= 810
+
+/*
+// multimem.ld_reduce.sem.global.op.s64 dest, [addr]; // PTX ISA 81, SM_90
+// .sem       = { .weak }
+// .op        = { .min }
+template <typename = void>
+__device__ static inline int64_t multimem_ld_reduce(
+  cuda::ptx::sem_weak_t,
+  cuda::ptx::op_min_t,
+  const int64_t* addr);
+*/
+#if __cccl_ptx_isa >= 810
+extern "C" _CCCL_DEVICE void __cuda_ptx_multimem_ld_reduce_is_not_supported_before_SM_90__();
+template <typename = void>
+_CCCL_DEVICE static inline _CUDA_VSTD::int64_t
+multimem_ld_reduce(sem_weak_t, op_min_t, const _CUDA_VSTD::int64_t* __addr)
+{
+// __sem == sem_weak (due to parameter type constraint)
+// __op == op_min (due to parameter type constraint)
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  _CUDA_VSTD::int64_t __dest;
+  asm("multimem.ld_reduce.weak.global.min.s64 %0, [%1];" : "=l"(__dest) : "l"(__as_ptr_gmem(__addr)) : "memory");
+  return __dest;
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_multimem_ld_reduce_is_not_supported_before_SM_90__();
+  return 0;
+#  endif
+}
+#endif // __cccl_ptx_isa >= 810
+
+/*
+// multimem.ld_reduce.sem.scope.global.op.s64 dest, [addr]; // PTX ISA 81, SM_90
+// .sem       = { .relaxed, .acquire }
+// .scope     = { .cta, .cluster, .gpu, .sys }
+// .op        = { .min }
+template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+__device__ static inline int64_t multimem_ld_reduce(
+  cuda::ptx::sem_t<Sem> sem,
+  cuda::ptx::scope_t<Scope> scope,
+  cuda::ptx::op_min_t,
+  const int64_t* addr);
+*/
+#if __cccl_ptx_isa >= 810
+extern "C" _CCCL_DEVICE void __cuda_ptx_multimem_ld_reduce_is_not_supported_before_SM_90__();
+template <dot_sem _Sem, dot_scope _Scope>
+_CCCL_DEVICE static inline _CUDA_VSTD::int64_t
+multimem_ld_reduce(sem_t<_Sem> __sem, scope_t<_Scope> __scope, op_min_t, const _CUDA_VSTD::int64_t* __addr)
+{
+  static_assert(__sem == sem_relaxed || __sem == sem_acquire, "");
+  static_assert(__scope == scope_cta || __scope == scope_cluster || __scope == scope_gpu || __scope == scope_sys, "");
+// __op == op_min (due to parameter type constraint)
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  _CUDA_VSTD::int64_t __dest;
+  _CCCL_IF_CONSTEXPR (__sem == sem_relaxed && __scope == scope_cta)
+  {
+    asm("multimem.ld_reduce.relaxed.cta.global.min.s64 %0, [%1];"
+        : "=l"(__dest)
+        : "l"(__as_ptr_gmem(__addr))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_relaxed && __scope == scope_cluster)
+  {
+    asm("multimem.ld_reduce.relaxed.cluster.global.min.s64 %0, [%1];"
+        : "=l"(__dest)
+        : "l"(__as_ptr_gmem(__addr))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_relaxed && __scope == scope_gpu)
+  {
+    asm("multimem.ld_reduce.relaxed.gpu.global.min.s64 %0, [%1];"
+        : "=l"(__dest)
+        : "l"(__as_ptr_gmem(__addr))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_relaxed && __scope == scope_sys)
+  {
+    asm("multimem.ld_reduce.relaxed.sys.global.min.s64 %0, [%1];"
+        : "=l"(__dest)
+        : "l"(__as_ptr_gmem(__addr))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_acquire && __scope == scope_cta)
+  {
+    asm("multimem.ld_reduce.acquire.cta.global.min.s64 %0, [%1];"
+        : "=l"(__dest)
+        : "l"(__as_ptr_gmem(__addr))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_acquire && __scope == scope_cluster)
+  {
+    asm("multimem.ld_reduce.acquire.cluster.global.min.s64 %0, [%1];"
+        : "=l"(__dest)
+        : "l"(__as_ptr_gmem(__addr))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_acquire && __scope == scope_gpu)
+  {
+    asm("multimem.ld_reduce.acquire.gpu.global.min.s64 %0, [%1];"
+        : "=l"(__dest)
+        : "l"(__as_ptr_gmem(__addr))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_acquire && __scope == scope_sys)
+  {
+    asm("multimem.ld_reduce.acquire.sys.global.min.s64 %0, [%1];"
+        : "=l"(__dest)
+        : "l"(__as_ptr_gmem(__addr))
+        : "memory");
+  }
+  return __dest;
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_multimem_ld_reduce_is_not_supported_before_SM_90__();
+  return 0;
+#  endif
+}
+#endif // __cccl_ptx_isa >= 810
+
+/*
+// multimem.ld_reduce.sem.global.op.u32 dest, [addr]; // PTX ISA 81, SM_90
+// .sem       = { .weak }
+// .op        = { .max }
+template <typename = void>
+__device__ static inline uint32_t multimem_ld_reduce(
+  cuda::ptx::sem_weak_t,
+  cuda::ptx::op_max_t,
+  const uint32_t* addr);
+*/
+#if __cccl_ptx_isa >= 810
+extern "C" _CCCL_DEVICE void __cuda_ptx_multimem_ld_reduce_is_not_supported_before_SM_90__();
+template <typename = void>
+_CCCL_DEVICE static inline _CUDA_VSTD::uint32_t
+multimem_ld_reduce(sem_weak_t, op_max_t, const _CUDA_VSTD::uint32_t* __addr)
+{
+// __sem == sem_weak (due to parameter type constraint)
+// __op == op_max (due to parameter type constraint)
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  _CUDA_VSTD::uint32_t __dest;
+  asm("multimem.ld_reduce.weak.global.max.u32 %0, [%1];" : "=r"(__dest) : "l"(__as_ptr_gmem(__addr)) : "memory");
+  return __dest;
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_multimem_ld_reduce_is_not_supported_before_SM_90__();
+  return 0;
+#  endif
+}
+#endif // __cccl_ptx_isa >= 810
+
+/*
+// multimem.ld_reduce.sem.scope.global.op.u32 dest, [addr]; // PTX ISA 81, SM_90
+// .sem       = { .relaxed, .acquire }
+// .scope     = { .cta, .cluster, .gpu, .sys }
+// .op        = { .max }
+template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+__device__ static inline uint32_t multimem_ld_reduce(
+  cuda::ptx::sem_t<Sem> sem,
+  cuda::ptx::scope_t<Scope> scope,
+  cuda::ptx::op_max_t,
+  const uint32_t* addr);
+*/
+#if __cccl_ptx_isa >= 810
+extern "C" _CCCL_DEVICE void __cuda_ptx_multimem_ld_reduce_is_not_supported_before_SM_90__();
+template <dot_sem _Sem, dot_scope _Scope>
+_CCCL_DEVICE static inline _CUDA_VSTD::uint32_t
+multimem_ld_reduce(sem_t<_Sem> __sem, scope_t<_Scope> __scope, op_max_t, const _CUDA_VSTD::uint32_t* __addr)
+{
+  static_assert(__sem == sem_relaxed || __sem == sem_acquire, "");
+  static_assert(__scope == scope_cta || __scope == scope_cluster || __scope == scope_gpu || __scope == scope_sys, "");
+// __op == op_max (due to parameter type constraint)
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  _CUDA_VSTD::uint32_t __dest;
+  _CCCL_IF_CONSTEXPR (__sem == sem_relaxed && __scope == scope_cta)
+  {
+    asm("multimem.ld_reduce.relaxed.cta.global.max.u32 %0, [%1];"
+        : "=r"(__dest)
+        : "l"(__as_ptr_gmem(__addr))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_relaxed && __scope == scope_cluster)
+  {
+    asm("multimem.ld_reduce.relaxed.cluster.global.max.u32 %0, [%1];"
+        : "=r"(__dest)
+        : "l"(__as_ptr_gmem(__addr))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_relaxed && __scope == scope_gpu)
+  {
+    asm("multimem.ld_reduce.relaxed.gpu.global.max.u32 %0, [%1];"
+        : "=r"(__dest)
+        : "l"(__as_ptr_gmem(__addr))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_relaxed && __scope == scope_sys)
+  {
+    asm("multimem.ld_reduce.relaxed.sys.global.max.u32 %0, [%1];"
+        : "=r"(__dest)
+        : "l"(__as_ptr_gmem(__addr))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_acquire && __scope == scope_cta)
+  {
+    asm("multimem.ld_reduce.acquire.cta.global.max.u32 %0, [%1];"
+        : "=r"(__dest)
+        : "l"(__as_ptr_gmem(__addr))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_acquire && __scope == scope_cluster)
+  {
+    asm("multimem.ld_reduce.acquire.cluster.global.max.u32 %0, [%1];"
+        : "=r"(__dest)
+        : "l"(__as_ptr_gmem(__addr))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_acquire && __scope == scope_gpu)
+  {
+    asm("multimem.ld_reduce.acquire.gpu.global.max.u32 %0, [%1];"
+        : "=r"(__dest)
+        : "l"(__as_ptr_gmem(__addr))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_acquire && __scope == scope_sys)
+  {
+    asm("multimem.ld_reduce.acquire.sys.global.max.u32 %0, [%1];"
+        : "=r"(__dest)
+        : "l"(__as_ptr_gmem(__addr))
+        : "memory");
+  }
+  return __dest;
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_multimem_ld_reduce_is_not_supported_before_SM_90__();
+  return 0;
+#  endif
+}
+#endif // __cccl_ptx_isa >= 810
+
+/*
+// multimem.ld_reduce.sem.global.op.u64 dest, [addr]; // PTX ISA 81, SM_90
+// .sem       = { .weak }
+// .op        = { .max }
+template <typename = void>
+__device__ static inline uint64_t multimem_ld_reduce(
+  cuda::ptx::sem_weak_t,
+  cuda::ptx::op_max_t,
+  const uint64_t* addr);
+*/
+#if __cccl_ptx_isa >= 810
+extern "C" _CCCL_DEVICE void __cuda_ptx_multimem_ld_reduce_is_not_supported_before_SM_90__();
+template <typename = void>
+_CCCL_DEVICE static inline _CUDA_VSTD::uint64_t
+multimem_ld_reduce(sem_weak_t, op_max_t, const _CUDA_VSTD::uint64_t* __addr)
+{
+// __sem == sem_weak (due to parameter type constraint)
+// __op == op_max (due to parameter type constraint)
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  _CUDA_VSTD::uint64_t __dest;
+  asm("multimem.ld_reduce.weak.global.max.u64 %0, [%1];" : "=l"(__dest) : "l"(__as_ptr_gmem(__addr)) : "memory");
+  return __dest;
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_multimem_ld_reduce_is_not_supported_before_SM_90__();
+  return 0;
+#  endif
+}
+#endif // __cccl_ptx_isa >= 810
+
+/*
+// multimem.ld_reduce.sem.scope.global.op.u64 dest, [addr]; // PTX ISA 81, SM_90
+// .sem       = { .relaxed, .acquire }
+// .scope     = { .cta, .cluster, .gpu, .sys }
+// .op        = { .max }
+template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+__device__ static inline uint64_t multimem_ld_reduce(
+  cuda::ptx::sem_t<Sem> sem,
+  cuda::ptx::scope_t<Scope> scope,
+  cuda::ptx::op_max_t,
+  const uint64_t* addr);
+*/
+#if __cccl_ptx_isa >= 810
+extern "C" _CCCL_DEVICE void __cuda_ptx_multimem_ld_reduce_is_not_supported_before_SM_90__();
+template <dot_sem _Sem, dot_scope _Scope>
+_CCCL_DEVICE static inline _CUDA_VSTD::uint64_t
+multimem_ld_reduce(sem_t<_Sem> __sem, scope_t<_Scope> __scope, op_max_t, const _CUDA_VSTD::uint64_t* __addr)
+{
+  static_assert(__sem == sem_relaxed || __sem == sem_acquire, "");
+  static_assert(__scope == scope_cta || __scope == scope_cluster || __scope == scope_gpu || __scope == scope_sys, "");
+// __op == op_max (due to parameter type constraint)
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  _CUDA_VSTD::uint64_t __dest;
+  _CCCL_IF_CONSTEXPR (__sem == sem_relaxed && __scope == scope_cta)
+  {
+    asm("multimem.ld_reduce.relaxed.cta.global.max.u64 %0, [%1];"
+        : "=l"(__dest)
+        : "l"(__as_ptr_gmem(__addr))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_relaxed && __scope == scope_cluster)
+  {
+    asm("multimem.ld_reduce.relaxed.cluster.global.max.u64 %0, [%1];"
+        : "=l"(__dest)
+        : "l"(__as_ptr_gmem(__addr))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_relaxed && __scope == scope_gpu)
+  {
+    asm("multimem.ld_reduce.relaxed.gpu.global.max.u64 %0, [%1];"
+        : "=l"(__dest)
+        : "l"(__as_ptr_gmem(__addr))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_relaxed && __scope == scope_sys)
+  {
+    asm("multimem.ld_reduce.relaxed.sys.global.max.u64 %0, [%1];"
+        : "=l"(__dest)
+        : "l"(__as_ptr_gmem(__addr))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_acquire && __scope == scope_cta)
+  {
+    asm("multimem.ld_reduce.acquire.cta.global.max.u64 %0, [%1];"
+        : "=l"(__dest)
+        : "l"(__as_ptr_gmem(__addr))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_acquire && __scope == scope_cluster)
+  {
+    asm("multimem.ld_reduce.acquire.cluster.global.max.u64 %0, [%1];"
+        : "=l"(__dest)
+        : "l"(__as_ptr_gmem(__addr))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_acquire && __scope == scope_gpu)
+  {
+    asm("multimem.ld_reduce.acquire.gpu.global.max.u64 %0, [%1];"
+        : "=l"(__dest)
+        : "l"(__as_ptr_gmem(__addr))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_acquire && __scope == scope_sys)
+  {
+    asm("multimem.ld_reduce.acquire.sys.global.max.u64 %0, [%1];"
+        : "=l"(__dest)
+        : "l"(__as_ptr_gmem(__addr))
+        : "memory");
+  }
+  return __dest;
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_multimem_ld_reduce_is_not_supported_before_SM_90__();
+  return 0;
+#  endif
+}
+#endif // __cccl_ptx_isa >= 810
+
+/*
+// multimem.ld_reduce.sem.global.op.s32 dest, [addr]; // PTX ISA 81, SM_90
+// .sem       = { .weak }
+// .op        = { .max }
+template <typename = void>
+__device__ static inline int32_t multimem_ld_reduce(
+  cuda::ptx::sem_weak_t,
+  cuda::ptx::op_max_t,
+  const int32_t* addr);
+*/
+#if __cccl_ptx_isa >= 810
+extern "C" _CCCL_DEVICE void __cuda_ptx_multimem_ld_reduce_is_not_supported_before_SM_90__();
+template <typename = void>
+_CCCL_DEVICE static inline _CUDA_VSTD::int32_t
+multimem_ld_reduce(sem_weak_t, op_max_t, const _CUDA_VSTD::int32_t* __addr)
+{
+// __sem == sem_weak (due to parameter type constraint)
+// __op == op_max (due to parameter type constraint)
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  _CUDA_VSTD::int32_t __dest;
+  asm("multimem.ld_reduce.weak.global.max.s32 %0, [%1];" : "=r"(__dest) : "l"(__as_ptr_gmem(__addr)) : "memory");
+  return __dest;
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_multimem_ld_reduce_is_not_supported_before_SM_90__();
+  return 0;
+#  endif
+}
+#endif // __cccl_ptx_isa >= 810
+
+/*
+// multimem.ld_reduce.sem.scope.global.op.s32 dest, [addr]; // PTX ISA 81, SM_90
+// .sem       = { .relaxed, .acquire }
+// .scope     = { .cta, .cluster, .gpu, .sys }
+// .op        = { .max }
+template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+__device__ static inline int32_t multimem_ld_reduce(
+  cuda::ptx::sem_t<Sem> sem,
+  cuda::ptx::scope_t<Scope> scope,
+  cuda::ptx::op_max_t,
+  const int32_t* addr);
+*/
+#if __cccl_ptx_isa >= 810
+extern "C" _CCCL_DEVICE void __cuda_ptx_multimem_ld_reduce_is_not_supported_before_SM_90__();
+template <dot_sem _Sem, dot_scope _Scope>
+_CCCL_DEVICE static inline _CUDA_VSTD::int32_t
+multimem_ld_reduce(sem_t<_Sem> __sem, scope_t<_Scope> __scope, op_max_t, const _CUDA_VSTD::int32_t* __addr)
+{
+  static_assert(__sem == sem_relaxed || __sem == sem_acquire, "");
+  static_assert(__scope == scope_cta || __scope == scope_cluster || __scope == scope_gpu || __scope == scope_sys, "");
+// __op == op_max (due to parameter type constraint)
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  _CUDA_VSTD::int32_t __dest;
+  _CCCL_IF_CONSTEXPR (__sem == sem_relaxed && __scope == scope_cta)
+  {
+    asm("multimem.ld_reduce.relaxed.cta.global.max.s32 %0, [%1];"
+        : "=r"(__dest)
+        : "l"(__as_ptr_gmem(__addr))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_relaxed && __scope == scope_cluster)
+  {
+    asm("multimem.ld_reduce.relaxed.cluster.global.max.s32 %0, [%1];"
+        : "=r"(__dest)
+        : "l"(__as_ptr_gmem(__addr))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_relaxed && __scope == scope_gpu)
+  {
+    asm("multimem.ld_reduce.relaxed.gpu.global.max.s32 %0, [%1];"
+        : "=r"(__dest)
+        : "l"(__as_ptr_gmem(__addr))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_relaxed && __scope == scope_sys)
+  {
+    asm("multimem.ld_reduce.relaxed.sys.global.max.s32 %0, [%1];"
+        : "=r"(__dest)
+        : "l"(__as_ptr_gmem(__addr))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_acquire && __scope == scope_cta)
+  {
+    asm("multimem.ld_reduce.acquire.cta.global.max.s32 %0, [%1];"
+        : "=r"(__dest)
+        : "l"(__as_ptr_gmem(__addr))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_acquire && __scope == scope_cluster)
+  {
+    asm("multimem.ld_reduce.acquire.cluster.global.max.s32 %0, [%1];"
+        : "=r"(__dest)
+        : "l"(__as_ptr_gmem(__addr))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_acquire && __scope == scope_gpu)
+  {
+    asm("multimem.ld_reduce.acquire.gpu.global.max.s32 %0, [%1];"
+        : "=r"(__dest)
+        : "l"(__as_ptr_gmem(__addr))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_acquire && __scope == scope_sys)
+  {
+    asm("multimem.ld_reduce.acquire.sys.global.max.s32 %0, [%1];"
+        : "=r"(__dest)
+        : "l"(__as_ptr_gmem(__addr))
+        : "memory");
+  }
+  return __dest;
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_multimem_ld_reduce_is_not_supported_before_SM_90__();
+  return 0;
+#  endif
+}
+#endif // __cccl_ptx_isa >= 810
+
+/*
+// multimem.ld_reduce.sem.global.op.s64 dest, [addr]; // PTX ISA 81, SM_90
+// .sem       = { .weak }
+// .op        = { .max }
+template <typename = void>
+__device__ static inline int64_t multimem_ld_reduce(
+  cuda::ptx::sem_weak_t,
+  cuda::ptx::op_max_t,
+  const int64_t* addr);
+*/
+#if __cccl_ptx_isa >= 810
+extern "C" _CCCL_DEVICE void __cuda_ptx_multimem_ld_reduce_is_not_supported_before_SM_90__();
+template <typename = void>
+_CCCL_DEVICE static inline _CUDA_VSTD::int64_t
+multimem_ld_reduce(sem_weak_t, op_max_t, const _CUDA_VSTD::int64_t* __addr)
+{
+// __sem == sem_weak (due to parameter type constraint)
+// __op == op_max (due to parameter type constraint)
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  _CUDA_VSTD::int64_t __dest;
+  asm("multimem.ld_reduce.weak.global.max.s64 %0, [%1];" : "=l"(__dest) : "l"(__as_ptr_gmem(__addr)) : "memory");
+  return __dest;
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_multimem_ld_reduce_is_not_supported_before_SM_90__();
+  return 0;
+#  endif
+}
+#endif // __cccl_ptx_isa >= 810
+
+/*
+// multimem.ld_reduce.sem.scope.global.op.s64 dest, [addr]; // PTX ISA 81, SM_90
+// .sem       = { .relaxed, .acquire }
+// .scope     = { .cta, .cluster, .gpu, .sys }
+// .op        = { .max }
+template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+__device__ static inline int64_t multimem_ld_reduce(
+  cuda::ptx::sem_t<Sem> sem,
+  cuda::ptx::scope_t<Scope> scope,
+  cuda::ptx::op_max_t,
+  const int64_t* addr);
+*/
+#if __cccl_ptx_isa >= 810
+extern "C" _CCCL_DEVICE void __cuda_ptx_multimem_ld_reduce_is_not_supported_before_SM_90__();
+template <dot_sem _Sem, dot_scope _Scope>
+_CCCL_DEVICE static inline _CUDA_VSTD::int64_t
+multimem_ld_reduce(sem_t<_Sem> __sem, scope_t<_Scope> __scope, op_max_t, const _CUDA_VSTD::int64_t* __addr)
+{
+  static_assert(__sem == sem_relaxed || __sem == sem_acquire, "");
+  static_assert(__scope == scope_cta || __scope == scope_cluster || __scope == scope_gpu || __scope == scope_sys, "");
+// __op == op_max (due to parameter type constraint)
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  _CUDA_VSTD::int64_t __dest;
+  _CCCL_IF_CONSTEXPR (__sem == sem_relaxed && __scope == scope_cta)
+  {
+    asm("multimem.ld_reduce.relaxed.cta.global.max.s64 %0, [%1];"
+        : "=l"(__dest)
+        : "l"(__as_ptr_gmem(__addr))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_relaxed && __scope == scope_cluster)
+  {
+    asm("multimem.ld_reduce.relaxed.cluster.global.max.s64 %0, [%1];"
+        : "=l"(__dest)
+        : "l"(__as_ptr_gmem(__addr))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_relaxed && __scope == scope_gpu)
+  {
+    asm("multimem.ld_reduce.relaxed.gpu.global.max.s64 %0, [%1];"
+        : "=l"(__dest)
+        : "l"(__as_ptr_gmem(__addr))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_relaxed && __scope == scope_sys)
+  {
+    asm("multimem.ld_reduce.relaxed.sys.global.max.s64 %0, [%1];"
+        : "=l"(__dest)
+        : "l"(__as_ptr_gmem(__addr))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_acquire && __scope == scope_cta)
+  {
+    asm("multimem.ld_reduce.acquire.cta.global.max.s64 %0, [%1];"
+        : "=l"(__dest)
+        : "l"(__as_ptr_gmem(__addr))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_acquire && __scope == scope_cluster)
+  {
+    asm("multimem.ld_reduce.acquire.cluster.global.max.s64 %0, [%1];"
+        : "=l"(__dest)
+        : "l"(__as_ptr_gmem(__addr))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_acquire && __scope == scope_gpu)
+  {
+    asm("multimem.ld_reduce.acquire.gpu.global.max.s64 %0, [%1];"
+        : "=l"(__dest)
+        : "l"(__as_ptr_gmem(__addr))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_acquire && __scope == scope_sys)
+  {
+    asm("multimem.ld_reduce.acquire.sys.global.max.s64 %0, [%1];"
+        : "=l"(__dest)
+        : "l"(__as_ptr_gmem(__addr))
+        : "memory");
+  }
+  return __dest;
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_multimem_ld_reduce_is_not_supported_before_SM_90__();
+  return 0;
+#  endif
+}
+#endif // __cccl_ptx_isa >= 810
+
+/*
+// multimem.ld_reduce.sem.global.op.u32 dest, [addr]; // PTX ISA 81, SM_90
+// .sem       = { .weak }
+// .op        = { .add }
+template <typename = void>
+__device__ static inline uint32_t multimem_ld_reduce(
+  cuda::ptx::sem_weak_t,
+  cuda::ptx::op_add_t,
+  const uint32_t* addr);
+*/
+#if __cccl_ptx_isa >= 810
+extern "C" _CCCL_DEVICE void __cuda_ptx_multimem_ld_reduce_is_not_supported_before_SM_90__();
+template <typename = void>
+_CCCL_DEVICE static inline _CUDA_VSTD::uint32_t
+multimem_ld_reduce(sem_weak_t, op_add_t, const _CUDA_VSTD::uint32_t* __addr)
+{
+// __sem == sem_weak (due to parameter type constraint)
+// __op == op_add (due to parameter type constraint)
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  _CUDA_VSTD::uint32_t __dest;
+  asm("multimem.ld_reduce.weak.global.add.u32 %0, [%1];" : "=r"(__dest) : "l"(__as_ptr_gmem(__addr)) : "memory");
+  return __dest;
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_multimem_ld_reduce_is_not_supported_before_SM_90__();
+  return 0;
+#  endif
+}
+#endif // __cccl_ptx_isa >= 810
+
+/*
+// multimem.ld_reduce.sem.scope.global.op.u32 dest, [addr]; // PTX ISA 81, SM_90
+// .sem       = { .relaxed, .acquire }
+// .scope     = { .cta, .cluster, .gpu, .sys }
+// .op        = { .add }
+template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+__device__ static inline uint32_t multimem_ld_reduce(
+  cuda::ptx::sem_t<Sem> sem,
+  cuda::ptx::scope_t<Scope> scope,
+  cuda::ptx::op_add_t,
+  const uint32_t* addr);
+*/
+#if __cccl_ptx_isa >= 810
+extern "C" _CCCL_DEVICE void __cuda_ptx_multimem_ld_reduce_is_not_supported_before_SM_90__();
+template <dot_sem _Sem, dot_scope _Scope>
+_CCCL_DEVICE static inline _CUDA_VSTD::uint32_t
+multimem_ld_reduce(sem_t<_Sem> __sem, scope_t<_Scope> __scope, op_add_t, const _CUDA_VSTD::uint32_t* __addr)
+{
+  static_assert(__sem == sem_relaxed || __sem == sem_acquire, "");
+  static_assert(__scope == scope_cta || __scope == scope_cluster || __scope == scope_gpu || __scope == scope_sys, "");
+// __op == op_add (due to parameter type constraint)
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  _CUDA_VSTD::uint32_t __dest;
+  _CCCL_IF_CONSTEXPR (__sem == sem_relaxed && __scope == scope_cta)
+  {
+    asm("multimem.ld_reduce.relaxed.cta.global.add.u32 %0, [%1];"
+        : "=r"(__dest)
+        : "l"(__as_ptr_gmem(__addr))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_relaxed && __scope == scope_cluster)
+  {
+    asm("multimem.ld_reduce.relaxed.cluster.global.add.u32 %0, [%1];"
+        : "=r"(__dest)
+        : "l"(__as_ptr_gmem(__addr))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_relaxed && __scope == scope_gpu)
+  {
+    asm("multimem.ld_reduce.relaxed.gpu.global.add.u32 %0, [%1];"
+        : "=r"(__dest)
+        : "l"(__as_ptr_gmem(__addr))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_relaxed && __scope == scope_sys)
+  {
+    asm("multimem.ld_reduce.relaxed.sys.global.add.u32 %0, [%1];"
+        : "=r"(__dest)
+        : "l"(__as_ptr_gmem(__addr))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_acquire && __scope == scope_cta)
+  {
+    asm("multimem.ld_reduce.acquire.cta.global.add.u32 %0, [%1];"
+        : "=r"(__dest)
+        : "l"(__as_ptr_gmem(__addr))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_acquire && __scope == scope_cluster)
+  {
+    asm("multimem.ld_reduce.acquire.cluster.global.add.u32 %0, [%1];"
+        : "=r"(__dest)
+        : "l"(__as_ptr_gmem(__addr))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_acquire && __scope == scope_gpu)
+  {
+    asm("multimem.ld_reduce.acquire.gpu.global.add.u32 %0, [%1];"
+        : "=r"(__dest)
+        : "l"(__as_ptr_gmem(__addr))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_acquire && __scope == scope_sys)
+  {
+    asm("multimem.ld_reduce.acquire.sys.global.add.u32 %0, [%1];"
+        : "=r"(__dest)
+        : "l"(__as_ptr_gmem(__addr))
+        : "memory");
+  }
+  return __dest;
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_multimem_ld_reduce_is_not_supported_before_SM_90__();
+  return 0;
+#  endif
+}
+#endif // __cccl_ptx_isa >= 810
+
+/*
+// multimem.ld_reduce.sem.global.op.u64 dest, [addr]; // PTX ISA 81, SM_90
+// .sem       = { .weak }
+// .op        = { .add }
+template <typename = void>
+__device__ static inline uint64_t multimem_ld_reduce(
+  cuda::ptx::sem_weak_t,
+  cuda::ptx::op_add_t,
+  const uint64_t* addr);
+*/
+#if __cccl_ptx_isa >= 810
+extern "C" _CCCL_DEVICE void __cuda_ptx_multimem_ld_reduce_is_not_supported_before_SM_90__();
+template <typename = void>
+_CCCL_DEVICE static inline _CUDA_VSTD::uint64_t
+multimem_ld_reduce(sem_weak_t, op_add_t, const _CUDA_VSTD::uint64_t* __addr)
+{
+// __sem == sem_weak (due to parameter type constraint)
+// __op == op_add (due to parameter type constraint)
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  _CUDA_VSTD::uint64_t __dest;
+  asm("multimem.ld_reduce.weak.global.add.u64 %0, [%1];" : "=l"(__dest) : "l"(__as_ptr_gmem(__addr)) : "memory");
+  return __dest;
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_multimem_ld_reduce_is_not_supported_before_SM_90__();
+  return 0;
+#  endif
+}
+#endif // __cccl_ptx_isa >= 810
+
+/*
+// multimem.ld_reduce.sem.scope.global.op.u64 dest, [addr]; // PTX ISA 81, SM_90
+// .sem       = { .relaxed, .acquire }
+// .scope     = { .cta, .cluster, .gpu, .sys }
+// .op        = { .add }
+template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+__device__ static inline uint64_t multimem_ld_reduce(
+  cuda::ptx::sem_t<Sem> sem,
+  cuda::ptx::scope_t<Scope> scope,
+  cuda::ptx::op_add_t,
+  const uint64_t* addr);
+*/
+#if __cccl_ptx_isa >= 810
+extern "C" _CCCL_DEVICE void __cuda_ptx_multimem_ld_reduce_is_not_supported_before_SM_90__();
+template <dot_sem _Sem, dot_scope _Scope>
+_CCCL_DEVICE static inline _CUDA_VSTD::uint64_t
+multimem_ld_reduce(sem_t<_Sem> __sem, scope_t<_Scope> __scope, op_add_t, const _CUDA_VSTD::uint64_t* __addr)
+{
+  static_assert(__sem == sem_relaxed || __sem == sem_acquire, "");
+  static_assert(__scope == scope_cta || __scope == scope_cluster || __scope == scope_gpu || __scope == scope_sys, "");
+// __op == op_add (due to parameter type constraint)
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  _CUDA_VSTD::uint64_t __dest;
+  _CCCL_IF_CONSTEXPR (__sem == sem_relaxed && __scope == scope_cta)
+  {
+    asm("multimem.ld_reduce.relaxed.cta.global.add.u64 %0, [%1];"
+        : "=l"(__dest)
+        : "l"(__as_ptr_gmem(__addr))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_relaxed && __scope == scope_cluster)
+  {
+    asm("multimem.ld_reduce.relaxed.cluster.global.add.u64 %0, [%1];"
+        : "=l"(__dest)
+        : "l"(__as_ptr_gmem(__addr))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_relaxed && __scope == scope_gpu)
+  {
+    asm("multimem.ld_reduce.relaxed.gpu.global.add.u64 %0, [%1];"
+        : "=l"(__dest)
+        : "l"(__as_ptr_gmem(__addr))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_relaxed && __scope == scope_sys)
+  {
+    asm("multimem.ld_reduce.relaxed.sys.global.add.u64 %0, [%1];"
+        : "=l"(__dest)
+        : "l"(__as_ptr_gmem(__addr))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_acquire && __scope == scope_cta)
+  {
+    asm("multimem.ld_reduce.acquire.cta.global.add.u64 %0, [%1];"
+        : "=l"(__dest)
+        : "l"(__as_ptr_gmem(__addr))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_acquire && __scope == scope_cluster)
+  {
+    asm("multimem.ld_reduce.acquire.cluster.global.add.u64 %0, [%1];"
+        : "=l"(__dest)
+        : "l"(__as_ptr_gmem(__addr))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_acquire && __scope == scope_gpu)
+  {
+    asm("multimem.ld_reduce.acquire.gpu.global.add.u64 %0, [%1];"
+        : "=l"(__dest)
+        : "l"(__as_ptr_gmem(__addr))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_acquire && __scope == scope_sys)
+  {
+    asm("multimem.ld_reduce.acquire.sys.global.add.u64 %0, [%1];"
+        : "=l"(__dest)
+        : "l"(__as_ptr_gmem(__addr))
+        : "memory");
+  }
+  return __dest;
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_multimem_ld_reduce_is_not_supported_before_SM_90__();
+  return 0;
+#  endif
+}
+#endif // __cccl_ptx_isa >= 810
+
+/*
+// multimem.ld_reduce.sem.global.op.s32 dest, [addr]; // PTX ISA 81, SM_90
+// .sem       = { .weak }
+// .op        = { .add }
+template <typename = void>
+__device__ static inline int32_t multimem_ld_reduce(
+  cuda::ptx::sem_weak_t,
+  cuda::ptx::op_add_t,
+  const int32_t* addr);
+*/
+#if __cccl_ptx_isa >= 810
+extern "C" _CCCL_DEVICE void __cuda_ptx_multimem_ld_reduce_is_not_supported_before_SM_90__();
+template <typename = void>
+_CCCL_DEVICE static inline _CUDA_VSTD::int32_t
+multimem_ld_reduce(sem_weak_t, op_add_t, const _CUDA_VSTD::int32_t* __addr)
+{
+// __sem == sem_weak (due to parameter type constraint)
+// __op == op_add (due to parameter type constraint)
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  _CUDA_VSTD::int32_t __dest;
+  asm("multimem.ld_reduce.weak.global.add.s32 %0, [%1];" : "=r"(__dest) : "l"(__as_ptr_gmem(__addr)) : "memory");
+  return __dest;
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_multimem_ld_reduce_is_not_supported_before_SM_90__();
+  return 0;
+#  endif
+}
+#endif // __cccl_ptx_isa >= 810
+
+/*
+// multimem.ld_reduce.sem.scope.global.op.s32 dest, [addr]; // PTX ISA 81, SM_90
+// .sem       = { .relaxed, .acquire }
+// .scope     = { .cta, .cluster, .gpu, .sys }
+// .op        = { .add }
+template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+__device__ static inline int32_t multimem_ld_reduce(
+  cuda::ptx::sem_t<Sem> sem,
+  cuda::ptx::scope_t<Scope> scope,
+  cuda::ptx::op_add_t,
+  const int32_t* addr);
+*/
+#if __cccl_ptx_isa >= 810
+extern "C" _CCCL_DEVICE void __cuda_ptx_multimem_ld_reduce_is_not_supported_before_SM_90__();
+template <dot_sem _Sem, dot_scope _Scope>
+_CCCL_DEVICE static inline _CUDA_VSTD::int32_t
+multimem_ld_reduce(sem_t<_Sem> __sem, scope_t<_Scope> __scope, op_add_t, const _CUDA_VSTD::int32_t* __addr)
+{
+  static_assert(__sem == sem_relaxed || __sem == sem_acquire, "");
+  static_assert(__scope == scope_cta || __scope == scope_cluster || __scope == scope_gpu || __scope == scope_sys, "");
+// __op == op_add (due to parameter type constraint)
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  _CUDA_VSTD::int32_t __dest;
+  _CCCL_IF_CONSTEXPR (__sem == sem_relaxed && __scope == scope_cta)
+  {
+    asm("multimem.ld_reduce.relaxed.cta.global.add.s32 %0, [%1];"
+        : "=r"(__dest)
+        : "l"(__as_ptr_gmem(__addr))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_relaxed && __scope == scope_cluster)
+  {
+    asm("multimem.ld_reduce.relaxed.cluster.global.add.s32 %0, [%1];"
+        : "=r"(__dest)
+        : "l"(__as_ptr_gmem(__addr))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_relaxed && __scope == scope_gpu)
+  {
+    asm("multimem.ld_reduce.relaxed.gpu.global.add.s32 %0, [%1];"
+        : "=r"(__dest)
+        : "l"(__as_ptr_gmem(__addr))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_relaxed && __scope == scope_sys)
+  {
+    asm("multimem.ld_reduce.relaxed.sys.global.add.s32 %0, [%1];"
+        : "=r"(__dest)
+        : "l"(__as_ptr_gmem(__addr))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_acquire && __scope == scope_cta)
+  {
+    asm("multimem.ld_reduce.acquire.cta.global.add.s32 %0, [%1];"
+        : "=r"(__dest)
+        : "l"(__as_ptr_gmem(__addr))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_acquire && __scope == scope_cluster)
+  {
+    asm("multimem.ld_reduce.acquire.cluster.global.add.s32 %0, [%1];"
+        : "=r"(__dest)
+        : "l"(__as_ptr_gmem(__addr))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_acquire && __scope == scope_gpu)
+  {
+    asm("multimem.ld_reduce.acquire.gpu.global.add.s32 %0, [%1];"
+        : "=r"(__dest)
+        : "l"(__as_ptr_gmem(__addr))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_acquire && __scope == scope_sys)
+  {
+    asm("multimem.ld_reduce.acquire.sys.global.add.s32 %0, [%1];"
+        : "=r"(__dest)
+        : "l"(__as_ptr_gmem(__addr))
+        : "memory");
+  }
+  return __dest;
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_multimem_ld_reduce_is_not_supported_before_SM_90__();
+  return 0;
+#  endif
+}
+#endif // __cccl_ptx_isa >= 810
+
+/*
+// multimem.ld_reduce.sem.global.op.u64 dest, [addr]; // PTX ISA 81, SM_90
+// .sem       = { .weak }
+// .op        = { .add }
+template <typename = void>
+__device__ static inline int64_t multimem_ld_reduce(
+  cuda::ptx::sem_weak_t,
+  cuda::ptx::op_add_t,
+  const int64_t* addr);
+*/
+#if __cccl_ptx_isa >= 810
+extern "C" _CCCL_DEVICE void __cuda_ptx_multimem_ld_reduce_is_not_supported_before_SM_90__();
+template <typename = void>
+_CCCL_DEVICE static inline _CUDA_VSTD::int64_t
+multimem_ld_reduce(sem_weak_t, op_add_t, const _CUDA_VSTD::int64_t* __addr)
+{
+// __sem == sem_weak (due to parameter type constraint)
+// __op == op_add (due to parameter type constraint)
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  _CUDA_VSTD::int64_t __dest;
+  asm("multimem.ld_reduce.weak.global.add.u64 %0, [%1];" : "=l"(__dest) : "l"(__as_ptr_gmem(__addr)) : "memory");
+  return __dest;
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_multimem_ld_reduce_is_not_supported_before_SM_90__();
+  return 0;
+#  endif
+}
+#endif // __cccl_ptx_isa >= 810
+
+/*
+// multimem.ld_reduce.sem.scope.global.op.u64 dest, [addr]; // PTX ISA 81, SM_90
+// .sem       = { .relaxed, .acquire }
+// .scope     = { .cta, .cluster, .gpu, .sys }
+// .op        = { .add }
+template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+__device__ static inline int64_t multimem_ld_reduce(
+  cuda::ptx::sem_t<Sem> sem,
+  cuda::ptx::scope_t<Scope> scope,
+  cuda::ptx::op_add_t,
+  const int64_t* addr);
+*/
+#if __cccl_ptx_isa >= 810
+extern "C" _CCCL_DEVICE void __cuda_ptx_multimem_ld_reduce_is_not_supported_before_SM_90__();
+template <dot_sem _Sem, dot_scope _Scope>
+_CCCL_DEVICE static inline _CUDA_VSTD::int64_t
+multimem_ld_reduce(sem_t<_Sem> __sem, scope_t<_Scope> __scope, op_add_t, const _CUDA_VSTD::int64_t* __addr)
+{
+  static_assert(__sem == sem_relaxed || __sem == sem_acquire, "");
+  static_assert(__scope == scope_cta || __scope == scope_cluster || __scope == scope_gpu || __scope == scope_sys, "");
+// __op == op_add (due to parameter type constraint)
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  _CUDA_VSTD::int64_t __dest;
+  _CCCL_IF_CONSTEXPR (__sem == sem_relaxed && __scope == scope_cta)
+  {
+    asm("multimem.ld_reduce.relaxed.cta.global.add.u64 %0, [%1];"
+        : "=l"(__dest)
+        : "l"(__as_ptr_gmem(__addr))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_relaxed && __scope == scope_cluster)
+  {
+    asm("multimem.ld_reduce.relaxed.cluster.global.add.u64 %0, [%1];"
+        : "=l"(__dest)
+        : "l"(__as_ptr_gmem(__addr))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_relaxed && __scope == scope_gpu)
+  {
+    asm("multimem.ld_reduce.relaxed.gpu.global.add.u64 %0, [%1];"
+        : "=l"(__dest)
+        : "l"(__as_ptr_gmem(__addr))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_relaxed && __scope == scope_sys)
+  {
+    asm("multimem.ld_reduce.relaxed.sys.global.add.u64 %0, [%1];"
+        : "=l"(__dest)
+        : "l"(__as_ptr_gmem(__addr))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_acquire && __scope == scope_cta)
+  {
+    asm("multimem.ld_reduce.acquire.cta.global.add.u64 %0, [%1];"
+        : "=l"(__dest)
+        : "l"(__as_ptr_gmem(__addr))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_acquire && __scope == scope_cluster)
+  {
+    asm("multimem.ld_reduce.acquire.cluster.global.add.u64 %0, [%1];"
+        : "=l"(__dest)
+        : "l"(__as_ptr_gmem(__addr))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_acquire && __scope == scope_gpu)
+  {
+    asm("multimem.ld_reduce.acquire.gpu.global.add.u64 %0, [%1];"
+        : "=l"(__dest)
+        : "l"(__as_ptr_gmem(__addr))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_acquire && __scope == scope_sys)
+  {
+    asm("multimem.ld_reduce.acquire.sys.global.add.u64 %0, [%1];"
+        : "=l"(__dest)
+        : "l"(__as_ptr_gmem(__addr))
+        : "memory");
+  }
+  return __dest;
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_multimem_ld_reduce_is_not_supported_before_SM_90__();
+  return 0;
+#  endif
+}
+#endif // __cccl_ptx_isa >= 810
+
+/*
+// multimem.ld_reduce.sem.global.op.b32 dest, [addr]; // PTX ISA 81, SM_90
+// .sem       = { .weak }
+// .op        = { .and }
+template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+__device__ static inline B32 multimem_ld_reduce(
+  cuda::ptx::sem_weak_t,
+  cuda::ptx::op_and_op_t,
+  const B32* addr);
+*/
+#if __cccl_ptx_isa >= 810
+extern "C" _CCCL_DEVICE void __cuda_ptx_multimem_ld_reduce_is_not_supported_before_SM_90__();
+template <typename _B32, _CUDA_VSTD::enable_if_t<sizeof(_B32) == 4, bool> = true>
+_CCCL_DEVICE static inline _B32 multimem_ld_reduce(sem_weak_t, op_and_op_t, const _B32* __addr)
+{
+  // __sem == sem_weak (due to parameter type constraint)
+  // __op == op_and_op (due to parameter type constraint)
+  static_assert(sizeof(_B32) == 4, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  _CUDA_VSTD::uint32_t __dest;
+  asm("multimem.ld_reduce.weak.global.and.b32 %0, [%1];" : "=r"(__dest) : "l"(__as_ptr_gmem(__addr)) : "memory");
+  return *reinterpret_cast<_B32*>(&__dest);
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_multimem_ld_reduce_is_not_supported_before_SM_90__();
+  _CUDA_VSTD::uint32_t __err_out_var = 0;
+  return *reinterpret_cast<_B32*>(&__err_out_var);
+#  endif
+}
+#endif // __cccl_ptx_isa >= 810
+
+/*
+// multimem.ld_reduce.sem.scope.global.op.b32 dest, [addr]; // PTX ISA 81, SM_90
+// .sem       = { .relaxed, .acquire }
+// .scope     = { .cta, .cluster, .gpu, .sys }
+// .op        = { .and }
+template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true, cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+__device__ static inline B32 multimem_ld_reduce(
+  cuda::ptx::sem_t<Sem> sem,
+  cuda::ptx::scope_t<Scope> scope,
+  cuda::ptx::op_and_op_t,
+  const B32* addr);
+*/
+#if __cccl_ptx_isa >= 810
+extern "C" _CCCL_DEVICE void __cuda_ptx_multimem_ld_reduce_is_not_supported_before_SM_90__();
+template <typename _B32, _CUDA_VSTD::enable_if_t<sizeof(_B32) == 4, bool> = true, dot_sem _Sem, dot_scope _Scope>
+_CCCL_DEVICE static inline _B32
+multimem_ld_reduce(sem_t<_Sem> __sem, scope_t<_Scope> __scope, op_and_op_t, const _B32* __addr)
+{
+  static_assert(__sem == sem_relaxed || __sem == sem_acquire, "");
+  static_assert(__scope == scope_cta || __scope == scope_cluster || __scope == scope_gpu || __scope == scope_sys, "");
+  // __op == op_and_op (due to parameter type constraint)
+  static_assert(sizeof(_B32) == 4, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  _CUDA_VSTD::uint32_t __dest;
+  _CCCL_IF_CONSTEXPR (__sem == sem_relaxed && __scope == scope_cta)
+  {
+    asm("multimem.ld_reduce.relaxed.cta.global.and.b32 %0, [%1];"
+        : "=r"(__dest)
+        : "l"(__as_ptr_gmem(__addr))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_relaxed && __scope == scope_cluster)
+  {
+    asm("multimem.ld_reduce.relaxed.cluster.global.and.b32 %0, [%1];"
+        : "=r"(__dest)
+        : "l"(__as_ptr_gmem(__addr))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_relaxed && __scope == scope_gpu)
+  {
+    asm("multimem.ld_reduce.relaxed.gpu.global.and.b32 %0, [%1];"
+        : "=r"(__dest)
+        : "l"(__as_ptr_gmem(__addr))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_relaxed && __scope == scope_sys)
+  {
+    asm("multimem.ld_reduce.relaxed.sys.global.and.b32 %0, [%1];"
+        : "=r"(__dest)
+        : "l"(__as_ptr_gmem(__addr))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_acquire && __scope == scope_cta)
+  {
+    asm("multimem.ld_reduce.acquire.cta.global.and.b32 %0, [%1];"
+        : "=r"(__dest)
+        : "l"(__as_ptr_gmem(__addr))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_acquire && __scope == scope_cluster)
+  {
+    asm("multimem.ld_reduce.acquire.cluster.global.and.b32 %0, [%1];"
+        : "=r"(__dest)
+        : "l"(__as_ptr_gmem(__addr))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_acquire && __scope == scope_gpu)
+  {
+    asm("multimem.ld_reduce.acquire.gpu.global.and.b32 %0, [%1];"
+        : "=r"(__dest)
+        : "l"(__as_ptr_gmem(__addr))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_acquire && __scope == scope_sys)
+  {
+    asm("multimem.ld_reduce.acquire.sys.global.and.b32 %0, [%1];"
+        : "=r"(__dest)
+        : "l"(__as_ptr_gmem(__addr))
+        : "memory");
+  }
+  return *reinterpret_cast<_B32*>(&__dest);
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_multimem_ld_reduce_is_not_supported_before_SM_90__();
+  _CUDA_VSTD::uint32_t __err_out_var = 0;
+  return *reinterpret_cast<_B32*>(&__err_out_var);
+#  endif
+}
+#endif // __cccl_ptx_isa >= 810
+
+/*
+// multimem.ld_reduce.sem.global.op.b32 dest, [addr]; // PTX ISA 81, SM_90
+// .sem       = { .weak }
+// .op        = { .or }
+template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+__device__ static inline B32 multimem_ld_reduce(
+  cuda::ptx::sem_weak_t,
+  cuda::ptx::op_or_op_t,
+  const B32* addr);
+*/
+#if __cccl_ptx_isa >= 810
+extern "C" _CCCL_DEVICE void __cuda_ptx_multimem_ld_reduce_is_not_supported_before_SM_90__();
+template <typename _B32, _CUDA_VSTD::enable_if_t<sizeof(_B32) == 4, bool> = true>
+_CCCL_DEVICE static inline _B32 multimem_ld_reduce(sem_weak_t, op_or_op_t, const _B32* __addr)
+{
+  // __sem == sem_weak (due to parameter type constraint)
+  // __op == op_or_op (due to parameter type constraint)
+  static_assert(sizeof(_B32) == 4, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  _CUDA_VSTD::uint32_t __dest;
+  asm("multimem.ld_reduce.weak.global.or.b32 %0, [%1];" : "=r"(__dest) : "l"(__as_ptr_gmem(__addr)) : "memory");
+  return *reinterpret_cast<_B32*>(&__dest);
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_multimem_ld_reduce_is_not_supported_before_SM_90__();
+  _CUDA_VSTD::uint32_t __err_out_var = 0;
+  return *reinterpret_cast<_B32*>(&__err_out_var);
+#  endif
+}
+#endif // __cccl_ptx_isa >= 810
+
+/*
+// multimem.ld_reduce.sem.scope.global.op.b32 dest, [addr]; // PTX ISA 81, SM_90
+// .sem       = { .relaxed, .acquire }
+// .scope     = { .cta, .cluster, .gpu, .sys }
+// .op        = { .or }
+template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true, cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+__device__ static inline B32 multimem_ld_reduce(
+  cuda::ptx::sem_t<Sem> sem,
+  cuda::ptx::scope_t<Scope> scope,
+  cuda::ptx::op_or_op_t,
+  const B32* addr);
+*/
+#if __cccl_ptx_isa >= 810
+extern "C" _CCCL_DEVICE void __cuda_ptx_multimem_ld_reduce_is_not_supported_before_SM_90__();
+template <typename _B32, _CUDA_VSTD::enable_if_t<sizeof(_B32) == 4, bool> = true, dot_sem _Sem, dot_scope _Scope>
+_CCCL_DEVICE static inline _B32
+multimem_ld_reduce(sem_t<_Sem> __sem, scope_t<_Scope> __scope, op_or_op_t, const _B32* __addr)
+{
+  static_assert(__sem == sem_relaxed || __sem == sem_acquire, "");
+  static_assert(__scope == scope_cta || __scope == scope_cluster || __scope == scope_gpu || __scope == scope_sys, "");
+  // __op == op_or_op (due to parameter type constraint)
+  static_assert(sizeof(_B32) == 4, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  _CUDA_VSTD::uint32_t __dest;
+  _CCCL_IF_CONSTEXPR (__sem == sem_relaxed && __scope == scope_cta)
+  {
+    asm("multimem.ld_reduce.relaxed.cta.global.or.b32 %0, [%1];"
+        : "=r"(__dest)
+        : "l"(__as_ptr_gmem(__addr))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_relaxed && __scope == scope_cluster)
+  {
+    asm("multimem.ld_reduce.relaxed.cluster.global.or.b32 %0, [%1];"
+        : "=r"(__dest)
+        : "l"(__as_ptr_gmem(__addr))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_relaxed && __scope == scope_gpu)
+  {
+    asm("multimem.ld_reduce.relaxed.gpu.global.or.b32 %0, [%1];"
+        : "=r"(__dest)
+        : "l"(__as_ptr_gmem(__addr))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_relaxed && __scope == scope_sys)
+  {
+    asm("multimem.ld_reduce.relaxed.sys.global.or.b32 %0, [%1];"
+        : "=r"(__dest)
+        : "l"(__as_ptr_gmem(__addr))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_acquire && __scope == scope_cta)
+  {
+    asm("multimem.ld_reduce.acquire.cta.global.or.b32 %0, [%1];"
+        : "=r"(__dest)
+        : "l"(__as_ptr_gmem(__addr))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_acquire && __scope == scope_cluster)
+  {
+    asm("multimem.ld_reduce.acquire.cluster.global.or.b32 %0, [%1];"
+        : "=r"(__dest)
+        : "l"(__as_ptr_gmem(__addr))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_acquire && __scope == scope_gpu)
+  {
+    asm("multimem.ld_reduce.acquire.gpu.global.or.b32 %0, [%1];"
+        : "=r"(__dest)
+        : "l"(__as_ptr_gmem(__addr))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_acquire && __scope == scope_sys)
+  {
+    asm("multimem.ld_reduce.acquire.sys.global.or.b32 %0, [%1];"
+        : "=r"(__dest)
+        : "l"(__as_ptr_gmem(__addr))
+        : "memory");
+  }
+  return *reinterpret_cast<_B32*>(&__dest);
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_multimem_ld_reduce_is_not_supported_before_SM_90__();
+  _CUDA_VSTD::uint32_t __err_out_var = 0;
+  return *reinterpret_cast<_B32*>(&__err_out_var);
+#  endif
+}
+#endif // __cccl_ptx_isa >= 810
+
+/*
+// multimem.ld_reduce.sem.global.op.b32 dest, [addr]; // PTX ISA 81, SM_90
+// .sem       = { .weak }
+// .op        = { .xor }
+template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+__device__ static inline B32 multimem_ld_reduce(
+  cuda::ptx::sem_weak_t,
+  cuda::ptx::op_xor_op_t,
+  const B32* addr);
+*/
+#if __cccl_ptx_isa >= 810
+extern "C" _CCCL_DEVICE void __cuda_ptx_multimem_ld_reduce_is_not_supported_before_SM_90__();
+template <typename _B32, _CUDA_VSTD::enable_if_t<sizeof(_B32) == 4, bool> = true>
+_CCCL_DEVICE static inline _B32 multimem_ld_reduce(sem_weak_t, op_xor_op_t, const _B32* __addr)
+{
+  // __sem == sem_weak (due to parameter type constraint)
+  // __op == op_xor_op (due to parameter type constraint)
+  static_assert(sizeof(_B32) == 4, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  _CUDA_VSTD::uint32_t __dest;
+  asm("multimem.ld_reduce.weak.global.xor.b32 %0, [%1];" : "=r"(__dest) : "l"(__as_ptr_gmem(__addr)) : "memory");
+  return *reinterpret_cast<_B32*>(&__dest);
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_multimem_ld_reduce_is_not_supported_before_SM_90__();
+  _CUDA_VSTD::uint32_t __err_out_var = 0;
+  return *reinterpret_cast<_B32*>(&__err_out_var);
+#  endif
+}
+#endif // __cccl_ptx_isa >= 810
+
+/*
+// multimem.ld_reduce.sem.scope.global.op.b32 dest, [addr]; // PTX ISA 81, SM_90
+// .sem       = { .relaxed, .acquire }
+// .scope     = { .cta, .cluster, .gpu, .sys }
+// .op        = { .xor }
+template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true, cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+__device__ static inline B32 multimem_ld_reduce(
+  cuda::ptx::sem_t<Sem> sem,
+  cuda::ptx::scope_t<Scope> scope,
+  cuda::ptx::op_xor_op_t,
+  const B32* addr);
+*/
+#if __cccl_ptx_isa >= 810
+extern "C" _CCCL_DEVICE void __cuda_ptx_multimem_ld_reduce_is_not_supported_before_SM_90__();
+template <typename _B32, _CUDA_VSTD::enable_if_t<sizeof(_B32) == 4, bool> = true, dot_sem _Sem, dot_scope _Scope>
+_CCCL_DEVICE static inline _B32
+multimem_ld_reduce(sem_t<_Sem> __sem, scope_t<_Scope> __scope, op_xor_op_t, const _B32* __addr)
+{
+  static_assert(__sem == sem_relaxed || __sem == sem_acquire, "");
+  static_assert(__scope == scope_cta || __scope == scope_cluster || __scope == scope_gpu || __scope == scope_sys, "");
+  // __op == op_xor_op (due to parameter type constraint)
+  static_assert(sizeof(_B32) == 4, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  _CUDA_VSTD::uint32_t __dest;
+  _CCCL_IF_CONSTEXPR (__sem == sem_relaxed && __scope == scope_cta)
+  {
+    asm("multimem.ld_reduce.relaxed.cta.global.xor.b32 %0, [%1];"
+        : "=r"(__dest)
+        : "l"(__as_ptr_gmem(__addr))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_relaxed && __scope == scope_cluster)
+  {
+    asm("multimem.ld_reduce.relaxed.cluster.global.xor.b32 %0, [%1];"
+        : "=r"(__dest)
+        : "l"(__as_ptr_gmem(__addr))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_relaxed && __scope == scope_gpu)
+  {
+    asm("multimem.ld_reduce.relaxed.gpu.global.xor.b32 %0, [%1];"
+        : "=r"(__dest)
+        : "l"(__as_ptr_gmem(__addr))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_relaxed && __scope == scope_sys)
+  {
+    asm("multimem.ld_reduce.relaxed.sys.global.xor.b32 %0, [%1];"
+        : "=r"(__dest)
+        : "l"(__as_ptr_gmem(__addr))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_acquire && __scope == scope_cta)
+  {
+    asm("multimem.ld_reduce.acquire.cta.global.xor.b32 %0, [%1];"
+        : "=r"(__dest)
+        : "l"(__as_ptr_gmem(__addr))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_acquire && __scope == scope_cluster)
+  {
+    asm("multimem.ld_reduce.acquire.cluster.global.xor.b32 %0, [%1];"
+        : "=r"(__dest)
+        : "l"(__as_ptr_gmem(__addr))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_acquire && __scope == scope_gpu)
+  {
+    asm("multimem.ld_reduce.acquire.gpu.global.xor.b32 %0, [%1];"
+        : "=r"(__dest)
+        : "l"(__as_ptr_gmem(__addr))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_acquire && __scope == scope_sys)
+  {
+    asm("multimem.ld_reduce.acquire.sys.global.xor.b32 %0, [%1];"
+        : "=r"(__dest)
+        : "l"(__as_ptr_gmem(__addr))
+        : "memory");
+  }
+  return *reinterpret_cast<_B32*>(&__dest);
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_multimem_ld_reduce_is_not_supported_before_SM_90__();
+  _CUDA_VSTD::uint32_t __err_out_var = 0;
+  return *reinterpret_cast<_B32*>(&__err_out_var);
+#  endif
+}
+#endif // __cccl_ptx_isa >= 810
+
+/*
+// multimem.ld_reduce.sem.global.op.b64 dest, [addr]; // PTX ISA 81, SM_90
+// .sem       = { .weak }
+// .op        = { .and }
+template <typename B64, enable_if_t<sizeof(B64) == 8, bool> = true>
+__device__ static inline B64 multimem_ld_reduce(
+  cuda::ptx::sem_weak_t,
+  cuda::ptx::op_and_op_t,
+  const B64* addr);
+*/
+#if __cccl_ptx_isa >= 810
+extern "C" _CCCL_DEVICE void __cuda_ptx_multimem_ld_reduce_is_not_supported_before_SM_90__();
+template <typename _B64, _CUDA_VSTD::enable_if_t<sizeof(_B64) == 8, bool> = true>
+_CCCL_DEVICE static inline _B64 multimem_ld_reduce(sem_weak_t, op_and_op_t, const _B64* __addr)
+{
+  // __sem == sem_weak (due to parameter type constraint)
+  // __op == op_and_op (due to parameter type constraint)
+  static_assert(sizeof(_B64) == 8, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  _CUDA_VSTD::uint64_t __dest;
+  asm("multimem.ld_reduce.weak.global.and.b64 %0, [%1];" : "=l"(__dest) : "l"(__as_ptr_gmem(__addr)) : "memory");
+  return *reinterpret_cast<_B64*>(&__dest);
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_multimem_ld_reduce_is_not_supported_before_SM_90__();
+  _CUDA_VSTD::uint64_t __err_out_var = 0;
+  return *reinterpret_cast<_B64*>(&__err_out_var);
+#  endif
+}
+#endif // __cccl_ptx_isa >= 810
+
+/*
+// multimem.ld_reduce.sem.scope.global.op.b64 dest, [addr]; // PTX ISA 81, SM_90
+// .sem       = { .relaxed, .acquire }
+// .scope     = { .cta, .cluster, .gpu, .sys }
+// .op        = { .and }
+template <typename B64, enable_if_t<sizeof(B64) == 8, bool> = true, cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+__device__ static inline B64 multimem_ld_reduce(
+  cuda::ptx::sem_t<Sem> sem,
+  cuda::ptx::scope_t<Scope> scope,
+  cuda::ptx::op_and_op_t,
+  const B64* addr);
+*/
+#if __cccl_ptx_isa >= 810
+extern "C" _CCCL_DEVICE void __cuda_ptx_multimem_ld_reduce_is_not_supported_before_SM_90__();
+template <typename _B64, _CUDA_VSTD::enable_if_t<sizeof(_B64) == 8, bool> = true, dot_sem _Sem, dot_scope _Scope>
+_CCCL_DEVICE static inline _B64
+multimem_ld_reduce(sem_t<_Sem> __sem, scope_t<_Scope> __scope, op_and_op_t, const _B64* __addr)
+{
+  static_assert(__sem == sem_relaxed || __sem == sem_acquire, "");
+  static_assert(__scope == scope_cta || __scope == scope_cluster || __scope == scope_gpu || __scope == scope_sys, "");
+  // __op == op_and_op (due to parameter type constraint)
+  static_assert(sizeof(_B64) == 8, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  _CUDA_VSTD::uint64_t __dest;
+  _CCCL_IF_CONSTEXPR (__sem == sem_relaxed && __scope == scope_cta)
+  {
+    asm("multimem.ld_reduce.relaxed.cta.global.and.b64 %0, [%1];"
+        : "=l"(__dest)
+        : "l"(__as_ptr_gmem(__addr))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_relaxed && __scope == scope_cluster)
+  {
+    asm("multimem.ld_reduce.relaxed.cluster.global.and.b64 %0, [%1];"
+        : "=l"(__dest)
+        : "l"(__as_ptr_gmem(__addr))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_relaxed && __scope == scope_gpu)
+  {
+    asm("multimem.ld_reduce.relaxed.gpu.global.and.b64 %0, [%1];"
+        : "=l"(__dest)
+        : "l"(__as_ptr_gmem(__addr))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_relaxed && __scope == scope_sys)
+  {
+    asm("multimem.ld_reduce.relaxed.sys.global.and.b64 %0, [%1];"
+        : "=l"(__dest)
+        : "l"(__as_ptr_gmem(__addr))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_acquire && __scope == scope_cta)
+  {
+    asm("multimem.ld_reduce.acquire.cta.global.and.b64 %0, [%1];"
+        : "=l"(__dest)
+        : "l"(__as_ptr_gmem(__addr))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_acquire && __scope == scope_cluster)
+  {
+    asm("multimem.ld_reduce.acquire.cluster.global.and.b64 %0, [%1];"
+        : "=l"(__dest)
+        : "l"(__as_ptr_gmem(__addr))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_acquire && __scope == scope_gpu)
+  {
+    asm("multimem.ld_reduce.acquire.gpu.global.and.b64 %0, [%1];"
+        : "=l"(__dest)
+        : "l"(__as_ptr_gmem(__addr))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_acquire && __scope == scope_sys)
+  {
+    asm("multimem.ld_reduce.acquire.sys.global.and.b64 %0, [%1];"
+        : "=l"(__dest)
+        : "l"(__as_ptr_gmem(__addr))
+        : "memory");
+  }
+  return *reinterpret_cast<_B64*>(&__dest);
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_multimem_ld_reduce_is_not_supported_before_SM_90__();
+  _CUDA_VSTD::uint64_t __err_out_var = 0;
+  return *reinterpret_cast<_B64*>(&__err_out_var);
+#  endif
+}
+#endif // __cccl_ptx_isa >= 810
+
+/*
+// multimem.ld_reduce.sem.global.op.b64 dest, [addr]; // PTX ISA 81, SM_90
+// .sem       = { .weak }
+// .op        = { .or }
+template <typename B64, enable_if_t<sizeof(B64) == 8, bool> = true>
+__device__ static inline B64 multimem_ld_reduce(
+  cuda::ptx::sem_weak_t,
+  cuda::ptx::op_or_op_t,
+  const B64* addr);
+*/
+#if __cccl_ptx_isa >= 810
+extern "C" _CCCL_DEVICE void __cuda_ptx_multimem_ld_reduce_is_not_supported_before_SM_90__();
+template <typename _B64, _CUDA_VSTD::enable_if_t<sizeof(_B64) == 8, bool> = true>
+_CCCL_DEVICE static inline _B64 multimem_ld_reduce(sem_weak_t, op_or_op_t, const _B64* __addr)
+{
+  // __sem == sem_weak (due to parameter type constraint)
+  // __op == op_or_op (due to parameter type constraint)
+  static_assert(sizeof(_B64) == 8, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  _CUDA_VSTD::uint64_t __dest;
+  asm("multimem.ld_reduce.weak.global.or.b64 %0, [%1];" : "=l"(__dest) : "l"(__as_ptr_gmem(__addr)) : "memory");
+  return *reinterpret_cast<_B64*>(&__dest);
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_multimem_ld_reduce_is_not_supported_before_SM_90__();
+  _CUDA_VSTD::uint64_t __err_out_var = 0;
+  return *reinterpret_cast<_B64*>(&__err_out_var);
+#  endif
+}
+#endif // __cccl_ptx_isa >= 810
+
+/*
+// multimem.ld_reduce.sem.scope.global.op.b64 dest, [addr]; // PTX ISA 81, SM_90
+// .sem       = { .relaxed, .acquire }
+// .scope     = { .cta, .cluster, .gpu, .sys }
+// .op        = { .or }
+template <typename B64, enable_if_t<sizeof(B64) == 8, bool> = true, cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+__device__ static inline B64 multimem_ld_reduce(
+  cuda::ptx::sem_t<Sem> sem,
+  cuda::ptx::scope_t<Scope> scope,
+  cuda::ptx::op_or_op_t,
+  const B64* addr);
+*/
+#if __cccl_ptx_isa >= 810
+extern "C" _CCCL_DEVICE void __cuda_ptx_multimem_ld_reduce_is_not_supported_before_SM_90__();
+template <typename _B64, _CUDA_VSTD::enable_if_t<sizeof(_B64) == 8, bool> = true, dot_sem _Sem, dot_scope _Scope>
+_CCCL_DEVICE static inline _B64
+multimem_ld_reduce(sem_t<_Sem> __sem, scope_t<_Scope> __scope, op_or_op_t, const _B64* __addr)
+{
+  static_assert(__sem == sem_relaxed || __sem == sem_acquire, "");
+  static_assert(__scope == scope_cta || __scope == scope_cluster || __scope == scope_gpu || __scope == scope_sys, "");
+  // __op == op_or_op (due to parameter type constraint)
+  static_assert(sizeof(_B64) == 8, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  _CUDA_VSTD::uint64_t __dest;
+  _CCCL_IF_CONSTEXPR (__sem == sem_relaxed && __scope == scope_cta)
+  {
+    asm("multimem.ld_reduce.relaxed.cta.global.or.b64 %0, [%1];"
+        : "=l"(__dest)
+        : "l"(__as_ptr_gmem(__addr))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_relaxed && __scope == scope_cluster)
+  {
+    asm("multimem.ld_reduce.relaxed.cluster.global.or.b64 %0, [%1];"
+        : "=l"(__dest)
+        : "l"(__as_ptr_gmem(__addr))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_relaxed && __scope == scope_gpu)
+  {
+    asm("multimem.ld_reduce.relaxed.gpu.global.or.b64 %0, [%1];"
+        : "=l"(__dest)
+        : "l"(__as_ptr_gmem(__addr))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_relaxed && __scope == scope_sys)
+  {
+    asm("multimem.ld_reduce.relaxed.sys.global.or.b64 %0, [%1];"
+        : "=l"(__dest)
+        : "l"(__as_ptr_gmem(__addr))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_acquire && __scope == scope_cta)
+  {
+    asm("multimem.ld_reduce.acquire.cta.global.or.b64 %0, [%1];"
+        : "=l"(__dest)
+        : "l"(__as_ptr_gmem(__addr))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_acquire && __scope == scope_cluster)
+  {
+    asm("multimem.ld_reduce.acquire.cluster.global.or.b64 %0, [%1];"
+        : "=l"(__dest)
+        : "l"(__as_ptr_gmem(__addr))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_acquire && __scope == scope_gpu)
+  {
+    asm("multimem.ld_reduce.acquire.gpu.global.or.b64 %0, [%1];"
+        : "=l"(__dest)
+        : "l"(__as_ptr_gmem(__addr))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_acquire && __scope == scope_sys)
+  {
+    asm("multimem.ld_reduce.acquire.sys.global.or.b64 %0, [%1];"
+        : "=l"(__dest)
+        : "l"(__as_ptr_gmem(__addr))
+        : "memory");
+  }
+  return *reinterpret_cast<_B64*>(&__dest);
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_multimem_ld_reduce_is_not_supported_before_SM_90__();
+  _CUDA_VSTD::uint64_t __err_out_var = 0;
+  return *reinterpret_cast<_B64*>(&__err_out_var);
+#  endif
+}
+#endif // __cccl_ptx_isa >= 810
+
+/*
+// multimem.ld_reduce.sem.global.op.b64 dest, [addr]; // PTX ISA 81, SM_90
+// .sem       = { .weak }
+// .op        = { .xor }
+template <typename B64, enable_if_t<sizeof(B64) == 8, bool> = true>
+__device__ static inline B64 multimem_ld_reduce(
+  cuda::ptx::sem_weak_t,
+  cuda::ptx::op_xor_op_t,
+  const B64* addr);
+*/
+#if __cccl_ptx_isa >= 810
+extern "C" _CCCL_DEVICE void __cuda_ptx_multimem_ld_reduce_is_not_supported_before_SM_90__();
+template <typename _B64, _CUDA_VSTD::enable_if_t<sizeof(_B64) == 8, bool> = true>
+_CCCL_DEVICE static inline _B64 multimem_ld_reduce(sem_weak_t, op_xor_op_t, const _B64* __addr)
+{
+  // __sem == sem_weak (due to parameter type constraint)
+  // __op == op_xor_op (due to parameter type constraint)
+  static_assert(sizeof(_B64) == 8, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  _CUDA_VSTD::uint64_t __dest;
+  asm("multimem.ld_reduce.weak.global.xor.b64 %0, [%1];" : "=l"(__dest) : "l"(__as_ptr_gmem(__addr)) : "memory");
+  return *reinterpret_cast<_B64*>(&__dest);
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_multimem_ld_reduce_is_not_supported_before_SM_90__();
+  _CUDA_VSTD::uint64_t __err_out_var = 0;
+  return *reinterpret_cast<_B64*>(&__err_out_var);
+#  endif
+}
+#endif // __cccl_ptx_isa >= 810
+
+/*
+// multimem.ld_reduce.sem.scope.global.op.b64 dest, [addr]; // PTX ISA 81, SM_90
+// .sem       = { .relaxed, .acquire }
+// .scope     = { .cta, .cluster, .gpu, .sys }
+// .op        = { .xor }
+template <typename B64, enable_if_t<sizeof(B64) == 8, bool> = true, cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+__device__ static inline B64 multimem_ld_reduce(
+  cuda::ptx::sem_t<Sem> sem,
+  cuda::ptx::scope_t<Scope> scope,
+  cuda::ptx::op_xor_op_t,
+  const B64* addr);
+*/
+#if __cccl_ptx_isa >= 810
+extern "C" _CCCL_DEVICE void __cuda_ptx_multimem_ld_reduce_is_not_supported_before_SM_90__();
+template <typename _B64, _CUDA_VSTD::enable_if_t<sizeof(_B64) == 8, bool> = true, dot_sem _Sem, dot_scope _Scope>
+_CCCL_DEVICE static inline _B64
+multimem_ld_reduce(sem_t<_Sem> __sem, scope_t<_Scope> __scope, op_xor_op_t, const _B64* __addr)
+{
+  static_assert(__sem == sem_relaxed || __sem == sem_acquire, "");
+  static_assert(__scope == scope_cta || __scope == scope_cluster || __scope == scope_gpu || __scope == scope_sys, "");
+  // __op == op_xor_op (due to parameter type constraint)
+  static_assert(sizeof(_B64) == 8, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  _CUDA_VSTD::uint64_t __dest;
+  _CCCL_IF_CONSTEXPR (__sem == sem_relaxed && __scope == scope_cta)
+  {
+    asm("multimem.ld_reduce.relaxed.cta.global.xor.b64 %0, [%1];"
+        : "=l"(__dest)
+        : "l"(__as_ptr_gmem(__addr))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_relaxed && __scope == scope_cluster)
+  {
+    asm("multimem.ld_reduce.relaxed.cluster.global.xor.b64 %0, [%1];"
+        : "=l"(__dest)
+        : "l"(__as_ptr_gmem(__addr))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_relaxed && __scope == scope_gpu)
+  {
+    asm("multimem.ld_reduce.relaxed.gpu.global.xor.b64 %0, [%1];"
+        : "=l"(__dest)
+        : "l"(__as_ptr_gmem(__addr))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_relaxed && __scope == scope_sys)
+  {
+    asm("multimem.ld_reduce.relaxed.sys.global.xor.b64 %0, [%1];"
+        : "=l"(__dest)
+        : "l"(__as_ptr_gmem(__addr))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_acquire && __scope == scope_cta)
+  {
+    asm("multimem.ld_reduce.acquire.cta.global.xor.b64 %0, [%1];"
+        : "=l"(__dest)
+        : "l"(__as_ptr_gmem(__addr))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_acquire && __scope == scope_cluster)
+  {
+    asm("multimem.ld_reduce.acquire.cluster.global.xor.b64 %0, [%1];"
+        : "=l"(__dest)
+        : "l"(__as_ptr_gmem(__addr))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_acquire && __scope == scope_gpu)
+  {
+    asm("multimem.ld_reduce.acquire.gpu.global.xor.b64 %0, [%1];"
+        : "=l"(__dest)
+        : "l"(__as_ptr_gmem(__addr))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_acquire && __scope == scope_sys)
+  {
+    asm("multimem.ld_reduce.acquire.sys.global.xor.b64 %0, [%1];"
+        : "=l"(__dest)
+        : "l"(__as_ptr_gmem(__addr))
+        : "memory");
+  }
+  return *reinterpret_cast<_B64*>(&__dest);
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_multimem_ld_reduce_is_not_supported_before_SM_90__();
+  _CUDA_VSTD::uint64_t __err_out_var = 0;
+  return *reinterpret_cast<_B64*>(&__err_out_var);
+#  endif
+}
+#endif // __cccl_ptx_isa >= 810
+
+#endif // _CUDA_PTX_GENERATED_MULTIMEM_LD_REDUCE_H_
diff --git a/libcudacxx/include/cuda/__ptx/instructions/generated/multimem_red.h b/libcudacxx/include/cuda/__ptx/instructions/generated/multimem_red.h
new file mode 100644
index 00000000000..1ef97121d31
--- /dev/null
+++ b/libcudacxx/include/cuda/__ptx/instructions/generated/multimem_red.h
@@ -0,0 +1,1272 @@
+// This file was automatically generated. Do not edit.
+
+#ifndef _CUDA_PTX_GENERATED_MULTIMEM_RED_H_
+#define _CUDA_PTX_GENERATED_MULTIMEM_RED_H_
+
+/*
+// multimem.red.sem.scope.global.op.u32 [addr], val; // PTX ISA 81, SM_90
+// .sem       = { .relaxed, .release }
+// .scope     = { .cta, .cluster, .gpu, .sys }
+// .op        = { .min }
+template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+__device__ static inline void multimem_red(
+  cuda::ptx::sem_t<Sem> sem,
+  cuda::ptx::scope_t<Scope> scope,
+  cuda::ptx::op_min_t,
+  uint32_t* addr,
+  uint32_t val);
+*/
+#if __cccl_ptx_isa >= 810
+extern "C" _CCCL_DEVICE void __cuda_ptx_multimem_red_is_not_supported_before_SM_90__();
+template <dot_sem _Sem, dot_scope _Scope>
+_CCCL_DEVICE static inline void multimem_red(
+  sem_t<_Sem> __sem, scope_t<_Scope> __scope, op_min_t, _CUDA_VSTD::uint32_t* __addr, _CUDA_VSTD::uint32_t __val)
+{
+  static_assert(__sem == sem_relaxed || __sem == sem_release, "");
+  static_assert(__scope == scope_cta || __scope == scope_cluster || __scope == scope_gpu || __scope == scope_sys, "");
+// __op == op_min (due to parameter type constraint)
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  _CCCL_IF_CONSTEXPR (__sem == sem_relaxed && __scope == scope_cta)
+  {
+    asm("multimem.red.relaxed.cta.global.min.u32 [%0], %1;" : : "l"(__as_ptr_gmem(__addr)), "r"(__val) : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_relaxed && __scope == scope_cluster)
+  {
+    asm("multimem.red.relaxed.cluster.global.min.u32 [%0], %1;" : : "l"(__as_ptr_gmem(__addr)), "r"(__val) : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_relaxed && __scope == scope_gpu)
+  {
+    asm("multimem.red.relaxed.gpu.global.min.u32 [%0], %1;" : : "l"(__as_ptr_gmem(__addr)), "r"(__val) : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_relaxed && __scope == scope_sys)
+  {
+    asm("multimem.red.relaxed.sys.global.min.u32 [%0], %1;" : : "l"(__as_ptr_gmem(__addr)), "r"(__val) : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_release && __scope == scope_cta)
+  {
+    asm("multimem.red.release.cta.global.min.u32 [%0], %1;" : : "l"(__as_ptr_gmem(__addr)), "r"(__val) : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_release && __scope == scope_cluster)
+  {
+    asm("multimem.red.release.cluster.global.min.u32 [%0], %1;" : : "l"(__as_ptr_gmem(__addr)), "r"(__val) : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_release && __scope == scope_gpu)
+  {
+    asm("multimem.red.release.gpu.global.min.u32 [%0], %1;" : : "l"(__as_ptr_gmem(__addr)), "r"(__val) : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_release && __scope == scope_sys)
+  {
+    asm("multimem.red.release.sys.global.min.u32 [%0], %1;" : : "l"(__as_ptr_gmem(__addr)), "r"(__val) : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_multimem_red_is_not_supported_before_SM_90__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 810
+
+/*
+// multimem.red.sem.scope.global.op.u64 [addr], val; // PTX ISA 81, SM_90
+// .sem       = { .relaxed, .release }
+// .scope     = { .cta, .cluster, .gpu, .sys }
+// .op        = { .min }
+template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+__device__ static inline void multimem_red(
+  cuda::ptx::sem_t<Sem> sem,
+  cuda::ptx::scope_t<Scope> scope,
+  cuda::ptx::op_min_t,
+  uint64_t* addr,
+  uint64_t val);
+*/
+#if __cccl_ptx_isa >= 810
+extern "C" _CCCL_DEVICE void __cuda_ptx_multimem_red_is_not_supported_before_SM_90__();
+template <dot_sem _Sem, dot_scope _Scope>
+_CCCL_DEVICE static inline void multimem_red(
+  sem_t<_Sem> __sem, scope_t<_Scope> __scope, op_min_t, _CUDA_VSTD::uint64_t* __addr, _CUDA_VSTD::uint64_t __val)
+{
+  static_assert(__sem == sem_relaxed || __sem == sem_release, "");
+  static_assert(__scope == scope_cta || __scope == scope_cluster || __scope == scope_gpu || __scope == scope_sys, "");
+// __op == op_min (due to parameter type constraint)
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  _CCCL_IF_CONSTEXPR (__sem == sem_relaxed && __scope == scope_cta)
+  {
+    asm("multimem.red.relaxed.cta.global.min.u64 [%0], %1;" : : "l"(__as_ptr_gmem(__addr)), "l"(__val) : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_relaxed && __scope == scope_cluster)
+  {
+    asm("multimem.red.relaxed.cluster.global.min.u64 [%0], %1;" : : "l"(__as_ptr_gmem(__addr)), "l"(__val) : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_relaxed && __scope == scope_gpu)
+  {
+    asm("multimem.red.relaxed.gpu.global.min.u64 [%0], %1;" : : "l"(__as_ptr_gmem(__addr)), "l"(__val) : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_relaxed && __scope == scope_sys)
+  {
+    asm("multimem.red.relaxed.sys.global.min.u64 [%0], %1;" : : "l"(__as_ptr_gmem(__addr)), "l"(__val) : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_release && __scope == scope_cta)
+  {
+    asm("multimem.red.release.cta.global.min.u64 [%0], %1;" : : "l"(__as_ptr_gmem(__addr)), "l"(__val) : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_release && __scope == scope_cluster)
+  {
+    asm("multimem.red.release.cluster.global.min.u64 [%0], %1;" : : "l"(__as_ptr_gmem(__addr)), "l"(__val) : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_release && __scope == scope_gpu)
+  {
+    asm("multimem.red.release.gpu.global.min.u64 [%0], %1;" : : "l"(__as_ptr_gmem(__addr)), "l"(__val) : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_release && __scope == scope_sys)
+  {
+    asm("multimem.red.release.sys.global.min.u64 [%0], %1;" : : "l"(__as_ptr_gmem(__addr)), "l"(__val) : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_multimem_red_is_not_supported_before_SM_90__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 810
+
+/*
+// multimem.red.sem.scope.global.op.s32 [addr], val; // PTX ISA 81, SM_90
+// .sem       = { .relaxed, .release }
+// .scope     = { .cta, .cluster, .gpu, .sys }
+// .op        = { .min }
+template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+__device__ static inline void multimem_red(
+  cuda::ptx::sem_t<Sem> sem,
+  cuda::ptx::scope_t<Scope> scope,
+  cuda::ptx::op_min_t,
+  int32_t* addr,
+  int32_t val);
+*/
+#if __cccl_ptx_isa >= 810
+extern "C" _CCCL_DEVICE void __cuda_ptx_multimem_red_is_not_supported_before_SM_90__();
+template <dot_sem _Sem, dot_scope _Scope>
+_CCCL_DEVICE static inline void multimem_red(
+  sem_t<_Sem> __sem, scope_t<_Scope> __scope, op_min_t, _CUDA_VSTD::int32_t* __addr, _CUDA_VSTD::int32_t __val)
+{
+  static_assert(__sem == sem_relaxed || __sem == sem_release, "");
+  static_assert(__scope == scope_cta || __scope == scope_cluster || __scope == scope_gpu || __scope == scope_sys, "");
+// __op == op_min (due to parameter type constraint)
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  _CCCL_IF_CONSTEXPR (__sem == sem_relaxed && __scope == scope_cta)
+  {
+    asm("multimem.red.relaxed.cta.global.min.s32 [%0], %1;" : : "l"(__as_ptr_gmem(__addr)), "r"(__val) : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_relaxed && __scope == scope_cluster)
+  {
+    asm("multimem.red.relaxed.cluster.global.min.s32 [%0], %1;" : : "l"(__as_ptr_gmem(__addr)), "r"(__val) : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_relaxed && __scope == scope_gpu)
+  {
+    asm("multimem.red.relaxed.gpu.global.min.s32 [%0], %1;" : : "l"(__as_ptr_gmem(__addr)), "r"(__val) : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_relaxed && __scope == scope_sys)
+  {
+    asm("multimem.red.relaxed.sys.global.min.s32 [%0], %1;" : : "l"(__as_ptr_gmem(__addr)), "r"(__val) : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_release && __scope == scope_cta)
+  {
+    asm("multimem.red.release.cta.global.min.s32 [%0], %1;" : : "l"(__as_ptr_gmem(__addr)), "r"(__val) : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_release && __scope == scope_cluster)
+  {
+    asm("multimem.red.release.cluster.global.min.s32 [%0], %1;" : : "l"(__as_ptr_gmem(__addr)), "r"(__val) : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_release && __scope == scope_gpu)
+  {
+    asm("multimem.red.release.gpu.global.min.s32 [%0], %1;" : : "l"(__as_ptr_gmem(__addr)), "r"(__val) : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_release && __scope == scope_sys)
+  {
+    asm("multimem.red.release.sys.global.min.s32 [%0], %1;" : : "l"(__as_ptr_gmem(__addr)), "r"(__val) : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_multimem_red_is_not_supported_before_SM_90__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 810
+
+/*
+// multimem.red.sem.scope.global.op.s64 [addr], val; // PTX ISA 81, SM_90
+// .sem       = { .relaxed, .release }
+// .scope     = { .cta, .cluster, .gpu, .sys }
+// .op        = { .min }
+template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+__device__ static inline void multimem_red(
+  cuda::ptx::sem_t<Sem> sem,
+  cuda::ptx::scope_t<Scope> scope,
+  cuda::ptx::op_min_t,
+  int64_t* addr,
+  int64_t val);
+*/
+#if __cccl_ptx_isa >= 810
+extern "C" _CCCL_DEVICE void __cuda_ptx_multimem_red_is_not_supported_before_SM_90__();
+template <dot_sem _Sem, dot_scope _Scope>
+_CCCL_DEVICE static inline void multimem_red(
+  sem_t<_Sem> __sem, scope_t<_Scope> __scope, op_min_t, _CUDA_VSTD::int64_t* __addr, _CUDA_VSTD::int64_t __val)
+{
+  static_assert(__sem == sem_relaxed || __sem == sem_release, "");
+  static_assert(__scope == scope_cta || __scope == scope_cluster || __scope == scope_gpu || __scope == scope_sys, "");
+// __op == op_min (due to parameter type constraint)
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  _CCCL_IF_CONSTEXPR (__sem == sem_relaxed && __scope == scope_cta)
+  {
+    asm("multimem.red.relaxed.cta.global.min.s64 [%0], %1;" : : "l"(__as_ptr_gmem(__addr)), "l"(__val) : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_relaxed && __scope == scope_cluster)
+  {
+    asm("multimem.red.relaxed.cluster.global.min.s64 [%0], %1;" : : "l"(__as_ptr_gmem(__addr)), "l"(__val) : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_relaxed && __scope == scope_gpu)
+  {
+    asm("multimem.red.relaxed.gpu.global.min.s64 [%0], %1;" : : "l"(__as_ptr_gmem(__addr)), "l"(__val) : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_relaxed && __scope == scope_sys)
+  {
+    asm("multimem.red.relaxed.sys.global.min.s64 [%0], %1;" : : "l"(__as_ptr_gmem(__addr)), "l"(__val) : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_release && __scope == scope_cta)
+  {
+    asm("multimem.red.release.cta.global.min.s64 [%0], %1;" : : "l"(__as_ptr_gmem(__addr)), "l"(__val) : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_release && __scope == scope_cluster)
+  {
+    asm("multimem.red.release.cluster.global.min.s64 [%0], %1;" : : "l"(__as_ptr_gmem(__addr)), "l"(__val) : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_release && __scope == scope_gpu)
+  {
+    asm("multimem.red.release.gpu.global.min.s64 [%0], %1;" : : "l"(__as_ptr_gmem(__addr)), "l"(__val) : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_release && __scope == scope_sys)
+  {
+    asm("multimem.red.release.sys.global.min.s64 [%0], %1;" : : "l"(__as_ptr_gmem(__addr)), "l"(__val) : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_multimem_red_is_not_supported_before_SM_90__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 810
+
+/*
+// multimem.red.sem.scope.global.op.u32 [addr], val; // PTX ISA 81, SM_90
+// .sem       = { .relaxed, .release }
+// .scope     = { .cta, .cluster, .gpu, .sys }
+// .op        = { .max }
+template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+__device__ static inline void multimem_red(
+  cuda::ptx::sem_t<Sem> sem,
+  cuda::ptx::scope_t<Scope> scope,
+  cuda::ptx::op_max_t,
+  uint32_t* addr,
+  uint32_t val);
+*/
+#if __cccl_ptx_isa >= 810
+extern "C" _CCCL_DEVICE void __cuda_ptx_multimem_red_is_not_supported_before_SM_90__();
+template <dot_sem _Sem, dot_scope _Scope>
+_CCCL_DEVICE static inline void multimem_red(
+  sem_t<_Sem> __sem, scope_t<_Scope> __scope, op_max_t, _CUDA_VSTD::uint32_t* __addr, _CUDA_VSTD::uint32_t __val)
+{
+  static_assert(__sem == sem_relaxed || __sem == sem_release, "");
+  static_assert(__scope == scope_cta || __scope == scope_cluster || __scope == scope_gpu || __scope == scope_sys, "");
+// __op == op_max (due to parameter type constraint)
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  _CCCL_IF_CONSTEXPR (__sem == sem_relaxed && __scope == scope_cta)
+  {
+    asm("multimem.red.relaxed.cta.global.max.u32 [%0], %1;" : : "l"(__as_ptr_gmem(__addr)), "r"(__val) : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_relaxed && __scope == scope_cluster)
+  {
+    asm("multimem.red.relaxed.cluster.global.max.u32 [%0], %1;" : : "l"(__as_ptr_gmem(__addr)), "r"(__val) : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_relaxed && __scope == scope_gpu)
+  {
+    asm("multimem.red.relaxed.gpu.global.max.u32 [%0], %1;" : : "l"(__as_ptr_gmem(__addr)), "r"(__val) : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_relaxed && __scope == scope_sys)
+  {
+    asm("multimem.red.relaxed.sys.global.max.u32 [%0], %1;" : : "l"(__as_ptr_gmem(__addr)), "r"(__val) : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_release && __scope == scope_cta)
+  {
+    asm("multimem.red.release.cta.global.max.u32 [%0], %1;" : : "l"(__as_ptr_gmem(__addr)), "r"(__val) : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_release && __scope == scope_cluster)
+  {
+    asm("multimem.red.release.cluster.global.max.u32 [%0], %1;" : : "l"(__as_ptr_gmem(__addr)), "r"(__val) : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_release && __scope == scope_gpu)
+  {
+    asm("multimem.red.release.gpu.global.max.u32 [%0], %1;" : : "l"(__as_ptr_gmem(__addr)), "r"(__val) : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_release && __scope == scope_sys)
+  {
+    asm("multimem.red.release.sys.global.max.u32 [%0], %1;" : : "l"(__as_ptr_gmem(__addr)), "r"(__val) : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_multimem_red_is_not_supported_before_SM_90__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 810
+
+/*
+// multimem.red.sem.scope.global.op.u64 [addr], val; // PTX ISA 81, SM_90
+// .sem       = { .relaxed, .release }
+// .scope     = { .cta, .cluster, .gpu, .sys }
+// .op        = { .max }
+template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+__device__ static inline void multimem_red(
+  cuda::ptx::sem_t<Sem> sem,
+  cuda::ptx::scope_t<Scope> scope,
+  cuda::ptx::op_max_t,
+  uint64_t* addr,
+  uint64_t val);
+*/
+#if __cccl_ptx_isa >= 810
+extern "C" _CCCL_DEVICE void __cuda_ptx_multimem_red_is_not_supported_before_SM_90__();
+template <dot_sem _Sem, dot_scope _Scope>
+_CCCL_DEVICE static inline void multimem_red(
+  sem_t<_Sem> __sem, scope_t<_Scope> __scope, op_max_t, _CUDA_VSTD::uint64_t* __addr, _CUDA_VSTD::uint64_t __val)
+{
+  static_assert(__sem == sem_relaxed || __sem == sem_release, "");
+  static_assert(__scope == scope_cta || __scope == scope_cluster || __scope == scope_gpu || __scope == scope_sys, "");
+// __op == op_max (due to parameter type constraint)
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  _CCCL_IF_CONSTEXPR (__sem == sem_relaxed && __scope == scope_cta)
+  {
+    asm("multimem.red.relaxed.cta.global.max.u64 [%0], %1;" : : "l"(__as_ptr_gmem(__addr)), "l"(__val) : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_relaxed && __scope == scope_cluster)
+  {
+    asm("multimem.red.relaxed.cluster.global.max.u64 [%0], %1;" : : "l"(__as_ptr_gmem(__addr)), "l"(__val) : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_relaxed && __scope == scope_gpu)
+  {
+    asm("multimem.red.relaxed.gpu.global.max.u64 [%0], %1;" : : "l"(__as_ptr_gmem(__addr)), "l"(__val) : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_relaxed && __scope == scope_sys)
+  {
+    asm("multimem.red.relaxed.sys.global.max.u64 [%0], %1;" : : "l"(__as_ptr_gmem(__addr)), "l"(__val) : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_release && __scope == scope_cta)
+  {
+    asm("multimem.red.release.cta.global.max.u64 [%0], %1;" : : "l"(__as_ptr_gmem(__addr)), "l"(__val) : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_release && __scope == scope_cluster)
+  {
+    asm("multimem.red.release.cluster.global.max.u64 [%0], %1;" : : "l"(__as_ptr_gmem(__addr)), "l"(__val) : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_release && __scope == scope_gpu)
+  {
+    asm("multimem.red.release.gpu.global.max.u64 [%0], %1;" : : "l"(__as_ptr_gmem(__addr)), "l"(__val) : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_release && __scope == scope_sys)
+  {
+    asm("multimem.red.release.sys.global.max.u64 [%0], %1;" : : "l"(__as_ptr_gmem(__addr)), "l"(__val) : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_multimem_red_is_not_supported_before_SM_90__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 810
+
+/*
+// multimem.red.sem.scope.global.op.s32 [addr], val; // PTX ISA 81, SM_90
+// .sem       = { .relaxed, .release }
+// .scope     = { .cta, .cluster, .gpu, .sys }
+// .op        = { .max }
+template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+__device__ static inline void multimem_red(
+  cuda::ptx::sem_t<Sem> sem,
+  cuda::ptx::scope_t<Scope> scope,
+  cuda::ptx::op_max_t,
+  int32_t* addr,
+  int32_t val);
+*/
+#if __cccl_ptx_isa >= 810
+extern "C" _CCCL_DEVICE void __cuda_ptx_multimem_red_is_not_supported_before_SM_90__();
+template <dot_sem _Sem, dot_scope _Scope>
+_CCCL_DEVICE static inline void multimem_red(
+  sem_t<_Sem> __sem, scope_t<_Scope> __scope, op_max_t, _CUDA_VSTD::int32_t* __addr, _CUDA_VSTD::int32_t __val)
+{
+  static_assert(__sem == sem_relaxed || __sem == sem_release, "");
+  static_assert(__scope == scope_cta || __scope == scope_cluster || __scope == scope_gpu || __scope == scope_sys, "");
+// __op == op_max (due to parameter type constraint)
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  _CCCL_IF_CONSTEXPR (__sem == sem_relaxed && __scope == scope_cta)
+  {
+    asm("multimem.red.relaxed.cta.global.max.s32 [%0], %1;" : : "l"(__as_ptr_gmem(__addr)), "r"(__val) : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_relaxed && __scope == scope_cluster)
+  {
+    asm("multimem.red.relaxed.cluster.global.max.s32 [%0], %1;" : : "l"(__as_ptr_gmem(__addr)), "r"(__val) : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_relaxed && __scope == scope_gpu)
+  {
+    asm("multimem.red.relaxed.gpu.global.max.s32 [%0], %1;" : : "l"(__as_ptr_gmem(__addr)), "r"(__val) : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_relaxed && __scope == scope_sys)
+  {
+    asm("multimem.red.relaxed.sys.global.max.s32 [%0], %1;" : : "l"(__as_ptr_gmem(__addr)), "r"(__val) : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_release && __scope == scope_cta)
+  {
+    asm("multimem.red.release.cta.global.max.s32 [%0], %1;" : : "l"(__as_ptr_gmem(__addr)), "r"(__val) : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_release && __scope == scope_cluster)
+  {
+    asm("multimem.red.release.cluster.global.max.s32 [%0], %1;" : : "l"(__as_ptr_gmem(__addr)), "r"(__val) : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_release && __scope == scope_gpu)
+  {
+    asm("multimem.red.release.gpu.global.max.s32 [%0], %1;" : : "l"(__as_ptr_gmem(__addr)), "r"(__val) : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_release && __scope == scope_sys)
+  {
+    asm("multimem.red.release.sys.global.max.s32 [%0], %1;" : : "l"(__as_ptr_gmem(__addr)), "r"(__val) : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_multimem_red_is_not_supported_before_SM_90__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 810
+
+/*
+// multimem.red.sem.scope.global.op.s64 [addr], val; // PTX ISA 81, SM_90
+// .sem       = { .relaxed, .release }
+// .scope     = { .cta, .cluster, .gpu, .sys }
+// .op        = { .max }
+template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+__device__ static inline void multimem_red(
+  cuda::ptx::sem_t<Sem> sem,
+  cuda::ptx::scope_t<Scope> scope,
+  cuda::ptx::op_max_t,
+  int64_t* addr,
+  int64_t val);
+*/
+#if __cccl_ptx_isa >= 810
+extern "C" _CCCL_DEVICE void __cuda_ptx_multimem_red_is_not_supported_before_SM_90__();
+template <dot_sem _Sem, dot_scope _Scope>
+_CCCL_DEVICE static inline void multimem_red(
+  sem_t<_Sem> __sem, scope_t<_Scope> __scope, op_max_t, _CUDA_VSTD::int64_t* __addr, _CUDA_VSTD::int64_t __val)
+{
+  static_assert(__sem == sem_relaxed || __sem == sem_release, "");
+  static_assert(__scope == scope_cta || __scope == scope_cluster || __scope == scope_gpu || __scope == scope_sys, "");
+// __op == op_max (due to parameter type constraint)
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  _CCCL_IF_CONSTEXPR (__sem == sem_relaxed && __scope == scope_cta)
+  {
+    asm("multimem.red.relaxed.cta.global.max.s64 [%0], %1;" : : "l"(__as_ptr_gmem(__addr)), "l"(__val) : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_relaxed && __scope == scope_cluster)
+  {
+    asm("multimem.red.relaxed.cluster.global.max.s64 [%0], %1;" : : "l"(__as_ptr_gmem(__addr)), "l"(__val) : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_relaxed && __scope == scope_gpu)
+  {
+    asm("multimem.red.relaxed.gpu.global.max.s64 [%0], %1;" : : "l"(__as_ptr_gmem(__addr)), "l"(__val) : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_relaxed && __scope == scope_sys)
+  {
+    asm("multimem.red.relaxed.sys.global.max.s64 [%0], %1;" : : "l"(__as_ptr_gmem(__addr)), "l"(__val) : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_release && __scope == scope_cta)
+  {
+    asm("multimem.red.release.cta.global.max.s64 [%0], %1;" : : "l"(__as_ptr_gmem(__addr)), "l"(__val) : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_release && __scope == scope_cluster)
+  {
+    asm("multimem.red.release.cluster.global.max.s64 [%0], %1;" : : "l"(__as_ptr_gmem(__addr)), "l"(__val) : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_release && __scope == scope_gpu)
+  {
+    asm("multimem.red.release.gpu.global.max.s64 [%0], %1;" : : "l"(__as_ptr_gmem(__addr)), "l"(__val) : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_release && __scope == scope_sys)
+  {
+    asm("multimem.red.release.sys.global.max.s64 [%0], %1;" : : "l"(__as_ptr_gmem(__addr)), "l"(__val) : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_multimem_red_is_not_supported_before_SM_90__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 810
+
+/*
+// multimem.red.sem.scope.global.op.u32 [addr], val; // PTX ISA 81, SM_90
+// .sem       = { .relaxed, .release }
+// .scope     = { .cta, .cluster, .gpu, .sys }
+// .op        = { .add }
+template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+__device__ static inline void multimem_red(
+  cuda::ptx::sem_t<Sem> sem,
+  cuda::ptx::scope_t<Scope> scope,
+  cuda::ptx::op_add_t,
+  uint32_t* addr,
+  uint32_t val);
+*/
+#if __cccl_ptx_isa >= 810
+extern "C" _CCCL_DEVICE void __cuda_ptx_multimem_red_is_not_supported_before_SM_90__();
+template <dot_sem _Sem, dot_scope _Scope>
+_CCCL_DEVICE static inline void multimem_red(
+  sem_t<_Sem> __sem, scope_t<_Scope> __scope, op_add_t, _CUDA_VSTD::uint32_t* __addr, _CUDA_VSTD::uint32_t __val)
+{
+  static_assert(__sem == sem_relaxed || __sem == sem_release, "");
+  static_assert(__scope == scope_cta || __scope == scope_cluster || __scope == scope_gpu || __scope == scope_sys, "");
+// __op == op_add (due to parameter type constraint)
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  _CCCL_IF_CONSTEXPR (__sem == sem_relaxed && __scope == scope_cta)
+  {
+    asm("multimem.red.relaxed.cta.global.add.u32 [%0], %1;" : : "l"(__as_ptr_gmem(__addr)), "r"(__val) : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_relaxed && __scope == scope_cluster)
+  {
+    asm("multimem.red.relaxed.cluster.global.add.u32 [%0], %1;" : : "l"(__as_ptr_gmem(__addr)), "r"(__val) : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_relaxed && __scope == scope_gpu)
+  {
+    asm("multimem.red.relaxed.gpu.global.add.u32 [%0], %1;" : : "l"(__as_ptr_gmem(__addr)), "r"(__val) : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_relaxed && __scope == scope_sys)
+  {
+    asm("multimem.red.relaxed.sys.global.add.u32 [%0], %1;" : : "l"(__as_ptr_gmem(__addr)), "r"(__val) : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_release && __scope == scope_cta)
+  {
+    asm("multimem.red.release.cta.global.add.u32 [%0], %1;" : : "l"(__as_ptr_gmem(__addr)), "r"(__val) : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_release && __scope == scope_cluster)
+  {
+    asm("multimem.red.release.cluster.global.add.u32 [%0], %1;" : : "l"(__as_ptr_gmem(__addr)), "r"(__val) : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_release && __scope == scope_gpu)
+  {
+    asm("multimem.red.release.gpu.global.add.u32 [%0], %1;" : : "l"(__as_ptr_gmem(__addr)), "r"(__val) : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_release && __scope == scope_sys)
+  {
+    asm("multimem.red.release.sys.global.add.u32 [%0], %1;" : : "l"(__as_ptr_gmem(__addr)), "r"(__val) : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_multimem_red_is_not_supported_before_SM_90__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 810
+
+/*
+// multimem.red.sem.scope.global.op.u64 [addr], val; // PTX ISA 81, SM_90
+// .sem       = { .relaxed, .release }
+// .scope     = { .cta, .cluster, .gpu, .sys }
+// .op        = { .add }
+template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+__device__ static inline void multimem_red(
+  cuda::ptx::sem_t<Sem> sem,
+  cuda::ptx::scope_t<Scope> scope,
+  cuda::ptx::op_add_t,
+  uint64_t* addr,
+  uint64_t val);
+*/
+#if __cccl_ptx_isa >= 810
+extern "C" _CCCL_DEVICE void __cuda_ptx_multimem_red_is_not_supported_before_SM_90__();
+template <dot_sem _Sem, dot_scope _Scope>
+_CCCL_DEVICE static inline void multimem_red(
+  sem_t<_Sem> __sem, scope_t<_Scope> __scope, op_add_t, _CUDA_VSTD::uint64_t* __addr, _CUDA_VSTD::uint64_t __val)
+{
+  static_assert(__sem == sem_relaxed || __sem == sem_release, "");
+  static_assert(__scope == scope_cta || __scope == scope_cluster || __scope == scope_gpu || __scope == scope_sys, "");
+// __op == op_add (due to parameter type constraint)
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  _CCCL_IF_CONSTEXPR (__sem == sem_relaxed && __scope == scope_cta)
+  {
+    asm("multimem.red.relaxed.cta.global.add.u64 [%0], %1;" : : "l"(__as_ptr_gmem(__addr)), "l"(__val) : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_relaxed && __scope == scope_cluster)
+  {
+    asm("multimem.red.relaxed.cluster.global.add.u64 [%0], %1;" : : "l"(__as_ptr_gmem(__addr)), "l"(__val) : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_relaxed && __scope == scope_gpu)
+  {
+    asm("multimem.red.relaxed.gpu.global.add.u64 [%0], %1;" : : "l"(__as_ptr_gmem(__addr)), "l"(__val) : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_relaxed && __scope == scope_sys)
+  {
+    asm("multimem.red.relaxed.sys.global.add.u64 [%0], %1;" : : "l"(__as_ptr_gmem(__addr)), "l"(__val) : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_release && __scope == scope_cta)
+  {
+    asm("multimem.red.release.cta.global.add.u64 [%0], %1;" : : "l"(__as_ptr_gmem(__addr)), "l"(__val) : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_release && __scope == scope_cluster)
+  {
+    asm("multimem.red.release.cluster.global.add.u64 [%0], %1;" : : "l"(__as_ptr_gmem(__addr)), "l"(__val) : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_release && __scope == scope_gpu)
+  {
+    asm("multimem.red.release.gpu.global.add.u64 [%0], %1;" : : "l"(__as_ptr_gmem(__addr)), "l"(__val) : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_release && __scope == scope_sys)
+  {
+    asm("multimem.red.release.sys.global.add.u64 [%0], %1;" : : "l"(__as_ptr_gmem(__addr)), "l"(__val) : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_multimem_red_is_not_supported_before_SM_90__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 810
+
+/*
+// multimem.red.sem.scope.global.op.s32 [addr], val; // PTX ISA 81, SM_90
+// .sem       = { .relaxed, .release }
+// .scope     = { .cta, .cluster, .gpu, .sys }
+// .op        = { .add }
+template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+__device__ static inline void multimem_red(
+  cuda::ptx::sem_t<Sem> sem,
+  cuda::ptx::scope_t<Scope> scope,
+  cuda::ptx::op_add_t,
+  int32_t* addr,
+  int32_t val);
+*/
+#if __cccl_ptx_isa >= 810
+extern "C" _CCCL_DEVICE void __cuda_ptx_multimem_red_is_not_supported_before_SM_90__();
+template <dot_sem _Sem, dot_scope _Scope>
+_CCCL_DEVICE static inline void multimem_red(
+  sem_t<_Sem> __sem, scope_t<_Scope> __scope, op_add_t, _CUDA_VSTD::int32_t* __addr, _CUDA_VSTD::int32_t __val)
+{
+  static_assert(__sem == sem_relaxed || __sem == sem_release, "");
+  static_assert(__scope == scope_cta || __scope == scope_cluster || __scope == scope_gpu || __scope == scope_sys, "");
+// __op == op_add (due to parameter type constraint)
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  _CCCL_IF_CONSTEXPR (__sem == sem_relaxed && __scope == scope_cta)
+  {
+    asm("multimem.red.relaxed.cta.global.add.s32 [%0], %1;" : : "l"(__as_ptr_gmem(__addr)), "r"(__val) : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_relaxed && __scope == scope_cluster)
+  {
+    asm("multimem.red.relaxed.cluster.global.add.s32 [%0], %1;" : : "l"(__as_ptr_gmem(__addr)), "r"(__val) : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_relaxed && __scope == scope_gpu)
+  {
+    asm("multimem.red.relaxed.gpu.global.add.s32 [%0], %1;" : : "l"(__as_ptr_gmem(__addr)), "r"(__val) : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_relaxed && __scope == scope_sys)
+  {
+    asm("multimem.red.relaxed.sys.global.add.s32 [%0], %1;" : : "l"(__as_ptr_gmem(__addr)), "r"(__val) : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_release && __scope == scope_cta)
+  {
+    asm("multimem.red.release.cta.global.add.s32 [%0], %1;" : : "l"(__as_ptr_gmem(__addr)), "r"(__val) : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_release && __scope == scope_cluster)
+  {
+    asm("multimem.red.release.cluster.global.add.s32 [%0], %1;" : : "l"(__as_ptr_gmem(__addr)), "r"(__val) : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_release && __scope == scope_gpu)
+  {
+    asm("multimem.red.release.gpu.global.add.s32 [%0], %1;" : : "l"(__as_ptr_gmem(__addr)), "r"(__val) : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_release && __scope == scope_sys)
+  {
+    asm("multimem.red.release.sys.global.add.s32 [%0], %1;" : : "l"(__as_ptr_gmem(__addr)), "r"(__val) : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_multimem_red_is_not_supported_before_SM_90__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 810
+
+/*
+// multimem.red.sem.scope.global.op.u64 [addr], val; // PTX ISA 81, SM_90
+// .sem       = { .relaxed, .release }
+// .scope     = { .cta, .cluster, .gpu, .sys }
+// .op        = { .add }
+template <cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+__device__ static inline void multimem_red(
+  cuda::ptx::sem_t<Sem> sem,
+  cuda::ptx::scope_t<Scope> scope,
+  cuda::ptx::op_add_t,
+  int64_t* addr,
+  int64_t val);
+*/
+#if __cccl_ptx_isa >= 810
+extern "C" _CCCL_DEVICE void __cuda_ptx_multimem_red_is_not_supported_before_SM_90__();
+template <dot_sem _Sem, dot_scope _Scope>
+_CCCL_DEVICE static inline void multimem_red(
+  sem_t<_Sem> __sem, scope_t<_Scope> __scope, op_add_t, _CUDA_VSTD::int64_t* __addr, _CUDA_VSTD::int64_t __val)
+{
+  static_assert(__sem == sem_relaxed || __sem == sem_release, "");
+  static_assert(__scope == scope_cta || __scope == scope_cluster || __scope == scope_gpu || __scope == scope_sys, "");
+// __op == op_add (due to parameter type constraint)
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  _CCCL_IF_CONSTEXPR (__sem == sem_relaxed && __scope == scope_cta)
+  {
+    asm("multimem.red.relaxed.cta.global.add.u64 [%0], %1;" : : "l"(__as_ptr_gmem(__addr)), "l"(__val) : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_relaxed && __scope == scope_cluster)
+  {
+    asm("multimem.red.relaxed.cluster.global.add.u64 [%0], %1;" : : "l"(__as_ptr_gmem(__addr)), "l"(__val) : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_relaxed && __scope == scope_gpu)
+  {
+    asm("multimem.red.relaxed.gpu.global.add.u64 [%0], %1;" : : "l"(__as_ptr_gmem(__addr)), "l"(__val) : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_relaxed && __scope == scope_sys)
+  {
+    asm("multimem.red.relaxed.sys.global.add.u64 [%0], %1;" : : "l"(__as_ptr_gmem(__addr)), "l"(__val) : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_release && __scope == scope_cta)
+  {
+    asm("multimem.red.release.cta.global.add.u64 [%0], %1;" : : "l"(__as_ptr_gmem(__addr)), "l"(__val) : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_release && __scope == scope_cluster)
+  {
+    asm("multimem.red.release.cluster.global.add.u64 [%0], %1;" : : "l"(__as_ptr_gmem(__addr)), "l"(__val) : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_release && __scope == scope_gpu)
+  {
+    asm("multimem.red.release.gpu.global.add.u64 [%0], %1;" : : "l"(__as_ptr_gmem(__addr)), "l"(__val) : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_release && __scope == scope_sys)
+  {
+    asm("multimem.red.release.sys.global.add.u64 [%0], %1;" : : "l"(__as_ptr_gmem(__addr)), "l"(__val) : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_multimem_red_is_not_supported_before_SM_90__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 810
+
+/*
+// multimem.red.sem.scope.global.op.b32 [addr], val; // PTX ISA 81, SM_90
+// .sem       = { .relaxed, .release }
+// .scope     = { .cta, .cluster, .gpu, .sys }
+// .op        = { .and }
+template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true, cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+__device__ static inline void multimem_red(
+  cuda::ptx::sem_t<Sem> sem,
+  cuda::ptx::scope_t<Scope> scope,
+  cuda::ptx::op_and_op_t,
+  B32* addr,
+  B32 val);
+*/
+#if __cccl_ptx_isa >= 810
+extern "C" _CCCL_DEVICE void __cuda_ptx_multimem_red_is_not_supported_before_SM_90__();
+template <typename _B32, _CUDA_VSTD::enable_if_t<sizeof(_B32) == 4, bool> = true, dot_sem _Sem, dot_scope _Scope>
+_CCCL_DEVICE static inline void
+multimem_red(sem_t<_Sem> __sem, scope_t<_Scope> __scope, op_and_op_t, _B32* __addr, _B32 __val)
+{
+  static_assert(__sem == sem_relaxed || __sem == sem_release, "");
+  static_assert(__scope == scope_cta || __scope == scope_cluster || __scope == scope_gpu || __scope == scope_sys, "");
+  // __op == op_and_op (due to parameter type constraint)
+  static_assert(sizeof(_B32) == 4, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  _CCCL_IF_CONSTEXPR (__sem == sem_relaxed && __scope == scope_cta)
+  {
+    asm("multimem.red.relaxed.cta.global.and.b32 [%0], %1;"
+        :
+        : "l"(__as_ptr_gmem(__addr)), "r"(__as_b32(__val))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_relaxed && __scope == scope_cluster)
+  {
+    asm("multimem.red.relaxed.cluster.global.and.b32 [%0], %1;"
+        :
+        : "l"(__as_ptr_gmem(__addr)), "r"(__as_b32(__val))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_relaxed && __scope == scope_gpu)
+  {
+    asm("multimem.red.relaxed.gpu.global.and.b32 [%0], %1;"
+        :
+        : "l"(__as_ptr_gmem(__addr)), "r"(__as_b32(__val))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_relaxed && __scope == scope_sys)
+  {
+    asm("multimem.red.relaxed.sys.global.and.b32 [%0], %1;"
+        :
+        : "l"(__as_ptr_gmem(__addr)), "r"(__as_b32(__val))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_release && __scope == scope_cta)
+  {
+    asm("multimem.red.release.cta.global.and.b32 [%0], %1;"
+        :
+        : "l"(__as_ptr_gmem(__addr)), "r"(__as_b32(__val))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_release && __scope == scope_cluster)
+  {
+    asm("multimem.red.release.cluster.global.and.b32 [%0], %1;"
+        :
+        : "l"(__as_ptr_gmem(__addr)), "r"(__as_b32(__val))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_release && __scope == scope_gpu)
+  {
+    asm("multimem.red.release.gpu.global.and.b32 [%0], %1;"
+        :
+        : "l"(__as_ptr_gmem(__addr)), "r"(__as_b32(__val))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_release && __scope == scope_sys)
+  {
+    asm("multimem.red.release.sys.global.and.b32 [%0], %1;"
+        :
+        : "l"(__as_ptr_gmem(__addr)), "r"(__as_b32(__val))
+        : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_multimem_red_is_not_supported_before_SM_90__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 810
+
+/*
+// multimem.red.sem.scope.global.op.b32 [addr], val; // PTX ISA 81, SM_90
+// .sem       = { .relaxed, .release }
+// .scope     = { .cta, .cluster, .gpu, .sys }
+// .op        = { .or }
+template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true, cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+__device__ static inline void multimem_red(
+  cuda::ptx::sem_t<Sem> sem,
+  cuda::ptx::scope_t<Scope> scope,
+  cuda::ptx::op_or_op_t,
+  B32* addr,
+  B32 val);
+*/
+#if __cccl_ptx_isa >= 810
+extern "C" _CCCL_DEVICE void __cuda_ptx_multimem_red_is_not_supported_before_SM_90__();
+template <typename _B32, _CUDA_VSTD::enable_if_t<sizeof(_B32) == 4, bool> = true, dot_sem _Sem, dot_scope _Scope>
+_CCCL_DEVICE static inline void
+multimem_red(sem_t<_Sem> __sem, scope_t<_Scope> __scope, op_or_op_t, _B32* __addr, _B32 __val)
+{
+  static_assert(__sem == sem_relaxed || __sem == sem_release, "");
+  static_assert(__scope == scope_cta || __scope == scope_cluster || __scope == scope_gpu || __scope == scope_sys, "");
+  // __op == op_or_op (due to parameter type constraint)
+  static_assert(sizeof(_B32) == 4, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  _CCCL_IF_CONSTEXPR (__sem == sem_relaxed && __scope == scope_cta)
+  {
+    asm("multimem.red.relaxed.cta.global.or.b32 [%0], %1;"
+        :
+        : "l"(__as_ptr_gmem(__addr)), "r"(__as_b32(__val))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_relaxed && __scope == scope_cluster)
+  {
+    asm("multimem.red.relaxed.cluster.global.or.b32 [%0], %1;"
+        :
+        : "l"(__as_ptr_gmem(__addr)), "r"(__as_b32(__val))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_relaxed && __scope == scope_gpu)
+  {
+    asm("multimem.red.relaxed.gpu.global.or.b32 [%0], %1;"
+        :
+        : "l"(__as_ptr_gmem(__addr)), "r"(__as_b32(__val))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_relaxed && __scope == scope_sys)
+  {
+    asm("multimem.red.relaxed.sys.global.or.b32 [%0], %1;"
+        :
+        : "l"(__as_ptr_gmem(__addr)), "r"(__as_b32(__val))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_release && __scope == scope_cta)
+  {
+    asm("multimem.red.release.cta.global.or.b32 [%0], %1;"
+        :
+        : "l"(__as_ptr_gmem(__addr)), "r"(__as_b32(__val))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_release && __scope == scope_cluster)
+  {
+    asm("multimem.red.release.cluster.global.or.b32 [%0], %1;"
+        :
+        : "l"(__as_ptr_gmem(__addr)), "r"(__as_b32(__val))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_release && __scope == scope_gpu)
+  {
+    asm("multimem.red.release.gpu.global.or.b32 [%0], %1;"
+        :
+        : "l"(__as_ptr_gmem(__addr)), "r"(__as_b32(__val))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_release && __scope == scope_sys)
+  {
+    asm("multimem.red.release.sys.global.or.b32 [%0], %1;"
+        :
+        : "l"(__as_ptr_gmem(__addr)), "r"(__as_b32(__val))
+        : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_multimem_red_is_not_supported_before_SM_90__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 810
+
+/*
+// multimem.red.sem.scope.global.op.b32 [addr], val; // PTX ISA 81, SM_90
+// .sem       = { .relaxed, .release }
+// .scope     = { .cta, .cluster, .gpu, .sys }
+// .op        = { .xor }
+template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true, cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+__device__ static inline void multimem_red(
+  cuda::ptx::sem_t<Sem> sem,
+  cuda::ptx::scope_t<Scope> scope,
+  cuda::ptx::op_xor_op_t,
+  B32* addr,
+  B32 val);
+*/
+#if __cccl_ptx_isa >= 810
+extern "C" _CCCL_DEVICE void __cuda_ptx_multimem_red_is_not_supported_before_SM_90__();
+template <typename _B32, _CUDA_VSTD::enable_if_t<sizeof(_B32) == 4, bool> = true, dot_sem _Sem, dot_scope _Scope>
+_CCCL_DEVICE static inline void
+multimem_red(sem_t<_Sem> __sem, scope_t<_Scope> __scope, op_xor_op_t, _B32* __addr, _B32 __val)
+{
+  static_assert(__sem == sem_relaxed || __sem == sem_release, "");
+  static_assert(__scope == scope_cta || __scope == scope_cluster || __scope == scope_gpu || __scope == scope_sys, "");
+  // __op == op_xor_op (due to parameter type constraint)
+  static_assert(sizeof(_B32) == 4, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  _CCCL_IF_CONSTEXPR (__sem == sem_relaxed && __scope == scope_cta)
+  {
+    asm("multimem.red.relaxed.cta.global.xor.b32 [%0], %1;"
+        :
+        : "l"(__as_ptr_gmem(__addr)), "r"(__as_b32(__val))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_relaxed && __scope == scope_cluster)
+  {
+    asm("multimem.red.relaxed.cluster.global.xor.b32 [%0], %1;"
+        :
+        : "l"(__as_ptr_gmem(__addr)), "r"(__as_b32(__val))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_relaxed && __scope == scope_gpu)
+  {
+    asm("multimem.red.relaxed.gpu.global.xor.b32 [%0], %1;"
+        :
+        : "l"(__as_ptr_gmem(__addr)), "r"(__as_b32(__val))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_relaxed && __scope == scope_sys)
+  {
+    asm("multimem.red.relaxed.sys.global.xor.b32 [%0], %1;"
+        :
+        : "l"(__as_ptr_gmem(__addr)), "r"(__as_b32(__val))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_release && __scope == scope_cta)
+  {
+    asm("multimem.red.release.cta.global.xor.b32 [%0], %1;"
+        :
+        : "l"(__as_ptr_gmem(__addr)), "r"(__as_b32(__val))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_release && __scope == scope_cluster)
+  {
+    asm("multimem.red.release.cluster.global.xor.b32 [%0], %1;"
+        :
+        : "l"(__as_ptr_gmem(__addr)), "r"(__as_b32(__val))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_release && __scope == scope_gpu)
+  {
+    asm("multimem.red.release.gpu.global.xor.b32 [%0], %1;"
+        :
+        : "l"(__as_ptr_gmem(__addr)), "r"(__as_b32(__val))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_release && __scope == scope_sys)
+  {
+    asm("multimem.red.release.sys.global.xor.b32 [%0], %1;"
+        :
+        : "l"(__as_ptr_gmem(__addr)), "r"(__as_b32(__val))
+        : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_multimem_red_is_not_supported_before_SM_90__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 810
+
+/*
+// multimem.red.sem.scope.global.op.b64 [addr], val; // PTX ISA 81, SM_90
+// .sem       = { .relaxed, .release }
+// .scope     = { .cta, .cluster, .gpu, .sys }
+// .op        = { .and }
+template <typename B64, enable_if_t<sizeof(B64) == 8, bool> = true, cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+__device__ static inline void multimem_red(
+  cuda::ptx::sem_t<Sem> sem,
+  cuda::ptx::scope_t<Scope> scope,
+  cuda::ptx::op_and_op_t,
+  B64* addr,
+  B64 val);
+*/
+#if __cccl_ptx_isa >= 810
+extern "C" _CCCL_DEVICE void __cuda_ptx_multimem_red_is_not_supported_before_SM_90__();
+template <typename _B64, _CUDA_VSTD::enable_if_t<sizeof(_B64) == 8, bool> = true, dot_sem _Sem, dot_scope _Scope>
+_CCCL_DEVICE static inline void
+multimem_red(sem_t<_Sem> __sem, scope_t<_Scope> __scope, op_and_op_t, _B64* __addr, _B64 __val)
+{
+  static_assert(__sem == sem_relaxed || __sem == sem_release, "");
+  static_assert(__scope == scope_cta || __scope == scope_cluster || __scope == scope_gpu || __scope == scope_sys, "");
+  // __op == op_and_op (due to parameter type constraint)
+  static_assert(sizeof(_B64) == 8, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  _CCCL_IF_CONSTEXPR (__sem == sem_relaxed && __scope == scope_cta)
+  {
+    asm("multimem.red.relaxed.cta.global.and.b64 [%0], %1;"
+        :
+        : "l"(__as_ptr_gmem(__addr)), "l"(__as_b64(__val))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_relaxed && __scope == scope_cluster)
+  {
+    asm("multimem.red.relaxed.cluster.global.and.b64 [%0], %1;"
+        :
+        : "l"(__as_ptr_gmem(__addr)), "l"(__as_b64(__val))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_relaxed && __scope == scope_gpu)
+  {
+    asm("multimem.red.relaxed.gpu.global.and.b64 [%0], %1;"
+        :
+        : "l"(__as_ptr_gmem(__addr)), "l"(__as_b64(__val))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_relaxed && __scope == scope_sys)
+  {
+    asm("multimem.red.relaxed.sys.global.and.b64 [%0], %1;"
+        :
+        : "l"(__as_ptr_gmem(__addr)), "l"(__as_b64(__val))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_release && __scope == scope_cta)
+  {
+    asm("multimem.red.release.cta.global.and.b64 [%0], %1;"
+        :
+        : "l"(__as_ptr_gmem(__addr)), "l"(__as_b64(__val))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_release && __scope == scope_cluster)
+  {
+    asm("multimem.red.release.cluster.global.and.b64 [%0], %1;"
+        :
+        : "l"(__as_ptr_gmem(__addr)), "l"(__as_b64(__val))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_release && __scope == scope_gpu)
+  {
+    asm("multimem.red.release.gpu.global.and.b64 [%0], %1;"
+        :
+        : "l"(__as_ptr_gmem(__addr)), "l"(__as_b64(__val))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_release && __scope == scope_sys)
+  {
+    asm("multimem.red.release.sys.global.and.b64 [%0], %1;"
+        :
+        : "l"(__as_ptr_gmem(__addr)), "l"(__as_b64(__val))
+        : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_multimem_red_is_not_supported_before_SM_90__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 810
+
+/*
+// multimem.red.sem.scope.global.op.b64 [addr], val; // PTX ISA 81, SM_90
+// .sem       = { .relaxed, .release }
+// .scope     = { .cta, .cluster, .gpu, .sys }
+// .op        = { .or }
+template <typename B64, enable_if_t<sizeof(B64) == 8, bool> = true, cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+__device__ static inline void multimem_red(
+  cuda::ptx::sem_t<Sem> sem,
+  cuda::ptx::scope_t<Scope> scope,
+  cuda::ptx::op_or_op_t,
+  B64* addr,
+  B64 val);
+*/
+#if __cccl_ptx_isa >= 810
+extern "C" _CCCL_DEVICE void __cuda_ptx_multimem_red_is_not_supported_before_SM_90__();
+template <typename _B64, _CUDA_VSTD::enable_if_t<sizeof(_B64) == 8, bool> = true, dot_sem _Sem, dot_scope _Scope>
+_CCCL_DEVICE static inline void
+multimem_red(sem_t<_Sem> __sem, scope_t<_Scope> __scope, op_or_op_t, _B64* __addr, _B64 __val)
+{
+  static_assert(__sem == sem_relaxed || __sem == sem_release, "");
+  static_assert(__scope == scope_cta || __scope == scope_cluster || __scope == scope_gpu || __scope == scope_sys, "");
+  // __op == op_or_op (due to parameter type constraint)
+  static_assert(sizeof(_B64) == 8, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  _CCCL_IF_CONSTEXPR (__sem == sem_relaxed && __scope == scope_cta)
+  {
+    asm("multimem.red.relaxed.cta.global.or.b64 [%0], %1;"
+        :
+        : "l"(__as_ptr_gmem(__addr)), "l"(__as_b64(__val))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_relaxed && __scope == scope_cluster)
+  {
+    asm("multimem.red.relaxed.cluster.global.or.b64 [%0], %1;"
+        :
+        : "l"(__as_ptr_gmem(__addr)), "l"(__as_b64(__val))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_relaxed && __scope == scope_gpu)
+  {
+    asm("multimem.red.relaxed.gpu.global.or.b64 [%0], %1;"
+        :
+        : "l"(__as_ptr_gmem(__addr)), "l"(__as_b64(__val))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_relaxed && __scope == scope_sys)
+  {
+    asm("multimem.red.relaxed.sys.global.or.b64 [%0], %1;"
+        :
+        : "l"(__as_ptr_gmem(__addr)), "l"(__as_b64(__val))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_release && __scope == scope_cta)
+  {
+    asm("multimem.red.release.cta.global.or.b64 [%0], %1;"
+        :
+        : "l"(__as_ptr_gmem(__addr)), "l"(__as_b64(__val))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_release && __scope == scope_cluster)
+  {
+    asm("multimem.red.release.cluster.global.or.b64 [%0], %1;"
+        :
+        : "l"(__as_ptr_gmem(__addr)), "l"(__as_b64(__val))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_release && __scope == scope_gpu)
+  {
+    asm("multimem.red.release.gpu.global.or.b64 [%0], %1;"
+        :
+        : "l"(__as_ptr_gmem(__addr)), "l"(__as_b64(__val))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_release && __scope == scope_sys)
+  {
+    asm("multimem.red.release.sys.global.or.b64 [%0], %1;"
+        :
+        : "l"(__as_ptr_gmem(__addr)), "l"(__as_b64(__val))
+        : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_multimem_red_is_not_supported_before_SM_90__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 810
+
+/*
+// multimem.red.sem.scope.global.op.b64 [addr], val; // PTX ISA 81, SM_90
+// .sem       = { .relaxed, .release }
+// .scope     = { .cta, .cluster, .gpu, .sys }
+// .op        = { .xor }
+template <typename B64, enable_if_t<sizeof(B64) == 8, bool> = true, cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+__device__ static inline void multimem_red(
+  cuda::ptx::sem_t<Sem> sem,
+  cuda::ptx::scope_t<Scope> scope,
+  cuda::ptx::op_xor_op_t,
+  B64* addr,
+  B64 val);
+*/
+#if __cccl_ptx_isa >= 810
+extern "C" _CCCL_DEVICE void __cuda_ptx_multimem_red_is_not_supported_before_SM_90__();
+template <typename _B64, _CUDA_VSTD::enable_if_t<sizeof(_B64) == 8, bool> = true, dot_sem _Sem, dot_scope _Scope>
+_CCCL_DEVICE static inline void
+multimem_red(sem_t<_Sem> __sem, scope_t<_Scope> __scope, op_xor_op_t, _B64* __addr, _B64 __val)
+{
+  static_assert(__sem == sem_relaxed || __sem == sem_release, "");
+  static_assert(__scope == scope_cta || __scope == scope_cluster || __scope == scope_gpu || __scope == scope_sys, "");
+  // __op == op_xor_op (due to parameter type constraint)
+  static_assert(sizeof(_B64) == 8, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  _CCCL_IF_CONSTEXPR (__sem == sem_relaxed && __scope == scope_cta)
+  {
+    asm("multimem.red.relaxed.cta.global.xor.b64 [%0], %1;"
+        :
+        : "l"(__as_ptr_gmem(__addr)), "l"(__as_b64(__val))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_relaxed && __scope == scope_cluster)
+  {
+    asm("multimem.red.relaxed.cluster.global.xor.b64 [%0], %1;"
+        :
+        : "l"(__as_ptr_gmem(__addr)), "l"(__as_b64(__val))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_relaxed && __scope == scope_gpu)
+  {
+    asm("multimem.red.relaxed.gpu.global.xor.b64 [%0], %1;"
+        :
+        : "l"(__as_ptr_gmem(__addr)), "l"(__as_b64(__val))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_relaxed && __scope == scope_sys)
+  {
+    asm("multimem.red.relaxed.sys.global.xor.b64 [%0], %1;"
+        :
+        : "l"(__as_ptr_gmem(__addr)), "l"(__as_b64(__val))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_release && __scope == scope_cta)
+  {
+    asm("multimem.red.release.cta.global.xor.b64 [%0], %1;"
+        :
+        : "l"(__as_ptr_gmem(__addr)), "l"(__as_b64(__val))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_release && __scope == scope_cluster)
+  {
+    asm("multimem.red.release.cluster.global.xor.b64 [%0], %1;"
+        :
+        : "l"(__as_ptr_gmem(__addr)), "l"(__as_b64(__val))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_release && __scope == scope_gpu)
+  {
+    asm("multimem.red.release.gpu.global.xor.b64 [%0], %1;"
+        :
+        : "l"(__as_ptr_gmem(__addr)), "l"(__as_b64(__val))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_release && __scope == scope_sys)
+  {
+    asm("multimem.red.release.sys.global.xor.b64 [%0], %1;"
+        :
+        : "l"(__as_ptr_gmem(__addr)), "l"(__as_b64(__val))
+        : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_multimem_red_is_not_supported_before_SM_90__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 810
+
+#endif // _CUDA_PTX_GENERATED_MULTIMEM_RED_H_
diff --git a/libcudacxx/include/cuda/__ptx/instructions/generated/multimem_st.h b/libcudacxx/include/cuda/__ptx/instructions/generated/multimem_st.h
new file mode 100644
index 00000000000..91319874243
--- /dev/null
+++ b/libcudacxx/include/cuda/__ptx/instructions/generated/multimem_st.h
@@ -0,0 +1,186 @@
+// This file was automatically generated. Do not edit.
+
+#ifndef _CUDA_PTX_GENERATED_MULTIMEM_ST_H_
+#define _CUDA_PTX_GENERATED_MULTIMEM_ST_H_
+
+/*
+// multimem.st.sem.global.b32 [addr], val; // PTX ISA 81, SM_90
+// .sem       = { .weak }
+template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+__device__ static inline void multimem_st(
+  cuda::ptx::sem_weak_t,
+  B32* addr,
+  B32 val);
+*/
+#if __cccl_ptx_isa >= 810
+extern "C" _CCCL_DEVICE void __cuda_ptx_multimem_st_is_not_supported_before_SM_90__();
+template <typename _B32, _CUDA_VSTD::enable_if_t<sizeof(_B32) == 4, bool> = true>
+_CCCL_DEVICE static inline void multimem_st(sem_weak_t, _B32* __addr, _B32 __val)
+{
+  // __sem == sem_weak (due to parameter type constraint)
+  static_assert(sizeof(_B32) == 4, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  asm("multimem.st.weak.global.b32 [%0], %1;" : : "l"(__as_ptr_gmem(__addr)), "r"(__as_b32(__val)) : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_multimem_st_is_not_supported_before_SM_90__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 810
+
+/*
+// multimem.st.sem.scope.global.b32 [addr], val; // PTX ISA 81, SM_90
+// .sem       = { .relaxed, .release }
+// .scope     = { .cta, .cluster, .gpu, .sys }
+template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true, cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+__device__ static inline void multimem_st(
+  cuda::ptx::sem_t<Sem> sem,
+  cuda::ptx::scope_t<Scope> scope,
+  B32* addr,
+  B32 val);
+*/
+#if __cccl_ptx_isa >= 810
+extern "C" _CCCL_DEVICE void __cuda_ptx_multimem_st_is_not_supported_before_SM_90__();
+template <typename _B32, _CUDA_VSTD::enable_if_t<sizeof(_B32) == 4, bool> = true, dot_sem _Sem, dot_scope _Scope>
+_CCCL_DEVICE static inline void multimem_st(sem_t<_Sem> __sem, scope_t<_Scope> __scope, _B32* __addr, _B32 __val)
+{
+  static_assert(__sem == sem_relaxed || __sem == sem_release, "");
+  static_assert(__scope == scope_cta || __scope == scope_cluster || __scope == scope_gpu || __scope == scope_sys, "");
+  static_assert(sizeof(_B32) == 4, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  _CCCL_IF_CONSTEXPR (__sem == sem_relaxed && __scope == scope_cta)
+  {
+    asm("multimem.st.relaxed.cta.global.b32 [%0], %1;" : : "l"(__as_ptr_gmem(__addr)), "r"(__as_b32(__val)) : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_relaxed && __scope == scope_cluster)
+  {
+    asm("multimem.st.relaxed.cluster.global.b32 [%0], %1;"
+        :
+        : "l"(__as_ptr_gmem(__addr)), "r"(__as_b32(__val))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_relaxed && __scope == scope_gpu)
+  {
+    asm("multimem.st.relaxed.gpu.global.b32 [%0], %1;" : : "l"(__as_ptr_gmem(__addr)), "r"(__as_b32(__val)) : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_relaxed && __scope == scope_sys)
+  {
+    asm("multimem.st.relaxed.sys.global.b32 [%0], %1;" : : "l"(__as_ptr_gmem(__addr)), "r"(__as_b32(__val)) : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_release && __scope == scope_cta)
+  {
+    asm("multimem.st.release.cta.global.b32 [%0], %1;" : : "l"(__as_ptr_gmem(__addr)), "r"(__as_b32(__val)) : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_release && __scope == scope_cluster)
+  {
+    asm("multimem.st.release.cluster.global.b32 [%0], %1;"
+        :
+        : "l"(__as_ptr_gmem(__addr)), "r"(__as_b32(__val))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_release && __scope == scope_gpu)
+  {
+    asm("multimem.st.release.gpu.global.b32 [%0], %1;" : : "l"(__as_ptr_gmem(__addr)), "r"(__as_b32(__val)) : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_release && __scope == scope_sys)
+  {
+    asm("multimem.st.release.sys.global.b32 [%0], %1;" : : "l"(__as_ptr_gmem(__addr)), "r"(__as_b32(__val)) : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_multimem_st_is_not_supported_before_SM_90__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 810
+
+/*
+// multimem.st.sem.global.b64 [addr], val; // PTX ISA 81, SM_90
+// .sem       = { .weak }
+template <typename B64, enable_if_t<sizeof(B64) == 8, bool> = true>
+__device__ static inline void multimem_st(
+  cuda::ptx::sem_weak_t,
+  B64* addr,
+  B64 val);
+*/
+#if __cccl_ptx_isa >= 810
+extern "C" _CCCL_DEVICE void __cuda_ptx_multimem_st_is_not_supported_before_SM_90__();
+template <typename _B64, _CUDA_VSTD::enable_if_t<sizeof(_B64) == 8, bool> = true>
+_CCCL_DEVICE static inline void multimem_st(sem_weak_t, _B64* __addr, _B64 __val)
+{
+  // __sem == sem_weak (due to parameter type constraint)
+  static_assert(sizeof(_B64) == 8, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  asm("multimem.st.weak.global.b64 [%0], %1;" : : "l"(__as_ptr_gmem(__addr)), "l"(__as_b64(__val)) : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_multimem_st_is_not_supported_before_SM_90__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 810
+
+/*
+// multimem.st.sem.scope.global.b64 [addr], val; // PTX ISA 81, SM_90
+// .sem       = { .relaxed, .release }
+// .scope     = { .cta, .cluster, .gpu, .sys }
+template <typename B64, enable_if_t<sizeof(B64) == 8, bool> = true, cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
+__device__ static inline void multimem_st(
+  cuda::ptx::sem_t<Sem> sem,
+  cuda::ptx::scope_t<Scope> scope,
+  B64* addr,
+  B64 val);
+*/
+#if __cccl_ptx_isa >= 810
+extern "C" _CCCL_DEVICE void __cuda_ptx_multimem_st_is_not_supported_before_SM_90__();
+template <typename _B64, _CUDA_VSTD::enable_if_t<sizeof(_B64) == 8, bool> = true, dot_sem _Sem, dot_scope _Scope>
+_CCCL_DEVICE static inline void multimem_st(sem_t<_Sem> __sem, scope_t<_Scope> __scope, _B64* __addr, _B64 __val)
+{
+  static_assert(__sem == sem_relaxed || __sem == sem_release, "");
+  static_assert(__scope == scope_cta || __scope == scope_cluster || __scope == scope_gpu || __scope == scope_sys, "");
+  static_assert(sizeof(_B64) == 8, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  _CCCL_IF_CONSTEXPR (__sem == sem_relaxed && __scope == scope_cta)
+  {
+    asm("multimem.st.relaxed.cta.global.b64 [%0], %1;" : : "l"(__as_ptr_gmem(__addr)), "l"(__as_b64(__val)) : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_relaxed && __scope == scope_cluster)
+  {
+    asm("multimem.st.relaxed.cluster.global.b64 [%0], %1;"
+        :
+        : "l"(__as_ptr_gmem(__addr)), "l"(__as_b64(__val))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_relaxed && __scope == scope_gpu)
+  {
+    asm("multimem.st.relaxed.gpu.global.b64 [%0], %1;" : : "l"(__as_ptr_gmem(__addr)), "l"(__as_b64(__val)) : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_relaxed && __scope == scope_sys)
+  {
+    asm("multimem.st.relaxed.sys.global.b64 [%0], %1;" : : "l"(__as_ptr_gmem(__addr)), "l"(__as_b64(__val)) : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_release && __scope == scope_cta)
+  {
+    asm("multimem.st.release.cta.global.b64 [%0], %1;" : : "l"(__as_ptr_gmem(__addr)), "l"(__as_b64(__val)) : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_release && __scope == scope_cluster)
+  {
+    asm("multimem.st.release.cluster.global.b64 [%0], %1;"
+        :
+        : "l"(__as_ptr_gmem(__addr)), "l"(__as_b64(__val))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_release && __scope == scope_gpu)
+  {
+    asm("multimem.st.release.gpu.global.b64 [%0], %1;" : : "l"(__as_ptr_gmem(__addr)), "l"(__as_b64(__val)) : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__sem == sem_release && __scope == scope_sys)
+  {
+    asm("multimem.st.release.sys.global.b64 [%0], %1;" : : "l"(__as_ptr_gmem(__addr)), "l"(__as_b64(__val)) : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_multimem_st_is_not_supported_before_SM_90__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 810
+
+#endif // _CUDA_PTX_GENERATED_MULTIMEM_ST_H_
diff --git a/libcudacxx/include/cuda/__ptx/instructions/generated/red_async.h b/libcudacxx/include/cuda/__ptx/instructions/generated/red_async.h
index 74110933270..767411d4719 100644
--- a/libcudacxx/include/cuda/__ptx/instructions/generated/red_async.h
+++ b/libcudacxx/include/cuda/__ptx/instructions/generated/red_async.h
@@ -4,8 +4,8 @@
 #define _CUDA_PTX_GENERATED_RED_ASYNC_H_
 
 /*
-// red.async.relaxed.cluster.shared::cluster.mbarrier::complete_tx::bytes{.op}{.type}  [dest], value, [remote_bar];  //
-PTX ISA 81, SM_90
+// red.async.relaxed.cluster.shared::cluster.mbarrier::complete_tx::bytes.op.type  [dest], value, [remote_bar];  // PTX
+ISA 81, SM_90
 // .type      = { .u32 }
 // .op        = { .inc }
 template <typename = void>
@@ -21,23 +21,23 @@ template <typename = void>
 _CCCL_DEVICE static inline void red_async(
   op_inc_t, _CUDA_VSTD::uint32_t* __dest, const _CUDA_VSTD::uint32_t& __value, _CUDA_VSTD::uint64_t* __remote_bar)
 {
-  // __type == type_u32 (due to parameter type constraint)
-  // __op == op_inc (due to parameter type constraint)
-  NV_IF_ELSE_TARGET(
-    NV_PROVIDES_SM_90,
-    (asm("red.async.relaxed.cluster.shared::cluster.mbarrier::complete_tx::bytes.inc.u32  [%0], %1, [%2]; " : : "r"(
-           __as_ptr_remote_dsmem(__dest)),
-         "r"(__value),
-         "r"(__as_ptr_remote_dsmem(__remote_bar)) : "memory");),
-    (
-      // Unsupported architectures will have a linker error with a semi-decent error message
-      __cuda_ptx_red_async_is_not_supported_before_SM_90__();));
+// __type == type_u32 (due to parameter type constraint)
+// __op == op_inc (due to parameter type constraint)
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  asm("red.async.relaxed.cluster.shared::cluster.mbarrier::complete_tx::bytes.inc.u32  [%0], %1, [%2]; "
+      :
+      : "r"(__as_ptr_remote_dsmem(__dest)), "r"(__value), "r"(__as_ptr_remote_dsmem(__remote_bar))
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_red_async_is_not_supported_before_SM_90__();
+#  endif
 }
 #endif // __cccl_ptx_isa >= 810
 
 /*
-// red.async.relaxed.cluster.shared::cluster.mbarrier::complete_tx::bytes{.op}{.type}  [dest], value, [remote_bar];  //
-PTX ISA 81, SM_90
+// red.async.relaxed.cluster.shared::cluster.mbarrier::complete_tx::bytes.op.type  [dest], value, [remote_bar];  // PTX
+ISA 81, SM_90
 // .type      = { .u32 }
 // .op        = { .dec }
 template <typename = void>
@@ -53,23 +53,23 @@ template <typename = void>
 _CCCL_DEVICE static inline void red_async(
   op_dec_t, _CUDA_VSTD::uint32_t* __dest, const _CUDA_VSTD::uint32_t& __value, _CUDA_VSTD::uint64_t* __remote_bar)
 {
-  // __type == type_u32 (due to parameter type constraint)
-  // __op == op_dec (due to parameter type constraint)
-  NV_IF_ELSE_TARGET(
-    NV_PROVIDES_SM_90,
-    (asm("red.async.relaxed.cluster.shared::cluster.mbarrier::complete_tx::bytes.dec.u32  [%0], %1, [%2]; " : : "r"(
-           __as_ptr_remote_dsmem(__dest)),
-         "r"(__value),
-         "r"(__as_ptr_remote_dsmem(__remote_bar)) : "memory");),
-    (
-      // Unsupported architectures will have a linker error with a semi-decent error message
-      __cuda_ptx_red_async_is_not_supported_before_SM_90__();));
+// __type == type_u32 (due to parameter type constraint)
+// __op == op_dec (due to parameter type constraint)
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  asm("red.async.relaxed.cluster.shared::cluster.mbarrier::complete_tx::bytes.dec.u32  [%0], %1, [%2]; "
+      :
+      : "r"(__as_ptr_remote_dsmem(__dest)), "r"(__value), "r"(__as_ptr_remote_dsmem(__remote_bar))
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_red_async_is_not_supported_before_SM_90__();
+#  endif
 }
 #endif // __cccl_ptx_isa >= 810
 
 /*
-// red.async.relaxed.cluster.shared::cluster.mbarrier::complete_tx::bytes{.op}{.type}  [dest], value, [remote_bar];  //
-PTX ISA 81, SM_90
+// red.async.relaxed.cluster.shared::cluster.mbarrier::complete_tx::bytes.op.type  [dest], value, [remote_bar];  // PTX
+ISA 81, SM_90
 // .type      = { .u32 }
 // .op        = { .min }
 template <typename = void>
@@ -85,23 +85,23 @@ template <typename = void>
 _CCCL_DEVICE static inline void red_async(
   op_min_t, _CUDA_VSTD::uint32_t* __dest, const _CUDA_VSTD::uint32_t& __value, _CUDA_VSTD::uint64_t* __remote_bar)
 {
-  // __type == type_u32 (due to parameter type constraint)
-  // __op == op_min (due to parameter type constraint)
-  NV_IF_ELSE_TARGET(
-    NV_PROVIDES_SM_90,
-    (asm("red.async.relaxed.cluster.shared::cluster.mbarrier::complete_tx::bytes.min.u32  [%0], %1, [%2]; " : : "r"(
-           __as_ptr_remote_dsmem(__dest)),
-         "r"(__value),
-         "r"(__as_ptr_remote_dsmem(__remote_bar)) : "memory");),
-    (
-      // Unsupported architectures will have a linker error with a semi-decent error message
-      __cuda_ptx_red_async_is_not_supported_before_SM_90__();));
+// __type == type_u32 (due to parameter type constraint)
+// __op == op_min (due to parameter type constraint)
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  asm("red.async.relaxed.cluster.shared::cluster.mbarrier::complete_tx::bytes.min.u32  [%0], %1, [%2]; "
+      :
+      : "r"(__as_ptr_remote_dsmem(__dest)), "r"(__value), "r"(__as_ptr_remote_dsmem(__remote_bar))
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_red_async_is_not_supported_before_SM_90__();
+#  endif
 }
 #endif // __cccl_ptx_isa >= 810
 
 /*
-// red.async.relaxed.cluster.shared::cluster.mbarrier::complete_tx::bytes{.op}{.type}  [dest], value, [remote_bar];  //
-PTX ISA 81, SM_90
+// red.async.relaxed.cluster.shared::cluster.mbarrier::complete_tx::bytes.op.type  [dest], value, [remote_bar];  // PTX
+ISA 81, SM_90
 // .type      = { .u32 }
 // .op        = { .max }
 template <typename = void>
@@ -117,23 +117,23 @@ template <typename = void>
 _CCCL_DEVICE static inline void red_async(
   op_max_t, _CUDA_VSTD::uint32_t* __dest, const _CUDA_VSTD::uint32_t& __value, _CUDA_VSTD::uint64_t* __remote_bar)
 {
-  // __type == type_u32 (due to parameter type constraint)
-  // __op == op_max (due to parameter type constraint)
-  NV_IF_ELSE_TARGET(
-    NV_PROVIDES_SM_90,
-    (asm("red.async.relaxed.cluster.shared::cluster.mbarrier::complete_tx::bytes.max.u32  [%0], %1, [%2]; " : : "r"(
-           __as_ptr_remote_dsmem(__dest)),
-         "r"(__value),
-         "r"(__as_ptr_remote_dsmem(__remote_bar)) : "memory");),
-    (
-      // Unsupported architectures will have a linker error with a semi-decent error message
-      __cuda_ptx_red_async_is_not_supported_before_SM_90__();));
+// __type == type_u32 (due to parameter type constraint)
+// __op == op_max (due to parameter type constraint)
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  asm("red.async.relaxed.cluster.shared::cluster.mbarrier::complete_tx::bytes.max.u32  [%0], %1, [%2]; "
+      :
+      : "r"(__as_ptr_remote_dsmem(__dest)), "r"(__value), "r"(__as_ptr_remote_dsmem(__remote_bar))
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_red_async_is_not_supported_before_SM_90__();
+#  endif
 }
 #endif // __cccl_ptx_isa >= 810
 
 /*
-// red.async.relaxed.cluster.shared::cluster.mbarrier::complete_tx::bytes{.op}{.type}  [dest], value, [remote_bar];  //
-PTX ISA 81, SM_90
+// red.async.relaxed.cluster.shared::cluster.mbarrier::complete_tx::bytes.op.type  [dest], value, [remote_bar];  // PTX
+ISA 81, SM_90
 // .type      = { .u32 }
 // .op        = { .add }
 template <typename = void>
@@ -149,23 +149,23 @@ template <typename = void>
 _CCCL_DEVICE static inline void red_async(
   op_add_t, _CUDA_VSTD::uint32_t* __dest, const _CUDA_VSTD::uint32_t& __value, _CUDA_VSTD::uint64_t* __remote_bar)
 {
-  // __type == type_u32 (due to parameter type constraint)
-  // __op == op_add (due to parameter type constraint)
-  NV_IF_ELSE_TARGET(
-    NV_PROVIDES_SM_90,
-    (asm("red.async.relaxed.cluster.shared::cluster.mbarrier::complete_tx::bytes.add.u32  [%0], %1, [%2]; " : : "r"(
-           __as_ptr_remote_dsmem(__dest)),
-         "r"(__value),
-         "r"(__as_ptr_remote_dsmem(__remote_bar)) : "memory");),
-    (
-      // Unsupported architectures will have a linker error with a semi-decent error message
-      __cuda_ptx_red_async_is_not_supported_before_SM_90__();));
+// __type == type_u32 (due to parameter type constraint)
+// __op == op_add (due to parameter type constraint)
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  asm("red.async.relaxed.cluster.shared::cluster.mbarrier::complete_tx::bytes.add.u32  [%0], %1, [%2]; "
+      :
+      : "r"(__as_ptr_remote_dsmem(__dest)), "r"(__value), "r"(__as_ptr_remote_dsmem(__remote_bar))
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_red_async_is_not_supported_before_SM_90__();
+#  endif
 }
 #endif // __cccl_ptx_isa >= 810
 
 /*
-// red.async.relaxed.cluster.shared::cluster.mbarrier::complete_tx::bytes{.op}{.type}  [dest], value, [remote_bar];  //
-PTX ISA 81, SM_90
+// red.async.relaxed.cluster.shared::cluster.mbarrier::complete_tx::bytes.op.type  [dest], value, [remote_bar];  // PTX
+ISA 81, SM_90
 // .type      = { .s32 }
 // .op        = { .min }
 template <typename = void>
@@ -181,23 +181,23 @@ template <typename = void>
 _CCCL_DEVICE static inline void
 red_async(op_min_t, _CUDA_VSTD::int32_t* __dest, const _CUDA_VSTD::int32_t& __value, _CUDA_VSTD::uint64_t* __remote_bar)
 {
-  // __type == type_s32 (due to parameter type constraint)
-  // __op == op_min (due to parameter type constraint)
-  NV_IF_ELSE_TARGET(
-    NV_PROVIDES_SM_90,
-    (asm("red.async.relaxed.cluster.shared::cluster.mbarrier::complete_tx::bytes.min.s32  [%0], %1, [%2]; " : : "r"(
-           __as_ptr_remote_dsmem(__dest)),
-         "r"(__value),
-         "r"(__as_ptr_remote_dsmem(__remote_bar)) : "memory");),
-    (
-      // Unsupported architectures will have a linker error with a semi-decent error message
-      __cuda_ptx_red_async_is_not_supported_before_SM_90__();));
+// __type == type_s32 (due to parameter type constraint)
+// __op == op_min (due to parameter type constraint)
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  asm("red.async.relaxed.cluster.shared::cluster.mbarrier::complete_tx::bytes.min.s32  [%0], %1, [%2]; "
+      :
+      : "r"(__as_ptr_remote_dsmem(__dest)), "r"(__value), "r"(__as_ptr_remote_dsmem(__remote_bar))
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_red_async_is_not_supported_before_SM_90__();
+#  endif
 }
 #endif // __cccl_ptx_isa >= 810
 
 /*
-// red.async.relaxed.cluster.shared::cluster.mbarrier::complete_tx::bytes{.op}{.type}  [dest], value, [remote_bar];  //
-PTX ISA 81, SM_90
+// red.async.relaxed.cluster.shared::cluster.mbarrier::complete_tx::bytes.op.type  [dest], value, [remote_bar];  // PTX
+ISA 81, SM_90
 // .type      = { .s32 }
 // .op        = { .max }
 template <typename = void>
@@ -213,23 +213,23 @@ template <typename = void>
 _CCCL_DEVICE static inline void
 red_async(op_max_t, _CUDA_VSTD::int32_t* __dest, const _CUDA_VSTD::int32_t& __value, _CUDA_VSTD::uint64_t* __remote_bar)
 {
-  // __type == type_s32 (due to parameter type constraint)
-  // __op == op_max (due to parameter type constraint)
-  NV_IF_ELSE_TARGET(
-    NV_PROVIDES_SM_90,
-    (asm("red.async.relaxed.cluster.shared::cluster.mbarrier::complete_tx::bytes.max.s32  [%0], %1, [%2]; " : : "r"(
-           __as_ptr_remote_dsmem(__dest)),
-         "r"(__value),
-         "r"(__as_ptr_remote_dsmem(__remote_bar)) : "memory");),
-    (
-      // Unsupported architectures will have a linker error with a semi-decent error message
-      __cuda_ptx_red_async_is_not_supported_before_SM_90__();));
+// __type == type_s32 (due to parameter type constraint)
+// __op == op_max (due to parameter type constraint)
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  asm("red.async.relaxed.cluster.shared::cluster.mbarrier::complete_tx::bytes.max.s32  [%0], %1, [%2]; "
+      :
+      : "r"(__as_ptr_remote_dsmem(__dest)), "r"(__value), "r"(__as_ptr_remote_dsmem(__remote_bar))
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_red_async_is_not_supported_before_SM_90__();
+#  endif
 }
 #endif // __cccl_ptx_isa >= 810
 
 /*
-// red.async.relaxed.cluster.shared::cluster.mbarrier::complete_tx::bytes{.op}{.type}  [dest], value, [remote_bar];  //
-PTX ISA 81, SM_90
+// red.async.relaxed.cluster.shared::cluster.mbarrier::complete_tx::bytes.op.type  [dest], value, [remote_bar];  // PTX
+ISA 81, SM_90
 // .type      = { .s32 }
 // .op        = { .add }
 template <typename = void>
@@ -245,26 +245,26 @@ template <typename = void>
 _CCCL_DEVICE static inline void
 red_async(op_add_t, _CUDA_VSTD::int32_t* __dest, const _CUDA_VSTD::int32_t& __value, _CUDA_VSTD::uint64_t* __remote_bar)
 {
-  // __type == type_s32 (due to parameter type constraint)
-  // __op == op_add (due to parameter type constraint)
-  NV_IF_ELSE_TARGET(
-    NV_PROVIDES_SM_90,
-    (asm("red.async.relaxed.cluster.shared::cluster.mbarrier::complete_tx::bytes.add.s32  [%0], %1, [%2]; " : : "r"(
-           __as_ptr_remote_dsmem(__dest)),
-         "r"(__value),
-         "r"(__as_ptr_remote_dsmem(__remote_bar)) : "memory");),
-    (
-      // Unsupported architectures will have a linker error with a semi-decent error message
-      __cuda_ptx_red_async_is_not_supported_before_SM_90__();));
+// __type == type_s32 (due to parameter type constraint)
+// __op == op_add (due to parameter type constraint)
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  asm("red.async.relaxed.cluster.shared::cluster.mbarrier::complete_tx::bytes.add.s32  [%0], %1, [%2]; "
+      :
+      : "r"(__as_ptr_remote_dsmem(__dest)), "r"(__value), "r"(__as_ptr_remote_dsmem(__remote_bar))
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_red_async_is_not_supported_before_SM_90__();
+#  endif
 }
 #endif // __cccl_ptx_isa >= 810
 
 /*
-// red.async.relaxed.cluster.shared::cluster.mbarrier::complete_tx::bytes{.op}{.type}  [dest], value, [remote_bar];  //
-PTX ISA 81, SM_90
+// red.async.relaxed.cluster.shared::cluster.mbarrier::complete_tx::bytes.op.type  [dest], value, [remote_bar];  // PTX
+ISA 81, SM_90
 // .type      = { .b32 }
 // .op        = { .and }
-template <typename B32>
+template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
 __device__ static inline void red_async(
   cuda::ptx::op_and_op_t,
   B32* dest,
@@ -273,31 +273,31 @@ __device__ static inline void red_async(
 */
 #if __cccl_ptx_isa >= 810
 extern "C" _CCCL_DEVICE void __cuda_ptx_red_async_is_not_supported_before_SM_90__();
-template <typename _B32>
+template <typename _B32, _CUDA_VSTD::enable_if_t<sizeof(_B32) == 4, bool> = true>
 _CCCL_DEVICE static inline void
 red_async(op_and_op_t, _B32* __dest, const _B32& __value, _CUDA_VSTD::uint64_t* __remote_bar)
 {
   // __type == type_b32 (due to parameter type constraint)
   // __op == op_and_op (due to parameter type constraint)
   static_assert(sizeof(_B32) == 4, "");
-  NV_IF_ELSE_TARGET(
-    NV_PROVIDES_SM_90,
-    (asm("red.async.relaxed.cluster.shared::cluster.mbarrier::complete_tx::bytes.and.b32  [%0], %1, [%2]; " : : "r"(
-           __as_ptr_remote_dsmem(__dest)),
-         "r"(__as_b32(__value)),
-         "r"(__as_ptr_remote_dsmem(__remote_bar)) : "memory");),
-    (
-      // Unsupported architectures will have a linker error with a semi-decent error message
-      __cuda_ptx_red_async_is_not_supported_before_SM_90__();));
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  asm("red.async.relaxed.cluster.shared::cluster.mbarrier::complete_tx::bytes.and.b32  [%0], %1, [%2]; "
+      :
+      : "r"(__as_ptr_remote_dsmem(__dest)), "r"(__as_b32(__value)), "r"(__as_ptr_remote_dsmem(__remote_bar))
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_red_async_is_not_supported_before_SM_90__();
+#  endif
 }
 #endif // __cccl_ptx_isa >= 810
 
 /*
-// red.async.relaxed.cluster.shared::cluster.mbarrier::complete_tx::bytes{.op}{.type}  [dest], value, [remote_bar];  //
-PTX ISA 81, SM_90
+// red.async.relaxed.cluster.shared::cluster.mbarrier::complete_tx::bytes.op.type  [dest], value, [remote_bar];  // PTX
+ISA 81, SM_90
 // .type      = { .b32 }
 // .op        = { .or }
-template <typename B32>
+template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
 __device__ static inline void red_async(
   cuda::ptx::op_or_op_t,
   B32* dest,
@@ -306,31 +306,31 @@ __device__ static inline void red_async(
 */
 #if __cccl_ptx_isa >= 810
 extern "C" _CCCL_DEVICE void __cuda_ptx_red_async_is_not_supported_before_SM_90__();
-template <typename _B32>
+template <typename _B32, _CUDA_VSTD::enable_if_t<sizeof(_B32) == 4, bool> = true>
 _CCCL_DEVICE static inline void
 red_async(op_or_op_t, _B32* __dest, const _B32& __value, _CUDA_VSTD::uint64_t* __remote_bar)
 {
   // __type == type_b32 (due to parameter type constraint)
   // __op == op_or_op (due to parameter type constraint)
   static_assert(sizeof(_B32) == 4, "");
-  NV_IF_ELSE_TARGET(
-    NV_PROVIDES_SM_90,
-    (asm("red.async.relaxed.cluster.shared::cluster.mbarrier::complete_tx::bytes.or.b32  [%0], %1, [%2]; " : : "r"(
-           __as_ptr_remote_dsmem(__dest)),
-         "r"(__as_b32(__value)),
-         "r"(__as_ptr_remote_dsmem(__remote_bar)) : "memory");),
-    (
-      // Unsupported architectures will have a linker error with a semi-decent error message
-      __cuda_ptx_red_async_is_not_supported_before_SM_90__();));
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  asm("red.async.relaxed.cluster.shared::cluster.mbarrier::complete_tx::bytes.or.b32  [%0], %1, [%2]; "
+      :
+      : "r"(__as_ptr_remote_dsmem(__dest)), "r"(__as_b32(__value)), "r"(__as_ptr_remote_dsmem(__remote_bar))
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_red_async_is_not_supported_before_SM_90__();
+#  endif
 }
 #endif // __cccl_ptx_isa >= 810
 
 /*
-// red.async.relaxed.cluster.shared::cluster.mbarrier::complete_tx::bytes{.op}{.type}  [dest], value, [remote_bar];  //
-PTX ISA 81, SM_90
+// red.async.relaxed.cluster.shared::cluster.mbarrier::complete_tx::bytes.op.type  [dest], value, [remote_bar];  // PTX
+ISA 81, SM_90
 // .type      = { .b32 }
 // .op        = { .xor }
-template <typename B32>
+template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
 __device__ static inline void red_async(
   cuda::ptx::op_xor_op_t,
   B32* dest,
@@ -339,28 +339,28 @@ __device__ static inline void red_async(
 */
 #if __cccl_ptx_isa >= 810
 extern "C" _CCCL_DEVICE void __cuda_ptx_red_async_is_not_supported_before_SM_90__();
-template <typename _B32>
+template <typename _B32, _CUDA_VSTD::enable_if_t<sizeof(_B32) == 4, bool> = true>
 _CCCL_DEVICE static inline void
 red_async(op_xor_op_t, _B32* __dest, const _B32& __value, _CUDA_VSTD::uint64_t* __remote_bar)
 {
   // __type == type_b32 (due to parameter type constraint)
   // __op == op_xor_op (due to parameter type constraint)
   static_assert(sizeof(_B32) == 4, "");
-  NV_IF_ELSE_TARGET(
-    NV_PROVIDES_SM_90,
-    (asm("red.async.relaxed.cluster.shared::cluster.mbarrier::complete_tx::bytes.xor.b32  [%0], %1, [%2]; " : : "r"(
-           __as_ptr_remote_dsmem(__dest)),
-         "r"(__as_b32(__value)),
-         "r"(__as_ptr_remote_dsmem(__remote_bar)) : "memory");),
-    (
-      // Unsupported architectures will have a linker error with a semi-decent error message
-      __cuda_ptx_red_async_is_not_supported_before_SM_90__();));
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  asm("red.async.relaxed.cluster.shared::cluster.mbarrier::complete_tx::bytes.xor.b32  [%0], %1, [%2]; "
+      :
+      : "r"(__as_ptr_remote_dsmem(__dest)), "r"(__as_b32(__value)), "r"(__as_ptr_remote_dsmem(__remote_bar))
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_red_async_is_not_supported_before_SM_90__();
+#  endif
 }
 #endif // __cccl_ptx_isa >= 810
 
 /*
-// red.async.relaxed.cluster.shared::cluster.mbarrier::complete_tx::bytes{.op}{.type}  [dest], value, [remote_bar];  //
-PTX ISA 81, SM_90
+// red.async.relaxed.cluster.shared::cluster.mbarrier::complete_tx::bytes.op.type  [dest], value, [remote_bar];  // PTX
+ISA 81, SM_90
 // .type      = { .u64 }
 // .op        = { .add }
 template <typename = void>
@@ -376,22 +376,22 @@ template <typename = void>
 _CCCL_DEVICE static inline void red_async(
   op_add_t, _CUDA_VSTD::uint64_t* __dest, const _CUDA_VSTD::uint64_t& __value, _CUDA_VSTD::uint64_t* __remote_bar)
 {
-  // __type == type_u64 (due to parameter type constraint)
-  // __op == op_add (due to parameter type constraint)
-  NV_IF_ELSE_TARGET(
-    NV_PROVIDES_SM_90,
-    (asm("red.async.relaxed.cluster.shared::cluster.mbarrier::complete_tx::bytes.add.u64  [%0], %1, [%2]; " : : "r"(
-           __as_ptr_remote_dsmem(__dest)),
-         "l"(__value),
-         "r"(__as_ptr_remote_dsmem(__remote_bar)) : "memory");),
-    (
-      // Unsupported architectures will have a linker error with a semi-decent error message
-      __cuda_ptx_red_async_is_not_supported_before_SM_90__();));
+// __type == type_u64 (due to parameter type constraint)
+// __op == op_add (due to parameter type constraint)
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  asm("red.async.relaxed.cluster.shared::cluster.mbarrier::complete_tx::bytes.add.u64  [%0], %1, [%2]; "
+      :
+      : "r"(__as_ptr_remote_dsmem(__dest)), "l"(__value), "r"(__as_ptr_remote_dsmem(__remote_bar))
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_red_async_is_not_supported_before_SM_90__();
+#  endif
 }
 #endif // __cccl_ptx_isa >= 810
 
 /*
-// red.async.relaxed.cluster.shared::cluster.mbarrier::complete_tx::bytes{.op}.u64  [dest], value, [remote_bar]; // .u64
+// red.async.relaxed.cluster.shared::cluster.mbarrier::complete_tx::bytes.op.u64  [dest], value, [remote_bar]; // .u64
 intentional PTX ISA 81, SM_90
 // .op        = { .add }
 template <typename = void>
@@ -407,16 +407,17 @@ template <typename = void>
 _CCCL_DEVICE static inline void
 red_async(op_add_t, _CUDA_VSTD::int64_t* __dest, const _CUDA_VSTD::int64_t& __value, _CUDA_VSTD::int64_t* __remote_bar)
 {
-  // __op == op_add (due to parameter type constraint)
-  NV_IF_ELSE_TARGET(
-    NV_PROVIDES_SM_90,
-    (asm("red.async.relaxed.cluster.shared::cluster.mbarrier::complete_tx::bytes.add.u64  [%0], %1, [%2]; // .u64 "
-         "intentional" : : "r"(__as_ptr_remote_dsmem(__dest)),
-         "l"(__value),
-         "r"(__as_ptr_remote_dsmem(__remote_bar)) : "memory");),
-    (
-      // Unsupported architectures will have a linker error with a semi-decent error message
-      __cuda_ptx_red_async_is_not_supported_before_SM_90__();));
+// __op == op_add (due to parameter type constraint)
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  asm("red.async.relaxed.cluster.shared::cluster.mbarrier::complete_tx::bytes.add.u64  [%0], %1, [%2]; // .u64 "
+      "intentional"
+      :
+      : "r"(__as_ptr_remote_dsmem(__dest)), "l"(__value), "r"(__as_ptr_remote_dsmem(__remote_bar))
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_red_async_is_not_supported_before_SM_90__();
+#  endif
 }
 #endif // __cccl_ptx_isa >= 810
 
diff --git a/libcudacxx/include/cuda/__ptx/instructions/generated/st_async.h b/libcudacxx/include/cuda/__ptx/instructions/generated/st_async.h
index e6c3fcf1737..e59208e59ba 100644
--- a/libcudacxx/include/cuda/__ptx/instructions/generated/st_async.h
+++ b/libcudacxx/include/cuda/__ptx/instructions/generated/st_async.h
@@ -4,7 +4,7 @@
 #define _CUDA_PTX_GENERATED_ST_ASYNC_H_
 
 /*
-// st.async.weak.shared::cluster.mbarrier::complete_tx::bytes{.type} [addr], value, [remote_bar];    // 1.  PTX ISA 81,
+// st.async.weak.shared::cluster.mbarrier::complete_tx::bytes.type [addr], value, [remote_bar];    // 1.  PTX ISA 81,
 SM_90
 // .type      = { .b32, .b64 }
 template <typename Type>
@@ -19,28 +19,30 @@ template <typename _Type>
 _CCCL_DEVICE static inline void st_async(_Type* __addr, const _Type& __value, _CUDA_VSTD::uint64_t* __remote_bar)
 {
   static_assert(sizeof(_Type) == 4 || sizeof(_Type) == 8, "");
-  NV_IF_ELSE_TARGET(
-    NV_PROVIDES_SM_90,
-    (
-      _CCCL_IF_CONSTEXPR (sizeof(_Type) == 4) {
-        asm("st.async.weak.shared::cluster.mbarrier::complete_tx::bytes.b32 [%0], %1, [%2];    // 1. "
-            :
-            : "r"(__as_ptr_remote_dsmem(__addr)), "r"(__as_b32(__value)), "r"(__as_ptr_remote_dsmem(__remote_bar))
-            : "memory");
-      } else _CCCL_IF_CONSTEXPR (sizeof(_Type) == 8) {
-        asm("st.async.weak.shared::cluster.mbarrier::complete_tx::bytes.b64 [%0], %1, [%2];    // 1. "
-            :
-            : "r"(__as_ptr_remote_dsmem(__addr)), "l"(__as_b64(__value)), "r"(__as_ptr_remote_dsmem(__remote_bar))
-            : "memory");
-      }),
-    (
-      // Unsupported architectures will have a linker error with a semi-decent error message
-      __cuda_ptx_st_async_is_not_supported_before_SM_90__();));
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  _CCCL_IF_CONSTEXPR (sizeof(_Type) == 4)
+  {
+    asm("st.async.weak.shared::cluster.mbarrier::complete_tx::bytes.b32 [%0], %1, [%2];    // 1. "
+        :
+        : "r"(__as_ptr_remote_dsmem(__addr)), "r"(__as_b32(__value)), "r"(__as_ptr_remote_dsmem(__remote_bar))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (sizeof(_Type) == 8)
+  {
+    asm("st.async.weak.shared::cluster.mbarrier::complete_tx::bytes.b64 [%0], %1, [%2];    // 1. "
+        :
+        : "r"(__as_ptr_remote_dsmem(__addr)), "l"(__as_b64(__value)), "r"(__as_ptr_remote_dsmem(__remote_bar))
+        : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_st_async_is_not_supported_before_SM_90__();
+#  endif
 }
 #endif // __cccl_ptx_isa >= 810
 
 /*
-// st.async.weak.shared::cluster.mbarrier::complete_tx::bytes.v2{.type} [addr], value, [remote_bar]; // 2.  PTX ISA 81,
+// st.async.weak.shared::cluster.mbarrier::complete_tx::bytes.v2.type [addr], value, [remote_bar]; // 2.  PTX ISA 81,
 SM_90
 // .type      = { .b32, .b64 }
 template <typename Type>
@@ -55,35 +57,37 @@ template <typename _Type>
 _CCCL_DEVICE static inline void st_async(_Type* __addr, const _Type (&__value)[2], _CUDA_VSTD::uint64_t* __remote_bar)
 {
   static_assert(sizeof(_Type) == 4 || sizeof(_Type) == 8, "");
-  NV_IF_ELSE_TARGET(
-    NV_PROVIDES_SM_90,
-    (
-      _CCCL_IF_CONSTEXPR (sizeof(_Type) == 4) {
-        asm("st.async.weak.shared::cluster.mbarrier::complete_tx::bytes.v2.b32 [%0], {%1, %2}, [%3]; // 2. "
-            :
-            : "r"(__as_ptr_remote_dsmem(__addr)),
-              "r"(__as_b32(__value[0])),
-              "r"(__as_b32(__value[1])),
-              "r"(__as_ptr_remote_dsmem(__remote_bar))
-            : "memory");
-      } else _CCCL_IF_CONSTEXPR (sizeof(_Type) == 8) {
-        asm("st.async.weak.shared::cluster.mbarrier::complete_tx::bytes.v2.b64 [%0], {%1, %2}, [%3]; // 2. "
-            :
-            : "r"(__as_ptr_remote_dsmem(__addr)),
-              "l"(__as_b64(__value[0])),
-              "l"(__as_b64(__value[1])),
-              "r"(__as_ptr_remote_dsmem(__remote_bar))
-            : "memory");
-      }),
-    (
-      // Unsupported architectures will have a linker error with a semi-decent error message
-      __cuda_ptx_st_async_is_not_supported_before_SM_90__();));
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  _CCCL_IF_CONSTEXPR (sizeof(_Type) == 4)
+  {
+    asm("st.async.weak.shared::cluster.mbarrier::complete_tx::bytes.v2.b32 [%0], {%1, %2}, [%3]; // 2. "
+        :
+        : "r"(__as_ptr_remote_dsmem(__addr)),
+          "r"(__as_b32(__value[0])),
+          "r"(__as_b32(__value[1])),
+          "r"(__as_ptr_remote_dsmem(__remote_bar))
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (sizeof(_Type) == 8)
+  {
+    asm("st.async.weak.shared::cluster.mbarrier::complete_tx::bytes.v2.b64 [%0], {%1, %2}, [%3]; // 2. "
+        :
+        : "r"(__as_ptr_remote_dsmem(__addr)),
+          "l"(__as_b64(__value[0])),
+          "l"(__as_b64(__value[1])),
+          "r"(__as_ptr_remote_dsmem(__remote_bar))
+        : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_st_async_is_not_supported_before_SM_90__();
+#  endif
 }
 #endif // __cccl_ptx_isa >= 810
 
 /*
 // st.async.weak.shared::cluster.mbarrier::complete_tx::bytes.v4.b32 [addr], value, [remote_bar];    // 3.  PTX ISA 81,
-SM_90 template <typename B32>
+SM_90 template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
 __device__ static inline void st_async(
   B32* addr,
   const B32 (&value)[4],
@@ -91,22 +95,24 @@ __device__ static inline void st_async(
 */
 #if __cccl_ptx_isa >= 810
 extern "C" _CCCL_DEVICE void __cuda_ptx_st_async_is_not_supported_before_SM_90__();
-template <typename _B32>
+template <typename _B32, _CUDA_VSTD::enable_if_t<sizeof(_B32) == 4, bool> = true>
 _CCCL_DEVICE static inline void st_async(_B32* __addr, const _B32 (&__value)[4], _CUDA_VSTD::uint64_t* __remote_bar)
 {
   static_assert(sizeof(_B32) == 4, "");
-  NV_IF_ELSE_TARGET(
-    NV_PROVIDES_SM_90,
-    (asm("st.async.weak.shared::cluster.mbarrier::complete_tx::bytes.v4.b32 [%0], {%1, %2, %3, %4}, [%5];    // "
-         "3. " : : "r"(__as_ptr_remote_dsmem(__addr)),
-         "r"(__as_b32(__value[0])),
-         "r"(__as_b32(__value[1])),
-         "r"(__as_b32(__value[2])),
-         "r"(__as_b32(__value[3])),
-         "r"(__as_ptr_remote_dsmem(__remote_bar)) : "memory");),
-    (
-      // Unsupported architectures will have a linker error with a semi-decent error message
-      __cuda_ptx_st_async_is_not_supported_before_SM_90__();));
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  asm("st.async.weak.shared::cluster.mbarrier::complete_tx::bytes.v4.b32 [%0], {%1, %2, %3, %4}, [%5];    // 3. "
+      :
+      : "r"(__as_ptr_remote_dsmem(__addr)),
+        "r"(__as_b32(__value[0])),
+        "r"(__as_b32(__value[1])),
+        "r"(__as_b32(__value[2])),
+        "r"(__as_b32(__value[3])),
+        "r"(__as_ptr_remote_dsmem(__remote_bar))
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_st_async_is_not_supported_before_SM_90__();
+#  endif
 }
 #endif // __cccl_ptx_isa >= 810
 
diff --git a/libcudacxx/include/cuda/__ptx/instructions/generated/st_bulk.h b/libcudacxx/include/cuda/__ptx/instructions/generated/st_bulk.h
new file mode 100644
index 00000000000..bc02c785f86
--- /dev/null
+++ b/libcudacxx/include/cuda/__ptx/instructions/generated/st_bulk.h
@@ -0,0 +1,31 @@
+// This file was automatically generated. Do not edit.
+
+#ifndef _CUDA_PTX_GENERATED_ST_BULK_H_
+#define _CUDA_PTX_GENERATED_ST_BULK_H_
+
+/*
+// st.bulk.weak.shared::cta [addr], size, initval; // PTX ISA 86, SM_100
+template <int N32>
+__device__ static inline void st_bulk(
+  void* addr,
+  uint64_t size,
+  cuda::ptx::n32_t<N32> initval);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_st_bulk_is_not_supported_before_SM_100__();
+template <int _N32>
+_CCCL_DEVICE static inline void st_bulk(void* __addr, _CUDA_VSTD::uint64_t __size, n32_t<_N32> __initval)
+{
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 1000
+  asm("st.bulk.weak.shared::cta [%0], %1, %2;"
+      :
+      : "r"(__as_ptr_smem(__addr)), "l"(__size), "n"(__initval.value)
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_st_bulk_is_not_supported_before_SM_100__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+#endif // _CUDA_PTX_GENERATED_ST_BULK_H_
diff --git a/libcudacxx/include/cuda/__ptx/instructions/generated/tcgen05_alloc.h b/libcudacxx/include/cuda/__ptx/instructions/generated/tcgen05_alloc.h
new file mode 100644
index 00000000000..27ca2f86080
--- /dev/null
+++ b/libcudacxx/include/cuda/__ptx/instructions/generated/tcgen05_alloc.h
@@ -0,0 +1,105 @@
+// This file was automatically generated. Do not edit.
+
+#ifndef _CUDA_PTX_GENERATED_TCGEN05_ALLOC_H_
+#define _CUDA_PTX_GENERATED_TCGEN05_ALLOC_H_
+
+/*
+// tcgen05.alloc.cta_group.sync.aligned.shared::cta.b32 [dst], nCols; // PTX ISA 86, SM_100a, SM_101a
+// .cta_group = { .cta_group::1, .cta_group::2 }
+template <cuda::ptx::dot_cta_group Cta_Group>
+__device__ static inline void tcgen05_alloc(
+  cuda::ptx::cta_group_t<Cta_Group> cta_group,
+  uint32_t* dst,
+  const uint32_t& nCols);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_alloc_is_not_supported_before_SM_100a_SM_101a__();
+template <dot_cta_group _Cta_Group>
+_CCCL_DEVICE static inline void
+tcgen05_alloc(cta_group_t<_Cta_Group> __cta_group, _CUDA_VSTD::uint32_t* __dst, const _CUDA_VSTD::uint32_t& __nCols)
+{
+  static_assert(__cta_group == cta_group_1 || __cta_group == cta_group_2, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  _CCCL_IF_CONSTEXPR (__cta_group == cta_group_1)
+  {
+    asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;"
+                 :
+                 : "r"(__as_ptr_smem(__dst)), "r"(__nCols)
+                 : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__cta_group == cta_group_2)
+  {
+    asm volatile("tcgen05.alloc.cta_group::2.sync.aligned.shared::cta.b32 [%0], %1;"
+                 :
+                 : "r"(__as_ptr_smem(__dst)), "r"(__nCols)
+                 : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_alloc_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.dealloc.cta_group.sync.aligned.b32 taddr, nCols; // PTX ISA 86, SM_100a, SM_101a
+// .cta_group = { .cta_group::1, .cta_group::2 }
+template <cuda::ptx::dot_cta_group Cta_Group>
+__device__ static inline void tcgen05_dealloc(
+  cuda::ptx::cta_group_t<Cta_Group> cta_group,
+  uint32_t taddr,
+  const uint32_t& nCols);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_dealloc_is_not_supported_before_SM_100a_SM_101a__();
+template <dot_cta_group _Cta_Group>
+_CCCL_DEVICE static inline void
+tcgen05_dealloc(cta_group_t<_Cta_Group> __cta_group, _CUDA_VSTD::uint32_t __taddr, const _CUDA_VSTD::uint32_t& __nCols)
+{
+  static_assert(__cta_group == cta_group_1 || __cta_group == cta_group_2, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  _CCCL_IF_CONSTEXPR (__cta_group == cta_group_1)
+  {
+    asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" : : "r"(__taddr), "r"(__nCols) : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__cta_group == cta_group_2)
+  {
+    asm volatile("tcgen05.dealloc.cta_group::2.sync.aligned.b32 %0, %1;" : : "r"(__taddr), "r"(__nCols) : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_dealloc_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.relinquish_alloc_permit.cta_group.sync.aligned; // PTX ISA 86, SM_100a, SM_101a
+// .cta_group = { .cta_group::1, .cta_group::2 }
+template <cuda::ptx::dot_cta_group Cta_Group>
+__device__ static inline void tcgen05_relinquish_alloc_permit(
+  cuda::ptx::cta_group_t<Cta_Group> cta_group);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_relinquish_alloc_permit_is_not_supported_before_SM_100a_SM_101a__();
+template <dot_cta_group _Cta_Group>
+_CCCL_DEVICE static inline void tcgen05_relinquish_alloc_permit(cta_group_t<_Cta_Group> __cta_group)
+{
+  static_assert(__cta_group == cta_group_1 || __cta_group == cta_group_2, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  _CCCL_IF_CONSTEXPR (__cta_group == cta_group_1)
+  {
+    asm volatile("tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;" : : : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__cta_group == cta_group_2)
+  {
+    asm volatile("tcgen05.relinquish_alloc_permit.cta_group::2.sync.aligned;" : : : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_relinquish_alloc_permit_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+#endif // _CUDA_PTX_GENERATED_TCGEN05_ALLOC_H_
diff --git a/libcudacxx/include/cuda/__ptx/instructions/generated/tcgen05_commit.h b/libcudacxx/include/cuda/__ptx/instructions/generated/tcgen05_commit.h
new file mode 100644
index 00000000000..30865d000df
--- /dev/null
+++ b/libcudacxx/include/cuda/__ptx/instructions/generated/tcgen05_commit.h
@@ -0,0 +1,81 @@
+// This file was automatically generated. Do not edit.
+
+#ifndef _CUDA_PTX_GENERATED_TCGEN05_COMMIT_H_
+#define _CUDA_PTX_GENERATED_TCGEN05_COMMIT_H_
+
+/*
+// tcgen05.commit.cta_group.mbarrier::arrive::one.shared::cluster.b64 [smem_bar]; // PTX ISA 86, SM_100a, SM_101a
+// .cta_group = { .cta_group::1, .cta_group::2 }
+template <cuda::ptx::dot_cta_group Cta_Group>
+__device__ static inline void tcgen05_commit(
+  cuda::ptx::cta_group_t<Cta_Group> cta_group,
+  uint64_t* smem_bar);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_commit_is_not_supported_before_SM_100a_SM_101a__();
+template <dot_cta_group _Cta_Group>
+_CCCL_DEVICE static inline void tcgen05_commit(cta_group_t<_Cta_Group> __cta_group, _CUDA_VSTD::uint64_t* __smem_bar)
+{
+  static_assert(__cta_group == cta_group_1 || __cta_group == cta_group_2, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  _CCCL_IF_CONSTEXPR (__cta_group == cta_group_1)
+  {
+    asm volatile("tcgen05.commit.cta_group::1.mbarrier::arrive::one.shared::cluster.b64 [%0];"
+                 :
+                 : "r"(__as_ptr_dsmem(__smem_bar))
+                 : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__cta_group == cta_group_2)
+  {
+    asm volatile("tcgen05.commit.cta_group::2.mbarrier::arrive::one.shared::cluster.b64 [%0];"
+                 :
+                 : "r"(__as_ptr_dsmem(__smem_bar))
+                 : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_commit_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.commit.cta_group.mbarrier::arrive::one.shared::cluster.multicast::cluster.b64 [smem_bar], ctaMask; // PTX ISA
+86, SM_100a, SM_101a
+// .cta_group = { .cta_group::1, .cta_group::2 }
+template <cuda::ptx::dot_cta_group Cta_Group>
+__device__ static inline void tcgen05_commit_multicast(
+  cuda::ptx::cta_group_t<Cta_Group> cta_group,
+  uint64_t* smem_bar,
+  uint16_t ctaMask);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_commit_multicast_is_not_supported_before_SM_100a_SM_101a__();
+template <dot_cta_group _Cta_Group>
+_CCCL_DEVICE static inline void tcgen05_commit_multicast(
+  cta_group_t<_Cta_Group> __cta_group, _CUDA_VSTD::uint64_t* __smem_bar, _CUDA_VSTD::uint16_t __ctaMask)
+{
+  static_assert(__cta_group == cta_group_1 || __cta_group == cta_group_2, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  _CCCL_IF_CONSTEXPR (__cta_group == cta_group_1)
+  {
+    asm volatile("tcgen05.commit.cta_group::1.mbarrier::arrive::one.shared::cluster.multicast::cluster.b64 [%0], %1;"
+                 :
+                 : "r"(__as_ptr_dsmem(__smem_bar)), "h"(__ctaMask)
+                 : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__cta_group == cta_group_2)
+  {
+    asm volatile("tcgen05.commit.cta_group::2.mbarrier::arrive::one.shared::cluster.multicast::cluster.b64 [%0], %1;"
+                 :
+                 : "r"(__as_ptr_dsmem(__smem_bar)), "h"(__ctaMask)
+                 : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_commit_multicast_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+#endif // _CUDA_PTX_GENERATED_TCGEN05_COMMIT_H_
diff --git a/libcudacxx/include/cuda/__ptx/instructions/generated/tcgen05_cp.h b/libcudacxx/include/cuda/__ptx/instructions/generated/tcgen05_cp.h
new file mode 100644
index 00000000000..e213f9ba745
--- /dev/null
+++ b/libcudacxx/include/cuda/__ptx/instructions/generated/tcgen05_cp.h
@@ -0,0 +1,612 @@
+// This file was automatically generated. Do not edit.
+
+#ifndef _CUDA_PTX_GENERATED_TCGEN05_CP_H_
+#define _CUDA_PTX_GENERATED_TCGEN05_CP_H_
+
+/*
+// tcgen05.cp.cta_group.128x256b [taddr], s_desc; // PTX ISA 86, SM_100a, SM_101a
+// .cta_group = { .cta_group::1, .cta_group::2 }
+template <cuda::ptx::dot_cta_group Cta_Group>
+__device__ static inline void tcgen05_cp_128x256b(
+  cuda::ptx::cta_group_t<Cta_Group> cta_group,
+  uint32_t taddr,
+  uint64_t s_desc);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_cp_128x256b_is_not_supported_before_SM_100a_SM_101a__();
+template <dot_cta_group _Cta_Group>
+_CCCL_DEVICE static inline void
+tcgen05_cp_128x256b(cta_group_t<_Cta_Group> __cta_group, _CUDA_VSTD::uint32_t __taddr, _CUDA_VSTD::uint64_t __s_desc)
+{
+  static_assert(__cta_group == cta_group_1 || __cta_group == cta_group_2, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  _CCCL_IF_CONSTEXPR (__cta_group == cta_group_1)
+  {
+    asm("tcgen05.cp.cta_group::1.128x256b [%0], %1;" : : "r"(__taddr), "l"(__s_desc) : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__cta_group == cta_group_2)
+  {
+    asm("tcgen05.cp.cta_group::2.128x256b [%0], %1;" : : "r"(__taddr), "l"(__s_desc) : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_cp_128x256b_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.cp.cta_group.4x256b [taddr], s_desc; // PTX ISA 86, SM_100a, SM_101a
+// .cta_group = { .cta_group::1, .cta_group::2 }
+template <cuda::ptx::dot_cta_group Cta_Group>
+__device__ static inline void tcgen05_cp_4x256b(
+  cuda::ptx::cta_group_t<Cta_Group> cta_group,
+  uint32_t taddr,
+  uint64_t s_desc);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_cp_4x256b_is_not_supported_before_SM_100a_SM_101a__();
+template <dot_cta_group _Cta_Group>
+_CCCL_DEVICE static inline void
+tcgen05_cp_4x256b(cta_group_t<_Cta_Group> __cta_group, _CUDA_VSTD::uint32_t __taddr, _CUDA_VSTD::uint64_t __s_desc)
+{
+  static_assert(__cta_group == cta_group_1 || __cta_group == cta_group_2, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  _CCCL_IF_CONSTEXPR (__cta_group == cta_group_1)
+  {
+    asm("tcgen05.cp.cta_group::1.4x256b [%0], %1;" : : "r"(__taddr), "l"(__s_desc) : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__cta_group == cta_group_2)
+  {
+    asm("tcgen05.cp.cta_group::2.4x256b [%0], %1;" : : "r"(__taddr), "l"(__s_desc) : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_cp_4x256b_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.cp.cta_group.128x128b [taddr], s_desc; // PTX ISA 86, SM_100a, SM_101a
+// .cta_group = { .cta_group::1, .cta_group::2 }
+template <cuda::ptx::dot_cta_group Cta_Group>
+__device__ static inline void tcgen05_cp_128x128b(
+  cuda::ptx::cta_group_t<Cta_Group> cta_group,
+  uint32_t taddr,
+  uint64_t s_desc);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_cp_128x128b_is_not_supported_before_SM_100a_SM_101a__();
+template <dot_cta_group _Cta_Group>
+_CCCL_DEVICE static inline void
+tcgen05_cp_128x128b(cta_group_t<_Cta_Group> __cta_group, _CUDA_VSTD::uint32_t __taddr, _CUDA_VSTD::uint64_t __s_desc)
+{
+  static_assert(__cta_group == cta_group_1 || __cta_group == cta_group_2, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  _CCCL_IF_CONSTEXPR (__cta_group == cta_group_1)
+  {
+    asm("tcgen05.cp.cta_group::1.128x128b [%0], %1;" : : "r"(__taddr), "l"(__s_desc) : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__cta_group == cta_group_2)
+  {
+    asm("tcgen05.cp.cta_group::2.128x128b [%0], %1;" : : "r"(__taddr), "l"(__s_desc) : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_cp_128x128b_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.cp.cta_group.64x128b.warpx2::02_13 [taddr], s_desc; // PTX ISA 86, SM_100a, SM_101a
+// .cta_group = { .cta_group::1, .cta_group::2 }
+template <cuda::ptx::dot_cta_group Cta_Group>
+__device__ static inline void tcgen05_cp_64x128b_warpx2_02_13(
+  cuda::ptx::cta_group_t<Cta_Group> cta_group,
+  uint32_t taddr,
+  uint64_t s_desc);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_cp_64x128b_warpx2_02_13_is_not_supported_before_SM_100a_SM_101a__();
+template <dot_cta_group _Cta_Group>
+_CCCL_DEVICE static inline void tcgen05_cp_64x128b_warpx2_02_13(
+  cta_group_t<_Cta_Group> __cta_group, _CUDA_VSTD::uint32_t __taddr, _CUDA_VSTD::uint64_t __s_desc)
+{
+  static_assert(__cta_group == cta_group_1 || __cta_group == cta_group_2, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  _CCCL_IF_CONSTEXPR (__cta_group == cta_group_1)
+  {
+    asm("tcgen05.cp.cta_group::1.64x128b.warpx2::02_13 [%0], %1;" : : "r"(__taddr), "l"(__s_desc) : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__cta_group == cta_group_2)
+  {
+    asm("tcgen05.cp.cta_group::2.64x128b.warpx2::02_13 [%0], %1;" : : "r"(__taddr), "l"(__s_desc) : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_cp_64x128b_warpx2_02_13_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.cp.cta_group.64x128b.warpx2::01_23 [taddr], s_desc; // PTX ISA 86, SM_100a, SM_101a
+// .cta_group = { .cta_group::1, .cta_group::2 }
+template <cuda::ptx::dot_cta_group Cta_Group>
+__device__ static inline void tcgen05_cp_64x128b_warpx2_01_23(
+  cuda::ptx::cta_group_t<Cta_Group> cta_group,
+  uint32_t taddr,
+  uint64_t s_desc);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_cp_64x128b_warpx2_01_23_is_not_supported_before_SM_100a_SM_101a__();
+template <dot_cta_group _Cta_Group>
+_CCCL_DEVICE static inline void tcgen05_cp_64x128b_warpx2_01_23(
+  cta_group_t<_Cta_Group> __cta_group, _CUDA_VSTD::uint32_t __taddr, _CUDA_VSTD::uint64_t __s_desc)
+{
+  static_assert(__cta_group == cta_group_1 || __cta_group == cta_group_2, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  _CCCL_IF_CONSTEXPR (__cta_group == cta_group_1)
+  {
+    asm("tcgen05.cp.cta_group::1.64x128b.warpx2::01_23 [%0], %1;" : : "r"(__taddr), "l"(__s_desc) : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__cta_group == cta_group_2)
+  {
+    asm("tcgen05.cp.cta_group::2.64x128b.warpx2::01_23 [%0], %1;" : : "r"(__taddr), "l"(__s_desc) : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_cp_64x128b_warpx2_01_23_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.cp.cta_group.32x128b.warpx4 [taddr], s_desc; // PTX ISA 86, SM_100a, SM_101a
+// .cta_group = { .cta_group::1, .cta_group::2 }
+template <cuda::ptx::dot_cta_group Cta_Group>
+__device__ static inline void tcgen05_cp_32x128b_warpx4(
+  cuda::ptx::cta_group_t<Cta_Group> cta_group,
+  uint32_t taddr,
+  uint64_t s_desc);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_cp_32x128b_warpx4_is_not_supported_before_SM_100a_SM_101a__();
+template <dot_cta_group _Cta_Group>
+_CCCL_DEVICE static inline void tcgen05_cp_32x128b_warpx4(
+  cta_group_t<_Cta_Group> __cta_group, _CUDA_VSTD::uint32_t __taddr, _CUDA_VSTD::uint64_t __s_desc)
+{
+  static_assert(__cta_group == cta_group_1 || __cta_group == cta_group_2, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  _CCCL_IF_CONSTEXPR (__cta_group == cta_group_1)
+  {
+    asm("tcgen05.cp.cta_group::1.32x128b.warpx4 [%0], %1;" : : "r"(__taddr), "l"(__s_desc) : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__cta_group == cta_group_2)
+  {
+    asm("tcgen05.cp.cta_group::2.32x128b.warpx4 [%0], %1;" : : "r"(__taddr), "l"(__s_desc) : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_cp_32x128b_warpx4_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.cp.cta_group.128x256b.b8x16.b6x16_p32 [taddr], s_desc; // PTX ISA 86, SM_100a, SM_101a
+// .cta_group = { .cta_group::1, .cta_group::2 }
+template <cuda::ptx::dot_cta_group Cta_Group>
+__device__ static inline void tcgen05_cp_128x256b_b8x16_b6x16_p32(
+  cuda::ptx::cta_group_t<Cta_Group> cta_group,
+  uint32_t taddr,
+  uint64_t s_desc);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_cp_128x256b_b8x16_b6x16_p32_is_not_supported_before_SM_100a_SM_101a__();
+template <dot_cta_group _Cta_Group>
+_CCCL_DEVICE static inline void tcgen05_cp_128x256b_b8x16_b6x16_p32(
+  cta_group_t<_Cta_Group> __cta_group, _CUDA_VSTD::uint32_t __taddr, _CUDA_VSTD::uint64_t __s_desc)
+{
+  static_assert(__cta_group == cta_group_1 || __cta_group == cta_group_2, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  _CCCL_IF_CONSTEXPR (__cta_group == cta_group_1)
+  {
+    asm("tcgen05.cp.cta_group::1.128x256b.b8x16.b6x16_p32 [%0], %1;" : : "r"(__taddr), "l"(__s_desc) : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__cta_group == cta_group_2)
+  {
+    asm("tcgen05.cp.cta_group::2.128x256b.b8x16.b6x16_p32 [%0], %1;" : : "r"(__taddr), "l"(__s_desc) : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_cp_128x256b_b8x16_b6x16_p32_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.cp.cta_group.4x256b.b8x16.b6x16_p32 [taddr], s_desc; // PTX ISA 86, SM_100a, SM_101a
+// .cta_group = { .cta_group::1, .cta_group::2 }
+template <cuda::ptx::dot_cta_group Cta_Group>
+__device__ static inline void tcgen05_cp_4x256b_b8x16_b6x16_p32(
+  cuda::ptx::cta_group_t<Cta_Group> cta_group,
+  uint32_t taddr,
+  uint64_t s_desc);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_cp_4x256b_b8x16_b6x16_p32_is_not_supported_before_SM_100a_SM_101a__();
+template <dot_cta_group _Cta_Group>
+_CCCL_DEVICE static inline void tcgen05_cp_4x256b_b8x16_b6x16_p32(
+  cta_group_t<_Cta_Group> __cta_group, _CUDA_VSTD::uint32_t __taddr, _CUDA_VSTD::uint64_t __s_desc)
+{
+  static_assert(__cta_group == cta_group_1 || __cta_group == cta_group_2, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  _CCCL_IF_CONSTEXPR (__cta_group == cta_group_1)
+  {
+    asm("tcgen05.cp.cta_group::1.4x256b.b8x16.b6x16_p32 [%0], %1;" : : "r"(__taddr), "l"(__s_desc) : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__cta_group == cta_group_2)
+  {
+    asm("tcgen05.cp.cta_group::2.4x256b.b8x16.b6x16_p32 [%0], %1;" : : "r"(__taddr), "l"(__s_desc) : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_cp_4x256b_b8x16_b6x16_p32_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.cp.cta_group.128x128b.b8x16.b6x16_p32 [taddr], s_desc; // PTX ISA 86, SM_100a, SM_101a
+// .cta_group = { .cta_group::1, .cta_group::2 }
+template <cuda::ptx::dot_cta_group Cta_Group>
+__device__ static inline void tcgen05_cp_128x128b_b8x16_b6x16_p32(
+  cuda::ptx::cta_group_t<Cta_Group> cta_group,
+  uint32_t taddr,
+  uint64_t s_desc);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_cp_128x128b_b8x16_b6x16_p32_is_not_supported_before_SM_100a_SM_101a__();
+template <dot_cta_group _Cta_Group>
+_CCCL_DEVICE static inline void tcgen05_cp_128x128b_b8x16_b6x16_p32(
+  cta_group_t<_Cta_Group> __cta_group, _CUDA_VSTD::uint32_t __taddr, _CUDA_VSTD::uint64_t __s_desc)
+{
+  static_assert(__cta_group == cta_group_1 || __cta_group == cta_group_2, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  _CCCL_IF_CONSTEXPR (__cta_group == cta_group_1)
+  {
+    asm("tcgen05.cp.cta_group::1.128x128b.b8x16.b6x16_p32 [%0], %1;" : : "r"(__taddr), "l"(__s_desc) : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__cta_group == cta_group_2)
+  {
+    asm("tcgen05.cp.cta_group::2.128x128b.b8x16.b6x16_p32 [%0], %1;" : : "r"(__taddr), "l"(__s_desc) : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_cp_128x128b_b8x16_b6x16_p32_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.cp.cta_group.64x128b.warpx2::02_13.b8x16.b6x16_p32 [taddr], s_desc; // PTX ISA 86, SM_100a, SM_101a
+// .cta_group = { .cta_group::1, .cta_group::2 }
+template <cuda::ptx::dot_cta_group Cta_Group>
+__device__ static inline void tcgen05_cp_64x128b_warpx2_02_13_b8x16_b6x16_p32(
+  cuda::ptx::cta_group_t<Cta_Group> cta_group,
+  uint32_t taddr,
+  uint64_t s_desc);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void
+__cuda_ptx_tcgen05_cp_64x128b_warpx2_02_13_b8x16_b6x16_p32_is_not_supported_before_SM_100a_SM_101a__();
+template <dot_cta_group _Cta_Group>
+_CCCL_DEVICE static inline void tcgen05_cp_64x128b_warpx2_02_13_b8x16_b6x16_p32(
+  cta_group_t<_Cta_Group> __cta_group, _CUDA_VSTD::uint32_t __taddr, _CUDA_VSTD::uint64_t __s_desc)
+{
+  static_assert(__cta_group == cta_group_1 || __cta_group == cta_group_2, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  _CCCL_IF_CONSTEXPR (__cta_group == cta_group_1)
+  {
+    asm("tcgen05.cp.cta_group::1.64x128b.warpx2::02_13.b8x16.b6x16_p32 [%0], %1;"
+        :
+        : "r"(__taddr), "l"(__s_desc)
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__cta_group == cta_group_2)
+  {
+    asm("tcgen05.cp.cta_group::2.64x128b.warpx2::02_13.b8x16.b6x16_p32 [%0], %1;"
+        :
+        : "r"(__taddr), "l"(__s_desc)
+        : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_cp_64x128b_warpx2_02_13_b8x16_b6x16_p32_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.cp.cta_group.64x128b.warpx2::01_23.b8x16.b6x16_p32 [taddr], s_desc; // PTX ISA 86, SM_100a, SM_101a
+// .cta_group = { .cta_group::1, .cta_group::2 }
+template <cuda::ptx::dot_cta_group Cta_Group>
+__device__ static inline void tcgen05_cp_64x128b_warpx2_01_23_b8x16_b6x16_p32(
+  cuda::ptx::cta_group_t<Cta_Group> cta_group,
+  uint32_t taddr,
+  uint64_t s_desc);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void
+__cuda_ptx_tcgen05_cp_64x128b_warpx2_01_23_b8x16_b6x16_p32_is_not_supported_before_SM_100a_SM_101a__();
+template <dot_cta_group _Cta_Group>
+_CCCL_DEVICE static inline void tcgen05_cp_64x128b_warpx2_01_23_b8x16_b6x16_p32(
+  cta_group_t<_Cta_Group> __cta_group, _CUDA_VSTD::uint32_t __taddr, _CUDA_VSTD::uint64_t __s_desc)
+{
+  static_assert(__cta_group == cta_group_1 || __cta_group == cta_group_2, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  _CCCL_IF_CONSTEXPR (__cta_group == cta_group_1)
+  {
+    asm("tcgen05.cp.cta_group::1.64x128b.warpx2::01_23.b8x16.b6x16_p32 [%0], %1;"
+        :
+        : "r"(__taddr), "l"(__s_desc)
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__cta_group == cta_group_2)
+  {
+    asm("tcgen05.cp.cta_group::2.64x128b.warpx2::01_23.b8x16.b6x16_p32 [%0], %1;"
+        :
+        : "r"(__taddr), "l"(__s_desc)
+        : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_cp_64x128b_warpx2_01_23_b8x16_b6x16_p32_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.cp.cta_group.32x128b.warpx4.b8x16.b6x16_p32 [taddr], s_desc; // PTX ISA 86, SM_100a, SM_101a
+// .cta_group = { .cta_group::1, .cta_group::2 }
+template <cuda::ptx::dot_cta_group Cta_Group>
+__device__ static inline void tcgen05_cp_32x128b_warpx4_b8x16_b6x16_p32(
+  cuda::ptx::cta_group_t<Cta_Group> cta_group,
+  uint32_t taddr,
+  uint64_t s_desc);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void
+__cuda_ptx_tcgen05_cp_32x128b_warpx4_b8x16_b6x16_p32_is_not_supported_before_SM_100a_SM_101a__();
+template <dot_cta_group _Cta_Group>
+_CCCL_DEVICE static inline void tcgen05_cp_32x128b_warpx4_b8x16_b6x16_p32(
+  cta_group_t<_Cta_Group> __cta_group, _CUDA_VSTD::uint32_t __taddr, _CUDA_VSTD::uint64_t __s_desc)
+{
+  static_assert(__cta_group == cta_group_1 || __cta_group == cta_group_2, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  _CCCL_IF_CONSTEXPR (__cta_group == cta_group_1)
+  {
+    asm("tcgen05.cp.cta_group::1.32x128b.warpx4.b8x16.b6x16_p32 [%0], %1;" : : "r"(__taddr), "l"(__s_desc) : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__cta_group == cta_group_2)
+  {
+    asm("tcgen05.cp.cta_group::2.32x128b.warpx4.b8x16.b6x16_p32 [%0], %1;" : : "r"(__taddr), "l"(__s_desc) : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_cp_32x128b_warpx4_b8x16_b6x16_p32_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.cp.cta_group.128x256b.b8x16.b4x16_p64 [taddr], s_desc; // PTX ISA 86, SM_100a, SM_101a
+// .cta_group = { .cta_group::1, .cta_group::2 }
+template <cuda::ptx::dot_cta_group Cta_Group>
+__device__ static inline void tcgen05_cp_128x256b_b8x16_b4x16_p64(
+  cuda::ptx::cta_group_t<Cta_Group> cta_group,
+  uint32_t taddr,
+  uint64_t s_desc);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_cp_128x256b_b8x16_b4x16_p64_is_not_supported_before_SM_100a_SM_101a__();
+template <dot_cta_group _Cta_Group>
+_CCCL_DEVICE static inline void tcgen05_cp_128x256b_b8x16_b4x16_p64(
+  cta_group_t<_Cta_Group> __cta_group, _CUDA_VSTD::uint32_t __taddr, _CUDA_VSTD::uint64_t __s_desc)
+{
+  static_assert(__cta_group == cta_group_1 || __cta_group == cta_group_2, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  _CCCL_IF_CONSTEXPR (__cta_group == cta_group_1)
+  {
+    asm("tcgen05.cp.cta_group::1.128x256b.b8x16.b4x16_p64 [%0], %1;" : : "r"(__taddr), "l"(__s_desc) : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__cta_group == cta_group_2)
+  {
+    asm("tcgen05.cp.cta_group::2.128x256b.b8x16.b4x16_p64 [%0], %1;" : : "r"(__taddr), "l"(__s_desc) : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_cp_128x256b_b8x16_b4x16_p64_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.cp.cta_group.4x256b.b8x16.b4x16_p64 [taddr], s_desc; // PTX ISA 86, SM_100a, SM_101a
+// .cta_group = { .cta_group::1, .cta_group::2 }
+template <cuda::ptx::dot_cta_group Cta_Group>
+__device__ static inline void tcgen05_cp_4x256b_b8x16_b4x16_p64(
+  cuda::ptx::cta_group_t<Cta_Group> cta_group,
+  uint32_t taddr,
+  uint64_t s_desc);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_cp_4x256b_b8x16_b4x16_p64_is_not_supported_before_SM_100a_SM_101a__();
+template <dot_cta_group _Cta_Group>
+_CCCL_DEVICE static inline void tcgen05_cp_4x256b_b8x16_b4x16_p64(
+  cta_group_t<_Cta_Group> __cta_group, _CUDA_VSTD::uint32_t __taddr, _CUDA_VSTD::uint64_t __s_desc)
+{
+  static_assert(__cta_group == cta_group_1 || __cta_group == cta_group_2, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  _CCCL_IF_CONSTEXPR (__cta_group == cta_group_1)
+  {
+    asm("tcgen05.cp.cta_group::1.4x256b.b8x16.b4x16_p64 [%0], %1;" : : "r"(__taddr), "l"(__s_desc) : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__cta_group == cta_group_2)
+  {
+    asm("tcgen05.cp.cta_group::2.4x256b.b8x16.b4x16_p64 [%0], %1;" : : "r"(__taddr), "l"(__s_desc) : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_cp_4x256b_b8x16_b4x16_p64_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.cp.cta_group.128x128b.b8x16.b4x16_p64 [taddr], s_desc; // PTX ISA 86, SM_100a, SM_101a
+// .cta_group = { .cta_group::1, .cta_group::2 }
+template <cuda::ptx::dot_cta_group Cta_Group>
+__device__ static inline void tcgen05_cp_128x128b_b8x16_b4x16_p64(
+  cuda::ptx::cta_group_t<Cta_Group> cta_group,
+  uint32_t taddr,
+  uint64_t s_desc);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_cp_128x128b_b8x16_b4x16_p64_is_not_supported_before_SM_100a_SM_101a__();
+template <dot_cta_group _Cta_Group>
+_CCCL_DEVICE static inline void tcgen05_cp_128x128b_b8x16_b4x16_p64(
+  cta_group_t<_Cta_Group> __cta_group, _CUDA_VSTD::uint32_t __taddr, _CUDA_VSTD::uint64_t __s_desc)
+{
+  static_assert(__cta_group == cta_group_1 || __cta_group == cta_group_2, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  _CCCL_IF_CONSTEXPR (__cta_group == cta_group_1)
+  {
+    asm("tcgen05.cp.cta_group::1.128x128b.b8x16.b4x16_p64 [%0], %1;" : : "r"(__taddr), "l"(__s_desc) : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__cta_group == cta_group_2)
+  {
+    asm("tcgen05.cp.cta_group::2.128x128b.b8x16.b4x16_p64 [%0], %1;" : : "r"(__taddr), "l"(__s_desc) : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_cp_128x128b_b8x16_b4x16_p64_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.cp.cta_group.64x128b.warpx2::02_13.b8x16.b4x16_p64 [taddr], s_desc; // PTX ISA 86, SM_100a, SM_101a
+// .cta_group = { .cta_group::1, .cta_group::2 }
+template <cuda::ptx::dot_cta_group Cta_Group>
+__device__ static inline void tcgen05_cp_64x128b_warpx2_02_13_b8x16_b4x16_p64(
+  cuda::ptx::cta_group_t<Cta_Group> cta_group,
+  uint32_t taddr,
+  uint64_t s_desc);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void
+__cuda_ptx_tcgen05_cp_64x128b_warpx2_02_13_b8x16_b4x16_p64_is_not_supported_before_SM_100a_SM_101a__();
+template <dot_cta_group _Cta_Group>
+_CCCL_DEVICE static inline void tcgen05_cp_64x128b_warpx2_02_13_b8x16_b4x16_p64(
+  cta_group_t<_Cta_Group> __cta_group, _CUDA_VSTD::uint32_t __taddr, _CUDA_VSTD::uint64_t __s_desc)
+{
+  static_assert(__cta_group == cta_group_1 || __cta_group == cta_group_2, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  _CCCL_IF_CONSTEXPR (__cta_group == cta_group_1)
+  {
+    asm("tcgen05.cp.cta_group::1.64x128b.warpx2::02_13.b8x16.b4x16_p64 [%0], %1;"
+        :
+        : "r"(__taddr), "l"(__s_desc)
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__cta_group == cta_group_2)
+  {
+    asm("tcgen05.cp.cta_group::2.64x128b.warpx2::02_13.b8x16.b4x16_p64 [%0], %1;"
+        :
+        : "r"(__taddr), "l"(__s_desc)
+        : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_cp_64x128b_warpx2_02_13_b8x16_b4x16_p64_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.cp.cta_group.64x128b.warpx2::01_23.b8x16.b4x16_p64 [taddr], s_desc; // PTX ISA 86, SM_100a, SM_101a
+// .cta_group = { .cta_group::1, .cta_group::2 }
+template <cuda::ptx::dot_cta_group Cta_Group>
+__device__ static inline void tcgen05_cp_64x128b_warpx2_01_23_b8x16_b4x16_p64(
+  cuda::ptx::cta_group_t<Cta_Group> cta_group,
+  uint32_t taddr,
+  uint64_t s_desc);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void
+__cuda_ptx_tcgen05_cp_64x128b_warpx2_01_23_b8x16_b4x16_p64_is_not_supported_before_SM_100a_SM_101a__();
+template <dot_cta_group _Cta_Group>
+_CCCL_DEVICE static inline void tcgen05_cp_64x128b_warpx2_01_23_b8x16_b4x16_p64(
+  cta_group_t<_Cta_Group> __cta_group, _CUDA_VSTD::uint32_t __taddr, _CUDA_VSTD::uint64_t __s_desc)
+{
+  static_assert(__cta_group == cta_group_1 || __cta_group == cta_group_2, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  _CCCL_IF_CONSTEXPR (__cta_group == cta_group_1)
+  {
+    asm("tcgen05.cp.cta_group::1.64x128b.warpx2::01_23.b8x16.b4x16_p64 [%0], %1;"
+        :
+        : "r"(__taddr), "l"(__s_desc)
+        : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__cta_group == cta_group_2)
+  {
+    asm("tcgen05.cp.cta_group::2.64x128b.warpx2::01_23.b8x16.b4x16_p64 [%0], %1;"
+        :
+        : "r"(__taddr), "l"(__s_desc)
+        : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_cp_64x128b_warpx2_01_23_b8x16_b4x16_p64_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.cp.cta_group.32x128b.warpx4.b8x16.b4x16_p64 [taddr], s_desc; // PTX ISA 86, SM_100a, SM_101a
+// .cta_group = { .cta_group::1, .cta_group::2 }
+template <cuda::ptx::dot_cta_group Cta_Group>
+__device__ static inline void tcgen05_cp_32x128b_warpx4_b8x16_b4x16_p64(
+  cuda::ptx::cta_group_t<Cta_Group> cta_group,
+  uint32_t taddr,
+  uint64_t s_desc);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void
+__cuda_ptx_tcgen05_cp_32x128b_warpx4_b8x16_b4x16_p64_is_not_supported_before_SM_100a_SM_101a__();
+template <dot_cta_group _Cta_Group>
+_CCCL_DEVICE static inline void tcgen05_cp_32x128b_warpx4_b8x16_b4x16_p64(
+  cta_group_t<_Cta_Group> __cta_group, _CUDA_VSTD::uint32_t __taddr, _CUDA_VSTD::uint64_t __s_desc)
+{
+  static_assert(__cta_group == cta_group_1 || __cta_group == cta_group_2, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  _CCCL_IF_CONSTEXPR (__cta_group == cta_group_1)
+  {
+    asm("tcgen05.cp.cta_group::1.32x128b.warpx4.b8x16.b4x16_p64 [%0], %1;" : : "r"(__taddr), "l"(__s_desc) : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__cta_group == cta_group_2)
+  {
+    asm("tcgen05.cp.cta_group::2.32x128b.warpx4.b8x16.b4x16_p64 [%0], %1;" : : "r"(__taddr), "l"(__s_desc) : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_cp_32x128b_warpx4_b8x16_b4x16_p64_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+#endif // _CUDA_PTX_GENERATED_TCGEN05_CP_H_
diff --git a/libcudacxx/include/cuda/__ptx/instructions/generated/tcgen05_fence.h b/libcudacxx/include/cuda/__ptx/instructions/generated/tcgen05_fence.h
new file mode 100644
index 00000000000..efedcf86a57
--- /dev/null
+++ b/libcudacxx/include/cuda/__ptx/instructions/generated/tcgen05_fence.h
@@ -0,0 +1,44 @@
+// This file was automatically generated. Do not edit.
+
+#ifndef _CUDA_PTX_GENERATED_TCGEN05_FENCE_H_
+#define _CUDA_PTX_GENERATED_TCGEN05_FENCE_H_
+
+/*
+// tcgen05.fence::before_thread_sync; // PTX ISA 86, SM_100a, SM_101a
+template <typename = void>
+__device__ static inline void tcgen05_fence_before_thread_sync();
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_fence_before_thread_sync_is_not_supported_before_SM_100a_SM_101a__();
+template <typename = void>
+_CCCL_DEVICE static inline void tcgen05_fence_before_thread_sync()
+{
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  asm volatile("tcgen05.fence::before_thread_sync;" : : : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_fence_before_thread_sync_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.fence::after_thread_sync; // PTX ISA 86, SM_100a, SM_101a
+template <typename = void>
+__device__ static inline void tcgen05_fence_after_thread_sync();
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_fence_after_thread_sync_is_not_supported_before_SM_100a_SM_101a__();
+template <typename = void>
+_CCCL_DEVICE static inline void tcgen05_fence_after_thread_sync()
+{
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  asm volatile("tcgen05.fence::after_thread_sync;" : : : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_fence_after_thread_sync_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+#endif // _CUDA_PTX_GENERATED_TCGEN05_FENCE_H_
diff --git a/libcudacxx/include/cuda/__ptx/instructions/generated/tcgen05_ld.h b/libcudacxx/include/cuda/__ptx/instructions/generated/tcgen05_ld.h
new file mode 100644
index 00000000000..e5ec1b686c2
--- /dev/null
+++ b/libcudacxx/include/cuda/__ptx/instructions/generated/tcgen05_ld.h
@@ -0,0 +1,4446 @@
+// This file was automatically generated. Do not edit.
+
+#ifndef _CUDA_PTX_GENERATED_TCGEN05_LD_H_
+#define _CUDA_PTX_GENERATED_TCGEN05_LD_H_
+
+/*
+// tcgen05.ld.sync.aligned.16x64b.x1.b32 out, [taddr]; // PTX ISA 86, SM_100a, SM_101a
+template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+__device__ static inline void tcgen05_ld_16x64b(
+  B32 (&out)[1],
+  uint32_t taddr);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_ld_16x64b_is_not_supported_before_SM_100a_SM_101a__();
+template <typename _B32, _CUDA_VSTD::enable_if_t<sizeof(_B32) == 4, bool> = true>
+_CCCL_DEVICE static inline void tcgen05_ld_16x64b(_B32 (&__out)[1], _CUDA_VSTD::uint32_t __taddr)
+{
+  static_assert(sizeof(_B32) == 4, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  asm("tcgen05.ld.sync.aligned.16x64b.x1.b32 {%0}, [%1];" : "=r"(__out[0]) : "r"(__taddr) : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_ld_16x64b_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.ld.sync.aligned.16x64b.x1.pack::16b.b32 out, [taddr]; // PTX ISA 86, SM_100a, SM_101a
+template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+__device__ static inline void tcgen05_ld_16x64b_pack_16b(
+  B32 (&out)[1],
+  uint32_t taddr);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_ld_16x64b_pack_16b_is_not_supported_before_SM_100a_SM_101a__();
+template <typename _B32, _CUDA_VSTD::enable_if_t<sizeof(_B32) == 4, bool> = true>
+_CCCL_DEVICE static inline void tcgen05_ld_16x64b_pack_16b(_B32 (&__out)[1], _CUDA_VSTD::uint32_t __taddr)
+{
+  static_assert(sizeof(_B32) == 4, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  asm("tcgen05.ld.sync.aligned.16x64b.x1.pack::16b.b32 {%0}, [%1];" : "=r"(__out[0]) : "r"(__taddr) : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_ld_16x64b_pack_16b_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.ld.sync.aligned.16x64b.x2.b32 out, [taddr]; // PTX ISA 86, SM_100a, SM_101a
+template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+__device__ static inline void tcgen05_ld_16x64b(
+  B32 (&out)[2],
+  uint32_t taddr);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_ld_16x64b_is_not_supported_before_SM_100a_SM_101a__();
+template <typename _B32, _CUDA_VSTD::enable_if_t<sizeof(_B32) == 4, bool> = true>
+_CCCL_DEVICE static inline void tcgen05_ld_16x64b(_B32 (&__out)[2], _CUDA_VSTD::uint32_t __taddr)
+{
+  static_assert(sizeof(_B32) == 4, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  asm("tcgen05.ld.sync.aligned.16x64b.x2.b32 {%0, %1}, [%2];"
+      : "=r"(__out[0]), "=r"(__out[1])
+      : "r"(__taddr)
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_ld_16x64b_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.ld.sync.aligned.16x64b.x2.pack::16b.b32 out, [taddr]; // PTX ISA 86, SM_100a, SM_101a
+template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+__device__ static inline void tcgen05_ld_16x64b_pack_16b(
+  B32 (&out)[2],
+  uint32_t taddr);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_ld_16x64b_pack_16b_is_not_supported_before_SM_100a_SM_101a__();
+template <typename _B32, _CUDA_VSTD::enable_if_t<sizeof(_B32) == 4, bool> = true>
+_CCCL_DEVICE static inline void tcgen05_ld_16x64b_pack_16b(_B32 (&__out)[2], _CUDA_VSTD::uint32_t __taddr)
+{
+  static_assert(sizeof(_B32) == 4, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  asm("tcgen05.ld.sync.aligned.16x64b.x2.pack::16b.b32 {%0, %1}, [%2];"
+      : "=r"(__out[0]), "=r"(__out[1])
+      : "r"(__taddr)
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_ld_16x64b_pack_16b_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.ld.sync.aligned.16x64b.x4.b32 out, [taddr]; // PTX ISA 86, SM_100a, SM_101a
+template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+__device__ static inline void tcgen05_ld_16x64b(
+  B32 (&out)[4],
+  uint32_t taddr);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_ld_16x64b_is_not_supported_before_SM_100a_SM_101a__();
+template <typename _B32, _CUDA_VSTD::enable_if_t<sizeof(_B32) == 4, bool> = true>
+_CCCL_DEVICE static inline void tcgen05_ld_16x64b(_B32 (&__out)[4], _CUDA_VSTD::uint32_t __taddr)
+{
+  static_assert(sizeof(_B32) == 4, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  asm("tcgen05.ld.sync.aligned.16x64b.x4.b32 {%0, %1, %2, %3}, [%4];"
+      : "=r"(__out[0]), "=r"(__out[1]), "=r"(__out[2]), "=r"(__out[3])
+      : "r"(__taddr)
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_ld_16x64b_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.ld.sync.aligned.16x64b.x4.pack::16b.b32 out, [taddr]; // PTX ISA 86, SM_100a, SM_101a
+template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+__device__ static inline void tcgen05_ld_16x64b_pack_16b(
+  B32 (&out)[4],
+  uint32_t taddr);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_ld_16x64b_pack_16b_is_not_supported_before_SM_100a_SM_101a__();
+template <typename _B32, _CUDA_VSTD::enable_if_t<sizeof(_B32) == 4, bool> = true>
+_CCCL_DEVICE static inline void tcgen05_ld_16x64b_pack_16b(_B32 (&__out)[4], _CUDA_VSTD::uint32_t __taddr)
+{
+  static_assert(sizeof(_B32) == 4, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  asm("tcgen05.ld.sync.aligned.16x64b.x4.pack::16b.b32 {%0, %1, %2, %3}, [%4];"
+      : "=r"(__out[0]), "=r"(__out[1]), "=r"(__out[2]), "=r"(__out[3])
+      : "r"(__taddr)
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_ld_16x64b_pack_16b_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.ld.sync.aligned.16x64b.x8.b32 out, [taddr]; // PTX ISA 86, SM_100a, SM_101a
+template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+__device__ static inline void tcgen05_ld_16x64b(
+  B32 (&out)[8],
+  uint32_t taddr);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_ld_16x64b_is_not_supported_before_SM_100a_SM_101a__();
+template <typename _B32, _CUDA_VSTD::enable_if_t<sizeof(_B32) == 4, bool> = true>
+_CCCL_DEVICE static inline void tcgen05_ld_16x64b(_B32 (&__out)[8], _CUDA_VSTD::uint32_t __taddr)
+{
+  static_assert(sizeof(_B32) == 4, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  asm("tcgen05.ld.sync.aligned.16x64b.x8.b32 {%0, %1, %2, %3, %4, %5, %6, %7}, [%8];"
+      : "=r"(__out[0]),
+        "=r"(__out[1]),
+        "=r"(__out[2]),
+        "=r"(__out[3]),
+        "=r"(__out[4]),
+        "=r"(__out[5]),
+        "=r"(__out[6]),
+        "=r"(__out[7])
+      : "r"(__taddr)
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_ld_16x64b_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.ld.sync.aligned.16x64b.x8.pack::16b.b32 out, [taddr]; // PTX ISA 86, SM_100a, SM_101a
+template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+__device__ static inline void tcgen05_ld_16x64b_pack_16b(
+  B32 (&out)[8],
+  uint32_t taddr);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_ld_16x64b_pack_16b_is_not_supported_before_SM_100a_SM_101a__();
+template <typename _B32, _CUDA_VSTD::enable_if_t<sizeof(_B32) == 4, bool> = true>
+_CCCL_DEVICE static inline void tcgen05_ld_16x64b_pack_16b(_B32 (&__out)[8], _CUDA_VSTD::uint32_t __taddr)
+{
+  static_assert(sizeof(_B32) == 4, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  asm("tcgen05.ld.sync.aligned.16x64b.x8.pack::16b.b32 {%0, %1, %2, %3, %4, %5, %6, %7}, [%8];"
+      : "=r"(__out[0]),
+        "=r"(__out[1]),
+        "=r"(__out[2]),
+        "=r"(__out[3]),
+        "=r"(__out[4]),
+        "=r"(__out[5]),
+        "=r"(__out[6]),
+        "=r"(__out[7])
+      : "r"(__taddr)
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_ld_16x64b_pack_16b_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.ld.sync.aligned.16x64b.x16.b32 out, [taddr]; // PTX ISA 86, SM_100a, SM_101a
+template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+__device__ static inline void tcgen05_ld_16x64b(
+  B32 (&out)[16],
+  uint32_t taddr);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_ld_16x64b_is_not_supported_before_SM_100a_SM_101a__();
+template <typename _B32, _CUDA_VSTD::enable_if_t<sizeof(_B32) == 4, bool> = true>
+_CCCL_DEVICE static inline void tcgen05_ld_16x64b(_B32 (&__out)[16], _CUDA_VSTD::uint32_t __taddr)
+{
+  static_assert(sizeof(_B32) == 4, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  asm("tcgen05.ld.sync.aligned.16x64b.x16.b32 {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15}, "
+      "[%16];"
+      : "=r"(__out[0]),
+        "=r"(__out[1]),
+        "=r"(__out[2]),
+        "=r"(__out[3]),
+        "=r"(__out[4]),
+        "=r"(__out[5]),
+        "=r"(__out[6]),
+        "=r"(__out[7]),
+        "=r"(__out[8]),
+        "=r"(__out[9]),
+        "=r"(__out[10]),
+        "=r"(__out[11]),
+        "=r"(__out[12]),
+        "=r"(__out[13]),
+        "=r"(__out[14]),
+        "=r"(__out[15])
+      : "r"(__taddr)
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_ld_16x64b_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.ld.sync.aligned.16x64b.x16.pack::16b.b32 out, [taddr]; // PTX ISA 86, SM_100a, SM_101a
+template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+__device__ static inline void tcgen05_ld_16x64b_pack_16b(
+  B32 (&out)[16],
+  uint32_t taddr);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_ld_16x64b_pack_16b_is_not_supported_before_SM_100a_SM_101a__();
+template <typename _B32, _CUDA_VSTD::enable_if_t<sizeof(_B32) == 4, bool> = true>
+_CCCL_DEVICE static inline void tcgen05_ld_16x64b_pack_16b(_B32 (&__out)[16], _CUDA_VSTD::uint32_t __taddr)
+{
+  static_assert(sizeof(_B32) == 4, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  asm("tcgen05.ld.sync.aligned.16x64b.x16.pack::16b.b32 {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, "
+      "%14, %15}, [%16];"
+      : "=r"(__out[0]),
+        "=r"(__out[1]),
+        "=r"(__out[2]),
+        "=r"(__out[3]),
+        "=r"(__out[4]),
+        "=r"(__out[5]),
+        "=r"(__out[6]),
+        "=r"(__out[7]),
+        "=r"(__out[8]),
+        "=r"(__out[9]),
+        "=r"(__out[10]),
+        "=r"(__out[11]),
+        "=r"(__out[12]),
+        "=r"(__out[13]),
+        "=r"(__out[14]),
+        "=r"(__out[15])
+      : "r"(__taddr)
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_ld_16x64b_pack_16b_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.ld.sync.aligned.16x64b.x32.b32 out, [taddr]; // PTX ISA 86, SM_100a, SM_101a
+template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+__device__ static inline void tcgen05_ld_16x64b(
+  B32 (&out)[32],
+  uint32_t taddr);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_ld_16x64b_is_not_supported_before_SM_100a_SM_101a__();
+template <typename _B32, _CUDA_VSTD::enable_if_t<sizeof(_B32) == 4, bool> = true>
+_CCCL_DEVICE static inline void tcgen05_ld_16x64b(_B32 (&__out)[32], _CUDA_VSTD::uint32_t __taddr)
+{
+  static_assert(sizeof(_B32) == 4, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  asm(
+    "tcgen05.ld.sync.aligned.16x64b.x32.b32 {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, "
+    "%16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31}, [%32];"
+    : "=r"(__out[0]),
+      "=r"(__out[1]),
+      "=r"(__out[2]),
+      "=r"(__out[3]),
+      "=r"(__out[4]),
+      "=r"(__out[5]),
+      "=r"(__out[6]),
+      "=r"(__out[7]),
+      "=r"(__out[8]),
+      "=r"(__out[9]),
+      "=r"(__out[10]),
+      "=r"(__out[11]),
+      "=r"(__out[12]),
+      "=r"(__out[13]),
+      "=r"(__out[14]),
+      "=r"(__out[15]),
+      "=r"(__out[16]),
+      "=r"(__out[17]),
+      "=r"(__out[18]),
+      "=r"(__out[19]),
+      "=r"(__out[20]),
+      "=r"(__out[21]),
+      "=r"(__out[22]),
+      "=r"(__out[23]),
+      "=r"(__out[24]),
+      "=r"(__out[25]),
+      "=r"(__out[26]),
+      "=r"(__out[27]),
+      "=r"(__out[28]),
+      "=r"(__out[29]),
+      "=r"(__out[30]),
+      "=r"(__out[31])
+    : "r"(__taddr)
+    : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_ld_16x64b_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.ld.sync.aligned.16x64b.x32.pack::16b.b32 out, [taddr]; // PTX ISA 86, SM_100a, SM_101a
+template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+__device__ static inline void tcgen05_ld_16x64b_pack_16b(
+  B32 (&out)[32],
+  uint32_t taddr);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_ld_16x64b_pack_16b_is_not_supported_before_SM_100a_SM_101a__();
+template <typename _B32, _CUDA_VSTD::enable_if_t<sizeof(_B32) == 4, bool> = true>
+_CCCL_DEVICE static inline void tcgen05_ld_16x64b_pack_16b(_B32 (&__out)[32], _CUDA_VSTD::uint32_t __taddr)
+{
+  static_assert(sizeof(_B32) == 4, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  asm(
+    "tcgen05.ld.sync.aligned.16x64b.x32.pack::16b.b32 {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, "
+    "%14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31}, [%32];"
+    : "=r"(__out[0]),
+      "=r"(__out[1]),
+      "=r"(__out[2]),
+      "=r"(__out[3]),
+      "=r"(__out[4]),
+      "=r"(__out[5]),
+      "=r"(__out[6]),
+      "=r"(__out[7]),
+      "=r"(__out[8]),
+      "=r"(__out[9]),
+      "=r"(__out[10]),
+      "=r"(__out[11]),
+      "=r"(__out[12]),
+      "=r"(__out[13]),
+      "=r"(__out[14]),
+      "=r"(__out[15]),
+      "=r"(__out[16]),
+      "=r"(__out[17]),
+      "=r"(__out[18]),
+      "=r"(__out[19]),
+      "=r"(__out[20]),
+      "=r"(__out[21]),
+      "=r"(__out[22]),
+      "=r"(__out[23]),
+      "=r"(__out[24]),
+      "=r"(__out[25]),
+      "=r"(__out[26]),
+      "=r"(__out[27]),
+      "=r"(__out[28]),
+      "=r"(__out[29]),
+      "=r"(__out[30]),
+      "=r"(__out[31])
+    : "r"(__taddr)
+    : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_ld_16x64b_pack_16b_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.ld.sync.aligned.16x64b.x64.b32 out, [taddr]; // PTX ISA 86, SM_100a, SM_101a
+template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+__device__ static inline void tcgen05_ld_16x64b(
+  B32 (&out)[64],
+  uint32_t taddr);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_ld_16x64b_is_not_supported_before_SM_100a_SM_101a__();
+template <typename _B32, _CUDA_VSTD::enable_if_t<sizeof(_B32) == 4, bool> = true>
+_CCCL_DEVICE static inline void tcgen05_ld_16x64b(_B32 (&__out)[64], _CUDA_VSTD::uint32_t __taddr)
+{
+  static_assert(sizeof(_B32) == 4, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  asm(
+    "tcgen05.ld.sync.aligned.16x64b.x64.b32 {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, "
+    "%16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, "
+    "%38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, "
+    "%60, %61, %62, %63}, [%64];"
+    : "=r"(__out[0]),
+      "=r"(__out[1]),
+      "=r"(__out[2]),
+      "=r"(__out[3]),
+      "=r"(__out[4]),
+      "=r"(__out[5]),
+      "=r"(__out[6]),
+      "=r"(__out[7]),
+      "=r"(__out[8]),
+      "=r"(__out[9]),
+      "=r"(__out[10]),
+      "=r"(__out[11]),
+      "=r"(__out[12]),
+      "=r"(__out[13]),
+      "=r"(__out[14]),
+      "=r"(__out[15]),
+      "=r"(__out[16]),
+      "=r"(__out[17]),
+      "=r"(__out[18]),
+      "=r"(__out[19]),
+      "=r"(__out[20]),
+      "=r"(__out[21]),
+      "=r"(__out[22]),
+      "=r"(__out[23]),
+      "=r"(__out[24]),
+      "=r"(__out[25]),
+      "=r"(__out[26]),
+      "=r"(__out[27]),
+      "=r"(__out[28]),
+      "=r"(__out[29]),
+      "=r"(__out[30]),
+      "=r"(__out[31]),
+      "=r"(__out[32]),
+      "=r"(__out[33]),
+      "=r"(__out[34]),
+      "=r"(__out[35]),
+      "=r"(__out[36]),
+      "=r"(__out[37]),
+      "=r"(__out[38]),
+      "=r"(__out[39]),
+      "=r"(__out[40]),
+      "=r"(__out[41]),
+      "=r"(__out[42]),
+      "=r"(__out[43]),
+      "=r"(__out[44]),
+      "=r"(__out[45]),
+      "=r"(__out[46]),
+      "=r"(__out[47]),
+      "=r"(__out[48]),
+      "=r"(__out[49]),
+      "=r"(__out[50]),
+      "=r"(__out[51]),
+      "=r"(__out[52]),
+      "=r"(__out[53]),
+      "=r"(__out[54]),
+      "=r"(__out[55]),
+      "=r"(__out[56]),
+      "=r"(__out[57]),
+      "=r"(__out[58]),
+      "=r"(__out[59]),
+      "=r"(__out[60]),
+      "=r"(__out[61]),
+      "=r"(__out[62]),
+      "=r"(__out[63])
+    : "r"(__taddr)
+    : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_ld_16x64b_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.ld.sync.aligned.16x64b.x64.pack::16b.b32 out, [taddr]; // PTX ISA 86, SM_100a, SM_101a
+template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+__device__ static inline void tcgen05_ld_16x64b_pack_16b(
+  B32 (&out)[64],
+  uint32_t taddr);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_ld_16x64b_pack_16b_is_not_supported_before_SM_100a_SM_101a__();
+template <typename _B32, _CUDA_VSTD::enable_if_t<sizeof(_B32) == 4, bool> = true>
+_CCCL_DEVICE static inline void tcgen05_ld_16x64b_pack_16b(_B32 (&__out)[64], _CUDA_VSTD::uint32_t __taddr)
+{
+  static_assert(sizeof(_B32) == 4, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  asm(
+    "tcgen05.ld.sync.aligned.16x64b.x64.pack::16b.b32 {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, "
+    "%14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, "
+    "%36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, "
+    "%58, %59, %60, %61, %62, %63}, [%64];"
+    : "=r"(__out[0]),
+      "=r"(__out[1]),
+      "=r"(__out[2]),
+      "=r"(__out[3]),
+      "=r"(__out[4]),
+      "=r"(__out[5]),
+      "=r"(__out[6]),
+      "=r"(__out[7]),
+      "=r"(__out[8]),
+      "=r"(__out[9]),
+      "=r"(__out[10]),
+      "=r"(__out[11]),
+      "=r"(__out[12]),
+      "=r"(__out[13]),
+      "=r"(__out[14]),
+      "=r"(__out[15]),
+      "=r"(__out[16]),
+      "=r"(__out[17]),
+      "=r"(__out[18]),
+      "=r"(__out[19]),
+      "=r"(__out[20]),
+      "=r"(__out[21]),
+      "=r"(__out[22]),
+      "=r"(__out[23]),
+      "=r"(__out[24]),
+      "=r"(__out[25]),
+      "=r"(__out[26]),
+      "=r"(__out[27]),
+      "=r"(__out[28]),
+      "=r"(__out[29]),
+      "=r"(__out[30]),
+      "=r"(__out[31]),
+      "=r"(__out[32]),
+      "=r"(__out[33]),
+      "=r"(__out[34]),
+      "=r"(__out[35]),
+      "=r"(__out[36]),
+      "=r"(__out[37]),
+      "=r"(__out[38]),
+      "=r"(__out[39]),
+      "=r"(__out[40]),
+      "=r"(__out[41]),
+      "=r"(__out[42]),
+      "=r"(__out[43]),
+      "=r"(__out[44]),
+      "=r"(__out[45]),
+      "=r"(__out[46]),
+      "=r"(__out[47]),
+      "=r"(__out[48]),
+      "=r"(__out[49]),
+      "=r"(__out[50]),
+      "=r"(__out[51]),
+      "=r"(__out[52]),
+      "=r"(__out[53]),
+      "=r"(__out[54]),
+      "=r"(__out[55]),
+      "=r"(__out[56]),
+      "=r"(__out[57]),
+      "=r"(__out[58]),
+      "=r"(__out[59]),
+      "=r"(__out[60]),
+      "=r"(__out[61]),
+      "=r"(__out[62]),
+      "=r"(__out[63])
+    : "r"(__taddr)
+    : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_ld_16x64b_pack_16b_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.ld.sync.aligned.16x64b.x128.b32 out, [taddr]; // PTX ISA 86, SM_100a, SM_101a
+template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+__device__ static inline void tcgen05_ld_16x64b(
+  B32 (&out)[128],
+  uint32_t taddr);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_ld_16x64b_is_not_supported_before_SM_100a_SM_101a__();
+template <typename _B32, _CUDA_VSTD::enable_if_t<sizeof(_B32) == 4, bool> = true>
+_CCCL_DEVICE static inline void tcgen05_ld_16x64b(_B32 (&__out)[128], _CUDA_VSTD::uint32_t __taddr)
+{
+  static_assert(sizeof(_B32) == 4, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  asm(
+    "tcgen05.ld.sync.aligned.16x64b.x128.b32 {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, "
+    "%16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, "
+    "%38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, "
+    "%60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, "
+    "%82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, "
+    "%104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, "
+    "%123, %124, %125, %126, %127}, [%128];"
+    : "=r"(__out[0]),
+      "=r"(__out[1]),
+      "=r"(__out[2]),
+      "=r"(__out[3]),
+      "=r"(__out[4]),
+      "=r"(__out[5]),
+      "=r"(__out[6]),
+      "=r"(__out[7]),
+      "=r"(__out[8]),
+      "=r"(__out[9]),
+      "=r"(__out[10]),
+      "=r"(__out[11]),
+      "=r"(__out[12]),
+      "=r"(__out[13]),
+      "=r"(__out[14]),
+      "=r"(__out[15]),
+      "=r"(__out[16]),
+      "=r"(__out[17]),
+      "=r"(__out[18]),
+      "=r"(__out[19]),
+      "=r"(__out[20]),
+      "=r"(__out[21]),
+      "=r"(__out[22]),
+      "=r"(__out[23]),
+      "=r"(__out[24]),
+      "=r"(__out[25]),
+      "=r"(__out[26]),
+      "=r"(__out[27]),
+      "=r"(__out[28]),
+      "=r"(__out[29]),
+      "=r"(__out[30]),
+      "=r"(__out[31]),
+      "=r"(__out[32]),
+      "=r"(__out[33]),
+      "=r"(__out[34]),
+      "=r"(__out[35]),
+      "=r"(__out[36]),
+      "=r"(__out[37]),
+      "=r"(__out[38]),
+      "=r"(__out[39]),
+      "=r"(__out[40]),
+      "=r"(__out[41]),
+      "=r"(__out[42]),
+      "=r"(__out[43]),
+      "=r"(__out[44]),
+      "=r"(__out[45]),
+      "=r"(__out[46]),
+      "=r"(__out[47]),
+      "=r"(__out[48]),
+      "=r"(__out[49]),
+      "=r"(__out[50]),
+      "=r"(__out[51]),
+      "=r"(__out[52]),
+      "=r"(__out[53]),
+      "=r"(__out[54]),
+      "=r"(__out[55]),
+      "=r"(__out[56]),
+      "=r"(__out[57]),
+      "=r"(__out[58]),
+      "=r"(__out[59]),
+      "=r"(__out[60]),
+      "=r"(__out[61]),
+      "=r"(__out[62]),
+      "=r"(__out[63]),
+      "=r"(__out[64]),
+      "=r"(__out[65]),
+      "=r"(__out[66]),
+      "=r"(__out[67]),
+      "=r"(__out[68]),
+      "=r"(__out[69]),
+      "=r"(__out[70]),
+      "=r"(__out[71]),
+      "=r"(__out[72]),
+      "=r"(__out[73]),
+      "=r"(__out[74]),
+      "=r"(__out[75]),
+      "=r"(__out[76]),
+      "=r"(__out[77]),
+      "=r"(__out[78]),
+      "=r"(__out[79]),
+      "=r"(__out[80]),
+      "=r"(__out[81]),
+      "=r"(__out[82]),
+      "=r"(__out[83]),
+      "=r"(__out[84]),
+      "=r"(__out[85]),
+      "=r"(__out[86]),
+      "=r"(__out[87]),
+      "=r"(__out[88]),
+      "=r"(__out[89]),
+      "=r"(__out[90]),
+      "=r"(__out[91]),
+      "=r"(__out[92]),
+      "=r"(__out[93]),
+      "=r"(__out[94]),
+      "=r"(__out[95]),
+      "=r"(__out[96]),
+      "=r"(__out[97]),
+      "=r"(__out[98]),
+      "=r"(__out[99]),
+      "=r"(__out[100]),
+      "=r"(__out[101]),
+      "=r"(__out[102]),
+      "=r"(__out[103]),
+      "=r"(__out[104]),
+      "=r"(__out[105]),
+      "=r"(__out[106]),
+      "=r"(__out[107]),
+      "=r"(__out[108]),
+      "=r"(__out[109]),
+      "=r"(__out[110]),
+      "=r"(__out[111]),
+      "=r"(__out[112]),
+      "=r"(__out[113]),
+      "=r"(__out[114]),
+      "=r"(__out[115]),
+      "=r"(__out[116]),
+      "=r"(__out[117]),
+      "=r"(__out[118]),
+      "=r"(__out[119]),
+      "=r"(__out[120]),
+      "=r"(__out[121]),
+      "=r"(__out[122]),
+      "=r"(__out[123]),
+      "=r"(__out[124]),
+      "=r"(__out[125]),
+      "=r"(__out[126]),
+      "=r"(__out[127])
+    : "r"(__taddr)
+    : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_ld_16x64b_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.ld.sync.aligned.16x64b.x128.pack::16b.b32 out, [taddr]; // PTX ISA 86, SM_100a, SM_101a
+template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+__device__ static inline void tcgen05_ld_16x64b_pack_16b(
+  B32 (&out)[128],
+  uint32_t taddr);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_ld_16x64b_pack_16b_is_not_supported_before_SM_100a_SM_101a__();
+template <typename _B32, _CUDA_VSTD::enable_if_t<sizeof(_B32) == 4, bool> = true>
+_CCCL_DEVICE static inline void tcgen05_ld_16x64b_pack_16b(_B32 (&__out)[128], _CUDA_VSTD::uint32_t __taddr)
+{
+  static_assert(sizeof(_B32) == 4, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  asm(
+    "tcgen05.ld.sync.aligned.16x64b.x128.pack::16b.b32 {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, "
+    "%14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, "
+    "%36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, "
+    "%58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, "
+    "%80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, "
+    "%102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, "
+    "%121, %122, %123, %124, %125, %126, %127}, [%128];"
+    : "=r"(__out[0]),
+      "=r"(__out[1]),
+      "=r"(__out[2]),
+      "=r"(__out[3]),
+      "=r"(__out[4]),
+      "=r"(__out[5]),
+      "=r"(__out[6]),
+      "=r"(__out[7]),
+      "=r"(__out[8]),
+      "=r"(__out[9]),
+      "=r"(__out[10]),
+      "=r"(__out[11]),
+      "=r"(__out[12]),
+      "=r"(__out[13]),
+      "=r"(__out[14]),
+      "=r"(__out[15]),
+      "=r"(__out[16]),
+      "=r"(__out[17]),
+      "=r"(__out[18]),
+      "=r"(__out[19]),
+      "=r"(__out[20]),
+      "=r"(__out[21]),
+      "=r"(__out[22]),
+      "=r"(__out[23]),
+      "=r"(__out[24]),
+      "=r"(__out[25]),
+      "=r"(__out[26]),
+      "=r"(__out[27]),
+      "=r"(__out[28]),
+      "=r"(__out[29]),
+      "=r"(__out[30]),
+      "=r"(__out[31]),
+      "=r"(__out[32]),
+      "=r"(__out[33]),
+      "=r"(__out[34]),
+      "=r"(__out[35]),
+      "=r"(__out[36]),
+      "=r"(__out[37]),
+      "=r"(__out[38]),
+      "=r"(__out[39]),
+      "=r"(__out[40]),
+      "=r"(__out[41]),
+      "=r"(__out[42]),
+      "=r"(__out[43]),
+      "=r"(__out[44]),
+      "=r"(__out[45]),
+      "=r"(__out[46]),
+      "=r"(__out[47]),
+      "=r"(__out[48]),
+      "=r"(__out[49]),
+      "=r"(__out[50]),
+      "=r"(__out[51]),
+      "=r"(__out[52]),
+      "=r"(__out[53]),
+      "=r"(__out[54]),
+      "=r"(__out[55]),
+      "=r"(__out[56]),
+      "=r"(__out[57]),
+      "=r"(__out[58]),
+      "=r"(__out[59]),
+      "=r"(__out[60]),
+      "=r"(__out[61]),
+      "=r"(__out[62]),
+      "=r"(__out[63]),
+      "=r"(__out[64]),
+      "=r"(__out[65]),
+      "=r"(__out[66]),
+      "=r"(__out[67]),
+      "=r"(__out[68]),
+      "=r"(__out[69]),
+      "=r"(__out[70]),
+      "=r"(__out[71]),
+      "=r"(__out[72]),
+      "=r"(__out[73]),
+      "=r"(__out[74]),
+      "=r"(__out[75]),
+      "=r"(__out[76]),
+      "=r"(__out[77]),
+      "=r"(__out[78]),
+      "=r"(__out[79]),
+      "=r"(__out[80]),
+      "=r"(__out[81]),
+      "=r"(__out[82]),
+      "=r"(__out[83]),
+      "=r"(__out[84]),
+      "=r"(__out[85]),
+      "=r"(__out[86]),
+      "=r"(__out[87]),
+      "=r"(__out[88]),
+      "=r"(__out[89]),
+      "=r"(__out[90]),
+      "=r"(__out[91]),
+      "=r"(__out[92]),
+      "=r"(__out[93]),
+      "=r"(__out[94]),
+      "=r"(__out[95]),
+      "=r"(__out[96]),
+      "=r"(__out[97]),
+      "=r"(__out[98]),
+      "=r"(__out[99]),
+      "=r"(__out[100]),
+      "=r"(__out[101]),
+      "=r"(__out[102]),
+      "=r"(__out[103]),
+      "=r"(__out[104]),
+      "=r"(__out[105]),
+      "=r"(__out[106]),
+      "=r"(__out[107]),
+      "=r"(__out[108]),
+      "=r"(__out[109]),
+      "=r"(__out[110]),
+      "=r"(__out[111]),
+      "=r"(__out[112]),
+      "=r"(__out[113]),
+      "=r"(__out[114]),
+      "=r"(__out[115]),
+      "=r"(__out[116]),
+      "=r"(__out[117]),
+      "=r"(__out[118]),
+      "=r"(__out[119]),
+      "=r"(__out[120]),
+      "=r"(__out[121]),
+      "=r"(__out[122]),
+      "=r"(__out[123]),
+      "=r"(__out[124]),
+      "=r"(__out[125]),
+      "=r"(__out[126]),
+      "=r"(__out[127])
+    : "r"(__taddr)
+    : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_ld_16x64b_pack_16b_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.ld.sync.aligned.16x128b.x1.b32 out, [taddr]; // PTX ISA 86, SM_100a, SM_101a
+template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+__device__ static inline void tcgen05_ld_16x128b(
+  B32 (&out)[2],
+  uint32_t taddr);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_ld_16x128b_is_not_supported_before_SM_100a_SM_101a__();
+template <typename _B32, _CUDA_VSTD::enable_if_t<sizeof(_B32) == 4, bool> = true>
+_CCCL_DEVICE static inline void tcgen05_ld_16x128b(_B32 (&__out)[2], _CUDA_VSTD::uint32_t __taddr)
+{
+  static_assert(sizeof(_B32) == 4, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  asm("tcgen05.ld.sync.aligned.16x128b.x1.b32 {%0, %1}, [%2];"
+      : "=r"(__out[0]), "=r"(__out[1])
+      : "r"(__taddr)
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_ld_16x128b_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.ld.sync.aligned.16x128b.x1.pack::16b.b32 out, [taddr]; // PTX ISA 86, SM_100a, SM_101a
+template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+__device__ static inline void tcgen05_ld_16x128b_pack_16b(
+  B32 (&out)[2],
+  uint32_t taddr);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_ld_16x128b_pack_16b_is_not_supported_before_SM_100a_SM_101a__();
+template <typename _B32, _CUDA_VSTD::enable_if_t<sizeof(_B32) == 4, bool> = true>
+_CCCL_DEVICE static inline void tcgen05_ld_16x128b_pack_16b(_B32 (&__out)[2], _CUDA_VSTD::uint32_t __taddr)
+{
+  static_assert(sizeof(_B32) == 4, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  asm("tcgen05.ld.sync.aligned.16x128b.x1.pack::16b.b32 {%0, %1}, [%2];"
+      : "=r"(__out[0]), "=r"(__out[1])
+      : "r"(__taddr)
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_ld_16x128b_pack_16b_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.ld.sync.aligned.16x128b.x2.b32 out, [taddr]; // PTX ISA 86, SM_100a, SM_101a
+template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+__device__ static inline void tcgen05_ld_16x128b(
+  B32 (&out)[4],
+  uint32_t taddr);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_ld_16x128b_is_not_supported_before_SM_100a_SM_101a__();
+template <typename _B32, _CUDA_VSTD::enable_if_t<sizeof(_B32) == 4, bool> = true>
+_CCCL_DEVICE static inline void tcgen05_ld_16x128b(_B32 (&__out)[4], _CUDA_VSTD::uint32_t __taddr)
+{
+  static_assert(sizeof(_B32) == 4, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  asm("tcgen05.ld.sync.aligned.16x128b.x2.b32 {%0, %1, %2, %3}, [%4];"
+      : "=r"(__out[0]), "=r"(__out[1]), "=r"(__out[2]), "=r"(__out[3])
+      : "r"(__taddr)
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_ld_16x128b_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.ld.sync.aligned.16x128b.x2.pack::16b.b32 out, [taddr]; // PTX ISA 86, SM_100a, SM_101a
+template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+__device__ static inline void tcgen05_ld_16x128b_pack_16b(
+  B32 (&out)[4],
+  uint32_t taddr);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_ld_16x128b_pack_16b_is_not_supported_before_SM_100a_SM_101a__();
+template <typename _B32, _CUDA_VSTD::enable_if_t<sizeof(_B32) == 4, bool> = true>
+_CCCL_DEVICE static inline void tcgen05_ld_16x128b_pack_16b(_B32 (&__out)[4], _CUDA_VSTD::uint32_t __taddr)
+{
+  static_assert(sizeof(_B32) == 4, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  asm("tcgen05.ld.sync.aligned.16x128b.x2.pack::16b.b32 {%0, %1, %2, %3}, [%4];"
+      : "=r"(__out[0]), "=r"(__out[1]), "=r"(__out[2]), "=r"(__out[3])
+      : "r"(__taddr)
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_ld_16x128b_pack_16b_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.ld.sync.aligned.16x128b.x4.b32 out, [taddr]; // PTX ISA 86, SM_100a, SM_101a
+template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+__device__ static inline void tcgen05_ld_16x128b(
+  B32 (&out)[8],
+  uint32_t taddr);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_ld_16x128b_is_not_supported_before_SM_100a_SM_101a__();
+template <typename _B32, _CUDA_VSTD::enable_if_t<sizeof(_B32) == 4, bool> = true>
+_CCCL_DEVICE static inline void tcgen05_ld_16x128b(_B32 (&__out)[8], _CUDA_VSTD::uint32_t __taddr)
+{
+  static_assert(sizeof(_B32) == 4, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  asm("tcgen05.ld.sync.aligned.16x128b.x4.b32 {%0, %1, %2, %3, %4, %5, %6, %7}, [%8];"
+      : "=r"(__out[0]),
+        "=r"(__out[1]),
+        "=r"(__out[2]),
+        "=r"(__out[3]),
+        "=r"(__out[4]),
+        "=r"(__out[5]),
+        "=r"(__out[6]),
+        "=r"(__out[7])
+      : "r"(__taddr)
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_ld_16x128b_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.ld.sync.aligned.16x128b.x4.pack::16b.b32 out, [taddr]; // PTX ISA 86, SM_100a, SM_101a
+template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+__device__ static inline void tcgen05_ld_16x128b_pack_16b(
+  B32 (&out)[8],
+  uint32_t taddr);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_ld_16x128b_pack_16b_is_not_supported_before_SM_100a_SM_101a__();
+template <typename _B32, _CUDA_VSTD::enable_if_t<sizeof(_B32) == 4, bool> = true>
+_CCCL_DEVICE static inline void tcgen05_ld_16x128b_pack_16b(_B32 (&__out)[8], _CUDA_VSTD::uint32_t __taddr)
+{
+  static_assert(sizeof(_B32) == 4, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  asm("tcgen05.ld.sync.aligned.16x128b.x4.pack::16b.b32 {%0, %1, %2, %3, %4, %5, %6, %7}, [%8];"
+      : "=r"(__out[0]),
+        "=r"(__out[1]),
+        "=r"(__out[2]),
+        "=r"(__out[3]),
+        "=r"(__out[4]),
+        "=r"(__out[5]),
+        "=r"(__out[6]),
+        "=r"(__out[7])
+      : "r"(__taddr)
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_ld_16x128b_pack_16b_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.ld.sync.aligned.16x128b.x8.b32 out, [taddr]; // PTX ISA 86, SM_100a, SM_101a
+template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+__device__ static inline void tcgen05_ld_16x128b(
+  B32 (&out)[16],
+  uint32_t taddr);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_ld_16x128b_is_not_supported_before_SM_100a_SM_101a__();
+template <typename _B32, _CUDA_VSTD::enable_if_t<sizeof(_B32) == 4, bool> = true>
+_CCCL_DEVICE static inline void tcgen05_ld_16x128b(_B32 (&__out)[16], _CUDA_VSTD::uint32_t __taddr)
+{
+  static_assert(sizeof(_B32) == 4, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  asm("tcgen05.ld.sync.aligned.16x128b.x8.b32 {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15}, "
+      "[%16];"
+      : "=r"(__out[0]),
+        "=r"(__out[1]),
+        "=r"(__out[2]),
+        "=r"(__out[3]),
+        "=r"(__out[4]),
+        "=r"(__out[5]),
+        "=r"(__out[6]),
+        "=r"(__out[7]),
+        "=r"(__out[8]),
+        "=r"(__out[9]),
+        "=r"(__out[10]),
+        "=r"(__out[11]),
+        "=r"(__out[12]),
+        "=r"(__out[13]),
+        "=r"(__out[14]),
+        "=r"(__out[15])
+      : "r"(__taddr)
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_ld_16x128b_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.ld.sync.aligned.16x128b.x8.pack::16b.b32 out, [taddr]; // PTX ISA 86, SM_100a, SM_101a
+template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+__device__ static inline void tcgen05_ld_16x128b_pack_16b(
+  B32 (&out)[16],
+  uint32_t taddr);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_ld_16x128b_pack_16b_is_not_supported_before_SM_100a_SM_101a__();
+template <typename _B32, _CUDA_VSTD::enable_if_t<sizeof(_B32) == 4, bool> = true>
+_CCCL_DEVICE static inline void tcgen05_ld_16x128b_pack_16b(_B32 (&__out)[16], _CUDA_VSTD::uint32_t __taddr)
+{
+  static_assert(sizeof(_B32) == 4, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  asm("tcgen05.ld.sync.aligned.16x128b.x8.pack::16b.b32 {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, "
+      "%14, %15}, [%16];"
+      : "=r"(__out[0]),
+        "=r"(__out[1]),
+        "=r"(__out[2]),
+        "=r"(__out[3]),
+        "=r"(__out[4]),
+        "=r"(__out[5]),
+        "=r"(__out[6]),
+        "=r"(__out[7]),
+        "=r"(__out[8]),
+        "=r"(__out[9]),
+        "=r"(__out[10]),
+        "=r"(__out[11]),
+        "=r"(__out[12]),
+        "=r"(__out[13]),
+        "=r"(__out[14]),
+        "=r"(__out[15])
+      : "r"(__taddr)
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_ld_16x128b_pack_16b_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.ld.sync.aligned.16x128b.x16.b32 out, [taddr]; // PTX ISA 86, SM_100a, SM_101a
+template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+__device__ static inline void tcgen05_ld_16x128b(
+  B32 (&out)[32],
+  uint32_t taddr);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_ld_16x128b_is_not_supported_before_SM_100a_SM_101a__();
+template <typename _B32, _CUDA_VSTD::enable_if_t<sizeof(_B32) == 4, bool> = true>
+_CCCL_DEVICE static inline void tcgen05_ld_16x128b(_B32 (&__out)[32], _CUDA_VSTD::uint32_t __taddr)
+{
+  static_assert(sizeof(_B32) == 4, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  asm(
+    "tcgen05.ld.sync.aligned.16x128b.x16.b32 {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, "
+    "%16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31}, [%32];"
+    : "=r"(__out[0]),
+      "=r"(__out[1]),
+      "=r"(__out[2]),
+      "=r"(__out[3]),
+      "=r"(__out[4]),
+      "=r"(__out[5]),
+      "=r"(__out[6]),
+      "=r"(__out[7]),
+      "=r"(__out[8]),
+      "=r"(__out[9]),
+      "=r"(__out[10]),
+      "=r"(__out[11]),
+      "=r"(__out[12]),
+      "=r"(__out[13]),
+      "=r"(__out[14]),
+      "=r"(__out[15]),
+      "=r"(__out[16]),
+      "=r"(__out[17]),
+      "=r"(__out[18]),
+      "=r"(__out[19]),
+      "=r"(__out[20]),
+      "=r"(__out[21]),
+      "=r"(__out[22]),
+      "=r"(__out[23]),
+      "=r"(__out[24]),
+      "=r"(__out[25]),
+      "=r"(__out[26]),
+      "=r"(__out[27]),
+      "=r"(__out[28]),
+      "=r"(__out[29]),
+      "=r"(__out[30]),
+      "=r"(__out[31])
+    : "r"(__taddr)
+    : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_ld_16x128b_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.ld.sync.aligned.16x128b.x16.pack::16b.b32 out, [taddr]; // PTX ISA 86, SM_100a, SM_101a
+template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+__device__ static inline void tcgen05_ld_16x128b_pack_16b(
+  B32 (&out)[32],
+  uint32_t taddr);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_ld_16x128b_pack_16b_is_not_supported_before_SM_100a_SM_101a__();
+template <typename _B32, _CUDA_VSTD::enable_if_t<sizeof(_B32) == 4, bool> = true>
+_CCCL_DEVICE static inline void tcgen05_ld_16x128b_pack_16b(_B32 (&__out)[32], _CUDA_VSTD::uint32_t __taddr)
+{
+  static_assert(sizeof(_B32) == 4, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  asm(
+    "tcgen05.ld.sync.aligned.16x128b.x16.pack::16b.b32 {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, "
+    "%14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31}, [%32];"
+    : "=r"(__out[0]),
+      "=r"(__out[1]),
+      "=r"(__out[2]),
+      "=r"(__out[3]),
+      "=r"(__out[4]),
+      "=r"(__out[5]),
+      "=r"(__out[6]),
+      "=r"(__out[7]),
+      "=r"(__out[8]),
+      "=r"(__out[9]),
+      "=r"(__out[10]),
+      "=r"(__out[11]),
+      "=r"(__out[12]),
+      "=r"(__out[13]),
+      "=r"(__out[14]),
+      "=r"(__out[15]),
+      "=r"(__out[16]),
+      "=r"(__out[17]),
+      "=r"(__out[18]),
+      "=r"(__out[19]),
+      "=r"(__out[20]),
+      "=r"(__out[21]),
+      "=r"(__out[22]),
+      "=r"(__out[23]),
+      "=r"(__out[24]),
+      "=r"(__out[25]),
+      "=r"(__out[26]),
+      "=r"(__out[27]),
+      "=r"(__out[28]),
+      "=r"(__out[29]),
+      "=r"(__out[30]),
+      "=r"(__out[31])
+    : "r"(__taddr)
+    : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_ld_16x128b_pack_16b_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.ld.sync.aligned.16x128b.x32.b32 out, [taddr]; // PTX ISA 86, SM_100a, SM_101a
+template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+__device__ static inline void tcgen05_ld_16x128b(
+  B32 (&out)[64],
+  uint32_t taddr);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_ld_16x128b_is_not_supported_before_SM_100a_SM_101a__();
+template <typename _B32, _CUDA_VSTD::enable_if_t<sizeof(_B32) == 4, bool> = true>
+_CCCL_DEVICE static inline void tcgen05_ld_16x128b(_B32 (&__out)[64], _CUDA_VSTD::uint32_t __taddr)
+{
+  static_assert(sizeof(_B32) == 4, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  asm(
+    "tcgen05.ld.sync.aligned.16x128b.x32.b32 {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, "
+    "%16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, "
+    "%38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, "
+    "%60, %61, %62, %63}, [%64];"
+    : "=r"(__out[0]),
+      "=r"(__out[1]),
+      "=r"(__out[2]),
+      "=r"(__out[3]),
+      "=r"(__out[4]),
+      "=r"(__out[5]),
+      "=r"(__out[6]),
+      "=r"(__out[7]),
+      "=r"(__out[8]),
+      "=r"(__out[9]),
+      "=r"(__out[10]),
+      "=r"(__out[11]),
+      "=r"(__out[12]),
+      "=r"(__out[13]),
+      "=r"(__out[14]),
+      "=r"(__out[15]),
+      "=r"(__out[16]),
+      "=r"(__out[17]),
+      "=r"(__out[18]),
+      "=r"(__out[19]),
+      "=r"(__out[20]),
+      "=r"(__out[21]),
+      "=r"(__out[22]),
+      "=r"(__out[23]),
+      "=r"(__out[24]),
+      "=r"(__out[25]),
+      "=r"(__out[26]),
+      "=r"(__out[27]),
+      "=r"(__out[28]),
+      "=r"(__out[29]),
+      "=r"(__out[30]),
+      "=r"(__out[31]),
+      "=r"(__out[32]),
+      "=r"(__out[33]),
+      "=r"(__out[34]),
+      "=r"(__out[35]),
+      "=r"(__out[36]),
+      "=r"(__out[37]),
+      "=r"(__out[38]),
+      "=r"(__out[39]),
+      "=r"(__out[40]),
+      "=r"(__out[41]),
+      "=r"(__out[42]),
+      "=r"(__out[43]),
+      "=r"(__out[44]),
+      "=r"(__out[45]),
+      "=r"(__out[46]),
+      "=r"(__out[47]),
+      "=r"(__out[48]),
+      "=r"(__out[49]),
+      "=r"(__out[50]),
+      "=r"(__out[51]),
+      "=r"(__out[52]),
+      "=r"(__out[53]),
+      "=r"(__out[54]),
+      "=r"(__out[55]),
+      "=r"(__out[56]),
+      "=r"(__out[57]),
+      "=r"(__out[58]),
+      "=r"(__out[59]),
+      "=r"(__out[60]),
+      "=r"(__out[61]),
+      "=r"(__out[62]),
+      "=r"(__out[63])
+    : "r"(__taddr)
+    : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_ld_16x128b_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.ld.sync.aligned.16x128b.x32.pack::16b.b32 out, [taddr]; // PTX ISA 86, SM_100a, SM_101a
+template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+__device__ static inline void tcgen05_ld_16x128b_pack_16b(
+  B32 (&out)[64],
+  uint32_t taddr);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_ld_16x128b_pack_16b_is_not_supported_before_SM_100a_SM_101a__();
+template <typename _B32, _CUDA_VSTD::enable_if_t<sizeof(_B32) == 4, bool> = true>
+_CCCL_DEVICE static inline void tcgen05_ld_16x128b_pack_16b(_B32 (&__out)[64], _CUDA_VSTD::uint32_t __taddr)
+{
+  static_assert(sizeof(_B32) == 4, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  asm(
+    "tcgen05.ld.sync.aligned.16x128b.x32.pack::16b.b32 {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, "
+    "%14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, "
+    "%36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, "
+    "%58, %59, %60, %61, %62, %63}, [%64];"
+    : "=r"(__out[0]),
+      "=r"(__out[1]),
+      "=r"(__out[2]),
+      "=r"(__out[3]),
+      "=r"(__out[4]),
+      "=r"(__out[5]),
+      "=r"(__out[6]),
+      "=r"(__out[7]),
+      "=r"(__out[8]),
+      "=r"(__out[9]),
+      "=r"(__out[10]),
+      "=r"(__out[11]),
+      "=r"(__out[12]),
+      "=r"(__out[13]),
+      "=r"(__out[14]),
+      "=r"(__out[15]),
+      "=r"(__out[16]),
+      "=r"(__out[17]),
+      "=r"(__out[18]),
+      "=r"(__out[19]),
+      "=r"(__out[20]),
+      "=r"(__out[21]),
+      "=r"(__out[22]),
+      "=r"(__out[23]),
+      "=r"(__out[24]),
+      "=r"(__out[25]),
+      "=r"(__out[26]),
+      "=r"(__out[27]),
+      "=r"(__out[28]),
+      "=r"(__out[29]),
+      "=r"(__out[30]),
+      "=r"(__out[31]),
+      "=r"(__out[32]),
+      "=r"(__out[33]),
+      "=r"(__out[34]),
+      "=r"(__out[35]),
+      "=r"(__out[36]),
+      "=r"(__out[37]),
+      "=r"(__out[38]),
+      "=r"(__out[39]),
+      "=r"(__out[40]),
+      "=r"(__out[41]),
+      "=r"(__out[42]),
+      "=r"(__out[43]),
+      "=r"(__out[44]),
+      "=r"(__out[45]),
+      "=r"(__out[46]),
+      "=r"(__out[47]),
+      "=r"(__out[48]),
+      "=r"(__out[49]),
+      "=r"(__out[50]),
+      "=r"(__out[51]),
+      "=r"(__out[52]),
+      "=r"(__out[53]),
+      "=r"(__out[54]),
+      "=r"(__out[55]),
+      "=r"(__out[56]),
+      "=r"(__out[57]),
+      "=r"(__out[58]),
+      "=r"(__out[59]),
+      "=r"(__out[60]),
+      "=r"(__out[61]),
+      "=r"(__out[62]),
+      "=r"(__out[63])
+    : "r"(__taddr)
+    : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_ld_16x128b_pack_16b_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.ld.sync.aligned.16x128b.x64.b32 out, [taddr]; // PTX ISA 86, SM_100a, SM_101a
+template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+__device__ static inline void tcgen05_ld_16x128b(
+  B32 (&out)[128],
+  uint32_t taddr);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_ld_16x128b_is_not_supported_before_SM_100a_SM_101a__();
+template <typename _B32, _CUDA_VSTD::enable_if_t<sizeof(_B32) == 4, bool> = true>
+_CCCL_DEVICE static inline void tcgen05_ld_16x128b(_B32 (&__out)[128], _CUDA_VSTD::uint32_t __taddr)
+{
+  static_assert(sizeof(_B32) == 4, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  asm(
+    "tcgen05.ld.sync.aligned.16x128b.x64.b32 {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, "
+    "%16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, "
+    "%38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, "
+    "%60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, "
+    "%82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, "
+    "%104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, "
+    "%123, %124, %125, %126, %127}, [%128];"
+    : "=r"(__out[0]),
+      "=r"(__out[1]),
+      "=r"(__out[2]),
+      "=r"(__out[3]),
+      "=r"(__out[4]),
+      "=r"(__out[5]),
+      "=r"(__out[6]),
+      "=r"(__out[7]),
+      "=r"(__out[8]),
+      "=r"(__out[9]),
+      "=r"(__out[10]),
+      "=r"(__out[11]),
+      "=r"(__out[12]),
+      "=r"(__out[13]),
+      "=r"(__out[14]),
+      "=r"(__out[15]),
+      "=r"(__out[16]),
+      "=r"(__out[17]),
+      "=r"(__out[18]),
+      "=r"(__out[19]),
+      "=r"(__out[20]),
+      "=r"(__out[21]),
+      "=r"(__out[22]),
+      "=r"(__out[23]),
+      "=r"(__out[24]),
+      "=r"(__out[25]),
+      "=r"(__out[26]),
+      "=r"(__out[27]),
+      "=r"(__out[28]),
+      "=r"(__out[29]),
+      "=r"(__out[30]),
+      "=r"(__out[31]),
+      "=r"(__out[32]),
+      "=r"(__out[33]),
+      "=r"(__out[34]),
+      "=r"(__out[35]),
+      "=r"(__out[36]),
+      "=r"(__out[37]),
+      "=r"(__out[38]),
+      "=r"(__out[39]),
+      "=r"(__out[40]),
+      "=r"(__out[41]),
+      "=r"(__out[42]),
+      "=r"(__out[43]),
+      "=r"(__out[44]),
+      "=r"(__out[45]),
+      "=r"(__out[46]),
+      "=r"(__out[47]),
+      "=r"(__out[48]),
+      "=r"(__out[49]),
+      "=r"(__out[50]),
+      "=r"(__out[51]),
+      "=r"(__out[52]),
+      "=r"(__out[53]),
+      "=r"(__out[54]),
+      "=r"(__out[55]),
+      "=r"(__out[56]),
+      "=r"(__out[57]),
+      "=r"(__out[58]),
+      "=r"(__out[59]),
+      "=r"(__out[60]),
+      "=r"(__out[61]),
+      "=r"(__out[62]),
+      "=r"(__out[63]),
+      "=r"(__out[64]),
+      "=r"(__out[65]),
+      "=r"(__out[66]),
+      "=r"(__out[67]),
+      "=r"(__out[68]),
+      "=r"(__out[69]),
+      "=r"(__out[70]),
+      "=r"(__out[71]),
+      "=r"(__out[72]),
+      "=r"(__out[73]),
+      "=r"(__out[74]),
+      "=r"(__out[75]),
+      "=r"(__out[76]),
+      "=r"(__out[77]),
+      "=r"(__out[78]),
+      "=r"(__out[79]),
+      "=r"(__out[80]),
+      "=r"(__out[81]),
+      "=r"(__out[82]),
+      "=r"(__out[83]),
+      "=r"(__out[84]),
+      "=r"(__out[85]),
+      "=r"(__out[86]),
+      "=r"(__out[87]),
+      "=r"(__out[88]),
+      "=r"(__out[89]),
+      "=r"(__out[90]),
+      "=r"(__out[91]),
+      "=r"(__out[92]),
+      "=r"(__out[93]),
+      "=r"(__out[94]),
+      "=r"(__out[95]),
+      "=r"(__out[96]),
+      "=r"(__out[97]),
+      "=r"(__out[98]),
+      "=r"(__out[99]),
+      "=r"(__out[100]),
+      "=r"(__out[101]),
+      "=r"(__out[102]),
+      "=r"(__out[103]),
+      "=r"(__out[104]),
+      "=r"(__out[105]),
+      "=r"(__out[106]),
+      "=r"(__out[107]),
+      "=r"(__out[108]),
+      "=r"(__out[109]),
+      "=r"(__out[110]),
+      "=r"(__out[111]),
+      "=r"(__out[112]),
+      "=r"(__out[113]),
+      "=r"(__out[114]),
+      "=r"(__out[115]),
+      "=r"(__out[116]),
+      "=r"(__out[117]),
+      "=r"(__out[118]),
+      "=r"(__out[119]),
+      "=r"(__out[120]),
+      "=r"(__out[121]),
+      "=r"(__out[122]),
+      "=r"(__out[123]),
+      "=r"(__out[124]),
+      "=r"(__out[125]),
+      "=r"(__out[126]),
+      "=r"(__out[127])
+    : "r"(__taddr)
+    : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_ld_16x128b_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.ld.sync.aligned.16x128b.x64.pack::16b.b32 out, [taddr]; // PTX ISA 86, SM_100a, SM_101a
+template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+__device__ static inline void tcgen05_ld_16x128b_pack_16b(
+  B32 (&out)[128],
+  uint32_t taddr);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_ld_16x128b_pack_16b_is_not_supported_before_SM_100a_SM_101a__();
+template <typename _B32, _CUDA_VSTD::enable_if_t<sizeof(_B32) == 4, bool> = true>
+_CCCL_DEVICE static inline void tcgen05_ld_16x128b_pack_16b(_B32 (&__out)[128], _CUDA_VSTD::uint32_t __taddr)
+{
+  static_assert(sizeof(_B32) == 4, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  asm(
+    "tcgen05.ld.sync.aligned.16x128b.x64.pack::16b.b32 {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, "
+    "%14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, "
+    "%36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, "
+    "%58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, "
+    "%80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, "
+    "%102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, "
+    "%121, %122, %123, %124, %125, %126, %127}, [%128];"
+    : "=r"(__out[0]),
+      "=r"(__out[1]),
+      "=r"(__out[2]),
+      "=r"(__out[3]),
+      "=r"(__out[4]),
+      "=r"(__out[5]),
+      "=r"(__out[6]),
+      "=r"(__out[7]),
+      "=r"(__out[8]),
+      "=r"(__out[9]),
+      "=r"(__out[10]),
+      "=r"(__out[11]),
+      "=r"(__out[12]),
+      "=r"(__out[13]),
+      "=r"(__out[14]),
+      "=r"(__out[15]),
+      "=r"(__out[16]),
+      "=r"(__out[17]),
+      "=r"(__out[18]),
+      "=r"(__out[19]),
+      "=r"(__out[20]),
+      "=r"(__out[21]),
+      "=r"(__out[22]),
+      "=r"(__out[23]),
+      "=r"(__out[24]),
+      "=r"(__out[25]),
+      "=r"(__out[26]),
+      "=r"(__out[27]),
+      "=r"(__out[28]),
+      "=r"(__out[29]),
+      "=r"(__out[30]),
+      "=r"(__out[31]),
+      "=r"(__out[32]),
+      "=r"(__out[33]),
+      "=r"(__out[34]),
+      "=r"(__out[35]),
+      "=r"(__out[36]),
+      "=r"(__out[37]),
+      "=r"(__out[38]),
+      "=r"(__out[39]),
+      "=r"(__out[40]),
+      "=r"(__out[41]),
+      "=r"(__out[42]),
+      "=r"(__out[43]),
+      "=r"(__out[44]),
+      "=r"(__out[45]),
+      "=r"(__out[46]),
+      "=r"(__out[47]),
+      "=r"(__out[48]),
+      "=r"(__out[49]),
+      "=r"(__out[50]),
+      "=r"(__out[51]),
+      "=r"(__out[52]),
+      "=r"(__out[53]),
+      "=r"(__out[54]),
+      "=r"(__out[55]),
+      "=r"(__out[56]),
+      "=r"(__out[57]),
+      "=r"(__out[58]),
+      "=r"(__out[59]),
+      "=r"(__out[60]),
+      "=r"(__out[61]),
+      "=r"(__out[62]),
+      "=r"(__out[63]),
+      "=r"(__out[64]),
+      "=r"(__out[65]),
+      "=r"(__out[66]),
+      "=r"(__out[67]),
+      "=r"(__out[68]),
+      "=r"(__out[69]),
+      "=r"(__out[70]),
+      "=r"(__out[71]),
+      "=r"(__out[72]),
+      "=r"(__out[73]),
+      "=r"(__out[74]),
+      "=r"(__out[75]),
+      "=r"(__out[76]),
+      "=r"(__out[77]),
+      "=r"(__out[78]),
+      "=r"(__out[79]),
+      "=r"(__out[80]),
+      "=r"(__out[81]),
+      "=r"(__out[82]),
+      "=r"(__out[83]),
+      "=r"(__out[84]),
+      "=r"(__out[85]),
+      "=r"(__out[86]),
+      "=r"(__out[87]),
+      "=r"(__out[88]),
+      "=r"(__out[89]),
+      "=r"(__out[90]),
+      "=r"(__out[91]),
+      "=r"(__out[92]),
+      "=r"(__out[93]),
+      "=r"(__out[94]),
+      "=r"(__out[95]),
+      "=r"(__out[96]),
+      "=r"(__out[97]),
+      "=r"(__out[98]),
+      "=r"(__out[99]),
+      "=r"(__out[100]),
+      "=r"(__out[101]),
+      "=r"(__out[102]),
+      "=r"(__out[103]),
+      "=r"(__out[104]),
+      "=r"(__out[105]),
+      "=r"(__out[106]),
+      "=r"(__out[107]),
+      "=r"(__out[108]),
+      "=r"(__out[109]),
+      "=r"(__out[110]),
+      "=r"(__out[111]),
+      "=r"(__out[112]),
+      "=r"(__out[113]),
+      "=r"(__out[114]),
+      "=r"(__out[115]),
+      "=r"(__out[116]),
+      "=r"(__out[117]),
+      "=r"(__out[118]),
+      "=r"(__out[119]),
+      "=r"(__out[120]),
+      "=r"(__out[121]),
+      "=r"(__out[122]),
+      "=r"(__out[123]),
+      "=r"(__out[124]),
+      "=r"(__out[125]),
+      "=r"(__out[126]),
+      "=r"(__out[127])
+    : "r"(__taddr)
+    : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_ld_16x128b_pack_16b_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.ld.sync.aligned.16x256b.x1.b32 out, [taddr]; // PTX ISA 86, SM_100a, SM_101a
+template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+__device__ static inline void tcgen05_ld_16x256b(
+  B32 (&out)[4],
+  uint32_t taddr);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_ld_16x256b_is_not_supported_before_SM_100a_SM_101a__();
+template <typename _B32, _CUDA_VSTD::enable_if_t<sizeof(_B32) == 4, bool> = true>
+_CCCL_DEVICE static inline void tcgen05_ld_16x256b(_B32 (&__out)[4], _CUDA_VSTD::uint32_t __taddr)
+{
+  static_assert(sizeof(_B32) == 4, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  asm("tcgen05.ld.sync.aligned.16x256b.x1.b32 {%0, %1, %2, %3}, [%4];"
+      : "=r"(__out[0]), "=r"(__out[1]), "=r"(__out[2]), "=r"(__out[3])
+      : "r"(__taddr)
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_ld_16x256b_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.ld.sync.aligned.16x256b.x1.pack::16b.b32 out, [taddr]; // PTX ISA 86, SM_100a, SM_101a
+template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+__device__ static inline void tcgen05_ld_16x256b_pack_16b(
+  B32 (&out)[4],
+  uint32_t taddr);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_ld_16x256b_pack_16b_is_not_supported_before_SM_100a_SM_101a__();
+template <typename _B32, _CUDA_VSTD::enable_if_t<sizeof(_B32) == 4, bool> = true>
+_CCCL_DEVICE static inline void tcgen05_ld_16x256b_pack_16b(_B32 (&__out)[4], _CUDA_VSTD::uint32_t __taddr)
+{
+  static_assert(sizeof(_B32) == 4, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  asm("tcgen05.ld.sync.aligned.16x256b.x1.pack::16b.b32 {%0, %1, %2, %3}, [%4];"
+      : "=r"(__out[0]), "=r"(__out[1]), "=r"(__out[2]), "=r"(__out[3])
+      : "r"(__taddr)
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_ld_16x256b_pack_16b_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.ld.sync.aligned.16x256b.x2.b32 out, [taddr]; // PTX ISA 86, SM_100a, SM_101a
+template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+__device__ static inline void tcgen05_ld_16x256b(
+  B32 (&out)[8],
+  uint32_t taddr);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_ld_16x256b_is_not_supported_before_SM_100a_SM_101a__();
+template <typename _B32, _CUDA_VSTD::enable_if_t<sizeof(_B32) == 4, bool> = true>
+_CCCL_DEVICE static inline void tcgen05_ld_16x256b(_B32 (&__out)[8], _CUDA_VSTD::uint32_t __taddr)
+{
+  static_assert(sizeof(_B32) == 4, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  asm("tcgen05.ld.sync.aligned.16x256b.x2.b32 {%0, %1, %2, %3, %4, %5, %6, %7}, [%8];"
+      : "=r"(__out[0]),
+        "=r"(__out[1]),
+        "=r"(__out[2]),
+        "=r"(__out[3]),
+        "=r"(__out[4]),
+        "=r"(__out[5]),
+        "=r"(__out[6]),
+        "=r"(__out[7])
+      : "r"(__taddr)
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_ld_16x256b_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.ld.sync.aligned.16x256b.x2.pack::16b.b32 out, [taddr]; // PTX ISA 86, SM_100a, SM_101a
+template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+__device__ static inline void tcgen05_ld_16x256b_pack_16b(
+  B32 (&out)[8],
+  uint32_t taddr);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_ld_16x256b_pack_16b_is_not_supported_before_SM_100a_SM_101a__();
+template <typename _B32, _CUDA_VSTD::enable_if_t<sizeof(_B32) == 4, bool> = true>
+_CCCL_DEVICE static inline void tcgen05_ld_16x256b_pack_16b(_B32 (&__out)[8], _CUDA_VSTD::uint32_t __taddr)
+{
+  static_assert(sizeof(_B32) == 4, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  asm("tcgen05.ld.sync.aligned.16x256b.x2.pack::16b.b32 {%0, %1, %2, %3, %4, %5, %6, %7}, [%8];"
+      : "=r"(__out[0]),
+        "=r"(__out[1]),
+        "=r"(__out[2]),
+        "=r"(__out[3]),
+        "=r"(__out[4]),
+        "=r"(__out[5]),
+        "=r"(__out[6]),
+        "=r"(__out[7])
+      : "r"(__taddr)
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_ld_16x256b_pack_16b_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.ld.sync.aligned.16x256b.x4.b32 out, [taddr]; // PTX ISA 86, SM_100a, SM_101a
+template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+__device__ static inline void tcgen05_ld_16x256b(
+  B32 (&out)[16],
+  uint32_t taddr);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_ld_16x256b_is_not_supported_before_SM_100a_SM_101a__();
+template <typename _B32, _CUDA_VSTD::enable_if_t<sizeof(_B32) == 4, bool> = true>
+_CCCL_DEVICE static inline void tcgen05_ld_16x256b(_B32 (&__out)[16], _CUDA_VSTD::uint32_t __taddr)
+{
+  static_assert(sizeof(_B32) == 4, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  asm("tcgen05.ld.sync.aligned.16x256b.x4.b32 {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15}, "
+      "[%16];"
+      : "=r"(__out[0]),
+        "=r"(__out[1]),
+        "=r"(__out[2]),
+        "=r"(__out[3]),
+        "=r"(__out[4]),
+        "=r"(__out[5]),
+        "=r"(__out[6]),
+        "=r"(__out[7]),
+        "=r"(__out[8]),
+        "=r"(__out[9]),
+        "=r"(__out[10]),
+        "=r"(__out[11]),
+        "=r"(__out[12]),
+        "=r"(__out[13]),
+        "=r"(__out[14]),
+        "=r"(__out[15])
+      : "r"(__taddr)
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_ld_16x256b_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.ld.sync.aligned.16x256b.x4.pack::16b.b32 out, [taddr]; // PTX ISA 86, SM_100a, SM_101a
+template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+__device__ static inline void tcgen05_ld_16x256b_pack_16b(
+  B32 (&out)[16],
+  uint32_t taddr);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_ld_16x256b_pack_16b_is_not_supported_before_SM_100a_SM_101a__();
+template <typename _B32, _CUDA_VSTD::enable_if_t<sizeof(_B32) == 4, bool> = true>
+_CCCL_DEVICE static inline void tcgen05_ld_16x256b_pack_16b(_B32 (&__out)[16], _CUDA_VSTD::uint32_t __taddr)
+{
+  static_assert(sizeof(_B32) == 4, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  asm("tcgen05.ld.sync.aligned.16x256b.x4.pack::16b.b32 {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, "
+      "%14, %15}, [%16];"
+      : "=r"(__out[0]),
+        "=r"(__out[1]),
+        "=r"(__out[2]),
+        "=r"(__out[3]),
+        "=r"(__out[4]),
+        "=r"(__out[5]),
+        "=r"(__out[6]),
+        "=r"(__out[7]),
+        "=r"(__out[8]),
+        "=r"(__out[9]),
+        "=r"(__out[10]),
+        "=r"(__out[11]),
+        "=r"(__out[12]),
+        "=r"(__out[13]),
+        "=r"(__out[14]),
+        "=r"(__out[15])
+      : "r"(__taddr)
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_ld_16x256b_pack_16b_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.ld.sync.aligned.16x256b.x8.b32 out, [taddr]; // PTX ISA 86, SM_100a, SM_101a
+template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+__device__ static inline void tcgen05_ld_16x256b(
+  B32 (&out)[32],
+  uint32_t taddr);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_ld_16x256b_is_not_supported_before_SM_100a_SM_101a__();
+template <typename _B32, _CUDA_VSTD::enable_if_t<sizeof(_B32) == 4, bool> = true>
+_CCCL_DEVICE static inline void tcgen05_ld_16x256b(_B32 (&__out)[32], _CUDA_VSTD::uint32_t __taddr)
+{
+  static_assert(sizeof(_B32) == 4, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  asm(
+    "tcgen05.ld.sync.aligned.16x256b.x8.b32 {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, "
+    "%16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31}, [%32];"
+    : "=r"(__out[0]),
+      "=r"(__out[1]),
+      "=r"(__out[2]),
+      "=r"(__out[3]),
+      "=r"(__out[4]),
+      "=r"(__out[5]),
+      "=r"(__out[6]),
+      "=r"(__out[7]),
+      "=r"(__out[8]),
+      "=r"(__out[9]),
+      "=r"(__out[10]),
+      "=r"(__out[11]),
+      "=r"(__out[12]),
+      "=r"(__out[13]),
+      "=r"(__out[14]),
+      "=r"(__out[15]),
+      "=r"(__out[16]),
+      "=r"(__out[17]),
+      "=r"(__out[18]),
+      "=r"(__out[19]),
+      "=r"(__out[20]),
+      "=r"(__out[21]),
+      "=r"(__out[22]),
+      "=r"(__out[23]),
+      "=r"(__out[24]),
+      "=r"(__out[25]),
+      "=r"(__out[26]),
+      "=r"(__out[27]),
+      "=r"(__out[28]),
+      "=r"(__out[29]),
+      "=r"(__out[30]),
+      "=r"(__out[31])
+    : "r"(__taddr)
+    : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_ld_16x256b_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.ld.sync.aligned.16x256b.x8.pack::16b.b32 out, [taddr]; // PTX ISA 86, SM_100a, SM_101a
+template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+__device__ static inline void tcgen05_ld_16x256b_pack_16b(
+  B32 (&out)[32],
+  uint32_t taddr);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_ld_16x256b_pack_16b_is_not_supported_before_SM_100a_SM_101a__();
+template <typename _B32, _CUDA_VSTD::enable_if_t<sizeof(_B32) == 4, bool> = true>
+_CCCL_DEVICE static inline void tcgen05_ld_16x256b_pack_16b(_B32 (&__out)[32], _CUDA_VSTD::uint32_t __taddr)
+{
+  static_assert(sizeof(_B32) == 4, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  asm(
+    "tcgen05.ld.sync.aligned.16x256b.x8.pack::16b.b32 {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, "
+    "%14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31}, [%32];"
+    : "=r"(__out[0]),
+      "=r"(__out[1]),
+      "=r"(__out[2]),
+      "=r"(__out[3]),
+      "=r"(__out[4]),
+      "=r"(__out[5]),
+      "=r"(__out[6]),
+      "=r"(__out[7]),
+      "=r"(__out[8]),
+      "=r"(__out[9]),
+      "=r"(__out[10]),
+      "=r"(__out[11]),
+      "=r"(__out[12]),
+      "=r"(__out[13]),
+      "=r"(__out[14]),
+      "=r"(__out[15]),
+      "=r"(__out[16]),
+      "=r"(__out[17]),
+      "=r"(__out[18]),
+      "=r"(__out[19]),
+      "=r"(__out[20]),
+      "=r"(__out[21]),
+      "=r"(__out[22]),
+      "=r"(__out[23]),
+      "=r"(__out[24]),
+      "=r"(__out[25]),
+      "=r"(__out[26]),
+      "=r"(__out[27]),
+      "=r"(__out[28]),
+      "=r"(__out[29]),
+      "=r"(__out[30]),
+      "=r"(__out[31])
+    : "r"(__taddr)
+    : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_ld_16x256b_pack_16b_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.ld.sync.aligned.16x256b.x16.b32 out, [taddr]; // PTX ISA 86, SM_100a, SM_101a
+template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+__device__ static inline void tcgen05_ld_16x256b(
+  B32 (&out)[64],
+  uint32_t taddr);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_ld_16x256b_is_not_supported_before_SM_100a_SM_101a__();
+template <typename _B32, _CUDA_VSTD::enable_if_t<sizeof(_B32) == 4, bool> = true>
+_CCCL_DEVICE static inline void tcgen05_ld_16x256b(_B32 (&__out)[64], _CUDA_VSTD::uint32_t __taddr)
+{
+  static_assert(sizeof(_B32) == 4, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  asm(
+    "tcgen05.ld.sync.aligned.16x256b.x16.b32 {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, "
+    "%16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, "
+    "%38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, "
+    "%60, %61, %62, %63}, [%64];"
+    : "=r"(__out[0]),
+      "=r"(__out[1]),
+      "=r"(__out[2]),
+      "=r"(__out[3]),
+      "=r"(__out[4]),
+      "=r"(__out[5]),
+      "=r"(__out[6]),
+      "=r"(__out[7]),
+      "=r"(__out[8]),
+      "=r"(__out[9]),
+      "=r"(__out[10]),
+      "=r"(__out[11]),
+      "=r"(__out[12]),
+      "=r"(__out[13]),
+      "=r"(__out[14]),
+      "=r"(__out[15]),
+      "=r"(__out[16]),
+      "=r"(__out[17]),
+      "=r"(__out[18]),
+      "=r"(__out[19]),
+      "=r"(__out[20]),
+      "=r"(__out[21]),
+      "=r"(__out[22]),
+      "=r"(__out[23]),
+      "=r"(__out[24]),
+      "=r"(__out[25]),
+      "=r"(__out[26]),
+      "=r"(__out[27]),
+      "=r"(__out[28]),
+      "=r"(__out[29]),
+      "=r"(__out[30]),
+      "=r"(__out[31]),
+      "=r"(__out[32]),
+      "=r"(__out[33]),
+      "=r"(__out[34]),
+      "=r"(__out[35]),
+      "=r"(__out[36]),
+      "=r"(__out[37]),
+      "=r"(__out[38]),
+      "=r"(__out[39]),
+      "=r"(__out[40]),
+      "=r"(__out[41]),
+      "=r"(__out[42]),
+      "=r"(__out[43]),
+      "=r"(__out[44]),
+      "=r"(__out[45]),
+      "=r"(__out[46]),
+      "=r"(__out[47]),
+      "=r"(__out[48]),
+      "=r"(__out[49]),
+      "=r"(__out[50]),
+      "=r"(__out[51]),
+      "=r"(__out[52]),
+      "=r"(__out[53]),
+      "=r"(__out[54]),
+      "=r"(__out[55]),
+      "=r"(__out[56]),
+      "=r"(__out[57]),
+      "=r"(__out[58]),
+      "=r"(__out[59]),
+      "=r"(__out[60]),
+      "=r"(__out[61]),
+      "=r"(__out[62]),
+      "=r"(__out[63])
+    : "r"(__taddr)
+    : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_ld_16x256b_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.ld.sync.aligned.16x256b.x16.pack::16b.b32 out, [taddr]; // PTX ISA 86, SM_100a, SM_101a
+template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+__device__ static inline void tcgen05_ld_16x256b_pack_16b(
+  B32 (&out)[64],
+  uint32_t taddr);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_ld_16x256b_pack_16b_is_not_supported_before_SM_100a_SM_101a__();
+template <typename _B32, _CUDA_VSTD::enable_if_t<sizeof(_B32) == 4, bool> = true>
+_CCCL_DEVICE static inline void tcgen05_ld_16x256b_pack_16b(_B32 (&__out)[64], _CUDA_VSTD::uint32_t __taddr)
+{
+  static_assert(sizeof(_B32) == 4, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  asm(
+    "tcgen05.ld.sync.aligned.16x256b.x16.pack::16b.b32 {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, "
+    "%14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, "
+    "%36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, "
+    "%58, %59, %60, %61, %62, %63}, [%64];"
+    : "=r"(__out[0]),
+      "=r"(__out[1]),
+      "=r"(__out[2]),
+      "=r"(__out[3]),
+      "=r"(__out[4]),
+      "=r"(__out[5]),
+      "=r"(__out[6]),
+      "=r"(__out[7]),
+      "=r"(__out[8]),
+      "=r"(__out[9]),
+      "=r"(__out[10]),
+      "=r"(__out[11]),
+      "=r"(__out[12]),
+      "=r"(__out[13]),
+      "=r"(__out[14]),
+      "=r"(__out[15]),
+      "=r"(__out[16]),
+      "=r"(__out[17]),
+      "=r"(__out[18]),
+      "=r"(__out[19]),
+      "=r"(__out[20]),
+      "=r"(__out[21]),
+      "=r"(__out[22]),
+      "=r"(__out[23]),
+      "=r"(__out[24]),
+      "=r"(__out[25]),
+      "=r"(__out[26]),
+      "=r"(__out[27]),
+      "=r"(__out[28]),
+      "=r"(__out[29]),
+      "=r"(__out[30]),
+      "=r"(__out[31]),
+      "=r"(__out[32]),
+      "=r"(__out[33]),
+      "=r"(__out[34]),
+      "=r"(__out[35]),
+      "=r"(__out[36]),
+      "=r"(__out[37]),
+      "=r"(__out[38]),
+      "=r"(__out[39]),
+      "=r"(__out[40]),
+      "=r"(__out[41]),
+      "=r"(__out[42]),
+      "=r"(__out[43]),
+      "=r"(__out[44]),
+      "=r"(__out[45]),
+      "=r"(__out[46]),
+      "=r"(__out[47]),
+      "=r"(__out[48]),
+      "=r"(__out[49]),
+      "=r"(__out[50]),
+      "=r"(__out[51]),
+      "=r"(__out[52]),
+      "=r"(__out[53]),
+      "=r"(__out[54]),
+      "=r"(__out[55]),
+      "=r"(__out[56]),
+      "=r"(__out[57]),
+      "=r"(__out[58]),
+      "=r"(__out[59]),
+      "=r"(__out[60]),
+      "=r"(__out[61]),
+      "=r"(__out[62]),
+      "=r"(__out[63])
+    : "r"(__taddr)
+    : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_ld_16x256b_pack_16b_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.ld.sync.aligned.16x256b.x32.b32 out, [taddr]; // PTX ISA 86, SM_100a, SM_101a
+template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+__device__ static inline void tcgen05_ld_16x256b(
+  B32 (&out)[128],
+  uint32_t taddr);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_ld_16x256b_is_not_supported_before_SM_100a_SM_101a__();
+template <typename _B32, _CUDA_VSTD::enable_if_t<sizeof(_B32) == 4, bool> = true>
+_CCCL_DEVICE static inline void tcgen05_ld_16x256b(_B32 (&__out)[128], _CUDA_VSTD::uint32_t __taddr)
+{
+  static_assert(sizeof(_B32) == 4, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  asm(
+    "tcgen05.ld.sync.aligned.16x256b.x32.b32 {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, "
+    "%16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, "
+    "%38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, "
+    "%60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, "
+    "%82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, "
+    "%104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, "
+    "%123, %124, %125, %126, %127}, [%128];"
+    : "=r"(__out[0]),
+      "=r"(__out[1]),
+      "=r"(__out[2]),
+      "=r"(__out[3]),
+      "=r"(__out[4]),
+      "=r"(__out[5]),
+      "=r"(__out[6]),
+      "=r"(__out[7]),
+      "=r"(__out[8]),
+      "=r"(__out[9]),
+      "=r"(__out[10]),
+      "=r"(__out[11]),
+      "=r"(__out[12]),
+      "=r"(__out[13]),
+      "=r"(__out[14]),
+      "=r"(__out[15]),
+      "=r"(__out[16]),
+      "=r"(__out[17]),
+      "=r"(__out[18]),
+      "=r"(__out[19]),
+      "=r"(__out[20]),
+      "=r"(__out[21]),
+      "=r"(__out[22]),
+      "=r"(__out[23]),
+      "=r"(__out[24]),
+      "=r"(__out[25]),
+      "=r"(__out[26]),
+      "=r"(__out[27]),
+      "=r"(__out[28]),
+      "=r"(__out[29]),
+      "=r"(__out[30]),
+      "=r"(__out[31]),
+      "=r"(__out[32]),
+      "=r"(__out[33]),
+      "=r"(__out[34]),
+      "=r"(__out[35]),
+      "=r"(__out[36]),
+      "=r"(__out[37]),
+      "=r"(__out[38]),
+      "=r"(__out[39]),
+      "=r"(__out[40]),
+      "=r"(__out[41]),
+      "=r"(__out[42]),
+      "=r"(__out[43]),
+      "=r"(__out[44]),
+      "=r"(__out[45]),
+      "=r"(__out[46]),
+      "=r"(__out[47]),
+      "=r"(__out[48]),
+      "=r"(__out[49]),
+      "=r"(__out[50]),
+      "=r"(__out[51]),
+      "=r"(__out[52]),
+      "=r"(__out[53]),
+      "=r"(__out[54]),
+      "=r"(__out[55]),
+      "=r"(__out[56]),
+      "=r"(__out[57]),
+      "=r"(__out[58]),
+      "=r"(__out[59]),
+      "=r"(__out[60]),
+      "=r"(__out[61]),
+      "=r"(__out[62]),
+      "=r"(__out[63]),
+      "=r"(__out[64]),
+      "=r"(__out[65]),
+      "=r"(__out[66]),
+      "=r"(__out[67]),
+      "=r"(__out[68]),
+      "=r"(__out[69]),
+      "=r"(__out[70]),
+      "=r"(__out[71]),
+      "=r"(__out[72]),
+      "=r"(__out[73]),
+      "=r"(__out[74]),
+      "=r"(__out[75]),
+      "=r"(__out[76]),
+      "=r"(__out[77]),
+      "=r"(__out[78]),
+      "=r"(__out[79]),
+      "=r"(__out[80]),
+      "=r"(__out[81]),
+      "=r"(__out[82]),
+      "=r"(__out[83]),
+      "=r"(__out[84]),
+      "=r"(__out[85]),
+      "=r"(__out[86]),
+      "=r"(__out[87]),
+      "=r"(__out[88]),
+      "=r"(__out[89]),
+      "=r"(__out[90]),
+      "=r"(__out[91]),
+      "=r"(__out[92]),
+      "=r"(__out[93]),
+      "=r"(__out[94]),
+      "=r"(__out[95]),
+      "=r"(__out[96]),
+      "=r"(__out[97]),
+      "=r"(__out[98]),
+      "=r"(__out[99]),
+      "=r"(__out[100]),
+      "=r"(__out[101]),
+      "=r"(__out[102]),
+      "=r"(__out[103]),
+      "=r"(__out[104]),
+      "=r"(__out[105]),
+      "=r"(__out[106]),
+      "=r"(__out[107]),
+      "=r"(__out[108]),
+      "=r"(__out[109]),
+      "=r"(__out[110]),
+      "=r"(__out[111]),
+      "=r"(__out[112]),
+      "=r"(__out[113]),
+      "=r"(__out[114]),
+      "=r"(__out[115]),
+      "=r"(__out[116]),
+      "=r"(__out[117]),
+      "=r"(__out[118]),
+      "=r"(__out[119]),
+      "=r"(__out[120]),
+      "=r"(__out[121]),
+      "=r"(__out[122]),
+      "=r"(__out[123]),
+      "=r"(__out[124]),
+      "=r"(__out[125]),
+      "=r"(__out[126]),
+      "=r"(__out[127])
+    : "r"(__taddr)
+    : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_ld_16x256b_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.ld.sync.aligned.16x256b.x32.pack::16b.b32 out, [taddr]; // PTX ISA 86, SM_100a, SM_101a
+template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+__device__ static inline void tcgen05_ld_16x256b_pack_16b(
+  B32 (&out)[128],
+  uint32_t taddr);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_ld_16x256b_pack_16b_is_not_supported_before_SM_100a_SM_101a__();
+template <typename _B32, _CUDA_VSTD::enable_if_t<sizeof(_B32) == 4, bool> = true>
+_CCCL_DEVICE static inline void tcgen05_ld_16x256b_pack_16b(_B32 (&__out)[128], _CUDA_VSTD::uint32_t __taddr)
+{
+  static_assert(sizeof(_B32) == 4, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  asm(
+    "tcgen05.ld.sync.aligned.16x256b.x32.pack::16b.b32 {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, "
+    "%14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, "
+    "%36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, "
+    "%58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, "
+    "%80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, "
+    "%102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, "
+    "%121, %122, %123, %124, %125, %126, %127}, [%128];"
+    : "=r"(__out[0]),
+      "=r"(__out[1]),
+      "=r"(__out[2]),
+      "=r"(__out[3]),
+      "=r"(__out[4]),
+      "=r"(__out[5]),
+      "=r"(__out[6]),
+      "=r"(__out[7]),
+      "=r"(__out[8]),
+      "=r"(__out[9]),
+      "=r"(__out[10]),
+      "=r"(__out[11]),
+      "=r"(__out[12]),
+      "=r"(__out[13]),
+      "=r"(__out[14]),
+      "=r"(__out[15]),
+      "=r"(__out[16]),
+      "=r"(__out[17]),
+      "=r"(__out[18]),
+      "=r"(__out[19]),
+      "=r"(__out[20]),
+      "=r"(__out[21]),
+      "=r"(__out[22]),
+      "=r"(__out[23]),
+      "=r"(__out[24]),
+      "=r"(__out[25]),
+      "=r"(__out[26]),
+      "=r"(__out[27]),
+      "=r"(__out[28]),
+      "=r"(__out[29]),
+      "=r"(__out[30]),
+      "=r"(__out[31]),
+      "=r"(__out[32]),
+      "=r"(__out[33]),
+      "=r"(__out[34]),
+      "=r"(__out[35]),
+      "=r"(__out[36]),
+      "=r"(__out[37]),
+      "=r"(__out[38]),
+      "=r"(__out[39]),
+      "=r"(__out[40]),
+      "=r"(__out[41]),
+      "=r"(__out[42]),
+      "=r"(__out[43]),
+      "=r"(__out[44]),
+      "=r"(__out[45]),
+      "=r"(__out[46]),
+      "=r"(__out[47]),
+      "=r"(__out[48]),
+      "=r"(__out[49]),
+      "=r"(__out[50]),
+      "=r"(__out[51]),
+      "=r"(__out[52]),
+      "=r"(__out[53]),
+      "=r"(__out[54]),
+      "=r"(__out[55]),
+      "=r"(__out[56]),
+      "=r"(__out[57]),
+      "=r"(__out[58]),
+      "=r"(__out[59]),
+      "=r"(__out[60]),
+      "=r"(__out[61]),
+      "=r"(__out[62]),
+      "=r"(__out[63]),
+      "=r"(__out[64]),
+      "=r"(__out[65]),
+      "=r"(__out[66]),
+      "=r"(__out[67]),
+      "=r"(__out[68]),
+      "=r"(__out[69]),
+      "=r"(__out[70]),
+      "=r"(__out[71]),
+      "=r"(__out[72]),
+      "=r"(__out[73]),
+      "=r"(__out[74]),
+      "=r"(__out[75]),
+      "=r"(__out[76]),
+      "=r"(__out[77]),
+      "=r"(__out[78]),
+      "=r"(__out[79]),
+      "=r"(__out[80]),
+      "=r"(__out[81]),
+      "=r"(__out[82]),
+      "=r"(__out[83]),
+      "=r"(__out[84]),
+      "=r"(__out[85]),
+      "=r"(__out[86]),
+      "=r"(__out[87]),
+      "=r"(__out[88]),
+      "=r"(__out[89]),
+      "=r"(__out[90]),
+      "=r"(__out[91]),
+      "=r"(__out[92]),
+      "=r"(__out[93]),
+      "=r"(__out[94]),
+      "=r"(__out[95]),
+      "=r"(__out[96]),
+      "=r"(__out[97]),
+      "=r"(__out[98]),
+      "=r"(__out[99]),
+      "=r"(__out[100]),
+      "=r"(__out[101]),
+      "=r"(__out[102]),
+      "=r"(__out[103]),
+      "=r"(__out[104]),
+      "=r"(__out[105]),
+      "=r"(__out[106]),
+      "=r"(__out[107]),
+      "=r"(__out[108]),
+      "=r"(__out[109]),
+      "=r"(__out[110]),
+      "=r"(__out[111]),
+      "=r"(__out[112]),
+      "=r"(__out[113]),
+      "=r"(__out[114]),
+      "=r"(__out[115]),
+      "=r"(__out[116]),
+      "=r"(__out[117]),
+      "=r"(__out[118]),
+      "=r"(__out[119]),
+      "=r"(__out[120]),
+      "=r"(__out[121]),
+      "=r"(__out[122]),
+      "=r"(__out[123]),
+      "=r"(__out[124]),
+      "=r"(__out[125]),
+      "=r"(__out[126]),
+      "=r"(__out[127])
+    : "r"(__taddr)
+    : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_ld_16x256b_pack_16b_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.ld.sync.aligned.32x32b.x1.b32 out, [taddr]; // PTX ISA 86, SM_100a, SM_101a
+template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+__device__ static inline void tcgen05_ld_32x32b(
+  B32 (&out)[1],
+  uint32_t taddr);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_ld_32x32b_is_not_supported_before_SM_100a_SM_101a__();
+template <typename _B32, _CUDA_VSTD::enable_if_t<sizeof(_B32) == 4, bool> = true>
+_CCCL_DEVICE static inline void tcgen05_ld_32x32b(_B32 (&__out)[1], _CUDA_VSTD::uint32_t __taddr)
+{
+  static_assert(sizeof(_B32) == 4, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  asm("tcgen05.ld.sync.aligned.32x32b.x1.b32 {%0}, [%1];" : "=r"(__out[0]) : "r"(__taddr) : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_ld_32x32b_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.ld.sync.aligned.32x32b.x1.pack::16b.b32 out, [taddr]; // PTX ISA 86, SM_100a, SM_101a
+template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+__device__ static inline void tcgen05_ld_32x32b_pack_16b(
+  B32 (&out)[1],
+  uint32_t taddr);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_ld_32x32b_pack_16b_is_not_supported_before_SM_100a_SM_101a__();
+template <typename _B32, _CUDA_VSTD::enable_if_t<sizeof(_B32) == 4, bool> = true>
+_CCCL_DEVICE static inline void tcgen05_ld_32x32b_pack_16b(_B32 (&__out)[1], _CUDA_VSTD::uint32_t __taddr)
+{
+  static_assert(sizeof(_B32) == 4, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  asm("tcgen05.ld.sync.aligned.32x32b.x1.pack::16b.b32 {%0}, [%1];" : "=r"(__out[0]) : "r"(__taddr) : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_ld_32x32b_pack_16b_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.ld.sync.aligned.32x32b.x2.b32 out, [taddr]; // PTX ISA 86, SM_100a, SM_101a
+template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+__device__ static inline void tcgen05_ld_32x32b(
+  B32 (&out)[2],
+  uint32_t taddr);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_ld_32x32b_is_not_supported_before_SM_100a_SM_101a__();
+template <typename _B32, _CUDA_VSTD::enable_if_t<sizeof(_B32) == 4, bool> = true>
+_CCCL_DEVICE static inline void tcgen05_ld_32x32b(_B32 (&__out)[2], _CUDA_VSTD::uint32_t __taddr)
+{
+  static_assert(sizeof(_B32) == 4, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  asm("tcgen05.ld.sync.aligned.32x32b.x2.b32 {%0, %1}, [%2];"
+      : "=r"(__out[0]), "=r"(__out[1])
+      : "r"(__taddr)
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_ld_32x32b_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.ld.sync.aligned.32x32b.x2.pack::16b.b32 out, [taddr]; // PTX ISA 86, SM_100a, SM_101a
+template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+__device__ static inline void tcgen05_ld_32x32b_pack_16b(
+  B32 (&out)[2],
+  uint32_t taddr);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_ld_32x32b_pack_16b_is_not_supported_before_SM_100a_SM_101a__();
+template <typename _B32, _CUDA_VSTD::enable_if_t<sizeof(_B32) == 4, bool> = true>
+_CCCL_DEVICE static inline void tcgen05_ld_32x32b_pack_16b(_B32 (&__out)[2], _CUDA_VSTD::uint32_t __taddr)
+{
+  static_assert(sizeof(_B32) == 4, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  asm("tcgen05.ld.sync.aligned.32x32b.x2.pack::16b.b32 {%0, %1}, [%2];"
+      : "=r"(__out[0]), "=r"(__out[1])
+      : "r"(__taddr)
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_ld_32x32b_pack_16b_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.ld.sync.aligned.32x32b.x4.b32 out, [taddr]; // PTX ISA 86, SM_100a, SM_101a
+template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+__device__ static inline void tcgen05_ld_32x32b(
+  B32 (&out)[4],
+  uint32_t taddr);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_ld_32x32b_is_not_supported_before_SM_100a_SM_101a__();
+template <typename _B32, _CUDA_VSTD::enable_if_t<sizeof(_B32) == 4, bool> = true>
+_CCCL_DEVICE static inline void tcgen05_ld_32x32b(_B32 (&__out)[4], _CUDA_VSTD::uint32_t __taddr)
+{
+  static_assert(sizeof(_B32) == 4, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  asm("tcgen05.ld.sync.aligned.32x32b.x4.b32 {%0, %1, %2, %3}, [%4];"
+      : "=r"(__out[0]), "=r"(__out[1]), "=r"(__out[2]), "=r"(__out[3])
+      : "r"(__taddr)
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_ld_32x32b_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.ld.sync.aligned.32x32b.x4.pack::16b.b32 out, [taddr]; // PTX ISA 86, SM_100a, SM_101a
+template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+__device__ static inline void tcgen05_ld_32x32b_pack_16b(
+  B32 (&out)[4],
+  uint32_t taddr);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_ld_32x32b_pack_16b_is_not_supported_before_SM_100a_SM_101a__();
+template <typename _B32, _CUDA_VSTD::enable_if_t<sizeof(_B32) == 4, bool> = true>
+_CCCL_DEVICE static inline void tcgen05_ld_32x32b_pack_16b(_B32 (&__out)[4], _CUDA_VSTD::uint32_t __taddr)
+{
+  static_assert(sizeof(_B32) == 4, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  asm("tcgen05.ld.sync.aligned.32x32b.x4.pack::16b.b32 {%0, %1, %2, %3}, [%4];"
+      : "=r"(__out[0]), "=r"(__out[1]), "=r"(__out[2]), "=r"(__out[3])
+      : "r"(__taddr)
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_ld_32x32b_pack_16b_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.ld.sync.aligned.32x32b.x8.b32 out, [taddr]; // PTX ISA 86, SM_100a, SM_101a
+template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+__device__ static inline void tcgen05_ld_32x32b(
+  B32 (&out)[8],
+  uint32_t taddr);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_ld_32x32b_is_not_supported_before_SM_100a_SM_101a__();
+template <typename _B32, _CUDA_VSTD::enable_if_t<sizeof(_B32) == 4, bool> = true>
+_CCCL_DEVICE static inline void tcgen05_ld_32x32b(_B32 (&__out)[8], _CUDA_VSTD::uint32_t __taddr)
+{
+  static_assert(sizeof(_B32) == 4, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  asm("tcgen05.ld.sync.aligned.32x32b.x8.b32 {%0, %1, %2, %3, %4, %5, %6, %7}, [%8];"
+      : "=r"(__out[0]),
+        "=r"(__out[1]),
+        "=r"(__out[2]),
+        "=r"(__out[3]),
+        "=r"(__out[4]),
+        "=r"(__out[5]),
+        "=r"(__out[6]),
+        "=r"(__out[7])
+      : "r"(__taddr)
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_ld_32x32b_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.ld.sync.aligned.32x32b.x8.pack::16b.b32 out, [taddr]; // PTX ISA 86, SM_100a, SM_101a
+template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+__device__ static inline void tcgen05_ld_32x32b_pack_16b(
+  B32 (&out)[8],
+  uint32_t taddr);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_ld_32x32b_pack_16b_is_not_supported_before_SM_100a_SM_101a__();
+template <typename _B32, _CUDA_VSTD::enable_if_t<sizeof(_B32) == 4, bool> = true>
+_CCCL_DEVICE static inline void tcgen05_ld_32x32b_pack_16b(_B32 (&__out)[8], _CUDA_VSTD::uint32_t __taddr)
+{
+  static_assert(sizeof(_B32) == 4, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  asm("tcgen05.ld.sync.aligned.32x32b.x8.pack::16b.b32 {%0, %1, %2, %3, %4, %5, %6, %7}, [%8];"
+      : "=r"(__out[0]),
+        "=r"(__out[1]),
+        "=r"(__out[2]),
+        "=r"(__out[3]),
+        "=r"(__out[4]),
+        "=r"(__out[5]),
+        "=r"(__out[6]),
+        "=r"(__out[7])
+      : "r"(__taddr)
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_ld_32x32b_pack_16b_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.ld.sync.aligned.32x32b.x16.b32 out, [taddr]; // PTX ISA 86, SM_100a, SM_101a
+template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+__device__ static inline void tcgen05_ld_32x32b(
+  B32 (&out)[16],
+  uint32_t taddr);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_ld_32x32b_is_not_supported_before_SM_100a_SM_101a__();
+template <typename _B32, _CUDA_VSTD::enable_if_t<sizeof(_B32) == 4, bool> = true>
+_CCCL_DEVICE static inline void tcgen05_ld_32x32b(_B32 (&__out)[16], _CUDA_VSTD::uint32_t __taddr)
+{
+  static_assert(sizeof(_B32) == 4, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  asm("tcgen05.ld.sync.aligned.32x32b.x16.b32 {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15}, "
+      "[%16];"
+      : "=r"(__out[0]),
+        "=r"(__out[1]),
+        "=r"(__out[2]),
+        "=r"(__out[3]),
+        "=r"(__out[4]),
+        "=r"(__out[5]),
+        "=r"(__out[6]),
+        "=r"(__out[7]),
+        "=r"(__out[8]),
+        "=r"(__out[9]),
+        "=r"(__out[10]),
+        "=r"(__out[11]),
+        "=r"(__out[12]),
+        "=r"(__out[13]),
+        "=r"(__out[14]),
+        "=r"(__out[15])
+      : "r"(__taddr)
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_ld_32x32b_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.ld.sync.aligned.32x32b.x16.pack::16b.b32 out, [taddr]; // PTX ISA 86, SM_100a, SM_101a
+template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+__device__ static inline void tcgen05_ld_32x32b_pack_16b(
+  B32 (&out)[16],
+  uint32_t taddr);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_ld_32x32b_pack_16b_is_not_supported_before_SM_100a_SM_101a__();
+template <typename _B32, _CUDA_VSTD::enable_if_t<sizeof(_B32) == 4, bool> = true>
+_CCCL_DEVICE static inline void tcgen05_ld_32x32b_pack_16b(_B32 (&__out)[16], _CUDA_VSTD::uint32_t __taddr)
+{
+  static_assert(sizeof(_B32) == 4, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  asm("tcgen05.ld.sync.aligned.32x32b.x16.pack::16b.b32 {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, "
+      "%14, %15}, [%16];"
+      : "=r"(__out[0]),
+        "=r"(__out[1]),
+        "=r"(__out[2]),
+        "=r"(__out[3]),
+        "=r"(__out[4]),
+        "=r"(__out[5]),
+        "=r"(__out[6]),
+        "=r"(__out[7]),
+        "=r"(__out[8]),
+        "=r"(__out[9]),
+        "=r"(__out[10]),
+        "=r"(__out[11]),
+        "=r"(__out[12]),
+        "=r"(__out[13]),
+        "=r"(__out[14]),
+        "=r"(__out[15])
+      : "r"(__taddr)
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_ld_32x32b_pack_16b_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.ld.sync.aligned.32x32b.x32.b32 out, [taddr]; // PTX ISA 86, SM_100a, SM_101a
+template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+__device__ static inline void tcgen05_ld_32x32b(
+  B32 (&out)[32],
+  uint32_t taddr);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_ld_32x32b_is_not_supported_before_SM_100a_SM_101a__();
+template <typename _B32, _CUDA_VSTD::enable_if_t<sizeof(_B32) == 4, bool> = true>
+_CCCL_DEVICE static inline void tcgen05_ld_32x32b(_B32 (&__out)[32], _CUDA_VSTD::uint32_t __taddr)
+{
+  static_assert(sizeof(_B32) == 4, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  asm(
+    "tcgen05.ld.sync.aligned.32x32b.x32.b32 {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, "
+    "%16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31}, [%32];"
+    : "=r"(__out[0]),
+      "=r"(__out[1]),
+      "=r"(__out[2]),
+      "=r"(__out[3]),
+      "=r"(__out[4]),
+      "=r"(__out[5]),
+      "=r"(__out[6]),
+      "=r"(__out[7]),
+      "=r"(__out[8]),
+      "=r"(__out[9]),
+      "=r"(__out[10]),
+      "=r"(__out[11]),
+      "=r"(__out[12]),
+      "=r"(__out[13]),
+      "=r"(__out[14]),
+      "=r"(__out[15]),
+      "=r"(__out[16]),
+      "=r"(__out[17]),
+      "=r"(__out[18]),
+      "=r"(__out[19]),
+      "=r"(__out[20]),
+      "=r"(__out[21]),
+      "=r"(__out[22]),
+      "=r"(__out[23]),
+      "=r"(__out[24]),
+      "=r"(__out[25]),
+      "=r"(__out[26]),
+      "=r"(__out[27]),
+      "=r"(__out[28]),
+      "=r"(__out[29]),
+      "=r"(__out[30]),
+      "=r"(__out[31])
+    : "r"(__taddr)
+    : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_ld_32x32b_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.ld.sync.aligned.32x32b.x32.pack::16b.b32 out, [taddr]; // PTX ISA 86, SM_100a, SM_101a
+template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+__device__ static inline void tcgen05_ld_32x32b_pack_16b(
+  B32 (&out)[32],
+  uint32_t taddr);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_ld_32x32b_pack_16b_is_not_supported_before_SM_100a_SM_101a__();
+template <typename _B32, _CUDA_VSTD::enable_if_t<sizeof(_B32) == 4, bool> = true>
+_CCCL_DEVICE static inline void tcgen05_ld_32x32b_pack_16b(_B32 (&__out)[32], _CUDA_VSTD::uint32_t __taddr)
+{
+  static_assert(sizeof(_B32) == 4, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  asm(
+    "tcgen05.ld.sync.aligned.32x32b.x32.pack::16b.b32 {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, "
+    "%14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31}, [%32];"
+    : "=r"(__out[0]),
+      "=r"(__out[1]),
+      "=r"(__out[2]),
+      "=r"(__out[3]),
+      "=r"(__out[4]),
+      "=r"(__out[5]),
+      "=r"(__out[6]),
+      "=r"(__out[7]),
+      "=r"(__out[8]),
+      "=r"(__out[9]),
+      "=r"(__out[10]),
+      "=r"(__out[11]),
+      "=r"(__out[12]),
+      "=r"(__out[13]),
+      "=r"(__out[14]),
+      "=r"(__out[15]),
+      "=r"(__out[16]),
+      "=r"(__out[17]),
+      "=r"(__out[18]),
+      "=r"(__out[19]),
+      "=r"(__out[20]),
+      "=r"(__out[21]),
+      "=r"(__out[22]),
+      "=r"(__out[23]),
+      "=r"(__out[24]),
+      "=r"(__out[25]),
+      "=r"(__out[26]),
+      "=r"(__out[27]),
+      "=r"(__out[28]),
+      "=r"(__out[29]),
+      "=r"(__out[30]),
+      "=r"(__out[31])
+    : "r"(__taddr)
+    : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_ld_32x32b_pack_16b_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.ld.sync.aligned.32x32b.x64.b32 out, [taddr]; // PTX ISA 86, SM_100a, SM_101a
+template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+__device__ static inline void tcgen05_ld_32x32b(
+  B32 (&out)[64],
+  uint32_t taddr);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_ld_32x32b_is_not_supported_before_SM_100a_SM_101a__();
+template <typename _B32, _CUDA_VSTD::enable_if_t<sizeof(_B32) == 4, bool> = true>
+_CCCL_DEVICE static inline void tcgen05_ld_32x32b(_B32 (&__out)[64], _CUDA_VSTD::uint32_t __taddr)
+{
+  static_assert(sizeof(_B32) == 4, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  asm(
+    "tcgen05.ld.sync.aligned.32x32b.x64.b32 {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, "
+    "%16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, "
+    "%38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, "
+    "%60, %61, %62, %63}, [%64];"
+    : "=r"(__out[0]),
+      "=r"(__out[1]),
+      "=r"(__out[2]),
+      "=r"(__out[3]),
+      "=r"(__out[4]),
+      "=r"(__out[5]),
+      "=r"(__out[6]),
+      "=r"(__out[7]),
+      "=r"(__out[8]),
+      "=r"(__out[9]),
+      "=r"(__out[10]),
+      "=r"(__out[11]),
+      "=r"(__out[12]),
+      "=r"(__out[13]),
+      "=r"(__out[14]),
+      "=r"(__out[15]),
+      "=r"(__out[16]),
+      "=r"(__out[17]),
+      "=r"(__out[18]),
+      "=r"(__out[19]),
+      "=r"(__out[20]),
+      "=r"(__out[21]),
+      "=r"(__out[22]),
+      "=r"(__out[23]),
+      "=r"(__out[24]),
+      "=r"(__out[25]),
+      "=r"(__out[26]),
+      "=r"(__out[27]),
+      "=r"(__out[28]),
+      "=r"(__out[29]),
+      "=r"(__out[30]),
+      "=r"(__out[31]),
+      "=r"(__out[32]),
+      "=r"(__out[33]),
+      "=r"(__out[34]),
+      "=r"(__out[35]),
+      "=r"(__out[36]),
+      "=r"(__out[37]),
+      "=r"(__out[38]),
+      "=r"(__out[39]),
+      "=r"(__out[40]),
+      "=r"(__out[41]),
+      "=r"(__out[42]),
+      "=r"(__out[43]),
+      "=r"(__out[44]),
+      "=r"(__out[45]),
+      "=r"(__out[46]),
+      "=r"(__out[47]),
+      "=r"(__out[48]),
+      "=r"(__out[49]),
+      "=r"(__out[50]),
+      "=r"(__out[51]),
+      "=r"(__out[52]),
+      "=r"(__out[53]),
+      "=r"(__out[54]),
+      "=r"(__out[55]),
+      "=r"(__out[56]),
+      "=r"(__out[57]),
+      "=r"(__out[58]),
+      "=r"(__out[59]),
+      "=r"(__out[60]),
+      "=r"(__out[61]),
+      "=r"(__out[62]),
+      "=r"(__out[63])
+    : "r"(__taddr)
+    : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_ld_32x32b_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.ld.sync.aligned.32x32b.x64.pack::16b.b32 out, [taddr]; // PTX ISA 86, SM_100a, SM_101a
+template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+__device__ static inline void tcgen05_ld_32x32b_pack_16b(
+  B32 (&out)[64],
+  uint32_t taddr);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_ld_32x32b_pack_16b_is_not_supported_before_SM_100a_SM_101a__();
+template <typename _B32, _CUDA_VSTD::enable_if_t<sizeof(_B32) == 4, bool> = true>
+_CCCL_DEVICE static inline void tcgen05_ld_32x32b_pack_16b(_B32 (&__out)[64], _CUDA_VSTD::uint32_t __taddr)
+{
+  static_assert(sizeof(_B32) == 4, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  asm(
+    "tcgen05.ld.sync.aligned.32x32b.x64.pack::16b.b32 {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, "
+    "%14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, "
+    "%36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, "
+    "%58, %59, %60, %61, %62, %63}, [%64];"
+    : "=r"(__out[0]),
+      "=r"(__out[1]),
+      "=r"(__out[2]),
+      "=r"(__out[3]),
+      "=r"(__out[4]),
+      "=r"(__out[5]),
+      "=r"(__out[6]),
+      "=r"(__out[7]),
+      "=r"(__out[8]),
+      "=r"(__out[9]),
+      "=r"(__out[10]),
+      "=r"(__out[11]),
+      "=r"(__out[12]),
+      "=r"(__out[13]),
+      "=r"(__out[14]),
+      "=r"(__out[15]),
+      "=r"(__out[16]),
+      "=r"(__out[17]),
+      "=r"(__out[18]),
+      "=r"(__out[19]),
+      "=r"(__out[20]),
+      "=r"(__out[21]),
+      "=r"(__out[22]),
+      "=r"(__out[23]),
+      "=r"(__out[24]),
+      "=r"(__out[25]),
+      "=r"(__out[26]),
+      "=r"(__out[27]),
+      "=r"(__out[28]),
+      "=r"(__out[29]),
+      "=r"(__out[30]),
+      "=r"(__out[31]),
+      "=r"(__out[32]),
+      "=r"(__out[33]),
+      "=r"(__out[34]),
+      "=r"(__out[35]),
+      "=r"(__out[36]),
+      "=r"(__out[37]),
+      "=r"(__out[38]),
+      "=r"(__out[39]),
+      "=r"(__out[40]),
+      "=r"(__out[41]),
+      "=r"(__out[42]),
+      "=r"(__out[43]),
+      "=r"(__out[44]),
+      "=r"(__out[45]),
+      "=r"(__out[46]),
+      "=r"(__out[47]),
+      "=r"(__out[48]),
+      "=r"(__out[49]),
+      "=r"(__out[50]),
+      "=r"(__out[51]),
+      "=r"(__out[52]),
+      "=r"(__out[53]),
+      "=r"(__out[54]),
+      "=r"(__out[55]),
+      "=r"(__out[56]),
+      "=r"(__out[57]),
+      "=r"(__out[58]),
+      "=r"(__out[59]),
+      "=r"(__out[60]),
+      "=r"(__out[61]),
+      "=r"(__out[62]),
+      "=r"(__out[63])
+    : "r"(__taddr)
+    : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_ld_32x32b_pack_16b_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.ld.sync.aligned.32x32b.x128.b32 out, [taddr]; // PTX ISA 86, SM_100a, SM_101a
+template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+__device__ static inline void tcgen05_ld_32x32b(
+  B32 (&out)[128],
+  uint32_t taddr);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_ld_32x32b_is_not_supported_before_SM_100a_SM_101a__();
+template <typename _B32, _CUDA_VSTD::enable_if_t<sizeof(_B32) == 4, bool> = true>
+_CCCL_DEVICE static inline void tcgen05_ld_32x32b(_B32 (&__out)[128], _CUDA_VSTD::uint32_t __taddr)
+{
+  static_assert(sizeof(_B32) == 4, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  asm(
+    "tcgen05.ld.sync.aligned.32x32b.x128.b32 {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, "
+    "%16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, "
+    "%38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, "
+    "%60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, "
+    "%82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, "
+    "%104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, "
+    "%123, %124, %125, %126, %127}, [%128];"
+    : "=r"(__out[0]),
+      "=r"(__out[1]),
+      "=r"(__out[2]),
+      "=r"(__out[3]),
+      "=r"(__out[4]),
+      "=r"(__out[5]),
+      "=r"(__out[6]),
+      "=r"(__out[7]),
+      "=r"(__out[8]),
+      "=r"(__out[9]),
+      "=r"(__out[10]),
+      "=r"(__out[11]),
+      "=r"(__out[12]),
+      "=r"(__out[13]),
+      "=r"(__out[14]),
+      "=r"(__out[15]),
+      "=r"(__out[16]),
+      "=r"(__out[17]),
+      "=r"(__out[18]),
+      "=r"(__out[19]),
+      "=r"(__out[20]),
+      "=r"(__out[21]),
+      "=r"(__out[22]),
+      "=r"(__out[23]),
+      "=r"(__out[24]),
+      "=r"(__out[25]),
+      "=r"(__out[26]),
+      "=r"(__out[27]),
+      "=r"(__out[28]),
+      "=r"(__out[29]),
+      "=r"(__out[30]),
+      "=r"(__out[31]),
+      "=r"(__out[32]),
+      "=r"(__out[33]),
+      "=r"(__out[34]),
+      "=r"(__out[35]),
+      "=r"(__out[36]),
+      "=r"(__out[37]),
+      "=r"(__out[38]),
+      "=r"(__out[39]),
+      "=r"(__out[40]),
+      "=r"(__out[41]),
+      "=r"(__out[42]),
+      "=r"(__out[43]),
+      "=r"(__out[44]),
+      "=r"(__out[45]),
+      "=r"(__out[46]),
+      "=r"(__out[47]),
+      "=r"(__out[48]),
+      "=r"(__out[49]),
+      "=r"(__out[50]),
+      "=r"(__out[51]),
+      "=r"(__out[52]),
+      "=r"(__out[53]),
+      "=r"(__out[54]),
+      "=r"(__out[55]),
+      "=r"(__out[56]),
+      "=r"(__out[57]),
+      "=r"(__out[58]),
+      "=r"(__out[59]),
+      "=r"(__out[60]),
+      "=r"(__out[61]),
+      "=r"(__out[62]),
+      "=r"(__out[63]),
+      "=r"(__out[64]),
+      "=r"(__out[65]),
+      "=r"(__out[66]),
+      "=r"(__out[67]),
+      "=r"(__out[68]),
+      "=r"(__out[69]),
+      "=r"(__out[70]),
+      "=r"(__out[71]),
+      "=r"(__out[72]),
+      "=r"(__out[73]),
+      "=r"(__out[74]),
+      "=r"(__out[75]),
+      "=r"(__out[76]),
+      "=r"(__out[77]),
+      "=r"(__out[78]),
+      "=r"(__out[79]),
+      "=r"(__out[80]),
+      "=r"(__out[81]),
+      "=r"(__out[82]),
+      "=r"(__out[83]),
+      "=r"(__out[84]),
+      "=r"(__out[85]),
+      "=r"(__out[86]),
+      "=r"(__out[87]),
+      "=r"(__out[88]),
+      "=r"(__out[89]),
+      "=r"(__out[90]),
+      "=r"(__out[91]),
+      "=r"(__out[92]),
+      "=r"(__out[93]),
+      "=r"(__out[94]),
+      "=r"(__out[95]),
+      "=r"(__out[96]),
+      "=r"(__out[97]),
+      "=r"(__out[98]),
+      "=r"(__out[99]),
+      "=r"(__out[100]),
+      "=r"(__out[101]),
+      "=r"(__out[102]),
+      "=r"(__out[103]),
+      "=r"(__out[104]),
+      "=r"(__out[105]),
+      "=r"(__out[106]),
+      "=r"(__out[107]),
+      "=r"(__out[108]),
+      "=r"(__out[109]),
+      "=r"(__out[110]),
+      "=r"(__out[111]),
+      "=r"(__out[112]),
+      "=r"(__out[113]),
+      "=r"(__out[114]),
+      "=r"(__out[115]),
+      "=r"(__out[116]),
+      "=r"(__out[117]),
+      "=r"(__out[118]),
+      "=r"(__out[119]),
+      "=r"(__out[120]),
+      "=r"(__out[121]),
+      "=r"(__out[122]),
+      "=r"(__out[123]),
+      "=r"(__out[124]),
+      "=r"(__out[125]),
+      "=r"(__out[126]),
+      "=r"(__out[127])
+    : "r"(__taddr)
+    : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_ld_32x32b_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.ld.sync.aligned.32x32b.x128.pack::16b.b32 out, [taddr]; // PTX ISA 86, SM_100a, SM_101a
+template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+__device__ static inline void tcgen05_ld_32x32b_pack_16b(
+  B32 (&out)[128],
+  uint32_t taddr);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_ld_32x32b_pack_16b_is_not_supported_before_SM_100a_SM_101a__();
+template <typename _B32, _CUDA_VSTD::enable_if_t<sizeof(_B32) == 4, bool> = true>
+_CCCL_DEVICE static inline void tcgen05_ld_32x32b_pack_16b(_B32 (&__out)[128], _CUDA_VSTD::uint32_t __taddr)
+{
+  static_assert(sizeof(_B32) == 4, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  asm(
+    "tcgen05.ld.sync.aligned.32x32b.x128.pack::16b.b32 {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, "
+    "%14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, "
+    "%36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, "
+    "%58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, "
+    "%80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, "
+    "%102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, "
+    "%121, %122, %123, %124, %125, %126, %127}, [%128];"
+    : "=r"(__out[0]),
+      "=r"(__out[1]),
+      "=r"(__out[2]),
+      "=r"(__out[3]),
+      "=r"(__out[4]),
+      "=r"(__out[5]),
+      "=r"(__out[6]),
+      "=r"(__out[7]),
+      "=r"(__out[8]),
+      "=r"(__out[9]),
+      "=r"(__out[10]),
+      "=r"(__out[11]),
+      "=r"(__out[12]),
+      "=r"(__out[13]),
+      "=r"(__out[14]),
+      "=r"(__out[15]),
+      "=r"(__out[16]),
+      "=r"(__out[17]),
+      "=r"(__out[18]),
+      "=r"(__out[19]),
+      "=r"(__out[20]),
+      "=r"(__out[21]),
+      "=r"(__out[22]),
+      "=r"(__out[23]),
+      "=r"(__out[24]),
+      "=r"(__out[25]),
+      "=r"(__out[26]),
+      "=r"(__out[27]),
+      "=r"(__out[28]),
+      "=r"(__out[29]),
+      "=r"(__out[30]),
+      "=r"(__out[31]),
+      "=r"(__out[32]),
+      "=r"(__out[33]),
+      "=r"(__out[34]),
+      "=r"(__out[35]),
+      "=r"(__out[36]),
+      "=r"(__out[37]),
+      "=r"(__out[38]),
+      "=r"(__out[39]),
+      "=r"(__out[40]),
+      "=r"(__out[41]),
+      "=r"(__out[42]),
+      "=r"(__out[43]),
+      "=r"(__out[44]),
+      "=r"(__out[45]),
+      "=r"(__out[46]),
+      "=r"(__out[47]),
+      "=r"(__out[48]),
+      "=r"(__out[49]),
+      "=r"(__out[50]),
+      "=r"(__out[51]),
+      "=r"(__out[52]),
+      "=r"(__out[53]),
+      "=r"(__out[54]),
+      "=r"(__out[55]),
+      "=r"(__out[56]),
+      "=r"(__out[57]),
+      "=r"(__out[58]),
+      "=r"(__out[59]),
+      "=r"(__out[60]),
+      "=r"(__out[61]),
+      "=r"(__out[62]),
+      "=r"(__out[63]),
+      "=r"(__out[64]),
+      "=r"(__out[65]),
+      "=r"(__out[66]),
+      "=r"(__out[67]),
+      "=r"(__out[68]),
+      "=r"(__out[69]),
+      "=r"(__out[70]),
+      "=r"(__out[71]),
+      "=r"(__out[72]),
+      "=r"(__out[73]),
+      "=r"(__out[74]),
+      "=r"(__out[75]),
+      "=r"(__out[76]),
+      "=r"(__out[77]),
+      "=r"(__out[78]),
+      "=r"(__out[79]),
+      "=r"(__out[80]),
+      "=r"(__out[81]),
+      "=r"(__out[82]),
+      "=r"(__out[83]),
+      "=r"(__out[84]),
+      "=r"(__out[85]),
+      "=r"(__out[86]),
+      "=r"(__out[87]),
+      "=r"(__out[88]),
+      "=r"(__out[89]),
+      "=r"(__out[90]),
+      "=r"(__out[91]),
+      "=r"(__out[92]),
+      "=r"(__out[93]),
+      "=r"(__out[94]),
+      "=r"(__out[95]),
+      "=r"(__out[96]),
+      "=r"(__out[97]),
+      "=r"(__out[98]),
+      "=r"(__out[99]),
+      "=r"(__out[100]),
+      "=r"(__out[101]),
+      "=r"(__out[102]),
+      "=r"(__out[103]),
+      "=r"(__out[104]),
+      "=r"(__out[105]),
+      "=r"(__out[106]),
+      "=r"(__out[107]),
+      "=r"(__out[108]),
+      "=r"(__out[109]),
+      "=r"(__out[110]),
+      "=r"(__out[111]),
+      "=r"(__out[112]),
+      "=r"(__out[113]),
+      "=r"(__out[114]),
+      "=r"(__out[115]),
+      "=r"(__out[116]),
+      "=r"(__out[117]),
+      "=r"(__out[118]),
+      "=r"(__out[119]),
+      "=r"(__out[120]),
+      "=r"(__out[121]),
+      "=r"(__out[122]),
+      "=r"(__out[123]),
+      "=r"(__out[124]),
+      "=r"(__out[125]),
+      "=r"(__out[126]),
+      "=r"(__out[127])
+    : "r"(__taddr)
+    : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_ld_32x32b_pack_16b_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.ld.sync.aligned.16x32bx2.x1.b32 out, [taddr], immHalfSplitoff; // PTX ISA 86, SM_100a, SM_101a
+template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true, int N32>
+__device__ static inline void tcgen05_ld_16x32bx2(
+  B32 (&out)[1],
+  uint32_t taddr,
+  cuda::ptx::n32_t<N32> immHalfSplitoff);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_ld_16x32bx2_is_not_supported_before_SM_100a_SM_101a__();
+template <typename _B32, _CUDA_VSTD::enable_if_t<sizeof(_B32) == 4, bool> = true, int _N32>
+_CCCL_DEVICE static inline void
+tcgen05_ld_16x32bx2(_B32 (&__out)[1], _CUDA_VSTD::uint32_t __taddr, n32_t<_N32> __immHalfSplitoff)
+{
+  static_assert(sizeof(_B32) == 4, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  asm("tcgen05.ld.sync.aligned.16x32bx2.x1.b32 {%0}, [%1], %2;"
+      : "=r"(__out[0])
+      : "r"(__taddr), "n"(__immHalfSplitoff.value)
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_ld_16x32bx2_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.ld.sync.aligned.16x32bx2.x1.pack::16b.b32 out, [taddr], immHalfSplitoff; // PTX ISA 86, SM_100a, SM_101a
+template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true, int N32>
+__device__ static inline void tcgen05_ld_16x32bx2_pack_16b(
+  B32 (&out)[1],
+  uint32_t taddr,
+  cuda::ptx::n32_t<N32> immHalfSplitoff);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_ld_16x32bx2_pack_16b_is_not_supported_before_SM_100a_SM_101a__();
+template <typename _B32, _CUDA_VSTD::enable_if_t<sizeof(_B32) == 4, bool> = true, int _N32>
+_CCCL_DEVICE static inline void
+tcgen05_ld_16x32bx2_pack_16b(_B32 (&__out)[1], _CUDA_VSTD::uint32_t __taddr, n32_t<_N32> __immHalfSplitoff)
+{
+  static_assert(sizeof(_B32) == 4, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  asm("tcgen05.ld.sync.aligned.16x32bx2.x1.pack::16b.b32 {%0}, [%1], %2;"
+      : "=r"(__out[0])
+      : "r"(__taddr), "n"(__immHalfSplitoff.value)
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_ld_16x32bx2_pack_16b_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.ld.sync.aligned.16x32bx2.x2.b32 out, [taddr], immHalfSplitoff; // PTX ISA 86, SM_100a, SM_101a
+template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true, int N32>
+__device__ static inline void tcgen05_ld_16x32bx2(
+  B32 (&out)[2],
+  uint32_t taddr,
+  cuda::ptx::n32_t<N32> immHalfSplitoff);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_ld_16x32bx2_is_not_supported_before_SM_100a_SM_101a__();
+template <typename _B32, _CUDA_VSTD::enable_if_t<sizeof(_B32) == 4, bool> = true, int _N32>
+_CCCL_DEVICE static inline void
+tcgen05_ld_16x32bx2(_B32 (&__out)[2], _CUDA_VSTD::uint32_t __taddr, n32_t<_N32> __immHalfSplitoff)
+{
+  static_assert(sizeof(_B32) == 4, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  asm("tcgen05.ld.sync.aligned.16x32bx2.x2.b32 {%0, %1}, [%2], %3;"
+      : "=r"(__out[0]), "=r"(__out[1])
+      : "r"(__taddr), "n"(__immHalfSplitoff.value)
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_ld_16x32bx2_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.ld.sync.aligned.16x32bx2.x2.pack::16b.b32 out, [taddr], immHalfSplitoff; // PTX ISA 86, SM_100a, SM_101a
+template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true, int N32>
+__device__ static inline void tcgen05_ld_16x32bx2_pack_16b(
+  B32 (&out)[2],
+  uint32_t taddr,
+  cuda::ptx::n32_t<N32> immHalfSplitoff);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_ld_16x32bx2_pack_16b_is_not_supported_before_SM_100a_SM_101a__();
+template <typename _B32, _CUDA_VSTD::enable_if_t<sizeof(_B32) == 4, bool> = true, int _N32>
+_CCCL_DEVICE static inline void
+tcgen05_ld_16x32bx2_pack_16b(_B32 (&__out)[2], _CUDA_VSTD::uint32_t __taddr, n32_t<_N32> __immHalfSplitoff)
+{
+  static_assert(sizeof(_B32) == 4, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  asm("tcgen05.ld.sync.aligned.16x32bx2.x2.pack::16b.b32 {%0, %1}, [%2], %3;"
+      : "=r"(__out[0]), "=r"(__out[1])
+      : "r"(__taddr), "n"(__immHalfSplitoff.value)
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_ld_16x32bx2_pack_16b_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.ld.sync.aligned.16x32bx2.x4.b32 out, [taddr], immHalfSplitoff; // PTX ISA 86, SM_100a, SM_101a
+template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true, int N32>
+__device__ static inline void tcgen05_ld_16x32bx2(
+  B32 (&out)[4],
+  uint32_t taddr,
+  cuda::ptx::n32_t<N32> immHalfSplitoff);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_ld_16x32bx2_is_not_supported_before_SM_100a_SM_101a__();
+template <typename _B32, _CUDA_VSTD::enable_if_t<sizeof(_B32) == 4, bool> = true, int _N32>
+_CCCL_DEVICE static inline void
+tcgen05_ld_16x32bx2(_B32 (&__out)[4], _CUDA_VSTD::uint32_t __taddr, n32_t<_N32> __immHalfSplitoff)
+{
+  static_assert(sizeof(_B32) == 4, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  asm("tcgen05.ld.sync.aligned.16x32bx2.x4.b32 {%0, %1, %2, %3}, [%4], %5;"
+      : "=r"(__out[0]), "=r"(__out[1]), "=r"(__out[2]), "=r"(__out[3])
+      : "r"(__taddr), "n"(__immHalfSplitoff.value)
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_ld_16x32bx2_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.ld.sync.aligned.16x32bx2.x4.pack::16b.b32 out, [taddr], immHalfSplitoff; // PTX ISA 86, SM_100a, SM_101a
+template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true, int N32>
+__device__ static inline void tcgen05_ld_16x32bx2_pack_16b(
+  B32 (&out)[4],
+  uint32_t taddr,
+  cuda::ptx::n32_t<N32> immHalfSplitoff);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_ld_16x32bx2_pack_16b_is_not_supported_before_SM_100a_SM_101a__();
+template <typename _B32, _CUDA_VSTD::enable_if_t<sizeof(_B32) == 4, bool> = true, int _N32>
+_CCCL_DEVICE static inline void
+tcgen05_ld_16x32bx2_pack_16b(_B32 (&__out)[4], _CUDA_VSTD::uint32_t __taddr, n32_t<_N32> __immHalfSplitoff)
+{
+  static_assert(sizeof(_B32) == 4, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  asm("tcgen05.ld.sync.aligned.16x32bx2.x4.pack::16b.b32 {%0, %1, %2, %3}, [%4], %5;"
+      : "=r"(__out[0]), "=r"(__out[1]), "=r"(__out[2]), "=r"(__out[3])
+      : "r"(__taddr), "n"(__immHalfSplitoff.value)
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_ld_16x32bx2_pack_16b_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.ld.sync.aligned.16x32bx2.x8.b32 out, [taddr], immHalfSplitoff; // PTX ISA 86, SM_100a, SM_101a
+template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true, int N32>
+__device__ static inline void tcgen05_ld_16x32bx2(
+  B32 (&out)[8],
+  uint32_t taddr,
+  cuda::ptx::n32_t<N32> immHalfSplitoff);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_ld_16x32bx2_is_not_supported_before_SM_100a_SM_101a__();
+template <typename _B32, _CUDA_VSTD::enable_if_t<sizeof(_B32) == 4, bool> = true, int _N32>
+_CCCL_DEVICE static inline void
+tcgen05_ld_16x32bx2(_B32 (&__out)[8], _CUDA_VSTD::uint32_t __taddr, n32_t<_N32> __immHalfSplitoff)
+{
+  static_assert(sizeof(_B32) == 4, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  asm("tcgen05.ld.sync.aligned.16x32bx2.x8.b32 {%0, %1, %2, %3, %4, %5, %6, %7}, [%8], %9;"
+      : "=r"(__out[0]),
+        "=r"(__out[1]),
+        "=r"(__out[2]),
+        "=r"(__out[3]),
+        "=r"(__out[4]),
+        "=r"(__out[5]),
+        "=r"(__out[6]),
+        "=r"(__out[7])
+      : "r"(__taddr), "n"(__immHalfSplitoff.value)
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_ld_16x32bx2_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.ld.sync.aligned.16x32bx2.x8.pack::16b.b32 out, [taddr], immHalfSplitoff; // PTX ISA 86, SM_100a, SM_101a
+template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true, int N32>
+__device__ static inline void tcgen05_ld_16x32bx2_pack_16b(
+  B32 (&out)[8],
+  uint32_t taddr,
+  cuda::ptx::n32_t<N32> immHalfSplitoff);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_ld_16x32bx2_pack_16b_is_not_supported_before_SM_100a_SM_101a__();
+template <typename _B32, _CUDA_VSTD::enable_if_t<sizeof(_B32) == 4, bool> = true, int _N32>
+_CCCL_DEVICE static inline void
+tcgen05_ld_16x32bx2_pack_16b(_B32 (&__out)[8], _CUDA_VSTD::uint32_t __taddr, n32_t<_N32> __immHalfSplitoff)
+{
+  static_assert(sizeof(_B32) == 4, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  asm("tcgen05.ld.sync.aligned.16x32bx2.x8.pack::16b.b32 {%0, %1, %2, %3, %4, %5, %6, %7}, [%8], %9;"
+      : "=r"(__out[0]),
+        "=r"(__out[1]),
+        "=r"(__out[2]),
+        "=r"(__out[3]),
+        "=r"(__out[4]),
+        "=r"(__out[5]),
+        "=r"(__out[6]),
+        "=r"(__out[7])
+      : "r"(__taddr), "n"(__immHalfSplitoff.value)
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_ld_16x32bx2_pack_16b_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.ld.sync.aligned.16x32bx2.x16.b32 out, [taddr], immHalfSplitoff; // PTX ISA 86, SM_100a, SM_101a
+template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true, int N32>
+__device__ static inline void tcgen05_ld_16x32bx2(
+  B32 (&out)[16],
+  uint32_t taddr,
+  cuda::ptx::n32_t<N32> immHalfSplitoff);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_ld_16x32bx2_is_not_supported_before_SM_100a_SM_101a__();
+template <typename _B32, _CUDA_VSTD::enable_if_t<sizeof(_B32) == 4, bool> = true, int _N32>
+_CCCL_DEVICE static inline void
+tcgen05_ld_16x32bx2(_B32 (&__out)[16], _CUDA_VSTD::uint32_t __taddr, n32_t<_N32> __immHalfSplitoff)
+{
+  static_assert(sizeof(_B32) == 4, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  asm("tcgen05.ld.sync.aligned.16x32bx2.x16.b32 {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, "
+      "%15}, [%16], %17;"
+      : "=r"(__out[0]),
+        "=r"(__out[1]),
+        "=r"(__out[2]),
+        "=r"(__out[3]),
+        "=r"(__out[4]),
+        "=r"(__out[5]),
+        "=r"(__out[6]),
+        "=r"(__out[7]),
+        "=r"(__out[8]),
+        "=r"(__out[9]),
+        "=r"(__out[10]),
+        "=r"(__out[11]),
+        "=r"(__out[12]),
+        "=r"(__out[13]),
+        "=r"(__out[14]),
+        "=r"(__out[15])
+      : "r"(__taddr), "n"(__immHalfSplitoff.value)
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_ld_16x32bx2_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.ld.sync.aligned.16x32bx2.x16.pack::16b.b32 out, [taddr], immHalfSplitoff; // PTX ISA 86, SM_100a, SM_101a
+template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true, int N32>
+__device__ static inline void tcgen05_ld_16x32bx2_pack_16b(
+  B32 (&out)[16],
+  uint32_t taddr,
+  cuda::ptx::n32_t<N32> immHalfSplitoff);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_ld_16x32bx2_pack_16b_is_not_supported_before_SM_100a_SM_101a__();
+template <typename _B32, _CUDA_VSTD::enable_if_t<sizeof(_B32) == 4, bool> = true, int _N32>
+_CCCL_DEVICE static inline void
+tcgen05_ld_16x32bx2_pack_16b(_B32 (&__out)[16], _CUDA_VSTD::uint32_t __taddr, n32_t<_N32> __immHalfSplitoff)
+{
+  static_assert(sizeof(_B32) == 4, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  asm("tcgen05.ld.sync.aligned.16x32bx2.x16.pack::16b.b32 {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, "
+      "%14, %15}, [%16], %17;"
+      : "=r"(__out[0]),
+        "=r"(__out[1]),
+        "=r"(__out[2]),
+        "=r"(__out[3]),
+        "=r"(__out[4]),
+        "=r"(__out[5]),
+        "=r"(__out[6]),
+        "=r"(__out[7]),
+        "=r"(__out[8]),
+        "=r"(__out[9]),
+        "=r"(__out[10]),
+        "=r"(__out[11]),
+        "=r"(__out[12]),
+        "=r"(__out[13]),
+        "=r"(__out[14]),
+        "=r"(__out[15])
+      : "r"(__taddr), "n"(__immHalfSplitoff.value)
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_ld_16x32bx2_pack_16b_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.ld.sync.aligned.16x32bx2.x32.b32 out, [taddr], immHalfSplitoff; // PTX ISA 86, SM_100a, SM_101a
+template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true, int N32>
+__device__ static inline void tcgen05_ld_16x32bx2(
+  B32 (&out)[32],
+  uint32_t taddr,
+  cuda::ptx::n32_t<N32> immHalfSplitoff);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_ld_16x32bx2_is_not_supported_before_SM_100a_SM_101a__();
+template <typename _B32, _CUDA_VSTD::enable_if_t<sizeof(_B32) == 4, bool> = true, int _N32>
+_CCCL_DEVICE static inline void
+tcgen05_ld_16x32bx2(_B32 (&__out)[32], _CUDA_VSTD::uint32_t __taddr, n32_t<_N32> __immHalfSplitoff)
+{
+  static_assert(sizeof(_B32) == 4, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  asm(
+    "tcgen05.ld.sync.aligned.16x32bx2.x32.b32 {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, "
+    "%16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31}, [%32], %33;"
+    : "=r"(__out[0]),
+      "=r"(__out[1]),
+      "=r"(__out[2]),
+      "=r"(__out[3]),
+      "=r"(__out[4]),
+      "=r"(__out[5]),
+      "=r"(__out[6]),
+      "=r"(__out[7]),
+      "=r"(__out[8]),
+      "=r"(__out[9]),
+      "=r"(__out[10]),
+      "=r"(__out[11]),
+      "=r"(__out[12]),
+      "=r"(__out[13]),
+      "=r"(__out[14]),
+      "=r"(__out[15]),
+      "=r"(__out[16]),
+      "=r"(__out[17]),
+      "=r"(__out[18]),
+      "=r"(__out[19]),
+      "=r"(__out[20]),
+      "=r"(__out[21]),
+      "=r"(__out[22]),
+      "=r"(__out[23]),
+      "=r"(__out[24]),
+      "=r"(__out[25]),
+      "=r"(__out[26]),
+      "=r"(__out[27]),
+      "=r"(__out[28]),
+      "=r"(__out[29]),
+      "=r"(__out[30]),
+      "=r"(__out[31])
+    : "r"(__taddr), "n"(__immHalfSplitoff.value)
+    : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_ld_16x32bx2_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.ld.sync.aligned.16x32bx2.x32.pack::16b.b32 out, [taddr], immHalfSplitoff; // PTX ISA 86, SM_100a, SM_101a
+template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true, int N32>
+__device__ static inline void tcgen05_ld_16x32bx2_pack_16b(
+  B32 (&out)[32],
+  uint32_t taddr,
+  cuda::ptx::n32_t<N32> immHalfSplitoff);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_ld_16x32bx2_pack_16b_is_not_supported_before_SM_100a_SM_101a__();
+template <typename _B32, _CUDA_VSTD::enable_if_t<sizeof(_B32) == 4, bool> = true, int _N32>
+_CCCL_DEVICE static inline void
+tcgen05_ld_16x32bx2_pack_16b(_B32 (&__out)[32], _CUDA_VSTD::uint32_t __taddr, n32_t<_N32> __immHalfSplitoff)
+{
+  static_assert(sizeof(_B32) == 4, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  asm(
+    "tcgen05.ld.sync.aligned.16x32bx2.x32.pack::16b.b32 {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, "
+    "%14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31}, [%32], %33;"
+    : "=r"(__out[0]),
+      "=r"(__out[1]),
+      "=r"(__out[2]),
+      "=r"(__out[3]),
+      "=r"(__out[4]),
+      "=r"(__out[5]),
+      "=r"(__out[6]),
+      "=r"(__out[7]),
+      "=r"(__out[8]),
+      "=r"(__out[9]),
+      "=r"(__out[10]),
+      "=r"(__out[11]),
+      "=r"(__out[12]),
+      "=r"(__out[13]),
+      "=r"(__out[14]),
+      "=r"(__out[15]),
+      "=r"(__out[16]),
+      "=r"(__out[17]),
+      "=r"(__out[18]),
+      "=r"(__out[19]),
+      "=r"(__out[20]),
+      "=r"(__out[21]),
+      "=r"(__out[22]),
+      "=r"(__out[23]),
+      "=r"(__out[24]),
+      "=r"(__out[25]),
+      "=r"(__out[26]),
+      "=r"(__out[27]),
+      "=r"(__out[28]),
+      "=r"(__out[29]),
+      "=r"(__out[30]),
+      "=r"(__out[31])
+    : "r"(__taddr), "n"(__immHalfSplitoff.value)
+    : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_ld_16x32bx2_pack_16b_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.ld.sync.aligned.16x32bx2.x64.b32 out, [taddr], immHalfSplitoff; // PTX ISA 86, SM_100a, SM_101a
+template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true, int N32>
+__device__ static inline void tcgen05_ld_16x32bx2(
+  B32 (&out)[64],
+  uint32_t taddr,
+  cuda::ptx::n32_t<N32> immHalfSplitoff);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_ld_16x32bx2_is_not_supported_before_SM_100a_SM_101a__();
+template <typename _B32, _CUDA_VSTD::enable_if_t<sizeof(_B32) == 4, bool> = true, int _N32>
+_CCCL_DEVICE static inline void
+tcgen05_ld_16x32bx2(_B32 (&__out)[64], _CUDA_VSTD::uint32_t __taddr, n32_t<_N32> __immHalfSplitoff)
+{
+  static_assert(sizeof(_B32) == 4, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  asm(
+    "tcgen05.ld.sync.aligned.16x32bx2.x64.b32 {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, "
+    "%16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, "
+    "%38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, "
+    "%60, %61, %62, %63}, [%64], %65;"
+    : "=r"(__out[0]),
+      "=r"(__out[1]),
+      "=r"(__out[2]),
+      "=r"(__out[3]),
+      "=r"(__out[4]),
+      "=r"(__out[5]),
+      "=r"(__out[6]),
+      "=r"(__out[7]),
+      "=r"(__out[8]),
+      "=r"(__out[9]),
+      "=r"(__out[10]),
+      "=r"(__out[11]),
+      "=r"(__out[12]),
+      "=r"(__out[13]),
+      "=r"(__out[14]),
+      "=r"(__out[15]),
+      "=r"(__out[16]),
+      "=r"(__out[17]),
+      "=r"(__out[18]),
+      "=r"(__out[19]),
+      "=r"(__out[20]),
+      "=r"(__out[21]),
+      "=r"(__out[22]),
+      "=r"(__out[23]),
+      "=r"(__out[24]),
+      "=r"(__out[25]),
+      "=r"(__out[26]),
+      "=r"(__out[27]),
+      "=r"(__out[28]),
+      "=r"(__out[29]),
+      "=r"(__out[30]),
+      "=r"(__out[31]),
+      "=r"(__out[32]),
+      "=r"(__out[33]),
+      "=r"(__out[34]),
+      "=r"(__out[35]),
+      "=r"(__out[36]),
+      "=r"(__out[37]),
+      "=r"(__out[38]),
+      "=r"(__out[39]),
+      "=r"(__out[40]),
+      "=r"(__out[41]),
+      "=r"(__out[42]),
+      "=r"(__out[43]),
+      "=r"(__out[44]),
+      "=r"(__out[45]),
+      "=r"(__out[46]),
+      "=r"(__out[47]),
+      "=r"(__out[48]),
+      "=r"(__out[49]),
+      "=r"(__out[50]),
+      "=r"(__out[51]),
+      "=r"(__out[52]),
+      "=r"(__out[53]),
+      "=r"(__out[54]),
+      "=r"(__out[55]),
+      "=r"(__out[56]),
+      "=r"(__out[57]),
+      "=r"(__out[58]),
+      "=r"(__out[59]),
+      "=r"(__out[60]),
+      "=r"(__out[61]),
+      "=r"(__out[62]),
+      "=r"(__out[63])
+    : "r"(__taddr), "n"(__immHalfSplitoff.value)
+    : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_ld_16x32bx2_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.ld.sync.aligned.16x32bx2.x64.pack::16b.b32 out, [taddr], immHalfSplitoff; // PTX ISA 86, SM_100a, SM_101a
+template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true, int N32>
+__device__ static inline void tcgen05_ld_16x32bx2_pack_16b(
+  B32 (&out)[64],
+  uint32_t taddr,
+  cuda::ptx::n32_t<N32> immHalfSplitoff);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_ld_16x32bx2_pack_16b_is_not_supported_before_SM_100a_SM_101a__();
+template <typename _B32, _CUDA_VSTD::enable_if_t<sizeof(_B32) == 4, bool> = true, int _N32>
+_CCCL_DEVICE static inline void
+tcgen05_ld_16x32bx2_pack_16b(_B32 (&__out)[64], _CUDA_VSTD::uint32_t __taddr, n32_t<_N32> __immHalfSplitoff)
+{
+  static_assert(sizeof(_B32) == 4, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  asm(
+    "tcgen05.ld.sync.aligned.16x32bx2.x64.pack::16b.b32 {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, "
+    "%14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, "
+    "%36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, "
+    "%58, %59, %60, %61, %62, %63}, [%64], %65;"
+    : "=r"(__out[0]),
+      "=r"(__out[1]),
+      "=r"(__out[2]),
+      "=r"(__out[3]),
+      "=r"(__out[4]),
+      "=r"(__out[5]),
+      "=r"(__out[6]),
+      "=r"(__out[7]),
+      "=r"(__out[8]),
+      "=r"(__out[9]),
+      "=r"(__out[10]),
+      "=r"(__out[11]),
+      "=r"(__out[12]),
+      "=r"(__out[13]),
+      "=r"(__out[14]),
+      "=r"(__out[15]),
+      "=r"(__out[16]),
+      "=r"(__out[17]),
+      "=r"(__out[18]),
+      "=r"(__out[19]),
+      "=r"(__out[20]),
+      "=r"(__out[21]),
+      "=r"(__out[22]),
+      "=r"(__out[23]),
+      "=r"(__out[24]),
+      "=r"(__out[25]),
+      "=r"(__out[26]),
+      "=r"(__out[27]),
+      "=r"(__out[28]),
+      "=r"(__out[29]),
+      "=r"(__out[30]),
+      "=r"(__out[31]),
+      "=r"(__out[32]),
+      "=r"(__out[33]),
+      "=r"(__out[34]),
+      "=r"(__out[35]),
+      "=r"(__out[36]),
+      "=r"(__out[37]),
+      "=r"(__out[38]),
+      "=r"(__out[39]),
+      "=r"(__out[40]),
+      "=r"(__out[41]),
+      "=r"(__out[42]),
+      "=r"(__out[43]),
+      "=r"(__out[44]),
+      "=r"(__out[45]),
+      "=r"(__out[46]),
+      "=r"(__out[47]),
+      "=r"(__out[48]),
+      "=r"(__out[49]),
+      "=r"(__out[50]),
+      "=r"(__out[51]),
+      "=r"(__out[52]),
+      "=r"(__out[53]),
+      "=r"(__out[54]),
+      "=r"(__out[55]),
+      "=r"(__out[56]),
+      "=r"(__out[57]),
+      "=r"(__out[58]),
+      "=r"(__out[59]),
+      "=r"(__out[60]),
+      "=r"(__out[61]),
+      "=r"(__out[62]),
+      "=r"(__out[63])
+    : "r"(__taddr), "n"(__immHalfSplitoff.value)
+    : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_ld_16x32bx2_pack_16b_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.ld.sync.aligned.16x32bx2.x128.b32 out, [taddr], immHalfSplitoff; // PTX ISA 86, SM_100a, SM_101a
+template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true, int N32>
+__device__ static inline void tcgen05_ld_16x32bx2(
+  B32 (&out)[128],
+  uint32_t taddr,
+  cuda::ptx::n32_t<N32> immHalfSplitoff);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_ld_16x32bx2_is_not_supported_before_SM_100a_SM_101a__();
+template <typename _B32, _CUDA_VSTD::enable_if_t<sizeof(_B32) == 4, bool> = true, int _N32>
+_CCCL_DEVICE static inline void
+tcgen05_ld_16x32bx2(_B32 (&__out)[128], _CUDA_VSTD::uint32_t __taddr, n32_t<_N32> __immHalfSplitoff)
+{
+  static_assert(sizeof(_B32) == 4, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  asm(
+    "tcgen05.ld.sync.aligned.16x32bx2.x128.b32 {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, "
+    "%16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, "
+    "%38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, "
+    "%60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, "
+    "%82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, "
+    "%104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, "
+    "%123, %124, %125, %126, %127}, [%128], %129;"
+    : "=r"(__out[0]),
+      "=r"(__out[1]),
+      "=r"(__out[2]),
+      "=r"(__out[3]),
+      "=r"(__out[4]),
+      "=r"(__out[5]),
+      "=r"(__out[6]),
+      "=r"(__out[7]),
+      "=r"(__out[8]),
+      "=r"(__out[9]),
+      "=r"(__out[10]),
+      "=r"(__out[11]),
+      "=r"(__out[12]),
+      "=r"(__out[13]),
+      "=r"(__out[14]),
+      "=r"(__out[15]),
+      "=r"(__out[16]),
+      "=r"(__out[17]),
+      "=r"(__out[18]),
+      "=r"(__out[19]),
+      "=r"(__out[20]),
+      "=r"(__out[21]),
+      "=r"(__out[22]),
+      "=r"(__out[23]),
+      "=r"(__out[24]),
+      "=r"(__out[25]),
+      "=r"(__out[26]),
+      "=r"(__out[27]),
+      "=r"(__out[28]),
+      "=r"(__out[29]),
+      "=r"(__out[30]),
+      "=r"(__out[31]),
+      "=r"(__out[32]),
+      "=r"(__out[33]),
+      "=r"(__out[34]),
+      "=r"(__out[35]),
+      "=r"(__out[36]),
+      "=r"(__out[37]),
+      "=r"(__out[38]),
+      "=r"(__out[39]),
+      "=r"(__out[40]),
+      "=r"(__out[41]),
+      "=r"(__out[42]),
+      "=r"(__out[43]),
+      "=r"(__out[44]),
+      "=r"(__out[45]),
+      "=r"(__out[46]),
+      "=r"(__out[47]),
+      "=r"(__out[48]),
+      "=r"(__out[49]),
+      "=r"(__out[50]),
+      "=r"(__out[51]),
+      "=r"(__out[52]),
+      "=r"(__out[53]),
+      "=r"(__out[54]),
+      "=r"(__out[55]),
+      "=r"(__out[56]),
+      "=r"(__out[57]),
+      "=r"(__out[58]),
+      "=r"(__out[59]),
+      "=r"(__out[60]),
+      "=r"(__out[61]),
+      "=r"(__out[62]),
+      "=r"(__out[63]),
+      "=r"(__out[64]),
+      "=r"(__out[65]),
+      "=r"(__out[66]),
+      "=r"(__out[67]),
+      "=r"(__out[68]),
+      "=r"(__out[69]),
+      "=r"(__out[70]),
+      "=r"(__out[71]),
+      "=r"(__out[72]),
+      "=r"(__out[73]),
+      "=r"(__out[74]),
+      "=r"(__out[75]),
+      "=r"(__out[76]),
+      "=r"(__out[77]),
+      "=r"(__out[78]),
+      "=r"(__out[79]),
+      "=r"(__out[80]),
+      "=r"(__out[81]),
+      "=r"(__out[82]),
+      "=r"(__out[83]),
+      "=r"(__out[84]),
+      "=r"(__out[85]),
+      "=r"(__out[86]),
+      "=r"(__out[87]),
+      "=r"(__out[88]),
+      "=r"(__out[89]),
+      "=r"(__out[90]),
+      "=r"(__out[91]),
+      "=r"(__out[92]),
+      "=r"(__out[93]),
+      "=r"(__out[94]),
+      "=r"(__out[95]),
+      "=r"(__out[96]),
+      "=r"(__out[97]),
+      "=r"(__out[98]),
+      "=r"(__out[99]),
+      "=r"(__out[100]),
+      "=r"(__out[101]),
+      "=r"(__out[102]),
+      "=r"(__out[103]),
+      "=r"(__out[104]),
+      "=r"(__out[105]),
+      "=r"(__out[106]),
+      "=r"(__out[107]),
+      "=r"(__out[108]),
+      "=r"(__out[109]),
+      "=r"(__out[110]),
+      "=r"(__out[111]),
+      "=r"(__out[112]),
+      "=r"(__out[113]),
+      "=r"(__out[114]),
+      "=r"(__out[115]),
+      "=r"(__out[116]),
+      "=r"(__out[117]),
+      "=r"(__out[118]),
+      "=r"(__out[119]),
+      "=r"(__out[120]),
+      "=r"(__out[121]),
+      "=r"(__out[122]),
+      "=r"(__out[123]),
+      "=r"(__out[124]),
+      "=r"(__out[125]),
+      "=r"(__out[126]),
+      "=r"(__out[127])
+    : "r"(__taddr), "n"(__immHalfSplitoff.value)
+    : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_ld_16x32bx2_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.ld.sync.aligned.16x32bx2.x128.pack::16b.b32 out, [taddr], immHalfSplitoff; // PTX ISA 86, SM_100a, SM_101a
+template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true, int N32>
+__device__ static inline void tcgen05_ld_16x32bx2_pack_16b(
+  B32 (&out)[128],
+  uint32_t taddr,
+  cuda::ptx::n32_t<N32> immHalfSplitoff);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_ld_16x32bx2_pack_16b_is_not_supported_before_SM_100a_SM_101a__();
+template <typename _B32, _CUDA_VSTD::enable_if_t<sizeof(_B32) == 4, bool> = true, int _N32>
+_CCCL_DEVICE static inline void
+tcgen05_ld_16x32bx2_pack_16b(_B32 (&__out)[128], _CUDA_VSTD::uint32_t __taddr, n32_t<_N32> __immHalfSplitoff)
+{
+  static_assert(sizeof(_B32) == 4, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  asm(
+    "tcgen05.ld.sync.aligned.16x32bx2.x128.pack::16b.b32 {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, "
+    "%14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, "
+    "%36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, "
+    "%58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, "
+    "%80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, "
+    "%102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, "
+    "%121, %122, %123, %124, %125, %126, %127}, [%128], %129;"
+    : "=r"(__out[0]),
+      "=r"(__out[1]),
+      "=r"(__out[2]),
+      "=r"(__out[3]),
+      "=r"(__out[4]),
+      "=r"(__out[5]),
+      "=r"(__out[6]),
+      "=r"(__out[7]),
+      "=r"(__out[8]),
+      "=r"(__out[9]),
+      "=r"(__out[10]),
+      "=r"(__out[11]),
+      "=r"(__out[12]),
+      "=r"(__out[13]),
+      "=r"(__out[14]),
+      "=r"(__out[15]),
+      "=r"(__out[16]),
+      "=r"(__out[17]),
+      "=r"(__out[18]),
+      "=r"(__out[19]),
+      "=r"(__out[20]),
+      "=r"(__out[21]),
+      "=r"(__out[22]),
+      "=r"(__out[23]),
+      "=r"(__out[24]),
+      "=r"(__out[25]),
+      "=r"(__out[26]),
+      "=r"(__out[27]),
+      "=r"(__out[28]),
+      "=r"(__out[29]),
+      "=r"(__out[30]),
+      "=r"(__out[31]),
+      "=r"(__out[32]),
+      "=r"(__out[33]),
+      "=r"(__out[34]),
+      "=r"(__out[35]),
+      "=r"(__out[36]),
+      "=r"(__out[37]),
+      "=r"(__out[38]),
+      "=r"(__out[39]),
+      "=r"(__out[40]),
+      "=r"(__out[41]),
+      "=r"(__out[42]),
+      "=r"(__out[43]),
+      "=r"(__out[44]),
+      "=r"(__out[45]),
+      "=r"(__out[46]),
+      "=r"(__out[47]),
+      "=r"(__out[48]),
+      "=r"(__out[49]),
+      "=r"(__out[50]),
+      "=r"(__out[51]),
+      "=r"(__out[52]),
+      "=r"(__out[53]),
+      "=r"(__out[54]),
+      "=r"(__out[55]),
+      "=r"(__out[56]),
+      "=r"(__out[57]),
+      "=r"(__out[58]),
+      "=r"(__out[59]),
+      "=r"(__out[60]),
+      "=r"(__out[61]),
+      "=r"(__out[62]),
+      "=r"(__out[63]),
+      "=r"(__out[64]),
+      "=r"(__out[65]),
+      "=r"(__out[66]),
+      "=r"(__out[67]),
+      "=r"(__out[68]),
+      "=r"(__out[69]),
+      "=r"(__out[70]),
+      "=r"(__out[71]),
+      "=r"(__out[72]),
+      "=r"(__out[73]),
+      "=r"(__out[74]),
+      "=r"(__out[75]),
+      "=r"(__out[76]),
+      "=r"(__out[77]),
+      "=r"(__out[78]),
+      "=r"(__out[79]),
+      "=r"(__out[80]),
+      "=r"(__out[81]),
+      "=r"(__out[82]),
+      "=r"(__out[83]),
+      "=r"(__out[84]),
+      "=r"(__out[85]),
+      "=r"(__out[86]),
+      "=r"(__out[87]),
+      "=r"(__out[88]),
+      "=r"(__out[89]),
+      "=r"(__out[90]),
+      "=r"(__out[91]),
+      "=r"(__out[92]),
+      "=r"(__out[93]),
+      "=r"(__out[94]),
+      "=r"(__out[95]),
+      "=r"(__out[96]),
+      "=r"(__out[97]),
+      "=r"(__out[98]),
+      "=r"(__out[99]),
+      "=r"(__out[100]),
+      "=r"(__out[101]),
+      "=r"(__out[102]),
+      "=r"(__out[103]),
+      "=r"(__out[104]),
+      "=r"(__out[105]),
+      "=r"(__out[106]),
+      "=r"(__out[107]),
+      "=r"(__out[108]),
+      "=r"(__out[109]),
+      "=r"(__out[110]),
+      "=r"(__out[111]),
+      "=r"(__out[112]),
+      "=r"(__out[113]),
+      "=r"(__out[114]),
+      "=r"(__out[115]),
+      "=r"(__out[116]),
+      "=r"(__out[117]),
+      "=r"(__out[118]),
+      "=r"(__out[119]),
+      "=r"(__out[120]),
+      "=r"(__out[121]),
+      "=r"(__out[122]),
+      "=r"(__out[123]),
+      "=r"(__out[124]),
+      "=r"(__out[125]),
+      "=r"(__out[126]),
+      "=r"(__out[127])
+    : "r"(__taddr), "n"(__immHalfSplitoff.value)
+    : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_ld_16x32bx2_pack_16b_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+#endif // _CUDA_PTX_GENERATED_TCGEN05_LD_H_
diff --git a/libcudacxx/include/cuda/__ptx/instructions/generated/tcgen05_mma.h b/libcudacxx/include/cuda/__ptx/instructions/generated/tcgen05_mma.h
new file mode 100644
index 00000000000..58e3f1e8363
--- /dev/null
+++ b/libcudacxx/include/cuda/__ptx/instructions/generated/tcgen05_mma.h
@@ -0,0 +1,3842 @@
+// This file was automatically generated. Do not edit.
+
+#ifndef _CUDA_PTX_GENERATED_TCGEN05_MMA_H_
+#define _CUDA_PTX_GENERATED_TCGEN05_MMA_H_
+
+/*
+// tcgen05.mma.cta_group.kind [d_tmem], a_desc, b_desc, idesc, disable_output_lane, enable_input_d, scale_input_d; //
+PTX ISA 86, SM_100a
+// .kind      = { .kind::f16, .kind::tf32 }
+// .cta_group = { .cta_group::1, .cta_group::2 }
+template <int N32, cuda::ptx::dot_kind Kind, cuda::ptx::dot_cta_group Cta_Group>
+__device__ static inline void tcgen05_mma(
+  cuda::ptx::kind_t<Kind> kind,
+  cuda::ptx::cta_group_t<Cta_Group> cta_group,
+  uint32_t d_tmem,
+  uint64_t a_desc,
+  uint64_t b_desc,
+  uint32_t idesc,
+  const uint32_t (&disable_output_lane)[4],
+  bool enable_input_d,
+  cuda::ptx::n32_t<N32> scale_input_d);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_mma_is_not_supported_before_SM_100a__();
+template <int _N32, dot_kind _Kind, dot_cta_group _Cta_Group>
+_CCCL_DEVICE static inline void tcgen05_mma(
+  kind_t<_Kind> __kind,
+  cta_group_t<_Cta_Group> __cta_group,
+  _CUDA_VSTD::uint32_t __d_tmem,
+  _CUDA_VSTD::uint64_t __a_desc,
+  _CUDA_VSTD::uint64_t __b_desc,
+  _CUDA_VSTD::uint32_t __idesc,
+  const _CUDA_VSTD::uint32_t (&__disable_output_lane)[4],
+  bool __enable_input_d,
+  n32_t<_N32> __scale_input_d)
+{
+  static_assert(__kind == kind_f16 || __kind == kind_tf32, "");
+  static_assert(__cta_group == cta_group_1 || __cta_group == cta_group_2, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL
+  _CCCL_IF_CONSTEXPR (__kind == kind_f16 && __cta_group == cta_group_1)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %8, 0;\n\t"
+      "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, {%4, %5, %6, %7}, PRED_enable_input_d, %9;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(__disable_output_lane[0]),
+        "r"(__disable_output_lane[1]),
+        "r"(__disable_output_lane[2]),
+        "r"(__disable_output_lane[3]),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d)),
+        "n"(__scale_input_d.value)
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_f16 && __cta_group == cta_group_2)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %8, 0;\n\t"
+      "tcgen05.mma.cta_group::2.kind::f16 [%0], %1, %2, %3, {%4, %5, %6, %7}, PRED_enable_input_d, %9;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(__disable_output_lane[0]),
+        "r"(__disable_output_lane[1]),
+        "r"(__disable_output_lane[2]),
+        "r"(__disable_output_lane[3]),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d)),
+        "n"(__scale_input_d.value)
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_tf32 && __cta_group == cta_group_1)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %8, 0;\n\t"
+      "tcgen05.mma.cta_group::1.kind::tf32 [%0], %1, %2, %3, {%4, %5, %6, %7}, PRED_enable_input_d, %9;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(__disable_output_lane[0]),
+        "r"(__disable_output_lane[1]),
+        "r"(__disable_output_lane[2]),
+        "r"(__disable_output_lane[3]),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d)),
+        "n"(__scale_input_d.value)
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_tf32 && __cta_group == cta_group_2)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %8, 0;\n\t"
+      "tcgen05.mma.cta_group::2.kind::tf32 [%0], %1, %2, %3, {%4, %5, %6, %7}, PRED_enable_input_d, %9;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(__disable_output_lane[0]),
+        "r"(__disable_output_lane[1]),
+        "r"(__disable_output_lane[2]),
+        "r"(__disable_output_lane[3]),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d)),
+        "n"(__scale_input_d.value)
+      : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_mma_is_not_supported_before_SM_100a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.mma.cta_group.kind [d_tmem], a_desc, b_desc, idesc, disable_output_lane, enable_input_d; // PTX ISA 86,
+SM_100a, SM_101a
+// .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+// .cta_group = { .cta_group::1, .cta_group::2 }
+template <cuda::ptx::dot_kind Kind, cuda::ptx::dot_cta_group Cta_Group>
+__device__ static inline void tcgen05_mma(
+  cuda::ptx::kind_t<Kind> kind,
+  cuda::ptx::cta_group_t<Cta_Group> cta_group,
+  uint32_t d_tmem,
+  uint64_t a_desc,
+  uint64_t b_desc,
+  uint32_t idesc,
+  const uint32_t (&disable_output_lane)[4],
+  bool enable_input_d);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_mma_is_not_supported_before_SM_100a_SM_101a__();
+template <dot_kind _Kind, dot_cta_group _Cta_Group>
+_CCCL_DEVICE static inline void tcgen05_mma(
+  kind_t<_Kind> __kind,
+  cta_group_t<_Cta_Group> __cta_group,
+  _CUDA_VSTD::uint32_t __d_tmem,
+  _CUDA_VSTD::uint64_t __a_desc,
+  _CUDA_VSTD::uint64_t __b_desc,
+  _CUDA_VSTD::uint32_t __idesc,
+  const _CUDA_VSTD::uint32_t (&__disable_output_lane)[4],
+  bool __enable_input_d)
+{
+  static_assert(__kind == kind_f16 || __kind == kind_tf32 || __kind == kind_f8f6f4 || __kind == kind_i8, "");
+  static_assert(__cta_group == cta_group_1 || __cta_group == cta_group_2, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  _CCCL_IF_CONSTEXPR (__kind == kind_f16 && __cta_group == cta_group_1)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %8, 0;\n\t"
+      "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, {%4, %5, %6, %7}, PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(__disable_output_lane[0]),
+        "r"(__disable_output_lane[1]),
+        "r"(__disable_output_lane[2]),
+        "r"(__disable_output_lane[3]),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_f16 && __cta_group == cta_group_2)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %8, 0;\n\t"
+      "tcgen05.mma.cta_group::2.kind::f16 [%0], %1, %2, %3, {%4, %5, %6, %7}, PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(__disable_output_lane[0]),
+        "r"(__disable_output_lane[1]),
+        "r"(__disable_output_lane[2]),
+        "r"(__disable_output_lane[3]),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_tf32 && __cta_group == cta_group_1)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %8, 0;\n\t"
+      "tcgen05.mma.cta_group::1.kind::tf32 [%0], %1, %2, %3, {%4, %5, %6, %7}, PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(__disable_output_lane[0]),
+        "r"(__disable_output_lane[1]),
+        "r"(__disable_output_lane[2]),
+        "r"(__disable_output_lane[3]),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_tf32 && __cta_group == cta_group_2)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %8, 0;\n\t"
+      "tcgen05.mma.cta_group::2.kind::tf32 [%0], %1, %2, %3, {%4, %5, %6, %7}, PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(__disable_output_lane[0]),
+        "r"(__disable_output_lane[1]),
+        "r"(__disable_output_lane[2]),
+        "r"(__disable_output_lane[3]),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_f8f6f4 && __cta_group == cta_group_1)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %8, 0;\n\t"
+      "tcgen05.mma.cta_group::1.kind::f8f6f4 [%0], %1, %2, %3, {%4, %5, %6, %7}, PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(__disable_output_lane[0]),
+        "r"(__disable_output_lane[1]),
+        "r"(__disable_output_lane[2]),
+        "r"(__disable_output_lane[3]),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_f8f6f4 && __cta_group == cta_group_2)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %8, 0;\n\t"
+      "tcgen05.mma.cta_group::2.kind::f8f6f4 [%0], %1, %2, %3, {%4, %5, %6, %7}, PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(__disable_output_lane[0]),
+        "r"(__disable_output_lane[1]),
+        "r"(__disable_output_lane[2]),
+        "r"(__disable_output_lane[3]),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_i8 && __cta_group == cta_group_1)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %8, 0;\n\t"
+      "tcgen05.mma.cta_group::1.kind::i8 [%0], %1, %2, %3, {%4, %5, %6, %7}, PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(__disable_output_lane[0]),
+        "r"(__disable_output_lane[1]),
+        "r"(__disable_output_lane[2]),
+        "r"(__disable_output_lane[3]),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_i8 && __cta_group == cta_group_2)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %8, 0;\n\t"
+      "tcgen05.mma.cta_group::2.kind::i8 [%0], %1, %2, %3, {%4, %5, %6, %7}, PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(__disable_output_lane[0]),
+        "r"(__disable_output_lane[1]),
+        "r"(__disable_output_lane[2]),
+        "r"(__disable_output_lane[3]),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_mma_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.mma.cta_group.kind [d_tmem], a_desc, b_desc, idesc, enable_input_d, scale_input_d; // PTX ISA 86, SM_100a
+// .kind      = { .kind::f16, .kind::tf32 }
+// .cta_group = { .cta_group::1, .cta_group::2 }
+template <int N32, cuda::ptx::dot_kind Kind, cuda::ptx::dot_cta_group Cta_Group>
+__device__ static inline void tcgen05_mma(
+  cuda::ptx::kind_t<Kind> kind,
+  cuda::ptx::cta_group_t<Cta_Group> cta_group,
+  uint32_t d_tmem,
+  uint64_t a_desc,
+  uint64_t b_desc,
+  uint32_t idesc,
+  bool enable_input_d,
+  cuda::ptx::n32_t<N32> scale_input_d);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_mma_is_not_supported_before_SM_100a__();
+template <int _N32, dot_kind _Kind, dot_cta_group _Cta_Group>
+_CCCL_DEVICE static inline void tcgen05_mma(
+  kind_t<_Kind> __kind,
+  cta_group_t<_Cta_Group> __cta_group,
+  _CUDA_VSTD::uint32_t __d_tmem,
+  _CUDA_VSTD::uint64_t __a_desc,
+  _CUDA_VSTD::uint64_t __b_desc,
+  _CUDA_VSTD::uint32_t __idesc,
+  bool __enable_input_d,
+  n32_t<_N32> __scale_input_d)
+{
+  static_assert(__kind == kind_f16 || __kind == kind_tf32, "");
+  static_assert(__cta_group == cta_group_1 || __cta_group == cta_group_2, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL
+  _CCCL_IF_CONSTEXPR (__kind == kind_f16 && __cta_group == cta_group_1)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, PRED_enable_input_d, %5;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d)),
+        "n"(__scale_input_d.value)
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_f16 && __cta_group == cta_group_2)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.cta_group::2.kind::f16 [%0], %1, %2, %3, PRED_enable_input_d, %5;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d)),
+        "n"(__scale_input_d.value)
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_tf32 && __cta_group == cta_group_1)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.cta_group::1.kind::tf32 [%0], %1, %2, %3, PRED_enable_input_d, %5;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d)),
+        "n"(__scale_input_d.value)
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_tf32 && __cta_group == cta_group_2)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.cta_group::2.kind::tf32 [%0], %1, %2, %3, PRED_enable_input_d, %5;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d)),
+        "n"(__scale_input_d.value)
+      : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_mma_is_not_supported_before_SM_100a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.mma.cta_group.kind [d_tmem], a_desc, b_desc, idesc, enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+// .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+// .cta_group = { .cta_group::1, .cta_group::2 }
+template <cuda::ptx::dot_kind Kind, cuda::ptx::dot_cta_group Cta_Group>
+__device__ static inline void tcgen05_mma(
+  cuda::ptx::kind_t<Kind> kind,
+  cuda::ptx::cta_group_t<Cta_Group> cta_group,
+  uint32_t d_tmem,
+  uint64_t a_desc,
+  uint64_t b_desc,
+  uint32_t idesc,
+  bool enable_input_d);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_mma_is_not_supported_before_SM_100a_SM_101a__();
+template <dot_kind _Kind, dot_cta_group _Cta_Group>
+_CCCL_DEVICE static inline void tcgen05_mma(
+  kind_t<_Kind> __kind,
+  cta_group_t<_Cta_Group> __cta_group,
+  _CUDA_VSTD::uint32_t __d_tmem,
+  _CUDA_VSTD::uint64_t __a_desc,
+  _CUDA_VSTD::uint64_t __b_desc,
+  _CUDA_VSTD::uint32_t __idesc,
+  bool __enable_input_d)
+{
+  static_assert(__kind == kind_f16 || __kind == kind_tf32 || __kind == kind_f8f6f4 || __kind == kind_i8, "");
+  static_assert(__cta_group == cta_group_1 || __cta_group == cta_group_2, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  _CCCL_IF_CONSTEXPR (__kind == kind_f16 && __cta_group == cta_group_1)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_f16 && __cta_group == cta_group_2)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.cta_group::2.kind::f16 [%0], %1, %2, %3, PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_tf32 && __cta_group == cta_group_1)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.cta_group::1.kind::tf32 [%0], %1, %2, %3, PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_tf32 && __cta_group == cta_group_2)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.cta_group::2.kind::tf32 [%0], %1, %2, %3, PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_f8f6f4 && __cta_group == cta_group_1)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.cta_group::1.kind::f8f6f4 [%0], %1, %2, %3, PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_f8f6f4 && __cta_group == cta_group_2)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.cta_group::2.kind::f8f6f4 [%0], %1, %2, %3, PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_i8 && __cta_group == cta_group_1)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.cta_group::1.kind::i8 [%0], %1, %2, %3, PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_i8 && __cta_group == cta_group_2)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.cta_group::2.kind::i8 [%0], %1, %2, %3, PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_mma_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.mma.cta_group.kind [d_tmem], [a_tmem], b_desc, idesc, disable_output_lane, enable_input_d, scale_input_d; //
+PTX ISA 86, SM_100a
+// .kind      = { .kind::f16, .kind::tf32 }
+// .cta_group = { .cta_group::1, .cta_group::2 }
+template <int N32, cuda::ptx::dot_kind Kind, cuda::ptx::dot_cta_group Cta_Group>
+__device__ static inline void tcgen05_mma_tmem_a(
+  cuda::ptx::kind_t<Kind> kind,
+  cuda::ptx::cta_group_t<Cta_Group> cta_group,
+  uint32_t d_tmem,
+  uint32_t a_tmem,
+  uint64_t b_desc,
+  uint32_t idesc,
+  const uint32_t (&disable_output_lane)[4],
+  bool enable_input_d,
+  cuda::ptx::n32_t<N32> scale_input_d);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_mma_tmem_a_is_not_supported_before_SM_100a__();
+template <int _N32, dot_kind _Kind, dot_cta_group _Cta_Group>
+_CCCL_DEVICE static inline void tcgen05_mma_tmem_a(
+  kind_t<_Kind> __kind,
+  cta_group_t<_Cta_Group> __cta_group,
+  _CUDA_VSTD::uint32_t __d_tmem,
+  _CUDA_VSTD::uint32_t __a_tmem,
+  _CUDA_VSTD::uint64_t __b_desc,
+  _CUDA_VSTD::uint32_t __idesc,
+  const _CUDA_VSTD::uint32_t (&__disable_output_lane)[4],
+  bool __enable_input_d,
+  n32_t<_N32> __scale_input_d)
+{
+  static_assert(__kind == kind_f16 || __kind == kind_tf32, "");
+  static_assert(__cta_group == cta_group_1 || __cta_group == cta_group_2, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL
+  _CCCL_IF_CONSTEXPR (__kind == kind_f16 && __cta_group == cta_group_1)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %8, 0;\n\t"
+      "tcgen05.mma.cta_group::1.kind::f16 [%0], [%1], %2, %3, {%4, %5, %6, %7}, PRED_enable_input_d, %9;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "r"(__a_tmem),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(__disable_output_lane[0]),
+        "r"(__disable_output_lane[1]),
+        "r"(__disable_output_lane[2]),
+        "r"(__disable_output_lane[3]),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d)),
+        "n"(__scale_input_d.value)
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_f16 && __cta_group == cta_group_2)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %8, 0;\n\t"
+      "tcgen05.mma.cta_group::2.kind::f16 [%0], [%1], %2, %3, {%4, %5, %6, %7}, PRED_enable_input_d, %9;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "r"(__a_tmem),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(__disable_output_lane[0]),
+        "r"(__disable_output_lane[1]),
+        "r"(__disable_output_lane[2]),
+        "r"(__disable_output_lane[3]),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d)),
+        "n"(__scale_input_d.value)
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_tf32 && __cta_group == cta_group_1)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %8, 0;\n\t"
+      "tcgen05.mma.cta_group::1.kind::tf32 [%0], [%1], %2, %3, {%4, %5, %6, %7}, PRED_enable_input_d, %9;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "r"(__a_tmem),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(__disable_output_lane[0]),
+        "r"(__disable_output_lane[1]),
+        "r"(__disable_output_lane[2]),
+        "r"(__disable_output_lane[3]),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d)),
+        "n"(__scale_input_d.value)
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_tf32 && __cta_group == cta_group_2)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %8, 0;\n\t"
+      "tcgen05.mma.cta_group::2.kind::tf32 [%0], [%1], %2, %3, {%4, %5, %6, %7}, PRED_enable_input_d, %9;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "r"(__a_tmem),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(__disable_output_lane[0]),
+        "r"(__disable_output_lane[1]),
+        "r"(__disable_output_lane[2]),
+        "r"(__disable_output_lane[3]),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d)),
+        "n"(__scale_input_d.value)
+      : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_mma_tmem_a_is_not_supported_before_SM_100a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.mma.cta_group.kind [d_tmem], [a_tmem], b_desc, idesc, disable_output_lane, enable_input_d; // PTX ISA 86,
+SM_100a, SM_101a
+// .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+// .cta_group = { .cta_group::1, .cta_group::2 }
+template <cuda::ptx::dot_kind Kind, cuda::ptx::dot_cta_group Cta_Group>
+__device__ static inline void tcgen05_mma_tmem_a(
+  cuda::ptx::kind_t<Kind> kind,
+  cuda::ptx::cta_group_t<Cta_Group> cta_group,
+  uint32_t d_tmem,
+  uint32_t a_tmem,
+  uint64_t b_desc,
+  uint32_t idesc,
+  const uint32_t (&disable_output_lane)[4],
+  bool enable_input_d);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_mma_tmem_a_is_not_supported_before_SM_100a_SM_101a__();
+template <dot_kind _Kind, dot_cta_group _Cta_Group>
+_CCCL_DEVICE static inline void tcgen05_mma_tmem_a(
+  kind_t<_Kind> __kind,
+  cta_group_t<_Cta_Group> __cta_group,
+  _CUDA_VSTD::uint32_t __d_tmem,
+  _CUDA_VSTD::uint32_t __a_tmem,
+  _CUDA_VSTD::uint64_t __b_desc,
+  _CUDA_VSTD::uint32_t __idesc,
+  const _CUDA_VSTD::uint32_t (&__disable_output_lane)[4],
+  bool __enable_input_d)
+{
+  static_assert(__kind == kind_f16 || __kind == kind_tf32 || __kind == kind_f8f6f4 || __kind == kind_i8, "");
+  static_assert(__cta_group == cta_group_1 || __cta_group == cta_group_2, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  _CCCL_IF_CONSTEXPR (__kind == kind_f16 && __cta_group == cta_group_1)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %8, 0;\n\t"
+      "tcgen05.mma.cta_group::1.kind::f16 [%0], [%1], %2, %3, {%4, %5, %6, %7}, PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "r"(__a_tmem),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(__disable_output_lane[0]),
+        "r"(__disable_output_lane[1]),
+        "r"(__disable_output_lane[2]),
+        "r"(__disable_output_lane[3]),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_f16 && __cta_group == cta_group_2)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %8, 0;\n\t"
+      "tcgen05.mma.cta_group::2.kind::f16 [%0], [%1], %2, %3, {%4, %5, %6, %7}, PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "r"(__a_tmem),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(__disable_output_lane[0]),
+        "r"(__disable_output_lane[1]),
+        "r"(__disable_output_lane[2]),
+        "r"(__disable_output_lane[3]),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_tf32 && __cta_group == cta_group_1)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %8, 0;\n\t"
+      "tcgen05.mma.cta_group::1.kind::tf32 [%0], [%1], %2, %3, {%4, %5, %6, %7}, PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "r"(__a_tmem),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(__disable_output_lane[0]),
+        "r"(__disable_output_lane[1]),
+        "r"(__disable_output_lane[2]),
+        "r"(__disable_output_lane[3]),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_tf32 && __cta_group == cta_group_2)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %8, 0;\n\t"
+      "tcgen05.mma.cta_group::2.kind::tf32 [%0], [%1], %2, %3, {%4, %5, %6, %7}, PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "r"(__a_tmem),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(__disable_output_lane[0]),
+        "r"(__disable_output_lane[1]),
+        "r"(__disable_output_lane[2]),
+        "r"(__disable_output_lane[3]),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_f8f6f4 && __cta_group == cta_group_1)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %8, 0;\n\t"
+      "tcgen05.mma.cta_group::1.kind::f8f6f4 [%0], [%1], %2, %3, {%4, %5, %6, %7}, PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "r"(__a_tmem),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(__disable_output_lane[0]),
+        "r"(__disable_output_lane[1]),
+        "r"(__disable_output_lane[2]),
+        "r"(__disable_output_lane[3]),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_f8f6f4 && __cta_group == cta_group_2)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %8, 0;\n\t"
+      "tcgen05.mma.cta_group::2.kind::f8f6f4 [%0], [%1], %2, %3, {%4, %5, %6, %7}, PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "r"(__a_tmem),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(__disable_output_lane[0]),
+        "r"(__disable_output_lane[1]),
+        "r"(__disable_output_lane[2]),
+        "r"(__disable_output_lane[3]),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_i8 && __cta_group == cta_group_1)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %8, 0;\n\t"
+      "tcgen05.mma.cta_group::1.kind::i8 [%0], [%1], %2, %3, {%4, %5, %6, %7}, PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "r"(__a_tmem),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(__disable_output_lane[0]),
+        "r"(__disable_output_lane[1]),
+        "r"(__disable_output_lane[2]),
+        "r"(__disable_output_lane[3]),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_i8 && __cta_group == cta_group_2)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %8, 0;\n\t"
+      "tcgen05.mma.cta_group::2.kind::i8 [%0], [%1], %2, %3, {%4, %5, %6, %7}, PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "r"(__a_tmem),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(__disable_output_lane[0]),
+        "r"(__disable_output_lane[1]),
+        "r"(__disable_output_lane[2]),
+        "r"(__disable_output_lane[3]),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_mma_tmem_a_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.mma.cta_group.kind [d_tmem], [a_tmem], b_desc, idesc, enable_input_d, scale_input_d; // PTX ISA 86, SM_100a
+// .kind      = { .kind::f16, .kind::tf32 }
+// .cta_group = { .cta_group::1, .cta_group::2 }
+template <int N32, cuda::ptx::dot_kind Kind, cuda::ptx::dot_cta_group Cta_Group>
+__device__ static inline void tcgen05_mma_tmem_a(
+  cuda::ptx::kind_t<Kind> kind,
+  cuda::ptx::cta_group_t<Cta_Group> cta_group,
+  uint32_t d_tmem,
+  uint32_t a_tmem,
+  uint64_t b_desc,
+  uint32_t idesc,
+  bool enable_input_d,
+  cuda::ptx::n32_t<N32> scale_input_d);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_mma_tmem_a_is_not_supported_before_SM_100a__();
+template <int _N32, dot_kind _Kind, dot_cta_group _Cta_Group>
+_CCCL_DEVICE static inline void tcgen05_mma_tmem_a(
+  kind_t<_Kind> __kind,
+  cta_group_t<_Cta_Group> __cta_group,
+  _CUDA_VSTD::uint32_t __d_tmem,
+  _CUDA_VSTD::uint32_t __a_tmem,
+  _CUDA_VSTD::uint64_t __b_desc,
+  _CUDA_VSTD::uint32_t __idesc,
+  bool __enable_input_d,
+  n32_t<_N32> __scale_input_d)
+{
+  static_assert(__kind == kind_f16 || __kind == kind_tf32, "");
+  static_assert(__cta_group == cta_group_1 || __cta_group == cta_group_2, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL
+  _CCCL_IF_CONSTEXPR (__kind == kind_f16 && __cta_group == cta_group_1)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.cta_group::1.kind::f16 [%0], [%1], %2, %3, PRED_enable_input_d, %5;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "r"(__a_tmem),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d)),
+        "n"(__scale_input_d.value)
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_f16 && __cta_group == cta_group_2)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.cta_group::2.kind::f16 [%0], [%1], %2, %3, PRED_enable_input_d, %5;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "r"(__a_tmem),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d)),
+        "n"(__scale_input_d.value)
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_tf32 && __cta_group == cta_group_1)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.cta_group::1.kind::tf32 [%0], [%1], %2, %3, PRED_enable_input_d, %5;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "r"(__a_tmem),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d)),
+        "n"(__scale_input_d.value)
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_tf32 && __cta_group == cta_group_2)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.cta_group::2.kind::tf32 [%0], [%1], %2, %3, PRED_enable_input_d, %5;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "r"(__a_tmem),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d)),
+        "n"(__scale_input_d.value)
+      : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_mma_tmem_a_is_not_supported_before_SM_100a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.mma.cta_group.kind [d_tmem], [a_tmem], b_desc, idesc, enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+// .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+// .cta_group = { .cta_group::1, .cta_group::2 }
+template <cuda::ptx::dot_kind Kind, cuda::ptx::dot_cta_group Cta_Group>
+__device__ static inline void tcgen05_mma_tmem_a(
+  cuda::ptx::kind_t<Kind> kind,
+  cuda::ptx::cta_group_t<Cta_Group> cta_group,
+  uint32_t d_tmem,
+  uint32_t a_tmem,
+  uint64_t b_desc,
+  uint32_t idesc,
+  bool enable_input_d);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_mma_tmem_a_is_not_supported_before_SM_100a_SM_101a__();
+template <dot_kind _Kind, dot_cta_group _Cta_Group>
+_CCCL_DEVICE static inline void tcgen05_mma_tmem_a(
+  kind_t<_Kind> __kind,
+  cta_group_t<_Cta_Group> __cta_group,
+  _CUDA_VSTD::uint32_t __d_tmem,
+  _CUDA_VSTD::uint32_t __a_tmem,
+  _CUDA_VSTD::uint64_t __b_desc,
+  _CUDA_VSTD::uint32_t __idesc,
+  bool __enable_input_d)
+{
+  static_assert(__kind == kind_f16 || __kind == kind_tf32 || __kind == kind_f8f6f4 || __kind == kind_i8, "");
+  static_assert(__cta_group == cta_group_1 || __cta_group == cta_group_2, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  _CCCL_IF_CONSTEXPR (__kind == kind_f16 && __cta_group == cta_group_1)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.cta_group::1.kind::f16 [%0], [%1], %2, %3, PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "r"(__a_tmem),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_f16 && __cta_group == cta_group_2)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.cta_group::2.kind::f16 [%0], [%1], %2, %3, PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "r"(__a_tmem),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_tf32 && __cta_group == cta_group_1)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.cta_group::1.kind::tf32 [%0], [%1], %2, %3, PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "r"(__a_tmem),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_tf32 && __cta_group == cta_group_2)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.cta_group::2.kind::tf32 [%0], [%1], %2, %3, PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "r"(__a_tmem),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_f8f6f4 && __cta_group == cta_group_1)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.cta_group::1.kind::f8f6f4 [%0], [%1], %2, %3, PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "r"(__a_tmem),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_f8f6f4 && __cta_group == cta_group_2)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.cta_group::2.kind::f8f6f4 [%0], [%1], %2, %3, PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "r"(__a_tmem),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_i8 && __cta_group == cta_group_1)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.cta_group::1.kind::i8 [%0], [%1], %2, %3, PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "r"(__a_tmem),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_i8 && __cta_group == cta_group_2)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.cta_group::2.kind::i8 [%0], [%1], %2, %3, PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "r"(__a_tmem),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_mma_tmem_a_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.mma.cta_group.kind.block_scale.scale_vec::1X [d_tmem], a_desc, b_desc, idesc, [scale_A_tmem], [scale_B_tmem],
+enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+// .kind      = { .kind::mxf8f6f4 }
+// .cta_group = { .cta_group::1, .cta_group::2 }
+template <cuda::ptx::dot_cta_group Cta_Group>
+__device__ static inline void tcgen05_mma_block_scale_vec_1x(
+  cuda::ptx::kind_mxf8f6f4_t,
+  cuda::ptx::cta_group_t<Cta_Group> cta_group,
+  uint32_t d_tmem,
+  uint64_t a_desc,
+  uint64_t b_desc,
+  uint32_t idesc,
+  uint32_t scale_A_tmem,
+  uint32_t scale_B_tmem,
+  bool enable_input_d);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_mma_block_scale_vec_1x_is_not_supported_before_SM_100a_SM_101a__();
+template <dot_cta_group _Cta_Group>
+_CCCL_DEVICE static inline void tcgen05_mma_block_scale_vec_1x(
+  kind_mxf8f6f4_t,
+  cta_group_t<_Cta_Group> __cta_group,
+  _CUDA_VSTD::uint32_t __d_tmem,
+  _CUDA_VSTD::uint64_t __a_desc,
+  _CUDA_VSTD::uint64_t __b_desc,
+  _CUDA_VSTD::uint32_t __idesc,
+  _CUDA_VSTD::uint32_t __scale_A_tmem,
+  _CUDA_VSTD::uint32_t __scale_B_tmem,
+  bool __enable_input_d)
+{
+  // __kind == kind_mxf8f6f4 (due to parameter type constraint)
+  static_assert(__cta_group == cta_group_1 || __cta_group == cta_group_2, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  _CCCL_IF_CONSTEXPR (__cta_group == cta_group_1)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %6, 0;\n\t"
+      "tcgen05.mma.cta_group::1.kind::mxf8f6f4.block_scale.scale_vec::1X [%0], %1, %2, %3, [%4], [%5], "
+      "PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(__scale_A_tmem),
+        "r"(__scale_B_tmem),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__cta_group == cta_group_2)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %6, 0;\n\t"
+      "tcgen05.mma.cta_group::2.kind::mxf8f6f4.block_scale.scale_vec::1X [%0], %1, %2, %3, [%4], [%5], "
+      "PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(__scale_A_tmem),
+        "r"(__scale_B_tmem),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_mma_block_scale_vec_1x_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.mma.cta_group.kind.block_scale.scale_vec::2X [d_tmem], a_desc, b_desc, idesc, [scale_A_tmem], [scale_B_tmem],
+enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+// .kind      = { .kind::mxf4, .kind::mxf4nvf4 }
+// .cta_group = { .cta_group::1, .cta_group::2 }
+template <cuda::ptx::dot_kind Kind, cuda::ptx::dot_cta_group Cta_Group>
+__device__ static inline void tcgen05_mma_block_scale_vec_2x(
+  cuda::ptx::kind_t<Kind> kind,
+  cuda::ptx::cta_group_t<Cta_Group> cta_group,
+  uint32_t d_tmem,
+  uint64_t a_desc,
+  uint64_t b_desc,
+  uint32_t idesc,
+  uint32_t scale_A_tmem,
+  uint32_t scale_B_tmem,
+  bool enable_input_d);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_mma_block_scale_vec_2x_is_not_supported_before_SM_100a_SM_101a__();
+template <dot_kind _Kind, dot_cta_group _Cta_Group>
+_CCCL_DEVICE static inline void tcgen05_mma_block_scale_vec_2x(
+  kind_t<_Kind> __kind,
+  cta_group_t<_Cta_Group> __cta_group,
+  _CUDA_VSTD::uint32_t __d_tmem,
+  _CUDA_VSTD::uint64_t __a_desc,
+  _CUDA_VSTD::uint64_t __b_desc,
+  _CUDA_VSTD::uint32_t __idesc,
+  _CUDA_VSTD::uint32_t __scale_A_tmem,
+  _CUDA_VSTD::uint32_t __scale_B_tmem,
+  bool __enable_input_d)
+{
+  static_assert(__kind == kind_mxf4 || __kind == kind_mxf4nvf4, "");
+  static_assert(__cta_group == cta_group_1 || __cta_group == cta_group_2, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  _CCCL_IF_CONSTEXPR (__kind == kind_mxf4 && __cta_group == cta_group_1)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %6, 0;\n\t"
+      "tcgen05.mma.cta_group::1.kind::mxf4.block_scale.scale_vec::2X [%0], %1, %2, %3, [%4], [%5], "
+      "PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(__scale_A_tmem),
+        "r"(__scale_B_tmem),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_mxf4 && __cta_group == cta_group_2)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %6, 0;\n\t"
+      "tcgen05.mma.cta_group::2.kind::mxf4.block_scale.scale_vec::2X [%0], %1, %2, %3, [%4], [%5], "
+      "PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(__scale_A_tmem),
+        "r"(__scale_B_tmem),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_mxf4nvf4 && __cta_group == cta_group_1)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %6, 0;\n\t"
+      "tcgen05.mma.cta_group::1.kind::mxf4nvf4.block_scale.scale_vec::2X [%0], %1, %2, %3, [%4], [%5], "
+      "PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(__scale_A_tmem),
+        "r"(__scale_B_tmem),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_mxf4nvf4 && __cta_group == cta_group_2)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %6, 0;\n\t"
+      "tcgen05.mma.cta_group::2.kind::mxf4nvf4.block_scale.scale_vec::2X [%0], %1, %2, %3, [%4], [%5], "
+      "PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(__scale_A_tmem),
+        "r"(__scale_B_tmem),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_mma_block_scale_vec_2x_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.mma.cta_group.kind.block_scale.scale_vec::4X [d_tmem], a_desc, b_desc, idesc, [scale_A_tmem], [scale_B_tmem],
+enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+// .kind      = { .kind::mxf4nvf4 }
+// .cta_group = { .cta_group::1, .cta_group::2 }
+template <cuda::ptx::dot_cta_group Cta_Group>
+__device__ static inline void tcgen05_mma_block_scale_vec_4x(
+  cuda::ptx::kind_mxf4nvf4_t,
+  cuda::ptx::cta_group_t<Cta_Group> cta_group,
+  uint32_t d_tmem,
+  uint64_t a_desc,
+  uint64_t b_desc,
+  uint32_t idesc,
+  uint32_t scale_A_tmem,
+  uint32_t scale_B_tmem,
+  bool enable_input_d);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_mma_block_scale_vec_4x_is_not_supported_before_SM_100a_SM_101a__();
+template <dot_cta_group _Cta_Group>
+_CCCL_DEVICE static inline void tcgen05_mma_block_scale_vec_4x(
+  kind_mxf4nvf4_t,
+  cta_group_t<_Cta_Group> __cta_group,
+  _CUDA_VSTD::uint32_t __d_tmem,
+  _CUDA_VSTD::uint64_t __a_desc,
+  _CUDA_VSTD::uint64_t __b_desc,
+  _CUDA_VSTD::uint32_t __idesc,
+  _CUDA_VSTD::uint32_t __scale_A_tmem,
+  _CUDA_VSTD::uint32_t __scale_B_tmem,
+  bool __enable_input_d)
+{
+  // __kind == kind_mxf4nvf4 (due to parameter type constraint)
+  static_assert(__cta_group == cta_group_1 || __cta_group == cta_group_2, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  _CCCL_IF_CONSTEXPR (__cta_group == cta_group_1)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %6, 0;\n\t"
+      "tcgen05.mma.cta_group::1.kind::mxf4nvf4.block_scale.scale_vec::4X [%0], %1, %2, %3, [%4], [%5], "
+      "PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(__scale_A_tmem),
+        "r"(__scale_B_tmem),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__cta_group == cta_group_2)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %6, 0;\n\t"
+      "tcgen05.mma.cta_group::2.kind::mxf4nvf4.block_scale.scale_vec::4X [%0], %1, %2, %3, [%4], [%5], "
+      "PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(__scale_A_tmem),
+        "r"(__scale_B_tmem),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_mma_block_scale_vec_4x_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.mma.cta_group.kind.block_scale.scale_vec::1X [d_tmem], a_desc, b_desc, idesc, [scale_A_tmem], [scale_B_tmem],
+enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+// .kind      = { .kind::mxf8f6f4 }
+// .cta_group = { .cta_group::1, .cta_group::2 }
+template <cuda::ptx::dot_cta_group Cta_Group>
+__device__ static inline void tcgen05_mma_block_scale_vec_1x_tmem_a(
+  cuda::ptx::kind_mxf8f6f4_t,
+  cuda::ptx::cta_group_t<Cta_Group> cta_group,
+  uint32_t d_tmem,
+  uint64_t a_desc,
+  uint64_t b_desc,
+  uint32_t idesc,
+  uint32_t scale_A_tmem,
+  uint32_t scale_B_tmem,
+  bool enable_input_d);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void
+__cuda_ptx_tcgen05_mma_block_scale_vec_1x_tmem_a_is_not_supported_before_SM_100a_SM_101a__();
+template <dot_cta_group _Cta_Group>
+_CCCL_DEVICE static inline void tcgen05_mma_block_scale_vec_1x_tmem_a(
+  kind_mxf8f6f4_t,
+  cta_group_t<_Cta_Group> __cta_group,
+  _CUDA_VSTD::uint32_t __d_tmem,
+  _CUDA_VSTD::uint64_t __a_desc,
+  _CUDA_VSTD::uint64_t __b_desc,
+  _CUDA_VSTD::uint32_t __idesc,
+  _CUDA_VSTD::uint32_t __scale_A_tmem,
+  _CUDA_VSTD::uint32_t __scale_B_tmem,
+  bool __enable_input_d)
+{
+  // __kind == kind_mxf8f6f4 (due to parameter type constraint)
+  static_assert(__cta_group == cta_group_1 || __cta_group == cta_group_2, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  _CCCL_IF_CONSTEXPR (__cta_group == cta_group_1)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %6, 0;\n\t"
+      "tcgen05.mma.cta_group::1.kind::mxf8f6f4.block_scale.scale_vec::1X [%0], %1, %2, %3, [%4], [%5], "
+      "PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(__scale_A_tmem),
+        "r"(__scale_B_tmem),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__cta_group == cta_group_2)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %6, 0;\n\t"
+      "tcgen05.mma.cta_group::2.kind::mxf8f6f4.block_scale.scale_vec::1X [%0], %1, %2, %3, [%4], [%5], "
+      "PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(__scale_A_tmem),
+        "r"(__scale_B_tmem),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_mma_block_scale_vec_1x_tmem_a_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.mma.cta_group.kind.block_scale.scale_vec::2X [d_tmem], a_desc, b_desc, idesc, [scale_A_tmem], [scale_B_tmem],
+enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+// .kind      = { .kind::mxf4, .kind::mxf4nvf4 }
+// .cta_group = { .cta_group::1, .cta_group::2 }
+template <cuda::ptx::dot_kind Kind, cuda::ptx::dot_cta_group Cta_Group>
+__device__ static inline void tcgen05_mma_block_scale_vec_2_tmem_a(
+  cuda::ptx::kind_t<Kind> kind,
+  cuda::ptx::cta_group_t<Cta_Group> cta_group,
+  uint32_t d_tmem,
+  uint64_t a_desc,
+  uint64_t b_desc,
+  uint32_t idesc,
+  uint32_t scale_A_tmem,
+  uint32_t scale_B_tmem,
+  bool enable_input_d);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_mma_block_scale_vec_2_tmem_a_is_not_supported_before_SM_100a_SM_101a__();
+template <dot_kind _Kind, dot_cta_group _Cta_Group>
+_CCCL_DEVICE static inline void tcgen05_mma_block_scale_vec_2_tmem_a(
+  kind_t<_Kind> __kind,
+  cta_group_t<_Cta_Group> __cta_group,
+  _CUDA_VSTD::uint32_t __d_tmem,
+  _CUDA_VSTD::uint64_t __a_desc,
+  _CUDA_VSTD::uint64_t __b_desc,
+  _CUDA_VSTD::uint32_t __idesc,
+  _CUDA_VSTD::uint32_t __scale_A_tmem,
+  _CUDA_VSTD::uint32_t __scale_B_tmem,
+  bool __enable_input_d)
+{
+  static_assert(__kind == kind_mxf4 || __kind == kind_mxf4nvf4, "");
+  static_assert(__cta_group == cta_group_1 || __cta_group == cta_group_2, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  _CCCL_IF_CONSTEXPR (__kind == kind_mxf4 && __cta_group == cta_group_1)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %6, 0;\n\t"
+      "tcgen05.mma.cta_group::1.kind::mxf4.block_scale.scale_vec::2X [%0], %1, %2, %3, [%4], [%5], "
+      "PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(__scale_A_tmem),
+        "r"(__scale_B_tmem),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_mxf4 && __cta_group == cta_group_2)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %6, 0;\n\t"
+      "tcgen05.mma.cta_group::2.kind::mxf4.block_scale.scale_vec::2X [%0], %1, %2, %3, [%4], [%5], "
+      "PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(__scale_A_tmem),
+        "r"(__scale_B_tmem),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_mxf4nvf4 && __cta_group == cta_group_1)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %6, 0;\n\t"
+      "tcgen05.mma.cta_group::1.kind::mxf4nvf4.block_scale.scale_vec::2X [%0], %1, %2, %3, [%4], [%5], "
+      "PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(__scale_A_tmem),
+        "r"(__scale_B_tmem),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_mxf4nvf4 && __cta_group == cta_group_2)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %6, 0;\n\t"
+      "tcgen05.mma.cta_group::2.kind::mxf4nvf4.block_scale.scale_vec::2X [%0], %1, %2, %3, [%4], [%5], "
+      "PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(__scale_A_tmem),
+        "r"(__scale_B_tmem),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_mma_block_scale_vec_2_tmem_a_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.mma.cta_group.kind.block_scale.scale_vec::4X [d_tmem], a_desc, b_desc, idesc, [scale_A_tmem], [scale_B_tmem],
+enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+// .kind      = { .kind::mxf4nvf4 }
+// .cta_group = { .cta_group::1, .cta_group::2 }
+template <cuda::ptx::dot_cta_group Cta_Group>
+__device__ static inline void tcgen05_mma_block_scale_vec_4x_tmem_a(
+  cuda::ptx::kind_mxf4nvf4_t,
+  cuda::ptx::cta_group_t<Cta_Group> cta_group,
+  uint32_t d_tmem,
+  uint64_t a_desc,
+  uint64_t b_desc,
+  uint32_t idesc,
+  uint32_t scale_A_tmem,
+  uint32_t scale_B_tmem,
+  bool enable_input_d);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void
+__cuda_ptx_tcgen05_mma_block_scale_vec_4x_tmem_a_is_not_supported_before_SM_100a_SM_101a__();
+template <dot_cta_group _Cta_Group>
+_CCCL_DEVICE static inline void tcgen05_mma_block_scale_vec_4x_tmem_a(
+  kind_mxf4nvf4_t,
+  cta_group_t<_Cta_Group> __cta_group,
+  _CUDA_VSTD::uint32_t __d_tmem,
+  _CUDA_VSTD::uint64_t __a_desc,
+  _CUDA_VSTD::uint64_t __b_desc,
+  _CUDA_VSTD::uint32_t __idesc,
+  _CUDA_VSTD::uint32_t __scale_A_tmem,
+  _CUDA_VSTD::uint32_t __scale_B_tmem,
+  bool __enable_input_d)
+{
+  // __kind == kind_mxf4nvf4 (due to parameter type constraint)
+  static_assert(__cta_group == cta_group_1 || __cta_group == cta_group_2, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  _CCCL_IF_CONSTEXPR (__cta_group == cta_group_1)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %6, 0;\n\t"
+      "tcgen05.mma.cta_group::1.kind::mxf4nvf4.block_scale.scale_vec::4X [%0], %1, %2, %3, [%4], [%5], "
+      "PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(__scale_A_tmem),
+        "r"(__scale_B_tmem),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__cta_group == cta_group_2)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %6, 0;\n\t"
+      "tcgen05.mma.cta_group::2.kind::mxf4nvf4.block_scale.scale_vec::4X [%0], %1, %2, %3, [%4], [%5], "
+      "PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(__scale_A_tmem),
+        "r"(__scale_B_tmem),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_mma_block_scale_vec_4x_tmem_a_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.mma.cta_group.kind.block_scale.scale_vec::1X.collector::a::fill [d_tmem], a_desc, b_desc, idesc,
+[scale_A_tmem], [scale_B_tmem], enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+// .kind      = { .kind::mxf8f6f4 }
+// .cta_group = { .cta_group::1, .cta_group::2 }
+template <cuda::ptx::dot_cta_group Cta_Group>
+__device__ static inline void tcgen05_mma_block_scale_vec_1x_collector_a_fill(
+  cuda::ptx::kind_mxf8f6f4_t,
+  cuda::ptx::cta_group_t<Cta_Group> cta_group,
+  uint32_t d_tmem,
+  uint64_t a_desc,
+  uint64_t b_desc,
+  uint32_t idesc,
+  uint32_t scale_A_tmem,
+  uint32_t scale_B_tmem,
+  bool enable_input_d);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void
+__cuda_ptx_tcgen05_mma_block_scale_vec_1x_collector_a_fill_is_not_supported_before_SM_100a_SM_101a__();
+template <dot_cta_group _Cta_Group>
+_CCCL_DEVICE static inline void tcgen05_mma_block_scale_vec_1x_collector_a_fill(
+  kind_mxf8f6f4_t,
+  cta_group_t<_Cta_Group> __cta_group,
+  _CUDA_VSTD::uint32_t __d_tmem,
+  _CUDA_VSTD::uint64_t __a_desc,
+  _CUDA_VSTD::uint64_t __b_desc,
+  _CUDA_VSTD::uint32_t __idesc,
+  _CUDA_VSTD::uint32_t __scale_A_tmem,
+  _CUDA_VSTD::uint32_t __scale_B_tmem,
+  bool __enable_input_d)
+{
+  // __kind == kind_mxf8f6f4 (due to parameter type constraint)
+  static_assert(__cta_group == cta_group_1 || __cta_group == cta_group_2, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  _CCCL_IF_CONSTEXPR (__cta_group == cta_group_1)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %6, 0;\n\t"
+      "tcgen05.mma.cta_group::1.kind::mxf8f6f4.block_scale.scale_vec::1X.collector::a::fill [%0], %1, %2, %3, [%4], "
+      "[%5], PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(__scale_A_tmem),
+        "r"(__scale_B_tmem),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__cta_group == cta_group_2)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %6, 0;\n\t"
+      "tcgen05.mma.cta_group::2.kind::mxf8f6f4.block_scale.scale_vec::1X.collector::a::fill [%0], %1, %2, %3, [%4], "
+      "[%5], PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(__scale_A_tmem),
+        "r"(__scale_B_tmem),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_mma_block_scale_vec_1x_collector_a_fill_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.mma.cta_group.kind.block_scale.scale_vec::2X.collector::a::fill [d_tmem], a_desc, b_desc, idesc,
+[scale_A_tmem], [scale_B_tmem], enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+// .kind      = { .kind::mxf4, .kind::mxf4nvf4 }
+// .cta_group = { .cta_group::1, .cta_group::2 }
+template <cuda::ptx::dot_kind Kind, cuda::ptx::dot_cta_group Cta_Group>
+__device__ static inline void tcgen05_mma_block_scale_vec_2x_collector_a_fill(
+  cuda::ptx::kind_t<Kind> kind,
+  cuda::ptx::cta_group_t<Cta_Group> cta_group,
+  uint32_t d_tmem,
+  uint64_t a_desc,
+  uint64_t b_desc,
+  uint32_t idesc,
+  uint32_t scale_A_tmem,
+  uint32_t scale_B_tmem,
+  bool enable_input_d);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void
+__cuda_ptx_tcgen05_mma_block_scale_vec_2x_collector_a_fill_is_not_supported_before_SM_100a_SM_101a__();
+template <dot_kind _Kind, dot_cta_group _Cta_Group>
+_CCCL_DEVICE static inline void tcgen05_mma_block_scale_vec_2x_collector_a_fill(
+  kind_t<_Kind> __kind,
+  cta_group_t<_Cta_Group> __cta_group,
+  _CUDA_VSTD::uint32_t __d_tmem,
+  _CUDA_VSTD::uint64_t __a_desc,
+  _CUDA_VSTD::uint64_t __b_desc,
+  _CUDA_VSTD::uint32_t __idesc,
+  _CUDA_VSTD::uint32_t __scale_A_tmem,
+  _CUDA_VSTD::uint32_t __scale_B_tmem,
+  bool __enable_input_d)
+{
+  static_assert(__kind == kind_mxf4 || __kind == kind_mxf4nvf4, "");
+  static_assert(__cta_group == cta_group_1 || __cta_group == cta_group_2, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  _CCCL_IF_CONSTEXPR (__kind == kind_mxf4 && __cta_group == cta_group_1)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %6, 0;\n\t"
+      "tcgen05.mma.cta_group::1.kind::mxf4.block_scale.scale_vec::2X.collector::a::fill [%0], %1, %2, %3, [%4], [%5], "
+      "PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(__scale_A_tmem),
+        "r"(__scale_B_tmem),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_mxf4 && __cta_group == cta_group_2)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %6, 0;\n\t"
+      "tcgen05.mma.cta_group::2.kind::mxf4.block_scale.scale_vec::2X.collector::a::fill [%0], %1, %2, %3, [%4], [%5], "
+      "PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(__scale_A_tmem),
+        "r"(__scale_B_tmem),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_mxf4nvf4 && __cta_group == cta_group_1)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %6, 0;\n\t"
+      "tcgen05.mma.cta_group::1.kind::mxf4nvf4.block_scale.scale_vec::2X.collector::a::fill [%0], %1, %2, %3, [%4], "
+      "[%5], PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(__scale_A_tmem),
+        "r"(__scale_B_tmem),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_mxf4nvf4 && __cta_group == cta_group_2)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %6, 0;\n\t"
+      "tcgen05.mma.cta_group::2.kind::mxf4nvf4.block_scale.scale_vec::2X.collector::a::fill [%0], %1, %2, %3, [%4], "
+      "[%5], PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(__scale_A_tmem),
+        "r"(__scale_B_tmem),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_mma_block_scale_vec_2x_collector_a_fill_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.mma.cta_group.kind.block_scale.scale_vec::4X.collector::a::fill [d_tmem], a_desc, b_desc, idesc,
+[scale_A_tmem], [scale_B_tmem], enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+// .kind      = { .kind::mxf4nvf4 }
+// .cta_group = { .cta_group::1, .cta_group::2 }
+template <cuda::ptx::dot_cta_group Cta_Group>
+__device__ static inline void tcgen05_mma_block_scale_vec_4x_collector_a_fill(
+  cuda::ptx::kind_mxf4nvf4_t,
+  cuda::ptx::cta_group_t<Cta_Group> cta_group,
+  uint32_t d_tmem,
+  uint64_t a_desc,
+  uint64_t b_desc,
+  uint32_t idesc,
+  uint32_t scale_A_tmem,
+  uint32_t scale_B_tmem,
+  bool enable_input_d);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void
+__cuda_ptx_tcgen05_mma_block_scale_vec_4x_collector_a_fill_is_not_supported_before_SM_100a_SM_101a__();
+template <dot_cta_group _Cta_Group>
+_CCCL_DEVICE static inline void tcgen05_mma_block_scale_vec_4x_collector_a_fill(
+  kind_mxf4nvf4_t,
+  cta_group_t<_Cta_Group> __cta_group,
+  _CUDA_VSTD::uint32_t __d_tmem,
+  _CUDA_VSTD::uint64_t __a_desc,
+  _CUDA_VSTD::uint64_t __b_desc,
+  _CUDA_VSTD::uint32_t __idesc,
+  _CUDA_VSTD::uint32_t __scale_A_tmem,
+  _CUDA_VSTD::uint32_t __scale_B_tmem,
+  bool __enable_input_d)
+{
+  // __kind == kind_mxf4nvf4 (due to parameter type constraint)
+  static_assert(__cta_group == cta_group_1 || __cta_group == cta_group_2, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  _CCCL_IF_CONSTEXPR (__cta_group == cta_group_1)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %6, 0;\n\t"
+      "tcgen05.mma.cta_group::1.kind::mxf4nvf4.block_scale.scale_vec::4X.collector::a::fill [%0], %1, %2, %3, [%4], "
+      "[%5], PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(__scale_A_tmem),
+        "r"(__scale_B_tmem),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__cta_group == cta_group_2)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %6, 0;\n\t"
+      "tcgen05.mma.cta_group::2.kind::mxf4nvf4.block_scale.scale_vec::4X.collector::a::fill [%0], %1, %2, %3, [%4], "
+      "[%5], PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(__scale_A_tmem),
+        "r"(__scale_B_tmem),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_mma_block_scale_vec_4x_collector_a_fill_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.mma.cta_group.kind.block_scale.scale_vec::1X.collector::a::fill [d_tmem], a_desc, b_desc, idesc,
+[scale_A_tmem], [scale_B_tmem], enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+// .kind      = { .kind::mxf8f6f4 }
+// .cta_group = { .cta_group::1, .cta_group::2 }
+template <cuda::ptx::dot_cta_group Cta_Group>
+__device__ static inline void tcgen05_mma_block_scale_vec_1x_tmem_a_collector_a_fill(
+  cuda::ptx::kind_mxf8f6f4_t,
+  cuda::ptx::cta_group_t<Cta_Group> cta_group,
+  uint32_t d_tmem,
+  uint64_t a_desc,
+  uint64_t b_desc,
+  uint32_t idesc,
+  uint32_t scale_A_tmem,
+  uint32_t scale_B_tmem,
+  bool enable_input_d);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void
+__cuda_ptx_tcgen05_mma_block_scale_vec_1x_tmem_a_collector_a_fill_is_not_supported_before_SM_100a_SM_101a__();
+template <dot_cta_group _Cta_Group>
+_CCCL_DEVICE static inline void tcgen05_mma_block_scale_vec_1x_tmem_a_collector_a_fill(
+  kind_mxf8f6f4_t,
+  cta_group_t<_Cta_Group> __cta_group,
+  _CUDA_VSTD::uint32_t __d_tmem,
+  _CUDA_VSTD::uint64_t __a_desc,
+  _CUDA_VSTD::uint64_t __b_desc,
+  _CUDA_VSTD::uint32_t __idesc,
+  _CUDA_VSTD::uint32_t __scale_A_tmem,
+  _CUDA_VSTD::uint32_t __scale_B_tmem,
+  bool __enable_input_d)
+{
+  // __kind == kind_mxf8f6f4 (due to parameter type constraint)
+  static_assert(__cta_group == cta_group_1 || __cta_group == cta_group_2, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  _CCCL_IF_CONSTEXPR (__cta_group == cta_group_1)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %6, 0;\n\t"
+      "tcgen05.mma.cta_group::1.kind::mxf8f6f4.block_scale.scale_vec::1X.collector::a::fill [%0], %1, %2, %3, [%4], "
+      "[%5], PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(__scale_A_tmem),
+        "r"(__scale_B_tmem),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__cta_group == cta_group_2)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %6, 0;\n\t"
+      "tcgen05.mma.cta_group::2.kind::mxf8f6f4.block_scale.scale_vec::1X.collector::a::fill [%0], %1, %2, %3, [%4], "
+      "[%5], PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(__scale_A_tmem),
+        "r"(__scale_B_tmem),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_mma_block_scale_vec_1x_tmem_a_collector_a_fill_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.mma.cta_group.kind.block_scale.scale_vec::2X.collector::a::fill [d_tmem], a_desc, b_desc, idesc,
+[scale_A_tmem], [scale_B_tmem], enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+// .kind      = { .kind::mxf4, .kind::mxf4nvf4 }
+// .cta_group = { .cta_group::1, .cta_group::2 }
+template <cuda::ptx::dot_kind Kind, cuda::ptx::dot_cta_group Cta_Group>
+__device__ static inline void tcgen05_mma_block_scale_vec_2_tmem_a_collector_a_fill(
+  cuda::ptx::kind_t<Kind> kind,
+  cuda::ptx::cta_group_t<Cta_Group> cta_group,
+  uint32_t d_tmem,
+  uint64_t a_desc,
+  uint64_t b_desc,
+  uint32_t idesc,
+  uint32_t scale_A_tmem,
+  uint32_t scale_B_tmem,
+  bool enable_input_d);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void
+__cuda_ptx_tcgen05_mma_block_scale_vec_2_tmem_a_collector_a_fill_is_not_supported_before_SM_100a_SM_101a__();
+template <dot_kind _Kind, dot_cta_group _Cta_Group>
+_CCCL_DEVICE static inline void tcgen05_mma_block_scale_vec_2_tmem_a_collector_a_fill(
+  kind_t<_Kind> __kind,
+  cta_group_t<_Cta_Group> __cta_group,
+  _CUDA_VSTD::uint32_t __d_tmem,
+  _CUDA_VSTD::uint64_t __a_desc,
+  _CUDA_VSTD::uint64_t __b_desc,
+  _CUDA_VSTD::uint32_t __idesc,
+  _CUDA_VSTD::uint32_t __scale_A_tmem,
+  _CUDA_VSTD::uint32_t __scale_B_tmem,
+  bool __enable_input_d)
+{
+  static_assert(__kind == kind_mxf4 || __kind == kind_mxf4nvf4, "");
+  static_assert(__cta_group == cta_group_1 || __cta_group == cta_group_2, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  _CCCL_IF_CONSTEXPR (__kind == kind_mxf4 && __cta_group == cta_group_1)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %6, 0;\n\t"
+      "tcgen05.mma.cta_group::1.kind::mxf4.block_scale.scale_vec::2X.collector::a::fill [%0], %1, %2, %3, [%4], [%5], "
+      "PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(__scale_A_tmem),
+        "r"(__scale_B_tmem),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_mxf4 && __cta_group == cta_group_2)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %6, 0;\n\t"
+      "tcgen05.mma.cta_group::2.kind::mxf4.block_scale.scale_vec::2X.collector::a::fill [%0], %1, %2, %3, [%4], [%5], "
+      "PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(__scale_A_tmem),
+        "r"(__scale_B_tmem),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_mxf4nvf4 && __cta_group == cta_group_1)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %6, 0;\n\t"
+      "tcgen05.mma.cta_group::1.kind::mxf4nvf4.block_scale.scale_vec::2X.collector::a::fill [%0], %1, %2, %3, [%4], "
+      "[%5], PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(__scale_A_tmem),
+        "r"(__scale_B_tmem),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_mxf4nvf4 && __cta_group == cta_group_2)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %6, 0;\n\t"
+      "tcgen05.mma.cta_group::2.kind::mxf4nvf4.block_scale.scale_vec::2X.collector::a::fill [%0], %1, %2, %3, [%4], "
+      "[%5], PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(__scale_A_tmem),
+        "r"(__scale_B_tmem),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_mma_block_scale_vec_2_tmem_a_collector_a_fill_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.mma.cta_group.kind.block_scale.scale_vec::4X.collector::a::fill [d_tmem], a_desc, b_desc, idesc,
+[scale_A_tmem], [scale_B_tmem], enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+// .kind      = { .kind::mxf4nvf4 }
+// .cta_group = { .cta_group::1, .cta_group::2 }
+template <cuda::ptx::dot_cta_group Cta_Group>
+__device__ static inline void tcgen05_mma_block_scale_vec_4x_tmem_a_collector_a_fill(
+  cuda::ptx::kind_mxf4nvf4_t,
+  cuda::ptx::cta_group_t<Cta_Group> cta_group,
+  uint32_t d_tmem,
+  uint64_t a_desc,
+  uint64_t b_desc,
+  uint32_t idesc,
+  uint32_t scale_A_tmem,
+  uint32_t scale_B_tmem,
+  bool enable_input_d);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void
+__cuda_ptx_tcgen05_mma_block_scale_vec_4x_tmem_a_collector_a_fill_is_not_supported_before_SM_100a_SM_101a__();
+template <dot_cta_group _Cta_Group>
+_CCCL_DEVICE static inline void tcgen05_mma_block_scale_vec_4x_tmem_a_collector_a_fill(
+  kind_mxf4nvf4_t,
+  cta_group_t<_Cta_Group> __cta_group,
+  _CUDA_VSTD::uint32_t __d_tmem,
+  _CUDA_VSTD::uint64_t __a_desc,
+  _CUDA_VSTD::uint64_t __b_desc,
+  _CUDA_VSTD::uint32_t __idesc,
+  _CUDA_VSTD::uint32_t __scale_A_tmem,
+  _CUDA_VSTD::uint32_t __scale_B_tmem,
+  bool __enable_input_d)
+{
+  // __kind == kind_mxf4nvf4 (due to parameter type constraint)
+  static_assert(__cta_group == cta_group_1 || __cta_group == cta_group_2, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  _CCCL_IF_CONSTEXPR (__cta_group == cta_group_1)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %6, 0;\n\t"
+      "tcgen05.mma.cta_group::1.kind::mxf4nvf4.block_scale.scale_vec::4X.collector::a::fill [%0], %1, %2, %3, [%4], "
+      "[%5], PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(__scale_A_tmem),
+        "r"(__scale_B_tmem),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__cta_group == cta_group_2)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %6, 0;\n\t"
+      "tcgen05.mma.cta_group::2.kind::mxf4nvf4.block_scale.scale_vec::4X.collector::a::fill [%0], %1, %2, %3, [%4], "
+      "[%5], PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(__scale_A_tmem),
+        "r"(__scale_B_tmem),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_mma_block_scale_vec_4x_tmem_a_collector_a_fill_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.mma.cta_group.kind.block_scale.scale_vec::1X.collector::a::use [d_tmem], a_desc, b_desc, idesc,
+[scale_A_tmem], [scale_B_tmem], enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+// .kind      = { .kind::mxf8f6f4 }
+// .cta_group = { .cta_group::1, .cta_group::2 }
+template <cuda::ptx::dot_cta_group Cta_Group>
+__device__ static inline void tcgen05_mma_block_scale_vec_1x_collector_a_use(
+  cuda::ptx::kind_mxf8f6f4_t,
+  cuda::ptx::cta_group_t<Cta_Group> cta_group,
+  uint32_t d_tmem,
+  uint64_t a_desc,
+  uint64_t b_desc,
+  uint32_t idesc,
+  uint32_t scale_A_tmem,
+  uint32_t scale_B_tmem,
+  bool enable_input_d);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void
+__cuda_ptx_tcgen05_mma_block_scale_vec_1x_collector_a_use_is_not_supported_before_SM_100a_SM_101a__();
+template <dot_cta_group _Cta_Group>
+_CCCL_DEVICE static inline void tcgen05_mma_block_scale_vec_1x_collector_a_use(
+  kind_mxf8f6f4_t,
+  cta_group_t<_Cta_Group> __cta_group,
+  _CUDA_VSTD::uint32_t __d_tmem,
+  _CUDA_VSTD::uint64_t __a_desc,
+  _CUDA_VSTD::uint64_t __b_desc,
+  _CUDA_VSTD::uint32_t __idesc,
+  _CUDA_VSTD::uint32_t __scale_A_tmem,
+  _CUDA_VSTD::uint32_t __scale_B_tmem,
+  bool __enable_input_d)
+{
+  // __kind == kind_mxf8f6f4 (due to parameter type constraint)
+  static_assert(__cta_group == cta_group_1 || __cta_group == cta_group_2, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  _CCCL_IF_CONSTEXPR (__cta_group == cta_group_1)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %6, 0;\n\t"
+      "tcgen05.mma.cta_group::1.kind::mxf8f6f4.block_scale.scale_vec::1X.collector::a::use [%0], %1, %2, %3, [%4], "
+      "[%5], PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(__scale_A_tmem),
+        "r"(__scale_B_tmem),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__cta_group == cta_group_2)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %6, 0;\n\t"
+      "tcgen05.mma.cta_group::2.kind::mxf8f6f4.block_scale.scale_vec::1X.collector::a::use [%0], %1, %2, %3, [%4], "
+      "[%5], PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(__scale_A_tmem),
+        "r"(__scale_B_tmem),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_mma_block_scale_vec_1x_collector_a_use_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.mma.cta_group.kind.block_scale.scale_vec::2X.collector::a::use [d_tmem], a_desc, b_desc, idesc,
+[scale_A_tmem], [scale_B_tmem], enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+// .kind      = { .kind::mxf4, .kind::mxf4nvf4 }
+// .cta_group = { .cta_group::1, .cta_group::2 }
+template <cuda::ptx::dot_kind Kind, cuda::ptx::dot_cta_group Cta_Group>
+__device__ static inline void tcgen05_mma_block_scale_vec_2x_collector_a_use(
+  cuda::ptx::kind_t<Kind> kind,
+  cuda::ptx::cta_group_t<Cta_Group> cta_group,
+  uint32_t d_tmem,
+  uint64_t a_desc,
+  uint64_t b_desc,
+  uint32_t idesc,
+  uint32_t scale_A_tmem,
+  uint32_t scale_B_tmem,
+  bool enable_input_d);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void
+__cuda_ptx_tcgen05_mma_block_scale_vec_2x_collector_a_use_is_not_supported_before_SM_100a_SM_101a__();
+template <dot_kind _Kind, dot_cta_group _Cta_Group>
+_CCCL_DEVICE static inline void tcgen05_mma_block_scale_vec_2x_collector_a_use(
+  kind_t<_Kind> __kind,
+  cta_group_t<_Cta_Group> __cta_group,
+  _CUDA_VSTD::uint32_t __d_tmem,
+  _CUDA_VSTD::uint64_t __a_desc,
+  _CUDA_VSTD::uint64_t __b_desc,
+  _CUDA_VSTD::uint32_t __idesc,
+  _CUDA_VSTD::uint32_t __scale_A_tmem,
+  _CUDA_VSTD::uint32_t __scale_B_tmem,
+  bool __enable_input_d)
+{
+  static_assert(__kind == kind_mxf4 || __kind == kind_mxf4nvf4, "");
+  static_assert(__cta_group == cta_group_1 || __cta_group == cta_group_2, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  _CCCL_IF_CONSTEXPR (__kind == kind_mxf4 && __cta_group == cta_group_1)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %6, 0;\n\t"
+      "tcgen05.mma.cta_group::1.kind::mxf4.block_scale.scale_vec::2X.collector::a::use [%0], %1, %2, %3, [%4], [%5], "
+      "PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(__scale_A_tmem),
+        "r"(__scale_B_tmem),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_mxf4 && __cta_group == cta_group_2)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %6, 0;\n\t"
+      "tcgen05.mma.cta_group::2.kind::mxf4.block_scale.scale_vec::2X.collector::a::use [%0], %1, %2, %3, [%4], [%5], "
+      "PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(__scale_A_tmem),
+        "r"(__scale_B_tmem),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_mxf4nvf4 && __cta_group == cta_group_1)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %6, 0;\n\t"
+      "tcgen05.mma.cta_group::1.kind::mxf4nvf4.block_scale.scale_vec::2X.collector::a::use [%0], %1, %2, %3, [%4], "
+      "[%5], PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(__scale_A_tmem),
+        "r"(__scale_B_tmem),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_mxf4nvf4 && __cta_group == cta_group_2)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %6, 0;\n\t"
+      "tcgen05.mma.cta_group::2.kind::mxf4nvf4.block_scale.scale_vec::2X.collector::a::use [%0], %1, %2, %3, [%4], "
+      "[%5], PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(__scale_A_tmem),
+        "r"(__scale_B_tmem),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_mma_block_scale_vec_2x_collector_a_use_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.mma.cta_group.kind.block_scale.scale_vec::4X.collector::a::use [d_tmem], a_desc, b_desc, idesc,
+[scale_A_tmem], [scale_B_tmem], enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+// .kind      = { .kind::mxf4nvf4 }
+// .cta_group = { .cta_group::1, .cta_group::2 }
+template <cuda::ptx::dot_cta_group Cta_Group>
+__device__ static inline void tcgen05_mma_block_scale_vec_4x_collector_a_use(
+  cuda::ptx::kind_mxf4nvf4_t,
+  cuda::ptx::cta_group_t<Cta_Group> cta_group,
+  uint32_t d_tmem,
+  uint64_t a_desc,
+  uint64_t b_desc,
+  uint32_t idesc,
+  uint32_t scale_A_tmem,
+  uint32_t scale_B_tmem,
+  bool enable_input_d);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void
+__cuda_ptx_tcgen05_mma_block_scale_vec_4x_collector_a_use_is_not_supported_before_SM_100a_SM_101a__();
+template <dot_cta_group _Cta_Group>
+_CCCL_DEVICE static inline void tcgen05_mma_block_scale_vec_4x_collector_a_use(
+  kind_mxf4nvf4_t,
+  cta_group_t<_Cta_Group> __cta_group,
+  _CUDA_VSTD::uint32_t __d_tmem,
+  _CUDA_VSTD::uint64_t __a_desc,
+  _CUDA_VSTD::uint64_t __b_desc,
+  _CUDA_VSTD::uint32_t __idesc,
+  _CUDA_VSTD::uint32_t __scale_A_tmem,
+  _CUDA_VSTD::uint32_t __scale_B_tmem,
+  bool __enable_input_d)
+{
+  // __kind == kind_mxf4nvf4 (due to parameter type constraint)
+  static_assert(__cta_group == cta_group_1 || __cta_group == cta_group_2, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  _CCCL_IF_CONSTEXPR (__cta_group == cta_group_1)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %6, 0;\n\t"
+      "tcgen05.mma.cta_group::1.kind::mxf4nvf4.block_scale.scale_vec::4X.collector::a::use [%0], %1, %2, %3, [%4], "
+      "[%5], PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(__scale_A_tmem),
+        "r"(__scale_B_tmem),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__cta_group == cta_group_2)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %6, 0;\n\t"
+      "tcgen05.mma.cta_group::2.kind::mxf4nvf4.block_scale.scale_vec::4X.collector::a::use [%0], %1, %2, %3, [%4], "
+      "[%5], PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(__scale_A_tmem),
+        "r"(__scale_B_tmem),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_mma_block_scale_vec_4x_collector_a_use_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.mma.cta_group.kind.block_scale.scale_vec::1X.collector::a::use [d_tmem], a_desc, b_desc, idesc,
+[scale_A_tmem], [scale_B_tmem], enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+// .kind      = { .kind::mxf8f6f4 }
+// .cta_group = { .cta_group::1, .cta_group::2 }
+template <cuda::ptx::dot_cta_group Cta_Group>
+__device__ static inline void tcgen05_mma_block_scale_vec_1x_tmem_a_collector_a_use(
+  cuda::ptx::kind_mxf8f6f4_t,
+  cuda::ptx::cta_group_t<Cta_Group> cta_group,
+  uint32_t d_tmem,
+  uint64_t a_desc,
+  uint64_t b_desc,
+  uint32_t idesc,
+  uint32_t scale_A_tmem,
+  uint32_t scale_B_tmem,
+  bool enable_input_d);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void
+__cuda_ptx_tcgen05_mma_block_scale_vec_1x_tmem_a_collector_a_use_is_not_supported_before_SM_100a_SM_101a__();
+template <dot_cta_group _Cta_Group>
+_CCCL_DEVICE static inline void tcgen05_mma_block_scale_vec_1x_tmem_a_collector_a_use(
+  kind_mxf8f6f4_t,
+  cta_group_t<_Cta_Group> __cta_group,
+  _CUDA_VSTD::uint32_t __d_tmem,
+  _CUDA_VSTD::uint64_t __a_desc,
+  _CUDA_VSTD::uint64_t __b_desc,
+  _CUDA_VSTD::uint32_t __idesc,
+  _CUDA_VSTD::uint32_t __scale_A_tmem,
+  _CUDA_VSTD::uint32_t __scale_B_tmem,
+  bool __enable_input_d)
+{
+  // __kind == kind_mxf8f6f4 (due to parameter type constraint)
+  static_assert(__cta_group == cta_group_1 || __cta_group == cta_group_2, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  _CCCL_IF_CONSTEXPR (__cta_group == cta_group_1)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %6, 0;\n\t"
+      "tcgen05.mma.cta_group::1.kind::mxf8f6f4.block_scale.scale_vec::1X.collector::a::use [%0], %1, %2, %3, [%4], "
+      "[%5], PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(__scale_A_tmem),
+        "r"(__scale_B_tmem),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__cta_group == cta_group_2)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %6, 0;\n\t"
+      "tcgen05.mma.cta_group::2.kind::mxf8f6f4.block_scale.scale_vec::1X.collector::a::use [%0], %1, %2, %3, [%4], "
+      "[%5], PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(__scale_A_tmem),
+        "r"(__scale_B_tmem),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_mma_block_scale_vec_1x_tmem_a_collector_a_use_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.mma.cta_group.kind.block_scale.scale_vec::2X.collector::a::use [d_tmem], a_desc, b_desc, idesc,
+[scale_A_tmem], [scale_B_tmem], enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+// .kind      = { .kind::mxf4, .kind::mxf4nvf4 }
+// .cta_group = { .cta_group::1, .cta_group::2 }
+template <cuda::ptx::dot_kind Kind, cuda::ptx::dot_cta_group Cta_Group>
+__device__ static inline void tcgen05_mma_block_scale_vec_2_tmem_a_collector_a_use(
+  cuda::ptx::kind_t<Kind> kind,
+  cuda::ptx::cta_group_t<Cta_Group> cta_group,
+  uint32_t d_tmem,
+  uint64_t a_desc,
+  uint64_t b_desc,
+  uint32_t idesc,
+  uint32_t scale_A_tmem,
+  uint32_t scale_B_tmem,
+  bool enable_input_d);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void
+__cuda_ptx_tcgen05_mma_block_scale_vec_2_tmem_a_collector_a_use_is_not_supported_before_SM_100a_SM_101a__();
+template <dot_kind _Kind, dot_cta_group _Cta_Group>
+_CCCL_DEVICE static inline void tcgen05_mma_block_scale_vec_2_tmem_a_collector_a_use(
+  kind_t<_Kind> __kind,
+  cta_group_t<_Cta_Group> __cta_group,
+  _CUDA_VSTD::uint32_t __d_tmem,
+  _CUDA_VSTD::uint64_t __a_desc,
+  _CUDA_VSTD::uint64_t __b_desc,
+  _CUDA_VSTD::uint32_t __idesc,
+  _CUDA_VSTD::uint32_t __scale_A_tmem,
+  _CUDA_VSTD::uint32_t __scale_B_tmem,
+  bool __enable_input_d)
+{
+  static_assert(__kind == kind_mxf4 || __kind == kind_mxf4nvf4, "");
+  static_assert(__cta_group == cta_group_1 || __cta_group == cta_group_2, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  _CCCL_IF_CONSTEXPR (__kind == kind_mxf4 && __cta_group == cta_group_1)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %6, 0;\n\t"
+      "tcgen05.mma.cta_group::1.kind::mxf4.block_scale.scale_vec::2X.collector::a::use [%0], %1, %2, %3, [%4], [%5], "
+      "PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(__scale_A_tmem),
+        "r"(__scale_B_tmem),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_mxf4 && __cta_group == cta_group_2)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %6, 0;\n\t"
+      "tcgen05.mma.cta_group::2.kind::mxf4.block_scale.scale_vec::2X.collector::a::use [%0], %1, %2, %3, [%4], [%5], "
+      "PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(__scale_A_tmem),
+        "r"(__scale_B_tmem),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_mxf4nvf4 && __cta_group == cta_group_1)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %6, 0;\n\t"
+      "tcgen05.mma.cta_group::1.kind::mxf4nvf4.block_scale.scale_vec::2X.collector::a::use [%0], %1, %2, %3, [%4], "
+      "[%5], PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(__scale_A_tmem),
+        "r"(__scale_B_tmem),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_mxf4nvf4 && __cta_group == cta_group_2)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %6, 0;\n\t"
+      "tcgen05.mma.cta_group::2.kind::mxf4nvf4.block_scale.scale_vec::2X.collector::a::use [%0], %1, %2, %3, [%4], "
+      "[%5], PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(__scale_A_tmem),
+        "r"(__scale_B_tmem),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_mma_block_scale_vec_2_tmem_a_collector_a_use_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.mma.cta_group.kind.block_scale.scale_vec::4X.collector::a::use [d_tmem], a_desc, b_desc, idesc,
+[scale_A_tmem], [scale_B_tmem], enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+// .kind      = { .kind::mxf4nvf4 }
+// .cta_group = { .cta_group::1, .cta_group::2 }
+template <cuda::ptx::dot_cta_group Cta_Group>
+__device__ static inline void tcgen05_mma_block_scale_vec_4x_tmem_a_collector_a_use(
+  cuda::ptx::kind_mxf4nvf4_t,
+  cuda::ptx::cta_group_t<Cta_Group> cta_group,
+  uint32_t d_tmem,
+  uint64_t a_desc,
+  uint64_t b_desc,
+  uint32_t idesc,
+  uint32_t scale_A_tmem,
+  uint32_t scale_B_tmem,
+  bool enable_input_d);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void
+__cuda_ptx_tcgen05_mma_block_scale_vec_4x_tmem_a_collector_a_use_is_not_supported_before_SM_100a_SM_101a__();
+template <dot_cta_group _Cta_Group>
+_CCCL_DEVICE static inline void tcgen05_mma_block_scale_vec_4x_tmem_a_collector_a_use(
+  kind_mxf4nvf4_t,
+  cta_group_t<_Cta_Group> __cta_group,
+  _CUDA_VSTD::uint32_t __d_tmem,
+  _CUDA_VSTD::uint64_t __a_desc,
+  _CUDA_VSTD::uint64_t __b_desc,
+  _CUDA_VSTD::uint32_t __idesc,
+  _CUDA_VSTD::uint32_t __scale_A_tmem,
+  _CUDA_VSTD::uint32_t __scale_B_tmem,
+  bool __enable_input_d)
+{
+  // __kind == kind_mxf4nvf4 (due to parameter type constraint)
+  static_assert(__cta_group == cta_group_1 || __cta_group == cta_group_2, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  _CCCL_IF_CONSTEXPR (__cta_group == cta_group_1)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %6, 0;\n\t"
+      "tcgen05.mma.cta_group::1.kind::mxf4nvf4.block_scale.scale_vec::4X.collector::a::use [%0], %1, %2, %3, [%4], "
+      "[%5], PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(__scale_A_tmem),
+        "r"(__scale_B_tmem),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__cta_group == cta_group_2)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %6, 0;\n\t"
+      "tcgen05.mma.cta_group::2.kind::mxf4nvf4.block_scale.scale_vec::4X.collector::a::use [%0], %1, %2, %3, [%4], "
+      "[%5], PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(__scale_A_tmem),
+        "r"(__scale_B_tmem),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_mma_block_scale_vec_4x_tmem_a_collector_a_use_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.mma.cta_group.kind.block_scale.scale_vec::1X.collector::a::lastuse [d_tmem], a_desc, b_desc, idesc,
+[scale_A_tmem], [scale_B_tmem], enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+// .kind      = { .kind::mxf8f6f4 }
+// .cta_group = { .cta_group::1, .cta_group::2 }
+template <cuda::ptx::dot_cta_group Cta_Group>
+__device__ static inline void tcgen05_mma_block_scale_vec_1x_collector_a_lastuse(
+  cuda::ptx::kind_mxf8f6f4_t,
+  cuda::ptx::cta_group_t<Cta_Group> cta_group,
+  uint32_t d_tmem,
+  uint64_t a_desc,
+  uint64_t b_desc,
+  uint32_t idesc,
+  uint32_t scale_A_tmem,
+  uint32_t scale_B_tmem,
+  bool enable_input_d);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void
+__cuda_ptx_tcgen05_mma_block_scale_vec_1x_collector_a_lastuse_is_not_supported_before_SM_100a_SM_101a__();
+template <dot_cta_group _Cta_Group>
+_CCCL_DEVICE static inline void tcgen05_mma_block_scale_vec_1x_collector_a_lastuse(
+  kind_mxf8f6f4_t,
+  cta_group_t<_Cta_Group> __cta_group,
+  _CUDA_VSTD::uint32_t __d_tmem,
+  _CUDA_VSTD::uint64_t __a_desc,
+  _CUDA_VSTD::uint64_t __b_desc,
+  _CUDA_VSTD::uint32_t __idesc,
+  _CUDA_VSTD::uint32_t __scale_A_tmem,
+  _CUDA_VSTD::uint32_t __scale_B_tmem,
+  bool __enable_input_d)
+{
+  // __kind == kind_mxf8f6f4 (due to parameter type constraint)
+  static_assert(__cta_group == cta_group_1 || __cta_group == cta_group_2, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  _CCCL_IF_CONSTEXPR (__cta_group == cta_group_1)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %6, 0;\n\t"
+      "tcgen05.mma.cta_group::1.kind::mxf8f6f4.block_scale.scale_vec::1X.collector::a::lastuse [%0], %1, %2, %3, [%4], "
+      "[%5], PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(__scale_A_tmem),
+        "r"(__scale_B_tmem),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__cta_group == cta_group_2)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %6, 0;\n\t"
+      "tcgen05.mma.cta_group::2.kind::mxf8f6f4.block_scale.scale_vec::1X.collector::a::lastuse [%0], %1, %2, %3, [%4], "
+      "[%5], PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(__scale_A_tmem),
+        "r"(__scale_B_tmem),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_mma_block_scale_vec_1x_collector_a_lastuse_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.mma.cta_group.kind.block_scale.scale_vec::2X.collector::a::lastuse [d_tmem], a_desc, b_desc, idesc,
+[scale_A_tmem], [scale_B_tmem], enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+// .kind      = { .kind::mxf4, .kind::mxf4nvf4 }
+// .cta_group = { .cta_group::1, .cta_group::2 }
+template <cuda::ptx::dot_kind Kind, cuda::ptx::dot_cta_group Cta_Group>
+__device__ static inline void tcgen05_mma_block_scale_vec_2x_collector_a_lastuse(
+  cuda::ptx::kind_t<Kind> kind,
+  cuda::ptx::cta_group_t<Cta_Group> cta_group,
+  uint32_t d_tmem,
+  uint64_t a_desc,
+  uint64_t b_desc,
+  uint32_t idesc,
+  uint32_t scale_A_tmem,
+  uint32_t scale_B_tmem,
+  bool enable_input_d);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void
+__cuda_ptx_tcgen05_mma_block_scale_vec_2x_collector_a_lastuse_is_not_supported_before_SM_100a_SM_101a__();
+template <dot_kind _Kind, dot_cta_group _Cta_Group>
+_CCCL_DEVICE static inline void tcgen05_mma_block_scale_vec_2x_collector_a_lastuse(
+  kind_t<_Kind> __kind,
+  cta_group_t<_Cta_Group> __cta_group,
+  _CUDA_VSTD::uint32_t __d_tmem,
+  _CUDA_VSTD::uint64_t __a_desc,
+  _CUDA_VSTD::uint64_t __b_desc,
+  _CUDA_VSTD::uint32_t __idesc,
+  _CUDA_VSTD::uint32_t __scale_A_tmem,
+  _CUDA_VSTD::uint32_t __scale_B_tmem,
+  bool __enable_input_d)
+{
+  static_assert(__kind == kind_mxf4 || __kind == kind_mxf4nvf4, "");
+  static_assert(__cta_group == cta_group_1 || __cta_group == cta_group_2, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  _CCCL_IF_CONSTEXPR (__kind == kind_mxf4 && __cta_group == cta_group_1)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %6, 0;\n\t"
+      "tcgen05.mma.cta_group::1.kind::mxf4.block_scale.scale_vec::2X.collector::a::lastuse [%0], %1, %2, %3, [%4], "
+      "[%5], PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(__scale_A_tmem),
+        "r"(__scale_B_tmem),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_mxf4 && __cta_group == cta_group_2)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %6, 0;\n\t"
+      "tcgen05.mma.cta_group::2.kind::mxf4.block_scale.scale_vec::2X.collector::a::lastuse [%0], %1, %2, %3, [%4], "
+      "[%5], PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(__scale_A_tmem),
+        "r"(__scale_B_tmem),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_mxf4nvf4 && __cta_group == cta_group_1)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %6, 0;\n\t"
+      "tcgen05.mma.cta_group::1.kind::mxf4nvf4.block_scale.scale_vec::2X.collector::a::lastuse [%0], %1, %2, %3, [%4], "
+      "[%5], PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(__scale_A_tmem),
+        "r"(__scale_B_tmem),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_mxf4nvf4 && __cta_group == cta_group_2)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %6, 0;\n\t"
+      "tcgen05.mma.cta_group::2.kind::mxf4nvf4.block_scale.scale_vec::2X.collector::a::lastuse [%0], %1, %2, %3, [%4], "
+      "[%5], PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(__scale_A_tmem),
+        "r"(__scale_B_tmem),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_mma_block_scale_vec_2x_collector_a_lastuse_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.mma.cta_group.kind.block_scale.scale_vec::4X.collector::a::lastuse [d_tmem], a_desc, b_desc, idesc,
+[scale_A_tmem], [scale_B_tmem], enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+// .kind      = { .kind::mxf4nvf4 }
+// .cta_group = { .cta_group::1, .cta_group::2 }
+template <cuda::ptx::dot_cta_group Cta_Group>
+__device__ static inline void tcgen05_mma_block_scale_vec_4x_collector_a_lastuse(
+  cuda::ptx::kind_mxf4nvf4_t,
+  cuda::ptx::cta_group_t<Cta_Group> cta_group,
+  uint32_t d_tmem,
+  uint64_t a_desc,
+  uint64_t b_desc,
+  uint32_t idesc,
+  uint32_t scale_A_tmem,
+  uint32_t scale_B_tmem,
+  bool enable_input_d);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void
+__cuda_ptx_tcgen05_mma_block_scale_vec_4x_collector_a_lastuse_is_not_supported_before_SM_100a_SM_101a__();
+template <dot_cta_group _Cta_Group>
+_CCCL_DEVICE static inline void tcgen05_mma_block_scale_vec_4x_collector_a_lastuse(
+  kind_mxf4nvf4_t,
+  cta_group_t<_Cta_Group> __cta_group,
+  _CUDA_VSTD::uint32_t __d_tmem,
+  _CUDA_VSTD::uint64_t __a_desc,
+  _CUDA_VSTD::uint64_t __b_desc,
+  _CUDA_VSTD::uint32_t __idesc,
+  _CUDA_VSTD::uint32_t __scale_A_tmem,
+  _CUDA_VSTD::uint32_t __scale_B_tmem,
+  bool __enable_input_d)
+{
+  // __kind == kind_mxf4nvf4 (due to parameter type constraint)
+  static_assert(__cta_group == cta_group_1 || __cta_group == cta_group_2, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  _CCCL_IF_CONSTEXPR (__cta_group == cta_group_1)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %6, 0;\n\t"
+      "tcgen05.mma.cta_group::1.kind::mxf4nvf4.block_scale.scale_vec::4X.collector::a::lastuse [%0], %1, %2, %3, [%4], "
+      "[%5], PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(__scale_A_tmem),
+        "r"(__scale_B_tmem),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__cta_group == cta_group_2)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %6, 0;\n\t"
+      "tcgen05.mma.cta_group::2.kind::mxf4nvf4.block_scale.scale_vec::4X.collector::a::lastuse [%0], %1, %2, %3, [%4], "
+      "[%5], PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(__scale_A_tmem),
+        "r"(__scale_B_tmem),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_mma_block_scale_vec_4x_collector_a_lastuse_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.mma.cta_group.kind.block_scale.scale_vec::1X.collector::a::lastuse [d_tmem], a_desc, b_desc, idesc,
+[scale_A_tmem], [scale_B_tmem], enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+// .kind      = { .kind::mxf8f6f4 }
+// .cta_group = { .cta_group::1, .cta_group::2 }
+template <cuda::ptx::dot_cta_group Cta_Group>
+__device__ static inline void tcgen05_mma_block_scale_vec_1x_tmem_a_collector_a_lastuse(
+  cuda::ptx::kind_mxf8f6f4_t,
+  cuda::ptx::cta_group_t<Cta_Group> cta_group,
+  uint32_t d_tmem,
+  uint64_t a_desc,
+  uint64_t b_desc,
+  uint32_t idesc,
+  uint32_t scale_A_tmem,
+  uint32_t scale_B_tmem,
+  bool enable_input_d);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void
+__cuda_ptx_tcgen05_mma_block_scale_vec_1x_tmem_a_collector_a_lastuse_is_not_supported_before_SM_100a_SM_101a__();
+template <dot_cta_group _Cta_Group>
+_CCCL_DEVICE static inline void tcgen05_mma_block_scale_vec_1x_tmem_a_collector_a_lastuse(
+  kind_mxf8f6f4_t,
+  cta_group_t<_Cta_Group> __cta_group,
+  _CUDA_VSTD::uint32_t __d_tmem,
+  _CUDA_VSTD::uint64_t __a_desc,
+  _CUDA_VSTD::uint64_t __b_desc,
+  _CUDA_VSTD::uint32_t __idesc,
+  _CUDA_VSTD::uint32_t __scale_A_tmem,
+  _CUDA_VSTD::uint32_t __scale_B_tmem,
+  bool __enable_input_d)
+{
+  // __kind == kind_mxf8f6f4 (due to parameter type constraint)
+  static_assert(__cta_group == cta_group_1 || __cta_group == cta_group_2, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  _CCCL_IF_CONSTEXPR (__cta_group == cta_group_1)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %6, 0;\n\t"
+      "tcgen05.mma.cta_group::1.kind::mxf8f6f4.block_scale.scale_vec::1X.collector::a::lastuse [%0], %1, %2, %3, [%4], "
+      "[%5], PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(__scale_A_tmem),
+        "r"(__scale_B_tmem),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__cta_group == cta_group_2)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %6, 0;\n\t"
+      "tcgen05.mma.cta_group::2.kind::mxf8f6f4.block_scale.scale_vec::1X.collector::a::lastuse [%0], %1, %2, %3, [%4], "
+      "[%5], PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(__scale_A_tmem),
+        "r"(__scale_B_tmem),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_mma_block_scale_vec_1x_tmem_a_collector_a_lastuse_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.mma.cta_group.kind.block_scale.scale_vec::2X.collector::a::lastuse [d_tmem], a_desc, b_desc, idesc,
+[scale_A_tmem], [scale_B_tmem], enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+// .kind      = { .kind::mxf4, .kind::mxf4nvf4 }
+// .cta_group = { .cta_group::1, .cta_group::2 }
+template <cuda::ptx::dot_kind Kind, cuda::ptx::dot_cta_group Cta_Group>
+__device__ static inline void tcgen05_mma_block_scale_vec_2_tmem_a_collector_a_lastuse(
+  cuda::ptx::kind_t<Kind> kind,
+  cuda::ptx::cta_group_t<Cta_Group> cta_group,
+  uint32_t d_tmem,
+  uint64_t a_desc,
+  uint64_t b_desc,
+  uint32_t idesc,
+  uint32_t scale_A_tmem,
+  uint32_t scale_B_tmem,
+  bool enable_input_d);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void
+__cuda_ptx_tcgen05_mma_block_scale_vec_2_tmem_a_collector_a_lastuse_is_not_supported_before_SM_100a_SM_101a__();
+template <dot_kind _Kind, dot_cta_group _Cta_Group>
+_CCCL_DEVICE static inline void tcgen05_mma_block_scale_vec_2_tmem_a_collector_a_lastuse(
+  kind_t<_Kind> __kind,
+  cta_group_t<_Cta_Group> __cta_group,
+  _CUDA_VSTD::uint32_t __d_tmem,
+  _CUDA_VSTD::uint64_t __a_desc,
+  _CUDA_VSTD::uint64_t __b_desc,
+  _CUDA_VSTD::uint32_t __idesc,
+  _CUDA_VSTD::uint32_t __scale_A_tmem,
+  _CUDA_VSTD::uint32_t __scale_B_tmem,
+  bool __enable_input_d)
+{
+  static_assert(__kind == kind_mxf4 || __kind == kind_mxf4nvf4, "");
+  static_assert(__cta_group == cta_group_1 || __cta_group == cta_group_2, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  _CCCL_IF_CONSTEXPR (__kind == kind_mxf4 && __cta_group == cta_group_1)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %6, 0;\n\t"
+      "tcgen05.mma.cta_group::1.kind::mxf4.block_scale.scale_vec::2X.collector::a::lastuse [%0], %1, %2, %3, [%4], "
+      "[%5], PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(__scale_A_tmem),
+        "r"(__scale_B_tmem),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_mxf4 && __cta_group == cta_group_2)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %6, 0;\n\t"
+      "tcgen05.mma.cta_group::2.kind::mxf4.block_scale.scale_vec::2X.collector::a::lastuse [%0], %1, %2, %3, [%4], "
+      "[%5], PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(__scale_A_tmem),
+        "r"(__scale_B_tmem),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_mxf4nvf4 && __cta_group == cta_group_1)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %6, 0;\n\t"
+      "tcgen05.mma.cta_group::1.kind::mxf4nvf4.block_scale.scale_vec::2X.collector::a::lastuse [%0], %1, %2, %3, [%4], "
+      "[%5], PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(__scale_A_tmem),
+        "r"(__scale_B_tmem),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_mxf4nvf4 && __cta_group == cta_group_2)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %6, 0;\n\t"
+      "tcgen05.mma.cta_group::2.kind::mxf4nvf4.block_scale.scale_vec::2X.collector::a::lastuse [%0], %1, %2, %3, [%4], "
+      "[%5], PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(__scale_A_tmem),
+        "r"(__scale_B_tmem),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_mma_block_scale_vec_2_tmem_a_collector_a_lastuse_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.mma.cta_group.kind.block_scale.scale_vec::4X.collector::a::lastuse [d_tmem], a_desc, b_desc, idesc,
+[scale_A_tmem], [scale_B_tmem], enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+// .kind      = { .kind::mxf4nvf4 }
+// .cta_group = { .cta_group::1, .cta_group::2 }
+template <cuda::ptx::dot_cta_group Cta_Group>
+__device__ static inline void tcgen05_mma_block_scale_vec_4x_tmem_a_collector_a_lastuse(
+  cuda::ptx::kind_mxf4nvf4_t,
+  cuda::ptx::cta_group_t<Cta_Group> cta_group,
+  uint32_t d_tmem,
+  uint64_t a_desc,
+  uint64_t b_desc,
+  uint32_t idesc,
+  uint32_t scale_A_tmem,
+  uint32_t scale_B_tmem,
+  bool enable_input_d);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void
+__cuda_ptx_tcgen05_mma_block_scale_vec_4x_tmem_a_collector_a_lastuse_is_not_supported_before_SM_100a_SM_101a__();
+template <dot_cta_group _Cta_Group>
+_CCCL_DEVICE static inline void tcgen05_mma_block_scale_vec_4x_tmem_a_collector_a_lastuse(
+  kind_mxf4nvf4_t,
+  cta_group_t<_Cta_Group> __cta_group,
+  _CUDA_VSTD::uint32_t __d_tmem,
+  _CUDA_VSTD::uint64_t __a_desc,
+  _CUDA_VSTD::uint64_t __b_desc,
+  _CUDA_VSTD::uint32_t __idesc,
+  _CUDA_VSTD::uint32_t __scale_A_tmem,
+  _CUDA_VSTD::uint32_t __scale_B_tmem,
+  bool __enable_input_d)
+{
+  // __kind == kind_mxf4nvf4 (due to parameter type constraint)
+  static_assert(__cta_group == cta_group_1 || __cta_group == cta_group_2, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  _CCCL_IF_CONSTEXPR (__cta_group == cta_group_1)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %6, 0;\n\t"
+      "tcgen05.mma.cta_group::1.kind::mxf4nvf4.block_scale.scale_vec::4X.collector::a::lastuse [%0], %1, %2, %3, [%4], "
+      "[%5], PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(__scale_A_tmem),
+        "r"(__scale_B_tmem),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__cta_group == cta_group_2)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %6, 0;\n\t"
+      "tcgen05.mma.cta_group::2.kind::mxf4nvf4.block_scale.scale_vec::4X.collector::a::lastuse [%0], %1, %2, %3, [%4], "
+      "[%5], PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(__scale_A_tmem),
+        "r"(__scale_B_tmem),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_mma_block_scale_vec_4x_tmem_a_collector_a_lastuse_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.mma.cta_group.kind.block_scale.scale_vec::1X.collector::a::discard [d_tmem], a_desc, b_desc, idesc,
+[scale_A_tmem], [scale_B_tmem], enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+// .kind      = { .kind::mxf8f6f4 }
+// .cta_group = { .cta_group::1, .cta_group::2 }
+template <cuda::ptx::dot_cta_group Cta_Group>
+__device__ static inline void tcgen05_mma_block_scale_vec_1x_collector_a_discard(
+  cuda::ptx::kind_mxf8f6f4_t,
+  cuda::ptx::cta_group_t<Cta_Group> cta_group,
+  uint32_t d_tmem,
+  uint64_t a_desc,
+  uint64_t b_desc,
+  uint32_t idesc,
+  uint32_t scale_A_tmem,
+  uint32_t scale_B_tmem,
+  bool enable_input_d);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void
+__cuda_ptx_tcgen05_mma_block_scale_vec_1x_collector_a_discard_is_not_supported_before_SM_100a_SM_101a__();
+template <dot_cta_group _Cta_Group>
+_CCCL_DEVICE static inline void tcgen05_mma_block_scale_vec_1x_collector_a_discard(
+  kind_mxf8f6f4_t,
+  cta_group_t<_Cta_Group> __cta_group,
+  _CUDA_VSTD::uint32_t __d_tmem,
+  _CUDA_VSTD::uint64_t __a_desc,
+  _CUDA_VSTD::uint64_t __b_desc,
+  _CUDA_VSTD::uint32_t __idesc,
+  _CUDA_VSTD::uint32_t __scale_A_tmem,
+  _CUDA_VSTD::uint32_t __scale_B_tmem,
+  bool __enable_input_d)
+{
+  // __kind == kind_mxf8f6f4 (due to parameter type constraint)
+  static_assert(__cta_group == cta_group_1 || __cta_group == cta_group_2, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  _CCCL_IF_CONSTEXPR (__cta_group == cta_group_1)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %6, 0;\n\t"
+      "tcgen05.mma.cta_group::1.kind::mxf8f6f4.block_scale.scale_vec::1X.collector::a::discard [%0], %1, %2, %3, [%4], "
+      "[%5], PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(__scale_A_tmem),
+        "r"(__scale_B_tmem),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__cta_group == cta_group_2)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %6, 0;\n\t"
+      "tcgen05.mma.cta_group::2.kind::mxf8f6f4.block_scale.scale_vec::1X.collector::a::discard [%0], %1, %2, %3, [%4], "
+      "[%5], PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(__scale_A_tmem),
+        "r"(__scale_B_tmem),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_mma_block_scale_vec_1x_collector_a_discard_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.mma.cta_group.kind.block_scale.scale_vec::2X.collector::a::discard [d_tmem], a_desc, b_desc, idesc,
+[scale_A_tmem], [scale_B_tmem], enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+// .kind      = { .kind::mxf4, .kind::mxf4nvf4 }
+// .cta_group = { .cta_group::1, .cta_group::2 }
+template <cuda::ptx::dot_kind Kind, cuda::ptx::dot_cta_group Cta_Group>
+__device__ static inline void tcgen05_mma_block_scale_vec_2x_collector_a_discard(
+  cuda::ptx::kind_t<Kind> kind,
+  cuda::ptx::cta_group_t<Cta_Group> cta_group,
+  uint32_t d_tmem,
+  uint64_t a_desc,
+  uint64_t b_desc,
+  uint32_t idesc,
+  uint32_t scale_A_tmem,
+  uint32_t scale_B_tmem,
+  bool enable_input_d);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void
+__cuda_ptx_tcgen05_mma_block_scale_vec_2x_collector_a_discard_is_not_supported_before_SM_100a_SM_101a__();
+template <dot_kind _Kind, dot_cta_group _Cta_Group>
+_CCCL_DEVICE static inline void tcgen05_mma_block_scale_vec_2x_collector_a_discard(
+  kind_t<_Kind> __kind,
+  cta_group_t<_Cta_Group> __cta_group,
+  _CUDA_VSTD::uint32_t __d_tmem,
+  _CUDA_VSTD::uint64_t __a_desc,
+  _CUDA_VSTD::uint64_t __b_desc,
+  _CUDA_VSTD::uint32_t __idesc,
+  _CUDA_VSTD::uint32_t __scale_A_tmem,
+  _CUDA_VSTD::uint32_t __scale_B_tmem,
+  bool __enable_input_d)
+{
+  static_assert(__kind == kind_mxf4 || __kind == kind_mxf4nvf4, "");
+  static_assert(__cta_group == cta_group_1 || __cta_group == cta_group_2, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  _CCCL_IF_CONSTEXPR (__kind == kind_mxf4 && __cta_group == cta_group_1)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %6, 0;\n\t"
+      "tcgen05.mma.cta_group::1.kind::mxf4.block_scale.scale_vec::2X.collector::a::discard [%0], %1, %2, %3, [%4], "
+      "[%5], PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(__scale_A_tmem),
+        "r"(__scale_B_tmem),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_mxf4 && __cta_group == cta_group_2)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %6, 0;\n\t"
+      "tcgen05.mma.cta_group::2.kind::mxf4.block_scale.scale_vec::2X.collector::a::discard [%0], %1, %2, %3, [%4], "
+      "[%5], PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(__scale_A_tmem),
+        "r"(__scale_B_tmem),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_mxf4nvf4 && __cta_group == cta_group_1)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %6, 0;\n\t"
+      "tcgen05.mma.cta_group::1.kind::mxf4nvf4.block_scale.scale_vec::2X.collector::a::discard [%0], %1, %2, %3, [%4], "
+      "[%5], PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(__scale_A_tmem),
+        "r"(__scale_B_tmem),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_mxf4nvf4 && __cta_group == cta_group_2)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %6, 0;\n\t"
+      "tcgen05.mma.cta_group::2.kind::mxf4nvf4.block_scale.scale_vec::2X.collector::a::discard [%0], %1, %2, %3, [%4], "
+      "[%5], PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(__scale_A_tmem),
+        "r"(__scale_B_tmem),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_mma_block_scale_vec_2x_collector_a_discard_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.mma.cta_group.kind.block_scale.scale_vec::4X.collector::a::discard [d_tmem], a_desc, b_desc, idesc,
+[scale_A_tmem], [scale_B_tmem], enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+// .kind      = { .kind::mxf4nvf4 }
+// .cta_group = { .cta_group::1, .cta_group::2 }
+template <cuda::ptx::dot_cta_group Cta_Group>
+__device__ static inline void tcgen05_mma_block_scale_vec_4x_collector_a_discard(
+  cuda::ptx::kind_mxf4nvf4_t,
+  cuda::ptx::cta_group_t<Cta_Group> cta_group,
+  uint32_t d_tmem,
+  uint64_t a_desc,
+  uint64_t b_desc,
+  uint32_t idesc,
+  uint32_t scale_A_tmem,
+  uint32_t scale_B_tmem,
+  bool enable_input_d);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void
+__cuda_ptx_tcgen05_mma_block_scale_vec_4x_collector_a_discard_is_not_supported_before_SM_100a_SM_101a__();
+template <dot_cta_group _Cta_Group>
+_CCCL_DEVICE static inline void tcgen05_mma_block_scale_vec_4x_collector_a_discard(
+  kind_mxf4nvf4_t,
+  cta_group_t<_Cta_Group> __cta_group,
+  _CUDA_VSTD::uint32_t __d_tmem,
+  _CUDA_VSTD::uint64_t __a_desc,
+  _CUDA_VSTD::uint64_t __b_desc,
+  _CUDA_VSTD::uint32_t __idesc,
+  _CUDA_VSTD::uint32_t __scale_A_tmem,
+  _CUDA_VSTD::uint32_t __scale_B_tmem,
+  bool __enable_input_d)
+{
+  // __kind == kind_mxf4nvf4 (due to parameter type constraint)
+  static_assert(__cta_group == cta_group_1 || __cta_group == cta_group_2, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  _CCCL_IF_CONSTEXPR (__cta_group == cta_group_1)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %6, 0;\n\t"
+      "tcgen05.mma.cta_group::1.kind::mxf4nvf4.block_scale.scale_vec::4X.collector::a::discard [%0], %1, %2, %3, [%4], "
+      "[%5], PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(__scale_A_tmem),
+        "r"(__scale_B_tmem),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__cta_group == cta_group_2)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %6, 0;\n\t"
+      "tcgen05.mma.cta_group::2.kind::mxf4nvf4.block_scale.scale_vec::4X.collector::a::discard [%0], %1, %2, %3, [%4], "
+      "[%5], PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(__scale_A_tmem),
+        "r"(__scale_B_tmem),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_mma_block_scale_vec_4x_collector_a_discard_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.mma.cta_group.kind.block_scale.scale_vec::1X.collector::a::discard [d_tmem], a_desc, b_desc, idesc,
+[scale_A_tmem], [scale_B_tmem], enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+// .kind      = { .kind::mxf8f6f4 }
+// .cta_group = { .cta_group::1, .cta_group::2 }
+template <cuda::ptx::dot_cta_group Cta_Group>
+__device__ static inline void tcgen05_mma_block_scale_vec_1x_tmem_a_collector_a_discard(
+  cuda::ptx::kind_mxf8f6f4_t,
+  cuda::ptx::cta_group_t<Cta_Group> cta_group,
+  uint32_t d_tmem,
+  uint64_t a_desc,
+  uint64_t b_desc,
+  uint32_t idesc,
+  uint32_t scale_A_tmem,
+  uint32_t scale_B_tmem,
+  bool enable_input_d);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void
+__cuda_ptx_tcgen05_mma_block_scale_vec_1x_tmem_a_collector_a_discard_is_not_supported_before_SM_100a_SM_101a__();
+template <dot_cta_group _Cta_Group>
+_CCCL_DEVICE static inline void tcgen05_mma_block_scale_vec_1x_tmem_a_collector_a_discard(
+  kind_mxf8f6f4_t,
+  cta_group_t<_Cta_Group> __cta_group,
+  _CUDA_VSTD::uint32_t __d_tmem,
+  _CUDA_VSTD::uint64_t __a_desc,
+  _CUDA_VSTD::uint64_t __b_desc,
+  _CUDA_VSTD::uint32_t __idesc,
+  _CUDA_VSTD::uint32_t __scale_A_tmem,
+  _CUDA_VSTD::uint32_t __scale_B_tmem,
+  bool __enable_input_d)
+{
+  // __kind == kind_mxf8f6f4 (due to parameter type constraint)
+  static_assert(__cta_group == cta_group_1 || __cta_group == cta_group_2, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  _CCCL_IF_CONSTEXPR (__cta_group == cta_group_1)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %6, 0;\n\t"
+      "tcgen05.mma.cta_group::1.kind::mxf8f6f4.block_scale.scale_vec::1X.collector::a::discard [%0], %1, %2, %3, [%4], "
+      "[%5], PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(__scale_A_tmem),
+        "r"(__scale_B_tmem),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__cta_group == cta_group_2)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %6, 0;\n\t"
+      "tcgen05.mma.cta_group::2.kind::mxf8f6f4.block_scale.scale_vec::1X.collector::a::discard [%0], %1, %2, %3, [%4], "
+      "[%5], PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(__scale_A_tmem),
+        "r"(__scale_B_tmem),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_mma_block_scale_vec_1x_tmem_a_collector_a_discard_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.mma.cta_group.kind.block_scale.scale_vec::2X.collector::a::discard [d_tmem], a_desc, b_desc, idesc,
+[scale_A_tmem], [scale_B_tmem], enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+// .kind      = { .kind::mxf4, .kind::mxf4nvf4 }
+// .cta_group = { .cta_group::1, .cta_group::2 }
+template <cuda::ptx::dot_kind Kind, cuda::ptx::dot_cta_group Cta_Group>
+__device__ static inline void tcgen05_mma_block_scale_vec_2_tmem_a_collector_a_discard(
+  cuda::ptx::kind_t<Kind> kind,
+  cuda::ptx::cta_group_t<Cta_Group> cta_group,
+  uint32_t d_tmem,
+  uint64_t a_desc,
+  uint64_t b_desc,
+  uint32_t idesc,
+  uint32_t scale_A_tmem,
+  uint32_t scale_B_tmem,
+  bool enable_input_d);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void
+__cuda_ptx_tcgen05_mma_block_scale_vec_2_tmem_a_collector_a_discard_is_not_supported_before_SM_100a_SM_101a__();
+template <dot_kind _Kind, dot_cta_group _Cta_Group>
+_CCCL_DEVICE static inline void tcgen05_mma_block_scale_vec_2_tmem_a_collector_a_discard(
+  kind_t<_Kind> __kind,
+  cta_group_t<_Cta_Group> __cta_group,
+  _CUDA_VSTD::uint32_t __d_tmem,
+  _CUDA_VSTD::uint64_t __a_desc,
+  _CUDA_VSTD::uint64_t __b_desc,
+  _CUDA_VSTD::uint32_t __idesc,
+  _CUDA_VSTD::uint32_t __scale_A_tmem,
+  _CUDA_VSTD::uint32_t __scale_B_tmem,
+  bool __enable_input_d)
+{
+  static_assert(__kind == kind_mxf4 || __kind == kind_mxf4nvf4, "");
+  static_assert(__cta_group == cta_group_1 || __cta_group == cta_group_2, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  _CCCL_IF_CONSTEXPR (__kind == kind_mxf4 && __cta_group == cta_group_1)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %6, 0;\n\t"
+      "tcgen05.mma.cta_group::1.kind::mxf4.block_scale.scale_vec::2X.collector::a::discard [%0], %1, %2, %3, [%4], "
+      "[%5], PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(__scale_A_tmem),
+        "r"(__scale_B_tmem),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_mxf4 && __cta_group == cta_group_2)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %6, 0;\n\t"
+      "tcgen05.mma.cta_group::2.kind::mxf4.block_scale.scale_vec::2X.collector::a::discard [%0], %1, %2, %3, [%4], "
+      "[%5], PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(__scale_A_tmem),
+        "r"(__scale_B_tmem),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_mxf4nvf4 && __cta_group == cta_group_1)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %6, 0;\n\t"
+      "tcgen05.mma.cta_group::1.kind::mxf4nvf4.block_scale.scale_vec::2X.collector::a::discard [%0], %1, %2, %3, [%4], "
+      "[%5], PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(__scale_A_tmem),
+        "r"(__scale_B_tmem),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_mxf4nvf4 && __cta_group == cta_group_2)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %6, 0;\n\t"
+      "tcgen05.mma.cta_group::2.kind::mxf4nvf4.block_scale.scale_vec::2X.collector::a::discard [%0], %1, %2, %3, [%4], "
+      "[%5], PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(__scale_A_tmem),
+        "r"(__scale_B_tmem),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_mma_block_scale_vec_2_tmem_a_collector_a_discard_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.mma.cta_group.kind.block_scale.scale_vec::4X.collector::a::discard [d_tmem], a_desc, b_desc, idesc,
+[scale_A_tmem], [scale_B_tmem], enable_input_d; // PTX ISA 86, SM_100a, SM_101a
+// .kind      = { .kind::mxf4nvf4 }
+// .cta_group = { .cta_group::1, .cta_group::2 }
+template <cuda::ptx::dot_cta_group Cta_Group>
+__device__ static inline void tcgen05_mma_block_scale_vec_4x_tmem_a_collector_a_discard(
+  cuda::ptx::kind_mxf4nvf4_t,
+  cuda::ptx::cta_group_t<Cta_Group> cta_group,
+  uint32_t d_tmem,
+  uint64_t a_desc,
+  uint64_t b_desc,
+  uint32_t idesc,
+  uint32_t scale_A_tmem,
+  uint32_t scale_B_tmem,
+  bool enable_input_d);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void
+__cuda_ptx_tcgen05_mma_block_scale_vec_4x_tmem_a_collector_a_discard_is_not_supported_before_SM_100a_SM_101a__();
+template <dot_cta_group _Cta_Group>
+_CCCL_DEVICE static inline void tcgen05_mma_block_scale_vec_4x_tmem_a_collector_a_discard(
+  kind_mxf4nvf4_t,
+  cta_group_t<_Cta_Group> __cta_group,
+  _CUDA_VSTD::uint32_t __d_tmem,
+  _CUDA_VSTD::uint64_t __a_desc,
+  _CUDA_VSTD::uint64_t __b_desc,
+  _CUDA_VSTD::uint32_t __idesc,
+  _CUDA_VSTD::uint32_t __scale_A_tmem,
+  _CUDA_VSTD::uint32_t __scale_B_tmem,
+  bool __enable_input_d)
+{
+  // __kind == kind_mxf4nvf4 (due to parameter type constraint)
+  static_assert(__cta_group == cta_group_1 || __cta_group == cta_group_2, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  _CCCL_IF_CONSTEXPR (__cta_group == cta_group_1)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %6, 0;\n\t"
+      "tcgen05.mma.cta_group::1.kind::mxf4nvf4.block_scale.scale_vec::4X.collector::a::discard [%0], %1, %2, %3, [%4], "
+      "[%5], PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(__scale_A_tmem),
+        "r"(__scale_B_tmem),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__cta_group == cta_group_2)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %6, 0;\n\t"
+      "tcgen05.mma.cta_group::2.kind::mxf4nvf4.block_scale.scale_vec::4X.collector::a::discard [%0], %1, %2, %3, [%4], "
+      "[%5], PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(__scale_A_tmem),
+        "r"(__scale_B_tmem),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_mma_block_scale_vec_4x_tmem_a_collector_a_discard_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+#endif // _CUDA_PTX_GENERATED_TCGEN05_MMA_H_
diff --git a/libcudacxx/include/cuda/__ptx/instructions/generated/tcgen05_mma_ws.h b/libcudacxx/include/cuda/__ptx/instructions/generated/tcgen05_mma_ws.h
new file mode 100644
index 00000000000..8d09698052d
--- /dev/null
+++ b/libcudacxx/include/cuda/__ptx/instructions/generated/tcgen05_mma_ws.h
@@ -0,0 +1,6438 @@
+// This file was automatically generated. Do not edit.
+
+#ifndef _CUDA_PTX_GENERATED_TCGEN05_MMA_WS_H_
+#define _CUDA_PTX_GENERATED_TCGEN05_MMA_WS_H_
+
+/*
+// tcgen05.mma.ws.cta_group.kind.collector::b0::fill [d_tmem], a_desc, b_desc, idesc, enable_input_d,
+zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_101a
+// .cta_group = { .cta_group::1 }
+// .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+template <cuda::ptx::dot_kind Kind>
+__device__ static inline void tcgen05_mma_ws_collector_b0_fill(
+  cuda::ptx::cta_group_1_t,
+  cuda::ptx::kind_t<Kind> kind,
+  uint32_t d_tmem,
+  uint64_t a_desc,
+  uint64_t b_desc,
+  uint32_t idesc,
+  bool enable_input_d,
+  uint64_t zero_column_mask_desc);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_mma_ws_collector_b0_fill_is_not_supported_before_SM_100a_SM_101a__();
+template <dot_kind _Kind>
+_CCCL_DEVICE static inline void tcgen05_mma_ws_collector_b0_fill(
+  cta_group_1_t,
+  kind_t<_Kind> __kind,
+  _CUDA_VSTD::uint32_t __d_tmem,
+  _CUDA_VSTD::uint64_t __a_desc,
+  _CUDA_VSTD::uint64_t __b_desc,
+  _CUDA_VSTD::uint32_t __idesc,
+  bool __enable_input_d,
+  _CUDA_VSTD::uint64_t __zero_column_mask_desc)
+{
+  // __cta_group == cta_group_1 (due to parameter type constraint)
+  static_assert(__kind == kind_f16 || __kind == kind_tf32 || __kind == kind_f8f6f4 || __kind == kind_i8, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  _CCCL_IF_CONSTEXPR (__kind == kind_f16)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b0::fill [%0], %1, %2, %3, PRED_enable_input_d, %5;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d)),
+        "l"(__zero_column_mask_desc)
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_tf32)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b0::fill [%0], %1, %2, %3, PRED_enable_input_d, %5;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d)),
+        "l"(__zero_column_mask_desc)
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_f8f6f4)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b0::fill [%0], %1, %2, %3, PRED_enable_input_d, %5;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d)),
+        "l"(__zero_column_mask_desc)
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_i8)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b0::fill [%0], %1, %2, %3, PRED_enable_input_d, %5;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d)),
+        "l"(__zero_column_mask_desc)
+      : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_mma_ws_collector_b0_fill_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.mma.ws.cta_group.kind.collector::b0::fill [d_tmem], a_desc, b_desc, idesc, enable_input_d; // PTX ISA 86,
+SM_100a, SM_101a
+// .cta_group = { .cta_group::1 }
+// .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+template <cuda::ptx::dot_kind Kind>
+__device__ static inline void tcgen05_mma_ws_collector_b0_fill(
+  cuda::ptx::cta_group_1_t,
+  cuda::ptx::kind_t<Kind> kind,
+  uint32_t d_tmem,
+  uint64_t a_desc,
+  uint64_t b_desc,
+  uint32_t idesc,
+  bool enable_input_d);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_mma_ws_collector_b0_fill_is_not_supported_before_SM_100a_SM_101a__();
+template <dot_kind _Kind>
+_CCCL_DEVICE static inline void tcgen05_mma_ws_collector_b0_fill(
+  cta_group_1_t,
+  kind_t<_Kind> __kind,
+  _CUDA_VSTD::uint32_t __d_tmem,
+  _CUDA_VSTD::uint64_t __a_desc,
+  _CUDA_VSTD::uint64_t __b_desc,
+  _CUDA_VSTD::uint32_t __idesc,
+  bool __enable_input_d)
+{
+  // __cta_group == cta_group_1 (due to parameter type constraint)
+  static_assert(__kind == kind_f16 || __kind == kind_tf32 || __kind == kind_f8f6f4 || __kind == kind_i8, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  _CCCL_IF_CONSTEXPR (__kind == kind_f16)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b0::fill [%0], %1, %2, %3, PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_tf32)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b0::fill [%0], %1, %2, %3, PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_f8f6f4)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b0::fill [%0], %1, %2, %3, PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_i8)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b0::fill [%0], %1, %2, %3, PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_mma_ws_collector_b0_fill_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.mma.ws.cta_group.kind.collector::b0::fill [d_tmem], [a_tmem], b_desc, idesc, enable_input_d,
+zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_101a
+// .cta_group = { .cta_group::1 }
+// .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+template <cuda::ptx::dot_kind Kind>
+__device__ static inline void tcgen05_mma_ws_tmem_a_collector_b0_fill(
+  cuda::ptx::cta_group_1_t,
+  cuda::ptx::kind_t<Kind> kind,
+  uint32_t d_tmem,
+  uint32_t a_tmem,
+  uint64_t b_desc,
+  uint32_t idesc,
+  bool enable_input_d,
+  uint64_t zero_column_mask_desc);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void
+__cuda_ptx_tcgen05_mma_ws_tmem_a_collector_b0_fill_is_not_supported_before_SM_100a_SM_101a__();
+template <dot_kind _Kind>
+_CCCL_DEVICE static inline void tcgen05_mma_ws_tmem_a_collector_b0_fill(
+  cta_group_1_t,
+  kind_t<_Kind> __kind,
+  _CUDA_VSTD::uint32_t __d_tmem,
+  _CUDA_VSTD::uint32_t __a_tmem,
+  _CUDA_VSTD::uint64_t __b_desc,
+  _CUDA_VSTD::uint32_t __idesc,
+  bool __enable_input_d,
+  _CUDA_VSTD::uint64_t __zero_column_mask_desc)
+{
+  // __cta_group == cta_group_1 (due to parameter type constraint)
+  static_assert(__kind == kind_f16 || __kind == kind_tf32 || __kind == kind_f8f6f4 || __kind == kind_i8, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  _CCCL_IF_CONSTEXPR (__kind == kind_f16)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b0::fill [%0], [%1], %2, %3, PRED_enable_input_d, %5;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "r"(__a_tmem),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d)),
+        "l"(__zero_column_mask_desc)
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_tf32)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b0::fill [%0], [%1], %2, %3, PRED_enable_input_d, %5;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "r"(__a_tmem),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d)),
+        "l"(__zero_column_mask_desc)
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_f8f6f4)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b0::fill [%0], [%1], %2, %3, PRED_enable_input_d, %5;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "r"(__a_tmem),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d)),
+        "l"(__zero_column_mask_desc)
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_i8)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b0::fill [%0], [%1], %2, %3, PRED_enable_input_d, %5;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "r"(__a_tmem),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d)),
+        "l"(__zero_column_mask_desc)
+      : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_mma_ws_tmem_a_collector_b0_fill_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.mma.ws.cta_group.kind.collector::b0::fill [d_tmem], [a_tmem], b_desc, idesc, enable_input_d; // PTX ISA 86,
+SM_100a, SM_101a
+// .cta_group = { .cta_group::1 }
+// .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+template <cuda::ptx::dot_kind Kind>
+__device__ static inline void tcgen05_mma_ws_tmem_a_collector_b0_fill(
+  cuda::ptx::cta_group_1_t,
+  cuda::ptx::kind_t<Kind> kind,
+  uint32_t d_tmem,
+  uint32_t a_tmem,
+  uint64_t b_desc,
+  uint32_t idesc,
+  bool enable_input_d);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void
+__cuda_ptx_tcgen05_mma_ws_tmem_a_collector_b0_fill_is_not_supported_before_SM_100a_SM_101a__();
+template <dot_kind _Kind>
+_CCCL_DEVICE static inline void tcgen05_mma_ws_tmem_a_collector_b0_fill(
+  cta_group_1_t,
+  kind_t<_Kind> __kind,
+  _CUDA_VSTD::uint32_t __d_tmem,
+  _CUDA_VSTD::uint32_t __a_tmem,
+  _CUDA_VSTD::uint64_t __b_desc,
+  _CUDA_VSTD::uint32_t __idesc,
+  bool __enable_input_d)
+{
+  // __cta_group == cta_group_1 (due to parameter type constraint)
+  static_assert(__kind == kind_f16 || __kind == kind_tf32 || __kind == kind_f8f6f4 || __kind == kind_i8, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  _CCCL_IF_CONSTEXPR (__kind == kind_f16)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b0::fill [%0], [%1], %2, %3, PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "r"(__a_tmem),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_tf32)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b0::fill [%0], [%1], %2, %3, PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "r"(__a_tmem),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_f8f6f4)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b0::fill [%0], [%1], %2, %3, PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "r"(__a_tmem),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_i8)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b0::fill [%0], [%1], %2, %3, PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "r"(__a_tmem),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_mma_ws_tmem_a_collector_b0_fill_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.mma.ws.cta_group.kind.collector::b0::use [d_tmem], a_desc, b_desc, idesc, enable_input_d,
+zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_101a
+// .cta_group = { .cta_group::1 }
+// .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+template <cuda::ptx::dot_kind Kind>
+__device__ static inline void tcgen05_mma_ws_collector_b0_use(
+  cuda::ptx::cta_group_1_t,
+  cuda::ptx::kind_t<Kind> kind,
+  uint32_t d_tmem,
+  uint64_t a_desc,
+  uint64_t b_desc,
+  uint32_t idesc,
+  bool enable_input_d,
+  uint64_t zero_column_mask_desc);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_mma_ws_collector_b0_use_is_not_supported_before_SM_100a_SM_101a__();
+template <dot_kind _Kind>
+_CCCL_DEVICE static inline void tcgen05_mma_ws_collector_b0_use(
+  cta_group_1_t,
+  kind_t<_Kind> __kind,
+  _CUDA_VSTD::uint32_t __d_tmem,
+  _CUDA_VSTD::uint64_t __a_desc,
+  _CUDA_VSTD::uint64_t __b_desc,
+  _CUDA_VSTD::uint32_t __idesc,
+  bool __enable_input_d,
+  _CUDA_VSTD::uint64_t __zero_column_mask_desc)
+{
+  // __cta_group == cta_group_1 (due to parameter type constraint)
+  static_assert(__kind == kind_f16 || __kind == kind_tf32 || __kind == kind_f8f6f4 || __kind == kind_i8, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  _CCCL_IF_CONSTEXPR (__kind == kind_f16)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b0::use [%0], %1, %2, %3, PRED_enable_input_d, %5;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d)),
+        "l"(__zero_column_mask_desc)
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_tf32)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b0::use [%0], %1, %2, %3, PRED_enable_input_d, %5;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d)),
+        "l"(__zero_column_mask_desc)
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_f8f6f4)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b0::use [%0], %1, %2, %3, PRED_enable_input_d, %5;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d)),
+        "l"(__zero_column_mask_desc)
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_i8)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b0::use [%0], %1, %2, %3, PRED_enable_input_d, %5;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d)),
+        "l"(__zero_column_mask_desc)
+      : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_mma_ws_collector_b0_use_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.mma.ws.cta_group.kind.collector::b0::use [d_tmem], a_desc, b_desc, idesc, enable_input_d; // PTX ISA 86,
+SM_100a, SM_101a
+// .cta_group = { .cta_group::1 }
+// .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+template <cuda::ptx::dot_kind Kind>
+__device__ static inline void tcgen05_mma_ws_collector_b0_use(
+  cuda::ptx::cta_group_1_t,
+  cuda::ptx::kind_t<Kind> kind,
+  uint32_t d_tmem,
+  uint64_t a_desc,
+  uint64_t b_desc,
+  uint32_t idesc,
+  bool enable_input_d);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_mma_ws_collector_b0_use_is_not_supported_before_SM_100a_SM_101a__();
+template <dot_kind _Kind>
+_CCCL_DEVICE static inline void tcgen05_mma_ws_collector_b0_use(
+  cta_group_1_t,
+  kind_t<_Kind> __kind,
+  _CUDA_VSTD::uint32_t __d_tmem,
+  _CUDA_VSTD::uint64_t __a_desc,
+  _CUDA_VSTD::uint64_t __b_desc,
+  _CUDA_VSTD::uint32_t __idesc,
+  bool __enable_input_d)
+{
+  // __cta_group == cta_group_1 (due to parameter type constraint)
+  static_assert(__kind == kind_f16 || __kind == kind_tf32 || __kind == kind_f8f6f4 || __kind == kind_i8, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  _CCCL_IF_CONSTEXPR (__kind == kind_f16)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b0::use [%0], %1, %2, %3, PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_tf32)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b0::use [%0], %1, %2, %3, PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_f8f6f4)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b0::use [%0], %1, %2, %3, PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_i8)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b0::use [%0], %1, %2, %3, PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_mma_ws_collector_b0_use_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.mma.ws.cta_group.kind.collector::b0::use [d_tmem], [a_tmem], b_desc, idesc, enable_input_d,
+zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_101a
+// .cta_group = { .cta_group::1 }
+// .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+template <cuda::ptx::dot_kind Kind>
+__device__ static inline void tcgen05_mma_ws_tmem_a_collector_b0_use(
+  cuda::ptx::cta_group_1_t,
+  cuda::ptx::kind_t<Kind> kind,
+  uint32_t d_tmem,
+  uint32_t a_tmem,
+  uint64_t b_desc,
+  uint32_t idesc,
+  bool enable_input_d,
+  uint64_t zero_column_mask_desc);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void
+__cuda_ptx_tcgen05_mma_ws_tmem_a_collector_b0_use_is_not_supported_before_SM_100a_SM_101a__();
+template <dot_kind _Kind>
+_CCCL_DEVICE static inline void tcgen05_mma_ws_tmem_a_collector_b0_use(
+  cta_group_1_t,
+  kind_t<_Kind> __kind,
+  _CUDA_VSTD::uint32_t __d_tmem,
+  _CUDA_VSTD::uint32_t __a_tmem,
+  _CUDA_VSTD::uint64_t __b_desc,
+  _CUDA_VSTD::uint32_t __idesc,
+  bool __enable_input_d,
+  _CUDA_VSTD::uint64_t __zero_column_mask_desc)
+{
+  // __cta_group == cta_group_1 (due to parameter type constraint)
+  static_assert(__kind == kind_f16 || __kind == kind_tf32 || __kind == kind_f8f6f4 || __kind == kind_i8, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  _CCCL_IF_CONSTEXPR (__kind == kind_f16)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b0::use [%0], [%1], %2, %3, PRED_enable_input_d, %5;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "r"(__a_tmem),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d)),
+        "l"(__zero_column_mask_desc)
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_tf32)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b0::use [%0], [%1], %2, %3, PRED_enable_input_d, %5;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "r"(__a_tmem),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d)),
+        "l"(__zero_column_mask_desc)
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_f8f6f4)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b0::use [%0], [%1], %2, %3, PRED_enable_input_d, %5;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "r"(__a_tmem),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d)),
+        "l"(__zero_column_mask_desc)
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_i8)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b0::use [%0], [%1], %2, %3, PRED_enable_input_d, %5;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "r"(__a_tmem),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d)),
+        "l"(__zero_column_mask_desc)
+      : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_mma_ws_tmem_a_collector_b0_use_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.mma.ws.cta_group.kind.collector::b0::use [d_tmem], [a_tmem], b_desc, idesc, enable_input_d; // PTX ISA 86,
+SM_100a, SM_101a
+// .cta_group = { .cta_group::1 }
+// .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+template <cuda::ptx::dot_kind Kind>
+__device__ static inline void tcgen05_mma_ws_tmem_a_collector_b0_use(
+  cuda::ptx::cta_group_1_t,
+  cuda::ptx::kind_t<Kind> kind,
+  uint32_t d_tmem,
+  uint32_t a_tmem,
+  uint64_t b_desc,
+  uint32_t idesc,
+  bool enable_input_d);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void
+__cuda_ptx_tcgen05_mma_ws_tmem_a_collector_b0_use_is_not_supported_before_SM_100a_SM_101a__();
+template <dot_kind _Kind>
+_CCCL_DEVICE static inline void tcgen05_mma_ws_tmem_a_collector_b0_use(
+  cta_group_1_t,
+  kind_t<_Kind> __kind,
+  _CUDA_VSTD::uint32_t __d_tmem,
+  _CUDA_VSTD::uint32_t __a_tmem,
+  _CUDA_VSTD::uint64_t __b_desc,
+  _CUDA_VSTD::uint32_t __idesc,
+  bool __enable_input_d)
+{
+  // __cta_group == cta_group_1 (due to parameter type constraint)
+  static_assert(__kind == kind_f16 || __kind == kind_tf32 || __kind == kind_f8f6f4 || __kind == kind_i8, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  _CCCL_IF_CONSTEXPR (__kind == kind_f16)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b0::use [%0], [%1], %2, %3, PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "r"(__a_tmem),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_tf32)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b0::use [%0], [%1], %2, %3, PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "r"(__a_tmem),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_f8f6f4)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b0::use [%0], [%1], %2, %3, PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "r"(__a_tmem),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_i8)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b0::use [%0], [%1], %2, %3, PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "r"(__a_tmem),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_mma_ws_tmem_a_collector_b0_use_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.mma.ws.cta_group.kind.collector::b0::lastuse [d_tmem], a_desc, b_desc, idesc, enable_input_d,
+zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_101a
+// .cta_group = { .cta_group::1 }
+// .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+template <cuda::ptx::dot_kind Kind>
+__device__ static inline void tcgen05_mma_ws_collector_b0_lastuse(
+  cuda::ptx::cta_group_1_t,
+  cuda::ptx::kind_t<Kind> kind,
+  uint32_t d_tmem,
+  uint64_t a_desc,
+  uint64_t b_desc,
+  uint32_t idesc,
+  bool enable_input_d,
+  uint64_t zero_column_mask_desc);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_mma_ws_collector_b0_lastuse_is_not_supported_before_SM_100a_SM_101a__();
+template <dot_kind _Kind>
+_CCCL_DEVICE static inline void tcgen05_mma_ws_collector_b0_lastuse(
+  cta_group_1_t,
+  kind_t<_Kind> __kind,
+  _CUDA_VSTD::uint32_t __d_tmem,
+  _CUDA_VSTD::uint64_t __a_desc,
+  _CUDA_VSTD::uint64_t __b_desc,
+  _CUDA_VSTD::uint32_t __idesc,
+  bool __enable_input_d,
+  _CUDA_VSTD::uint64_t __zero_column_mask_desc)
+{
+  // __cta_group == cta_group_1 (due to parameter type constraint)
+  static_assert(__kind == kind_f16 || __kind == kind_tf32 || __kind == kind_f8f6f4 || __kind == kind_i8, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  _CCCL_IF_CONSTEXPR (__kind == kind_f16)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b0::lastuse [%0], %1, %2, %3, PRED_enable_input_d, %5;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d)),
+        "l"(__zero_column_mask_desc)
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_tf32)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b0::lastuse [%0], %1, %2, %3, PRED_enable_input_d, %5;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d)),
+        "l"(__zero_column_mask_desc)
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_f8f6f4)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b0::lastuse [%0], %1, %2, %3, PRED_enable_input_d, %5;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d)),
+        "l"(__zero_column_mask_desc)
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_i8)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b0::lastuse [%0], %1, %2, %3, PRED_enable_input_d, %5;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d)),
+        "l"(__zero_column_mask_desc)
+      : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_mma_ws_collector_b0_lastuse_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.mma.ws.cta_group.kind.collector::b0::lastuse [d_tmem], a_desc, b_desc, idesc, enable_input_d; // PTX ISA 86,
+SM_100a, SM_101a
+// .cta_group = { .cta_group::1 }
+// .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+template <cuda::ptx::dot_kind Kind>
+__device__ static inline void tcgen05_mma_ws_collector_b0_lastuse(
+  cuda::ptx::cta_group_1_t,
+  cuda::ptx::kind_t<Kind> kind,
+  uint32_t d_tmem,
+  uint64_t a_desc,
+  uint64_t b_desc,
+  uint32_t idesc,
+  bool enable_input_d);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_mma_ws_collector_b0_lastuse_is_not_supported_before_SM_100a_SM_101a__();
+template <dot_kind _Kind>
+_CCCL_DEVICE static inline void tcgen05_mma_ws_collector_b0_lastuse(
+  cta_group_1_t,
+  kind_t<_Kind> __kind,
+  _CUDA_VSTD::uint32_t __d_tmem,
+  _CUDA_VSTD::uint64_t __a_desc,
+  _CUDA_VSTD::uint64_t __b_desc,
+  _CUDA_VSTD::uint32_t __idesc,
+  bool __enable_input_d)
+{
+  // __cta_group == cta_group_1 (due to parameter type constraint)
+  static_assert(__kind == kind_f16 || __kind == kind_tf32 || __kind == kind_f8f6f4 || __kind == kind_i8, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  _CCCL_IF_CONSTEXPR (__kind == kind_f16)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b0::lastuse [%0], %1, %2, %3, PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_tf32)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b0::lastuse [%0], %1, %2, %3, PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_f8f6f4)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b0::lastuse [%0], %1, %2, %3, PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_i8)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b0::lastuse [%0], %1, %2, %3, PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_mma_ws_collector_b0_lastuse_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.mma.ws.cta_group.kind.collector::b0::lastuse [d_tmem], [a_tmem], b_desc, idesc, enable_input_d,
+zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_101a
+// .cta_group = { .cta_group::1 }
+// .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+template <cuda::ptx::dot_kind Kind>
+__device__ static inline void tcgen05_mma_ws_tmem_a_collector_b0_lastuse(
+  cuda::ptx::cta_group_1_t,
+  cuda::ptx::kind_t<Kind> kind,
+  uint32_t d_tmem,
+  uint32_t a_tmem,
+  uint64_t b_desc,
+  uint32_t idesc,
+  bool enable_input_d,
+  uint64_t zero_column_mask_desc);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void
+__cuda_ptx_tcgen05_mma_ws_tmem_a_collector_b0_lastuse_is_not_supported_before_SM_100a_SM_101a__();
+template <dot_kind _Kind>
+_CCCL_DEVICE static inline void tcgen05_mma_ws_tmem_a_collector_b0_lastuse(
+  cta_group_1_t,
+  kind_t<_Kind> __kind,
+  _CUDA_VSTD::uint32_t __d_tmem,
+  _CUDA_VSTD::uint32_t __a_tmem,
+  _CUDA_VSTD::uint64_t __b_desc,
+  _CUDA_VSTD::uint32_t __idesc,
+  bool __enable_input_d,
+  _CUDA_VSTD::uint64_t __zero_column_mask_desc)
+{
+  // __cta_group == cta_group_1 (due to parameter type constraint)
+  static_assert(__kind == kind_f16 || __kind == kind_tf32 || __kind == kind_f8f6f4 || __kind == kind_i8, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  _CCCL_IF_CONSTEXPR (__kind == kind_f16)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b0::lastuse [%0], [%1], %2, %3, PRED_enable_input_d, %5;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "r"(__a_tmem),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d)),
+        "l"(__zero_column_mask_desc)
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_tf32)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b0::lastuse [%0], [%1], %2, %3, PRED_enable_input_d, %5;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "r"(__a_tmem),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d)),
+        "l"(__zero_column_mask_desc)
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_f8f6f4)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b0::lastuse [%0], [%1], %2, %3, PRED_enable_input_d, %5;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "r"(__a_tmem),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d)),
+        "l"(__zero_column_mask_desc)
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_i8)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b0::lastuse [%0], [%1], %2, %3, PRED_enable_input_d, %5;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "r"(__a_tmem),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d)),
+        "l"(__zero_column_mask_desc)
+      : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_mma_ws_tmem_a_collector_b0_lastuse_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.mma.ws.cta_group.kind.collector::b0::lastuse [d_tmem], [a_tmem], b_desc, idesc, enable_input_d; // PTX ISA
+86, SM_100a, SM_101a
+// .cta_group = { .cta_group::1 }
+// .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+template <cuda::ptx::dot_kind Kind>
+__device__ static inline void tcgen05_mma_ws_tmem_a_collector_b0_lastuse(
+  cuda::ptx::cta_group_1_t,
+  cuda::ptx::kind_t<Kind> kind,
+  uint32_t d_tmem,
+  uint32_t a_tmem,
+  uint64_t b_desc,
+  uint32_t idesc,
+  bool enable_input_d);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void
+__cuda_ptx_tcgen05_mma_ws_tmem_a_collector_b0_lastuse_is_not_supported_before_SM_100a_SM_101a__();
+template <dot_kind _Kind>
+_CCCL_DEVICE static inline void tcgen05_mma_ws_tmem_a_collector_b0_lastuse(
+  cta_group_1_t,
+  kind_t<_Kind> __kind,
+  _CUDA_VSTD::uint32_t __d_tmem,
+  _CUDA_VSTD::uint32_t __a_tmem,
+  _CUDA_VSTD::uint64_t __b_desc,
+  _CUDA_VSTD::uint32_t __idesc,
+  bool __enable_input_d)
+{
+  // __cta_group == cta_group_1 (due to parameter type constraint)
+  static_assert(__kind == kind_f16 || __kind == kind_tf32 || __kind == kind_f8f6f4 || __kind == kind_i8, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  _CCCL_IF_CONSTEXPR (__kind == kind_f16)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b0::lastuse [%0], [%1], %2, %3, PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "r"(__a_tmem),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_tf32)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b0::lastuse [%0], [%1], %2, %3, PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "r"(__a_tmem),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_f8f6f4)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b0::lastuse [%0], [%1], %2, %3, PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "r"(__a_tmem),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_i8)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b0::lastuse [%0], [%1], %2, %3, PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "r"(__a_tmem),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_mma_ws_tmem_a_collector_b0_lastuse_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.mma.ws.cta_group.kind.collector::b0::discard [d_tmem], a_desc, b_desc, idesc, enable_input_d,
+zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_101a
+// .cta_group = { .cta_group::1 }
+// .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+template <cuda::ptx::dot_kind Kind>
+__device__ static inline void tcgen05_mma_ws_collector_b0_discard(
+  cuda::ptx::cta_group_1_t,
+  cuda::ptx::kind_t<Kind> kind,
+  uint32_t d_tmem,
+  uint64_t a_desc,
+  uint64_t b_desc,
+  uint32_t idesc,
+  bool enable_input_d,
+  uint64_t zero_column_mask_desc);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_mma_ws_collector_b0_discard_is_not_supported_before_SM_100a_SM_101a__();
+template <dot_kind _Kind>
+_CCCL_DEVICE static inline void tcgen05_mma_ws_collector_b0_discard(
+  cta_group_1_t,
+  kind_t<_Kind> __kind,
+  _CUDA_VSTD::uint32_t __d_tmem,
+  _CUDA_VSTD::uint64_t __a_desc,
+  _CUDA_VSTD::uint64_t __b_desc,
+  _CUDA_VSTD::uint32_t __idesc,
+  bool __enable_input_d,
+  _CUDA_VSTD::uint64_t __zero_column_mask_desc)
+{
+  // __cta_group == cta_group_1 (due to parameter type constraint)
+  static_assert(__kind == kind_f16 || __kind == kind_tf32 || __kind == kind_f8f6f4 || __kind == kind_i8, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  _CCCL_IF_CONSTEXPR (__kind == kind_f16)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b0::discard [%0], %1, %2, %3, PRED_enable_input_d, %5;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d)),
+        "l"(__zero_column_mask_desc)
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_tf32)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b0::discard [%0], %1, %2, %3, PRED_enable_input_d, %5;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d)),
+        "l"(__zero_column_mask_desc)
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_f8f6f4)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b0::discard [%0], %1, %2, %3, PRED_enable_input_d, %5;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d)),
+        "l"(__zero_column_mask_desc)
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_i8)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b0::discard [%0], %1, %2, %3, PRED_enable_input_d, %5;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d)),
+        "l"(__zero_column_mask_desc)
+      : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_mma_ws_collector_b0_discard_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.mma.ws.cta_group.kind.collector::b0::discard [d_tmem], a_desc, b_desc, idesc, enable_input_d; // PTX ISA 86,
+SM_100a, SM_101a
+// .cta_group = { .cta_group::1 }
+// .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+template <cuda::ptx::dot_kind Kind>
+__device__ static inline void tcgen05_mma_ws_collector_b0_discard(
+  cuda::ptx::cta_group_1_t,
+  cuda::ptx::kind_t<Kind> kind,
+  uint32_t d_tmem,
+  uint64_t a_desc,
+  uint64_t b_desc,
+  uint32_t idesc,
+  bool enable_input_d);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_mma_ws_collector_b0_discard_is_not_supported_before_SM_100a_SM_101a__();
+template <dot_kind _Kind>
+_CCCL_DEVICE static inline void tcgen05_mma_ws_collector_b0_discard(
+  cta_group_1_t,
+  kind_t<_Kind> __kind,
+  _CUDA_VSTD::uint32_t __d_tmem,
+  _CUDA_VSTD::uint64_t __a_desc,
+  _CUDA_VSTD::uint64_t __b_desc,
+  _CUDA_VSTD::uint32_t __idesc,
+  bool __enable_input_d)
+{
+  // __cta_group == cta_group_1 (due to parameter type constraint)
+  static_assert(__kind == kind_f16 || __kind == kind_tf32 || __kind == kind_f8f6f4 || __kind == kind_i8, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  _CCCL_IF_CONSTEXPR (__kind == kind_f16)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b0::discard [%0], %1, %2, %3, PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_tf32)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b0::discard [%0], %1, %2, %3, PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_f8f6f4)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b0::discard [%0], %1, %2, %3, PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_i8)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b0::discard [%0], %1, %2, %3, PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_mma_ws_collector_b0_discard_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.mma.ws.cta_group.kind.collector::b0::discard [d_tmem], [a_tmem], b_desc, idesc, enable_input_d,
+zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_101a
+// .cta_group = { .cta_group::1 }
+// .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+template <cuda::ptx::dot_kind Kind>
+__device__ static inline void tcgen05_mma_ws_tmem_a_collector_b0_discard(
+  cuda::ptx::cta_group_1_t,
+  cuda::ptx::kind_t<Kind> kind,
+  uint32_t d_tmem,
+  uint32_t a_tmem,
+  uint64_t b_desc,
+  uint32_t idesc,
+  bool enable_input_d,
+  uint64_t zero_column_mask_desc);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void
+__cuda_ptx_tcgen05_mma_ws_tmem_a_collector_b0_discard_is_not_supported_before_SM_100a_SM_101a__();
+template <dot_kind _Kind>
+_CCCL_DEVICE static inline void tcgen05_mma_ws_tmem_a_collector_b0_discard(
+  cta_group_1_t,
+  kind_t<_Kind> __kind,
+  _CUDA_VSTD::uint32_t __d_tmem,
+  _CUDA_VSTD::uint32_t __a_tmem,
+  _CUDA_VSTD::uint64_t __b_desc,
+  _CUDA_VSTD::uint32_t __idesc,
+  bool __enable_input_d,
+  _CUDA_VSTD::uint64_t __zero_column_mask_desc)
+{
+  // __cta_group == cta_group_1 (due to parameter type constraint)
+  static_assert(__kind == kind_f16 || __kind == kind_tf32 || __kind == kind_f8f6f4 || __kind == kind_i8, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  _CCCL_IF_CONSTEXPR (__kind == kind_f16)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b0::discard [%0], [%1], %2, %3, PRED_enable_input_d, %5;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "r"(__a_tmem),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d)),
+        "l"(__zero_column_mask_desc)
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_tf32)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b0::discard [%0], [%1], %2, %3, PRED_enable_input_d, %5;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "r"(__a_tmem),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d)),
+        "l"(__zero_column_mask_desc)
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_f8f6f4)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b0::discard [%0], [%1], %2, %3, PRED_enable_input_d, %5;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "r"(__a_tmem),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d)),
+        "l"(__zero_column_mask_desc)
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_i8)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b0::discard [%0], [%1], %2, %3, PRED_enable_input_d, %5;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "r"(__a_tmem),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d)),
+        "l"(__zero_column_mask_desc)
+      : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_mma_ws_tmem_a_collector_b0_discard_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.mma.ws.cta_group.kind.collector::b0::discard [d_tmem], [a_tmem], b_desc, idesc, enable_input_d; // PTX ISA
+86, SM_100a, SM_101a
+// .cta_group = { .cta_group::1 }
+// .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+template <cuda::ptx::dot_kind Kind>
+__device__ static inline void tcgen05_mma_ws_tmem_a_collector_b0_discard(
+  cuda::ptx::cta_group_1_t,
+  cuda::ptx::kind_t<Kind> kind,
+  uint32_t d_tmem,
+  uint32_t a_tmem,
+  uint64_t b_desc,
+  uint32_t idesc,
+  bool enable_input_d);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void
+__cuda_ptx_tcgen05_mma_ws_tmem_a_collector_b0_discard_is_not_supported_before_SM_100a_SM_101a__();
+template <dot_kind _Kind>
+_CCCL_DEVICE static inline void tcgen05_mma_ws_tmem_a_collector_b0_discard(
+  cta_group_1_t,
+  kind_t<_Kind> __kind,
+  _CUDA_VSTD::uint32_t __d_tmem,
+  _CUDA_VSTD::uint32_t __a_tmem,
+  _CUDA_VSTD::uint64_t __b_desc,
+  _CUDA_VSTD::uint32_t __idesc,
+  bool __enable_input_d)
+{
+  // __cta_group == cta_group_1 (due to parameter type constraint)
+  static_assert(__kind == kind_f16 || __kind == kind_tf32 || __kind == kind_f8f6f4 || __kind == kind_i8, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  _CCCL_IF_CONSTEXPR (__kind == kind_f16)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b0::discard [%0], [%1], %2, %3, PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "r"(__a_tmem),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_tf32)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b0::discard [%0], [%1], %2, %3, PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "r"(__a_tmem),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_f8f6f4)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b0::discard [%0], [%1], %2, %3, PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "r"(__a_tmem),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_i8)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b0::discard [%0], [%1], %2, %3, PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "r"(__a_tmem),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_mma_ws_tmem_a_collector_b0_discard_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.mma.ws.cta_group.kind.collector::b1::fill [d_tmem], a_desc, b_desc, idesc, enable_input_d,
+zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_101a
+// .cta_group = { .cta_group::1 }
+// .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+template <cuda::ptx::dot_kind Kind>
+__device__ static inline void tcgen05_mma_ws_collector_b1_fill(
+  cuda::ptx::cta_group_1_t,
+  cuda::ptx::kind_t<Kind> kind,
+  uint32_t d_tmem,
+  uint64_t a_desc,
+  uint64_t b_desc,
+  uint32_t idesc,
+  bool enable_input_d,
+  uint64_t zero_column_mask_desc);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_mma_ws_collector_b1_fill_is_not_supported_before_SM_100a_SM_101a__();
+template <dot_kind _Kind>
+_CCCL_DEVICE static inline void tcgen05_mma_ws_collector_b1_fill(
+  cta_group_1_t,
+  kind_t<_Kind> __kind,
+  _CUDA_VSTD::uint32_t __d_tmem,
+  _CUDA_VSTD::uint64_t __a_desc,
+  _CUDA_VSTD::uint64_t __b_desc,
+  _CUDA_VSTD::uint32_t __idesc,
+  bool __enable_input_d,
+  _CUDA_VSTD::uint64_t __zero_column_mask_desc)
+{
+  // __cta_group == cta_group_1 (due to parameter type constraint)
+  static_assert(__kind == kind_f16 || __kind == kind_tf32 || __kind == kind_f8f6f4 || __kind == kind_i8, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  _CCCL_IF_CONSTEXPR (__kind == kind_f16)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b1::fill [%0], %1, %2, %3, PRED_enable_input_d, %5;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d)),
+        "l"(__zero_column_mask_desc)
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_tf32)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b1::fill [%0], %1, %2, %3, PRED_enable_input_d, %5;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d)),
+        "l"(__zero_column_mask_desc)
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_f8f6f4)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b1::fill [%0], %1, %2, %3, PRED_enable_input_d, %5;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d)),
+        "l"(__zero_column_mask_desc)
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_i8)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b1::fill [%0], %1, %2, %3, PRED_enable_input_d, %5;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d)),
+        "l"(__zero_column_mask_desc)
+      : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_mma_ws_collector_b1_fill_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.mma.ws.cta_group.kind.collector::b1::fill [d_tmem], a_desc, b_desc, idesc, enable_input_d; // PTX ISA 86,
+SM_100a, SM_101a
+// .cta_group = { .cta_group::1 }
+// .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+template <cuda::ptx::dot_kind Kind>
+__device__ static inline void tcgen05_mma_ws_collector_b1_fill(
+  cuda::ptx::cta_group_1_t,
+  cuda::ptx::kind_t<Kind> kind,
+  uint32_t d_tmem,
+  uint64_t a_desc,
+  uint64_t b_desc,
+  uint32_t idesc,
+  bool enable_input_d);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_mma_ws_collector_b1_fill_is_not_supported_before_SM_100a_SM_101a__();
+template <dot_kind _Kind>
+_CCCL_DEVICE static inline void tcgen05_mma_ws_collector_b1_fill(
+  cta_group_1_t,
+  kind_t<_Kind> __kind,
+  _CUDA_VSTD::uint32_t __d_tmem,
+  _CUDA_VSTD::uint64_t __a_desc,
+  _CUDA_VSTD::uint64_t __b_desc,
+  _CUDA_VSTD::uint32_t __idesc,
+  bool __enable_input_d)
+{
+  // __cta_group == cta_group_1 (due to parameter type constraint)
+  static_assert(__kind == kind_f16 || __kind == kind_tf32 || __kind == kind_f8f6f4 || __kind == kind_i8, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  _CCCL_IF_CONSTEXPR (__kind == kind_f16)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b1::fill [%0], %1, %2, %3, PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_tf32)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b1::fill [%0], %1, %2, %3, PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_f8f6f4)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b1::fill [%0], %1, %2, %3, PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_i8)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b1::fill [%0], %1, %2, %3, PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_mma_ws_collector_b1_fill_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.mma.ws.cta_group.kind.collector::b1::fill [d_tmem], [a_tmem], b_desc, idesc, enable_input_d,
+zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_101a
+// .cta_group = { .cta_group::1 }
+// .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+template <cuda::ptx::dot_kind Kind>
+__device__ static inline void tcgen05_mma_ws_tmem_a_collector_b1_fill(
+  cuda::ptx::cta_group_1_t,
+  cuda::ptx::kind_t<Kind> kind,
+  uint32_t d_tmem,
+  uint32_t a_tmem,
+  uint64_t b_desc,
+  uint32_t idesc,
+  bool enable_input_d,
+  uint64_t zero_column_mask_desc);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void
+__cuda_ptx_tcgen05_mma_ws_tmem_a_collector_b1_fill_is_not_supported_before_SM_100a_SM_101a__();
+template <dot_kind _Kind>
+_CCCL_DEVICE static inline void tcgen05_mma_ws_tmem_a_collector_b1_fill(
+  cta_group_1_t,
+  kind_t<_Kind> __kind,
+  _CUDA_VSTD::uint32_t __d_tmem,
+  _CUDA_VSTD::uint32_t __a_tmem,
+  _CUDA_VSTD::uint64_t __b_desc,
+  _CUDA_VSTD::uint32_t __idesc,
+  bool __enable_input_d,
+  _CUDA_VSTD::uint64_t __zero_column_mask_desc)
+{
+  // __cta_group == cta_group_1 (due to parameter type constraint)
+  static_assert(__kind == kind_f16 || __kind == kind_tf32 || __kind == kind_f8f6f4 || __kind == kind_i8, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  _CCCL_IF_CONSTEXPR (__kind == kind_f16)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b1::fill [%0], [%1], %2, %3, PRED_enable_input_d, %5;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "r"(__a_tmem),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d)),
+        "l"(__zero_column_mask_desc)
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_tf32)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b1::fill [%0], [%1], %2, %3, PRED_enable_input_d, %5;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "r"(__a_tmem),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d)),
+        "l"(__zero_column_mask_desc)
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_f8f6f4)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b1::fill [%0], [%1], %2, %3, PRED_enable_input_d, %5;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "r"(__a_tmem),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d)),
+        "l"(__zero_column_mask_desc)
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_i8)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b1::fill [%0], [%1], %2, %3, PRED_enable_input_d, %5;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "r"(__a_tmem),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d)),
+        "l"(__zero_column_mask_desc)
+      : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_mma_ws_tmem_a_collector_b1_fill_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.mma.ws.cta_group.kind.collector::b1::fill [d_tmem], [a_tmem], b_desc, idesc, enable_input_d; // PTX ISA 86,
+SM_100a, SM_101a
+// .cta_group = { .cta_group::1 }
+// .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+template <cuda::ptx::dot_kind Kind>
+__device__ static inline void tcgen05_mma_ws_tmem_a_collector_b1_fill(
+  cuda::ptx::cta_group_1_t,
+  cuda::ptx::kind_t<Kind> kind,
+  uint32_t d_tmem,
+  uint32_t a_tmem,
+  uint64_t b_desc,
+  uint32_t idesc,
+  bool enable_input_d);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void
+__cuda_ptx_tcgen05_mma_ws_tmem_a_collector_b1_fill_is_not_supported_before_SM_100a_SM_101a__();
+template <dot_kind _Kind>
+_CCCL_DEVICE static inline void tcgen05_mma_ws_tmem_a_collector_b1_fill(
+  cta_group_1_t,
+  kind_t<_Kind> __kind,
+  _CUDA_VSTD::uint32_t __d_tmem,
+  _CUDA_VSTD::uint32_t __a_tmem,
+  _CUDA_VSTD::uint64_t __b_desc,
+  _CUDA_VSTD::uint32_t __idesc,
+  bool __enable_input_d)
+{
+  // __cta_group == cta_group_1 (due to parameter type constraint)
+  static_assert(__kind == kind_f16 || __kind == kind_tf32 || __kind == kind_f8f6f4 || __kind == kind_i8, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  _CCCL_IF_CONSTEXPR (__kind == kind_f16)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b1::fill [%0], [%1], %2, %3, PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "r"(__a_tmem),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_tf32)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b1::fill [%0], [%1], %2, %3, PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "r"(__a_tmem),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_f8f6f4)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b1::fill [%0], [%1], %2, %3, PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "r"(__a_tmem),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_i8)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b1::fill [%0], [%1], %2, %3, PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "r"(__a_tmem),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_mma_ws_tmem_a_collector_b1_fill_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.mma.ws.cta_group.kind.collector::b1::use [d_tmem], a_desc, b_desc, idesc, enable_input_d,
+zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_101a
+// .cta_group = { .cta_group::1 }
+// .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+template <cuda::ptx::dot_kind Kind>
+__device__ static inline void tcgen05_mma_ws_collector_b1_use(
+  cuda::ptx::cta_group_1_t,
+  cuda::ptx::kind_t<Kind> kind,
+  uint32_t d_tmem,
+  uint64_t a_desc,
+  uint64_t b_desc,
+  uint32_t idesc,
+  bool enable_input_d,
+  uint64_t zero_column_mask_desc);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_mma_ws_collector_b1_use_is_not_supported_before_SM_100a_SM_101a__();
+template <dot_kind _Kind>
+_CCCL_DEVICE static inline void tcgen05_mma_ws_collector_b1_use(
+  cta_group_1_t,
+  kind_t<_Kind> __kind,
+  _CUDA_VSTD::uint32_t __d_tmem,
+  _CUDA_VSTD::uint64_t __a_desc,
+  _CUDA_VSTD::uint64_t __b_desc,
+  _CUDA_VSTD::uint32_t __idesc,
+  bool __enable_input_d,
+  _CUDA_VSTD::uint64_t __zero_column_mask_desc)
+{
+  // __cta_group == cta_group_1 (due to parameter type constraint)
+  static_assert(__kind == kind_f16 || __kind == kind_tf32 || __kind == kind_f8f6f4 || __kind == kind_i8, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  _CCCL_IF_CONSTEXPR (__kind == kind_f16)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b1::use [%0], %1, %2, %3, PRED_enable_input_d, %5;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d)),
+        "l"(__zero_column_mask_desc)
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_tf32)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b1::use [%0], %1, %2, %3, PRED_enable_input_d, %5;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d)),
+        "l"(__zero_column_mask_desc)
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_f8f6f4)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b1::use [%0], %1, %2, %3, PRED_enable_input_d, %5;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d)),
+        "l"(__zero_column_mask_desc)
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_i8)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b1::use [%0], %1, %2, %3, PRED_enable_input_d, %5;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d)),
+        "l"(__zero_column_mask_desc)
+      : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_mma_ws_collector_b1_use_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.mma.ws.cta_group.kind.collector::b1::use [d_tmem], a_desc, b_desc, idesc, enable_input_d; // PTX ISA 86,
+SM_100a, SM_101a
+// .cta_group = { .cta_group::1 }
+// .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+template <cuda::ptx::dot_kind Kind>
+__device__ static inline void tcgen05_mma_ws_collector_b1_use(
+  cuda::ptx::cta_group_1_t,
+  cuda::ptx::kind_t<Kind> kind,
+  uint32_t d_tmem,
+  uint64_t a_desc,
+  uint64_t b_desc,
+  uint32_t idesc,
+  bool enable_input_d);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_mma_ws_collector_b1_use_is_not_supported_before_SM_100a_SM_101a__();
+template <dot_kind _Kind>
+_CCCL_DEVICE static inline void tcgen05_mma_ws_collector_b1_use(
+  cta_group_1_t,
+  kind_t<_Kind> __kind,
+  _CUDA_VSTD::uint32_t __d_tmem,
+  _CUDA_VSTD::uint64_t __a_desc,
+  _CUDA_VSTD::uint64_t __b_desc,
+  _CUDA_VSTD::uint32_t __idesc,
+  bool __enable_input_d)
+{
+  // __cta_group == cta_group_1 (due to parameter type constraint)
+  static_assert(__kind == kind_f16 || __kind == kind_tf32 || __kind == kind_f8f6f4 || __kind == kind_i8, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  _CCCL_IF_CONSTEXPR (__kind == kind_f16)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b1::use [%0], %1, %2, %3, PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_tf32)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b1::use [%0], %1, %2, %3, PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_f8f6f4)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b1::use [%0], %1, %2, %3, PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_i8)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b1::use [%0], %1, %2, %3, PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_mma_ws_collector_b1_use_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.mma.ws.cta_group.kind.collector::b1::use [d_tmem], [a_tmem], b_desc, idesc, enable_input_d,
+zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_101a
+// .cta_group = { .cta_group::1 }
+// .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+template <cuda::ptx::dot_kind Kind>
+__device__ static inline void tcgen05_mma_ws_tmem_a_collector_b1_use(
+  cuda::ptx::cta_group_1_t,
+  cuda::ptx::kind_t<Kind> kind,
+  uint32_t d_tmem,
+  uint32_t a_tmem,
+  uint64_t b_desc,
+  uint32_t idesc,
+  bool enable_input_d,
+  uint64_t zero_column_mask_desc);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void
+__cuda_ptx_tcgen05_mma_ws_tmem_a_collector_b1_use_is_not_supported_before_SM_100a_SM_101a__();
+template <dot_kind _Kind>
+_CCCL_DEVICE static inline void tcgen05_mma_ws_tmem_a_collector_b1_use(
+  cta_group_1_t,
+  kind_t<_Kind> __kind,
+  _CUDA_VSTD::uint32_t __d_tmem,
+  _CUDA_VSTD::uint32_t __a_tmem,
+  _CUDA_VSTD::uint64_t __b_desc,
+  _CUDA_VSTD::uint32_t __idesc,
+  bool __enable_input_d,
+  _CUDA_VSTD::uint64_t __zero_column_mask_desc)
+{
+  // __cta_group == cta_group_1 (due to parameter type constraint)
+  static_assert(__kind == kind_f16 || __kind == kind_tf32 || __kind == kind_f8f6f4 || __kind == kind_i8, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  _CCCL_IF_CONSTEXPR (__kind == kind_f16)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b1::use [%0], [%1], %2, %3, PRED_enable_input_d, %5;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "r"(__a_tmem),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d)),
+        "l"(__zero_column_mask_desc)
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_tf32)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b1::use [%0], [%1], %2, %3, PRED_enable_input_d, %5;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "r"(__a_tmem),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d)),
+        "l"(__zero_column_mask_desc)
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_f8f6f4)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b1::use [%0], [%1], %2, %3, PRED_enable_input_d, %5;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "r"(__a_tmem),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d)),
+        "l"(__zero_column_mask_desc)
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_i8)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b1::use [%0], [%1], %2, %3, PRED_enable_input_d, %5;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "r"(__a_tmem),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d)),
+        "l"(__zero_column_mask_desc)
+      : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_mma_ws_tmem_a_collector_b1_use_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.mma.ws.cta_group.kind.collector::b1::use [d_tmem], [a_tmem], b_desc, idesc, enable_input_d; // PTX ISA 86,
+SM_100a, SM_101a
+// .cta_group = { .cta_group::1 }
+// .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+template <cuda::ptx::dot_kind Kind>
+__device__ static inline void tcgen05_mma_ws_tmem_a_collector_b1_use(
+  cuda::ptx::cta_group_1_t,
+  cuda::ptx::kind_t<Kind> kind,
+  uint32_t d_tmem,
+  uint32_t a_tmem,
+  uint64_t b_desc,
+  uint32_t idesc,
+  bool enable_input_d);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void
+__cuda_ptx_tcgen05_mma_ws_tmem_a_collector_b1_use_is_not_supported_before_SM_100a_SM_101a__();
+template <dot_kind _Kind>
+_CCCL_DEVICE static inline void tcgen05_mma_ws_tmem_a_collector_b1_use(
+  cta_group_1_t,
+  kind_t<_Kind> __kind,
+  _CUDA_VSTD::uint32_t __d_tmem,
+  _CUDA_VSTD::uint32_t __a_tmem,
+  _CUDA_VSTD::uint64_t __b_desc,
+  _CUDA_VSTD::uint32_t __idesc,
+  bool __enable_input_d)
+{
+  // __cta_group == cta_group_1 (due to parameter type constraint)
+  static_assert(__kind == kind_f16 || __kind == kind_tf32 || __kind == kind_f8f6f4 || __kind == kind_i8, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  _CCCL_IF_CONSTEXPR (__kind == kind_f16)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b1::use [%0], [%1], %2, %3, PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "r"(__a_tmem),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_tf32)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b1::use [%0], [%1], %2, %3, PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "r"(__a_tmem),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_f8f6f4)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b1::use [%0], [%1], %2, %3, PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "r"(__a_tmem),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_i8)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b1::use [%0], [%1], %2, %3, PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "r"(__a_tmem),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_mma_ws_tmem_a_collector_b1_use_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.mma.ws.cta_group.kind.collector::b1::lastuse [d_tmem], a_desc, b_desc, idesc, enable_input_d,
+zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_101a
+// .cta_group = { .cta_group::1 }
+// .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+template <cuda::ptx::dot_kind Kind>
+__device__ static inline void tcgen05_mma_ws_collector_b1_lastuse(
+  cuda::ptx::cta_group_1_t,
+  cuda::ptx::kind_t<Kind> kind,
+  uint32_t d_tmem,
+  uint64_t a_desc,
+  uint64_t b_desc,
+  uint32_t idesc,
+  bool enable_input_d,
+  uint64_t zero_column_mask_desc);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_mma_ws_collector_b1_lastuse_is_not_supported_before_SM_100a_SM_101a__();
+template <dot_kind _Kind>
+_CCCL_DEVICE static inline void tcgen05_mma_ws_collector_b1_lastuse(
+  cta_group_1_t,
+  kind_t<_Kind> __kind,
+  _CUDA_VSTD::uint32_t __d_tmem,
+  _CUDA_VSTD::uint64_t __a_desc,
+  _CUDA_VSTD::uint64_t __b_desc,
+  _CUDA_VSTD::uint32_t __idesc,
+  bool __enable_input_d,
+  _CUDA_VSTD::uint64_t __zero_column_mask_desc)
+{
+  // __cta_group == cta_group_1 (due to parameter type constraint)
+  static_assert(__kind == kind_f16 || __kind == kind_tf32 || __kind == kind_f8f6f4 || __kind == kind_i8, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  _CCCL_IF_CONSTEXPR (__kind == kind_f16)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b1::lastuse [%0], %1, %2, %3, PRED_enable_input_d, %5;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d)),
+        "l"(__zero_column_mask_desc)
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_tf32)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b1::lastuse [%0], %1, %2, %3, PRED_enable_input_d, %5;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d)),
+        "l"(__zero_column_mask_desc)
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_f8f6f4)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b1::lastuse [%0], %1, %2, %3, PRED_enable_input_d, %5;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d)),
+        "l"(__zero_column_mask_desc)
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_i8)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b1::lastuse [%0], %1, %2, %3, PRED_enable_input_d, %5;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d)),
+        "l"(__zero_column_mask_desc)
+      : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_mma_ws_collector_b1_lastuse_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.mma.ws.cta_group.kind.collector::b1::lastuse [d_tmem], a_desc, b_desc, idesc, enable_input_d; // PTX ISA 86,
+SM_100a, SM_101a
+// .cta_group = { .cta_group::1 }
+// .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+template <cuda::ptx::dot_kind Kind>
+__device__ static inline void tcgen05_mma_ws_collector_b1_lastuse(
+  cuda::ptx::cta_group_1_t,
+  cuda::ptx::kind_t<Kind> kind,
+  uint32_t d_tmem,
+  uint64_t a_desc,
+  uint64_t b_desc,
+  uint32_t idesc,
+  bool enable_input_d);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_mma_ws_collector_b1_lastuse_is_not_supported_before_SM_100a_SM_101a__();
+template <dot_kind _Kind>
+_CCCL_DEVICE static inline void tcgen05_mma_ws_collector_b1_lastuse(
+  cta_group_1_t,
+  kind_t<_Kind> __kind,
+  _CUDA_VSTD::uint32_t __d_tmem,
+  _CUDA_VSTD::uint64_t __a_desc,
+  _CUDA_VSTD::uint64_t __b_desc,
+  _CUDA_VSTD::uint32_t __idesc,
+  bool __enable_input_d)
+{
+  // __cta_group == cta_group_1 (due to parameter type constraint)
+  static_assert(__kind == kind_f16 || __kind == kind_tf32 || __kind == kind_f8f6f4 || __kind == kind_i8, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  _CCCL_IF_CONSTEXPR (__kind == kind_f16)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b1::lastuse [%0], %1, %2, %3, PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_tf32)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b1::lastuse [%0], %1, %2, %3, PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_f8f6f4)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b1::lastuse [%0], %1, %2, %3, PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_i8)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b1::lastuse [%0], %1, %2, %3, PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_mma_ws_collector_b1_lastuse_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.mma.ws.cta_group.kind.collector::b1::lastuse [d_tmem], [a_tmem], b_desc, idesc, enable_input_d,
+zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_101a
+// .cta_group = { .cta_group::1 }
+// .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+template <cuda::ptx::dot_kind Kind>
+__device__ static inline void tcgen05_mma_ws_tmem_a_collector_b1_lastuse(
+  cuda::ptx::cta_group_1_t,
+  cuda::ptx::kind_t<Kind> kind,
+  uint32_t d_tmem,
+  uint32_t a_tmem,
+  uint64_t b_desc,
+  uint32_t idesc,
+  bool enable_input_d,
+  uint64_t zero_column_mask_desc);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void
+__cuda_ptx_tcgen05_mma_ws_tmem_a_collector_b1_lastuse_is_not_supported_before_SM_100a_SM_101a__();
+template <dot_kind _Kind>
+_CCCL_DEVICE static inline void tcgen05_mma_ws_tmem_a_collector_b1_lastuse(
+  cta_group_1_t,
+  kind_t<_Kind> __kind,
+  _CUDA_VSTD::uint32_t __d_tmem,
+  _CUDA_VSTD::uint32_t __a_tmem,
+  _CUDA_VSTD::uint64_t __b_desc,
+  _CUDA_VSTD::uint32_t __idesc,
+  bool __enable_input_d,
+  _CUDA_VSTD::uint64_t __zero_column_mask_desc)
+{
+  // __cta_group == cta_group_1 (due to parameter type constraint)
+  static_assert(__kind == kind_f16 || __kind == kind_tf32 || __kind == kind_f8f6f4 || __kind == kind_i8, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  _CCCL_IF_CONSTEXPR (__kind == kind_f16)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b1::lastuse [%0], [%1], %2, %3, PRED_enable_input_d, %5;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "r"(__a_tmem),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d)),
+        "l"(__zero_column_mask_desc)
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_tf32)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b1::lastuse [%0], [%1], %2, %3, PRED_enable_input_d, %5;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "r"(__a_tmem),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d)),
+        "l"(__zero_column_mask_desc)
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_f8f6f4)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b1::lastuse [%0], [%1], %2, %3, PRED_enable_input_d, %5;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "r"(__a_tmem),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d)),
+        "l"(__zero_column_mask_desc)
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_i8)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b1::lastuse [%0], [%1], %2, %3, PRED_enable_input_d, %5;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "r"(__a_tmem),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d)),
+        "l"(__zero_column_mask_desc)
+      : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_mma_ws_tmem_a_collector_b1_lastuse_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.mma.ws.cta_group.kind.collector::b1::lastuse [d_tmem], [a_tmem], b_desc, idesc, enable_input_d; // PTX ISA
+86, SM_100a, SM_101a
+// .cta_group = { .cta_group::1 }
+// .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+template <cuda::ptx::dot_kind Kind>
+__device__ static inline void tcgen05_mma_ws_tmem_a_collector_b1_lastuse(
+  cuda::ptx::cta_group_1_t,
+  cuda::ptx::kind_t<Kind> kind,
+  uint32_t d_tmem,
+  uint32_t a_tmem,
+  uint64_t b_desc,
+  uint32_t idesc,
+  bool enable_input_d);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void
+__cuda_ptx_tcgen05_mma_ws_tmem_a_collector_b1_lastuse_is_not_supported_before_SM_100a_SM_101a__();
+template <dot_kind _Kind>
+_CCCL_DEVICE static inline void tcgen05_mma_ws_tmem_a_collector_b1_lastuse(
+  cta_group_1_t,
+  kind_t<_Kind> __kind,
+  _CUDA_VSTD::uint32_t __d_tmem,
+  _CUDA_VSTD::uint32_t __a_tmem,
+  _CUDA_VSTD::uint64_t __b_desc,
+  _CUDA_VSTD::uint32_t __idesc,
+  bool __enable_input_d)
+{
+  // __cta_group == cta_group_1 (due to parameter type constraint)
+  static_assert(__kind == kind_f16 || __kind == kind_tf32 || __kind == kind_f8f6f4 || __kind == kind_i8, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  _CCCL_IF_CONSTEXPR (__kind == kind_f16)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b1::lastuse [%0], [%1], %2, %3, PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "r"(__a_tmem),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_tf32)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b1::lastuse [%0], [%1], %2, %3, PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "r"(__a_tmem),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_f8f6f4)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b1::lastuse [%0], [%1], %2, %3, PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "r"(__a_tmem),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_i8)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b1::lastuse [%0], [%1], %2, %3, PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "r"(__a_tmem),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_mma_ws_tmem_a_collector_b1_lastuse_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.mma.ws.cta_group.kind.collector::b1::discard [d_tmem], a_desc, b_desc, idesc, enable_input_d,
+zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_101a
+// .cta_group = { .cta_group::1 }
+// .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+template <cuda::ptx::dot_kind Kind>
+__device__ static inline void tcgen05_mma_ws_collector_b1_discard(
+  cuda::ptx::cta_group_1_t,
+  cuda::ptx::kind_t<Kind> kind,
+  uint32_t d_tmem,
+  uint64_t a_desc,
+  uint64_t b_desc,
+  uint32_t idesc,
+  bool enable_input_d,
+  uint64_t zero_column_mask_desc);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_mma_ws_collector_b1_discard_is_not_supported_before_SM_100a_SM_101a__();
+template <dot_kind _Kind>
+_CCCL_DEVICE static inline void tcgen05_mma_ws_collector_b1_discard(
+  cta_group_1_t,
+  kind_t<_Kind> __kind,
+  _CUDA_VSTD::uint32_t __d_tmem,
+  _CUDA_VSTD::uint64_t __a_desc,
+  _CUDA_VSTD::uint64_t __b_desc,
+  _CUDA_VSTD::uint32_t __idesc,
+  bool __enable_input_d,
+  _CUDA_VSTD::uint64_t __zero_column_mask_desc)
+{
+  // __cta_group == cta_group_1 (due to parameter type constraint)
+  static_assert(__kind == kind_f16 || __kind == kind_tf32 || __kind == kind_f8f6f4 || __kind == kind_i8, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  _CCCL_IF_CONSTEXPR (__kind == kind_f16)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b1::discard [%0], %1, %2, %3, PRED_enable_input_d, %5;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d)),
+        "l"(__zero_column_mask_desc)
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_tf32)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b1::discard [%0], %1, %2, %3, PRED_enable_input_d, %5;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d)),
+        "l"(__zero_column_mask_desc)
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_f8f6f4)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b1::discard [%0], %1, %2, %3, PRED_enable_input_d, %5;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d)),
+        "l"(__zero_column_mask_desc)
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_i8)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b1::discard [%0], %1, %2, %3, PRED_enable_input_d, %5;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d)),
+        "l"(__zero_column_mask_desc)
+      : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_mma_ws_collector_b1_discard_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.mma.ws.cta_group.kind.collector::b1::discard [d_tmem], a_desc, b_desc, idesc, enable_input_d; // PTX ISA 86,
+SM_100a, SM_101a
+// .cta_group = { .cta_group::1 }
+// .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+template <cuda::ptx::dot_kind Kind>
+__device__ static inline void tcgen05_mma_ws_collector_b1_discard(
+  cuda::ptx::cta_group_1_t,
+  cuda::ptx::kind_t<Kind> kind,
+  uint32_t d_tmem,
+  uint64_t a_desc,
+  uint64_t b_desc,
+  uint32_t idesc,
+  bool enable_input_d);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_mma_ws_collector_b1_discard_is_not_supported_before_SM_100a_SM_101a__();
+template <dot_kind _Kind>
+_CCCL_DEVICE static inline void tcgen05_mma_ws_collector_b1_discard(
+  cta_group_1_t,
+  kind_t<_Kind> __kind,
+  _CUDA_VSTD::uint32_t __d_tmem,
+  _CUDA_VSTD::uint64_t __a_desc,
+  _CUDA_VSTD::uint64_t __b_desc,
+  _CUDA_VSTD::uint32_t __idesc,
+  bool __enable_input_d)
+{
+  // __cta_group == cta_group_1 (due to parameter type constraint)
+  static_assert(__kind == kind_f16 || __kind == kind_tf32 || __kind == kind_f8f6f4 || __kind == kind_i8, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  _CCCL_IF_CONSTEXPR (__kind == kind_f16)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b1::discard [%0], %1, %2, %3, PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_tf32)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b1::discard [%0], %1, %2, %3, PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_f8f6f4)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b1::discard [%0], %1, %2, %3, PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_i8)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b1::discard [%0], %1, %2, %3, PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_mma_ws_collector_b1_discard_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.mma.ws.cta_group.kind.collector::b1::discard [d_tmem], [a_tmem], b_desc, idesc, enable_input_d,
+zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_101a
+// .cta_group = { .cta_group::1 }
+// .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+template <cuda::ptx::dot_kind Kind>
+__device__ static inline void tcgen05_mma_ws_tmem_a_collector_b1_discard(
+  cuda::ptx::cta_group_1_t,
+  cuda::ptx::kind_t<Kind> kind,
+  uint32_t d_tmem,
+  uint32_t a_tmem,
+  uint64_t b_desc,
+  uint32_t idesc,
+  bool enable_input_d,
+  uint64_t zero_column_mask_desc);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void
+__cuda_ptx_tcgen05_mma_ws_tmem_a_collector_b1_discard_is_not_supported_before_SM_100a_SM_101a__();
+template <dot_kind _Kind>
+_CCCL_DEVICE static inline void tcgen05_mma_ws_tmem_a_collector_b1_discard(
+  cta_group_1_t,
+  kind_t<_Kind> __kind,
+  _CUDA_VSTD::uint32_t __d_tmem,
+  _CUDA_VSTD::uint32_t __a_tmem,
+  _CUDA_VSTD::uint64_t __b_desc,
+  _CUDA_VSTD::uint32_t __idesc,
+  bool __enable_input_d,
+  _CUDA_VSTD::uint64_t __zero_column_mask_desc)
+{
+  // __cta_group == cta_group_1 (due to parameter type constraint)
+  static_assert(__kind == kind_f16 || __kind == kind_tf32 || __kind == kind_f8f6f4 || __kind == kind_i8, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  _CCCL_IF_CONSTEXPR (__kind == kind_f16)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b1::discard [%0], [%1], %2, %3, PRED_enable_input_d, %5;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "r"(__a_tmem),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d)),
+        "l"(__zero_column_mask_desc)
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_tf32)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b1::discard [%0], [%1], %2, %3, PRED_enable_input_d, %5;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "r"(__a_tmem),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d)),
+        "l"(__zero_column_mask_desc)
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_f8f6f4)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b1::discard [%0], [%1], %2, %3, PRED_enable_input_d, %5;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "r"(__a_tmem),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d)),
+        "l"(__zero_column_mask_desc)
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_i8)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b1::discard [%0], [%1], %2, %3, PRED_enable_input_d, %5;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "r"(__a_tmem),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d)),
+        "l"(__zero_column_mask_desc)
+      : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_mma_ws_tmem_a_collector_b1_discard_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.mma.ws.cta_group.kind.collector::b1::discard [d_tmem], [a_tmem], b_desc, idesc, enable_input_d; // PTX ISA
+86, SM_100a, SM_101a
+// .cta_group = { .cta_group::1 }
+// .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+template <cuda::ptx::dot_kind Kind>
+__device__ static inline void tcgen05_mma_ws_tmem_a_collector_b1_discard(
+  cuda::ptx::cta_group_1_t,
+  cuda::ptx::kind_t<Kind> kind,
+  uint32_t d_tmem,
+  uint32_t a_tmem,
+  uint64_t b_desc,
+  uint32_t idesc,
+  bool enable_input_d);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void
+__cuda_ptx_tcgen05_mma_ws_tmem_a_collector_b1_discard_is_not_supported_before_SM_100a_SM_101a__();
+template <dot_kind _Kind>
+_CCCL_DEVICE static inline void tcgen05_mma_ws_tmem_a_collector_b1_discard(
+  cta_group_1_t,
+  kind_t<_Kind> __kind,
+  _CUDA_VSTD::uint32_t __d_tmem,
+  _CUDA_VSTD::uint32_t __a_tmem,
+  _CUDA_VSTD::uint64_t __b_desc,
+  _CUDA_VSTD::uint32_t __idesc,
+  bool __enable_input_d)
+{
+  // __cta_group == cta_group_1 (due to parameter type constraint)
+  static_assert(__kind == kind_f16 || __kind == kind_tf32 || __kind == kind_f8f6f4 || __kind == kind_i8, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  _CCCL_IF_CONSTEXPR (__kind == kind_f16)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b1::discard [%0], [%1], %2, %3, PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "r"(__a_tmem),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_tf32)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b1::discard [%0], [%1], %2, %3, PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "r"(__a_tmem),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_f8f6f4)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b1::discard [%0], [%1], %2, %3, PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "r"(__a_tmem),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_i8)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b1::discard [%0], [%1], %2, %3, PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "r"(__a_tmem),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_mma_ws_tmem_a_collector_b1_discard_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.mma.ws.cta_group.kind.collector::b2::fill [d_tmem], a_desc, b_desc, idesc, enable_input_d,
+zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_101a
+// .cta_group = { .cta_group::1 }
+// .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+template <cuda::ptx::dot_kind Kind>
+__device__ static inline void tcgen05_mma_ws_collector_b2_fill(
+  cuda::ptx::cta_group_1_t,
+  cuda::ptx::kind_t<Kind> kind,
+  uint32_t d_tmem,
+  uint64_t a_desc,
+  uint64_t b_desc,
+  uint32_t idesc,
+  bool enable_input_d,
+  uint64_t zero_column_mask_desc);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_mma_ws_collector_b2_fill_is_not_supported_before_SM_100a_SM_101a__();
+template <dot_kind _Kind>
+_CCCL_DEVICE static inline void tcgen05_mma_ws_collector_b2_fill(
+  cta_group_1_t,
+  kind_t<_Kind> __kind,
+  _CUDA_VSTD::uint32_t __d_tmem,
+  _CUDA_VSTD::uint64_t __a_desc,
+  _CUDA_VSTD::uint64_t __b_desc,
+  _CUDA_VSTD::uint32_t __idesc,
+  bool __enable_input_d,
+  _CUDA_VSTD::uint64_t __zero_column_mask_desc)
+{
+  // __cta_group == cta_group_1 (due to parameter type constraint)
+  static_assert(__kind == kind_f16 || __kind == kind_tf32 || __kind == kind_f8f6f4 || __kind == kind_i8, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  _CCCL_IF_CONSTEXPR (__kind == kind_f16)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b2::fill [%0], %1, %2, %3, PRED_enable_input_d, %5;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d)),
+        "l"(__zero_column_mask_desc)
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_tf32)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b2::fill [%0], %1, %2, %3, PRED_enable_input_d, %5;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d)),
+        "l"(__zero_column_mask_desc)
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_f8f6f4)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b2::fill [%0], %1, %2, %3, PRED_enable_input_d, %5;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d)),
+        "l"(__zero_column_mask_desc)
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_i8)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b2::fill [%0], %1, %2, %3, PRED_enable_input_d, %5;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d)),
+        "l"(__zero_column_mask_desc)
+      : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_mma_ws_collector_b2_fill_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.mma.ws.cta_group.kind.collector::b2::fill [d_tmem], a_desc, b_desc, idesc, enable_input_d; // PTX ISA 86,
+SM_100a, SM_101a
+// .cta_group = { .cta_group::1 }
+// .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+template <cuda::ptx::dot_kind Kind>
+__device__ static inline void tcgen05_mma_ws_collector_b2_fill(
+  cuda::ptx::cta_group_1_t,
+  cuda::ptx::kind_t<Kind> kind,
+  uint32_t d_tmem,
+  uint64_t a_desc,
+  uint64_t b_desc,
+  uint32_t idesc,
+  bool enable_input_d);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_mma_ws_collector_b2_fill_is_not_supported_before_SM_100a_SM_101a__();
+template <dot_kind _Kind>
+_CCCL_DEVICE static inline void tcgen05_mma_ws_collector_b2_fill(
+  cta_group_1_t,
+  kind_t<_Kind> __kind,
+  _CUDA_VSTD::uint32_t __d_tmem,
+  _CUDA_VSTD::uint64_t __a_desc,
+  _CUDA_VSTD::uint64_t __b_desc,
+  _CUDA_VSTD::uint32_t __idesc,
+  bool __enable_input_d)
+{
+  // __cta_group == cta_group_1 (due to parameter type constraint)
+  static_assert(__kind == kind_f16 || __kind == kind_tf32 || __kind == kind_f8f6f4 || __kind == kind_i8, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  _CCCL_IF_CONSTEXPR (__kind == kind_f16)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b2::fill [%0], %1, %2, %3, PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_tf32)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b2::fill [%0], %1, %2, %3, PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_f8f6f4)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b2::fill [%0], %1, %2, %3, PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_i8)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b2::fill [%0], %1, %2, %3, PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_mma_ws_collector_b2_fill_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.mma.ws.cta_group.kind.collector::b2::fill [d_tmem], [a_tmem], b_desc, idesc, enable_input_d,
+zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_101a
+// .cta_group = { .cta_group::1 }
+// .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+template <cuda::ptx::dot_kind Kind>
+__device__ static inline void tcgen05_mma_ws_tmem_a_collector_b2_fill(
+  cuda::ptx::cta_group_1_t,
+  cuda::ptx::kind_t<Kind> kind,
+  uint32_t d_tmem,
+  uint32_t a_tmem,
+  uint64_t b_desc,
+  uint32_t idesc,
+  bool enable_input_d,
+  uint64_t zero_column_mask_desc);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void
+__cuda_ptx_tcgen05_mma_ws_tmem_a_collector_b2_fill_is_not_supported_before_SM_100a_SM_101a__();
+template <dot_kind _Kind>
+_CCCL_DEVICE static inline void tcgen05_mma_ws_tmem_a_collector_b2_fill(
+  cta_group_1_t,
+  kind_t<_Kind> __kind,
+  _CUDA_VSTD::uint32_t __d_tmem,
+  _CUDA_VSTD::uint32_t __a_tmem,
+  _CUDA_VSTD::uint64_t __b_desc,
+  _CUDA_VSTD::uint32_t __idesc,
+  bool __enable_input_d,
+  _CUDA_VSTD::uint64_t __zero_column_mask_desc)
+{
+  // __cta_group == cta_group_1 (due to parameter type constraint)
+  static_assert(__kind == kind_f16 || __kind == kind_tf32 || __kind == kind_f8f6f4 || __kind == kind_i8, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  _CCCL_IF_CONSTEXPR (__kind == kind_f16)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b2::fill [%0], [%1], %2, %3, PRED_enable_input_d, %5;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "r"(__a_tmem),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d)),
+        "l"(__zero_column_mask_desc)
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_tf32)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b2::fill [%0], [%1], %2, %3, PRED_enable_input_d, %5;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "r"(__a_tmem),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d)),
+        "l"(__zero_column_mask_desc)
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_f8f6f4)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b2::fill [%0], [%1], %2, %3, PRED_enable_input_d, %5;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "r"(__a_tmem),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d)),
+        "l"(__zero_column_mask_desc)
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_i8)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b2::fill [%0], [%1], %2, %3, PRED_enable_input_d, %5;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "r"(__a_tmem),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d)),
+        "l"(__zero_column_mask_desc)
+      : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_mma_ws_tmem_a_collector_b2_fill_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.mma.ws.cta_group.kind.collector::b2::fill [d_tmem], [a_tmem], b_desc, idesc, enable_input_d; // PTX ISA 86,
+SM_100a, SM_101a
+// .cta_group = { .cta_group::1 }
+// .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+template <cuda::ptx::dot_kind Kind>
+__device__ static inline void tcgen05_mma_ws_tmem_a_collector_b2_fill(
+  cuda::ptx::cta_group_1_t,
+  cuda::ptx::kind_t<Kind> kind,
+  uint32_t d_tmem,
+  uint32_t a_tmem,
+  uint64_t b_desc,
+  uint32_t idesc,
+  bool enable_input_d);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void
+__cuda_ptx_tcgen05_mma_ws_tmem_a_collector_b2_fill_is_not_supported_before_SM_100a_SM_101a__();
+template <dot_kind _Kind>
+_CCCL_DEVICE static inline void tcgen05_mma_ws_tmem_a_collector_b2_fill(
+  cta_group_1_t,
+  kind_t<_Kind> __kind,
+  _CUDA_VSTD::uint32_t __d_tmem,
+  _CUDA_VSTD::uint32_t __a_tmem,
+  _CUDA_VSTD::uint64_t __b_desc,
+  _CUDA_VSTD::uint32_t __idesc,
+  bool __enable_input_d)
+{
+  // __cta_group == cta_group_1 (due to parameter type constraint)
+  static_assert(__kind == kind_f16 || __kind == kind_tf32 || __kind == kind_f8f6f4 || __kind == kind_i8, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  _CCCL_IF_CONSTEXPR (__kind == kind_f16)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b2::fill [%0], [%1], %2, %3, PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "r"(__a_tmem),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_tf32)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b2::fill [%0], [%1], %2, %3, PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "r"(__a_tmem),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_f8f6f4)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b2::fill [%0], [%1], %2, %3, PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "r"(__a_tmem),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_i8)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b2::fill [%0], [%1], %2, %3, PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "r"(__a_tmem),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_mma_ws_tmem_a_collector_b2_fill_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.mma.ws.cta_group.kind.collector::b2::use [d_tmem], a_desc, b_desc, idesc, enable_input_d,
+zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_101a
+// .cta_group = { .cta_group::1 }
+// .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+template <cuda::ptx::dot_kind Kind>
+__device__ static inline void tcgen05_mma_ws_collector_b2_use(
+  cuda::ptx::cta_group_1_t,
+  cuda::ptx::kind_t<Kind> kind,
+  uint32_t d_tmem,
+  uint64_t a_desc,
+  uint64_t b_desc,
+  uint32_t idesc,
+  bool enable_input_d,
+  uint64_t zero_column_mask_desc);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_mma_ws_collector_b2_use_is_not_supported_before_SM_100a_SM_101a__();
+template <dot_kind _Kind>
+_CCCL_DEVICE static inline void tcgen05_mma_ws_collector_b2_use(
+  cta_group_1_t,
+  kind_t<_Kind> __kind,
+  _CUDA_VSTD::uint32_t __d_tmem,
+  _CUDA_VSTD::uint64_t __a_desc,
+  _CUDA_VSTD::uint64_t __b_desc,
+  _CUDA_VSTD::uint32_t __idesc,
+  bool __enable_input_d,
+  _CUDA_VSTD::uint64_t __zero_column_mask_desc)
+{
+  // __cta_group == cta_group_1 (due to parameter type constraint)
+  static_assert(__kind == kind_f16 || __kind == kind_tf32 || __kind == kind_f8f6f4 || __kind == kind_i8, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  _CCCL_IF_CONSTEXPR (__kind == kind_f16)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b2::use [%0], %1, %2, %3, PRED_enable_input_d, %5;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d)),
+        "l"(__zero_column_mask_desc)
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_tf32)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b2::use [%0], %1, %2, %3, PRED_enable_input_d, %5;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d)),
+        "l"(__zero_column_mask_desc)
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_f8f6f4)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b2::use [%0], %1, %2, %3, PRED_enable_input_d, %5;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d)),
+        "l"(__zero_column_mask_desc)
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_i8)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b2::use [%0], %1, %2, %3, PRED_enable_input_d, %5;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d)),
+        "l"(__zero_column_mask_desc)
+      : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_mma_ws_collector_b2_use_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.mma.ws.cta_group.kind.collector::b2::use [d_tmem], a_desc, b_desc, idesc, enable_input_d; // PTX ISA 86,
+SM_100a, SM_101a
+// .cta_group = { .cta_group::1 }
+// .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+template <cuda::ptx::dot_kind Kind>
+__device__ static inline void tcgen05_mma_ws_collector_b2_use(
+  cuda::ptx::cta_group_1_t,
+  cuda::ptx::kind_t<Kind> kind,
+  uint32_t d_tmem,
+  uint64_t a_desc,
+  uint64_t b_desc,
+  uint32_t idesc,
+  bool enable_input_d);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_mma_ws_collector_b2_use_is_not_supported_before_SM_100a_SM_101a__();
+template <dot_kind _Kind>
+_CCCL_DEVICE static inline void tcgen05_mma_ws_collector_b2_use(
+  cta_group_1_t,
+  kind_t<_Kind> __kind,
+  _CUDA_VSTD::uint32_t __d_tmem,
+  _CUDA_VSTD::uint64_t __a_desc,
+  _CUDA_VSTD::uint64_t __b_desc,
+  _CUDA_VSTD::uint32_t __idesc,
+  bool __enable_input_d)
+{
+  // __cta_group == cta_group_1 (due to parameter type constraint)
+  static_assert(__kind == kind_f16 || __kind == kind_tf32 || __kind == kind_f8f6f4 || __kind == kind_i8, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  _CCCL_IF_CONSTEXPR (__kind == kind_f16)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b2::use [%0], %1, %2, %3, PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_tf32)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b2::use [%0], %1, %2, %3, PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_f8f6f4)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b2::use [%0], %1, %2, %3, PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_i8)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b2::use [%0], %1, %2, %3, PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_mma_ws_collector_b2_use_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.mma.ws.cta_group.kind.collector::b2::use [d_tmem], [a_tmem], b_desc, idesc, enable_input_d,
+zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_101a
+// .cta_group = { .cta_group::1 }
+// .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+template <cuda::ptx::dot_kind Kind>
+__device__ static inline void tcgen05_mma_ws_tmem_a_collector_b2_use(
+  cuda::ptx::cta_group_1_t,
+  cuda::ptx::kind_t<Kind> kind,
+  uint32_t d_tmem,
+  uint32_t a_tmem,
+  uint64_t b_desc,
+  uint32_t idesc,
+  bool enable_input_d,
+  uint64_t zero_column_mask_desc);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void
+__cuda_ptx_tcgen05_mma_ws_tmem_a_collector_b2_use_is_not_supported_before_SM_100a_SM_101a__();
+template <dot_kind _Kind>
+_CCCL_DEVICE static inline void tcgen05_mma_ws_tmem_a_collector_b2_use(
+  cta_group_1_t,
+  kind_t<_Kind> __kind,
+  _CUDA_VSTD::uint32_t __d_tmem,
+  _CUDA_VSTD::uint32_t __a_tmem,
+  _CUDA_VSTD::uint64_t __b_desc,
+  _CUDA_VSTD::uint32_t __idesc,
+  bool __enable_input_d,
+  _CUDA_VSTD::uint64_t __zero_column_mask_desc)
+{
+  // __cta_group == cta_group_1 (due to parameter type constraint)
+  static_assert(__kind == kind_f16 || __kind == kind_tf32 || __kind == kind_f8f6f4 || __kind == kind_i8, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  _CCCL_IF_CONSTEXPR (__kind == kind_f16)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b2::use [%0], [%1], %2, %3, PRED_enable_input_d, %5;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "r"(__a_tmem),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d)),
+        "l"(__zero_column_mask_desc)
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_tf32)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b2::use [%0], [%1], %2, %3, PRED_enable_input_d, %5;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "r"(__a_tmem),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d)),
+        "l"(__zero_column_mask_desc)
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_f8f6f4)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b2::use [%0], [%1], %2, %3, PRED_enable_input_d, %5;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "r"(__a_tmem),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d)),
+        "l"(__zero_column_mask_desc)
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_i8)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b2::use [%0], [%1], %2, %3, PRED_enable_input_d, %5;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "r"(__a_tmem),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d)),
+        "l"(__zero_column_mask_desc)
+      : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_mma_ws_tmem_a_collector_b2_use_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.mma.ws.cta_group.kind.collector::b2::use [d_tmem], [a_tmem], b_desc, idesc, enable_input_d; // PTX ISA 86,
+SM_100a, SM_101a
+// .cta_group = { .cta_group::1 }
+// .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+template <cuda::ptx::dot_kind Kind>
+__device__ static inline void tcgen05_mma_ws_tmem_a_collector_b2_use(
+  cuda::ptx::cta_group_1_t,
+  cuda::ptx::kind_t<Kind> kind,
+  uint32_t d_tmem,
+  uint32_t a_tmem,
+  uint64_t b_desc,
+  uint32_t idesc,
+  bool enable_input_d);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void
+__cuda_ptx_tcgen05_mma_ws_tmem_a_collector_b2_use_is_not_supported_before_SM_100a_SM_101a__();
+template <dot_kind _Kind>
+_CCCL_DEVICE static inline void tcgen05_mma_ws_tmem_a_collector_b2_use(
+  cta_group_1_t,
+  kind_t<_Kind> __kind,
+  _CUDA_VSTD::uint32_t __d_tmem,
+  _CUDA_VSTD::uint32_t __a_tmem,
+  _CUDA_VSTD::uint64_t __b_desc,
+  _CUDA_VSTD::uint32_t __idesc,
+  bool __enable_input_d)
+{
+  // __cta_group == cta_group_1 (due to parameter type constraint)
+  static_assert(__kind == kind_f16 || __kind == kind_tf32 || __kind == kind_f8f6f4 || __kind == kind_i8, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  _CCCL_IF_CONSTEXPR (__kind == kind_f16)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b2::use [%0], [%1], %2, %3, PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "r"(__a_tmem),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_tf32)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b2::use [%0], [%1], %2, %3, PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "r"(__a_tmem),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_f8f6f4)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b2::use [%0], [%1], %2, %3, PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "r"(__a_tmem),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_i8)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b2::use [%0], [%1], %2, %3, PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "r"(__a_tmem),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_mma_ws_tmem_a_collector_b2_use_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.mma.ws.cta_group.kind.collector::b2::lastuse [d_tmem], a_desc, b_desc, idesc, enable_input_d,
+zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_101a
+// .cta_group = { .cta_group::1 }
+// .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+template <cuda::ptx::dot_kind Kind>
+__device__ static inline void tcgen05_mma_ws_collector_b2_lastuse(
+  cuda::ptx::cta_group_1_t,
+  cuda::ptx::kind_t<Kind> kind,
+  uint32_t d_tmem,
+  uint64_t a_desc,
+  uint64_t b_desc,
+  uint32_t idesc,
+  bool enable_input_d,
+  uint64_t zero_column_mask_desc);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_mma_ws_collector_b2_lastuse_is_not_supported_before_SM_100a_SM_101a__();
+template <dot_kind _Kind>
+_CCCL_DEVICE static inline void tcgen05_mma_ws_collector_b2_lastuse(
+  cta_group_1_t,
+  kind_t<_Kind> __kind,
+  _CUDA_VSTD::uint32_t __d_tmem,
+  _CUDA_VSTD::uint64_t __a_desc,
+  _CUDA_VSTD::uint64_t __b_desc,
+  _CUDA_VSTD::uint32_t __idesc,
+  bool __enable_input_d,
+  _CUDA_VSTD::uint64_t __zero_column_mask_desc)
+{
+  // __cta_group == cta_group_1 (due to parameter type constraint)
+  static_assert(__kind == kind_f16 || __kind == kind_tf32 || __kind == kind_f8f6f4 || __kind == kind_i8, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  _CCCL_IF_CONSTEXPR (__kind == kind_f16)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b2::lastuse [%0], %1, %2, %3, PRED_enable_input_d, %5;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d)),
+        "l"(__zero_column_mask_desc)
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_tf32)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b2::lastuse [%0], %1, %2, %3, PRED_enable_input_d, %5;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d)),
+        "l"(__zero_column_mask_desc)
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_f8f6f4)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b2::lastuse [%0], %1, %2, %3, PRED_enable_input_d, %5;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d)),
+        "l"(__zero_column_mask_desc)
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_i8)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b2::lastuse [%0], %1, %2, %3, PRED_enable_input_d, %5;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d)),
+        "l"(__zero_column_mask_desc)
+      : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_mma_ws_collector_b2_lastuse_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.mma.ws.cta_group.kind.collector::b2::lastuse [d_tmem], a_desc, b_desc, idesc, enable_input_d; // PTX ISA 86,
+SM_100a, SM_101a
+// .cta_group = { .cta_group::1 }
+// .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+template <cuda::ptx::dot_kind Kind>
+__device__ static inline void tcgen05_mma_ws_collector_b2_lastuse(
+  cuda::ptx::cta_group_1_t,
+  cuda::ptx::kind_t<Kind> kind,
+  uint32_t d_tmem,
+  uint64_t a_desc,
+  uint64_t b_desc,
+  uint32_t idesc,
+  bool enable_input_d);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_mma_ws_collector_b2_lastuse_is_not_supported_before_SM_100a_SM_101a__();
+template <dot_kind _Kind>
+_CCCL_DEVICE static inline void tcgen05_mma_ws_collector_b2_lastuse(
+  cta_group_1_t,
+  kind_t<_Kind> __kind,
+  _CUDA_VSTD::uint32_t __d_tmem,
+  _CUDA_VSTD::uint64_t __a_desc,
+  _CUDA_VSTD::uint64_t __b_desc,
+  _CUDA_VSTD::uint32_t __idesc,
+  bool __enable_input_d)
+{
+  // __cta_group == cta_group_1 (due to parameter type constraint)
+  static_assert(__kind == kind_f16 || __kind == kind_tf32 || __kind == kind_f8f6f4 || __kind == kind_i8, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  _CCCL_IF_CONSTEXPR (__kind == kind_f16)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b2::lastuse [%0], %1, %2, %3, PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_tf32)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b2::lastuse [%0], %1, %2, %3, PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_f8f6f4)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b2::lastuse [%0], %1, %2, %3, PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_i8)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b2::lastuse [%0], %1, %2, %3, PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_mma_ws_collector_b2_lastuse_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.mma.ws.cta_group.kind.collector::b2::lastuse [d_tmem], [a_tmem], b_desc, idesc, enable_input_d,
+zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_101a
+// .cta_group = { .cta_group::1 }
+// .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+template <cuda::ptx::dot_kind Kind>
+__device__ static inline void tcgen05_mma_ws_tmem_a_collector_b2_lastuse(
+  cuda::ptx::cta_group_1_t,
+  cuda::ptx::kind_t<Kind> kind,
+  uint32_t d_tmem,
+  uint32_t a_tmem,
+  uint64_t b_desc,
+  uint32_t idesc,
+  bool enable_input_d,
+  uint64_t zero_column_mask_desc);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void
+__cuda_ptx_tcgen05_mma_ws_tmem_a_collector_b2_lastuse_is_not_supported_before_SM_100a_SM_101a__();
+template <dot_kind _Kind>
+_CCCL_DEVICE static inline void tcgen05_mma_ws_tmem_a_collector_b2_lastuse(
+  cta_group_1_t,
+  kind_t<_Kind> __kind,
+  _CUDA_VSTD::uint32_t __d_tmem,
+  _CUDA_VSTD::uint32_t __a_tmem,
+  _CUDA_VSTD::uint64_t __b_desc,
+  _CUDA_VSTD::uint32_t __idesc,
+  bool __enable_input_d,
+  _CUDA_VSTD::uint64_t __zero_column_mask_desc)
+{
+  // __cta_group == cta_group_1 (due to parameter type constraint)
+  static_assert(__kind == kind_f16 || __kind == kind_tf32 || __kind == kind_f8f6f4 || __kind == kind_i8, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  _CCCL_IF_CONSTEXPR (__kind == kind_f16)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b2::lastuse [%0], [%1], %2, %3, PRED_enable_input_d, %5;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "r"(__a_tmem),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d)),
+        "l"(__zero_column_mask_desc)
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_tf32)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b2::lastuse [%0], [%1], %2, %3, PRED_enable_input_d, %5;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "r"(__a_tmem),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d)),
+        "l"(__zero_column_mask_desc)
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_f8f6f4)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b2::lastuse [%0], [%1], %2, %3, PRED_enable_input_d, %5;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "r"(__a_tmem),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d)),
+        "l"(__zero_column_mask_desc)
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_i8)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b2::lastuse [%0], [%1], %2, %3, PRED_enable_input_d, %5;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "r"(__a_tmem),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d)),
+        "l"(__zero_column_mask_desc)
+      : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_mma_ws_tmem_a_collector_b2_lastuse_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.mma.ws.cta_group.kind.collector::b2::lastuse [d_tmem], [a_tmem], b_desc, idesc, enable_input_d; // PTX ISA
+86, SM_100a, SM_101a
+// .cta_group = { .cta_group::1 }
+// .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+template <cuda::ptx::dot_kind Kind>
+__device__ static inline void tcgen05_mma_ws_tmem_a_collector_b2_lastuse(
+  cuda::ptx::cta_group_1_t,
+  cuda::ptx::kind_t<Kind> kind,
+  uint32_t d_tmem,
+  uint32_t a_tmem,
+  uint64_t b_desc,
+  uint32_t idesc,
+  bool enable_input_d);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void
+__cuda_ptx_tcgen05_mma_ws_tmem_a_collector_b2_lastuse_is_not_supported_before_SM_100a_SM_101a__();
+template <dot_kind _Kind>
+_CCCL_DEVICE static inline void tcgen05_mma_ws_tmem_a_collector_b2_lastuse(
+  cta_group_1_t,
+  kind_t<_Kind> __kind,
+  _CUDA_VSTD::uint32_t __d_tmem,
+  _CUDA_VSTD::uint32_t __a_tmem,
+  _CUDA_VSTD::uint64_t __b_desc,
+  _CUDA_VSTD::uint32_t __idesc,
+  bool __enable_input_d)
+{
+  // __cta_group == cta_group_1 (due to parameter type constraint)
+  static_assert(__kind == kind_f16 || __kind == kind_tf32 || __kind == kind_f8f6f4 || __kind == kind_i8, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  _CCCL_IF_CONSTEXPR (__kind == kind_f16)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b2::lastuse [%0], [%1], %2, %3, PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "r"(__a_tmem),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_tf32)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b2::lastuse [%0], [%1], %2, %3, PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "r"(__a_tmem),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_f8f6f4)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b2::lastuse [%0], [%1], %2, %3, PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "r"(__a_tmem),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_i8)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b2::lastuse [%0], [%1], %2, %3, PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "r"(__a_tmem),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_mma_ws_tmem_a_collector_b2_lastuse_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.mma.ws.cta_group.kind.collector::b2::discard [d_tmem], a_desc, b_desc, idesc, enable_input_d,
+zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_101a
+// .cta_group = { .cta_group::1 }
+// .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+template <cuda::ptx::dot_kind Kind>
+__device__ static inline void tcgen05_mma_ws_collector_b2_discard(
+  cuda::ptx::cta_group_1_t,
+  cuda::ptx::kind_t<Kind> kind,
+  uint32_t d_tmem,
+  uint64_t a_desc,
+  uint64_t b_desc,
+  uint32_t idesc,
+  bool enable_input_d,
+  uint64_t zero_column_mask_desc);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_mma_ws_collector_b2_discard_is_not_supported_before_SM_100a_SM_101a__();
+template <dot_kind _Kind>
+_CCCL_DEVICE static inline void tcgen05_mma_ws_collector_b2_discard(
+  cta_group_1_t,
+  kind_t<_Kind> __kind,
+  _CUDA_VSTD::uint32_t __d_tmem,
+  _CUDA_VSTD::uint64_t __a_desc,
+  _CUDA_VSTD::uint64_t __b_desc,
+  _CUDA_VSTD::uint32_t __idesc,
+  bool __enable_input_d,
+  _CUDA_VSTD::uint64_t __zero_column_mask_desc)
+{
+  // __cta_group == cta_group_1 (due to parameter type constraint)
+  static_assert(__kind == kind_f16 || __kind == kind_tf32 || __kind == kind_f8f6f4 || __kind == kind_i8, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  _CCCL_IF_CONSTEXPR (__kind == kind_f16)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b2::discard [%0], %1, %2, %3, PRED_enable_input_d, %5;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d)),
+        "l"(__zero_column_mask_desc)
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_tf32)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b2::discard [%0], %1, %2, %3, PRED_enable_input_d, %5;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d)),
+        "l"(__zero_column_mask_desc)
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_f8f6f4)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b2::discard [%0], %1, %2, %3, PRED_enable_input_d, %5;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d)),
+        "l"(__zero_column_mask_desc)
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_i8)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b2::discard [%0], %1, %2, %3, PRED_enable_input_d, %5;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d)),
+        "l"(__zero_column_mask_desc)
+      : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_mma_ws_collector_b2_discard_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.mma.ws.cta_group.kind.collector::b2::discard [d_tmem], a_desc, b_desc, idesc, enable_input_d; // PTX ISA 86,
+SM_100a, SM_101a
+// .cta_group = { .cta_group::1 }
+// .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+template <cuda::ptx::dot_kind Kind>
+__device__ static inline void tcgen05_mma_ws_collector_b2_discard(
+  cuda::ptx::cta_group_1_t,
+  cuda::ptx::kind_t<Kind> kind,
+  uint32_t d_tmem,
+  uint64_t a_desc,
+  uint64_t b_desc,
+  uint32_t idesc,
+  bool enable_input_d);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_mma_ws_collector_b2_discard_is_not_supported_before_SM_100a_SM_101a__();
+template <dot_kind _Kind>
+_CCCL_DEVICE static inline void tcgen05_mma_ws_collector_b2_discard(
+  cta_group_1_t,
+  kind_t<_Kind> __kind,
+  _CUDA_VSTD::uint32_t __d_tmem,
+  _CUDA_VSTD::uint64_t __a_desc,
+  _CUDA_VSTD::uint64_t __b_desc,
+  _CUDA_VSTD::uint32_t __idesc,
+  bool __enable_input_d)
+{
+  // __cta_group == cta_group_1 (due to parameter type constraint)
+  static_assert(__kind == kind_f16 || __kind == kind_tf32 || __kind == kind_f8f6f4 || __kind == kind_i8, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  _CCCL_IF_CONSTEXPR (__kind == kind_f16)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b2::discard [%0], %1, %2, %3, PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_tf32)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b2::discard [%0], %1, %2, %3, PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_f8f6f4)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b2::discard [%0], %1, %2, %3, PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_i8)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b2::discard [%0], %1, %2, %3, PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_mma_ws_collector_b2_discard_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.mma.ws.cta_group.kind.collector::b2::discard [d_tmem], [a_tmem], b_desc, idesc, enable_input_d,
+zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_101a
+// .cta_group = { .cta_group::1 }
+// .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+template <cuda::ptx::dot_kind Kind>
+__device__ static inline void tcgen05_mma_ws_tmem_a_collector_b2_discard(
+  cuda::ptx::cta_group_1_t,
+  cuda::ptx::kind_t<Kind> kind,
+  uint32_t d_tmem,
+  uint32_t a_tmem,
+  uint64_t b_desc,
+  uint32_t idesc,
+  bool enable_input_d,
+  uint64_t zero_column_mask_desc);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void
+__cuda_ptx_tcgen05_mma_ws_tmem_a_collector_b2_discard_is_not_supported_before_SM_100a_SM_101a__();
+template <dot_kind _Kind>
+_CCCL_DEVICE static inline void tcgen05_mma_ws_tmem_a_collector_b2_discard(
+  cta_group_1_t,
+  kind_t<_Kind> __kind,
+  _CUDA_VSTD::uint32_t __d_tmem,
+  _CUDA_VSTD::uint32_t __a_tmem,
+  _CUDA_VSTD::uint64_t __b_desc,
+  _CUDA_VSTD::uint32_t __idesc,
+  bool __enable_input_d,
+  _CUDA_VSTD::uint64_t __zero_column_mask_desc)
+{
+  // __cta_group == cta_group_1 (due to parameter type constraint)
+  static_assert(__kind == kind_f16 || __kind == kind_tf32 || __kind == kind_f8f6f4 || __kind == kind_i8, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  _CCCL_IF_CONSTEXPR (__kind == kind_f16)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b2::discard [%0], [%1], %2, %3, PRED_enable_input_d, %5;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "r"(__a_tmem),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d)),
+        "l"(__zero_column_mask_desc)
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_tf32)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b2::discard [%0], [%1], %2, %3, PRED_enable_input_d, %5;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "r"(__a_tmem),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d)),
+        "l"(__zero_column_mask_desc)
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_f8f6f4)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b2::discard [%0], [%1], %2, %3, PRED_enable_input_d, %5;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "r"(__a_tmem),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d)),
+        "l"(__zero_column_mask_desc)
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_i8)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b2::discard [%0], [%1], %2, %3, PRED_enable_input_d, %5;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "r"(__a_tmem),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d)),
+        "l"(__zero_column_mask_desc)
+      : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_mma_ws_tmem_a_collector_b2_discard_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.mma.ws.cta_group.kind.collector::b2::discard [d_tmem], [a_tmem], b_desc, idesc, enable_input_d; // PTX ISA
+86, SM_100a, SM_101a
+// .cta_group = { .cta_group::1 }
+// .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+template <cuda::ptx::dot_kind Kind>
+__device__ static inline void tcgen05_mma_ws_tmem_a_collector_b2_discard(
+  cuda::ptx::cta_group_1_t,
+  cuda::ptx::kind_t<Kind> kind,
+  uint32_t d_tmem,
+  uint32_t a_tmem,
+  uint64_t b_desc,
+  uint32_t idesc,
+  bool enable_input_d);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void
+__cuda_ptx_tcgen05_mma_ws_tmem_a_collector_b2_discard_is_not_supported_before_SM_100a_SM_101a__();
+template <dot_kind _Kind>
+_CCCL_DEVICE static inline void tcgen05_mma_ws_tmem_a_collector_b2_discard(
+  cta_group_1_t,
+  kind_t<_Kind> __kind,
+  _CUDA_VSTD::uint32_t __d_tmem,
+  _CUDA_VSTD::uint32_t __a_tmem,
+  _CUDA_VSTD::uint64_t __b_desc,
+  _CUDA_VSTD::uint32_t __idesc,
+  bool __enable_input_d)
+{
+  // __cta_group == cta_group_1 (due to parameter type constraint)
+  static_assert(__kind == kind_f16 || __kind == kind_tf32 || __kind == kind_f8f6f4 || __kind == kind_i8, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  _CCCL_IF_CONSTEXPR (__kind == kind_f16)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b2::discard [%0], [%1], %2, %3, PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "r"(__a_tmem),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_tf32)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b2::discard [%0], [%1], %2, %3, PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "r"(__a_tmem),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_f8f6f4)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b2::discard [%0], [%1], %2, %3, PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "r"(__a_tmem),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_i8)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b2::discard [%0], [%1], %2, %3, PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "r"(__a_tmem),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_mma_ws_tmem_a_collector_b2_discard_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.mma.ws.cta_group.kind.collector::b3::fill [d_tmem], a_desc, b_desc, idesc, enable_input_d,
+zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_101a
+// .cta_group = { .cta_group::1 }
+// .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+template <cuda::ptx::dot_kind Kind>
+__device__ static inline void tcgen05_mma_ws_collector_b3_fill(
+  cuda::ptx::cta_group_1_t,
+  cuda::ptx::kind_t<Kind> kind,
+  uint32_t d_tmem,
+  uint64_t a_desc,
+  uint64_t b_desc,
+  uint32_t idesc,
+  bool enable_input_d,
+  uint64_t zero_column_mask_desc);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_mma_ws_collector_b3_fill_is_not_supported_before_SM_100a_SM_101a__();
+template <dot_kind _Kind>
+_CCCL_DEVICE static inline void tcgen05_mma_ws_collector_b3_fill(
+  cta_group_1_t,
+  kind_t<_Kind> __kind,
+  _CUDA_VSTD::uint32_t __d_tmem,
+  _CUDA_VSTD::uint64_t __a_desc,
+  _CUDA_VSTD::uint64_t __b_desc,
+  _CUDA_VSTD::uint32_t __idesc,
+  bool __enable_input_d,
+  _CUDA_VSTD::uint64_t __zero_column_mask_desc)
+{
+  // __cta_group == cta_group_1 (due to parameter type constraint)
+  static_assert(__kind == kind_f16 || __kind == kind_tf32 || __kind == kind_f8f6f4 || __kind == kind_i8, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  _CCCL_IF_CONSTEXPR (__kind == kind_f16)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b3::fill [%0], %1, %2, %3, PRED_enable_input_d, %5;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d)),
+        "l"(__zero_column_mask_desc)
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_tf32)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b3::fill [%0], %1, %2, %3, PRED_enable_input_d, %5;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d)),
+        "l"(__zero_column_mask_desc)
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_f8f6f4)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b3::fill [%0], %1, %2, %3, PRED_enable_input_d, %5;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d)),
+        "l"(__zero_column_mask_desc)
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_i8)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b3::fill [%0], %1, %2, %3, PRED_enable_input_d, %5;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d)),
+        "l"(__zero_column_mask_desc)
+      : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_mma_ws_collector_b3_fill_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.mma.ws.cta_group.kind.collector::b3::fill [d_tmem], a_desc, b_desc, idesc, enable_input_d; // PTX ISA 86,
+SM_100a, SM_101a
+// .cta_group = { .cta_group::1 }
+// .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+template <cuda::ptx::dot_kind Kind>
+__device__ static inline void tcgen05_mma_ws_collector_b3_fill(
+  cuda::ptx::cta_group_1_t,
+  cuda::ptx::kind_t<Kind> kind,
+  uint32_t d_tmem,
+  uint64_t a_desc,
+  uint64_t b_desc,
+  uint32_t idesc,
+  bool enable_input_d);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_mma_ws_collector_b3_fill_is_not_supported_before_SM_100a_SM_101a__();
+template <dot_kind _Kind>
+_CCCL_DEVICE static inline void tcgen05_mma_ws_collector_b3_fill(
+  cta_group_1_t,
+  kind_t<_Kind> __kind,
+  _CUDA_VSTD::uint32_t __d_tmem,
+  _CUDA_VSTD::uint64_t __a_desc,
+  _CUDA_VSTD::uint64_t __b_desc,
+  _CUDA_VSTD::uint32_t __idesc,
+  bool __enable_input_d)
+{
+  // __cta_group == cta_group_1 (due to parameter type constraint)
+  static_assert(__kind == kind_f16 || __kind == kind_tf32 || __kind == kind_f8f6f4 || __kind == kind_i8, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  _CCCL_IF_CONSTEXPR (__kind == kind_f16)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b3::fill [%0], %1, %2, %3, PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_tf32)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b3::fill [%0], %1, %2, %3, PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_f8f6f4)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b3::fill [%0], %1, %2, %3, PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_i8)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b3::fill [%0], %1, %2, %3, PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_mma_ws_collector_b3_fill_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.mma.ws.cta_group.kind.collector::b3::fill [d_tmem], [a_tmem], b_desc, idesc, enable_input_d,
+zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_101a
+// .cta_group = { .cta_group::1 }
+// .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+template <cuda::ptx::dot_kind Kind>
+__device__ static inline void tcgen05_mma_ws_tmem_a_collector_b3_fill(
+  cuda::ptx::cta_group_1_t,
+  cuda::ptx::kind_t<Kind> kind,
+  uint32_t d_tmem,
+  uint32_t a_tmem,
+  uint64_t b_desc,
+  uint32_t idesc,
+  bool enable_input_d,
+  uint64_t zero_column_mask_desc);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void
+__cuda_ptx_tcgen05_mma_ws_tmem_a_collector_b3_fill_is_not_supported_before_SM_100a_SM_101a__();
+template <dot_kind _Kind>
+_CCCL_DEVICE static inline void tcgen05_mma_ws_tmem_a_collector_b3_fill(
+  cta_group_1_t,
+  kind_t<_Kind> __kind,
+  _CUDA_VSTD::uint32_t __d_tmem,
+  _CUDA_VSTD::uint32_t __a_tmem,
+  _CUDA_VSTD::uint64_t __b_desc,
+  _CUDA_VSTD::uint32_t __idesc,
+  bool __enable_input_d,
+  _CUDA_VSTD::uint64_t __zero_column_mask_desc)
+{
+  // __cta_group == cta_group_1 (due to parameter type constraint)
+  static_assert(__kind == kind_f16 || __kind == kind_tf32 || __kind == kind_f8f6f4 || __kind == kind_i8, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  _CCCL_IF_CONSTEXPR (__kind == kind_f16)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b3::fill [%0], [%1], %2, %3, PRED_enable_input_d, %5;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "r"(__a_tmem),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d)),
+        "l"(__zero_column_mask_desc)
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_tf32)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b3::fill [%0], [%1], %2, %3, PRED_enable_input_d, %5;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "r"(__a_tmem),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d)),
+        "l"(__zero_column_mask_desc)
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_f8f6f4)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b3::fill [%0], [%1], %2, %3, PRED_enable_input_d, %5;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "r"(__a_tmem),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d)),
+        "l"(__zero_column_mask_desc)
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_i8)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b3::fill [%0], [%1], %2, %3, PRED_enable_input_d, %5;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "r"(__a_tmem),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d)),
+        "l"(__zero_column_mask_desc)
+      : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_mma_ws_tmem_a_collector_b3_fill_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.mma.ws.cta_group.kind.collector::b3::fill [d_tmem], [a_tmem], b_desc, idesc, enable_input_d; // PTX ISA 86,
+SM_100a, SM_101a
+// .cta_group = { .cta_group::1 }
+// .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+template <cuda::ptx::dot_kind Kind>
+__device__ static inline void tcgen05_mma_ws_tmem_a_collector_b3_fill(
+  cuda::ptx::cta_group_1_t,
+  cuda::ptx::kind_t<Kind> kind,
+  uint32_t d_tmem,
+  uint32_t a_tmem,
+  uint64_t b_desc,
+  uint32_t idesc,
+  bool enable_input_d);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void
+__cuda_ptx_tcgen05_mma_ws_tmem_a_collector_b3_fill_is_not_supported_before_SM_100a_SM_101a__();
+template <dot_kind _Kind>
+_CCCL_DEVICE static inline void tcgen05_mma_ws_tmem_a_collector_b3_fill(
+  cta_group_1_t,
+  kind_t<_Kind> __kind,
+  _CUDA_VSTD::uint32_t __d_tmem,
+  _CUDA_VSTD::uint32_t __a_tmem,
+  _CUDA_VSTD::uint64_t __b_desc,
+  _CUDA_VSTD::uint32_t __idesc,
+  bool __enable_input_d)
+{
+  // __cta_group == cta_group_1 (due to parameter type constraint)
+  static_assert(__kind == kind_f16 || __kind == kind_tf32 || __kind == kind_f8f6f4 || __kind == kind_i8, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  _CCCL_IF_CONSTEXPR (__kind == kind_f16)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b3::fill [%0], [%1], %2, %3, PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "r"(__a_tmem),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_tf32)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b3::fill [%0], [%1], %2, %3, PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "r"(__a_tmem),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_f8f6f4)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b3::fill [%0], [%1], %2, %3, PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "r"(__a_tmem),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_i8)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b3::fill [%0], [%1], %2, %3, PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "r"(__a_tmem),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_mma_ws_tmem_a_collector_b3_fill_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.mma.ws.cta_group.kind.collector::b3::use [d_tmem], a_desc, b_desc, idesc, enable_input_d,
+zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_101a
+// .cta_group = { .cta_group::1 }
+// .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+template <cuda::ptx::dot_kind Kind>
+__device__ static inline void tcgen05_mma_ws_collector_b3_use(
+  cuda::ptx::cta_group_1_t,
+  cuda::ptx::kind_t<Kind> kind,
+  uint32_t d_tmem,
+  uint64_t a_desc,
+  uint64_t b_desc,
+  uint32_t idesc,
+  bool enable_input_d,
+  uint64_t zero_column_mask_desc);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_mma_ws_collector_b3_use_is_not_supported_before_SM_100a_SM_101a__();
+template <dot_kind _Kind>
+_CCCL_DEVICE static inline void tcgen05_mma_ws_collector_b3_use(
+  cta_group_1_t,
+  kind_t<_Kind> __kind,
+  _CUDA_VSTD::uint32_t __d_tmem,
+  _CUDA_VSTD::uint64_t __a_desc,
+  _CUDA_VSTD::uint64_t __b_desc,
+  _CUDA_VSTD::uint32_t __idesc,
+  bool __enable_input_d,
+  _CUDA_VSTD::uint64_t __zero_column_mask_desc)
+{
+  // __cta_group == cta_group_1 (due to parameter type constraint)
+  static_assert(__kind == kind_f16 || __kind == kind_tf32 || __kind == kind_f8f6f4 || __kind == kind_i8, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  _CCCL_IF_CONSTEXPR (__kind == kind_f16)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b3::use [%0], %1, %2, %3, PRED_enable_input_d, %5;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d)),
+        "l"(__zero_column_mask_desc)
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_tf32)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b3::use [%0], %1, %2, %3, PRED_enable_input_d, %5;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d)),
+        "l"(__zero_column_mask_desc)
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_f8f6f4)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b3::use [%0], %1, %2, %3, PRED_enable_input_d, %5;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d)),
+        "l"(__zero_column_mask_desc)
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_i8)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b3::use [%0], %1, %2, %3, PRED_enable_input_d, %5;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d)),
+        "l"(__zero_column_mask_desc)
+      : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_mma_ws_collector_b3_use_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.mma.ws.cta_group.kind.collector::b3::use [d_tmem], a_desc, b_desc, idesc, enable_input_d; // PTX ISA 86,
+SM_100a, SM_101a
+// .cta_group = { .cta_group::1 }
+// .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+template <cuda::ptx::dot_kind Kind>
+__device__ static inline void tcgen05_mma_ws_collector_b3_use(
+  cuda::ptx::cta_group_1_t,
+  cuda::ptx::kind_t<Kind> kind,
+  uint32_t d_tmem,
+  uint64_t a_desc,
+  uint64_t b_desc,
+  uint32_t idesc,
+  bool enable_input_d);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_mma_ws_collector_b3_use_is_not_supported_before_SM_100a_SM_101a__();
+template <dot_kind _Kind>
+_CCCL_DEVICE static inline void tcgen05_mma_ws_collector_b3_use(
+  cta_group_1_t,
+  kind_t<_Kind> __kind,
+  _CUDA_VSTD::uint32_t __d_tmem,
+  _CUDA_VSTD::uint64_t __a_desc,
+  _CUDA_VSTD::uint64_t __b_desc,
+  _CUDA_VSTD::uint32_t __idesc,
+  bool __enable_input_d)
+{
+  // __cta_group == cta_group_1 (due to parameter type constraint)
+  static_assert(__kind == kind_f16 || __kind == kind_tf32 || __kind == kind_f8f6f4 || __kind == kind_i8, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  _CCCL_IF_CONSTEXPR (__kind == kind_f16)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b3::use [%0], %1, %2, %3, PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_tf32)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b3::use [%0], %1, %2, %3, PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_f8f6f4)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b3::use [%0], %1, %2, %3, PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_i8)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b3::use [%0], %1, %2, %3, PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_mma_ws_collector_b3_use_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.mma.ws.cta_group.kind.collector::b3::use [d_tmem], [a_tmem], b_desc, idesc, enable_input_d,
+zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_101a
+// .cta_group = { .cta_group::1 }
+// .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+template <cuda::ptx::dot_kind Kind>
+__device__ static inline void tcgen05_mma_ws_tmem_a_collector_b3_use(
+  cuda::ptx::cta_group_1_t,
+  cuda::ptx::kind_t<Kind> kind,
+  uint32_t d_tmem,
+  uint32_t a_tmem,
+  uint64_t b_desc,
+  uint32_t idesc,
+  bool enable_input_d,
+  uint64_t zero_column_mask_desc);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void
+__cuda_ptx_tcgen05_mma_ws_tmem_a_collector_b3_use_is_not_supported_before_SM_100a_SM_101a__();
+template <dot_kind _Kind>
+_CCCL_DEVICE static inline void tcgen05_mma_ws_tmem_a_collector_b3_use(
+  cta_group_1_t,
+  kind_t<_Kind> __kind,
+  _CUDA_VSTD::uint32_t __d_tmem,
+  _CUDA_VSTD::uint32_t __a_tmem,
+  _CUDA_VSTD::uint64_t __b_desc,
+  _CUDA_VSTD::uint32_t __idesc,
+  bool __enable_input_d,
+  _CUDA_VSTD::uint64_t __zero_column_mask_desc)
+{
+  // __cta_group == cta_group_1 (due to parameter type constraint)
+  static_assert(__kind == kind_f16 || __kind == kind_tf32 || __kind == kind_f8f6f4 || __kind == kind_i8, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  _CCCL_IF_CONSTEXPR (__kind == kind_f16)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b3::use [%0], [%1], %2, %3, PRED_enable_input_d, %5;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "r"(__a_tmem),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d)),
+        "l"(__zero_column_mask_desc)
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_tf32)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b3::use [%0], [%1], %2, %3, PRED_enable_input_d, %5;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "r"(__a_tmem),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d)),
+        "l"(__zero_column_mask_desc)
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_f8f6f4)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b3::use [%0], [%1], %2, %3, PRED_enable_input_d, %5;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "r"(__a_tmem),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d)),
+        "l"(__zero_column_mask_desc)
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_i8)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b3::use [%0], [%1], %2, %3, PRED_enable_input_d, %5;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "r"(__a_tmem),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d)),
+        "l"(__zero_column_mask_desc)
+      : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_mma_ws_tmem_a_collector_b3_use_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.mma.ws.cta_group.kind.collector::b3::use [d_tmem], [a_tmem], b_desc, idesc, enable_input_d; // PTX ISA 86,
+SM_100a, SM_101a
+// .cta_group = { .cta_group::1 }
+// .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+template <cuda::ptx::dot_kind Kind>
+__device__ static inline void tcgen05_mma_ws_tmem_a_collector_b3_use(
+  cuda::ptx::cta_group_1_t,
+  cuda::ptx::kind_t<Kind> kind,
+  uint32_t d_tmem,
+  uint32_t a_tmem,
+  uint64_t b_desc,
+  uint32_t idesc,
+  bool enable_input_d);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void
+__cuda_ptx_tcgen05_mma_ws_tmem_a_collector_b3_use_is_not_supported_before_SM_100a_SM_101a__();
+template <dot_kind _Kind>
+_CCCL_DEVICE static inline void tcgen05_mma_ws_tmem_a_collector_b3_use(
+  cta_group_1_t,
+  kind_t<_Kind> __kind,
+  _CUDA_VSTD::uint32_t __d_tmem,
+  _CUDA_VSTD::uint32_t __a_tmem,
+  _CUDA_VSTD::uint64_t __b_desc,
+  _CUDA_VSTD::uint32_t __idesc,
+  bool __enable_input_d)
+{
+  // __cta_group == cta_group_1 (due to parameter type constraint)
+  static_assert(__kind == kind_f16 || __kind == kind_tf32 || __kind == kind_f8f6f4 || __kind == kind_i8, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  _CCCL_IF_CONSTEXPR (__kind == kind_f16)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b3::use [%0], [%1], %2, %3, PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "r"(__a_tmem),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_tf32)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b3::use [%0], [%1], %2, %3, PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "r"(__a_tmem),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_f8f6f4)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b3::use [%0], [%1], %2, %3, PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "r"(__a_tmem),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_i8)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b3::use [%0], [%1], %2, %3, PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "r"(__a_tmem),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_mma_ws_tmem_a_collector_b3_use_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.mma.ws.cta_group.kind.collector::b3::lastuse [d_tmem], a_desc, b_desc, idesc, enable_input_d,
+zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_101a
+// .cta_group = { .cta_group::1 }
+// .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+template <cuda::ptx::dot_kind Kind>
+__device__ static inline void tcgen05_mma_ws_collector_b3_lastuse(
+  cuda::ptx::cta_group_1_t,
+  cuda::ptx::kind_t<Kind> kind,
+  uint32_t d_tmem,
+  uint64_t a_desc,
+  uint64_t b_desc,
+  uint32_t idesc,
+  bool enable_input_d,
+  uint64_t zero_column_mask_desc);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_mma_ws_collector_b3_lastuse_is_not_supported_before_SM_100a_SM_101a__();
+template <dot_kind _Kind>
+_CCCL_DEVICE static inline void tcgen05_mma_ws_collector_b3_lastuse(
+  cta_group_1_t,
+  kind_t<_Kind> __kind,
+  _CUDA_VSTD::uint32_t __d_tmem,
+  _CUDA_VSTD::uint64_t __a_desc,
+  _CUDA_VSTD::uint64_t __b_desc,
+  _CUDA_VSTD::uint32_t __idesc,
+  bool __enable_input_d,
+  _CUDA_VSTD::uint64_t __zero_column_mask_desc)
+{
+  // __cta_group == cta_group_1 (due to parameter type constraint)
+  static_assert(__kind == kind_f16 || __kind == kind_tf32 || __kind == kind_f8f6f4 || __kind == kind_i8, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  _CCCL_IF_CONSTEXPR (__kind == kind_f16)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b3::lastuse [%0], %1, %2, %3, PRED_enable_input_d, %5;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d)),
+        "l"(__zero_column_mask_desc)
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_tf32)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b3::lastuse [%0], %1, %2, %3, PRED_enable_input_d, %5;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d)),
+        "l"(__zero_column_mask_desc)
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_f8f6f4)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b3::lastuse [%0], %1, %2, %3, PRED_enable_input_d, %5;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d)),
+        "l"(__zero_column_mask_desc)
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_i8)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b3::lastuse [%0], %1, %2, %3, PRED_enable_input_d, %5;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d)),
+        "l"(__zero_column_mask_desc)
+      : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_mma_ws_collector_b3_lastuse_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.mma.ws.cta_group.kind.collector::b3::lastuse [d_tmem], a_desc, b_desc, idesc, enable_input_d; // PTX ISA 86,
+SM_100a, SM_101a
+// .cta_group = { .cta_group::1 }
+// .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+template <cuda::ptx::dot_kind Kind>
+__device__ static inline void tcgen05_mma_ws_collector_b3_lastuse(
+  cuda::ptx::cta_group_1_t,
+  cuda::ptx::kind_t<Kind> kind,
+  uint32_t d_tmem,
+  uint64_t a_desc,
+  uint64_t b_desc,
+  uint32_t idesc,
+  bool enable_input_d);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_mma_ws_collector_b3_lastuse_is_not_supported_before_SM_100a_SM_101a__();
+template <dot_kind _Kind>
+_CCCL_DEVICE static inline void tcgen05_mma_ws_collector_b3_lastuse(
+  cta_group_1_t,
+  kind_t<_Kind> __kind,
+  _CUDA_VSTD::uint32_t __d_tmem,
+  _CUDA_VSTD::uint64_t __a_desc,
+  _CUDA_VSTD::uint64_t __b_desc,
+  _CUDA_VSTD::uint32_t __idesc,
+  bool __enable_input_d)
+{
+  // __cta_group == cta_group_1 (due to parameter type constraint)
+  static_assert(__kind == kind_f16 || __kind == kind_tf32 || __kind == kind_f8f6f4 || __kind == kind_i8, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  _CCCL_IF_CONSTEXPR (__kind == kind_f16)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b3::lastuse [%0], %1, %2, %3, PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_tf32)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b3::lastuse [%0], %1, %2, %3, PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_f8f6f4)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b3::lastuse [%0], %1, %2, %3, PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_i8)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b3::lastuse [%0], %1, %2, %3, PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_mma_ws_collector_b3_lastuse_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.mma.ws.cta_group.kind.collector::b3::lastuse [d_tmem], [a_tmem], b_desc, idesc, enable_input_d,
+zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_101a
+// .cta_group = { .cta_group::1 }
+// .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+template <cuda::ptx::dot_kind Kind>
+__device__ static inline void tcgen05_mma_ws_tmem_a_collector_b3_lastuse(
+  cuda::ptx::cta_group_1_t,
+  cuda::ptx::kind_t<Kind> kind,
+  uint32_t d_tmem,
+  uint32_t a_tmem,
+  uint64_t b_desc,
+  uint32_t idesc,
+  bool enable_input_d,
+  uint64_t zero_column_mask_desc);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void
+__cuda_ptx_tcgen05_mma_ws_tmem_a_collector_b3_lastuse_is_not_supported_before_SM_100a_SM_101a__();
+template <dot_kind _Kind>
+_CCCL_DEVICE static inline void tcgen05_mma_ws_tmem_a_collector_b3_lastuse(
+  cta_group_1_t,
+  kind_t<_Kind> __kind,
+  _CUDA_VSTD::uint32_t __d_tmem,
+  _CUDA_VSTD::uint32_t __a_tmem,
+  _CUDA_VSTD::uint64_t __b_desc,
+  _CUDA_VSTD::uint32_t __idesc,
+  bool __enable_input_d,
+  _CUDA_VSTD::uint64_t __zero_column_mask_desc)
+{
+  // __cta_group == cta_group_1 (due to parameter type constraint)
+  static_assert(__kind == kind_f16 || __kind == kind_tf32 || __kind == kind_f8f6f4 || __kind == kind_i8, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  _CCCL_IF_CONSTEXPR (__kind == kind_f16)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b3::lastuse [%0], [%1], %2, %3, PRED_enable_input_d, %5;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "r"(__a_tmem),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d)),
+        "l"(__zero_column_mask_desc)
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_tf32)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b3::lastuse [%0], [%1], %2, %3, PRED_enable_input_d, %5;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "r"(__a_tmem),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d)),
+        "l"(__zero_column_mask_desc)
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_f8f6f4)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b3::lastuse [%0], [%1], %2, %3, PRED_enable_input_d, %5;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "r"(__a_tmem),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d)),
+        "l"(__zero_column_mask_desc)
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_i8)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b3::lastuse [%0], [%1], %2, %3, PRED_enable_input_d, %5;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "r"(__a_tmem),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d)),
+        "l"(__zero_column_mask_desc)
+      : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_mma_ws_tmem_a_collector_b3_lastuse_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.mma.ws.cta_group.kind.collector::b3::lastuse [d_tmem], [a_tmem], b_desc, idesc, enable_input_d; // PTX ISA
+86, SM_100a, SM_101a
+// .cta_group = { .cta_group::1 }
+// .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+template <cuda::ptx::dot_kind Kind>
+__device__ static inline void tcgen05_mma_ws_tmem_a_collector_b3_lastuse(
+  cuda::ptx::cta_group_1_t,
+  cuda::ptx::kind_t<Kind> kind,
+  uint32_t d_tmem,
+  uint32_t a_tmem,
+  uint64_t b_desc,
+  uint32_t idesc,
+  bool enable_input_d);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void
+__cuda_ptx_tcgen05_mma_ws_tmem_a_collector_b3_lastuse_is_not_supported_before_SM_100a_SM_101a__();
+template <dot_kind _Kind>
+_CCCL_DEVICE static inline void tcgen05_mma_ws_tmem_a_collector_b3_lastuse(
+  cta_group_1_t,
+  kind_t<_Kind> __kind,
+  _CUDA_VSTD::uint32_t __d_tmem,
+  _CUDA_VSTD::uint32_t __a_tmem,
+  _CUDA_VSTD::uint64_t __b_desc,
+  _CUDA_VSTD::uint32_t __idesc,
+  bool __enable_input_d)
+{
+  // __cta_group == cta_group_1 (due to parameter type constraint)
+  static_assert(__kind == kind_f16 || __kind == kind_tf32 || __kind == kind_f8f6f4 || __kind == kind_i8, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  _CCCL_IF_CONSTEXPR (__kind == kind_f16)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b3::lastuse [%0], [%1], %2, %3, PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "r"(__a_tmem),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_tf32)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b3::lastuse [%0], [%1], %2, %3, PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "r"(__a_tmem),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_f8f6f4)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b3::lastuse [%0], [%1], %2, %3, PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "r"(__a_tmem),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_i8)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b3::lastuse [%0], [%1], %2, %3, PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "r"(__a_tmem),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_mma_ws_tmem_a_collector_b3_lastuse_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.mma.ws.cta_group.kind.collector::b3::discard [d_tmem], a_desc, b_desc, idesc, enable_input_d,
+zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_101a
+// .cta_group = { .cta_group::1 }
+// .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+template <cuda::ptx::dot_kind Kind>
+__device__ static inline void tcgen05_mma_ws_collector_b3_discard(
+  cuda::ptx::cta_group_1_t,
+  cuda::ptx::kind_t<Kind> kind,
+  uint32_t d_tmem,
+  uint64_t a_desc,
+  uint64_t b_desc,
+  uint32_t idesc,
+  bool enable_input_d,
+  uint64_t zero_column_mask_desc);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_mma_ws_collector_b3_discard_is_not_supported_before_SM_100a_SM_101a__();
+template <dot_kind _Kind>
+_CCCL_DEVICE static inline void tcgen05_mma_ws_collector_b3_discard(
+  cta_group_1_t,
+  kind_t<_Kind> __kind,
+  _CUDA_VSTD::uint32_t __d_tmem,
+  _CUDA_VSTD::uint64_t __a_desc,
+  _CUDA_VSTD::uint64_t __b_desc,
+  _CUDA_VSTD::uint32_t __idesc,
+  bool __enable_input_d,
+  _CUDA_VSTD::uint64_t __zero_column_mask_desc)
+{
+  // __cta_group == cta_group_1 (due to parameter type constraint)
+  static_assert(__kind == kind_f16 || __kind == kind_tf32 || __kind == kind_f8f6f4 || __kind == kind_i8, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  _CCCL_IF_CONSTEXPR (__kind == kind_f16)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b3::discard [%0], %1, %2, %3, PRED_enable_input_d, %5;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d)),
+        "l"(__zero_column_mask_desc)
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_tf32)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b3::discard [%0], %1, %2, %3, PRED_enable_input_d, %5;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d)),
+        "l"(__zero_column_mask_desc)
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_f8f6f4)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b3::discard [%0], %1, %2, %3, PRED_enable_input_d, %5;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d)),
+        "l"(__zero_column_mask_desc)
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_i8)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b3::discard [%0], %1, %2, %3, PRED_enable_input_d, %5;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d)),
+        "l"(__zero_column_mask_desc)
+      : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_mma_ws_collector_b3_discard_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.mma.ws.cta_group.kind.collector::b3::discard [d_tmem], a_desc, b_desc, idesc, enable_input_d; // PTX ISA 86,
+SM_100a, SM_101a
+// .cta_group = { .cta_group::1 }
+// .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+template <cuda::ptx::dot_kind Kind>
+__device__ static inline void tcgen05_mma_ws_collector_b3_discard(
+  cuda::ptx::cta_group_1_t,
+  cuda::ptx::kind_t<Kind> kind,
+  uint32_t d_tmem,
+  uint64_t a_desc,
+  uint64_t b_desc,
+  uint32_t idesc,
+  bool enable_input_d);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_mma_ws_collector_b3_discard_is_not_supported_before_SM_100a_SM_101a__();
+template <dot_kind _Kind>
+_CCCL_DEVICE static inline void tcgen05_mma_ws_collector_b3_discard(
+  cta_group_1_t,
+  kind_t<_Kind> __kind,
+  _CUDA_VSTD::uint32_t __d_tmem,
+  _CUDA_VSTD::uint64_t __a_desc,
+  _CUDA_VSTD::uint64_t __b_desc,
+  _CUDA_VSTD::uint32_t __idesc,
+  bool __enable_input_d)
+{
+  // __cta_group == cta_group_1 (due to parameter type constraint)
+  static_assert(__kind == kind_f16 || __kind == kind_tf32 || __kind == kind_f8f6f4 || __kind == kind_i8, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  _CCCL_IF_CONSTEXPR (__kind == kind_f16)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b3::discard [%0], %1, %2, %3, PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_tf32)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b3::discard [%0], %1, %2, %3, PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_f8f6f4)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b3::discard [%0], %1, %2, %3, PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_i8)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b3::discard [%0], %1, %2, %3, PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "l"(__a_desc),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_mma_ws_collector_b3_discard_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.mma.ws.cta_group.kind.collector::b3::discard [d_tmem], [a_tmem], b_desc, idesc, enable_input_d,
+zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_101a
+// .cta_group = { .cta_group::1 }
+// .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+template <cuda::ptx::dot_kind Kind>
+__device__ static inline void tcgen05_mma_ws_tmem_a_collector_b3_discard(
+  cuda::ptx::cta_group_1_t,
+  cuda::ptx::kind_t<Kind> kind,
+  uint32_t d_tmem,
+  uint32_t a_tmem,
+  uint64_t b_desc,
+  uint32_t idesc,
+  bool enable_input_d,
+  uint64_t zero_column_mask_desc);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void
+__cuda_ptx_tcgen05_mma_ws_tmem_a_collector_b3_discard_is_not_supported_before_SM_100a_SM_101a__();
+template <dot_kind _Kind>
+_CCCL_DEVICE static inline void tcgen05_mma_ws_tmem_a_collector_b3_discard(
+  cta_group_1_t,
+  kind_t<_Kind> __kind,
+  _CUDA_VSTD::uint32_t __d_tmem,
+  _CUDA_VSTD::uint32_t __a_tmem,
+  _CUDA_VSTD::uint64_t __b_desc,
+  _CUDA_VSTD::uint32_t __idesc,
+  bool __enable_input_d,
+  _CUDA_VSTD::uint64_t __zero_column_mask_desc)
+{
+  // __cta_group == cta_group_1 (due to parameter type constraint)
+  static_assert(__kind == kind_f16 || __kind == kind_tf32 || __kind == kind_f8f6f4 || __kind == kind_i8, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  _CCCL_IF_CONSTEXPR (__kind == kind_f16)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b3::discard [%0], [%1], %2, %3, PRED_enable_input_d, %5;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "r"(__a_tmem),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d)),
+        "l"(__zero_column_mask_desc)
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_tf32)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b3::discard [%0], [%1], %2, %3, PRED_enable_input_d, %5;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "r"(__a_tmem),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d)),
+        "l"(__zero_column_mask_desc)
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_f8f6f4)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b3::discard [%0], [%1], %2, %3, PRED_enable_input_d, %5;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "r"(__a_tmem),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d)),
+        "l"(__zero_column_mask_desc)
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_i8)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b3::discard [%0], [%1], %2, %3, PRED_enable_input_d, %5;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "r"(__a_tmem),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d)),
+        "l"(__zero_column_mask_desc)
+      : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_mma_ws_tmem_a_collector_b3_discard_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.mma.ws.cta_group.kind.collector::b3::discard [d_tmem], [a_tmem], b_desc, idesc, enable_input_d; // PTX ISA
+86, SM_100a, SM_101a
+// .cta_group = { .cta_group::1 }
+// .kind      = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 }
+template <cuda::ptx::dot_kind Kind>
+__device__ static inline void tcgen05_mma_ws_tmem_a_collector_b3_discard(
+  cuda::ptx::cta_group_1_t,
+  cuda::ptx::kind_t<Kind> kind,
+  uint32_t d_tmem,
+  uint32_t a_tmem,
+  uint64_t b_desc,
+  uint32_t idesc,
+  bool enable_input_d);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void
+__cuda_ptx_tcgen05_mma_ws_tmem_a_collector_b3_discard_is_not_supported_before_SM_100a_SM_101a__();
+template <dot_kind _Kind>
+_CCCL_DEVICE static inline void tcgen05_mma_ws_tmem_a_collector_b3_discard(
+  cta_group_1_t,
+  kind_t<_Kind> __kind,
+  _CUDA_VSTD::uint32_t __d_tmem,
+  _CUDA_VSTD::uint32_t __a_tmem,
+  _CUDA_VSTD::uint64_t __b_desc,
+  _CUDA_VSTD::uint32_t __idesc,
+  bool __enable_input_d)
+{
+  // __cta_group == cta_group_1 (due to parameter type constraint)
+  static_assert(__kind == kind_f16 || __kind == kind_tf32 || __kind == kind_f8f6f4 || __kind == kind_i8, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  _CCCL_IF_CONSTEXPR (__kind == kind_f16)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b3::discard [%0], [%1], %2, %3, PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "r"(__a_tmem),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_tf32)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b3::discard [%0], [%1], %2, %3, PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "r"(__a_tmem),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_f8f6f4)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b3::discard [%0], [%1], %2, %3, PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "r"(__a_tmem),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__kind == kind_i8)
+  {
+    asm volatile(
+      "{\n\t .reg .pred PRED_enable_input_d; \n\t"
+      "setp.ne.b32 PRED_enable_input_d, %4, 0;\n\t"
+      "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b3::discard [%0], [%1], %2, %3, PRED_enable_input_d;\n\t"
+      "}"
+      :
+      : "r"(__d_tmem),
+        "r"(__a_tmem),
+        "l"(__b_desc),
+        "r"(__idesc),
+        "r"(static_cast<_CUDA_VSTD::uint32_t>(__enable_input_d))
+      : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_mma_ws_tmem_a_collector_b3_discard_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+#endif // _CUDA_PTX_GENERATED_TCGEN05_MMA_WS_H_
diff --git a/libcudacxx/include/cuda/__ptx/instructions/generated/tcgen05_shift.h b/libcudacxx/include/cuda/__ptx/instructions/generated/tcgen05_shift.h
new file mode 100644
index 00000000000..0c28ba5d888
--- /dev/null
+++ b/libcudacxx/include/cuda/__ptx/instructions/generated/tcgen05_shift.h
@@ -0,0 +1,36 @@
+// This file was automatically generated. Do not edit.
+
+#ifndef _CUDA_PTX_GENERATED_TCGEN05_SHIFT_H_
+#define _CUDA_PTX_GENERATED_TCGEN05_SHIFT_H_
+
+/*
+// tcgen05.shift.cta_group.down [taddr]; // PTX ISA 86, SM_100a, SM_101a
+// .cta_group = { .cta_group::1, .cta_group::2 }
+template <cuda::ptx::dot_cta_group Cta_Group>
+__device__ static inline void tcgen05_shift_down(
+  cuda::ptx::cta_group_t<Cta_Group> cta_group,
+  uint32_t taddr);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_shift_down_is_not_supported_before_SM_100a_SM_101a__();
+template <dot_cta_group _Cta_Group>
+_CCCL_DEVICE static inline void tcgen05_shift_down(cta_group_t<_Cta_Group> __cta_group, _CUDA_VSTD::uint32_t __taddr)
+{
+  static_assert(__cta_group == cta_group_1 || __cta_group == cta_group_2, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  _CCCL_IF_CONSTEXPR (__cta_group == cta_group_1)
+  {
+    asm volatile("tcgen05.shift.cta_group::1.down [%0];" : : "r"(__taddr) : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__cta_group == cta_group_2)
+  {
+    asm volatile("tcgen05.shift.cta_group::2.down [%0];" : : "r"(__taddr) : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_shift_down_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+#endif // _CUDA_PTX_GENERATED_TCGEN05_SHIFT_H_
diff --git a/libcudacxx/include/cuda/__ptx/instructions/generated/tcgen05_st.h b/libcudacxx/include/cuda/__ptx/instructions/generated/tcgen05_st.h
new file mode 100644
index 00000000000..83e9d13810e
--- /dev/null
+++ b/libcudacxx/include/cuda/__ptx/instructions/generated/tcgen05_st.h
@@ -0,0 +1,4554 @@
+// This file was automatically generated. Do not edit.
+
+#ifndef _CUDA_PTX_GENERATED_TCGEN05_ST_H_
+#define _CUDA_PTX_GENERATED_TCGEN05_ST_H_
+
+/*
+// tcgen05.st.sync.aligned.16x64b.x1.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_101a
+template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+__device__ static inline void tcgen05_st_16x64b(
+  uint32_t taddr,
+  const B32 (&values)[1]);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_st_16x64b_is_not_supported_before_SM_100a_SM_101a__();
+template <typename _B32, _CUDA_VSTD::enable_if_t<sizeof(_B32) == 4, bool> = true>
+_CCCL_DEVICE static inline void tcgen05_st_16x64b(_CUDA_VSTD::uint32_t __taddr, const _B32 (&__values)[1])
+{
+  static_assert(sizeof(_B32) == 4, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  asm("tcgen05.st.sync.aligned.16x64b.x1.b32 [%0], {%1};" : : "r"(__taddr), "r"(__as_b32(__values[0])) : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_st_16x64b_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.st.sync.aligned.16x64b.x1.unpack::16b.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_101a
+template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+__device__ static inline void tcgen05_st_16x64b_unpack_16b(
+  uint32_t taddr,
+  const B32 (&values)[1]);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_st_16x64b_unpack_16b_is_not_supported_before_SM_100a_SM_101a__();
+template <typename _B32, _CUDA_VSTD::enable_if_t<sizeof(_B32) == 4, bool> = true>
+_CCCL_DEVICE static inline void tcgen05_st_16x64b_unpack_16b(_CUDA_VSTD::uint32_t __taddr, const _B32 (&__values)[1])
+{
+  static_assert(sizeof(_B32) == 4, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  asm("tcgen05.st.sync.aligned.16x64b.x1.unpack::16b.b32 [%0], {%1};"
+      :
+      : "r"(__taddr), "r"(__as_b32(__values[0]))
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_st_16x64b_unpack_16b_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.st.sync.aligned.16x64b.x2.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_101a
+template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+__device__ static inline void tcgen05_st_16x64b(
+  uint32_t taddr,
+  const B32 (&values)[2]);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_st_16x64b_is_not_supported_before_SM_100a_SM_101a__();
+template <typename _B32, _CUDA_VSTD::enable_if_t<sizeof(_B32) == 4, bool> = true>
+_CCCL_DEVICE static inline void tcgen05_st_16x64b(_CUDA_VSTD::uint32_t __taddr, const _B32 (&__values)[2])
+{
+  static_assert(sizeof(_B32) == 4, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  asm("tcgen05.st.sync.aligned.16x64b.x2.b32 [%0], {%1, %2};"
+      :
+      : "r"(__taddr), "r"(__as_b32(__values[0])), "r"(__as_b32(__values[1]))
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_st_16x64b_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.st.sync.aligned.16x64b.x2.unpack::16b.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_101a
+template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+__device__ static inline void tcgen05_st_16x64b_unpack_16b(
+  uint32_t taddr,
+  const B32 (&values)[2]);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_st_16x64b_unpack_16b_is_not_supported_before_SM_100a_SM_101a__();
+template <typename _B32, _CUDA_VSTD::enable_if_t<sizeof(_B32) == 4, bool> = true>
+_CCCL_DEVICE static inline void tcgen05_st_16x64b_unpack_16b(_CUDA_VSTD::uint32_t __taddr, const _B32 (&__values)[2])
+{
+  static_assert(sizeof(_B32) == 4, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  asm("tcgen05.st.sync.aligned.16x64b.x2.unpack::16b.b32 [%0], {%1, %2};"
+      :
+      : "r"(__taddr), "r"(__as_b32(__values[0])), "r"(__as_b32(__values[1]))
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_st_16x64b_unpack_16b_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.st.sync.aligned.16x64b.x4.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_101a
+template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+__device__ static inline void tcgen05_st_16x64b(
+  uint32_t taddr,
+  const B32 (&values)[4]);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_st_16x64b_is_not_supported_before_SM_100a_SM_101a__();
+template <typename _B32, _CUDA_VSTD::enable_if_t<sizeof(_B32) == 4, bool> = true>
+_CCCL_DEVICE static inline void tcgen05_st_16x64b(_CUDA_VSTD::uint32_t __taddr, const _B32 (&__values)[4])
+{
+  static_assert(sizeof(_B32) == 4, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  asm("tcgen05.st.sync.aligned.16x64b.x4.b32 [%0], {%1, %2, %3, %4};"
+      :
+      : "r"(__taddr),
+        "r"(__as_b32(__values[0])),
+        "r"(__as_b32(__values[1])),
+        "r"(__as_b32(__values[2])),
+        "r"(__as_b32(__values[3]))
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_st_16x64b_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.st.sync.aligned.16x64b.x4.unpack::16b.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_101a
+template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+__device__ static inline void tcgen05_st_16x64b_unpack_16b(
+  uint32_t taddr,
+  const B32 (&values)[4]);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_st_16x64b_unpack_16b_is_not_supported_before_SM_100a_SM_101a__();
+template <typename _B32, _CUDA_VSTD::enable_if_t<sizeof(_B32) == 4, bool> = true>
+_CCCL_DEVICE static inline void tcgen05_st_16x64b_unpack_16b(_CUDA_VSTD::uint32_t __taddr, const _B32 (&__values)[4])
+{
+  static_assert(sizeof(_B32) == 4, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  asm("tcgen05.st.sync.aligned.16x64b.x4.unpack::16b.b32 [%0], {%1, %2, %3, %4};"
+      :
+      : "r"(__taddr),
+        "r"(__as_b32(__values[0])),
+        "r"(__as_b32(__values[1])),
+        "r"(__as_b32(__values[2])),
+        "r"(__as_b32(__values[3]))
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_st_16x64b_unpack_16b_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.st.sync.aligned.16x64b.x8.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_101a
+template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+__device__ static inline void tcgen05_st_16x64b(
+  uint32_t taddr,
+  const B32 (&values)[8]);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_st_16x64b_is_not_supported_before_SM_100a_SM_101a__();
+template <typename _B32, _CUDA_VSTD::enable_if_t<sizeof(_B32) == 4, bool> = true>
+_CCCL_DEVICE static inline void tcgen05_st_16x64b(_CUDA_VSTD::uint32_t __taddr, const _B32 (&__values)[8])
+{
+  static_assert(sizeof(_B32) == 4, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  asm("tcgen05.st.sync.aligned.16x64b.x8.b32 [%0], {%1, %2, %3, %4, %5, %6, %7, %8};"
+      :
+      : "r"(__taddr),
+        "r"(__as_b32(__values[0])),
+        "r"(__as_b32(__values[1])),
+        "r"(__as_b32(__values[2])),
+        "r"(__as_b32(__values[3])),
+        "r"(__as_b32(__values[4])),
+        "r"(__as_b32(__values[5])),
+        "r"(__as_b32(__values[6])),
+        "r"(__as_b32(__values[7]))
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_st_16x64b_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.st.sync.aligned.16x64b.x8.unpack::16b.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_101a
+template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+__device__ static inline void tcgen05_st_16x64b_unpack_16b(
+  uint32_t taddr,
+  const B32 (&values)[8]);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_st_16x64b_unpack_16b_is_not_supported_before_SM_100a_SM_101a__();
+template <typename _B32, _CUDA_VSTD::enable_if_t<sizeof(_B32) == 4, bool> = true>
+_CCCL_DEVICE static inline void tcgen05_st_16x64b_unpack_16b(_CUDA_VSTD::uint32_t __taddr, const _B32 (&__values)[8])
+{
+  static_assert(sizeof(_B32) == 4, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  asm("tcgen05.st.sync.aligned.16x64b.x8.unpack::16b.b32 [%0], {%1, %2, %3, %4, %5, %6, %7, %8};"
+      :
+      : "r"(__taddr),
+        "r"(__as_b32(__values[0])),
+        "r"(__as_b32(__values[1])),
+        "r"(__as_b32(__values[2])),
+        "r"(__as_b32(__values[3])),
+        "r"(__as_b32(__values[4])),
+        "r"(__as_b32(__values[5])),
+        "r"(__as_b32(__values[6])),
+        "r"(__as_b32(__values[7]))
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_st_16x64b_unpack_16b_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.st.sync.aligned.16x64b.x16.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_101a
+template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+__device__ static inline void tcgen05_st_16x64b(
+  uint32_t taddr,
+  const B32 (&values)[16]);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_st_16x64b_is_not_supported_before_SM_100a_SM_101a__();
+template <typename _B32, _CUDA_VSTD::enable_if_t<sizeof(_B32) == 4, bool> = true>
+_CCCL_DEVICE static inline void tcgen05_st_16x64b(_CUDA_VSTD::uint32_t __taddr, const _B32 (&__values)[16])
+{
+  static_assert(sizeof(_B32) == 4, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  asm("tcgen05.st.sync.aligned.16x64b.x16.b32 [%0], {%1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, "
+      "%16};"
+      :
+      : "r"(__taddr),
+        "r"(__as_b32(__values[0])),
+        "r"(__as_b32(__values[1])),
+        "r"(__as_b32(__values[2])),
+        "r"(__as_b32(__values[3])),
+        "r"(__as_b32(__values[4])),
+        "r"(__as_b32(__values[5])),
+        "r"(__as_b32(__values[6])),
+        "r"(__as_b32(__values[7])),
+        "r"(__as_b32(__values[8])),
+        "r"(__as_b32(__values[9])),
+        "r"(__as_b32(__values[10])),
+        "r"(__as_b32(__values[11])),
+        "r"(__as_b32(__values[12])),
+        "r"(__as_b32(__values[13])),
+        "r"(__as_b32(__values[14])),
+        "r"(__as_b32(__values[15]))
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_st_16x64b_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.st.sync.aligned.16x64b.x16.unpack::16b.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_101a
+template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+__device__ static inline void tcgen05_st_16x64b_unpack_16b(
+  uint32_t taddr,
+  const B32 (&values)[16]);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_st_16x64b_unpack_16b_is_not_supported_before_SM_100a_SM_101a__();
+template <typename _B32, _CUDA_VSTD::enable_if_t<sizeof(_B32) == 4, bool> = true>
+_CCCL_DEVICE static inline void tcgen05_st_16x64b_unpack_16b(_CUDA_VSTD::uint32_t __taddr, const _B32 (&__values)[16])
+{
+  static_assert(sizeof(_B32) == 4, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  asm("tcgen05.st.sync.aligned.16x64b.x16.unpack::16b.b32 [%0], {%1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, "
+      "%13, %14, %15, %16};"
+      :
+      : "r"(__taddr),
+        "r"(__as_b32(__values[0])),
+        "r"(__as_b32(__values[1])),
+        "r"(__as_b32(__values[2])),
+        "r"(__as_b32(__values[3])),
+        "r"(__as_b32(__values[4])),
+        "r"(__as_b32(__values[5])),
+        "r"(__as_b32(__values[6])),
+        "r"(__as_b32(__values[7])),
+        "r"(__as_b32(__values[8])),
+        "r"(__as_b32(__values[9])),
+        "r"(__as_b32(__values[10])),
+        "r"(__as_b32(__values[11])),
+        "r"(__as_b32(__values[12])),
+        "r"(__as_b32(__values[13])),
+        "r"(__as_b32(__values[14])),
+        "r"(__as_b32(__values[15]))
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_st_16x64b_unpack_16b_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.st.sync.aligned.16x64b.x32.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_101a
+template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+__device__ static inline void tcgen05_st_16x64b(
+  uint32_t taddr,
+  const B32 (&values)[32]);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_st_16x64b_is_not_supported_before_SM_100a_SM_101a__();
+template <typename _B32, _CUDA_VSTD::enable_if_t<sizeof(_B32) == 4, bool> = true>
+_CCCL_DEVICE static inline void tcgen05_st_16x64b(_CUDA_VSTD::uint32_t __taddr, const _B32 (&__values)[32])
+{
+  static_assert(sizeof(_B32) == 4, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  asm(
+    "tcgen05.st.sync.aligned.16x64b.x32.b32 [%0], {%1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, "
+    "%16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32};"
+    :
+    : "r"(__taddr),
+      "r"(__as_b32(__values[0])),
+      "r"(__as_b32(__values[1])),
+      "r"(__as_b32(__values[2])),
+      "r"(__as_b32(__values[3])),
+      "r"(__as_b32(__values[4])),
+      "r"(__as_b32(__values[5])),
+      "r"(__as_b32(__values[6])),
+      "r"(__as_b32(__values[7])),
+      "r"(__as_b32(__values[8])),
+      "r"(__as_b32(__values[9])),
+      "r"(__as_b32(__values[10])),
+      "r"(__as_b32(__values[11])),
+      "r"(__as_b32(__values[12])),
+      "r"(__as_b32(__values[13])),
+      "r"(__as_b32(__values[14])),
+      "r"(__as_b32(__values[15])),
+      "r"(__as_b32(__values[16])),
+      "r"(__as_b32(__values[17])),
+      "r"(__as_b32(__values[18])),
+      "r"(__as_b32(__values[19])),
+      "r"(__as_b32(__values[20])),
+      "r"(__as_b32(__values[21])),
+      "r"(__as_b32(__values[22])),
+      "r"(__as_b32(__values[23])),
+      "r"(__as_b32(__values[24])),
+      "r"(__as_b32(__values[25])),
+      "r"(__as_b32(__values[26])),
+      "r"(__as_b32(__values[27])),
+      "r"(__as_b32(__values[28])),
+      "r"(__as_b32(__values[29])),
+      "r"(__as_b32(__values[30])),
+      "r"(__as_b32(__values[31]))
+    : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_st_16x64b_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.st.sync.aligned.16x64b.x32.unpack::16b.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_101a
+template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+__device__ static inline void tcgen05_st_16x64b_unpack_16b(
+  uint32_t taddr,
+  const B32 (&values)[32]);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_st_16x64b_unpack_16b_is_not_supported_before_SM_100a_SM_101a__();
+template <typename _B32, _CUDA_VSTD::enable_if_t<sizeof(_B32) == 4, bool> = true>
+_CCCL_DEVICE static inline void tcgen05_st_16x64b_unpack_16b(_CUDA_VSTD::uint32_t __taddr, const _B32 (&__values)[32])
+{
+  static_assert(sizeof(_B32) == 4, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  asm(
+    "tcgen05.st.sync.aligned.16x64b.x32.unpack::16b.b32 [%0], {%1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, "
+    "%14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32};"
+    :
+    : "r"(__taddr),
+      "r"(__as_b32(__values[0])),
+      "r"(__as_b32(__values[1])),
+      "r"(__as_b32(__values[2])),
+      "r"(__as_b32(__values[3])),
+      "r"(__as_b32(__values[4])),
+      "r"(__as_b32(__values[5])),
+      "r"(__as_b32(__values[6])),
+      "r"(__as_b32(__values[7])),
+      "r"(__as_b32(__values[8])),
+      "r"(__as_b32(__values[9])),
+      "r"(__as_b32(__values[10])),
+      "r"(__as_b32(__values[11])),
+      "r"(__as_b32(__values[12])),
+      "r"(__as_b32(__values[13])),
+      "r"(__as_b32(__values[14])),
+      "r"(__as_b32(__values[15])),
+      "r"(__as_b32(__values[16])),
+      "r"(__as_b32(__values[17])),
+      "r"(__as_b32(__values[18])),
+      "r"(__as_b32(__values[19])),
+      "r"(__as_b32(__values[20])),
+      "r"(__as_b32(__values[21])),
+      "r"(__as_b32(__values[22])),
+      "r"(__as_b32(__values[23])),
+      "r"(__as_b32(__values[24])),
+      "r"(__as_b32(__values[25])),
+      "r"(__as_b32(__values[26])),
+      "r"(__as_b32(__values[27])),
+      "r"(__as_b32(__values[28])),
+      "r"(__as_b32(__values[29])),
+      "r"(__as_b32(__values[30])),
+      "r"(__as_b32(__values[31]))
+    : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_st_16x64b_unpack_16b_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.st.sync.aligned.16x64b.x64.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_101a
+template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+__device__ static inline void tcgen05_st_16x64b(
+  uint32_t taddr,
+  const B32 (&values)[64]);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_st_16x64b_is_not_supported_before_SM_100a_SM_101a__();
+template <typename _B32, _CUDA_VSTD::enable_if_t<sizeof(_B32) == 4, bool> = true>
+_CCCL_DEVICE static inline void tcgen05_st_16x64b(_CUDA_VSTD::uint32_t __taddr, const _B32 (&__values)[64])
+{
+  static_assert(sizeof(_B32) == 4, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  asm(
+    "tcgen05.st.sync.aligned.16x64b.x64.b32 [%0], {%1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, "
+    "%16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, "
+    "%38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, "
+    "%60, %61, %62, %63, %64};"
+    :
+    : "r"(__taddr),
+      "r"(__as_b32(__values[0])),
+      "r"(__as_b32(__values[1])),
+      "r"(__as_b32(__values[2])),
+      "r"(__as_b32(__values[3])),
+      "r"(__as_b32(__values[4])),
+      "r"(__as_b32(__values[5])),
+      "r"(__as_b32(__values[6])),
+      "r"(__as_b32(__values[7])),
+      "r"(__as_b32(__values[8])),
+      "r"(__as_b32(__values[9])),
+      "r"(__as_b32(__values[10])),
+      "r"(__as_b32(__values[11])),
+      "r"(__as_b32(__values[12])),
+      "r"(__as_b32(__values[13])),
+      "r"(__as_b32(__values[14])),
+      "r"(__as_b32(__values[15])),
+      "r"(__as_b32(__values[16])),
+      "r"(__as_b32(__values[17])),
+      "r"(__as_b32(__values[18])),
+      "r"(__as_b32(__values[19])),
+      "r"(__as_b32(__values[20])),
+      "r"(__as_b32(__values[21])),
+      "r"(__as_b32(__values[22])),
+      "r"(__as_b32(__values[23])),
+      "r"(__as_b32(__values[24])),
+      "r"(__as_b32(__values[25])),
+      "r"(__as_b32(__values[26])),
+      "r"(__as_b32(__values[27])),
+      "r"(__as_b32(__values[28])),
+      "r"(__as_b32(__values[29])),
+      "r"(__as_b32(__values[30])),
+      "r"(__as_b32(__values[31])),
+      "r"(__as_b32(__values[32])),
+      "r"(__as_b32(__values[33])),
+      "r"(__as_b32(__values[34])),
+      "r"(__as_b32(__values[35])),
+      "r"(__as_b32(__values[36])),
+      "r"(__as_b32(__values[37])),
+      "r"(__as_b32(__values[38])),
+      "r"(__as_b32(__values[39])),
+      "r"(__as_b32(__values[40])),
+      "r"(__as_b32(__values[41])),
+      "r"(__as_b32(__values[42])),
+      "r"(__as_b32(__values[43])),
+      "r"(__as_b32(__values[44])),
+      "r"(__as_b32(__values[45])),
+      "r"(__as_b32(__values[46])),
+      "r"(__as_b32(__values[47])),
+      "r"(__as_b32(__values[48])),
+      "r"(__as_b32(__values[49])),
+      "r"(__as_b32(__values[50])),
+      "r"(__as_b32(__values[51])),
+      "r"(__as_b32(__values[52])),
+      "r"(__as_b32(__values[53])),
+      "r"(__as_b32(__values[54])),
+      "r"(__as_b32(__values[55])),
+      "r"(__as_b32(__values[56])),
+      "r"(__as_b32(__values[57])),
+      "r"(__as_b32(__values[58])),
+      "r"(__as_b32(__values[59])),
+      "r"(__as_b32(__values[60])),
+      "r"(__as_b32(__values[61])),
+      "r"(__as_b32(__values[62])),
+      "r"(__as_b32(__values[63]))
+    : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_st_16x64b_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.st.sync.aligned.16x64b.x64.unpack::16b.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_101a
+template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+__device__ static inline void tcgen05_st_16x64b_unpack_16b(
+  uint32_t taddr,
+  const B32 (&values)[64]);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_st_16x64b_unpack_16b_is_not_supported_before_SM_100a_SM_101a__();
+template <typename _B32, _CUDA_VSTD::enable_if_t<sizeof(_B32) == 4, bool> = true>
+_CCCL_DEVICE static inline void tcgen05_st_16x64b_unpack_16b(_CUDA_VSTD::uint32_t __taddr, const _B32 (&__values)[64])
+{
+  static_assert(sizeof(_B32) == 4, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  asm(
+    "tcgen05.st.sync.aligned.16x64b.x64.unpack::16b.b32 [%0], {%1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, "
+    "%14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, "
+    "%36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, "
+    "%58, %59, %60, %61, %62, %63, %64};"
+    :
+    : "r"(__taddr),
+      "r"(__as_b32(__values[0])),
+      "r"(__as_b32(__values[1])),
+      "r"(__as_b32(__values[2])),
+      "r"(__as_b32(__values[3])),
+      "r"(__as_b32(__values[4])),
+      "r"(__as_b32(__values[5])),
+      "r"(__as_b32(__values[6])),
+      "r"(__as_b32(__values[7])),
+      "r"(__as_b32(__values[8])),
+      "r"(__as_b32(__values[9])),
+      "r"(__as_b32(__values[10])),
+      "r"(__as_b32(__values[11])),
+      "r"(__as_b32(__values[12])),
+      "r"(__as_b32(__values[13])),
+      "r"(__as_b32(__values[14])),
+      "r"(__as_b32(__values[15])),
+      "r"(__as_b32(__values[16])),
+      "r"(__as_b32(__values[17])),
+      "r"(__as_b32(__values[18])),
+      "r"(__as_b32(__values[19])),
+      "r"(__as_b32(__values[20])),
+      "r"(__as_b32(__values[21])),
+      "r"(__as_b32(__values[22])),
+      "r"(__as_b32(__values[23])),
+      "r"(__as_b32(__values[24])),
+      "r"(__as_b32(__values[25])),
+      "r"(__as_b32(__values[26])),
+      "r"(__as_b32(__values[27])),
+      "r"(__as_b32(__values[28])),
+      "r"(__as_b32(__values[29])),
+      "r"(__as_b32(__values[30])),
+      "r"(__as_b32(__values[31])),
+      "r"(__as_b32(__values[32])),
+      "r"(__as_b32(__values[33])),
+      "r"(__as_b32(__values[34])),
+      "r"(__as_b32(__values[35])),
+      "r"(__as_b32(__values[36])),
+      "r"(__as_b32(__values[37])),
+      "r"(__as_b32(__values[38])),
+      "r"(__as_b32(__values[39])),
+      "r"(__as_b32(__values[40])),
+      "r"(__as_b32(__values[41])),
+      "r"(__as_b32(__values[42])),
+      "r"(__as_b32(__values[43])),
+      "r"(__as_b32(__values[44])),
+      "r"(__as_b32(__values[45])),
+      "r"(__as_b32(__values[46])),
+      "r"(__as_b32(__values[47])),
+      "r"(__as_b32(__values[48])),
+      "r"(__as_b32(__values[49])),
+      "r"(__as_b32(__values[50])),
+      "r"(__as_b32(__values[51])),
+      "r"(__as_b32(__values[52])),
+      "r"(__as_b32(__values[53])),
+      "r"(__as_b32(__values[54])),
+      "r"(__as_b32(__values[55])),
+      "r"(__as_b32(__values[56])),
+      "r"(__as_b32(__values[57])),
+      "r"(__as_b32(__values[58])),
+      "r"(__as_b32(__values[59])),
+      "r"(__as_b32(__values[60])),
+      "r"(__as_b32(__values[61])),
+      "r"(__as_b32(__values[62])),
+      "r"(__as_b32(__values[63]))
+    : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_st_16x64b_unpack_16b_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.st.sync.aligned.16x64b.x128.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_101a
+template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+__device__ static inline void tcgen05_st_16x64b(
+  uint32_t taddr,
+  const B32 (&values)[128]);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_st_16x64b_is_not_supported_before_SM_100a_SM_101a__();
+template <typename _B32, _CUDA_VSTD::enable_if_t<sizeof(_B32) == 4, bool> = true>
+_CCCL_DEVICE static inline void tcgen05_st_16x64b(_CUDA_VSTD::uint32_t __taddr, const _B32 (&__values)[128])
+{
+  static_assert(sizeof(_B32) == 4, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  asm(
+    "tcgen05.st.sync.aligned.16x64b.x128.b32 [%0], {%1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, "
+    "%16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, "
+    "%38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, "
+    "%60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, "
+    "%82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, "
+    "%104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, "
+    "%123, %124, %125, %126, %127, %128};"
+    :
+    : "r"(__taddr),
+      "r"(__as_b32(__values[0])),
+      "r"(__as_b32(__values[1])),
+      "r"(__as_b32(__values[2])),
+      "r"(__as_b32(__values[3])),
+      "r"(__as_b32(__values[4])),
+      "r"(__as_b32(__values[5])),
+      "r"(__as_b32(__values[6])),
+      "r"(__as_b32(__values[7])),
+      "r"(__as_b32(__values[8])),
+      "r"(__as_b32(__values[9])),
+      "r"(__as_b32(__values[10])),
+      "r"(__as_b32(__values[11])),
+      "r"(__as_b32(__values[12])),
+      "r"(__as_b32(__values[13])),
+      "r"(__as_b32(__values[14])),
+      "r"(__as_b32(__values[15])),
+      "r"(__as_b32(__values[16])),
+      "r"(__as_b32(__values[17])),
+      "r"(__as_b32(__values[18])),
+      "r"(__as_b32(__values[19])),
+      "r"(__as_b32(__values[20])),
+      "r"(__as_b32(__values[21])),
+      "r"(__as_b32(__values[22])),
+      "r"(__as_b32(__values[23])),
+      "r"(__as_b32(__values[24])),
+      "r"(__as_b32(__values[25])),
+      "r"(__as_b32(__values[26])),
+      "r"(__as_b32(__values[27])),
+      "r"(__as_b32(__values[28])),
+      "r"(__as_b32(__values[29])),
+      "r"(__as_b32(__values[30])),
+      "r"(__as_b32(__values[31])),
+      "r"(__as_b32(__values[32])),
+      "r"(__as_b32(__values[33])),
+      "r"(__as_b32(__values[34])),
+      "r"(__as_b32(__values[35])),
+      "r"(__as_b32(__values[36])),
+      "r"(__as_b32(__values[37])),
+      "r"(__as_b32(__values[38])),
+      "r"(__as_b32(__values[39])),
+      "r"(__as_b32(__values[40])),
+      "r"(__as_b32(__values[41])),
+      "r"(__as_b32(__values[42])),
+      "r"(__as_b32(__values[43])),
+      "r"(__as_b32(__values[44])),
+      "r"(__as_b32(__values[45])),
+      "r"(__as_b32(__values[46])),
+      "r"(__as_b32(__values[47])),
+      "r"(__as_b32(__values[48])),
+      "r"(__as_b32(__values[49])),
+      "r"(__as_b32(__values[50])),
+      "r"(__as_b32(__values[51])),
+      "r"(__as_b32(__values[52])),
+      "r"(__as_b32(__values[53])),
+      "r"(__as_b32(__values[54])),
+      "r"(__as_b32(__values[55])),
+      "r"(__as_b32(__values[56])),
+      "r"(__as_b32(__values[57])),
+      "r"(__as_b32(__values[58])),
+      "r"(__as_b32(__values[59])),
+      "r"(__as_b32(__values[60])),
+      "r"(__as_b32(__values[61])),
+      "r"(__as_b32(__values[62])),
+      "r"(__as_b32(__values[63])),
+      "r"(__as_b32(__values[64])),
+      "r"(__as_b32(__values[65])),
+      "r"(__as_b32(__values[66])),
+      "r"(__as_b32(__values[67])),
+      "r"(__as_b32(__values[68])),
+      "r"(__as_b32(__values[69])),
+      "r"(__as_b32(__values[70])),
+      "r"(__as_b32(__values[71])),
+      "r"(__as_b32(__values[72])),
+      "r"(__as_b32(__values[73])),
+      "r"(__as_b32(__values[74])),
+      "r"(__as_b32(__values[75])),
+      "r"(__as_b32(__values[76])),
+      "r"(__as_b32(__values[77])),
+      "r"(__as_b32(__values[78])),
+      "r"(__as_b32(__values[79])),
+      "r"(__as_b32(__values[80])),
+      "r"(__as_b32(__values[81])),
+      "r"(__as_b32(__values[82])),
+      "r"(__as_b32(__values[83])),
+      "r"(__as_b32(__values[84])),
+      "r"(__as_b32(__values[85])),
+      "r"(__as_b32(__values[86])),
+      "r"(__as_b32(__values[87])),
+      "r"(__as_b32(__values[88])),
+      "r"(__as_b32(__values[89])),
+      "r"(__as_b32(__values[90])),
+      "r"(__as_b32(__values[91])),
+      "r"(__as_b32(__values[92])),
+      "r"(__as_b32(__values[93])),
+      "r"(__as_b32(__values[94])),
+      "r"(__as_b32(__values[95])),
+      "r"(__as_b32(__values[96])),
+      "r"(__as_b32(__values[97])),
+      "r"(__as_b32(__values[98])),
+      "r"(__as_b32(__values[99])),
+      "r"(__as_b32(__values[100])),
+      "r"(__as_b32(__values[101])),
+      "r"(__as_b32(__values[102])),
+      "r"(__as_b32(__values[103])),
+      "r"(__as_b32(__values[104])),
+      "r"(__as_b32(__values[105])),
+      "r"(__as_b32(__values[106])),
+      "r"(__as_b32(__values[107])),
+      "r"(__as_b32(__values[108])),
+      "r"(__as_b32(__values[109])),
+      "r"(__as_b32(__values[110])),
+      "r"(__as_b32(__values[111])),
+      "r"(__as_b32(__values[112])),
+      "r"(__as_b32(__values[113])),
+      "r"(__as_b32(__values[114])),
+      "r"(__as_b32(__values[115])),
+      "r"(__as_b32(__values[116])),
+      "r"(__as_b32(__values[117])),
+      "r"(__as_b32(__values[118])),
+      "r"(__as_b32(__values[119])),
+      "r"(__as_b32(__values[120])),
+      "r"(__as_b32(__values[121])),
+      "r"(__as_b32(__values[122])),
+      "r"(__as_b32(__values[123])),
+      "r"(__as_b32(__values[124])),
+      "r"(__as_b32(__values[125])),
+      "r"(__as_b32(__values[126])),
+      "r"(__as_b32(__values[127]))
+    : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_st_16x64b_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.st.sync.aligned.16x64b.x128.unpack::16b.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_101a
+template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+__device__ static inline void tcgen05_st_16x64b_unpack_16b(
+  uint32_t taddr,
+  const B32 (&values)[128]);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_st_16x64b_unpack_16b_is_not_supported_before_SM_100a_SM_101a__();
+template <typename _B32, _CUDA_VSTD::enable_if_t<sizeof(_B32) == 4, bool> = true>
+_CCCL_DEVICE static inline void tcgen05_st_16x64b_unpack_16b(_CUDA_VSTD::uint32_t __taddr, const _B32 (&__values)[128])
+{
+  static_assert(sizeof(_B32) == 4, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  asm(
+    "tcgen05.st.sync.aligned.16x64b.x128.unpack::16b.b32 [%0], {%1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, "
+    "%13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, "
+    "%35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, "
+    "%57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, "
+    "%79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, "
+    "%101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, "
+    "%120, %121, %122, %123, %124, %125, %126, %127, %128};"
+    :
+    : "r"(__taddr),
+      "r"(__as_b32(__values[0])),
+      "r"(__as_b32(__values[1])),
+      "r"(__as_b32(__values[2])),
+      "r"(__as_b32(__values[3])),
+      "r"(__as_b32(__values[4])),
+      "r"(__as_b32(__values[5])),
+      "r"(__as_b32(__values[6])),
+      "r"(__as_b32(__values[7])),
+      "r"(__as_b32(__values[8])),
+      "r"(__as_b32(__values[9])),
+      "r"(__as_b32(__values[10])),
+      "r"(__as_b32(__values[11])),
+      "r"(__as_b32(__values[12])),
+      "r"(__as_b32(__values[13])),
+      "r"(__as_b32(__values[14])),
+      "r"(__as_b32(__values[15])),
+      "r"(__as_b32(__values[16])),
+      "r"(__as_b32(__values[17])),
+      "r"(__as_b32(__values[18])),
+      "r"(__as_b32(__values[19])),
+      "r"(__as_b32(__values[20])),
+      "r"(__as_b32(__values[21])),
+      "r"(__as_b32(__values[22])),
+      "r"(__as_b32(__values[23])),
+      "r"(__as_b32(__values[24])),
+      "r"(__as_b32(__values[25])),
+      "r"(__as_b32(__values[26])),
+      "r"(__as_b32(__values[27])),
+      "r"(__as_b32(__values[28])),
+      "r"(__as_b32(__values[29])),
+      "r"(__as_b32(__values[30])),
+      "r"(__as_b32(__values[31])),
+      "r"(__as_b32(__values[32])),
+      "r"(__as_b32(__values[33])),
+      "r"(__as_b32(__values[34])),
+      "r"(__as_b32(__values[35])),
+      "r"(__as_b32(__values[36])),
+      "r"(__as_b32(__values[37])),
+      "r"(__as_b32(__values[38])),
+      "r"(__as_b32(__values[39])),
+      "r"(__as_b32(__values[40])),
+      "r"(__as_b32(__values[41])),
+      "r"(__as_b32(__values[42])),
+      "r"(__as_b32(__values[43])),
+      "r"(__as_b32(__values[44])),
+      "r"(__as_b32(__values[45])),
+      "r"(__as_b32(__values[46])),
+      "r"(__as_b32(__values[47])),
+      "r"(__as_b32(__values[48])),
+      "r"(__as_b32(__values[49])),
+      "r"(__as_b32(__values[50])),
+      "r"(__as_b32(__values[51])),
+      "r"(__as_b32(__values[52])),
+      "r"(__as_b32(__values[53])),
+      "r"(__as_b32(__values[54])),
+      "r"(__as_b32(__values[55])),
+      "r"(__as_b32(__values[56])),
+      "r"(__as_b32(__values[57])),
+      "r"(__as_b32(__values[58])),
+      "r"(__as_b32(__values[59])),
+      "r"(__as_b32(__values[60])),
+      "r"(__as_b32(__values[61])),
+      "r"(__as_b32(__values[62])),
+      "r"(__as_b32(__values[63])),
+      "r"(__as_b32(__values[64])),
+      "r"(__as_b32(__values[65])),
+      "r"(__as_b32(__values[66])),
+      "r"(__as_b32(__values[67])),
+      "r"(__as_b32(__values[68])),
+      "r"(__as_b32(__values[69])),
+      "r"(__as_b32(__values[70])),
+      "r"(__as_b32(__values[71])),
+      "r"(__as_b32(__values[72])),
+      "r"(__as_b32(__values[73])),
+      "r"(__as_b32(__values[74])),
+      "r"(__as_b32(__values[75])),
+      "r"(__as_b32(__values[76])),
+      "r"(__as_b32(__values[77])),
+      "r"(__as_b32(__values[78])),
+      "r"(__as_b32(__values[79])),
+      "r"(__as_b32(__values[80])),
+      "r"(__as_b32(__values[81])),
+      "r"(__as_b32(__values[82])),
+      "r"(__as_b32(__values[83])),
+      "r"(__as_b32(__values[84])),
+      "r"(__as_b32(__values[85])),
+      "r"(__as_b32(__values[86])),
+      "r"(__as_b32(__values[87])),
+      "r"(__as_b32(__values[88])),
+      "r"(__as_b32(__values[89])),
+      "r"(__as_b32(__values[90])),
+      "r"(__as_b32(__values[91])),
+      "r"(__as_b32(__values[92])),
+      "r"(__as_b32(__values[93])),
+      "r"(__as_b32(__values[94])),
+      "r"(__as_b32(__values[95])),
+      "r"(__as_b32(__values[96])),
+      "r"(__as_b32(__values[97])),
+      "r"(__as_b32(__values[98])),
+      "r"(__as_b32(__values[99])),
+      "r"(__as_b32(__values[100])),
+      "r"(__as_b32(__values[101])),
+      "r"(__as_b32(__values[102])),
+      "r"(__as_b32(__values[103])),
+      "r"(__as_b32(__values[104])),
+      "r"(__as_b32(__values[105])),
+      "r"(__as_b32(__values[106])),
+      "r"(__as_b32(__values[107])),
+      "r"(__as_b32(__values[108])),
+      "r"(__as_b32(__values[109])),
+      "r"(__as_b32(__values[110])),
+      "r"(__as_b32(__values[111])),
+      "r"(__as_b32(__values[112])),
+      "r"(__as_b32(__values[113])),
+      "r"(__as_b32(__values[114])),
+      "r"(__as_b32(__values[115])),
+      "r"(__as_b32(__values[116])),
+      "r"(__as_b32(__values[117])),
+      "r"(__as_b32(__values[118])),
+      "r"(__as_b32(__values[119])),
+      "r"(__as_b32(__values[120])),
+      "r"(__as_b32(__values[121])),
+      "r"(__as_b32(__values[122])),
+      "r"(__as_b32(__values[123])),
+      "r"(__as_b32(__values[124])),
+      "r"(__as_b32(__values[125])),
+      "r"(__as_b32(__values[126])),
+      "r"(__as_b32(__values[127]))
+    : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_st_16x64b_unpack_16b_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.st.sync.aligned.16x128b.x1.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_101a
+template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+__device__ static inline void tcgen05_st_16x128b(
+  uint32_t taddr,
+  const B32 (&values)[2]);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_st_16x128b_is_not_supported_before_SM_100a_SM_101a__();
+template <typename _B32, _CUDA_VSTD::enable_if_t<sizeof(_B32) == 4, bool> = true>
+_CCCL_DEVICE static inline void tcgen05_st_16x128b(_CUDA_VSTD::uint32_t __taddr, const _B32 (&__values)[2])
+{
+  static_assert(sizeof(_B32) == 4, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  asm("tcgen05.st.sync.aligned.16x128b.x1.b32 [%0], {%1, %2};"
+      :
+      : "r"(__taddr), "r"(__as_b32(__values[0])), "r"(__as_b32(__values[1]))
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_st_16x128b_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.st.sync.aligned.16x128b.x1.unpack::16b.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_101a
+template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+__device__ static inline void tcgen05_st_16x128b_unpack_16b(
+  uint32_t taddr,
+  const B32 (&values)[2]);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_st_16x128b_unpack_16b_is_not_supported_before_SM_100a_SM_101a__();
+template <typename _B32, _CUDA_VSTD::enable_if_t<sizeof(_B32) == 4, bool> = true>
+_CCCL_DEVICE static inline void tcgen05_st_16x128b_unpack_16b(_CUDA_VSTD::uint32_t __taddr, const _B32 (&__values)[2])
+{
+  static_assert(sizeof(_B32) == 4, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  asm("tcgen05.st.sync.aligned.16x128b.x1.unpack::16b.b32 [%0], {%1, %2};"
+      :
+      : "r"(__taddr), "r"(__as_b32(__values[0])), "r"(__as_b32(__values[1]))
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_st_16x128b_unpack_16b_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.st.sync.aligned.16x128b.x2.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_101a
+template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+__device__ static inline void tcgen05_st_16x128b(
+  uint32_t taddr,
+  const B32 (&values)[4]);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_st_16x128b_is_not_supported_before_SM_100a_SM_101a__();
+template <typename _B32, _CUDA_VSTD::enable_if_t<sizeof(_B32) == 4, bool> = true>
+_CCCL_DEVICE static inline void tcgen05_st_16x128b(_CUDA_VSTD::uint32_t __taddr, const _B32 (&__values)[4])
+{
+  static_assert(sizeof(_B32) == 4, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  asm("tcgen05.st.sync.aligned.16x128b.x2.b32 [%0], {%1, %2, %3, %4};"
+      :
+      : "r"(__taddr),
+        "r"(__as_b32(__values[0])),
+        "r"(__as_b32(__values[1])),
+        "r"(__as_b32(__values[2])),
+        "r"(__as_b32(__values[3]))
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_st_16x128b_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.st.sync.aligned.16x128b.x2.unpack::16b.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_101a
+template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+__device__ static inline void tcgen05_st_16x128b_unpack_16b(
+  uint32_t taddr,
+  const B32 (&values)[4]);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_st_16x128b_unpack_16b_is_not_supported_before_SM_100a_SM_101a__();
+template <typename _B32, _CUDA_VSTD::enable_if_t<sizeof(_B32) == 4, bool> = true>
+_CCCL_DEVICE static inline void tcgen05_st_16x128b_unpack_16b(_CUDA_VSTD::uint32_t __taddr, const _B32 (&__values)[4])
+{
+  static_assert(sizeof(_B32) == 4, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  asm("tcgen05.st.sync.aligned.16x128b.x2.unpack::16b.b32 [%0], {%1, %2, %3, %4};"
+      :
+      : "r"(__taddr),
+        "r"(__as_b32(__values[0])),
+        "r"(__as_b32(__values[1])),
+        "r"(__as_b32(__values[2])),
+        "r"(__as_b32(__values[3]))
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_st_16x128b_unpack_16b_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.st.sync.aligned.16x128b.x4.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_101a
+template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+__device__ static inline void tcgen05_st_16x128b(
+  uint32_t taddr,
+  const B32 (&values)[8]);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_st_16x128b_is_not_supported_before_SM_100a_SM_101a__();
+template <typename _B32, _CUDA_VSTD::enable_if_t<sizeof(_B32) == 4, bool> = true>
+_CCCL_DEVICE static inline void tcgen05_st_16x128b(_CUDA_VSTD::uint32_t __taddr, const _B32 (&__values)[8])
+{
+  static_assert(sizeof(_B32) == 4, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  asm("tcgen05.st.sync.aligned.16x128b.x4.b32 [%0], {%1, %2, %3, %4, %5, %6, %7, %8};"
+      :
+      : "r"(__taddr),
+        "r"(__as_b32(__values[0])),
+        "r"(__as_b32(__values[1])),
+        "r"(__as_b32(__values[2])),
+        "r"(__as_b32(__values[3])),
+        "r"(__as_b32(__values[4])),
+        "r"(__as_b32(__values[5])),
+        "r"(__as_b32(__values[6])),
+        "r"(__as_b32(__values[7]))
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_st_16x128b_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.st.sync.aligned.16x128b.x4.unpack::16b.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_101a
+template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+__device__ static inline void tcgen05_st_16x128b_unpack_16b(
+  uint32_t taddr,
+  const B32 (&values)[8]);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_st_16x128b_unpack_16b_is_not_supported_before_SM_100a_SM_101a__();
+template <typename _B32, _CUDA_VSTD::enable_if_t<sizeof(_B32) == 4, bool> = true>
+_CCCL_DEVICE static inline void tcgen05_st_16x128b_unpack_16b(_CUDA_VSTD::uint32_t __taddr, const _B32 (&__values)[8])
+{
+  static_assert(sizeof(_B32) == 4, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  asm("tcgen05.st.sync.aligned.16x128b.x4.unpack::16b.b32 [%0], {%1, %2, %3, %4, %5, %6, %7, %8};"
+      :
+      : "r"(__taddr),
+        "r"(__as_b32(__values[0])),
+        "r"(__as_b32(__values[1])),
+        "r"(__as_b32(__values[2])),
+        "r"(__as_b32(__values[3])),
+        "r"(__as_b32(__values[4])),
+        "r"(__as_b32(__values[5])),
+        "r"(__as_b32(__values[6])),
+        "r"(__as_b32(__values[7]))
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_st_16x128b_unpack_16b_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.st.sync.aligned.16x128b.x8.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_101a
+template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+__device__ static inline void tcgen05_st_16x128b(
+  uint32_t taddr,
+  const B32 (&values)[16]);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_st_16x128b_is_not_supported_before_SM_100a_SM_101a__();
+template <typename _B32, _CUDA_VSTD::enable_if_t<sizeof(_B32) == 4, bool> = true>
+_CCCL_DEVICE static inline void tcgen05_st_16x128b(_CUDA_VSTD::uint32_t __taddr, const _B32 (&__values)[16])
+{
+  static_assert(sizeof(_B32) == 4, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  asm("tcgen05.st.sync.aligned.16x128b.x8.b32 [%0], {%1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, "
+      "%16};"
+      :
+      : "r"(__taddr),
+        "r"(__as_b32(__values[0])),
+        "r"(__as_b32(__values[1])),
+        "r"(__as_b32(__values[2])),
+        "r"(__as_b32(__values[3])),
+        "r"(__as_b32(__values[4])),
+        "r"(__as_b32(__values[5])),
+        "r"(__as_b32(__values[6])),
+        "r"(__as_b32(__values[7])),
+        "r"(__as_b32(__values[8])),
+        "r"(__as_b32(__values[9])),
+        "r"(__as_b32(__values[10])),
+        "r"(__as_b32(__values[11])),
+        "r"(__as_b32(__values[12])),
+        "r"(__as_b32(__values[13])),
+        "r"(__as_b32(__values[14])),
+        "r"(__as_b32(__values[15]))
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_st_16x128b_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.st.sync.aligned.16x128b.x8.unpack::16b.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_101a
+template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+__device__ static inline void tcgen05_st_16x128b_unpack_16b(
+  uint32_t taddr,
+  const B32 (&values)[16]);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_st_16x128b_unpack_16b_is_not_supported_before_SM_100a_SM_101a__();
+template <typename _B32, _CUDA_VSTD::enable_if_t<sizeof(_B32) == 4, bool> = true>
+_CCCL_DEVICE static inline void tcgen05_st_16x128b_unpack_16b(_CUDA_VSTD::uint32_t __taddr, const _B32 (&__values)[16])
+{
+  static_assert(sizeof(_B32) == 4, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  asm("tcgen05.st.sync.aligned.16x128b.x8.unpack::16b.b32 [%0], {%1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, "
+      "%13, %14, %15, %16};"
+      :
+      : "r"(__taddr),
+        "r"(__as_b32(__values[0])),
+        "r"(__as_b32(__values[1])),
+        "r"(__as_b32(__values[2])),
+        "r"(__as_b32(__values[3])),
+        "r"(__as_b32(__values[4])),
+        "r"(__as_b32(__values[5])),
+        "r"(__as_b32(__values[6])),
+        "r"(__as_b32(__values[7])),
+        "r"(__as_b32(__values[8])),
+        "r"(__as_b32(__values[9])),
+        "r"(__as_b32(__values[10])),
+        "r"(__as_b32(__values[11])),
+        "r"(__as_b32(__values[12])),
+        "r"(__as_b32(__values[13])),
+        "r"(__as_b32(__values[14])),
+        "r"(__as_b32(__values[15]))
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_st_16x128b_unpack_16b_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.st.sync.aligned.16x128b.x16.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_101a
+template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+__device__ static inline void tcgen05_st_16x128b(
+  uint32_t taddr,
+  const B32 (&values)[32]);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_st_16x128b_is_not_supported_before_SM_100a_SM_101a__();
+template <typename _B32, _CUDA_VSTD::enable_if_t<sizeof(_B32) == 4, bool> = true>
+_CCCL_DEVICE static inline void tcgen05_st_16x128b(_CUDA_VSTD::uint32_t __taddr, const _B32 (&__values)[32])
+{
+  static_assert(sizeof(_B32) == 4, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  asm(
+    "tcgen05.st.sync.aligned.16x128b.x16.b32 [%0], {%1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, "
+    "%16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32};"
+    :
+    : "r"(__taddr),
+      "r"(__as_b32(__values[0])),
+      "r"(__as_b32(__values[1])),
+      "r"(__as_b32(__values[2])),
+      "r"(__as_b32(__values[3])),
+      "r"(__as_b32(__values[4])),
+      "r"(__as_b32(__values[5])),
+      "r"(__as_b32(__values[6])),
+      "r"(__as_b32(__values[7])),
+      "r"(__as_b32(__values[8])),
+      "r"(__as_b32(__values[9])),
+      "r"(__as_b32(__values[10])),
+      "r"(__as_b32(__values[11])),
+      "r"(__as_b32(__values[12])),
+      "r"(__as_b32(__values[13])),
+      "r"(__as_b32(__values[14])),
+      "r"(__as_b32(__values[15])),
+      "r"(__as_b32(__values[16])),
+      "r"(__as_b32(__values[17])),
+      "r"(__as_b32(__values[18])),
+      "r"(__as_b32(__values[19])),
+      "r"(__as_b32(__values[20])),
+      "r"(__as_b32(__values[21])),
+      "r"(__as_b32(__values[22])),
+      "r"(__as_b32(__values[23])),
+      "r"(__as_b32(__values[24])),
+      "r"(__as_b32(__values[25])),
+      "r"(__as_b32(__values[26])),
+      "r"(__as_b32(__values[27])),
+      "r"(__as_b32(__values[28])),
+      "r"(__as_b32(__values[29])),
+      "r"(__as_b32(__values[30])),
+      "r"(__as_b32(__values[31]))
+    : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_st_16x128b_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.st.sync.aligned.16x128b.x16.unpack::16b.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_101a
+template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+__device__ static inline void tcgen05_st_16x128b_unpack_16b(
+  uint32_t taddr,
+  const B32 (&values)[32]);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_st_16x128b_unpack_16b_is_not_supported_before_SM_100a_SM_101a__();
+template <typename _B32, _CUDA_VSTD::enable_if_t<sizeof(_B32) == 4, bool> = true>
+_CCCL_DEVICE static inline void tcgen05_st_16x128b_unpack_16b(_CUDA_VSTD::uint32_t __taddr, const _B32 (&__values)[32])
+{
+  static_assert(sizeof(_B32) == 4, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  asm(
+    "tcgen05.st.sync.aligned.16x128b.x16.unpack::16b.b32 [%0], {%1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, "
+    "%13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32};"
+    :
+    : "r"(__taddr),
+      "r"(__as_b32(__values[0])),
+      "r"(__as_b32(__values[1])),
+      "r"(__as_b32(__values[2])),
+      "r"(__as_b32(__values[3])),
+      "r"(__as_b32(__values[4])),
+      "r"(__as_b32(__values[5])),
+      "r"(__as_b32(__values[6])),
+      "r"(__as_b32(__values[7])),
+      "r"(__as_b32(__values[8])),
+      "r"(__as_b32(__values[9])),
+      "r"(__as_b32(__values[10])),
+      "r"(__as_b32(__values[11])),
+      "r"(__as_b32(__values[12])),
+      "r"(__as_b32(__values[13])),
+      "r"(__as_b32(__values[14])),
+      "r"(__as_b32(__values[15])),
+      "r"(__as_b32(__values[16])),
+      "r"(__as_b32(__values[17])),
+      "r"(__as_b32(__values[18])),
+      "r"(__as_b32(__values[19])),
+      "r"(__as_b32(__values[20])),
+      "r"(__as_b32(__values[21])),
+      "r"(__as_b32(__values[22])),
+      "r"(__as_b32(__values[23])),
+      "r"(__as_b32(__values[24])),
+      "r"(__as_b32(__values[25])),
+      "r"(__as_b32(__values[26])),
+      "r"(__as_b32(__values[27])),
+      "r"(__as_b32(__values[28])),
+      "r"(__as_b32(__values[29])),
+      "r"(__as_b32(__values[30])),
+      "r"(__as_b32(__values[31]))
+    : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_st_16x128b_unpack_16b_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.st.sync.aligned.16x128b.x32.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_101a
+template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+__device__ static inline void tcgen05_st_16x128b(
+  uint32_t taddr,
+  const B32 (&values)[64]);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_st_16x128b_is_not_supported_before_SM_100a_SM_101a__();
+template <typename _B32, _CUDA_VSTD::enable_if_t<sizeof(_B32) == 4, bool> = true>
+_CCCL_DEVICE static inline void tcgen05_st_16x128b(_CUDA_VSTD::uint32_t __taddr, const _B32 (&__values)[64])
+{
+  static_assert(sizeof(_B32) == 4, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  asm(
+    "tcgen05.st.sync.aligned.16x128b.x32.b32 [%0], {%1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, "
+    "%16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, "
+    "%38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, "
+    "%60, %61, %62, %63, %64};"
+    :
+    : "r"(__taddr),
+      "r"(__as_b32(__values[0])),
+      "r"(__as_b32(__values[1])),
+      "r"(__as_b32(__values[2])),
+      "r"(__as_b32(__values[3])),
+      "r"(__as_b32(__values[4])),
+      "r"(__as_b32(__values[5])),
+      "r"(__as_b32(__values[6])),
+      "r"(__as_b32(__values[7])),
+      "r"(__as_b32(__values[8])),
+      "r"(__as_b32(__values[9])),
+      "r"(__as_b32(__values[10])),
+      "r"(__as_b32(__values[11])),
+      "r"(__as_b32(__values[12])),
+      "r"(__as_b32(__values[13])),
+      "r"(__as_b32(__values[14])),
+      "r"(__as_b32(__values[15])),
+      "r"(__as_b32(__values[16])),
+      "r"(__as_b32(__values[17])),
+      "r"(__as_b32(__values[18])),
+      "r"(__as_b32(__values[19])),
+      "r"(__as_b32(__values[20])),
+      "r"(__as_b32(__values[21])),
+      "r"(__as_b32(__values[22])),
+      "r"(__as_b32(__values[23])),
+      "r"(__as_b32(__values[24])),
+      "r"(__as_b32(__values[25])),
+      "r"(__as_b32(__values[26])),
+      "r"(__as_b32(__values[27])),
+      "r"(__as_b32(__values[28])),
+      "r"(__as_b32(__values[29])),
+      "r"(__as_b32(__values[30])),
+      "r"(__as_b32(__values[31])),
+      "r"(__as_b32(__values[32])),
+      "r"(__as_b32(__values[33])),
+      "r"(__as_b32(__values[34])),
+      "r"(__as_b32(__values[35])),
+      "r"(__as_b32(__values[36])),
+      "r"(__as_b32(__values[37])),
+      "r"(__as_b32(__values[38])),
+      "r"(__as_b32(__values[39])),
+      "r"(__as_b32(__values[40])),
+      "r"(__as_b32(__values[41])),
+      "r"(__as_b32(__values[42])),
+      "r"(__as_b32(__values[43])),
+      "r"(__as_b32(__values[44])),
+      "r"(__as_b32(__values[45])),
+      "r"(__as_b32(__values[46])),
+      "r"(__as_b32(__values[47])),
+      "r"(__as_b32(__values[48])),
+      "r"(__as_b32(__values[49])),
+      "r"(__as_b32(__values[50])),
+      "r"(__as_b32(__values[51])),
+      "r"(__as_b32(__values[52])),
+      "r"(__as_b32(__values[53])),
+      "r"(__as_b32(__values[54])),
+      "r"(__as_b32(__values[55])),
+      "r"(__as_b32(__values[56])),
+      "r"(__as_b32(__values[57])),
+      "r"(__as_b32(__values[58])),
+      "r"(__as_b32(__values[59])),
+      "r"(__as_b32(__values[60])),
+      "r"(__as_b32(__values[61])),
+      "r"(__as_b32(__values[62])),
+      "r"(__as_b32(__values[63]))
+    : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_st_16x128b_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.st.sync.aligned.16x128b.x32.unpack::16b.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_101a
+template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+__device__ static inline void tcgen05_st_16x128b_unpack_16b(
+  uint32_t taddr,
+  const B32 (&values)[64]);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_st_16x128b_unpack_16b_is_not_supported_before_SM_100a_SM_101a__();
+template <typename _B32, _CUDA_VSTD::enable_if_t<sizeof(_B32) == 4, bool> = true>
+_CCCL_DEVICE static inline void tcgen05_st_16x128b_unpack_16b(_CUDA_VSTD::uint32_t __taddr, const _B32 (&__values)[64])
+{
+  static_assert(sizeof(_B32) == 4, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  asm(
+    "tcgen05.st.sync.aligned.16x128b.x32.unpack::16b.b32 [%0], {%1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, "
+    "%13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, "
+    "%35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, "
+    "%57, %58, %59, %60, %61, %62, %63, %64};"
+    :
+    : "r"(__taddr),
+      "r"(__as_b32(__values[0])),
+      "r"(__as_b32(__values[1])),
+      "r"(__as_b32(__values[2])),
+      "r"(__as_b32(__values[3])),
+      "r"(__as_b32(__values[4])),
+      "r"(__as_b32(__values[5])),
+      "r"(__as_b32(__values[6])),
+      "r"(__as_b32(__values[7])),
+      "r"(__as_b32(__values[8])),
+      "r"(__as_b32(__values[9])),
+      "r"(__as_b32(__values[10])),
+      "r"(__as_b32(__values[11])),
+      "r"(__as_b32(__values[12])),
+      "r"(__as_b32(__values[13])),
+      "r"(__as_b32(__values[14])),
+      "r"(__as_b32(__values[15])),
+      "r"(__as_b32(__values[16])),
+      "r"(__as_b32(__values[17])),
+      "r"(__as_b32(__values[18])),
+      "r"(__as_b32(__values[19])),
+      "r"(__as_b32(__values[20])),
+      "r"(__as_b32(__values[21])),
+      "r"(__as_b32(__values[22])),
+      "r"(__as_b32(__values[23])),
+      "r"(__as_b32(__values[24])),
+      "r"(__as_b32(__values[25])),
+      "r"(__as_b32(__values[26])),
+      "r"(__as_b32(__values[27])),
+      "r"(__as_b32(__values[28])),
+      "r"(__as_b32(__values[29])),
+      "r"(__as_b32(__values[30])),
+      "r"(__as_b32(__values[31])),
+      "r"(__as_b32(__values[32])),
+      "r"(__as_b32(__values[33])),
+      "r"(__as_b32(__values[34])),
+      "r"(__as_b32(__values[35])),
+      "r"(__as_b32(__values[36])),
+      "r"(__as_b32(__values[37])),
+      "r"(__as_b32(__values[38])),
+      "r"(__as_b32(__values[39])),
+      "r"(__as_b32(__values[40])),
+      "r"(__as_b32(__values[41])),
+      "r"(__as_b32(__values[42])),
+      "r"(__as_b32(__values[43])),
+      "r"(__as_b32(__values[44])),
+      "r"(__as_b32(__values[45])),
+      "r"(__as_b32(__values[46])),
+      "r"(__as_b32(__values[47])),
+      "r"(__as_b32(__values[48])),
+      "r"(__as_b32(__values[49])),
+      "r"(__as_b32(__values[50])),
+      "r"(__as_b32(__values[51])),
+      "r"(__as_b32(__values[52])),
+      "r"(__as_b32(__values[53])),
+      "r"(__as_b32(__values[54])),
+      "r"(__as_b32(__values[55])),
+      "r"(__as_b32(__values[56])),
+      "r"(__as_b32(__values[57])),
+      "r"(__as_b32(__values[58])),
+      "r"(__as_b32(__values[59])),
+      "r"(__as_b32(__values[60])),
+      "r"(__as_b32(__values[61])),
+      "r"(__as_b32(__values[62])),
+      "r"(__as_b32(__values[63]))
+    : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_st_16x128b_unpack_16b_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.st.sync.aligned.16x128b.x64.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_101a
+template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+__device__ static inline void tcgen05_st_16x128b(
+  uint32_t taddr,
+  const B32 (&values)[128]);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_st_16x128b_is_not_supported_before_SM_100a_SM_101a__();
+template <typename _B32, _CUDA_VSTD::enable_if_t<sizeof(_B32) == 4, bool> = true>
+_CCCL_DEVICE static inline void tcgen05_st_16x128b(_CUDA_VSTD::uint32_t __taddr, const _B32 (&__values)[128])
+{
+  static_assert(sizeof(_B32) == 4, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  asm(
+    "tcgen05.st.sync.aligned.16x128b.x64.b32 [%0], {%1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, "
+    "%16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, "
+    "%38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, "
+    "%60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, "
+    "%82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, "
+    "%104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, "
+    "%123, %124, %125, %126, %127, %128};"
+    :
+    : "r"(__taddr),
+      "r"(__as_b32(__values[0])),
+      "r"(__as_b32(__values[1])),
+      "r"(__as_b32(__values[2])),
+      "r"(__as_b32(__values[3])),
+      "r"(__as_b32(__values[4])),
+      "r"(__as_b32(__values[5])),
+      "r"(__as_b32(__values[6])),
+      "r"(__as_b32(__values[7])),
+      "r"(__as_b32(__values[8])),
+      "r"(__as_b32(__values[9])),
+      "r"(__as_b32(__values[10])),
+      "r"(__as_b32(__values[11])),
+      "r"(__as_b32(__values[12])),
+      "r"(__as_b32(__values[13])),
+      "r"(__as_b32(__values[14])),
+      "r"(__as_b32(__values[15])),
+      "r"(__as_b32(__values[16])),
+      "r"(__as_b32(__values[17])),
+      "r"(__as_b32(__values[18])),
+      "r"(__as_b32(__values[19])),
+      "r"(__as_b32(__values[20])),
+      "r"(__as_b32(__values[21])),
+      "r"(__as_b32(__values[22])),
+      "r"(__as_b32(__values[23])),
+      "r"(__as_b32(__values[24])),
+      "r"(__as_b32(__values[25])),
+      "r"(__as_b32(__values[26])),
+      "r"(__as_b32(__values[27])),
+      "r"(__as_b32(__values[28])),
+      "r"(__as_b32(__values[29])),
+      "r"(__as_b32(__values[30])),
+      "r"(__as_b32(__values[31])),
+      "r"(__as_b32(__values[32])),
+      "r"(__as_b32(__values[33])),
+      "r"(__as_b32(__values[34])),
+      "r"(__as_b32(__values[35])),
+      "r"(__as_b32(__values[36])),
+      "r"(__as_b32(__values[37])),
+      "r"(__as_b32(__values[38])),
+      "r"(__as_b32(__values[39])),
+      "r"(__as_b32(__values[40])),
+      "r"(__as_b32(__values[41])),
+      "r"(__as_b32(__values[42])),
+      "r"(__as_b32(__values[43])),
+      "r"(__as_b32(__values[44])),
+      "r"(__as_b32(__values[45])),
+      "r"(__as_b32(__values[46])),
+      "r"(__as_b32(__values[47])),
+      "r"(__as_b32(__values[48])),
+      "r"(__as_b32(__values[49])),
+      "r"(__as_b32(__values[50])),
+      "r"(__as_b32(__values[51])),
+      "r"(__as_b32(__values[52])),
+      "r"(__as_b32(__values[53])),
+      "r"(__as_b32(__values[54])),
+      "r"(__as_b32(__values[55])),
+      "r"(__as_b32(__values[56])),
+      "r"(__as_b32(__values[57])),
+      "r"(__as_b32(__values[58])),
+      "r"(__as_b32(__values[59])),
+      "r"(__as_b32(__values[60])),
+      "r"(__as_b32(__values[61])),
+      "r"(__as_b32(__values[62])),
+      "r"(__as_b32(__values[63])),
+      "r"(__as_b32(__values[64])),
+      "r"(__as_b32(__values[65])),
+      "r"(__as_b32(__values[66])),
+      "r"(__as_b32(__values[67])),
+      "r"(__as_b32(__values[68])),
+      "r"(__as_b32(__values[69])),
+      "r"(__as_b32(__values[70])),
+      "r"(__as_b32(__values[71])),
+      "r"(__as_b32(__values[72])),
+      "r"(__as_b32(__values[73])),
+      "r"(__as_b32(__values[74])),
+      "r"(__as_b32(__values[75])),
+      "r"(__as_b32(__values[76])),
+      "r"(__as_b32(__values[77])),
+      "r"(__as_b32(__values[78])),
+      "r"(__as_b32(__values[79])),
+      "r"(__as_b32(__values[80])),
+      "r"(__as_b32(__values[81])),
+      "r"(__as_b32(__values[82])),
+      "r"(__as_b32(__values[83])),
+      "r"(__as_b32(__values[84])),
+      "r"(__as_b32(__values[85])),
+      "r"(__as_b32(__values[86])),
+      "r"(__as_b32(__values[87])),
+      "r"(__as_b32(__values[88])),
+      "r"(__as_b32(__values[89])),
+      "r"(__as_b32(__values[90])),
+      "r"(__as_b32(__values[91])),
+      "r"(__as_b32(__values[92])),
+      "r"(__as_b32(__values[93])),
+      "r"(__as_b32(__values[94])),
+      "r"(__as_b32(__values[95])),
+      "r"(__as_b32(__values[96])),
+      "r"(__as_b32(__values[97])),
+      "r"(__as_b32(__values[98])),
+      "r"(__as_b32(__values[99])),
+      "r"(__as_b32(__values[100])),
+      "r"(__as_b32(__values[101])),
+      "r"(__as_b32(__values[102])),
+      "r"(__as_b32(__values[103])),
+      "r"(__as_b32(__values[104])),
+      "r"(__as_b32(__values[105])),
+      "r"(__as_b32(__values[106])),
+      "r"(__as_b32(__values[107])),
+      "r"(__as_b32(__values[108])),
+      "r"(__as_b32(__values[109])),
+      "r"(__as_b32(__values[110])),
+      "r"(__as_b32(__values[111])),
+      "r"(__as_b32(__values[112])),
+      "r"(__as_b32(__values[113])),
+      "r"(__as_b32(__values[114])),
+      "r"(__as_b32(__values[115])),
+      "r"(__as_b32(__values[116])),
+      "r"(__as_b32(__values[117])),
+      "r"(__as_b32(__values[118])),
+      "r"(__as_b32(__values[119])),
+      "r"(__as_b32(__values[120])),
+      "r"(__as_b32(__values[121])),
+      "r"(__as_b32(__values[122])),
+      "r"(__as_b32(__values[123])),
+      "r"(__as_b32(__values[124])),
+      "r"(__as_b32(__values[125])),
+      "r"(__as_b32(__values[126])),
+      "r"(__as_b32(__values[127]))
+    : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_st_16x128b_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.st.sync.aligned.16x128b.x64.unpack::16b.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_101a
+template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+__device__ static inline void tcgen05_st_16x128b_unpack_16b(
+  uint32_t taddr,
+  const B32 (&values)[128]);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_st_16x128b_unpack_16b_is_not_supported_before_SM_100a_SM_101a__();
+template <typename _B32, _CUDA_VSTD::enable_if_t<sizeof(_B32) == 4, bool> = true>
+_CCCL_DEVICE static inline void tcgen05_st_16x128b_unpack_16b(_CUDA_VSTD::uint32_t __taddr, const _B32 (&__values)[128])
+{
+  static_assert(sizeof(_B32) == 4, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  asm(
+    "tcgen05.st.sync.aligned.16x128b.x64.unpack::16b.b32 [%0], {%1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, "
+    "%13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, "
+    "%35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, "
+    "%57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, "
+    "%79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, "
+    "%101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, "
+    "%120, %121, %122, %123, %124, %125, %126, %127, %128};"
+    :
+    : "r"(__taddr),
+      "r"(__as_b32(__values[0])),
+      "r"(__as_b32(__values[1])),
+      "r"(__as_b32(__values[2])),
+      "r"(__as_b32(__values[3])),
+      "r"(__as_b32(__values[4])),
+      "r"(__as_b32(__values[5])),
+      "r"(__as_b32(__values[6])),
+      "r"(__as_b32(__values[7])),
+      "r"(__as_b32(__values[8])),
+      "r"(__as_b32(__values[9])),
+      "r"(__as_b32(__values[10])),
+      "r"(__as_b32(__values[11])),
+      "r"(__as_b32(__values[12])),
+      "r"(__as_b32(__values[13])),
+      "r"(__as_b32(__values[14])),
+      "r"(__as_b32(__values[15])),
+      "r"(__as_b32(__values[16])),
+      "r"(__as_b32(__values[17])),
+      "r"(__as_b32(__values[18])),
+      "r"(__as_b32(__values[19])),
+      "r"(__as_b32(__values[20])),
+      "r"(__as_b32(__values[21])),
+      "r"(__as_b32(__values[22])),
+      "r"(__as_b32(__values[23])),
+      "r"(__as_b32(__values[24])),
+      "r"(__as_b32(__values[25])),
+      "r"(__as_b32(__values[26])),
+      "r"(__as_b32(__values[27])),
+      "r"(__as_b32(__values[28])),
+      "r"(__as_b32(__values[29])),
+      "r"(__as_b32(__values[30])),
+      "r"(__as_b32(__values[31])),
+      "r"(__as_b32(__values[32])),
+      "r"(__as_b32(__values[33])),
+      "r"(__as_b32(__values[34])),
+      "r"(__as_b32(__values[35])),
+      "r"(__as_b32(__values[36])),
+      "r"(__as_b32(__values[37])),
+      "r"(__as_b32(__values[38])),
+      "r"(__as_b32(__values[39])),
+      "r"(__as_b32(__values[40])),
+      "r"(__as_b32(__values[41])),
+      "r"(__as_b32(__values[42])),
+      "r"(__as_b32(__values[43])),
+      "r"(__as_b32(__values[44])),
+      "r"(__as_b32(__values[45])),
+      "r"(__as_b32(__values[46])),
+      "r"(__as_b32(__values[47])),
+      "r"(__as_b32(__values[48])),
+      "r"(__as_b32(__values[49])),
+      "r"(__as_b32(__values[50])),
+      "r"(__as_b32(__values[51])),
+      "r"(__as_b32(__values[52])),
+      "r"(__as_b32(__values[53])),
+      "r"(__as_b32(__values[54])),
+      "r"(__as_b32(__values[55])),
+      "r"(__as_b32(__values[56])),
+      "r"(__as_b32(__values[57])),
+      "r"(__as_b32(__values[58])),
+      "r"(__as_b32(__values[59])),
+      "r"(__as_b32(__values[60])),
+      "r"(__as_b32(__values[61])),
+      "r"(__as_b32(__values[62])),
+      "r"(__as_b32(__values[63])),
+      "r"(__as_b32(__values[64])),
+      "r"(__as_b32(__values[65])),
+      "r"(__as_b32(__values[66])),
+      "r"(__as_b32(__values[67])),
+      "r"(__as_b32(__values[68])),
+      "r"(__as_b32(__values[69])),
+      "r"(__as_b32(__values[70])),
+      "r"(__as_b32(__values[71])),
+      "r"(__as_b32(__values[72])),
+      "r"(__as_b32(__values[73])),
+      "r"(__as_b32(__values[74])),
+      "r"(__as_b32(__values[75])),
+      "r"(__as_b32(__values[76])),
+      "r"(__as_b32(__values[77])),
+      "r"(__as_b32(__values[78])),
+      "r"(__as_b32(__values[79])),
+      "r"(__as_b32(__values[80])),
+      "r"(__as_b32(__values[81])),
+      "r"(__as_b32(__values[82])),
+      "r"(__as_b32(__values[83])),
+      "r"(__as_b32(__values[84])),
+      "r"(__as_b32(__values[85])),
+      "r"(__as_b32(__values[86])),
+      "r"(__as_b32(__values[87])),
+      "r"(__as_b32(__values[88])),
+      "r"(__as_b32(__values[89])),
+      "r"(__as_b32(__values[90])),
+      "r"(__as_b32(__values[91])),
+      "r"(__as_b32(__values[92])),
+      "r"(__as_b32(__values[93])),
+      "r"(__as_b32(__values[94])),
+      "r"(__as_b32(__values[95])),
+      "r"(__as_b32(__values[96])),
+      "r"(__as_b32(__values[97])),
+      "r"(__as_b32(__values[98])),
+      "r"(__as_b32(__values[99])),
+      "r"(__as_b32(__values[100])),
+      "r"(__as_b32(__values[101])),
+      "r"(__as_b32(__values[102])),
+      "r"(__as_b32(__values[103])),
+      "r"(__as_b32(__values[104])),
+      "r"(__as_b32(__values[105])),
+      "r"(__as_b32(__values[106])),
+      "r"(__as_b32(__values[107])),
+      "r"(__as_b32(__values[108])),
+      "r"(__as_b32(__values[109])),
+      "r"(__as_b32(__values[110])),
+      "r"(__as_b32(__values[111])),
+      "r"(__as_b32(__values[112])),
+      "r"(__as_b32(__values[113])),
+      "r"(__as_b32(__values[114])),
+      "r"(__as_b32(__values[115])),
+      "r"(__as_b32(__values[116])),
+      "r"(__as_b32(__values[117])),
+      "r"(__as_b32(__values[118])),
+      "r"(__as_b32(__values[119])),
+      "r"(__as_b32(__values[120])),
+      "r"(__as_b32(__values[121])),
+      "r"(__as_b32(__values[122])),
+      "r"(__as_b32(__values[123])),
+      "r"(__as_b32(__values[124])),
+      "r"(__as_b32(__values[125])),
+      "r"(__as_b32(__values[126])),
+      "r"(__as_b32(__values[127]))
+    : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_st_16x128b_unpack_16b_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.st.sync.aligned.16x256b.x1.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_101a
+template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+__device__ static inline void tcgen05_st_16x256b(
+  uint32_t taddr,
+  const B32 (&values)[4]);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_st_16x256b_is_not_supported_before_SM_100a_SM_101a__();
+template <typename _B32, _CUDA_VSTD::enable_if_t<sizeof(_B32) == 4, bool> = true>
+_CCCL_DEVICE static inline void tcgen05_st_16x256b(_CUDA_VSTD::uint32_t __taddr, const _B32 (&__values)[4])
+{
+  static_assert(sizeof(_B32) == 4, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  asm("tcgen05.st.sync.aligned.16x256b.x1.b32 [%0], {%1, %2, %3, %4};"
+      :
+      : "r"(__taddr),
+        "r"(__as_b32(__values[0])),
+        "r"(__as_b32(__values[1])),
+        "r"(__as_b32(__values[2])),
+        "r"(__as_b32(__values[3]))
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_st_16x256b_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.st.sync.aligned.16x256b.x1.unpack::16b.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_101a
+template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+__device__ static inline void tcgen05_st_16x256b_unpack_16b(
+  uint32_t taddr,
+  const B32 (&values)[4]);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_st_16x256b_unpack_16b_is_not_supported_before_SM_100a_SM_101a__();
+template <typename _B32, _CUDA_VSTD::enable_if_t<sizeof(_B32) == 4, bool> = true>
+_CCCL_DEVICE static inline void tcgen05_st_16x256b_unpack_16b(_CUDA_VSTD::uint32_t __taddr, const _B32 (&__values)[4])
+{
+  static_assert(sizeof(_B32) == 4, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  asm("tcgen05.st.sync.aligned.16x256b.x1.unpack::16b.b32 [%0], {%1, %2, %3, %4};"
+      :
+      : "r"(__taddr),
+        "r"(__as_b32(__values[0])),
+        "r"(__as_b32(__values[1])),
+        "r"(__as_b32(__values[2])),
+        "r"(__as_b32(__values[3]))
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_st_16x256b_unpack_16b_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.st.sync.aligned.16x256b.x2.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_101a
+template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+__device__ static inline void tcgen05_st_16x256b(
+  uint32_t taddr,
+  const B32 (&values)[8]);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_st_16x256b_is_not_supported_before_SM_100a_SM_101a__();
+template <typename _B32, _CUDA_VSTD::enable_if_t<sizeof(_B32) == 4, bool> = true>
+_CCCL_DEVICE static inline void tcgen05_st_16x256b(_CUDA_VSTD::uint32_t __taddr, const _B32 (&__values)[8])
+{
+  static_assert(sizeof(_B32) == 4, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  asm("tcgen05.st.sync.aligned.16x256b.x2.b32 [%0], {%1, %2, %3, %4, %5, %6, %7, %8};"
+      :
+      : "r"(__taddr),
+        "r"(__as_b32(__values[0])),
+        "r"(__as_b32(__values[1])),
+        "r"(__as_b32(__values[2])),
+        "r"(__as_b32(__values[3])),
+        "r"(__as_b32(__values[4])),
+        "r"(__as_b32(__values[5])),
+        "r"(__as_b32(__values[6])),
+        "r"(__as_b32(__values[7]))
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_st_16x256b_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.st.sync.aligned.16x256b.x2.unpack::16b.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_101a
+template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+__device__ static inline void tcgen05_st_16x256b_unpack_16b(
+  uint32_t taddr,
+  const B32 (&values)[8]);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_st_16x256b_unpack_16b_is_not_supported_before_SM_100a_SM_101a__();
+template <typename _B32, _CUDA_VSTD::enable_if_t<sizeof(_B32) == 4, bool> = true>
+_CCCL_DEVICE static inline void tcgen05_st_16x256b_unpack_16b(_CUDA_VSTD::uint32_t __taddr, const _B32 (&__values)[8])
+{
+  static_assert(sizeof(_B32) == 4, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  asm("tcgen05.st.sync.aligned.16x256b.x2.unpack::16b.b32 [%0], {%1, %2, %3, %4, %5, %6, %7, %8};"
+      :
+      : "r"(__taddr),
+        "r"(__as_b32(__values[0])),
+        "r"(__as_b32(__values[1])),
+        "r"(__as_b32(__values[2])),
+        "r"(__as_b32(__values[3])),
+        "r"(__as_b32(__values[4])),
+        "r"(__as_b32(__values[5])),
+        "r"(__as_b32(__values[6])),
+        "r"(__as_b32(__values[7]))
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_st_16x256b_unpack_16b_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.st.sync.aligned.16x256b.x4.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_101a
+template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+__device__ static inline void tcgen05_st_16x256b(
+  uint32_t taddr,
+  const B32 (&values)[16]);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_st_16x256b_is_not_supported_before_SM_100a_SM_101a__();
+template <typename _B32, _CUDA_VSTD::enable_if_t<sizeof(_B32) == 4, bool> = true>
+_CCCL_DEVICE static inline void tcgen05_st_16x256b(_CUDA_VSTD::uint32_t __taddr, const _B32 (&__values)[16])
+{
+  static_assert(sizeof(_B32) == 4, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  asm("tcgen05.st.sync.aligned.16x256b.x4.b32 [%0], {%1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, "
+      "%16};"
+      :
+      : "r"(__taddr),
+        "r"(__as_b32(__values[0])),
+        "r"(__as_b32(__values[1])),
+        "r"(__as_b32(__values[2])),
+        "r"(__as_b32(__values[3])),
+        "r"(__as_b32(__values[4])),
+        "r"(__as_b32(__values[5])),
+        "r"(__as_b32(__values[6])),
+        "r"(__as_b32(__values[7])),
+        "r"(__as_b32(__values[8])),
+        "r"(__as_b32(__values[9])),
+        "r"(__as_b32(__values[10])),
+        "r"(__as_b32(__values[11])),
+        "r"(__as_b32(__values[12])),
+        "r"(__as_b32(__values[13])),
+        "r"(__as_b32(__values[14])),
+        "r"(__as_b32(__values[15]))
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_st_16x256b_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.st.sync.aligned.16x256b.x4.unpack::16b.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_101a
+template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+__device__ static inline void tcgen05_st_16x256b_unpack_16b(
+  uint32_t taddr,
+  const B32 (&values)[16]);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_st_16x256b_unpack_16b_is_not_supported_before_SM_100a_SM_101a__();
+template <typename _B32, _CUDA_VSTD::enable_if_t<sizeof(_B32) == 4, bool> = true>
+_CCCL_DEVICE static inline void tcgen05_st_16x256b_unpack_16b(_CUDA_VSTD::uint32_t __taddr, const _B32 (&__values)[16])
+{
+  static_assert(sizeof(_B32) == 4, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  asm("tcgen05.st.sync.aligned.16x256b.x4.unpack::16b.b32 [%0], {%1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, "
+      "%13, %14, %15, %16};"
+      :
+      : "r"(__taddr),
+        "r"(__as_b32(__values[0])),
+        "r"(__as_b32(__values[1])),
+        "r"(__as_b32(__values[2])),
+        "r"(__as_b32(__values[3])),
+        "r"(__as_b32(__values[4])),
+        "r"(__as_b32(__values[5])),
+        "r"(__as_b32(__values[6])),
+        "r"(__as_b32(__values[7])),
+        "r"(__as_b32(__values[8])),
+        "r"(__as_b32(__values[9])),
+        "r"(__as_b32(__values[10])),
+        "r"(__as_b32(__values[11])),
+        "r"(__as_b32(__values[12])),
+        "r"(__as_b32(__values[13])),
+        "r"(__as_b32(__values[14])),
+        "r"(__as_b32(__values[15]))
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_st_16x256b_unpack_16b_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.st.sync.aligned.16x256b.x8.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_101a
+template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+__device__ static inline void tcgen05_st_16x256b(
+  uint32_t taddr,
+  const B32 (&values)[32]);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_st_16x256b_is_not_supported_before_SM_100a_SM_101a__();
+template <typename _B32, _CUDA_VSTD::enable_if_t<sizeof(_B32) == 4, bool> = true>
+_CCCL_DEVICE static inline void tcgen05_st_16x256b(_CUDA_VSTD::uint32_t __taddr, const _B32 (&__values)[32])
+{
+  static_assert(sizeof(_B32) == 4, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  asm(
+    "tcgen05.st.sync.aligned.16x256b.x8.b32 [%0], {%1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, "
+    "%16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32};"
+    :
+    : "r"(__taddr),
+      "r"(__as_b32(__values[0])),
+      "r"(__as_b32(__values[1])),
+      "r"(__as_b32(__values[2])),
+      "r"(__as_b32(__values[3])),
+      "r"(__as_b32(__values[4])),
+      "r"(__as_b32(__values[5])),
+      "r"(__as_b32(__values[6])),
+      "r"(__as_b32(__values[7])),
+      "r"(__as_b32(__values[8])),
+      "r"(__as_b32(__values[9])),
+      "r"(__as_b32(__values[10])),
+      "r"(__as_b32(__values[11])),
+      "r"(__as_b32(__values[12])),
+      "r"(__as_b32(__values[13])),
+      "r"(__as_b32(__values[14])),
+      "r"(__as_b32(__values[15])),
+      "r"(__as_b32(__values[16])),
+      "r"(__as_b32(__values[17])),
+      "r"(__as_b32(__values[18])),
+      "r"(__as_b32(__values[19])),
+      "r"(__as_b32(__values[20])),
+      "r"(__as_b32(__values[21])),
+      "r"(__as_b32(__values[22])),
+      "r"(__as_b32(__values[23])),
+      "r"(__as_b32(__values[24])),
+      "r"(__as_b32(__values[25])),
+      "r"(__as_b32(__values[26])),
+      "r"(__as_b32(__values[27])),
+      "r"(__as_b32(__values[28])),
+      "r"(__as_b32(__values[29])),
+      "r"(__as_b32(__values[30])),
+      "r"(__as_b32(__values[31]))
+    : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_st_16x256b_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.st.sync.aligned.16x256b.x8.unpack::16b.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_101a
+template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+__device__ static inline void tcgen05_st_16x256b_unpack_16b(
+  uint32_t taddr,
+  const B32 (&values)[32]);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_st_16x256b_unpack_16b_is_not_supported_before_SM_100a_SM_101a__();
+template <typename _B32, _CUDA_VSTD::enable_if_t<sizeof(_B32) == 4, bool> = true>
+_CCCL_DEVICE static inline void tcgen05_st_16x256b_unpack_16b(_CUDA_VSTD::uint32_t __taddr, const _B32 (&__values)[32])
+{
+  static_assert(sizeof(_B32) == 4, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  asm(
+    "tcgen05.st.sync.aligned.16x256b.x8.unpack::16b.b32 [%0], {%1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, "
+    "%14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32};"
+    :
+    : "r"(__taddr),
+      "r"(__as_b32(__values[0])),
+      "r"(__as_b32(__values[1])),
+      "r"(__as_b32(__values[2])),
+      "r"(__as_b32(__values[3])),
+      "r"(__as_b32(__values[4])),
+      "r"(__as_b32(__values[5])),
+      "r"(__as_b32(__values[6])),
+      "r"(__as_b32(__values[7])),
+      "r"(__as_b32(__values[8])),
+      "r"(__as_b32(__values[9])),
+      "r"(__as_b32(__values[10])),
+      "r"(__as_b32(__values[11])),
+      "r"(__as_b32(__values[12])),
+      "r"(__as_b32(__values[13])),
+      "r"(__as_b32(__values[14])),
+      "r"(__as_b32(__values[15])),
+      "r"(__as_b32(__values[16])),
+      "r"(__as_b32(__values[17])),
+      "r"(__as_b32(__values[18])),
+      "r"(__as_b32(__values[19])),
+      "r"(__as_b32(__values[20])),
+      "r"(__as_b32(__values[21])),
+      "r"(__as_b32(__values[22])),
+      "r"(__as_b32(__values[23])),
+      "r"(__as_b32(__values[24])),
+      "r"(__as_b32(__values[25])),
+      "r"(__as_b32(__values[26])),
+      "r"(__as_b32(__values[27])),
+      "r"(__as_b32(__values[28])),
+      "r"(__as_b32(__values[29])),
+      "r"(__as_b32(__values[30])),
+      "r"(__as_b32(__values[31]))
+    : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_st_16x256b_unpack_16b_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.st.sync.aligned.16x256b.x16.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_101a
+template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+__device__ static inline void tcgen05_st_16x256b(
+  uint32_t taddr,
+  const B32 (&values)[64]);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_st_16x256b_is_not_supported_before_SM_100a_SM_101a__();
+template <typename _B32, _CUDA_VSTD::enable_if_t<sizeof(_B32) == 4, bool> = true>
+_CCCL_DEVICE static inline void tcgen05_st_16x256b(_CUDA_VSTD::uint32_t __taddr, const _B32 (&__values)[64])
+{
+  static_assert(sizeof(_B32) == 4, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  asm(
+    "tcgen05.st.sync.aligned.16x256b.x16.b32 [%0], {%1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, "
+    "%16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, "
+    "%38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, "
+    "%60, %61, %62, %63, %64};"
+    :
+    : "r"(__taddr),
+      "r"(__as_b32(__values[0])),
+      "r"(__as_b32(__values[1])),
+      "r"(__as_b32(__values[2])),
+      "r"(__as_b32(__values[3])),
+      "r"(__as_b32(__values[4])),
+      "r"(__as_b32(__values[5])),
+      "r"(__as_b32(__values[6])),
+      "r"(__as_b32(__values[7])),
+      "r"(__as_b32(__values[8])),
+      "r"(__as_b32(__values[9])),
+      "r"(__as_b32(__values[10])),
+      "r"(__as_b32(__values[11])),
+      "r"(__as_b32(__values[12])),
+      "r"(__as_b32(__values[13])),
+      "r"(__as_b32(__values[14])),
+      "r"(__as_b32(__values[15])),
+      "r"(__as_b32(__values[16])),
+      "r"(__as_b32(__values[17])),
+      "r"(__as_b32(__values[18])),
+      "r"(__as_b32(__values[19])),
+      "r"(__as_b32(__values[20])),
+      "r"(__as_b32(__values[21])),
+      "r"(__as_b32(__values[22])),
+      "r"(__as_b32(__values[23])),
+      "r"(__as_b32(__values[24])),
+      "r"(__as_b32(__values[25])),
+      "r"(__as_b32(__values[26])),
+      "r"(__as_b32(__values[27])),
+      "r"(__as_b32(__values[28])),
+      "r"(__as_b32(__values[29])),
+      "r"(__as_b32(__values[30])),
+      "r"(__as_b32(__values[31])),
+      "r"(__as_b32(__values[32])),
+      "r"(__as_b32(__values[33])),
+      "r"(__as_b32(__values[34])),
+      "r"(__as_b32(__values[35])),
+      "r"(__as_b32(__values[36])),
+      "r"(__as_b32(__values[37])),
+      "r"(__as_b32(__values[38])),
+      "r"(__as_b32(__values[39])),
+      "r"(__as_b32(__values[40])),
+      "r"(__as_b32(__values[41])),
+      "r"(__as_b32(__values[42])),
+      "r"(__as_b32(__values[43])),
+      "r"(__as_b32(__values[44])),
+      "r"(__as_b32(__values[45])),
+      "r"(__as_b32(__values[46])),
+      "r"(__as_b32(__values[47])),
+      "r"(__as_b32(__values[48])),
+      "r"(__as_b32(__values[49])),
+      "r"(__as_b32(__values[50])),
+      "r"(__as_b32(__values[51])),
+      "r"(__as_b32(__values[52])),
+      "r"(__as_b32(__values[53])),
+      "r"(__as_b32(__values[54])),
+      "r"(__as_b32(__values[55])),
+      "r"(__as_b32(__values[56])),
+      "r"(__as_b32(__values[57])),
+      "r"(__as_b32(__values[58])),
+      "r"(__as_b32(__values[59])),
+      "r"(__as_b32(__values[60])),
+      "r"(__as_b32(__values[61])),
+      "r"(__as_b32(__values[62])),
+      "r"(__as_b32(__values[63]))
+    : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_st_16x256b_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.st.sync.aligned.16x256b.x16.unpack::16b.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_101a
+template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+__device__ static inline void tcgen05_st_16x256b_unpack_16b(
+  uint32_t taddr,
+  const B32 (&values)[64]);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_st_16x256b_unpack_16b_is_not_supported_before_SM_100a_SM_101a__();
+template <typename _B32, _CUDA_VSTD::enable_if_t<sizeof(_B32) == 4, bool> = true>
+_CCCL_DEVICE static inline void tcgen05_st_16x256b_unpack_16b(_CUDA_VSTD::uint32_t __taddr, const _B32 (&__values)[64])
+{
+  static_assert(sizeof(_B32) == 4, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  asm(
+    "tcgen05.st.sync.aligned.16x256b.x16.unpack::16b.b32 [%0], {%1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, "
+    "%13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, "
+    "%35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, "
+    "%57, %58, %59, %60, %61, %62, %63, %64};"
+    :
+    : "r"(__taddr),
+      "r"(__as_b32(__values[0])),
+      "r"(__as_b32(__values[1])),
+      "r"(__as_b32(__values[2])),
+      "r"(__as_b32(__values[3])),
+      "r"(__as_b32(__values[4])),
+      "r"(__as_b32(__values[5])),
+      "r"(__as_b32(__values[6])),
+      "r"(__as_b32(__values[7])),
+      "r"(__as_b32(__values[8])),
+      "r"(__as_b32(__values[9])),
+      "r"(__as_b32(__values[10])),
+      "r"(__as_b32(__values[11])),
+      "r"(__as_b32(__values[12])),
+      "r"(__as_b32(__values[13])),
+      "r"(__as_b32(__values[14])),
+      "r"(__as_b32(__values[15])),
+      "r"(__as_b32(__values[16])),
+      "r"(__as_b32(__values[17])),
+      "r"(__as_b32(__values[18])),
+      "r"(__as_b32(__values[19])),
+      "r"(__as_b32(__values[20])),
+      "r"(__as_b32(__values[21])),
+      "r"(__as_b32(__values[22])),
+      "r"(__as_b32(__values[23])),
+      "r"(__as_b32(__values[24])),
+      "r"(__as_b32(__values[25])),
+      "r"(__as_b32(__values[26])),
+      "r"(__as_b32(__values[27])),
+      "r"(__as_b32(__values[28])),
+      "r"(__as_b32(__values[29])),
+      "r"(__as_b32(__values[30])),
+      "r"(__as_b32(__values[31])),
+      "r"(__as_b32(__values[32])),
+      "r"(__as_b32(__values[33])),
+      "r"(__as_b32(__values[34])),
+      "r"(__as_b32(__values[35])),
+      "r"(__as_b32(__values[36])),
+      "r"(__as_b32(__values[37])),
+      "r"(__as_b32(__values[38])),
+      "r"(__as_b32(__values[39])),
+      "r"(__as_b32(__values[40])),
+      "r"(__as_b32(__values[41])),
+      "r"(__as_b32(__values[42])),
+      "r"(__as_b32(__values[43])),
+      "r"(__as_b32(__values[44])),
+      "r"(__as_b32(__values[45])),
+      "r"(__as_b32(__values[46])),
+      "r"(__as_b32(__values[47])),
+      "r"(__as_b32(__values[48])),
+      "r"(__as_b32(__values[49])),
+      "r"(__as_b32(__values[50])),
+      "r"(__as_b32(__values[51])),
+      "r"(__as_b32(__values[52])),
+      "r"(__as_b32(__values[53])),
+      "r"(__as_b32(__values[54])),
+      "r"(__as_b32(__values[55])),
+      "r"(__as_b32(__values[56])),
+      "r"(__as_b32(__values[57])),
+      "r"(__as_b32(__values[58])),
+      "r"(__as_b32(__values[59])),
+      "r"(__as_b32(__values[60])),
+      "r"(__as_b32(__values[61])),
+      "r"(__as_b32(__values[62])),
+      "r"(__as_b32(__values[63]))
+    : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_st_16x256b_unpack_16b_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.st.sync.aligned.16x256b.x32.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_101a
+template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+__device__ static inline void tcgen05_st_16x256b(
+  uint32_t taddr,
+  const B32 (&values)[128]);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_st_16x256b_is_not_supported_before_SM_100a_SM_101a__();
+template <typename _B32, _CUDA_VSTD::enable_if_t<sizeof(_B32) == 4, bool> = true>
+_CCCL_DEVICE static inline void tcgen05_st_16x256b(_CUDA_VSTD::uint32_t __taddr, const _B32 (&__values)[128])
+{
+  static_assert(sizeof(_B32) == 4, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  asm(
+    "tcgen05.st.sync.aligned.16x256b.x32.b32 [%0], {%1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, "
+    "%16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, "
+    "%38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, "
+    "%60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, "
+    "%82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, "
+    "%104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, "
+    "%123, %124, %125, %126, %127, %128};"
+    :
+    : "r"(__taddr),
+      "r"(__as_b32(__values[0])),
+      "r"(__as_b32(__values[1])),
+      "r"(__as_b32(__values[2])),
+      "r"(__as_b32(__values[3])),
+      "r"(__as_b32(__values[4])),
+      "r"(__as_b32(__values[5])),
+      "r"(__as_b32(__values[6])),
+      "r"(__as_b32(__values[7])),
+      "r"(__as_b32(__values[8])),
+      "r"(__as_b32(__values[9])),
+      "r"(__as_b32(__values[10])),
+      "r"(__as_b32(__values[11])),
+      "r"(__as_b32(__values[12])),
+      "r"(__as_b32(__values[13])),
+      "r"(__as_b32(__values[14])),
+      "r"(__as_b32(__values[15])),
+      "r"(__as_b32(__values[16])),
+      "r"(__as_b32(__values[17])),
+      "r"(__as_b32(__values[18])),
+      "r"(__as_b32(__values[19])),
+      "r"(__as_b32(__values[20])),
+      "r"(__as_b32(__values[21])),
+      "r"(__as_b32(__values[22])),
+      "r"(__as_b32(__values[23])),
+      "r"(__as_b32(__values[24])),
+      "r"(__as_b32(__values[25])),
+      "r"(__as_b32(__values[26])),
+      "r"(__as_b32(__values[27])),
+      "r"(__as_b32(__values[28])),
+      "r"(__as_b32(__values[29])),
+      "r"(__as_b32(__values[30])),
+      "r"(__as_b32(__values[31])),
+      "r"(__as_b32(__values[32])),
+      "r"(__as_b32(__values[33])),
+      "r"(__as_b32(__values[34])),
+      "r"(__as_b32(__values[35])),
+      "r"(__as_b32(__values[36])),
+      "r"(__as_b32(__values[37])),
+      "r"(__as_b32(__values[38])),
+      "r"(__as_b32(__values[39])),
+      "r"(__as_b32(__values[40])),
+      "r"(__as_b32(__values[41])),
+      "r"(__as_b32(__values[42])),
+      "r"(__as_b32(__values[43])),
+      "r"(__as_b32(__values[44])),
+      "r"(__as_b32(__values[45])),
+      "r"(__as_b32(__values[46])),
+      "r"(__as_b32(__values[47])),
+      "r"(__as_b32(__values[48])),
+      "r"(__as_b32(__values[49])),
+      "r"(__as_b32(__values[50])),
+      "r"(__as_b32(__values[51])),
+      "r"(__as_b32(__values[52])),
+      "r"(__as_b32(__values[53])),
+      "r"(__as_b32(__values[54])),
+      "r"(__as_b32(__values[55])),
+      "r"(__as_b32(__values[56])),
+      "r"(__as_b32(__values[57])),
+      "r"(__as_b32(__values[58])),
+      "r"(__as_b32(__values[59])),
+      "r"(__as_b32(__values[60])),
+      "r"(__as_b32(__values[61])),
+      "r"(__as_b32(__values[62])),
+      "r"(__as_b32(__values[63])),
+      "r"(__as_b32(__values[64])),
+      "r"(__as_b32(__values[65])),
+      "r"(__as_b32(__values[66])),
+      "r"(__as_b32(__values[67])),
+      "r"(__as_b32(__values[68])),
+      "r"(__as_b32(__values[69])),
+      "r"(__as_b32(__values[70])),
+      "r"(__as_b32(__values[71])),
+      "r"(__as_b32(__values[72])),
+      "r"(__as_b32(__values[73])),
+      "r"(__as_b32(__values[74])),
+      "r"(__as_b32(__values[75])),
+      "r"(__as_b32(__values[76])),
+      "r"(__as_b32(__values[77])),
+      "r"(__as_b32(__values[78])),
+      "r"(__as_b32(__values[79])),
+      "r"(__as_b32(__values[80])),
+      "r"(__as_b32(__values[81])),
+      "r"(__as_b32(__values[82])),
+      "r"(__as_b32(__values[83])),
+      "r"(__as_b32(__values[84])),
+      "r"(__as_b32(__values[85])),
+      "r"(__as_b32(__values[86])),
+      "r"(__as_b32(__values[87])),
+      "r"(__as_b32(__values[88])),
+      "r"(__as_b32(__values[89])),
+      "r"(__as_b32(__values[90])),
+      "r"(__as_b32(__values[91])),
+      "r"(__as_b32(__values[92])),
+      "r"(__as_b32(__values[93])),
+      "r"(__as_b32(__values[94])),
+      "r"(__as_b32(__values[95])),
+      "r"(__as_b32(__values[96])),
+      "r"(__as_b32(__values[97])),
+      "r"(__as_b32(__values[98])),
+      "r"(__as_b32(__values[99])),
+      "r"(__as_b32(__values[100])),
+      "r"(__as_b32(__values[101])),
+      "r"(__as_b32(__values[102])),
+      "r"(__as_b32(__values[103])),
+      "r"(__as_b32(__values[104])),
+      "r"(__as_b32(__values[105])),
+      "r"(__as_b32(__values[106])),
+      "r"(__as_b32(__values[107])),
+      "r"(__as_b32(__values[108])),
+      "r"(__as_b32(__values[109])),
+      "r"(__as_b32(__values[110])),
+      "r"(__as_b32(__values[111])),
+      "r"(__as_b32(__values[112])),
+      "r"(__as_b32(__values[113])),
+      "r"(__as_b32(__values[114])),
+      "r"(__as_b32(__values[115])),
+      "r"(__as_b32(__values[116])),
+      "r"(__as_b32(__values[117])),
+      "r"(__as_b32(__values[118])),
+      "r"(__as_b32(__values[119])),
+      "r"(__as_b32(__values[120])),
+      "r"(__as_b32(__values[121])),
+      "r"(__as_b32(__values[122])),
+      "r"(__as_b32(__values[123])),
+      "r"(__as_b32(__values[124])),
+      "r"(__as_b32(__values[125])),
+      "r"(__as_b32(__values[126])),
+      "r"(__as_b32(__values[127]))
+    : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_st_16x256b_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.st.sync.aligned.16x256b.x32.unpack::16b.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_101a
+template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+__device__ static inline void tcgen05_st_16x256b_unpack_16b(
+  uint32_t taddr,
+  const B32 (&values)[128]);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_st_16x256b_unpack_16b_is_not_supported_before_SM_100a_SM_101a__();
+template <typename _B32, _CUDA_VSTD::enable_if_t<sizeof(_B32) == 4, bool> = true>
+_CCCL_DEVICE static inline void tcgen05_st_16x256b_unpack_16b(_CUDA_VSTD::uint32_t __taddr, const _B32 (&__values)[128])
+{
+  static_assert(sizeof(_B32) == 4, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  asm(
+    "tcgen05.st.sync.aligned.16x256b.x32.unpack::16b.b32 [%0], {%1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, "
+    "%13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, "
+    "%35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, "
+    "%57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, "
+    "%79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, "
+    "%101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, "
+    "%120, %121, %122, %123, %124, %125, %126, %127, %128};"
+    :
+    : "r"(__taddr),
+      "r"(__as_b32(__values[0])),
+      "r"(__as_b32(__values[1])),
+      "r"(__as_b32(__values[2])),
+      "r"(__as_b32(__values[3])),
+      "r"(__as_b32(__values[4])),
+      "r"(__as_b32(__values[5])),
+      "r"(__as_b32(__values[6])),
+      "r"(__as_b32(__values[7])),
+      "r"(__as_b32(__values[8])),
+      "r"(__as_b32(__values[9])),
+      "r"(__as_b32(__values[10])),
+      "r"(__as_b32(__values[11])),
+      "r"(__as_b32(__values[12])),
+      "r"(__as_b32(__values[13])),
+      "r"(__as_b32(__values[14])),
+      "r"(__as_b32(__values[15])),
+      "r"(__as_b32(__values[16])),
+      "r"(__as_b32(__values[17])),
+      "r"(__as_b32(__values[18])),
+      "r"(__as_b32(__values[19])),
+      "r"(__as_b32(__values[20])),
+      "r"(__as_b32(__values[21])),
+      "r"(__as_b32(__values[22])),
+      "r"(__as_b32(__values[23])),
+      "r"(__as_b32(__values[24])),
+      "r"(__as_b32(__values[25])),
+      "r"(__as_b32(__values[26])),
+      "r"(__as_b32(__values[27])),
+      "r"(__as_b32(__values[28])),
+      "r"(__as_b32(__values[29])),
+      "r"(__as_b32(__values[30])),
+      "r"(__as_b32(__values[31])),
+      "r"(__as_b32(__values[32])),
+      "r"(__as_b32(__values[33])),
+      "r"(__as_b32(__values[34])),
+      "r"(__as_b32(__values[35])),
+      "r"(__as_b32(__values[36])),
+      "r"(__as_b32(__values[37])),
+      "r"(__as_b32(__values[38])),
+      "r"(__as_b32(__values[39])),
+      "r"(__as_b32(__values[40])),
+      "r"(__as_b32(__values[41])),
+      "r"(__as_b32(__values[42])),
+      "r"(__as_b32(__values[43])),
+      "r"(__as_b32(__values[44])),
+      "r"(__as_b32(__values[45])),
+      "r"(__as_b32(__values[46])),
+      "r"(__as_b32(__values[47])),
+      "r"(__as_b32(__values[48])),
+      "r"(__as_b32(__values[49])),
+      "r"(__as_b32(__values[50])),
+      "r"(__as_b32(__values[51])),
+      "r"(__as_b32(__values[52])),
+      "r"(__as_b32(__values[53])),
+      "r"(__as_b32(__values[54])),
+      "r"(__as_b32(__values[55])),
+      "r"(__as_b32(__values[56])),
+      "r"(__as_b32(__values[57])),
+      "r"(__as_b32(__values[58])),
+      "r"(__as_b32(__values[59])),
+      "r"(__as_b32(__values[60])),
+      "r"(__as_b32(__values[61])),
+      "r"(__as_b32(__values[62])),
+      "r"(__as_b32(__values[63])),
+      "r"(__as_b32(__values[64])),
+      "r"(__as_b32(__values[65])),
+      "r"(__as_b32(__values[66])),
+      "r"(__as_b32(__values[67])),
+      "r"(__as_b32(__values[68])),
+      "r"(__as_b32(__values[69])),
+      "r"(__as_b32(__values[70])),
+      "r"(__as_b32(__values[71])),
+      "r"(__as_b32(__values[72])),
+      "r"(__as_b32(__values[73])),
+      "r"(__as_b32(__values[74])),
+      "r"(__as_b32(__values[75])),
+      "r"(__as_b32(__values[76])),
+      "r"(__as_b32(__values[77])),
+      "r"(__as_b32(__values[78])),
+      "r"(__as_b32(__values[79])),
+      "r"(__as_b32(__values[80])),
+      "r"(__as_b32(__values[81])),
+      "r"(__as_b32(__values[82])),
+      "r"(__as_b32(__values[83])),
+      "r"(__as_b32(__values[84])),
+      "r"(__as_b32(__values[85])),
+      "r"(__as_b32(__values[86])),
+      "r"(__as_b32(__values[87])),
+      "r"(__as_b32(__values[88])),
+      "r"(__as_b32(__values[89])),
+      "r"(__as_b32(__values[90])),
+      "r"(__as_b32(__values[91])),
+      "r"(__as_b32(__values[92])),
+      "r"(__as_b32(__values[93])),
+      "r"(__as_b32(__values[94])),
+      "r"(__as_b32(__values[95])),
+      "r"(__as_b32(__values[96])),
+      "r"(__as_b32(__values[97])),
+      "r"(__as_b32(__values[98])),
+      "r"(__as_b32(__values[99])),
+      "r"(__as_b32(__values[100])),
+      "r"(__as_b32(__values[101])),
+      "r"(__as_b32(__values[102])),
+      "r"(__as_b32(__values[103])),
+      "r"(__as_b32(__values[104])),
+      "r"(__as_b32(__values[105])),
+      "r"(__as_b32(__values[106])),
+      "r"(__as_b32(__values[107])),
+      "r"(__as_b32(__values[108])),
+      "r"(__as_b32(__values[109])),
+      "r"(__as_b32(__values[110])),
+      "r"(__as_b32(__values[111])),
+      "r"(__as_b32(__values[112])),
+      "r"(__as_b32(__values[113])),
+      "r"(__as_b32(__values[114])),
+      "r"(__as_b32(__values[115])),
+      "r"(__as_b32(__values[116])),
+      "r"(__as_b32(__values[117])),
+      "r"(__as_b32(__values[118])),
+      "r"(__as_b32(__values[119])),
+      "r"(__as_b32(__values[120])),
+      "r"(__as_b32(__values[121])),
+      "r"(__as_b32(__values[122])),
+      "r"(__as_b32(__values[123])),
+      "r"(__as_b32(__values[124])),
+      "r"(__as_b32(__values[125])),
+      "r"(__as_b32(__values[126])),
+      "r"(__as_b32(__values[127]))
+    : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_st_16x256b_unpack_16b_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.st.sync.aligned.32x32b.x1.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_101a
+template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+__device__ static inline void tcgen05_st_32x32b(
+  uint32_t taddr,
+  const B32 (&values)[1]);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_st_32x32b_is_not_supported_before_SM_100a_SM_101a__();
+template <typename _B32, _CUDA_VSTD::enable_if_t<sizeof(_B32) == 4, bool> = true>
+_CCCL_DEVICE static inline void tcgen05_st_32x32b(_CUDA_VSTD::uint32_t __taddr, const _B32 (&__values)[1])
+{
+  static_assert(sizeof(_B32) == 4, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  asm("tcgen05.st.sync.aligned.32x32b.x1.b32 [%0], {%1};" : : "r"(__taddr), "r"(__as_b32(__values[0])) : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_st_32x32b_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.st.sync.aligned.32x32b.x1.unpack::16b.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_101a
+template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+__device__ static inline void tcgen05_st_32x32b_unpack_16b(
+  uint32_t taddr,
+  const B32 (&values)[1]);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_st_32x32b_unpack_16b_is_not_supported_before_SM_100a_SM_101a__();
+template <typename _B32, _CUDA_VSTD::enable_if_t<sizeof(_B32) == 4, bool> = true>
+_CCCL_DEVICE static inline void tcgen05_st_32x32b_unpack_16b(_CUDA_VSTD::uint32_t __taddr, const _B32 (&__values)[1])
+{
+  static_assert(sizeof(_B32) == 4, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  asm("tcgen05.st.sync.aligned.32x32b.x1.unpack::16b.b32 [%0], {%1};"
+      :
+      : "r"(__taddr), "r"(__as_b32(__values[0]))
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_st_32x32b_unpack_16b_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.st.sync.aligned.32x32b.x2.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_101a
+template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+__device__ static inline void tcgen05_st_32x32b(
+  uint32_t taddr,
+  const B32 (&values)[2]);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_st_32x32b_is_not_supported_before_SM_100a_SM_101a__();
+template <typename _B32, _CUDA_VSTD::enable_if_t<sizeof(_B32) == 4, bool> = true>
+_CCCL_DEVICE static inline void tcgen05_st_32x32b(_CUDA_VSTD::uint32_t __taddr, const _B32 (&__values)[2])
+{
+  static_assert(sizeof(_B32) == 4, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  asm("tcgen05.st.sync.aligned.32x32b.x2.b32 [%0], {%1, %2};"
+      :
+      : "r"(__taddr), "r"(__as_b32(__values[0])), "r"(__as_b32(__values[1]))
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_st_32x32b_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.st.sync.aligned.32x32b.x2.unpack::16b.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_101a
+template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+__device__ static inline void tcgen05_st_32x32b_unpack_16b(
+  uint32_t taddr,
+  const B32 (&values)[2]);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_st_32x32b_unpack_16b_is_not_supported_before_SM_100a_SM_101a__();
+template <typename _B32, _CUDA_VSTD::enable_if_t<sizeof(_B32) == 4, bool> = true>
+_CCCL_DEVICE static inline void tcgen05_st_32x32b_unpack_16b(_CUDA_VSTD::uint32_t __taddr, const _B32 (&__values)[2])
+{
+  static_assert(sizeof(_B32) == 4, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  asm("tcgen05.st.sync.aligned.32x32b.x2.unpack::16b.b32 [%0], {%1, %2};"
+      :
+      : "r"(__taddr), "r"(__as_b32(__values[0])), "r"(__as_b32(__values[1]))
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_st_32x32b_unpack_16b_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.st.sync.aligned.32x32b.x4.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_101a
+template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+__device__ static inline void tcgen05_st_32x32b(
+  uint32_t taddr,
+  const B32 (&values)[4]);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_st_32x32b_is_not_supported_before_SM_100a_SM_101a__();
+template <typename _B32, _CUDA_VSTD::enable_if_t<sizeof(_B32) == 4, bool> = true>
+_CCCL_DEVICE static inline void tcgen05_st_32x32b(_CUDA_VSTD::uint32_t __taddr, const _B32 (&__values)[4])
+{
+  static_assert(sizeof(_B32) == 4, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  asm("tcgen05.st.sync.aligned.32x32b.x4.b32 [%0], {%1, %2, %3, %4};"
+      :
+      : "r"(__taddr),
+        "r"(__as_b32(__values[0])),
+        "r"(__as_b32(__values[1])),
+        "r"(__as_b32(__values[2])),
+        "r"(__as_b32(__values[3]))
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_st_32x32b_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.st.sync.aligned.32x32b.x4.unpack::16b.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_101a
+template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+__device__ static inline void tcgen05_st_32x32b_unpack_16b(
+  uint32_t taddr,
+  const B32 (&values)[4]);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_st_32x32b_unpack_16b_is_not_supported_before_SM_100a_SM_101a__();
+template <typename _B32, _CUDA_VSTD::enable_if_t<sizeof(_B32) == 4, bool> = true>
+_CCCL_DEVICE static inline void tcgen05_st_32x32b_unpack_16b(_CUDA_VSTD::uint32_t __taddr, const _B32 (&__values)[4])
+{
+  static_assert(sizeof(_B32) == 4, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  asm("tcgen05.st.sync.aligned.32x32b.x4.unpack::16b.b32 [%0], {%1, %2, %3, %4};"
+      :
+      : "r"(__taddr),
+        "r"(__as_b32(__values[0])),
+        "r"(__as_b32(__values[1])),
+        "r"(__as_b32(__values[2])),
+        "r"(__as_b32(__values[3]))
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_st_32x32b_unpack_16b_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.st.sync.aligned.32x32b.x8.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_101a
+template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+__device__ static inline void tcgen05_st_32x32b(
+  uint32_t taddr,
+  const B32 (&values)[8]);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_st_32x32b_is_not_supported_before_SM_100a_SM_101a__();
+template <typename _B32, _CUDA_VSTD::enable_if_t<sizeof(_B32) == 4, bool> = true>
+_CCCL_DEVICE static inline void tcgen05_st_32x32b(_CUDA_VSTD::uint32_t __taddr, const _B32 (&__values)[8])
+{
+  static_assert(sizeof(_B32) == 4, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  asm("tcgen05.st.sync.aligned.32x32b.x8.b32 [%0], {%1, %2, %3, %4, %5, %6, %7, %8};"
+      :
+      : "r"(__taddr),
+        "r"(__as_b32(__values[0])),
+        "r"(__as_b32(__values[1])),
+        "r"(__as_b32(__values[2])),
+        "r"(__as_b32(__values[3])),
+        "r"(__as_b32(__values[4])),
+        "r"(__as_b32(__values[5])),
+        "r"(__as_b32(__values[6])),
+        "r"(__as_b32(__values[7]))
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_st_32x32b_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.st.sync.aligned.32x32b.x8.unpack::16b.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_101a
+template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+__device__ static inline void tcgen05_st_32x32b_unpack_16b(
+  uint32_t taddr,
+  const B32 (&values)[8]);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_st_32x32b_unpack_16b_is_not_supported_before_SM_100a_SM_101a__();
+template <typename _B32, _CUDA_VSTD::enable_if_t<sizeof(_B32) == 4, bool> = true>
+_CCCL_DEVICE static inline void tcgen05_st_32x32b_unpack_16b(_CUDA_VSTD::uint32_t __taddr, const _B32 (&__values)[8])
+{
+  static_assert(sizeof(_B32) == 4, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  asm("tcgen05.st.sync.aligned.32x32b.x8.unpack::16b.b32 [%0], {%1, %2, %3, %4, %5, %6, %7, %8};"
+      :
+      : "r"(__taddr),
+        "r"(__as_b32(__values[0])),
+        "r"(__as_b32(__values[1])),
+        "r"(__as_b32(__values[2])),
+        "r"(__as_b32(__values[3])),
+        "r"(__as_b32(__values[4])),
+        "r"(__as_b32(__values[5])),
+        "r"(__as_b32(__values[6])),
+        "r"(__as_b32(__values[7]))
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_st_32x32b_unpack_16b_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.st.sync.aligned.32x32b.x16.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_101a
+template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+__device__ static inline void tcgen05_st_32x32b(
+  uint32_t taddr,
+  const B32 (&values)[16]);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_st_32x32b_is_not_supported_before_SM_100a_SM_101a__();
+template <typename _B32, _CUDA_VSTD::enable_if_t<sizeof(_B32) == 4, bool> = true>
+_CCCL_DEVICE static inline void tcgen05_st_32x32b(_CUDA_VSTD::uint32_t __taddr, const _B32 (&__values)[16])
+{
+  static_assert(sizeof(_B32) == 4, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  asm("tcgen05.st.sync.aligned.32x32b.x16.b32 [%0], {%1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, "
+      "%16};"
+      :
+      : "r"(__taddr),
+        "r"(__as_b32(__values[0])),
+        "r"(__as_b32(__values[1])),
+        "r"(__as_b32(__values[2])),
+        "r"(__as_b32(__values[3])),
+        "r"(__as_b32(__values[4])),
+        "r"(__as_b32(__values[5])),
+        "r"(__as_b32(__values[6])),
+        "r"(__as_b32(__values[7])),
+        "r"(__as_b32(__values[8])),
+        "r"(__as_b32(__values[9])),
+        "r"(__as_b32(__values[10])),
+        "r"(__as_b32(__values[11])),
+        "r"(__as_b32(__values[12])),
+        "r"(__as_b32(__values[13])),
+        "r"(__as_b32(__values[14])),
+        "r"(__as_b32(__values[15]))
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_st_32x32b_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.st.sync.aligned.32x32b.x16.unpack::16b.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_101a
+template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+__device__ static inline void tcgen05_st_32x32b_unpack_16b(
+  uint32_t taddr,
+  const B32 (&values)[16]);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_st_32x32b_unpack_16b_is_not_supported_before_SM_100a_SM_101a__();
+template <typename _B32, _CUDA_VSTD::enable_if_t<sizeof(_B32) == 4, bool> = true>
+_CCCL_DEVICE static inline void tcgen05_st_32x32b_unpack_16b(_CUDA_VSTD::uint32_t __taddr, const _B32 (&__values)[16])
+{
+  static_assert(sizeof(_B32) == 4, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  asm("tcgen05.st.sync.aligned.32x32b.x16.unpack::16b.b32 [%0], {%1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, "
+      "%13, %14, %15, %16};"
+      :
+      : "r"(__taddr),
+        "r"(__as_b32(__values[0])),
+        "r"(__as_b32(__values[1])),
+        "r"(__as_b32(__values[2])),
+        "r"(__as_b32(__values[3])),
+        "r"(__as_b32(__values[4])),
+        "r"(__as_b32(__values[5])),
+        "r"(__as_b32(__values[6])),
+        "r"(__as_b32(__values[7])),
+        "r"(__as_b32(__values[8])),
+        "r"(__as_b32(__values[9])),
+        "r"(__as_b32(__values[10])),
+        "r"(__as_b32(__values[11])),
+        "r"(__as_b32(__values[12])),
+        "r"(__as_b32(__values[13])),
+        "r"(__as_b32(__values[14])),
+        "r"(__as_b32(__values[15]))
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_st_32x32b_unpack_16b_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.st.sync.aligned.32x32b.x32.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_101a
+template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+__device__ static inline void tcgen05_st_32x32b(
+  uint32_t taddr,
+  const B32 (&values)[32]);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_st_32x32b_is_not_supported_before_SM_100a_SM_101a__();
+template <typename _B32, _CUDA_VSTD::enable_if_t<sizeof(_B32) == 4, bool> = true>
+_CCCL_DEVICE static inline void tcgen05_st_32x32b(_CUDA_VSTD::uint32_t __taddr, const _B32 (&__values)[32])
+{
+  static_assert(sizeof(_B32) == 4, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  asm(
+    "tcgen05.st.sync.aligned.32x32b.x32.b32 [%0], {%1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, "
+    "%16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32};"
+    :
+    : "r"(__taddr),
+      "r"(__as_b32(__values[0])),
+      "r"(__as_b32(__values[1])),
+      "r"(__as_b32(__values[2])),
+      "r"(__as_b32(__values[3])),
+      "r"(__as_b32(__values[4])),
+      "r"(__as_b32(__values[5])),
+      "r"(__as_b32(__values[6])),
+      "r"(__as_b32(__values[7])),
+      "r"(__as_b32(__values[8])),
+      "r"(__as_b32(__values[9])),
+      "r"(__as_b32(__values[10])),
+      "r"(__as_b32(__values[11])),
+      "r"(__as_b32(__values[12])),
+      "r"(__as_b32(__values[13])),
+      "r"(__as_b32(__values[14])),
+      "r"(__as_b32(__values[15])),
+      "r"(__as_b32(__values[16])),
+      "r"(__as_b32(__values[17])),
+      "r"(__as_b32(__values[18])),
+      "r"(__as_b32(__values[19])),
+      "r"(__as_b32(__values[20])),
+      "r"(__as_b32(__values[21])),
+      "r"(__as_b32(__values[22])),
+      "r"(__as_b32(__values[23])),
+      "r"(__as_b32(__values[24])),
+      "r"(__as_b32(__values[25])),
+      "r"(__as_b32(__values[26])),
+      "r"(__as_b32(__values[27])),
+      "r"(__as_b32(__values[28])),
+      "r"(__as_b32(__values[29])),
+      "r"(__as_b32(__values[30])),
+      "r"(__as_b32(__values[31]))
+    : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_st_32x32b_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.st.sync.aligned.32x32b.x32.unpack::16b.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_101a
+template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+__device__ static inline void tcgen05_st_32x32b_unpack_16b(
+  uint32_t taddr,
+  const B32 (&values)[32]);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_st_32x32b_unpack_16b_is_not_supported_before_SM_100a_SM_101a__();
+template <typename _B32, _CUDA_VSTD::enable_if_t<sizeof(_B32) == 4, bool> = true>
+_CCCL_DEVICE static inline void tcgen05_st_32x32b_unpack_16b(_CUDA_VSTD::uint32_t __taddr, const _B32 (&__values)[32])
+{
+  static_assert(sizeof(_B32) == 4, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  asm(
+    "tcgen05.st.sync.aligned.32x32b.x32.unpack::16b.b32 [%0], {%1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, "
+    "%14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32};"
+    :
+    : "r"(__taddr),
+      "r"(__as_b32(__values[0])),
+      "r"(__as_b32(__values[1])),
+      "r"(__as_b32(__values[2])),
+      "r"(__as_b32(__values[3])),
+      "r"(__as_b32(__values[4])),
+      "r"(__as_b32(__values[5])),
+      "r"(__as_b32(__values[6])),
+      "r"(__as_b32(__values[7])),
+      "r"(__as_b32(__values[8])),
+      "r"(__as_b32(__values[9])),
+      "r"(__as_b32(__values[10])),
+      "r"(__as_b32(__values[11])),
+      "r"(__as_b32(__values[12])),
+      "r"(__as_b32(__values[13])),
+      "r"(__as_b32(__values[14])),
+      "r"(__as_b32(__values[15])),
+      "r"(__as_b32(__values[16])),
+      "r"(__as_b32(__values[17])),
+      "r"(__as_b32(__values[18])),
+      "r"(__as_b32(__values[19])),
+      "r"(__as_b32(__values[20])),
+      "r"(__as_b32(__values[21])),
+      "r"(__as_b32(__values[22])),
+      "r"(__as_b32(__values[23])),
+      "r"(__as_b32(__values[24])),
+      "r"(__as_b32(__values[25])),
+      "r"(__as_b32(__values[26])),
+      "r"(__as_b32(__values[27])),
+      "r"(__as_b32(__values[28])),
+      "r"(__as_b32(__values[29])),
+      "r"(__as_b32(__values[30])),
+      "r"(__as_b32(__values[31]))
+    : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_st_32x32b_unpack_16b_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.st.sync.aligned.32x32b.x64.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_101a
+template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+__device__ static inline void tcgen05_st_32x32b(
+  uint32_t taddr,
+  const B32 (&values)[64]);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_st_32x32b_is_not_supported_before_SM_100a_SM_101a__();
+template <typename _B32, _CUDA_VSTD::enable_if_t<sizeof(_B32) == 4, bool> = true>
+_CCCL_DEVICE static inline void tcgen05_st_32x32b(_CUDA_VSTD::uint32_t __taddr, const _B32 (&__values)[64])
+{
+  static_assert(sizeof(_B32) == 4, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  asm(
+    "tcgen05.st.sync.aligned.32x32b.x64.b32 [%0], {%1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, "
+    "%16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, "
+    "%38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, "
+    "%60, %61, %62, %63, %64};"
+    :
+    : "r"(__taddr),
+      "r"(__as_b32(__values[0])),
+      "r"(__as_b32(__values[1])),
+      "r"(__as_b32(__values[2])),
+      "r"(__as_b32(__values[3])),
+      "r"(__as_b32(__values[4])),
+      "r"(__as_b32(__values[5])),
+      "r"(__as_b32(__values[6])),
+      "r"(__as_b32(__values[7])),
+      "r"(__as_b32(__values[8])),
+      "r"(__as_b32(__values[9])),
+      "r"(__as_b32(__values[10])),
+      "r"(__as_b32(__values[11])),
+      "r"(__as_b32(__values[12])),
+      "r"(__as_b32(__values[13])),
+      "r"(__as_b32(__values[14])),
+      "r"(__as_b32(__values[15])),
+      "r"(__as_b32(__values[16])),
+      "r"(__as_b32(__values[17])),
+      "r"(__as_b32(__values[18])),
+      "r"(__as_b32(__values[19])),
+      "r"(__as_b32(__values[20])),
+      "r"(__as_b32(__values[21])),
+      "r"(__as_b32(__values[22])),
+      "r"(__as_b32(__values[23])),
+      "r"(__as_b32(__values[24])),
+      "r"(__as_b32(__values[25])),
+      "r"(__as_b32(__values[26])),
+      "r"(__as_b32(__values[27])),
+      "r"(__as_b32(__values[28])),
+      "r"(__as_b32(__values[29])),
+      "r"(__as_b32(__values[30])),
+      "r"(__as_b32(__values[31])),
+      "r"(__as_b32(__values[32])),
+      "r"(__as_b32(__values[33])),
+      "r"(__as_b32(__values[34])),
+      "r"(__as_b32(__values[35])),
+      "r"(__as_b32(__values[36])),
+      "r"(__as_b32(__values[37])),
+      "r"(__as_b32(__values[38])),
+      "r"(__as_b32(__values[39])),
+      "r"(__as_b32(__values[40])),
+      "r"(__as_b32(__values[41])),
+      "r"(__as_b32(__values[42])),
+      "r"(__as_b32(__values[43])),
+      "r"(__as_b32(__values[44])),
+      "r"(__as_b32(__values[45])),
+      "r"(__as_b32(__values[46])),
+      "r"(__as_b32(__values[47])),
+      "r"(__as_b32(__values[48])),
+      "r"(__as_b32(__values[49])),
+      "r"(__as_b32(__values[50])),
+      "r"(__as_b32(__values[51])),
+      "r"(__as_b32(__values[52])),
+      "r"(__as_b32(__values[53])),
+      "r"(__as_b32(__values[54])),
+      "r"(__as_b32(__values[55])),
+      "r"(__as_b32(__values[56])),
+      "r"(__as_b32(__values[57])),
+      "r"(__as_b32(__values[58])),
+      "r"(__as_b32(__values[59])),
+      "r"(__as_b32(__values[60])),
+      "r"(__as_b32(__values[61])),
+      "r"(__as_b32(__values[62])),
+      "r"(__as_b32(__values[63]))
+    : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_st_32x32b_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.st.sync.aligned.32x32b.x64.unpack::16b.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_101a
+template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+__device__ static inline void tcgen05_st_32x32b_unpack_16b(
+  uint32_t taddr,
+  const B32 (&values)[64]);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_st_32x32b_unpack_16b_is_not_supported_before_SM_100a_SM_101a__();
+template <typename _B32, _CUDA_VSTD::enable_if_t<sizeof(_B32) == 4, bool> = true>
+_CCCL_DEVICE static inline void tcgen05_st_32x32b_unpack_16b(_CUDA_VSTD::uint32_t __taddr, const _B32 (&__values)[64])
+{
+  static_assert(sizeof(_B32) == 4, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  asm(
+    "tcgen05.st.sync.aligned.32x32b.x64.unpack::16b.b32 [%0], {%1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, "
+    "%14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, "
+    "%36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, "
+    "%58, %59, %60, %61, %62, %63, %64};"
+    :
+    : "r"(__taddr),
+      "r"(__as_b32(__values[0])),
+      "r"(__as_b32(__values[1])),
+      "r"(__as_b32(__values[2])),
+      "r"(__as_b32(__values[3])),
+      "r"(__as_b32(__values[4])),
+      "r"(__as_b32(__values[5])),
+      "r"(__as_b32(__values[6])),
+      "r"(__as_b32(__values[7])),
+      "r"(__as_b32(__values[8])),
+      "r"(__as_b32(__values[9])),
+      "r"(__as_b32(__values[10])),
+      "r"(__as_b32(__values[11])),
+      "r"(__as_b32(__values[12])),
+      "r"(__as_b32(__values[13])),
+      "r"(__as_b32(__values[14])),
+      "r"(__as_b32(__values[15])),
+      "r"(__as_b32(__values[16])),
+      "r"(__as_b32(__values[17])),
+      "r"(__as_b32(__values[18])),
+      "r"(__as_b32(__values[19])),
+      "r"(__as_b32(__values[20])),
+      "r"(__as_b32(__values[21])),
+      "r"(__as_b32(__values[22])),
+      "r"(__as_b32(__values[23])),
+      "r"(__as_b32(__values[24])),
+      "r"(__as_b32(__values[25])),
+      "r"(__as_b32(__values[26])),
+      "r"(__as_b32(__values[27])),
+      "r"(__as_b32(__values[28])),
+      "r"(__as_b32(__values[29])),
+      "r"(__as_b32(__values[30])),
+      "r"(__as_b32(__values[31])),
+      "r"(__as_b32(__values[32])),
+      "r"(__as_b32(__values[33])),
+      "r"(__as_b32(__values[34])),
+      "r"(__as_b32(__values[35])),
+      "r"(__as_b32(__values[36])),
+      "r"(__as_b32(__values[37])),
+      "r"(__as_b32(__values[38])),
+      "r"(__as_b32(__values[39])),
+      "r"(__as_b32(__values[40])),
+      "r"(__as_b32(__values[41])),
+      "r"(__as_b32(__values[42])),
+      "r"(__as_b32(__values[43])),
+      "r"(__as_b32(__values[44])),
+      "r"(__as_b32(__values[45])),
+      "r"(__as_b32(__values[46])),
+      "r"(__as_b32(__values[47])),
+      "r"(__as_b32(__values[48])),
+      "r"(__as_b32(__values[49])),
+      "r"(__as_b32(__values[50])),
+      "r"(__as_b32(__values[51])),
+      "r"(__as_b32(__values[52])),
+      "r"(__as_b32(__values[53])),
+      "r"(__as_b32(__values[54])),
+      "r"(__as_b32(__values[55])),
+      "r"(__as_b32(__values[56])),
+      "r"(__as_b32(__values[57])),
+      "r"(__as_b32(__values[58])),
+      "r"(__as_b32(__values[59])),
+      "r"(__as_b32(__values[60])),
+      "r"(__as_b32(__values[61])),
+      "r"(__as_b32(__values[62])),
+      "r"(__as_b32(__values[63]))
+    : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_st_32x32b_unpack_16b_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.st.sync.aligned.32x32b.x128.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_101a
+template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+__device__ static inline void tcgen05_st_32x32b(
+  uint32_t taddr,
+  const B32 (&values)[128]);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_st_32x32b_is_not_supported_before_SM_100a_SM_101a__();
+template <typename _B32, _CUDA_VSTD::enable_if_t<sizeof(_B32) == 4, bool> = true>
+_CCCL_DEVICE static inline void tcgen05_st_32x32b(_CUDA_VSTD::uint32_t __taddr, const _B32 (&__values)[128])
+{
+  static_assert(sizeof(_B32) == 4, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  asm(
+    "tcgen05.st.sync.aligned.32x32b.x128.b32 [%0], {%1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, "
+    "%16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, "
+    "%38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, "
+    "%60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, "
+    "%82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, "
+    "%104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, "
+    "%123, %124, %125, %126, %127, %128};"
+    :
+    : "r"(__taddr),
+      "r"(__as_b32(__values[0])),
+      "r"(__as_b32(__values[1])),
+      "r"(__as_b32(__values[2])),
+      "r"(__as_b32(__values[3])),
+      "r"(__as_b32(__values[4])),
+      "r"(__as_b32(__values[5])),
+      "r"(__as_b32(__values[6])),
+      "r"(__as_b32(__values[7])),
+      "r"(__as_b32(__values[8])),
+      "r"(__as_b32(__values[9])),
+      "r"(__as_b32(__values[10])),
+      "r"(__as_b32(__values[11])),
+      "r"(__as_b32(__values[12])),
+      "r"(__as_b32(__values[13])),
+      "r"(__as_b32(__values[14])),
+      "r"(__as_b32(__values[15])),
+      "r"(__as_b32(__values[16])),
+      "r"(__as_b32(__values[17])),
+      "r"(__as_b32(__values[18])),
+      "r"(__as_b32(__values[19])),
+      "r"(__as_b32(__values[20])),
+      "r"(__as_b32(__values[21])),
+      "r"(__as_b32(__values[22])),
+      "r"(__as_b32(__values[23])),
+      "r"(__as_b32(__values[24])),
+      "r"(__as_b32(__values[25])),
+      "r"(__as_b32(__values[26])),
+      "r"(__as_b32(__values[27])),
+      "r"(__as_b32(__values[28])),
+      "r"(__as_b32(__values[29])),
+      "r"(__as_b32(__values[30])),
+      "r"(__as_b32(__values[31])),
+      "r"(__as_b32(__values[32])),
+      "r"(__as_b32(__values[33])),
+      "r"(__as_b32(__values[34])),
+      "r"(__as_b32(__values[35])),
+      "r"(__as_b32(__values[36])),
+      "r"(__as_b32(__values[37])),
+      "r"(__as_b32(__values[38])),
+      "r"(__as_b32(__values[39])),
+      "r"(__as_b32(__values[40])),
+      "r"(__as_b32(__values[41])),
+      "r"(__as_b32(__values[42])),
+      "r"(__as_b32(__values[43])),
+      "r"(__as_b32(__values[44])),
+      "r"(__as_b32(__values[45])),
+      "r"(__as_b32(__values[46])),
+      "r"(__as_b32(__values[47])),
+      "r"(__as_b32(__values[48])),
+      "r"(__as_b32(__values[49])),
+      "r"(__as_b32(__values[50])),
+      "r"(__as_b32(__values[51])),
+      "r"(__as_b32(__values[52])),
+      "r"(__as_b32(__values[53])),
+      "r"(__as_b32(__values[54])),
+      "r"(__as_b32(__values[55])),
+      "r"(__as_b32(__values[56])),
+      "r"(__as_b32(__values[57])),
+      "r"(__as_b32(__values[58])),
+      "r"(__as_b32(__values[59])),
+      "r"(__as_b32(__values[60])),
+      "r"(__as_b32(__values[61])),
+      "r"(__as_b32(__values[62])),
+      "r"(__as_b32(__values[63])),
+      "r"(__as_b32(__values[64])),
+      "r"(__as_b32(__values[65])),
+      "r"(__as_b32(__values[66])),
+      "r"(__as_b32(__values[67])),
+      "r"(__as_b32(__values[68])),
+      "r"(__as_b32(__values[69])),
+      "r"(__as_b32(__values[70])),
+      "r"(__as_b32(__values[71])),
+      "r"(__as_b32(__values[72])),
+      "r"(__as_b32(__values[73])),
+      "r"(__as_b32(__values[74])),
+      "r"(__as_b32(__values[75])),
+      "r"(__as_b32(__values[76])),
+      "r"(__as_b32(__values[77])),
+      "r"(__as_b32(__values[78])),
+      "r"(__as_b32(__values[79])),
+      "r"(__as_b32(__values[80])),
+      "r"(__as_b32(__values[81])),
+      "r"(__as_b32(__values[82])),
+      "r"(__as_b32(__values[83])),
+      "r"(__as_b32(__values[84])),
+      "r"(__as_b32(__values[85])),
+      "r"(__as_b32(__values[86])),
+      "r"(__as_b32(__values[87])),
+      "r"(__as_b32(__values[88])),
+      "r"(__as_b32(__values[89])),
+      "r"(__as_b32(__values[90])),
+      "r"(__as_b32(__values[91])),
+      "r"(__as_b32(__values[92])),
+      "r"(__as_b32(__values[93])),
+      "r"(__as_b32(__values[94])),
+      "r"(__as_b32(__values[95])),
+      "r"(__as_b32(__values[96])),
+      "r"(__as_b32(__values[97])),
+      "r"(__as_b32(__values[98])),
+      "r"(__as_b32(__values[99])),
+      "r"(__as_b32(__values[100])),
+      "r"(__as_b32(__values[101])),
+      "r"(__as_b32(__values[102])),
+      "r"(__as_b32(__values[103])),
+      "r"(__as_b32(__values[104])),
+      "r"(__as_b32(__values[105])),
+      "r"(__as_b32(__values[106])),
+      "r"(__as_b32(__values[107])),
+      "r"(__as_b32(__values[108])),
+      "r"(__as_b32(__values[109])),
+      "r"(__as_b32(__values[110])),
+      "r"(__as_b32(__values[111])),
+      "r"(__as_b32(__values[112])),
+      "r"(__as_b32(__values[113])),
+      "r"(__as_b32(__values[114])),
+      "r"(__as_b32(__values[115])),
+      "r"(__as_b32(__values[116])),
+      "r"(__as_b32(__values[117])),
+      "r"(__as_b32(__values[118])),
+      "r"(__as_b32(__values[119])),
+      "r"(__as_b32(__values[120])),
+      "r"(__as_b32(__values[121])),
+      "r"(__as_b32(__values[122])),
+      "r"(__as_b32(__values[123])),
+      "r"(__as_b32(__values[124])),
+      "r"(__as_b32(__values[125])),
+      "r"(__as_b32(__values[126])),
+      "r"(__as_b32(__values[127]))
+    : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_st_32x32b_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.st.sync.aligned.32x32b.x128.unpack::16b.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_101a
+template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+__device__ static inline void tcgen05_st_32x32b_unpack_16b(
+  uint32_t taddr,
+  const B32 (&values)[128]);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_st_32x32b_unpack_16b_is_not_supported_before_SM_100a_SM_101a__();
+template <typename _B32, _CUDA_VSTD::enable_if_t<sizeof(_B32) == 4, bool> = true>
+_CCCL_DEVICE static inline void tcgen05_st_32x32b_unpack_16b(_CUDA_VSTD::uint32_t __taddr, const _B32 (&__values)[128])
+{
+  static_assert(sizeof(_B32) == 4, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  asm(
+    "tcgen05.st.sync.aligned.32x32b.x128.unpack::16b.b32 [%0], {%1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, "
+    "%13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, "
+    "%35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, "
+    "%57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, "
+    "%79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, "
+    "%101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, "
+    "%120, %121, %122, %123, %124, %125, %126, %127, %128};"
+    :
+    : "r"(__taddr),
+      "r"(__as_b32(__values[0])),
+      "r"(__as_b32(__values[1])),
+      "r"(__as_b32(__values[2])),
+      "r"(__as_b32(__values[3])),
+      "r"(__as_b32(__values[4])),
+      "r"(__as_b32(__values[5])),
+      "r"(__as_b32(__values[6])),
+      "r"(__as_b32(__values[7])),
+      "r"(__as_b32(__values[8])),
+      "r"(__as_b32(__values[9])),
+      "r"(__as_b32(__values[10])),
+      "r"(__as_b32(__values[11])),
+      "r"(__as_b32(__values[12])),
+      "r"(__as_b32(__values[13])),
+      "r"(__as_b32(__values[14])),
+      "r"(__as_b32(__values[15])),
+      "r"(__as_b32(__values[16])),
+      "r"(__as_b32(__values[17])),
+      "r"(__as_b32(__values[18])),
+      "r"(__as_b32(__values[19])),
+      "r"(__as_b32(__values[20])),
+      "r"(__as_b32(__values[21])),
+      "r"(__as_b32(__values[22])),
+      "r"(__as_b32(__values[23])),
+      "r"(__as_b32(__values[24])),
+      "r"(__as_b32(__values[25])),
+      "r"(__as_b32(__values[26])),
+      "r"(__as_b32(__values[27])),
+      "r"(__as_b32(__values[28])),
+      "r"(__as_b32(__values[29])),
+      "r"(__as_b32(__values[30])),
+      "r"(__as_b32(__values[31])),
+      "r"(__as_b32(__values[32])),
+      "r"(__as_b32(__values[33])),
+      "r"(__as_b32(__values[34])),
+      "r"(__as_b32(__values[35])),
+      "r"(__as_b32(__values[36])),
+      "r"(__as_b32(__values[37])),
+      "r"(__as_b32(__values[38])),
+      "r"(__as_b32(__values[39])),
+      "r"(__as_b32(__values[40])),
+      "r"(__as_b32(__values[41])),
+      "r"(__as_b32(__values[42])),
+      "r"(__as_b32(__values[43])),
+      "r"(__as_b32(__values[44])),
+      "r"(__as_b32(__values[45])),
+      "r"(__as_b32(__values[46])),
+      "r"(__as_b32(__values[47])),
+      "r"(__as_b32(__values[48])),
+      "r"(__as_b32(__values[49])),
+      "r"(__as_b32(__values[50])),
+      "r"(__as_b32(__values[51])),
+      "r"(__as_b32(__values[52])),
+      "r"(__as_b32(__values[53])),
+      "r"(__as_b32(__values[54])),
+      "r"(__as_b32(__values[55])),
+      "r"(__as_b32(__values[56])),
+      "r"(__as_b32(__values[57])),
+      "r"(__as_b32(__values[58])),
+      "r"(__as_b32(__values[59])),
+      "r"(__as_b32(__values[60])),
+      "r"(__as_b32(__values[61])),
+      "r"(__as_b32(__values[62])),
+      "r"(__as_b32(__values[63])),
+      "r"(__as_b32(__values[64])),
+      "r"(__as_b32(__values[65])),
+      "r"(__as_b32(__values[66])),
+      "r"(__as_b32(__values[67])),
+      "r"(__as_b32(__values[68])),
+      "r"(__as_b32(__values[69])),
+      "r"(__as_b32(__values[70])),
+      "r"(__as_b32(__values[71])),
+      "r"(__as_b32(__values[72])),
+      "r"(__as_b32(__values[73])),
+      "r"(__as_b32(__values[74])),
+      "r"(__as_b32(__values[75])),
+      "r"(__as_b32(__values[76])),
+      "r"(__as_b32(__values[77])),
+      "r"(__as_b32(__values[78])),
+      "r"(__as_b32(__values[79])),
+      "r"(__as_b32(__values[80])),
+      "r"(__as_b32(__values[81])),
+      "r"(__as_b32(__values[82])),
+      "r"(__as_b32(__values[83])),
+      "r"(__as_b32(__values[84])),
+      "r"(__as_b32(__values[85])),
+      "r"(__as_b32(__values[86])),
+      "r"(__as_b32(__values[87])),
+      "r"(__as_b32(__values[88])),
+      "r"(__as_b32(__values[89])),
+      "r"(__as_b32(__values[90])),
+      "r"(__as_b32(__values[91])),
+      "r"(__as_b32(__values[92])),
+      "r"(__as_b32(__values[93])),
+      "r"(__as_b32(__values[94])),
+      "r"(__as_b32(__values[95])),
+      "r"(__as_b32(__values[96])),
+      "r"(__as_b32(__values[97])),
+      "r"(__as_b32(__values[98])),
+      "r"(__as_b32(__values[99])),
+      "r"(__as_b32(__values[100])),
+      "r"(__as_b32(__values[101])),
+      "r"(__as_b32(__values[102])),
+      "r"(__as_b32(__values[103])),
+      "r"(__as_b32(__values[104])),
+      "r"(__as_b32(__values[105])),
+      "r"(__as_b32(__values[106])),
+      "r"(__as_b32(__values[107])),
+      "r"(__as_b32(__values[108])),
+      "r"(__as_b32(__values[109])),
+      "r"(__as_b32(__values[110])),
+      "r"(__as_b32(__values[111])),
+      "r"(__as_b32(__values[112])),
+      "r"(__as_b32(__values[113])),
+      "r"(__as_b32(__values[114])),
+      "r"(__as_b32(__values[115])),
+      "r"(__as_b32(__values[116])),
+      "r"(__as_b32(__values[117])),
+      "r"(__as_b32(__values[118])),
+      "r"(__as_b32(__values[119])),
+      "r"(__as_b32(__values[120])),
+      "r"(__as_b32(__values[121])),
+      "r"(__as_b32(__values[122])),
+      "r"(__as_b32(__values[123])),
+      "r"(__as_b32(__values[124])),
+      "r"(__as_b32(__values[125])),
+      "r"(__as_b32(__values[126])),
+      "r"(__as_b32(__values[127]))
+    : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_st_32x32b_unpack_16b_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.st.sync.aligned.16x32bx2.x1.b32 [taddr], immHalfSplitoff, values; // PTX ISA 86, SM_100a, SM_101a
+template <int N32, typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+__device__ static inline void tcgen05_st_16x32bx2(
+  uint32_t taddr,
+  cuda::ptx::n32_t<N32> immHalfSplitoff,
+  const B32 (&values)[1]);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_st_16x32bx2_is_not_supported_before_SM_100a_SM_101a__();
+template <int _N32, typename _B32, _CUDA_VSTD::enable_if_t<sizeof(_B32) == 4, bool> = true>
+_CCCL_DEVICE static inline void
+tcgen05_st_16x32bx2(_CUDA_VSTD::uint32_t __taddr, n32_t<_N32> __immHalfSplitoff, const _B32 (&__values)[1])
+{
+  static_assert(sizeof(_B32) == 4, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  asm("tcgen05.st.sync.aligned.16x32bx2.x1.b32 [%0], %1, {%2};"
+      :
+      : "r"(__taddr), "n"(__immHalfSplitoff.value), "r"(__as_b32(__values[0]))
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_st_16x32bx2_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.st.sync.aligned.16x32bx2.x1.unpack::16b.b32 [taddr], immHalfSplitoff, values; // PTX ISA 86, SM_100a, SM_101a
+template <int N32, typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+__device__ static inline void tcgen05_st_16x32bx2_unpack_16b(
+  uint32_t taddr,
+  cuda::ptx::n32_t<N32> immHalfSplitoff,
+  const B32 (&values)[1]);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_st_16x32bx2_unpack_16b_is_not_supported_before_SM_100a_SM_101a__();
+template <int _N32, typename _B32, _CUDA_VSTD::enable_if_t<sizeof(_B32) == 4, bool> = true>
+_CCCL_DEVICE static inline void
+tcgen05_st_16x32bx2_unpack_16b(_CUDA_VSTD::uint32_t __taddr, n32_t<_N32> __immHalfSplitoff, const _B32 (&__values)[1])
+{
+  static_assert(sizeof(_B32) == 4, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  asm("tcgen05.st.sync.aligned.16x32bx2.x1.unpack::16b.b32 [%0], %1, {%2};"
+      :
+      : "r"(__taddr), "n"(__immHalfSplitoff.value), "r"(__as_b32(__values[0]))
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_st_16x32bx2_unpack_16b_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.st.sync.aligned.16x32bx2.x2.b32 [taddr], immHalfSplitoff, values; // PTX ISA 86, SM_100a, SM_101a
+template <int N32, typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+__device__ static inline void tcgen05_st_16x32bx2(
+  uint32_t taddr,
+  cuda::ptx::n32_t<N32> immHalfSplitoff,
+  const B32 (&values)[2]);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_st_16x32bx2_is_not_supported_before_SM_100a_SM_101a__();
+template <int _N32, typename _B32, _CUDA_VSTD::enable_if_t<sizeof(_B32) == 4, bool> = true>
+_CCCL_DEVICE static inline void
+tcgen05_st_16x32bx2(_CUDA_VSTD::uint32_t __taddr, n32_t<_N32> __immHalfSplitoff, const _B32 (&__values)[2])
+{
+  static_assert(sizeof(_B32) == 4, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  asm("tcgen05.st.sync.aligned.16x32bx2.x2.b32 [%0], %1, {%2, %3};"
+      :
+      : "r"(__taddr), "n"(__immHalfSplitoff.value), "r"(__as_b32(__values[0])), "r"(__as_b32(__values[1]))
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_st_16x32bx2_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.st.sync.aligned.16x32bx2.x2.unpack::16b.b32 [taddr], immHalfSplitoff, values; // PTX ISA 86, SM_100a, SM_101a
+template <int N32, typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+__device__ static inline void tcgen05_st_16x32bx2_unpack_16b(
+  uint32_t taddr,
+  cuda::ptx::n32_t<N32> immHalfSplitoff,
+  const B32 (&values)[2]);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_st_16x32bx2_unpack_16b_is_not_supported_before_SM_100a_SM_101a__();
+template <int _N32, typename _B32, _CUDA_VSTD::enable_if_t<sizeof(_B32) == 4, bool> = true>
+_CCCL_DEVICE static inline void
+tcgen05_st_16x32bx2_unpack_16b(_CUDA_VSTD::uint32_t __taddr, n32_t<_N32> __immHalfSplitoff, const _B32 (&__values)[2])
+{
+  static_assert(sizeof(_B32) == 4, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  asm("tcgen05.st.sync.aligned.16x32bx2.x2.unpack::16b.b32 [%0], %1, {%2, %3};"
+      :
+      : "r"(__taddr), "n"(__immHalfSplitoff.value), "r"(__as_b32(__values[0])), "r"(__as_b32(__values[1]))
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_st_16x32bx2_unpack_16b_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.st.sync.aligned.16x32bx2.x4.b32 [taddr], immHalfSplitoff, values; // PTX ISA 86, SM_100a, SM_101a
+template <int N32, typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+__device__ static inline void tcgen05_st_16x32bx2(
+  uint32_t taddr,
+  cuda::ptx::n32_t<N32> immHalfSplitoff,
+  const B32 (&values)[4]);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_st_16x32bx2_is_not_supported_before_SM_100a_SM_101a__();
+template <int _N32, typename _B32, _CUDA_VSTD::enable_if_t<sizeof(_B32) == 4, bool> = true>
+_CCCL_DEVICE static inline void
+tcgen05_st_16x32bx2(_CUDA_VSTD::uint32_t __taddr, n32_t<_N32> __immHalfSplitoff, const _B32 (&__values)[4])
+{
+  static_assert(sizeof(_B32) == 4, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  asm("tcgen05.st.sync.aligned.16x32bx2.x4.b32 [%0], %1, {%2, %3, %4, %5};"
+      :
+      : "r"(__taddr),
+        "n"(__immHalfSplitoff.value),
+        "r"(__as_b32(__values[0])),
+        "r"(__as_b32(__values[1])),
+        "r"(__as_b32(__values[2])),
+        "r"(__as_b32(__values[3]))
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_st_16x32bx2_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.st.sync.aligned.16x32bx2.x4.unpack::16b.b32 [taddr], immHalfSplitoff, values; // PTX ISA 86, SM_100a, SM_101a
+template <int N32, typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+__device__ static inline void tcgen05_st_16x32bx2_unpack_16b(
+  uint32_t taddr,
+  cuda::ptx::n32_t<N32> immHalfSplitoff,
+  const B32 (&values)[4]);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_st_16x32bx2_unpack_16b_is_not_supported_before_SM_100a_SM_101a__();
+template <int _N32, typename _B32, _CUDA_VSTD::enable_if_t<sizeof(_B32) == 4, bool> = true>
+_CCCL_DEVICE static inline void
+tcgen05_st_16x32bx2_unpack_16b(_CUDA_VSTD::uint32_t __taddr, n32_t<_N32> __immHalfSplitoff, const _B32 (&__values)[4])
+{
+  static_assert(sizeof(_B32) == 4, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  asm("tcgen05.st.sync.aligned.16x32bx2.x4.unpack::16b.b32 [%0], %1, {%2, %3, %4, %5};"
+      :
+      : "r"(__taddr),
+        "n"(__immHalfSplitoff.value),
+        "r"(__as_b32(__values[0])),
+        "r"(__as_b32(__values[1])),
+        "r"(__as_b32(__values[2])),
+        "r"(__as_b32(__values[3]))
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_st_16x32bx2_unpack_16b_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.st.sync.aligned.16x32bx2.x8.b32 [taddr], immHalfSplitoff, values; // PTX ISA 86, SM_100a, SM_101a
+template <int N32, typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+__device__ static inline void tcgen05_st_16x32bx2(
+  uint32_t taddr,
+  cuda::ptx::n32_t<N32> immHalfSplitoff,
+  const B32 (&values)[8]);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_st_16x32bx2_is_not_supported_before_SM_100a_SM_101a__();
+template <int _N32, typename _B32, _CUDA_VSTD::enable_if_t<sizeof(_B32) == 4, bool> = true>
+_CCCL_DEVICE static inline void
+tcgen05_st_16x32bx2(_CUDA_VSTD::uint32_t __taddr, n32_t<_N32> __immHalfSplitoff, const _B32 (&__values)[8])
+{
+  static_assert(sizeof(_B32) == 4, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  asm("tcgen05.st.sync.aligned.16x32bx2.x8.b32 [%0], %1, {%2, %3, %4, %5, %6, %7, %8, %9};"
+      :
+      : "r"(__taddr),
+        "n"(__immHalfSplitoff.value),
+        "r"(__as_b32(__values[0])),
+        "r"(__as_b32(__values[1])),
+        "r"(__as_b32(__values[2])),
+        "r"(__as_b32(__values[3])),
+        "r"(__as_b32(__values[4])),
+        "r"(__as_b32(__values[5])),
+        "r"(__as_b32(__values[6])),
+        "r"(__as_b32(__values[7]))
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_st_16x32bx2_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.st.sync.aligned.16x32bx2.x8.unpack::16b.b32 [taddr], immHalfSplitoff, values; // PTX ISA 86, SM_100a, SM_101a
+template <int N32, typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+__device__ static inline void tcgen05_st_16x32bx2_unpack_16b(
+  uint32_t taddr,
+  cuda::ptx::n32_t<N32> immHalfSplitoff,
+  const B32 (&values)[8]);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_st_16x32bx2_unpack_16b_is_not_supported_before_SM_100a_SM_101a__();
+template <int _N32, typename _B32, _CUDA_VSTD::enable_if_t<sizeof(_B32) == 4, bool> = true>
+_CCCL_DEVICE static inline void
+tcgen05_st_16x32bx2_unpack_16b(_CUDA_VSTD::uint32_t __taddr, n32_t<_N32> __immHalfSplitoff, const _B32 (&__values)[8])
+{
+  static_assert(sizeof(_B32) == 4, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  asm("tcgen05.st.sync.aligned.16x32bx2.x8.unpack::16b.b32 [%0], %1, {%2, %3, %4, %5, %6, %7, %8, %9};"
+      :
+      : "r"(__taddr),
+        "n"(__immHalfSplitoff.value),
+        "r"(__as_b32(__values[0])),
+        "r"(__as_b32(__values[1])),
+        "r"(__as_b32(__values[2])),
+        "r"(__as_b32(__values[3])),
+        "r"(__as_b32(__values[4])),
+        "r"(__as_b32(__values[5])),
+        "r"(__as_b32(__values[6])),
+        "r"(__as_b32(__values[7]))
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_st_16x32bx2_unpack_16b_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.st.sync.aligned.16x32bx2.x16.b32 [taddr], immHalfSplitoff, values; // PTX ISA 86, SM_100a, SM_101a
+template <int N32, typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+__device__ static inline void tcgen05_st_16x32bx2(
+  uint32_t taddr,
+  cuda::ptx::n32_t<N32> immHalfSplitoff,
+  const B32 (&values)[16]);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_st_16x32bx2_is_not_supported_before_SM_100a_SM_101a__();
+template <int _N32, typename _B32, _CUDA_VSTD::enable_if_t<sizeof(_B32) == 4, bool> = true>
+_CCCL_DEVICE static inline void
+tcgen05_st_16x32bx2(_CUDA_VSTD::uint32_t __taddr, n32_t<_N32> __immHalfSplitoff, const _B32 (&__values)[16])
+{
+  static_assert(sizeof(_B32) == 4, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  asm("tcgen05.st.sync.aligned.16x32bx2.x16.b32 [%0], %1, {%2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, "
+      "%15, %16, %17};"
+      :
+      : "r"(__taddr),
+        "n"(__immHalfSplitoff.value),
+        "r"(__as_b32(__values[0])),
+        "r"(__as_b32(__values[1])),
+        "r"(__as_b32(__values[2])),
+        "r"(__as_b32(__values[3])),
+        "r"(__as_b32(__values[4])),
+        "r"(__as_b32(__values[5])),
+        "r"(__as_b32(__values[6])),
+        "r"(__as_b32(__values[7])),
+        "r"(__as_b32(__values[8])),
+        "r"(__as_b32(__values[9])),
+        "r"(__as_b32(__values[10])),
+        "r"(__as_b32(__values[11])),
+        "r"(__as_b32(__values[12])),
+        "r"(__as_b32(__values[13])),
+        "r"(__as_b32(__values[14])),
+        "r"(__as_b32(__values[15]))
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_st_16x32bx2_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.st.sync.aligned.16x32bx2.x16.unpack::16b.b32 [taddr], immHalfSplitoff, values; // PTX ISA 86, SM_100a,
+SM_101a template <int N32, typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+__device__ static inline void tcgen05_st_16x32bx2_unpack_16b(
+  uint32_t taddr,
+  cuda::ptx::n32_t<N32> immHalfSplitoff,
+  const B32 (&values)[16]);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_st_16x32bx2_unpack_16b_is_not_supported_before_SM_100a_SM_101a__();
+template <int _N32, typename _B32, _CUDA_VSTD::enable_if_t<sizeof(_B32) == 4, bool> = true>
+_CCCL_DEVICE static inline void
+tcgen05_st_16x32bx2_unpack_16b(_CUDA_VSTD::uint32_t __taddr, n32_t<_N32> __immHalfSplitoff, const _B32 (&__values)[16])
+{
+  static_assert(sizeof(_B32) == 4, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  asm("tcgen05.st.sync.aligned.16x32bx2.x16.unpack::16b.b32 [%0], %1, {%2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, "
+      "%13, %14, %15, %16, %17};"
+      :
+      : "r"(__taddr),
+        "n"(__immHalfSplitoff.value),
+        "r"(__as_b32(__values[0])),
+        "r"(__as_b32(__values[1])),
+        "r"(__as_b32(__values[2])),
+        "r"(__as_b32(__values[3])),
+        "r"(__as_b32(__values[4])),
+        "r"(__as_b32(__values[5])),
+        "r"(__as_b32(__values[6])),
+        "r"(__as_b32(__values[7])),
+        "r"(__as_b32(__values[8])),
+        "r"(__as_b32(__values[9])),
+        "r"(__as_b32(__values[10])),
+        "r"(__as_b32(__values[11])),
+        "r"(__as_b32(__values[12])),
+        "r"(__as_b32(__values[13])),
+        "r"(__as_b32(__values[14])),
+        "r"(__as_b32(__values[15]))
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_st_16x32bx2_unpack_16b_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.st.sync.aligned.16x32bx2.x32.b32 [taddr], immHalfSplitoff, values; // PTX ISA 86, SM_100a, SM_101a
+template <int N32, typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+__device__ static inline void tcgen05_st_16x32bx2(
+  uint32_t taddr,
+  cuda::ptx::n32_t<N32> immHalfSplitoff,
+  const B32 (&values)[32]);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_st_16x32bx2_is_not_supported_before_SM_100a_SM_101a__();
+template <int _N32, typename _B32, _CUDA_VSTD::enable_if_t<sizeof(_B32) == 4, bool> = true>
+_CCCL_DEVICE static inline void
+tcgen05_st_16x32bx2(_CUDA_VSTD::uint32_t __taddr, n32_t<_N32> __immHalfSplitoff, const _B32 (&__values)[32])
+{
+  static_assert(sizeof(_B32) == 4, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  asm(
+    "tcgen05.st.sync.aligned.16x32bx2.x32.b32 [%0], %1, {%2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, "
+    "%16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33};"
+    :
+    : "r"(__taddr),
+      "n"(__immHalfSplitoff.value),
+      "r"(__as_b32(__values[0])),
+      "r"(__as_b32(__values[1])),
+      "r"(__as_b32(__values[2])),
+      "r"(__as_b32(__values[3])),
+      "r"(__as_b32(__values[4])),
+      "r"(__as_b32(__values[5])),
+      "r"(__as_b32(__values[6])),
+      "r"(__as_b32(__values[7])),
+      "r"(__as_b32(__values[8])),
+      "r"(__as_b32(__values[9])),
+      "r"(__as_b32(__values[10])),
+      "r"(__as_b32(__values[11])),
+      "r"(__as_b32(__values[12])),
+      "r"(__as_b32(__values[13])),
+      "r"(__as_b32(__values[14])),
+      "r"(__as_b32(__values[15])),
+      "r"(__as_b32(__values[16])),
+      "r"(__as_b32(__values[17])),
+      "r"(__as_b32(__values[18])),
+      "r"(__as_b32(__values[19])),
+      "r"(__as_b32(__values[20])),
+      "r"(__as_b32(__values[21])),
+      "r"(__as_b32(__values[22])),
+      "r"(__as_b32(__values[23])),
+      "r"(__as_b32(__values[24])),
+      "r"(__as_b32(__values[25])),
+      "r"(__as_b32(__values[26])),
+      "r"(__as_b32(__values[27])),
+      "r"(__as_b32(__values[28])),
+      "r"(__as_b32(__values[29])),
+      "r"(__as_b32(__values[30])),
+      "r"(__as_b32(__values[31]))
+    : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_st_16x32bx2_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.st.sync.aligned.16x32bx2.x32.unpack::16b.b32 [taddr], immHalfSplitoff, values; // PTX ISA 86, SM_100a,
+SM_101a template <int N32, typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+__device__ static inline void tcgen05_st_16x32bx2_unpack_16b(
+  uint32_t taddr,
+  cuda::ptx::n32_t<N32> immHalfSplitoff,
+  const B32 (&values)[32]);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_st_16x32bx2_unpack_16b_is_not_supported_before_SM_100a_SM_101a__();
+template <int _N32, typename _B32, _CUDA_VSTD::enable_if_t<sizeof(_B32) == 4, bool> = true>
+_CCCL_DEVICE static inline void
+tcgen05_st_16x32bx2_unpack_16b(_CUDA_VSTD::uint32_t __taddr, n32_t<_N32> __immHalfSplitoff, const _B32 (&__values)[32])
+{
+  static_assert(sizeof(_B32) == 4, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  asm(
+    "tcgen05.st.sync.aligned.16x32bx2.x32.unpack::16b.b32 [%0], %1, {%2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, "
+    "%13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33};"
+    :
+    : "r"(__taddr),
+      "n"(__immHalfSplitoff.value),
+      "r"(__as_b32(__values[0])),
+      "r"(__as_b32(__values[1])),
+      "r"(__as_b32(__values[2])),
+      "r"(__as_b32(__values[3])),
+      "r"(__as_b32(__values[4])),
+      "r"(__as_b32(__values[5])),
+      "r"(__as_b32(__values[6])),
+      "r"(__as_b32(__values[7])),
+      "r"(__as_b32(__values[8])),
+      "r"(__as_b32(__values[9])),
+      "r"(__as_b32(__values[10])),
+      "r"(__as_b32(__values[11])),
+      "r"(__as_b32(__values[12])),
+      "r"(__as_b32(__values[13])),
+      "r"(__as_b32(__values[14])),
+      "r"(__as_b32(__values[15])),
+      "r"(__as_b32(__values[16])),
+      "r"(__as_b32(__values[17])),
+      "r"(__as_b32(__values[18])),
+      "r"(__as_b32(__values[19])),
+      "r"(__as_b32(__values[20])),
+      "r"(__as_b32(__values[21])),
+      "r"(__as_b32(__values[22])),
+      "r"(__as_b32(__values[23])),
+      "r"(__as_b32(__values[24])),
+      "r"(__as_b32(__values[25])),
+      "r"(__as_b32(__values[26])),
+      "r"(__as_b32(__values[27])),
+      "r"(__as_b32(__values[28])),
+      "r"(__as_b32(__values[29])),
+      "r"(__as_b32(__values[30])),
+      "r"(__as_b32(__values[31]))
+    : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_st_16x32bx2_unpack_16b_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.st.sync.aligned.16x32bx2.x64.b32 [taddr], immHalfSplitoff, values; // PTX ISA 86, SM_100a, SM_101a
+template <int N32, typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+__device__ static inline void tcgen05_st_16x32bx2(
+  uint32_t taddr,
+  cuda::ptx::n32_t<N32> immHalfSplitoff,
+  const B32 (&values)[64]);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_st_16x32bx2_is_not_supported_before_SM_100a_SM_101a__();
+template <int _N32, typename _B32, _CUDA_VSTD::enable_if_t<sizeof(_B32) == 4, bool> = true>
+_CCCL_DEVICE static inline void
+tcgen05_st_16x32bx2(_CUDA_VSTD::uint32_t __taddr, n32_t<_N32> __immHalfSplitoff, const _B32 (&__values)[64])
+{
+  static_assert(sizeof(_B32) == 4, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  asm(
+    "tcgen05.st.sync.aligned.16x32bx2.x64.b32 [%0], %1, {%2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, "
+    "%16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, "
+    "%38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, "
+    "%60, %61, %62, %63, %64, %65};"
+    :
+    : "r"(__taddr),
+      "n"(__immHalfSplitoff.value),
+      "r"(__as_b32(__values[0])),
+      "r"(__as_b32(__values[1])),
+      "r"(__as_b32(__values[2])),
+      "r"(__as_b32(__values[3])),
+      "r"(__as_b32(__values[4])),
+      "r"(__as_b32(__values[5])),
+      "r"(__as_b32(__values[6])),
+      "r"(__as_b32(__values[7])),
+      "r"(__as_b32(__values[8])),
+      "r"(__as_b32(__values[9])),
+      "r"(__as_b32(__values[10])),
+      "r"(__as_b32(__values[11])),
+      "r"(__as_b32(__values[12])),
+      "r"(__as_b32(__values[13])),
+      "r"(__as_b32(__values[14])),
+      "r"(__as_b32(__values[15])),
+      "r"(__as_b32(__values[16])),
+      "r"(__as_b32(__values[17])),
+      "r"(__as_b32(__values[18])),
+      "r"(__as_b32(__values[19])),
+      "r"(__as_b32(__values[20])),
+      "r"(__as_b32(__values[21])),
+      "r"(__as_b32(__values[22])),
+      "r"(__as_b32(__values[23])),
+      "r"(__as_b32(__values[24])),
+      "r"(__as_b32(__values[25])),
+      "r"(__as_b32(__values[26])),
+      "r"(__as_b32(__values[27])),
+      "r"(__as_b32(__values[28])),
+      "r"(__as_b32(__values[29])),
+      "r"(__as_b32(__values[30])),
+      "r"(__as_b32(__values[31])),
+      "r"(__as_b32(__values[32])),
+      "r"(__as_b32(__values[33])),
+      "r"(__as_b32(__values[34])),
+      "r"(__as_b32(__values[35])),
+      "r"(__as_b32(__values[36])),
+      "r"(__as_b32(__values[37])),
+      "r"(__as_b32(__values[38])),
+      "r"(__as_b32(__values[39])),
+      "r"(__as_b32(__values[40])),
+      "r"(__as_b32(__values[41])),
+      "r"(__as_b32(__values[42])),
+      "r"(__as_b32(__values[43])),
+      "r"(__as_b32(__values[44])),
+      "r"(__as_b32(__values[45])),
+      "r"(__as_b32(__values[46])),
+      "r"(__as_b32(__values[47])),
+      "r"(__as_b32(__values[48])),
+      "r"(__as_b32(__values[49])),
+      "r"(__as_b32(__values[50])),
+      "r"(__as_b32(__values[51])),
+      "r"(__as_b32(__values[52])),
+      "r"(__as_b32(__values[53])),
+      "r"(__as_b32(__values[54])),
+      "r"(__as_b32(__values[55])),
+      "r"(__as_b32(__values[56])),
+      "r"(__as_b32(__values[57])),
+      "r"(__as_b32(__values[58])),
+      "r"(__as_b32(__values[59])),
+      "r"(__as_b32(__values[60])),
+      "r"(__as_b32(__values[61])),
+      "r"(__as_b32(__values[62])),
+      "r"(__as_b32(__values[63]))
+    : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_st_16x32bx2_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.st.sync.aligned.16x32bx2.x64.unpack::16b.b32 [taddr], immHalfSplitoff, values; // PTX ISA 86, SM_100a,
+SM_101a template <int N32, typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+__device__ static inline void tcgen05_st_16x32bx2_unpack_16b(
+  uint32_t taddr,
+  cuda::ptx::n32_t<N32> immHalfSplitoff,
+  const B32 (&values)[64]);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_st_16x32bx2_unpack_16b_is_not_supported_before_SM_100a_SM_101a__();
+template <int _N32, typename _B32, _CUDA_VSTD::enable_if_t<sizeof(_B32) == 4, bool> = true>
+_CCCL_DEVICE static inline void
+tcgen05_st_16x32bx2_unpack_16b(_CUDA_VSTD::uint32_t __taddr, n32_t<_N32> __immHalfSplitoff, const _B32 (&__values)[64])
+{
+  static_assert(sizeof(_B32) == 4, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  asm(
+    "tcgen05.st.sync.aligned.16x32bx2.x64.unpack::16b.b32 [%0], %1, {%2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, "
+    "%13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, "
+    "%35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, "
+    "%57, %58, %59, %60, %61, %62, %63, %64, %65};"
+    :
+    : "r"(__taddr),
+      "n"(__immHalfSplitoff.value),
+      "r"(__as_b32(__values[0])),
+      "r"(__as_b32(__values[1])),
+      "r"(__as_b32(__values[2])),
+      "r"(__as_b32(__values[3])),
+      "r"(__as_b32(__values[4])),
+      "r"(__as_b32(__values[5])),
+      "r"(__as_b32(__values[6])),
+      "r"(__as_b32(__values[7])),
+      "r"(__as_b32(__values[8])),
+      "r"(__as_b32(__values[9])),
+      "r"(__as_b32(__values[10])),
+      "r"(__as_b32(__values[11])),
+      "r"(__as_b32(__values[12])),
+      "r"(__as_b32(__values[13])),
+      "r"(__as_b32(__values[14])),
+      "r"(__as_b32(__values[15])),
+      "r"(__as_b32(__values[16])),
+      "r"(__as_b32(__values[17])),
+      "r"(__as_b32(__values[18])),
+      "r"(__as_b32(__values[19])),
+      "r"(__as_b32(__values[20])),
+      "r"(__as_b32(__values[21])),
+      "r"(__as_b32(__values[22])),
+      "r"(__as_b32(__values[23])),
+      "r"(__as_b32(__values[24])),
+      "r"(__as_b32(__values[25])),
+      "r"(__as_b32(__values[26])),
+      "r"(__as_b32(__values[27])),
+      "r"(__as_b32(__values[28])),
+      "r"(__as_b32(__values[29])),
+      "r"(__as_b32(__values[30])),
+      "r"(__as_b32(__values[31])),
+      "r"(__as_b32(__values[32])),
+      "r"(__as_b32(__values[33])),
+      "r"(__as_b32(__values[34])),
+      "r"(__as_b32(__values[35])),
+      "r"(__as_b32(__values[36])),
+      "r"(__as_b32(__values[37])),
+      "r"(__as_b32(__values[38])),
+      "r"(__as_b32(__values[39])),
+      "r"(__as_b32(__values[40])),
+      "r"(__as_b32(__values[41])),
+      "r"(__as_b32(__values[42])),
+      "r"(__as_b32(__values[43])),
+      "r"(__as_b32(__values[44])),
+      "r"(__as_b32(__values[45])),
+      "r"(__as_b32(__values[46])),
+      "r"(__as_b32(__values[47])),
+      "r"(__as_b32(__values[48])),
+      "r"(__as_b32(__values[49])),
+      "r"(__as_b32(__values[50])),
+      "r"(__as_b32(__values[51])),
+      "r"(__as_b32(__values[52])),
+      "r"(__as_b32(__values[53])),
+      "r"(__as_b32(__values[54])),
+      "r"(__as_b32(__values[55])),
+      "r"(__as_b32(__values[56])),
+      "r"(__as_b32(__values[57])),
+      "r"(__as_b32(__values[58])),
+      "r"(__as_b32(__values[59])),
+      "r"(__as_b32(__values[60])),
+      "r"(__as_b32(__values[61])),
+      "r"(__as_b32(__values[62])),
+      "r"(__as_b32(__values[63]))
+    : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_st_16x32bx2_unpack_16b_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.st.sync.aligned.16x32bx2.x128.b32 [taddr], immHalfSplitoff, values; // PTX ISA 86, SM_100a, SM_101a
+template <int N32, typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+__device__ static inline void tcgen05_st_16x32bx2(
+  uint32_t taddr,
+  cuda::ptx::n32_t<N32> immHalfSplitoff,
+  const B32 (&values)[128]);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_st_16x32bx2_is_not_supported_before_SM_100a_SM_101a__();
+template <int _N32, typename _B32, _CUDA_VSTD::enable_if_t<sizeof(_B32) == 4, bool> = true>
+_CCCL_DEVICE static inline void
+tcgen05_st_16x32bx2(_CUDA_VSTD::uint32_t __taddr, n32_t<_N32> __immHalfSplitoff, const _B32 (&__values)[128])
+{
+  static_assert(sizeof(_B32) == 4, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  asm(
+    "tcgen05.st.sync.aligned.16x32bx2.x128.b32 [%0], %1, {%2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, "
+    "%15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, "
+    "%37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, "
+    "%59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, "
+    "%81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, "
+    "%103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, "
+    "%122, %123, %124, %125, %126, %127, %128, %129};"
+    :
+    : "r"(__taddr),
+      "n"(__immHalfSplitoff.value),
+      "r"(__as_b32(__values[0])),
+      "r"(__as_b32(__values[1])),
+      "r"(__as_b32(__values[2])),
+      "r"(__as_b32(__values[3])),
+      "r"(__as_b32(__values[4])),
+      "r"(__as_b32(__values[5])),
+      "r"(__as_b32(__values[6])),
+      "r"(__as_b32(__values[7])),
+      "r"(__as_b32(__values[8])),
+      "r"(__as_b32(__values[9])),
+      "r"(__as_b32(__values[10])),
+      "r"(__as_b32(__values[11])),
+      "r"(__as_b32(__values[12])),
+      "r"(__as_b32(__values[13])),
+      "r"(__as_b32(__values[14])),
+      "r"(__as_b32(__values[15])),
+      "r"(__as_b32(__values[16])),
+      "r"(__as_b32(__values[17])),
+      "r"(__as_b32(__values[18])),
+      "r"(__as_b32(__values[19])),
+      "r"(__as_b32(__values[20])),
+      "r"(__as_b32(__values[21])),
+      "r"(__as_b32(__values[22])),
+      "r"(__as_b32(__values[23])),
+      "r"(__as_b32(__values[24])),
+      "r"(__as_b32(__values[25])),
+      "r"(__as_b32(__values[26])),
+      "r"(__as_b32(__values[27])),
+      "r"(__as_b32(__values[28])),
+      "r"(__as_b32(__values[29])),
+      "r"(__as_b32(__values[30])),
+      "r"(__as_b32(__values[31])),
+      "r"(__as_b32(__values[32])),
+      "r"(__as_b32(__values[33])),
+      "r"(__as_b32(__values[34])),
+      "r"(__as_b32(__values[35])),
+      "r"(__as_b32(__values[36])),
+      "r"(__as_b32(__values[37])),
+      "r"(__as_b32(__values[38])),
+      "r"(__as_b32(__values[39])),
+      "r"(__as_b32(__values[40])),
+      "r"(__as_b32(__values[41])),
+      "r"(__as_b32(__values[42])),
+      "r"(__as_b32(__values[43])),
+      "r"(__as_b32(__values[44])),
+      "r"(__as_b32(__values[45])),
+      "r"(__as_b32(__values[46])),
+      "r"(__as_b32(__values[47])),
+      "r"(__as_b32(__values[48])),
+      "r"(__as_b32(__values[49])),
+      "r"(__as_b32(__values[50])),
+      "r"(__as_b32(__values[51])),
+      "r"(__as_b32(__values[52])),
+      "r"(__as_b32(__values[53])),
+      "r"(__as_b32(__values[54])),
+      "r"(__as_b32(__values[55])),
+      "r"(__as_b32(__values[56])),
+      "r"(__as_b32(__values[57])),
+      "r"(__as_b32(__values[58])),
+      "r"(__as_b32(__values[59])),
+      "r"(__as_b32(__values[60])),
+      "r"(__as_b32(__values[61])),
+      "r"(__as_b32(__values[62])),
+      "r"(__as_b32(__values[63])),
+      "r"(__as_b32(__values[64])),
+      "r"(__as_b32(__values[65])),
+      "r"(__as_b32(__values[66])),
+      "r"(__as_b32(__values[67])),
+      "r"(__as_b32(__values[68])),
+      "r"(__as_b32(__values[69])),
+      "r"(__as_b32(__values[70])),
+      "r"(__as_b32(__values[71])),
+      "r"(__as_b32(__values[72])),
+      "r"(__as_b32(__values[73])),
+      "r"(__as_b32(__values[74])),
+      "r"(__as_b32(__values[75])),
+      "r"(__as_b32(__values[76])),
+      "r"(__as_b32(__values[77])),
+      "r"(__as_b32(__values[78])),
+      "r"(__as_b32(__values[79])),
+      "r"(__as_b32(__values[80])),
+      "r"(__as_b32(__values[81])),
+      "r"(__as_b32(__values[82])),
+      "r"(__as_b32(__values[83])),
+      "r"(__as_b32(__values[84])),
+      "r"(__as_b32(__values[85])),
+      "r"(__as_b32(__values[86])),
+      "r"(__as_b32(__values[87])),
+      "r"(__as_b32(__values[88])),
+      "r"(__as_b32(__values[89])),
+      "r"(__as_b32(__values[90])),
+      "r"(__as_b32(__values[91])),
+      "r"(__as_b32(__values[92])),
+      "r"(__as_b32(__values[93])),
+      "r"(__as_b32(__values[94])),
+      "r"(__as_b32(__values[95])),
+      "r"(__as_b32(__values[96])),
+      "r"(__as_b32(__values[97])),
+      "r"(__as_b32(__values[98])),
+      "r"(__as_b32(__values[99])),
+      "r"(__as_b32(__values[100])),
+      "r"(__as_b32(__values[101])),
+      "r"(__as_b32(__values[102])),
+      "r"(__as_b32(__values[103])),
+      "r"(__as_b32(__values[104])),
+      "r"(__as_b32(__values[105])),
+      "r"(__as_b32(__values[106])),
+      "r"(__as_b32(__values[107])),
+      "r"(__as_b32(__values[108])),
+      "r"(__as_b32(__values[109])),
+      "r"(__as_b32(__values[110])),
+      "r"(__as_b32(__values[111])),
+      "r"(__as_b32(__values[112])),
+      "r"(__as_b32(__values[113])),
+      "r"(__as_b32(__values[114])),
+      "r"(__as_b32(__values[115])),
+      "r"(__as_b32(__values[116])),
+      "r"(__as_b32(__values[117])),
+      "r"(__as_b32(__values[118])),
+      "r"(__as_b32(__values[119])),
+      "r"(__as_b32(__values[120])),
+      "r"(__as_b32(__values[121])),
+      "r"(__as_b32(__values[122])),
+      "r"(__as_b32(__values[123])),
+      "r"(__as_b32(__values[124])),
+      "r"(__as_b32(__values[125])),
+      "r"(__as_b32(__values[126])),
+      "r"(__as_b32(__values[127]))
+    : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_st_16x32bx2_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.st.sync.aligned.16x32bx2.x128.unpack::16b.b32 [taddr], immHalfSplitoff, values; // PTX ISA 86, SM_100a,
+SM_101a template <int N32, typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+__device__ static inline void tcgen05_st_16x32bx2_unpack_16b(
+  uint32_t taddr,
+  cuda::ptx::n32_t<N32> immHalfSplitoff,
+  const B32 (&values)[128]);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_st_16x32bx2_unpack_16b_is_not_supported_before_SM_100a_SM_101a__();
+template <int _N32, typename _B32, _CUDA_VSTD::enable_if_t<sizeof(_B32) == 4, bool> = true>
+_CCCL_DEVICE static inline void
+tcgen05_st_16x32bx2_unpack_16b(_CUDA_VSTD::uint32_t __taddr, n32_t<_N32> __immHalfSplitoff, const _B32 (&__values)[128])
+{
+  static_assert(sizeof(_B32) == 4, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  asm(
+    "tcgen05.st.sync.aligned.16x32bx2.x128.unpack::16b.b32 [%0], %1, {%2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, "
+    "%13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, "
+    "%35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, "
+    "%57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, "
+    "%79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, "
+    "%101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, "
+    "%120, %121, %122, %123, %124, %125, %126, %127, %128, %129};"
+    :
+    : "r"(__taddr),
+      "n"(__immHalfSplitoff.value),
+      "r"(__as_b32(__values[0])),
+      "r"(__as_b32(__values[1])),
+      "r"(__as_b32(__values[2])),
+      "r"(__as_b32(__values[3])),
+      "r"(__as_b32(__values[4])),
+      "r"(__as_b32(__values[5])),
+      "r"(__as_b32(__values[6])),
+      "r"(__as_b32(__values[7])),
+      "r"(__as_b32(__values[8])),
+      "r"(__as_b32(__values[9])),
+      "r"(__as_b32(__values[10])),
+      "r"(__as_b32(__values[11])),
+      "r"(__as_b32(__values[12])),
+      "r"(__as_b32(__values[13])),
+      "r"(__as_b32(__values[14])),
+      "r"(__as_b32(__values[15])),
+      "r"(__as_b32(__values[16])),
+      "r"(__as_b32(__values[17])),
+      "r"(__as_b32(__values[18])),
+      "r"(__as_b32(__values[19])),
+      "r"(__as_b32(__values[20])),
+      "r"(__as_b32(__values[21])),
+      "r"(__as_b32(__values[22])),
+      "r"(__as_b32(__values[23])),
+      "r"(__as_b32(__values[24])),
+      "r"(__as_b32(__values[25])),
+      "r"(__as_b32(__values[26])),
+      "r"(__as_b32(__values[27])),
+      "r"(__as_b32(__values[28])),
+      "r"(__as_b32(__values[29])),
+      "r"(__as_b32(__values[30])),
+      "r"(__as_b32(__values[31])),
+      "r"(__as_b32(__values[32])),
+      "r"(__as_b32(__values[33])),
+      "r"(__as_b32(__values[34])),
+      "r"(__as_b32(__values[35])),
+      "r"(__as_b32(__values[36])),
+      "r"(__as_b32(__values[37])),
+      "r"(__as_b32(__values[38])),
+      "r"(__as_b32(__values[39])),
+      "r"(__as_b32(__values[40])),
+      "r"(__as_b32(__values[41])),
+      "r"(__as_b32(__values[42])),
+      "r"(__as_b32(__values[43])),
+      "r"(__as_b32(__values[44])),
+      "r"(__as_b32(__values[45])),
+      "r"(__as_b32(__values[46])),
+      "r"(__as_b32(__values[47])),
+      "r"(__as_b32(__values[48])),
+      "r"(__as_b32(__values[49])),
+      "r"(__as_b32(__values[50])),
+      "r"(__as_b32(__values[51])),
+      "r"(__as_b32(__values[52])),
+      "r"(__as_b32(__values[53])),
+      "r"(__as_b32(__values[54])),
+      "r"(__as_b32(__values[55])),
+      "r"(__as_b32(__values[56])),
+      "r"(__as_b32(__values[57])),
+      "r"(__as_b32(__values[58])),
+      "r"(__as_b32(__values[59])),
+      "r"(__as_b32(__values[60])),
+      "r"(__as_b32(__values[61])),
+      "r"(__as_b32(__values[62])),
+      "r"(__as_b32(__values[63])),
+      "r"(__as_b32(__values[64])),
+      "r"(__as_b32(__values[65])),
+      "r"(__as_b32(__values[66])),
+      "r"(__as_b32(__values[67])),
+      "r"(__as_b32(__values[68])),
+      "r"(__as_b32(__values[69])),
+      "r"(__as_b32(__values[70])),
+      "r"(__as_b32(__values[71])),
+      "r"(__as_b32(__values[72])),
+      "r"(__as_b32(__values[73])),
+      "r"(__as_b32(__values[74])),
+      "r"(__as_b32(__values[75])),
+      "r"(__as_b32(__values[76])),
+      "r"(__as_b32(__values[77])),
+      "r"(__as_b32(__values[78])),
+      "r"(__as_b32(__values[79])),
+      "r"(__as_b32(__values[80])),
+      "r"(__as_b32(__values[81])),
+      "r"(__as_b32(__values[82])),
+      "r"(__as_b32(__values[83])),
+      "r"(__as_b32(__values[84])),
+      "r"(__as_b32(__values[85])),
+      "r"(__as_b32(__values[86])),
+      "r"(__as_b32(__values[87])),
+      "r"(__as_b32(__values[88])),
+      "r"(__as_b32(__values[89])),
+      "r"(__as_b32(__values[90])),
+      "r"(__as_b32(__values[91])),
+      "r"(__as_b32(__values[92])),
+      "r"(__as_b32(__values[93])),
+      "r"(__as_b32(__values[94])),
+      "r"(__as_b32(__values[95])),
+      "r"(__as_b32(__values[96])),
+      "r"(__as_b32(__values[97])),
+      "r"(__as_b32(__values[98])),
+      "r"(__as_b32(__values[99])),
+      "r"(__as_b32(__values[100])),
+      "r"(__as_b32(__values[101])),
+      "r"(__as_b32(__values[102])),
+      "r"(__as_b32(__values[103])),
+      "r"(__as_b32(__values[104])),
+      "r"(__as_b32(__values[105])),
+      "r"(__as_b32(__values[106])),
+      "r"(__as_b32(__values[107])),
+      "r"(__as_b32(__values[108])),
+      "r"(__as_b32(__values[109])),
+      "r"(__as_b32(__values[110])),
+      "r"(__as_b32(__values[111])),
+      "r"(__as_b32(__values[112])),
+      "r"(__as_b32(__values[113])),
+      "r"(__as_b32(__values[114])),
+      "r"(__as_b32(__values[115])),
+      "r"(__as_b32(__values[116])),
+      "r"(__as_b32(__values[117])),
+      "r"(__as_b32(__values[118])),
+      "r"(__as_b32(__values[119])),
+      "r"(__as_b32(__values[120])),
+      "r"(__as_b32(__values[121])),
+      "r"(__as_b32(__values[122])),
+      "r"(__as_b32(__values[123])),
+      "r"(__as_b32(__values[124])),
+      "r"(__as_b32(__values[125])),
+      "r"(__as_b32(__values[126])),
+      "r"(__as_b32(__values[127]))
+    : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_st_16x32bx2_unpack_16b_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+#endif // _CUDA_PTX_GENERATED_TCGEN05_ST_H_
diff --git a/libcudacxx/include/cuda/__ptx/instructions/generated/tcgen05_wait.h b/libcudacxx/include/cuda/__ptx/instructions/generated/tcgen05_wait.h
new file mode 100644
index 00000000000..5f683c07fea
--- /dev/null
+++ b/libcudacxx/include/cuda/__ptx/instructions/generated/tcgen05_wait.h
@@ -0,0 +1,44 @@
+// This file was automatically generated. Do not edit.
+
+#ifndef _CUDA_PTX_GENERATED_TCGEN05_WAIT_H_
+#define _CUDA_PTX_GENERATED_TCGEN05_WAIT_H_
+
+/*
+// tcgen05.wait::ld.sync.aligned; // PTX ISA 86, SM_100a, SM_101a
+template <typename = void>
+__device__ static inline void tcgen05_wait_ld();
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_wait_ld_is_not_supported_before_SM_100a_SM_101a__();
+template <typename = void>
+_CCCL_DEVICE static inline void tcgen05_wait_ld()
+{
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  asm volatile("tcgen05.wait::ld.sync.aligned;" : : : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_wait_ld_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tcgen05.wait::st.sync.aligned; // PTX ISA 86, SM_100a, SM_101a
+template <typename = void>
+__device__ static inline void tcgen05_wait_st();
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tcgen05_wait_st_is_not_supported_before_SM_100a_SM_101a__();
+template <typename = void>
+_CCCL_DEVICE static inline void tcgen05_wait_st()
+{
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  asm volatile("tcgen05.wait::st.sync.aligned;" : : : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tcgen05_wait_st_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+#endif // _CUDA_PTX_GENERATED_TCGEN05_WAIT_H_
diff --git a/libcudacxx/include/cuda/__ptx/instructions/generated/tensormap_cp_fenceproxy.h b/libcudacxx/include/cuda/__ptx/instructions/generated/tensormap_cp_fenceproxy.h
index b51b5185db0..db5e7dde640 100644
--- a/libcudacxx/include/cuda/__ptx/instructions/generated/tensormap_cp_fenceproxy.h
+++ b/libcudacxx/include/cuda/__ptx/instructions/generated/tensormap_cp_fenceproxy.h
@@ -24,37 +24,43 @@ tensormap_cp_fenceproxy(sem_release_t, scope_t<_Scope> __scope, void* __dst, con
 {
   // __sem == sem_release (due to parameter type constraint)
   static_assert(__scope == scope_cta || __scope == scope_cluster || __scope == scope_gpu || __scope == scope_sys, "");
-  NV_IF_ELSE_TARGET(
-    NV_PROVIDES_SM_90,
-    (
-      _CCCL_IF_CONSTEXPR (__scope == scope_cta) {
-        asm volatile(
-          "tensormap.cp_fenceproxy.global.shared::cta.tensormap::generic.release.cta.sync.aligned  [%0], [%1], %2;"
-          :
-          : "l"(__as_ptr_gmem(__dst)), "r"(__as_ptr_smem(__src)), "n"(__size.value)
-          : "memory");
-      } else _CCCL_IF_CONSTEXPR (__scope == scope_cluster) {
-        asm volatile(
-          "tensormap.cp_fenceproxy.global.shared::cta.tensormap::generic.release.cluster.sync.aligned  [%0], [%1], %2;"
-          :
-          : "l"(__as_ptr_gmem(__dst)), "r"(__as_ptr_smem(__src)), "n"(__size.value)
-          : "memory");
-      } else _CCCL_IF_CONSTEXPR (__scope == scope_gpu) {
-        asm volatile(
-          "tensormap.cp_fenceproxy.global.shared::cta.tensormap::generic.release.gpu.sync.aligned  [%0], [%1], %2;"
-          :
-          : "l"(__as_ptr_gmem(__dst)), "r"(__as_ptr_smem(__src)), "n"(__size.value)
-          : "memory");
-      } else _CCCL_IF_CONSTEXPR (__scope == scope_sys) {
-        asm volatile(
-          "tensormap.cp_fenceproxy.global.shared::cta.tensormap::generic.release.sys.sync.aligned  [%0], [%1], %2;"
-          :
-          : "l"(__as_ptr_gmem(__dst)), "r"(__as_ptr_smem(__src)), "n"(__size.value)
-          : "memory");
-      }),
-    (
-      // Unsupported architectures will have a linker error with a semi-decent error message
-      __cuda_ptx_tensormap_cp_fenceproxy_is_not_supported_before_SM_90__();));
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
+  _CCCL_IF_CONSTEXPR (__scope == scope_cta)
+  {
+    asm volatile(
+      "tensormap.cp_fenceproxy.global.shared::cta.tensormap::generic.release.cta.sync.aligned  [%0], [%1], %2;"
+      :
+      : "l"(__as_ptr_gmem(__dst)), "r"(__as_ptr_smem(__src)), "n"(__size.value)
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__scope == scope_cluster)
+  {
+    asm volatile(
+      "tensormap.cp_fenceproxy.global.shared::cta.tensormap::generic.release.cluster.sync.aligned  [%0], [%1], %2;"
+      :
+      : "l"(__as_ptr_gmem(__dst)), "r"(__as_ptr_smem(__src)), "n"(__size.value)
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__scope == scope_gpu)
+  {
+    asm volatile(
+      "tensormap.cp_fenceproxy.global.shared::cta.tensormap::generic.release.gpu.sync.aligned  [%0], [%1], %2;"
+      :
+      : "l"(__as_ptr_gmem(__dst)), "r"(__as_ptr_smem(__src)), "n"(__size.value)
+      : "memory");
+  }
+  else _CCCL_IF_CONSTEXPR (__scope == scope_sys)
+  {
+    asm volatile(
+      "tensormap.cp_fenceproxy.global.shared::cta.tensormap::generic.release.sys.sync.aligned  [%0], [%1], %2;"
+      :
+      : "l"(__as_ptr_gmem(__dst)), "r"(__as_ptr_smem(__src)), "n"(__size.value)
+      : "memory");
+  }
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tensormap_cp_fenceproxy_is_not_supported_before_SM_90__();
+#  endif
 }
 #endif // __cccl_ptx_isa >= 830
 
diff --git a/libcudacxx/include/cuda/__ptx/instructions/generated/tensormap_replace.h b/libcudacxx/include/cuda/__ptx/instructions/generated/tensormap_replace.h
index 598b56f90b0..53c56e159f7 100644
--- a/libcudacxx/include/cuda/__ptx/instructions/generated/tensormap_replace.h
+++ b/libcudacxx/include/cuda/__ptx/instructions/generated/tensormap_replace.h
@@ -4,113 +4,127 @@
 #define _CUDA_PTX_GENERATED_TENSORMAP_REPLACE_H_
 
 /*
-// tensormap.replace.tile.global_address.space.b1024.b64    [tm_addr], new_val; // PTX ISA 83, SM_90a
+// tensormap.replace.tile.global_address.space.b1024.b64 [tm_addr], new_val; // PTX ISA 83, SM_90a, SM_100a, SM_101a
 // .space     = { .global }
-template <typename B64>
+template <typename B64, enable_if_t<sizeof(B64) == 8, bool> = true>
 __device__ static inline void tensormap_replace_global_address(
   cuda::ptx::space_global_t,
   void* tm_addr,
   B64 new_val);
 */
 #if __cccl_ptx_isa >= 830
-extern "C" _CCCL_DEVICE void __cuda_ptx_tensormap_replace_global_address_is_not_supported_before_SM_90a__();
-template <typename _B64>
+extern "C" _CCCL_DEVICE void
+__cuda_ptx_tensormap_replace_global_address_is_not_supported_before_SM_90a_SM_100a_SM_101a__();
+template <typename _B64, _CUDA_VSTD::enable_if_t<sizeof(_B64) == 8, bool> = true>
 _CCCL_DEVICE static inline void tensormap_replace_global_address(space_global_t, void* __tm_addr, _B64 __new_val)
 {
   // __space == space_global (due to parameter type constraint)
   static_assert(sizeof(_B64) == 8, "");
-  NV_IF_ELSE_TARGET(
-    NV_HAS_FEATURE_SM_90a,
-    (asm("tensormap.replace.tile.global_address.global.b1024.b64    [%0], %1;" : : "l"(__as_ptr_gmem(__tm_addr)),
-         "l"(__as_b64(__new_val)) : "memory");),
-    (
-      // Unsupported architectures will have a linker error with a semi-decent error message
-      __cuda_ptx_tensormap_replace_global_address_is_not_supported_before_SM_90a__();));
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM90_ALL || __CUDA_ARCH_FEAT_SM100_ALL \
+    || __CUDA_ARCH_FEAT_SM101_ALL
+  asm("tensormap.replace.tile.global_address.global.b1024.b64 [%0], %1;"
+      :
+      : "l"(__as_ptr_gmem(__tm_addr)), "l"(__as_b64(__new_val))
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tensormap_replace_global_address_is_not_supported_before_SM_90a_SM_100a_SM_101a__();
+#  endif
 }
 #endif // __cccl_ptx_isa >= 830
 
 /*
-// tensormap.replace.tile.global_address.space.b1024.b64    [tm_addr], new_val; // PTX ISA 83, SM_90a
+// tensormap.replace.tile.global_address.space.b1024.b64 [tm_addr], new_val; // PTX ISA 83, SM_90a, SM_100a, SM_101a
 // .space     = { .shared::cta }
-template <typename B64>
+template <typename B64, enable_if_t<sizeof(B64) == 8, bool> = true>
 __device__ static inline void tensormap_replace_global_address(
   cuda::ptx::space_shared_t,
   void* tm_addr,
   B64 new_val);
 */
 #if __cccl_ptx_isa >= 830
-extern "C" _CCCL_DEVICE void __cuda_ptx_tensormap_replace_global_address_is_not_supported_before_SM_90a__();
-template <typename _B64>
+extern "C" _CCCL_DEVICE void
+__cuda_ptx_tensormap_replace_global_address_is_not_supported_before_SM_90a_SM_100a_SM_101a__();
+template <typename _B64, _CUDA_VSTD::enable_if_t<sizeof(_B64) == 8, bool> = true>
 _CCCL_DEVICE static inline void tensormap_replace_global_address(space_shared_t, void* __tm_addr, _B64 __new_val)
 {
   // __space == space_shared (due to parameter type constraint)
   static_assert(sizeof(_B64) == 8, "");
-  NV_IF_ELSE_TARGET(
-    NV_HAS_FEATURE_SM_90a,
-    (asm("tensormap.replace.tile.global_address.shared::cta.b1024.b64    [%0], %1;" : : "r"(__as_ptr_smem(__tm_addr)),
-         "l"(__as_b64(__new_val)) : "memory");),
-    (
-      // Unsupported architectures will have a linker error with a semi-decent error message
-      __cuda_ptx_tensormap_replace_global_address_is_not_supported_before_SM_90a__();));
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM90_ALL || __CUDA_ARCH_FEAT_SM100_ALL \
+    || __CUDA_ARCH_FEAT_SM101_ALL
+  asm("tensormap.replace.tile.global_address.shared::cta.b1024.b64 [%0], %1;"
+      :
+      : "r"(__as_ptr_smem(__tm_addr)), "l"(__as_b64(__new_val))
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tensormap_replace_global_address_is_not_supported_before_SM_90a_SM_100a_SM_101a__();
+#  endif
 }
 #endif // __cccl_ptx_isa >= 830
 
 /*
-// tensormap.replace.tile.rank.space.b1024.b32              [tm_addr], new_val; // PTX ISA 83, SM_90a
+// tensormap.replace.tile.rank.space.b1024.b32 [tm_addr], new_val; // PTX ISA 83, SM_90a, SM_100a, SM_101a
 // .space     = { .global }
-template <typename B32>
+template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
 __device__ static inline void tensormap_replace_rank(
   cuda::ptx::space_global_t,
   void* tm_addr,
   B32 new_val);
 */
 #if __cccl_ptx_isa >= 830
-extern "C" _CCCL_DEVICE void __cuda_ptx_tensormap_replace_rank_is_not_supported_before_SM_90a__();
-template <typename _B32>
+extern "C" _CCCL_DEVICE void __cuda_ptx_tensormap_replace_rank_is_not_supported_before_SM_90a_SM_100a_SM_101a__();
+template <typename _B32, _CUDA_VSTD::enable_if_t<sizeof(_B32) == 4, bool> = true>
 _CCCL_DEVICE static inline void tensormap_replace_rank(space_global_t, void* __tm_addr, _B32 __new_val)
 {
   // __space == space_global (due to parameter type constraint)
   static_assert(sizeof(_B32) == 4, "");
-  NV_IF_ELSE_TARGET(
-    NV_HAS_FEATURE_SM_90a,
-    (asm("tensormap.replace.tile.rank.global.b1024.b32              [%0], %1;" : : "l"(__as_ptr_gmem(__tm_addr)),
-         "r"(__as_b32(__new_val)) : "memory");),
-    (
-      // Unsupported architectures will have a linker error with a semi-decent error message
-      __cuda_ptx_tensormap_replace_rank_is_not_supported_before_SM_90a__();));
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM90_ALL || __CUDA_ARCH_FEAT_SM100_ALL \
+    || __CUDA_ARCH_FEAT_SM101_ALL
+  asm("tensormap.replace.tile.rank.global.b1024.b32 [%0], %1;"
+      :
+      : "l"(__as_ptr_gmem(__tm_addr)), "r"(__as_b32(__new_val))
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tensormap_replace_rank_is_not_supported_before_SM_90a_SM_100a_SM_101a__();
+#  endif
 }
 #endif // __cccl_ptx_isa >= 830
 
 /*
-// tensormap.replace.tile.rank.space.b1024.b32              [tm_addr], new_val; // PTX ISA 83, SM_90a
+// tensormap.replace.tile.rank.space.b1024.b32 [tm_addr], new_val; // PTX ISA 83, SM_90a, SM_100a, SM_101a
 // .space     = { .shared::cta }
-template <typename B32>
+template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
 __device__ static inline void tensormap_replace_rank(
   cuda::ptx::space_shared_t,
   void* tm_addr,
   B32 new_val);
 */
 #if __cccl_ptx_isa >= 830
-extern "C" _CCCL_DEVICE void __cuda_ptx_tensormap_replace_rank_is_not_supported_before_SM_90a__();
-template <typename _B32>
+extern "C" _CCCL_DEVICE void __cuda_ptx_tensormap_replace_rank_is_not_supported_before_SM_90a_SM_100a_SM_101a__();
+template <typename _B32, _CUDA_VSTD::enable_if_t<sizeof(_B32) == 4, bool> = true>
 _CCCL_DEVICE static inline void tensormap_replace_rank(space_shared_t, void* __tm_addr, _B32 __new_val)
 {
   // __space == space_shared (due to parameter type constraint)
   static_assert(sizeof(_B32) == 4, "");
-  NV_IF_ELSE_TARGET(
-    NV_HAS_FEATURE_SM_90a,
-    (asm("tensormap.replace.tile.rank.shared::cta.b1024.b32              [%0], %1;" : : "r"(__as_ptr_smem(__tm_addr)),
-         "r"(__as_b32(__new_val)) : "memory");),
-    (
-      // Unsupported architectures will have a linker error with a semi-decent error message
-      __cuda_ptx_tensormap_replace_rank_is_not_supported_before_SM_90a__();));
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM90_ALL || __CUDA_ARCH_FEAT_SM100_ALL \
+    || __CUDA_ARCH_FEAT_SM101_ALL
+  asm("tensormap.replace.tile.rank.shared::cta.b1024.b32 [%0], %1;"
+      :
+      : "r"(__as_ptr_smem(__tm_addr)), "r"(__as_b32(__new_val))
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tensormap_replace_rank_is_not_supported_before_SM_90a_SM_100a_SM_101a__();
+#  endif
 }
 #endif // __cccl_ptx_isa >= 830
 
 /*
-// tensormap.replace.tile.box_dim.space.b1024.b32           [tm_addr], ord, new_val; // PTX ISA 83, SM_90a
+// tensormap.replace.tile.box_dim.space.b1024.b32 [tm_addr], ord, new_val; // PTX ISA 83, SM_90a, SM_100a, SM_101a
 // .space     = { .global }
-template <int N32, typename B32>
+template <int N32, typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
 __device__ static inline void tensormap_replace_box_dim(
   cuda::ptx::space_global_t,
   void* tm_addr,
@@ -118,28 +132,30 @@ __device__ static inline void tensormap_replace_box_dim(
   B32 new_val);
 */
 #if __cccl_ptx_isa >= 830
-extern "C" _CCCL_DEVICE void __cuda_ptx_tensormap_replace_box_dim_is_not_supported_before_SM_90a__();
-template <int _N32, typename _B32>
+extern "C" _CCCL_DEVICE void __cuda_ptx_tensormap_replace_box_dim_is_not_supported_before_SM_90a_SM_100a_SM_101a__();
+template <int _N32, typename _B32, _CUDA_VSTD::enable_if_t<sizeof(_B32) == 4, bool> = true>
 _CCCL_DEVICE static inline void
 tensormap_replace_box_dim(space_global_t, void* __tm_addr, n32_t<_N32> __ord, _B32 __new_val)
 {
   // __space == space_global (due to parameter type constraint)
   static_assert(sizeof(_B32) == 4, "");
-  NV_IF_ELSE_TARGET(
-    NV_HAS_FEATURE_SM_90a,
-    (asm("tensormap.replace.tile.box_dim.global.b1024.b32           [%0], %1, %2;" : : "l"(__as_ptr_gmem(__tm_addr)),
-         "n"(__ord.value),
-         "r"(__as_b32(__new_val)) : "memory");),
-    (
-      // Unsupported architectures will have a linker error with a semi-decent error message
-      __cuda_ptx_tensormap_replace_box_dim_is_not_supported_before_SM_90a__();));
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM90_ALL || __CUDA_ARCH_FEAT_SM100_ALL \
+    || __CUDA_ARCH_FEAT_SM101_ALL
+  asm("tensormap.replace.tile.box_dim.global.b1024.b32 [%0], %1, %2;"
+      :
+      : "l"(__as_ptr_gmem(__tm_addr)), "n"(__ord.value), "r"(__as_b32(__new_val))
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tensormap_replace_box_dim_is_not_supported_before_SM_90a_SM_100a_SM_101a__();
+#  endif
 }
 #endif // __cccl_ptx_isa >= 830
 
 /*
-// tensormap.replace.tile.box_dim.space.b1024.b32           [tm_addr], ord, new_val; // PTX ISA 83, SM_90a
+// tensormap.replace.tile.box_dim.space.b1024.b32 [tm_addr], ord, new_val; // PTX ISA 83, SM_90a, SM_100a, SM_101a
 // .space     = { .shared::cta }
-template <int N32, typename B32>
+template <int N32, typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
 __device__ static inline void tensormap_replace_box_dim(
   cuda::ptx::space_shared_t,
   void* tm_addr,
@@ -147,29 +163,30 @@ __device__ static inline void tensormap_replace_box_dim(
   B32 new_val);
 */
 #if __cccl_ptx_isa >= 830
-extern "C" _CCCL_DEVICE void __cuda_ptx_tensormap_replace_box_dim_is_not_supported_before_SM_90a__();
-template <int _N32, typename _B32>
+extern "C" _CCCL_DEVICE void __cuda_ptx_tensormap_replace_box_dim_is_not_supported_before_SM_90a_SM_100a_SM_101a__();
+template <int _N32, typename _B32, _CUDA_VSTD::enable_if_t<sizeof(_B32) == 4, bool> = true>
 _CCCL_DEVICE static inline void
 tensormap_replace_box_dim(space_shared_t, void* __tm_addr, n32_t<_N32> __ord, _B32 __new_val)
 {
   // __space == space_shared (due to parameter type constraint)
   static_assert(sizeof(_B32) == 4, "");
-  NV_IF_ELSE_TARGET(
-    NV_HAS_FEATURE_SM_90a,
-    (asm(
-       "tensormap.replace.tile.box_dim.shared::cta.b1024.b32           [%0], %1, %2;" : : "r"(__as_ptr_smem(__tm_addr)),
-       "n"(__ord.value),
-       "r"(__as_b32(__new_val)) : "memory");),
-    (
-      // Unsupported architectures will have a linker error with a semi-decent error message
-      __cuda_ptx_tensormap_replace_box_dim_is_not_supported_before_SM_90a__();));
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM90_ALL || __CUDA_ARCH_FEAT_SM100_ALL \
+    || __CUDA_ARCH_FEAT_SM101_ALL
+  asm("tensormap.replace.tile.box_dim.shared::cta.b1024.b32 [%0], %1, %2;"
+      :
+      : "r"(__as_ptr_smem(__tm_addr)), "n"(__ord.value), "r"(__as_b32(__new_val))
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tensormap_replace_box_dim_is_not_supported_before_SM_90a_SM_100a_SM_101a__();
+#  endif
 }
 #endif // __cccl_ptx_isa >= 830
 
 /*
-// tensormap.replace.tile.global_dim.space.b1024.b32        [tm_addr], ord, new_val; // PTX ISA 83, SM_90a
+// tensormap.replace.tile.global_dim.space.b1024.b32 [tm_addr], ord, new_val; // PTX ISA 83, SM_90a, SM_100a, SM_101a
 // .space     = { .global }
-template <int N32, typename B32>
+template <int N32, typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
 __device__ static inline void tensormap_replace_global_dim(
   cuda::ptx::space_global_t,
   void* tm_addr,
@@ -177,28 +194,30 @@ __device__ static inline void tensormap_replace_global_dim(
   B32 new_val);
 */
 #if __cccl_ptx_isa >= 830
-extern "C" _CCCL_DEVICE void __cuda_ptx_tensormap_replace_global_dim_is_not_supported_before_SM_90a__();
-template <int _N32, typename _B32>
+extern "C" _CCCL_DEVICE void __cuda_ptx_tensormap_replace_global_dim_is_not_supported_before_SM_90a_SM_100a_SM_101a__();
+template <int _N32, typename _B32, _CUDA_VSTD::enable_if_t<sizeof(_B32) == 4, bool> = true>
 _CCCL_DEVICE static inline void
 tensormap_replace_global_dim(space_global_t, void* __tm_addr, n32_t<_N32> __ord, _B32 __new_val)
 {
   // __space == space_global (due to parameter type constraint)
   static_assert(sizeof(_B32) == 4, "");
-  NV_IF_ELSE_TARGET(
-    NV_HAS_FEATURE_SM_90a,
-    (asm("tensormap.replace.tile.global_dim.global.b1024.b32        [%0], %1, %2;" : : "l"(__as_ptr_gmem(__tm_addr)),
-         "n"(__ord.value),
-         "r"(__as_b32(__new_val)) : "memory");),
-    (
-      // Unsupported architectures will have a linker error with a semi-decent error message
-      __cuda_ptx_tensormap_replace_global_dim_is_not_supported_before_SM_90a__();));
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM90_ALL || __CUDA_ARCH_FEAT_SM100_ALL \
+    || __CUDA_ARCH_FEAT_SM101_ALL
+  asm("tensormap.replace.tile.global_dim.global.b1024.b32 [%0], %1, %2;"
+      :
+      : "l"(__as_ptr_gmem(__tm_addr)), "n"(__ord.value), "r"(__as_b32(__new_val))
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tensormap_replace_global_dim_is_not_supported_before_SM_90a_SM_100a_SM_101a__();
+#  endif
 }
 #endif // __cccl_ptx_isa >= 830
 
 /*
-// tensormap.replace.tile.global_dim.space.b1024.b32        [tm_addr], ord, new_val; // PTX ISA 83, SM_90a
+// tensormap.replace.tile.global_dim.space.b1024.b32 [tm_addr], ord, new_val; // PTX ISA 83, SM_90a, SM_100a, SM_101a
 // .space     = { .shared::cta }
-template <int N32, typename B32>
+template <int N32, typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
 __device__ static inline void tensormap_replace_global_dim(
   cuda::ptx::space_shared_t,
   void* tm_addr,
@@ -206,29 +225,30 @@ __device__ static inline void tensormap_replace_global_dim(
   B32 new_val);
 */
 #if __cccl_ptx_isa >= 830
-extern "C" _CCCL_DEVICE void __cuda_ptx_tensormap_replace_global_dim_is_not_supported_before_SM_90a__();
-template <int _N32, typename _B32>
+extern "C" _CCCL_DEVICE void __cuda_ptx_tensormap_replace_global_dim_is_not_supported_before_SM_90a_SM_100a_SM_101a__();
+template <int _N32, typename _B32, _CUDA_VSTD::enable_if_t<sizeof(_B32) == 4, bool> = true>
 _CCCL_DEVICE static inline void
 tensormap_replace_global_dim(space_shared_t, void* __tm_addr, n32_t<_N32> __ord, _B32 __new_val)
 {
   // __space == space_shared (due to parameter type constraint)
   static_assert(sizeof(_B32) == 4, "");
-  NV_IF_ELSE_TARGET(
-    NV_HAS_FEATURE_SM_90a,
-    (asm(
-       "tensormap.replace.tile.global_dim.shared::cta.b1024.b32        [%0], %1, %2;" : : "r"(__as_ptr_smem(__tm_addr)),
-       "n"(__ord.value),
-       "r"(__as_b32(__new_val)) : "memory");),
-    (
-      // Unsupported architectures will have a linker error with a semi-decent error message
-      __cuda_ptx_tensormap_replace_global_dim_is_not_supported_before_SM_90a__();));
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM90_ALL || __CUDA_ARCH_FEAT_SM100_ALL \
+    || __CUDA_ARCH_FEAT_SM101_ALL
+  asm("tensormap.replace.tile.global_dim.shared::cta.b1024.b32 [%0], %1, %2;"
+      :
+      : "r"(__as_ptr_smem(__tm_addr)), "n"(__ord.value), "r"(__as_b32(__new_val))
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tensormap_replace_global_dim_is_not_supported_before_SM_90a_SM_100a_SM_101a__();
+#  endif
 }
 #endif // __cccl_ptx_isa >= 830
 
 /*
-// tensormap.replace.tile.global_stride.space.b1024.b64     [tm_addr], ord, new_val; // PTX ISA 83, SM_90a
+// tensormap.replace.tile.global_stride.space.b1024.b64 [tm_addr], ord, new_val; // PTX ISA 83, SM_90a, SM_100a, SM_101a
 // .space     = { .global }
-template <int N32, typename B64>
+template <int N32, typename B64, enable_if_t<sizeof(B64) == 8, bool> = true>
 __device__ static inline void tensormap_replace_global_stride(
   cuda::ptx::space_global_t,
   void* tm_addr,
@@ -236,28 +256,31 @@ __device__ static inline void tensormap_replace_global_stride(
   B64 new_val);
 */
 #if __cccl_ptx_isa >= 830
-extern "C" _CCCL_DEVICE void __cuda_ptx_tensormap_replace_global_stride_is_not_supported_before_SM_90a__();
-template <int _N32, typename _B64>
+extern "C" _CCCL_DEVICE void
+__cuda_ptx_tensormap_replace_global_stride_is_not_supported_before_SM_90a_SM_100a_SM_101a__();
+template <int _N32, typename _B64, _CUDA_VSTD::enable_if_t<sizeof(_B64) == 8, bool> = true>
 _CCCL_DEVICE static inline void
 tensormap_replace_global_stride(space_global_t, void* __tm_addr, n32_t<_N32> __ord, _B64 __new_val)
 {
   // __space == space_global (due to parameter type constraint)
   static_assert(sizeof(_B64) == 8, "");
-  NV_IF_ELSE_TARGET(
-    NV_HAS_FEATURE_SM_90a,
-    (asm("tensormap.replace.tile.global_stride.global.b1024.b64     [%0], %1, %2;" : : "l"(__as_ptr_gmem(__tm_addr)),
-         "n"(__ord.value),
-         "l"(__as_b64(__new_val)) : "memory");),
-    (
-      // Unsupported architectures will have a linker error with a semi-decent error message
-      __cuda_ptx_tensormap_replace_global_stride_is_not_supported_before_SM_90a__();));
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM90_ALL || __CUDA_ARCH_FEAT_SM100_ALL \
+    || __CUDA_ARCH_FEAT_SM101_ALL
+  asm("tensormap.replace.tile.global_stride.global.b1024.b64 [%0], %1, %2;"
+      :
+      : "l"(__as_ptr_gmem(__tm_addr)), "n"(__ord.value), "l"(__as_b64(__new_val))
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tensormap_replace_global_stride_is_not_supported_before_SM_90a_SM_100a_SM_101a__();
+#  endif
 }
 #endif // __cccl_ptx_isa >= 830
 
 /*
-// tensormap.replace.tile.global_stride.space.b1024.b64     [tm_addr], ord, new_val; // PTX ISA 83, SM_90a
+// tensormap.replace.tile.global_stride.space.b1024.b64 [tm_addr], ord, new_val; // PTX ISA 83, SM_90a, SM_100a, SM_101a
 // .space     = { .shared::cta }
-template <int N32, typename B64>
+template <int N32, typename B64, enable_if_t<sizeof(B64) == 8, bool> = true>
 __device__ static inline void tensormap_replace_global_stride(
   cuda::ptx::space_shared_t,
   void* tm_addr,
@@ -265,29 +288,98 @@ __device__ static inline void tensormap_replace_global_stride(
   B64 new_val);
 */
 #if __cccl_ptx_isa >= 830
-extern "C" _CCCL_DEVICE void __cuda_ptx_tensormap_replace_global_stride_is_not_supported_before_SM_90a__();
-template <int _N32, typename _B64>
+extern "C" _CCCL_DEVICE void
+__cuda_ptx_tensormap_replace_global_stride_is_not_supported_before_SM_90a_SM_100a_SM_101a__();
+template <int _N32, typename _B64, _CUDA_VSTD::enable_if_t<sizeof(_B64) == 8, bool> = true>
 _CCCL_DEVICE static inline void
 tensormap_replace_global_stride(space_shared_t, void* __tm_addr, n32_t<_N32> __ord, _B64 __new_val)
 {
   // __space == space_shared (due to parameter type constraint)
   static_assert(sizeof(_B64) == 8, "");
-  NV_IF_ELSE_TARGET(
-    NV_HAS_FEATURE_SM_90a,
-    (asm(
-       "tensormap.replace.tile.global_stride.shared::cta.b1024.b64     [%0], %1, %2;" : : "r"(__as_ptr_smem(__tm_addr)),
-       "n"(__ord.value),
-       "l"(__as_b64(__new_val)) : "memory");),
-    (
-      // Unsupported architectures will have a linker error with a semi-decent error message
-      __cuda_ptx_tensormap_replace_global_stride_is_not_supported_before_SM_90a__();));
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM90_ALL || __CUDA_ARCH_FEAT_SM100_ALL \
+    || __CUDA_ARCH_FEAT_SM101_ALL
+  asm("tensormap.replace.tile.global_stride.shared::cta.b1024.b64 [%0], %1, %2;"
+      :
+      : "r"(__as_ptr_smem(__tm_addr)), "n"(__ord.value), "l"(__as_b64(__new_val))
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tensormap_replace_global_stride_is_not_supported_before_SM_90a_SM_100a_SM_101a__();
+#  endif
 }
 #endif // __cccl_ptx_isa >= 830
 
 /*
-// tensormap.replace.tile.element_stride.space.b1024.b32    [tm_addr], ord, new_val; // PTX ISA 83, SM_90a
+// tensormap.replace.tile.element_stride.space.b1024.b32 [tm_addr], ord, new_val; // PTX ISA 83, SM_90a, SM_100a,
+SM_101a
 // .space     = { .global }
-template <int N32, typename B32>
+template <int N32, typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+__device__ static inline void tensormap_replace_element_stride(
+  cuda::ptx::space_global_t,
+  void* tm_addr,
+  cuda::ptx::n32_t<N32> ord,
+  B32 new_val);
+*/
+#if __cccl_ptx_isa >= 830
+extern "C" _CCCL_DEVICE void
+__cuda_ptx_tensormap_replace_element_stride_is_not_supported_before_SM_90a_SM_100a_SM_101a__();
+template <int _N32, typename _B32, _CUDA_VSTD::enable_if_t<sizeof(_B32) == 4, bool> = true>
+_CCCL_DEVICE static inline void
+tensormap_replace_element_stride(space_global_t, void* __tm_addr, n32_t<_N32> __ord, _B32 __new_val)
+{
+  // __space == space_global (due to parameter type constraint)
+  static_assert(sizeof(_B32) == 4, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM90_ALL || __CUDA_ARCH_FEAT_SM100_ALL \
+    || __CUDA_ARCH_FEAT_SM101_ALL
+  asm("tensormap.replace.tile.element_stride.global.b1024.b32 [%0], %1, %2;"
+      :
+      : "l"(__as_ptr_gmem(__tm_addr)), "n"(__ord.value), "r"(__as_b32(__new_val))
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tensormap_replace_element_stride_is_not_supported_before_SM_90a_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 830
+
+/*
+// tensormap.replace.tile.element_stride.space.b1024.b32 [tm_addr], ord, new_val; // PTX ISA 83, SM_90a, SM_100a,
+SM_101a
+// .space     = { .shared::cta }
+template <int N32, typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
+__device__ static inline void tensormap_replace_element_stride(
+  cuda::ptx::space_shared_t,
+  void* tm_addr,
+  cuda::ptx::n32_t<N32> ord,
+  B32 new_val);
+*/
+#if __cccl_ptx_isa >= 830
+extern "C" _CCCL_DEVICE void
+__cuda_ptx_tensormap_replace_element_stride_is_not_supported_before_SM_90a_SM_100a_SM_101a__();
+template <int _N32, typename _B32, _CUDA_VSTD::enable_if_t<sizeof(_B32) == 4, bool> = true>
+_CCCL_DEVICE static inline void
+tensormap_replace_element_stride(space_shared_t, void* __tm_addr, n32_t<_N32> __ord, _B32 __new_val)
+{
+  // __space == space_shared (due to parameter type constraint)
+  static_assert(sizeof(_B32) == 4, "");
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM90_ALL || __CUDA_ARCH_FEAT_SM100_ALL \
+    || __CUDA_ARCH_FEAT_SM101_ALL
+  asm("tensormap.replace.tile.element_stride.shared::cta.b1024.b32 [%0], %1, %2;"
+      :
+      : "r"(__as_ptr_smem(__tm_addr)), "n"(__ord.value), "r"(__as_b32(__new_val))
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tensormap_replace_element_stride_is_not_supported_before_SM_90a_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 830
+
+/*
+// tensormap.replace.tile.element_stride.space.b1024.b32 [tm_addr], ord, new_val; // PTX ISA 83, SM_90a, SM_100a,
+SM_101a
+// .space     = { .global }
+template <int N32, typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
 __device__ static inline void tensormap_replace_element_size(
   cuda::ptx::space_global_t,
   void* tm_addr,
@@ -295,28 +387,32 @@ __device__ static inline void tensormap_replace_element_size(
   B32 new_val);
 */
 #if __cccl_ptx_isa >= 830
-extern "C" _CCCL_DEVICE void __cuda_ptx_tensormap_replace_element_size_is_not_supported_before_SM_90a__();
-template <int _N32, typename _B32>
+extern "C" _CCCL_DEVICE void
+__cuda_ptx_tensormap_replace_element_size_is_not_supported_before_SM_90a_SM_100a_SM_101a__();
+template <int _N32, typename _B32, _CUDA_VSTD::enable_if_t<sizeof(_B32) == 4, bool> = true>
 _CCCL_DEVICE static inline void
 tensormap_replace_element_size(space_global_t, void* __tm_addr, n32_t<_N32> __ord, _B32 __new_val)
 {
   // __space == space_global (due to parameter type constraint)
   static_assert(sizeof(_B32) == 4, "");
-  NV_IF_ELSE_TARGET(
-    NV_HAS_FEATURE_SM_90a,
-    (asm("tensormap.replace.tile.element_stride.global.b1024.b32    [%0], %1, %2;" : : "l"(__as_ptr_gmem(__tm_addr)),
-         "n"(__ord.value),
-         "r"(__as_b32(__new_val)) : "memory");),
-    (
-      // Unsupported architectures will have a linker error with a semi-decent error message
-      __cuda_ptx_tensormap_replace_element_size_is_not_supported_before_SM_90a__();));
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM90_ALL || __CUDA_ARCH_FEAT_SM100_ALL \
+    || __CUDA_ARCH_FEAT_SM101_ALL
+  asm("tensormap.replace.tile.element_stride.global.b1024.b32 [%0], %1, %2;"
+      :
+      : "l"(__as_ptr_gmem(__tm_addr)), "n"(__ord.value), "r"(__as_b32(__new_val))
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tensormap_replace_element_size_is_not_supported_before_SM_90a_SM_100a_SM_101a__();
+#  endif
 }
 #endif // __cccl_ptx_isa >= 830
 
 /*
-// tensormap.replace.tile.element_stride.space.b1024.b32    [tm_addr], ord, new_val; // PTX ISA 83, SM_90a
+// tensormap.replace.tile.element_stride.space.b1024.b32 [tm_addr], ord, new_val; // PTX ISA 83, SM_90a, SM_100a,
+SM_101a
 // .space     = { .shared::cta }
-template <int N32, typename B32>
+template <int N32, typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
 __device__ static inline void tensormap_replace_element_size(
   cuda::ptx::space_shared_t,
   void* tm_addr,
@@ -324,27 +420,29 @@ __device__ static inline void tensormap_replace_element_size(
   B32 new_val);
 */
 #if __cccl_ptx_isa >= 830
-extern "C" _CCCL_DEVICE void __cuda_ptx_tensormap_replace_element_size_is_not_supported_before_SM_90a__();
-template <int _N32, typename _B32>
+extern "C" _CCCL_DEVICE void
+__cuda_ptx_tensormap_replace_element_size_is_not_supported_before_SM_90a_SM_100a_SM_101a__();
+template <int _N32, typename _B32, _CUDA_VSTD::enable_if_t<sizeof(_B32) == 4, bool> = true>
 _CCCL_DEVICE static inline void
 tensormap_replace_element_size(space_shared_t, void* __tm_addr, n32_t<_N32> __ord, _B32 __new_val)
 {
   // __space == space_shared (due to parameter type constraint)
   static_assert(sizeof(_B32) == 4, "");
-  NV_IF_ELSE_TARGET(
-    NV_HAS_FEATURE_SM_90a,
-    (asm(
-       "tensormap.replace.tile.element_stride.shared::cta.b1024.b32    [%0], %1, %2;" : : "r"(__as_ptr_smem(__tm_addr)),
-       "n"(__ord.value),
-       "r"(__as_b32(__new_val)) : "memory");),
-    (
-      // Unsupported architectures will have a linker error with a semi-decent error message
-      __cuda_ptx_tensormap_replace_element_size_is_not_supported_before_SM_90a__();));
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM90_ALL || __CUDA_ARCH_FEAT_SM100_ALL \
+    || __CUDA_ARCH_FEAT_SM101_ALL
+  asm("tensormap.replace.tile.element_stride.shared::cta.b1024.b32 [%0], %1, %2;"
+      :
+      : "r"(__as_ptr_smem(__tm_addr)), "n"(__ord.value), "r"(__as_b32(__new_val))
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tensormap_replace_element_size_is_not_supported_before_SM_90a_SM_100a_SM_101a__();
+#  endif
 }
 #endif // __cccl_ptx_isa >= 830
 
 /*
-// tensormap.replace.tile.elemtype.space.b1024.b32          [tm_addr], new_val; // PTX ISA 83, SM_90a
+// tensormap.replace.tile.elemtype.space.b1024.b32 [tm_addr], new_val; // PTX ISA 83, SM_90a, SM_100a, SM_101a
 // .space     = { .global }
 template <int N32>
 __device__ static inline void tensormap_replace_elemtype(
@@ -353,23 +451,26 @@ __device__ static inline void tensormap_replace_elemtype(
   cuda::ptx::n32_t<N32> new_val);
 */
 #if __cccl_ptx_isa >= 830
-extern "C" _CCCL_DEVICE void __cuda_ptx_tensormap_replace_elemtype_is_not_supported_before_SM_90a__();
+extern "C" _CCCL_DEVICE void __cuda_ptx_tensormap_replace_elemtype_is_not_supported_before_SM_90a_SM_100a_SM_101a__();
 template <int _N32>
 _CCCL_DEVICE static inline void tensormap_replace_elemtype(space_global_t, void* __tm_addr, n32_t<_N32> __new_val)
 {
-  // __space == space_global (due to parameter type constraint)
-  NV_IF_ELSE_TARGET(
-    NV_HAS_FEATURE_SM_90a,
-    (asm("tensormap.replace.tile.elemtype.global.b1024.b32          [%0], %1;" : : "l"(__as_ptr_gmem(__tm_addr)),
-         "n"(__new_val.value) : "memory");),
-    (
-      // Unsupported architectures will have a linker error with a semi-decent error message
-      __cuda_ptx_tensormap_replace_elemtype_is_not_supported_before_SM_90a__();));
+// __space == space_global (due to parameter type constraint)
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM90_ALL || __CUDA_ARCH_FEAT_SM100_ALL \
+    || __CUDA_ARCH_FEAT_SM101_ALL
+  asm("tensormap.replace.tile.elemtype.global.b1024.b32 [%0], %1;"
+      :
+      : "l"(__as_ptr_gmem(__tm_addr)), "n"(__new_val.value)
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tensormap_replace_elemtype_is_not_supported_before_SM_90a_SM_100a_SM_101a__();
+#  endif
 }
 #endif // __cccl_ptx_isa >= 830
 
 /*
-// tensormap.replace.tile.elemtype.space.b1024.b32          [tm_addr], new_val; // PTX ISA 83, SM_90a
+// tensormap.replace.tile.elemtype.space.b1024.b32 [tm_addr], new_val; // PTX ISA 83, SM_90a, SM_100a, SM_101a
 // .space     = { .shared::cta }
 template <int N32>
 __device__ static inline void tensormap_replace_elemtype(
@@ -378,23 +479,26 @@ __device__ static inline void tensormap_replace_elemtype(
   cuda::ptx::n32_t<N32> new_val);
 */
 #if __cccl_ptx_isa >= 830
-extern "C" _CCCL_DEVICE void __cuda_ptx_tensormap_replace_elemtype_is_not_supported_before_SM_90a__();
+extern "C" _CCCL_DEVICE void __cuda_ptx_tensormap_replace_elemtype_is_not_supported_before_SM_90a_SM_100a_SM_101a__();
 template <int _N32>
 _CCCL_DEVICE static inline void tensormap_replace_elemtype(space_shared_t, void* __tm_addr, n32_t<_N32> __new_val)
 {
-  // __space == space_shared (due to parameter type constraint)
-  NV_IF_ELSE_TARGET(
-    NV_HAS_FEATURE_SM_90a,
-    (asm("tensormap.replace.tile.elemtype.shared::cta.b1024.b32          [%0], %1;" : : "r"(__as_ptr_smem(__tm_addr)),
-         "n"(__new_val.value) : "memory");),
-    (
-      // Unsupported architectures will have a linker error with a semi-decent error message
-      __cuda_ptx_tensormap_replace_elemtype_is_not_supported_before_SM_90a__();));
+// __space == space_shared (due to parameter type constraint)
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM90_ALL || __CUDA_ARCH_FEAT_SM100_ALL \
+    || __CUDA_ARCH_FEAT_SM101_ALL
+  asm("tensormap.replace.tile.elemtype.shared::cta.b1024.b32 [%0], %1;"
+      :
+      : "r"(__as_ptr_smem(__tm_addr)), "n"(__new_val.value)
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tensormap_replace_elemtype_is_not_supported_before_SM_90a_SM_100a_SM_101a__();
+#  endif
 }
 #endif // __cccl_ptx_isa >= 830
 
 /*
-// tensormap.replace.tile.interleave_layout.space.b1024.b32 [tm_addr], new_val; // PTX ISA 83, SM_90a
+// tensormap.replace.tile.interleave_layout.space.b1024.b32 [tm_addr], new_val; // PTX ISA 83, SM_90a, SM_100a, SM_101a
 // .space     = { .global }
 template <int N32>
 __device__ static inline void tensormap_replace_interleave_layout(
@@ -403,24 +507,28 @@ __device__ static inline void tensormap_replace_interleave_layout(
   cuda::ptx::n32_t<N32> new_val);
 */
 #if __cccl_ptx_isa >= 830
-extern "C" _CCCL_DEVICE void __cuda_ptx_tensormap_replace_interleave_layout_is_not_supported_before_SM_90a__();
+extern "C" _CCCL_DEVICE void
+__cuda_ptx_tensormap_replace_interleave_layout_is_not_supported_before_SM_90a_SM_100a_SM_101a__();
 template <int _N32>
 _CCCL_DEVICE static inline void
 tensormap_replace_interleave_layout(space_global_t, void* __tm_addr, n32_t<_N32> __new_val)
 {
-  // __space == space_global (due to parameter type constraint)
-  NV_IF_ELSE_TARGET(
-    NV_HAS_FEATURE_SM_90a,
-    (asm("tensormap.replace.tile.interleave_layout.global.b1024.b32 [%0], %1;" : : "l"(__as_ptr_gmem(__tm_addr)),
-         "n"(__new_val.value) : "memory");),
-    (
-      // Unsupported architectures will have a linker error with a semi-decent error message
-      __cuda_ptx_tensormap_replace_interleave_layout_is_not_supported_before_SM_90a__();));
+// __space == space_global (due to parameter type constraint)
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM90_ALL || __CUDA_ARCH_FEAT_SM100_ALL \
+    || __CUDA_ARCH_FEAT_SM101_ALL
+  asm("tensormap.replace.tile.interleave_layout.global.b1024.b32 [%0], %1;"
+      :
+      : "l"(__as_ptr_gmem(__tm_addr)), "n"(__new_val.value)
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tensormap_replace_interleave_layout_is_not_supported_before_SM_90a_SM_100a_SM_101a__();
+#  endif
 }
 #endif // __cccl_ptx_isa >= 830
 
 /*
-// tensormap.replace.tile.interleave_layout.space.b1024.b32 [tm_addr], new_val; // PTX ISA 83, SM_90a
+// tensormap.replace.tile.interleave_layout.space.b1024.b32 [tm_addr], new_val; // PTX ISA 83, SM_90a, SM_100a, SM_101a
 // .space     = { .shared::cta }
 template <int N32>
 __device__ static inline void tensormap_replace_interleave_layout(
@@ -429,24 +537,28 @@ __device__ static inline void tensormap_replace_interleave_layout(
   cuda::ptx::n32_t<N32> new_val);
 */
 #if __cccl_ptx_isa >= 830
-extern "C" _CCCL_DEVICE void __cuda_ptx_tensormap_replace_interleave_layout_is_not_supported_before_SM_90a__();
+extern "C" _CCCL_DEVICE void
+__cuda_ptx_tensormap_replace_interleave_layout_is_not_supported_before_SM_90a_SM_100a_SM_101a__();
 template <int _N32>
 _CCCL_DEVICE static inline void
 tensormap_replace_interleave_layout(space_shared_t, void* __tm_addr, n32_t<_N32> __new_val)
 {
-  // __space == space_shared (due to parameter type constraint)
-  NV_IF_ELSE_TARGET(
-    NV_HAS_FEATURE_SM_90a,
-    (asm("tensormap.replace.tile.interleave_layout.shared::cta.b1024.b32 [%0], %1;" : : "r"(__as_ptr_smem(__tm_addr)),
-         "n"(__new_val.value) : "memory");),
-    (
-      // Unsupported architectures will have a linker error with a semi-decent error message
-      __cuda_ptx_tensormap_replace_interleave_layout_is_not_supported_before_SM_90a__();));
+// __space == space_shared (due to parameter type constraint)
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM90_ALL || __CUDA_ARCH_FEAT_SM100_ALL \
+    || __CUDA_ARCH_FEAT_SM101_ALL
+  asm("tensormap.replace.tile.interleave_layout.shared::cta.b1024.b32 [%0], %1;"
+      :
+      : "r"(__as_ptr_smem(__tm_addr)), "n"(__new_val.value)
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tensormap_replace_interleave_layout_is_not_supported_before_SM_90a_SM_100a_SM_101a__();
+#  endif
 }
 #endif // __cccl_ptx_isa >= 830
 
 /*
-// tensormap.replace.tile.swizzle_mode.space.b1024.b32      [tm_addr], new_val; // PTX ISA 83, SM_90a
+// tensormap.replace.tile.swizzle_mode.space.b1024.b32 [tm_addr], new_val; // PTX ISA 83, SM_90a, SM_100a, SM_101a
 // .space     = { .global }
 template <int N32>
 __device__ static inline void tensormap_replace_swizzle_mode(
@@ -455,23 +567,27 @@ __device__ static inline void tensormap_replace_swizzle_mode(
   cuda::ptx::n32_t<N32> new_val);
 */
 #if __cccl_ptx_isa >= 830
-extern "C" _CCCL_DEVICE void __cuda_ptx_tensormap_replace_swizzle_mode_is_not_supported_before_SM_90a__();
+extern "C" _CCCL_DEVICE void
+__cuda_ptx_tensormap_replace_swizzle_mode_is_not_supported_before_SM_90a_SM_100a_SM_101a__();
 template <int _N32>
 _CCCL_DEVICE static inline void tensormap_replace_swizzle_mode(space_global_t, void* __tm_addr, n32_t<_N32> __new_val)
 {
-  // __space == space_global (due to parameter type constraint)
-  NV_IF_ELSE_TARGET(
-    NV_HAS_FEATURE_SM_90a,
-    (asm("tensormap.replace.tile.swizzle_mode.global.b1024.b32      [%0], %1;" : : "l"(__as_ptr_gmem(__tm_addr)),
-         "n"(__new_val.value) : "memory");),
-    (
-      // Unsupported architectures will have a linker error with a semi-decent error message
-      __cuda_ptx_tensormap_replace_swizzle_mode_is_not_supported_before_SM_90a__();));
+// __space == space_global (due to parameter type constraint)
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM90_ALL || __CUDA_ARCH_FEAT_SM100_ALL \
+    || __CUDA_ARCH_FEAT_SM101_ALL
+  asm("tensormap.replace.tile.swizzle_mode.global.b1024.b32 [%0], %1;"
+      :
+      : "l"(__as_ptr_gmem(__tm_addr)), "n"(__new_val.value)
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tensormap_replace_swizzle_mode_is_not_supported_before_SM_90a_SM_100a_SM_101a__();
+#  endif
 }
 #endif // __cccl_ptx_isa >= 830
 
 /*
-// tensormap.replace.tile.swizzle_mode.space.b1024.b32      [tm_addr], new_val; // PTX ISA 83, SM_90a
+// tensormap.replace.tile.swizzle_mode.space.b1024.b32 [tm_addr], new_val; // PTX ISA 83, SM_90a, SM_100a, SM_101a
 // .space     = { .shared::cta }
 template <int N32>
 __device__ static inline void tensormap_replace_swizzle_mode(
@@ -480,23 +596,27 @@ __device__ static inline void tensormap_replace_swizzle_mode(
   cuda::ptx::n32_t<N32> new_val);
 */
 #if __cccl_ptx_isa >= 830
-extern "C" _CCCL_DEVICE void __cuda_ptx_tensormap_replace_swizzle_mode_is_not_supported_before_SM_90a__();
+extern "C" _CCCL_DEVICE void
+__cuda_ptx_tensormap_replace_swizzle_mode_is_not_supported_before_SM_90a_SM_100a_SM_101a__();
 template <int _N32>
 _CCCL_DEVICE static inline void tensormap_replace_swizzle_mode(space_shared_t, void* __tm_addr, n32_t<_N32> __new_val)
 {
-  // __space == space_shared (due to parameter type constraint)
-  NV_IF_ELSE_TARGET(
-    NV_HAS_FEATURE_SM_90a,
-    (asm("tensormap.replace.tile.swizzle_mode.shared::cta.b1024.b32      [%0], %1;" : : "r"(__as_ptr_smem(__tm_addr)),
-         "n"(__new_val.value) : "memory");),
-    (
-      // Unsupported architectures will have a linker error with a semi-decent error message
-      __cuda_ptx_tensormap_replace_swizzle_mode_is_not_supported_before_SM_90a__();));
+// __space == space_shared (due to parameter type constraint)
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM90_ALL || __CUDA_ARCH_FEAT_SM100_ALL \
+    || __CUDA_ARCH_FEAT_SM101_ALL
+  asm("tensormap.replace.tile.swizzle_mode.shared::cta.b1024.b32 [%0], %1;"
+      :
+      : "r"(__as_ptr_smem(__tm_addr)), "n"(__new_val.value)
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tensormap_replace_swizzle_mode_is_not_supported_before_SM_90a_SM_100a_SM_101a__();
+#  endif
 }
 #endif // __cccl_ptx_isa >= 830
 
 /*
-// tensormap.replace.tile.fill_mode.space.b1024.b32         [tm_addr], new_val; // PTX ISA 83, SM_90a
+// tensormap.replace.tile.fill_mode.space.b1024.b32 [tm_addr], new_val; // PTX ISA 83, SM_90a, SM_100a, SM_101a
 // .space     = { .global }
 template <int N32>
 __device__ static inline void tensormap_replace_fill_mode(
@@ -505,23 +625,26 @@ __device__ static inline void tensormap_replace_fill_mode(
   cuda::ptx::n32_t<N32> new_val);
 */
 #if __cccl_ptx_isa >= 830
-extern "C" _CCCL_DEVICE void __cuda_ptx_tensormap_replace_fill_mode_is_not_supported_before_SM_90a__();
+extern "C" _CCCL_DEVICE void __cuda_ptx_tensormap_replace_fill_mode_is_not_supported_before_SM_90a_SM_100a_SM_101a__();
 template <int _N32>
 _CCCL_DEVICE static inline void tensormap_replace_fill_mode(space_global_t, void* __tm_addr, n32_t<_N32> __new_val)
 {
-  // __space == space_global (due to parameter type constraint)
-  NV_IF_ELSE_TARGET(
-    NV_HAS_FEATURE_SM_90a,
-    (asm("tensormap.replace.tile.fill_mode.global.b1024.b32         [%0], %1;" : : "l"(__as_ptr_gmem(__tm_addr)),
-         "n"(__new_val.value) : "memory");),
-    (
-      // Unsupported architectures will have a linker error with a semi-decent error message
-      __cuda_ptx_tensormap_replace_fill_mode_is_not_supported_before_SM_90a__();));
+// __space == space_global (due to parameter type constraint)
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM90_ALL || __CUDA_ARCH_FEAT_SM100_ALL \
+    || __CUDA_ARCH_FEAT_SM101_ALL
+  asm("tensormap.replace.tile.fill_mode.global.b1024.b32 [%0], %1;"
+      :
+      : "l"(__as_ptr_gmem(__tm_addr)), "n"(__new_val.value)
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tensormap_replace_fill_mode_is_not_supported_before_SM_90a_SM_100a_SM_101a__();
+#  endif
 }
 #endif // __cccl_ptx_isa >= 830
 
 /*
-// tensormap.replace.tile.fill_mode.space.b1024.b32         [tm_addr], new_val; // PTX ISA 83, SM_90a
+// tensormap.replace.tile.fill_mode.space.b1024.b32 [tm_addr], new_val; // PTX ISA 83, SM_90a, SM_100a, SM_101a
 // .space     = { .shared::cta }
 template <int N32>
 __device__ static inline void tensormap_replace_fill_mode(
@@ -530,19 +653,78 @@ __device__ static inline void tensormap_replace_fill_mode(
   cuda::ptx::n32_t<N32> new_val);
 */
 #if __cccl_ptx_isa >= 830
-extern "C" _CCCL_DEVICE void __cuda_ptx_tensormap_replace_fill_mode_is_not_supported_before_SM_90a__();
+extern "C" _CCCL_DEVICE void __cuda_ptx_tensormap_replace_fill_mode_is_not_supported_before_SM_90a_SM_100a_SM_101a__();
 template <int _N32>
 _CCCL_DEVICE static inline void tensormap_replace_fill_mode(space_shared_t, void* __tm_addr, n32_t<_N32> __new_val)
 {
-  // __space == space_shared (due to parameter type constraint)
-  NV_IF_ELSE_TARGET(
-    NV_HAS_FEATURE_SM_90a,
-    (asm("tensormap.replace.tile.fill_mode.shared::cta.b1024.b32         [%0], %1;" : : "r"(__as_ptr_smem(__tm_addr)),
-         "n"(__new_val.value) : "memory");),
-    (
-      // Unsupported architectures will have a linker error with a semi-decent error message
-      __cuda_ptx_tensormap_replace_fill_mode_is_not_supported_before_SM_90a__();));
+// __space == space_shared (due to parameter type constraint)
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM90_ALL || __CUDA_ARCH_FEAT_SM100_ALL \
+    || __CUDA_ARCH_FEAT_SM101_ALL
+  asm("tensormap.replace.tile.fill_mode.shared::cta.b1024.b32 [%0], %1;"
+      :
+      : "r"(__as_ptr_smem(__tm_addr)), "n"(__new_val.value)
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tensormap_replace_fill_mode_is_not_supported_before_SM_90a_SM_100a_SM_101a__();
+#  endif
 }
 #endif // __cccl_ptx_isa >= 830
 
+/*
+// tensormap.replace.tile.swizzle_atomicity.space.b1024.b32 [tm_addr], new_val; // PTX ISA 86, SM_100a, SM_101a
+// .space     = { .global }
+template <int N32>
+__device__ static inline void tensormap_replace_swizzle_atomicity(
+  cuda::ptx::space_global_t,
+  void* tm_addr,
+  cuda::ptx::n32_t<N32> new_val);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tensormap_replace_swizzle_atomicity_is_not_supported_before_SM_100a_SM_101a__();
+template <int _N32>
+_CCCL_DEVICE static inline void
+tensormap_replace_swizzle_atomicity(space_global_t, void* __tm_addr, n32_t<_N32> __new_val)
+{
+// __space == space_global (due to parameter type constraint)
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  asm("tensormap.replace.tile.swizzle_atomicity.global.b1024.b32 [%0], %1;"
+      :
+      : "l"(__as_ptr_gmem(__tm_addr)), "n"(__new_val.value)
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tensormap_replace_swizzle_atomicity_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
+/*
+// tensormap.replace.tile.swizzle_atomicity.space.b1024.b32 [tm_addr], new_val; // PTX ISA 86, SM_100a, SM_101a
+// .space     = { .shared::cta }
+template <int N32>
+__device__ static inline void tensormap_replace_swizzle_atomicity(
+  cuda::ptx::space_shared_t,
+  void* tm_addr,
+  cuda::ptx::n32_t<N32> new_val);
+*/
+#if __cccl_ptx_isa >= 860
+extern "C" _CCCL_DEVICE void __cuda_ptx_tensormap_replace_swizzle_atomicity_is_not_supported_before_SM_100a_SM_101a__();
+template <int _N32>
+_CCCL_DEVICE static inline void
+tensormap_replace_swizzle_atomicity(space_shared_t, void* __tm_addr, n32_t<_N32> __new_val)
+{
+// __space == space_shared (due to parameter type constraint)
+#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH_FEAT_SM100_ALL || __CUDA_ARCH_FEAT_SM101_ALL
+  asm("tensormap.replace.tile.swizzle_atomicity.shared::cta.b1024.b32 [%0], %1;"
+      :
+      : "r"(__as_ptr_smem(__tm_addr)), "n"(__new_val.value)
+      : "memory");
+#  else
+  // Unsupported architectures will have a linker error with a semi-decent error message
+  __cuda_ptx_tensormap_replace_swizzle_atomicity_is_not_supported_before_SM_100a_SM_101a__();
+#  endif
+}
+#endif // __cccl_ptx_isa >= 860
+
 #endif // _CUDA_PTX_GENERATED_TENSORMAP_REPLACE_H_
diff --git a/libcudacxx/test/libcudacxx/cuda/ptx/generated/barrier_cluster_aligned.h b/libcudacxx/test/libcudacxx/cuda/ptx/generated/barrier_cluster_aligned.h
new file mode 100644
index 00000000000..6f5a022dbc8
--- /dev/null
+++ b/libcudacxx/test/libcudacxx/cuda/ptx/generated/barrier_cluster_aligned.h
@@ -0,0 +1,61 @@
+// This file was automatically generated. Do not edit.
+
+// We use a special strategy to force the generation of the PTX. This is mainly
+// a fight against dead-code-elimination in the NVVM layer.
+//
+// The reason we need this strategy is because certain older versions of ptxas
+// segfault when a non-sensical sequence of PTX is generated. So instead, we try
+// to force the instantiation and compilation to PTX of all the overloads of the
+// PTX wrapping functions.
+//
+// We do this by writing a function pointer of each overload to the kernel
+// parameter `fn_ptr`.
+//
+// Because `fn_ptr` is possibly visible outside this translation unit, the
+// compiler must compile all the functions which are stored.
+
+__global__ void test_barrier_cluster_aligned(void** fn_ptr)
+{
+#if __cccl_ptx_isa >= 780
+  NV_IF_TARGET(NV_PROVIDES_SM_90,
+               (
+                   // barrier.cluster.arrive.aligned;
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(cuda::ptx::dot_aligned_t)>(cuda::ptx::barrier_cluster_arrive));));
+#endif // __cccl_ptx_isa >= 780
+
+#if __cccl_ptx_isa >= 780
+  NV_IF_TARGET(NV_PROVIDES_SM_90,
+               (
+                   // barrier.cluster.wait.aligned;
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(cuda::ptx::dot_aligned_t)>(cuda::ptx::barrier_cluster_wait));));
+#endif // __cccl_ptx_isa >= 780
+
+#if __cccl_ptx_isa >= 800
+  NV_IF_TARGET(
+    NV_PROVIDES_SM_90,
+    (
+        // barrier.cluster.arrive.release.aligned;
+        * fn_ptr++ = reinterpret_cast<void*>(static_cast<void (*)(cuda::ptx::sem_release_t, cuda::ptx::dot_aligned_t)>(
+          cuda::ptx::barrier_cluster_arrive));));
+#endif // __cccl_ptx_isa >= 800
+
+#if __cccl_ptx_isa >= 800
+  NV_IF_TARGET(
+    NV_PROVIDES_SM_90,
+    (
+        // barrier.cluster.arrive.relaxed.aligned;
+        * fn_ptr++ = reinterpret_cast<void*>(static_cast<void (*)(cuda::ptx::sem_relaxed_t, cuda::ptx::dot_aligned_t)>(
+          cuda::ptx::barrier_cluster_arrive));));
+#endif // __cccl_ptx_isa >= 800
+
+#if __cccl_ptx_isa >= 800
+  NV_IF_TARGET(
+    NV_PROVIDES_SM_90,
+    (
+        // barrier.cluster.wait.acquire.aligned;
+        * fn_ptr++ = reinterpret_cast<void*>(static_cast<void (*)(cuda::ptx::sem_acquire_t, cuda::ptx::dot_aligned_t)>(
+          cuda::ptx::barrier_cluster_wait));));
+#endif // __cccl_ptx_isa >= 800
+}
diff --git a/libcudacxx/test/libcudacxx/cuda/ptx/generated/clusterlaunchcontrol.h b/libcudacxx/test/libcudacxx/cuda/ptx/generated/clusterlaunchcontrol.h
new file mode 100644
index 00000000000..c5df06bc787
--- /dev/null
+++ b/libcudacxx/test/libcudacxx/cuda/ptx/generated/clusterlaunchcontrol.h
@@ -0,0 +1,84 @@
+// This file was automatically generated. Do not edit.
+
+// We use a special strategy to force the generation of the PTX. This is mainly
+// a fight against dead-code-elimination in the NVVM layer.
+//
+// The reason we need this strategy is because certain older versions of ptxas
+// segfault when a non-sensical sequence of PTX is generated. So instead, we try
+// to force the instantiation and compilation to PTX of all the overloads of the
+// PTX wrapping functions.
+//
+// We do this by writing a function pointer of each overload to the kernel
+// parameter `fn_ptr`.
+//
+// Because `fn_ptr` is possibly visible outside this translation unit, the
+// compiler must compile all the functions which are stored.
+
+__global__ void test_clusterlaunchcontrol(void** fn_ptr)
+{
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(NV_PROVIDES_SM_100,
+               (
+                   // clusterlaunchcontrol.try_cancel.async.shared::cta.mbarrier::complete_tx::bytes.b128 [addr],
+                   // [smem_bar];
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(void*, uint64_t*)>(cuda::ptx::clusterlaunchcontrol_try_cancel));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // clusterlaunchcontrol.try_cancel.async.shared::cta.mbarrier::complete_tx::bytes.multicast::cluster::all.b128
+        // [addr], [smem_bar];
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(void*, uint64_t*)>(cuda::ptx::clusterlaunchcontrol_try_cancel_multicast));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // clusterlaunchcontrol.try_cancel.async.shared::cta.mbarrier::complete_tx::bytes.multicast::cluster::all.b128
+        // [addr], [smem_bar];
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(void*, uint64_t*)>(cuda::ptx::clusterlaunchcontrol_try_cancel_multicast));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(NV_PROVIDES_SM_100,
+               (
+                   // clusterlaunchcontrol.query_cancel.is_canceled.pred.b128 pred_is_canceled, try_cancel_response;
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<bool (*)(__int128)>(cuda::ptx::clusterlaunchcontrol_query_cancel_is_canceled));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(NV_PROVIDES_SM_100,
+               (
+                   // clusterlaunchcontrol.query_cancel.get_first_ctaid::x.b32.b128 ret_dim, try_cancel_response;
+                   * fn_ptr++ = reinterpret_cast<void*>(static_cast<int32_t (*)(__int128)>(
+                     cuda::ptx::clusterlaunchcontrol_query_cancel_get_first_ctaid_x));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(NV_PROVIDES_SM_100,
+               (
+                   // clusterlaunchcontrol.query_cancel.get_first_ctaid::y.b32.b128 ret_dim, try_cancel_response;
+                   * fn_ptr++ = reinterpret_cast<void*>(static_cast<int32_t (*)(__int128)>(
+                     cuda::ptx::clusterlaunchcontrol_query_cancel_get_first_ctaid_y));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(NV_PROVIDES_SM_100,
+               (
+                   // clusterlaunchcontrol.query_cancel.get_first_ctaid::z.b32.b128 ret_dim, try_cancel_response;
+                   * fn_ptr++ = reinterpret_cast<void*>(static_cast<int32_t (*)(__int128)>(
+                     cuda::ptx::clusterlaunchcontrol_query_cancel_get_first_ctaid_z));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(NV_PROVIDES_SM_100,
+               (
+                   // clusterlaunchcontrol.query_cancel.get_first_ctaid.v4.b32.b128 block_dim, try_cancel_response;
+                   * fn_ptr++ = reinterpret_cast<void*>(static_cast<void (*)(int32_t(&block_dim)[4], __int128)>(
+                     cuda::ptx::clusterlaunchcontrol_query_cancel_get_first_ctaid));));
+#endif // __cccl_ptx_isa >= 860
+}
diff --git a/libcudacxx/test/libcudacxx/cuda/ptx/generated/cp_async_bulk.h b/libcudacxx/test/libcudacxx/cuda/ptx/generated/cp_async_bulk.h
index a342954591a..de118140440 100644
--- a/libcudacxx/test/libcudacxx/cuda/ptx/generated/cp_async_bulk.h
+++ b/libcudacxx/test/libcudacxx/cuda/ptx/generated/cp_async_bulk.h
@@ -20,20 +20,30 @@ __global__ void test_cp_async_bulk(void** fn_ptr)
   NV_IF_TARGET(
     NV_PROVIDES_SM_90,
     (
-        // cp.async.bulk.shared::cluster.global.mbarrier::complete_tx::bytes [dstMem], [srcMem], size, [smem_bar]; //
-        // 1a. unicast
+        // cp.async.bulk.shared::cluster.global.mbarrier::complete_tx::bytes [dstMem], [srcMem], size, [smem_bar];
         * fn_ptr++ = reinterpret_cast<void*>(
           static_cast<void (*)(
             cuda::ptx::space_cluster_t, cuda::ptx::space_global_t, void*, const void*, const uint32_t&, uint64_t*)>(
             cuda::ptx::cp_async_bulk));));
 #endif // __cccl_ptx_isa >= 800
 
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_PROVIDES_SM_90,
+    (
+        // cp.async.bulk.shared::cta.global.mbarrier::complete_tx::bytes [dstMem], [srcMem], size, [smem_bar];
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(
+            cuda::ptx::space_shared_t, cuda::ptx::space_global_t, void*, const void*, const uint32_t&, uint64_t*)>(
+            cuda::ptx::cp_async_bulk));));
+#endif // __cccl_ptx_isa >= 860
+
 #if __cccl_ptx_isa >= 800
   NV_IF_TARGET(
     NV_PROVIDES_SM_90,
     (
         // cp.async.bulk.shared::cluster.shared::cta.mbarrier::complete_tx::bytes [dstMem], [srcMem], size,
-        // [rdsmem_bar]; // 2.
+        // [rdsmem_bar];
         * fn_ptr++ = reinterpret_cast<void*>(
           static_cast<void (*)(
             cuda::ptx::space_cluster_t, cuda::ptx::space_shared_t, void*, const void*, const uint32_t&, uint64_t*)>(
@@ -44,10 +54,21 @@ __global__ void test_cp_async_bulk(void** fn_ptr)
   NV_IF_TARGET(
     NV_PROVIDES_SM_90,
     (
-        // cp.async.bulk.global.shared::cta.bulk_group [dstMem], [srcMem], size; // 3.
+        // cp.async.bulk.global.shared::cta.bulk_group [dstMem], [srcMem], size;
         * fn_ptr++ = reinterpret_cast<void*>(
           static_cast<void (*)(
             cuda::ptx::space_global_t, cuda::ptx::space_shared_t, void*, const void*, const uint32_t&)>(
             cuda::ptx::cp_async_bulk));));
 #endif // __cccl_ptx_isa >= 800
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_PROVIDES_SM_100,
+    (
+        // cp.async.bulk.global.shared::cta.bulk_group.cp_mask [dstMem], [srcMem], size, byteMask;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(
+            cuda::ptx::space_global_t, cuda::ptx::space_shared_t, void*, const void*, const uint32_t&, const uint16_t&)>(
+            cuda::ptx::cp_async_bulk_cp_mask));));
+#endif // __cccl_ptx_isa >= 860
 }
diff --git a/libcudacxx/test/libcudacxx/cuda/ptx/generated/cp_async_bulk_multicast.h b/libcudacxx/test/libcudacxx/cuda/ptx/generated/cp_async_bulk_multicast.h
index 6e2a986e7bd..81298beb481 100644
--- a/libcudacxx/test/libcudacxx/cuda/ptx/generated/cp_async_bulk_multicast.h
+++ b/libcudacxx/test/libcudacxx/cuda/ptx/generated/cp_async_bulk_multicast.h
@@ -21,7 +21,33 @@ __global__ void test_cp_async_bulk_multicast(void** fn_ptr)
     NV_HAS_FEATURE_SM_90a,
     (
         // cp.async.bulk.shared::cluster.global.mbarrier::complete_tx::bytes.multicast::cluster [dstMem], [srcMem],
-        // size, [smem_bar], ctaMask; // 1.
+        // size, [smem_bar], ctaMask;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(cuda::ptx::space_cluster_t,
+                               cuda::ptx::space_global_t,
+                               void*,
+                               const void*,
+                               const uint32_t&,
+                               uint64_t*,
+                               const uint16_t&)>(cuda::ptx::cp_async_bulk));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // cp.async.bulk.shared::cluster.global.mbarrier::complete_tx::bytes.multicast::cluster [dstMem], [srcMem],
+        // size, [smem_bar], ctaMask;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(cuda::ptx::space_cluster_t,
+                               cuda::ptx::space_global_t,
+                               void*,
+                               const void*,
+                               const uint32_t&,
+                               uint64_t*,
+                               const uint16_t&)>(cuda::ptx::cp_async_bulk));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // cp.async.bulk.shared::cluster.global.mbarrier::complete_tx::bytes.multicast::cluster [dstMem], [srcMem],
+        // size, [smem_bar], ctaMask;
         * fn_ptr++ = reinterpret_cast<void*>(
           static_cast<void (*)(cuda::ptx::space_cluster_t,
                                cuda::ptx::space_global_t,
diff --git a/libcudacxx/test/libcudacxx/cuda/ptx/generated/cp_async_bulk_tensor.h b/libcudacxx/test/libcudacxx/cuda/ptx/generated/cp_async_bulk_tensor.h
index 4618f3ea7a0..ff70fe0a435 100644
--- a/libcudacxx/test/libcudacxx/cuda/ptx/generated/cp_async_bulk_tensor.h
+++ b/libcudacxx/test/libcudacxx/cuda/ptx/generated/cp_async_bulk_tensor.h
@@ -21,18 +21,79 @@ __global__ void test_cp_async_bulk_tensor(void** fn_ptr)
     NV_PROVIDES_SM_90,
     (
         // cp.async.bulk.tensor.1d.shared::cluster.global.tile.mbarrier::complete_tx::bytes [dstMem], [tensorMap,
-        // tensorCoords], [smem_bar];// 1a.
+        // tensorCoords], [smem_bar];
         * fn_ptr++ = reinterpret_cast<void*>(
           static_cast<void (*)(
             cuda::ptx::space_cluster_t, cuda::ptx::space_global_t, void*, const void*, const int32_t(&)[1], uint64_t*)>(
             cuda::ptx::cp_async_bulk_tensor));));
 #endif // __cccl_ptx_isa >= 800
 
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_PROVIDES_SM_90,
+    (
+        // cp.async.bulk.tensor.1d.shared::cta.global.tile.mbarrier::complete_tx::bytes [dstMem], [tensorMap,
+        // tensorCoords], [smem_bar];
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(
+            cuda::ptx::space_shared_t, cuda::ptx::space_global_t, void*, const void*, const int32_t(&)[1], uint64_t*)>(
+            cuda::ptx::cp_async_bulk_tensor));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // cp.async.bulk.tensor.1d.shared::cta.global.tile.mbarrier::complete_tx::bytes.cta_group::1 [dstMem],
+        // [tensorMap, tensorCoords], [smem_bar];
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(cuda::ptx::space_shared_t,
+                               cuda::ptx::space_global_t,
+                               cuda::ptx::cta_group_1_t,
+                               void*,
+                               const void*,
+                               const int32_t(&)[1],
+                               uint64_t*)>(cuda::ptx::cp_async_bulk_tensor));
+          // cp.async.bulk.tensor.1d.shared::cta.global.tile.mbarrier::complete_tx::bytes.cta_group::2 [dstMem],
+          // [tensorMap, tensorCoords], [smem_bar];
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::space_shared_t,
+                                   cuda::ptx::space_global_t,
+                                   cuda::ptx::cta_group_2_t,
+                                   void*,
+                                   const void*,
+                                   const int32_t(&)[1],
+                                   uint64_t*)>(cuda::ptx::cp_async_bulk_tensor));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // cp.async.bulk.tensor.1d.shared::cta.global.tile.mbarrier::complete_tx::bytes.cta_group::1 [dstMem],
+        // [tensorMap, tensorCoords], [smem_bar];
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(cuda::ptx::space_shared_t,
+                               cuda::ptx::space_global_t,
+                               cuda::ptx::cta_group_1_t,
+                               void*,
+                               const void*,
+                               const int32_t(&)[1],
+                               uint64_t*)>(cuda::ptx::cp_async_bulk_tensor));
+          // cp.async.bulk.tensor.1d.shared::cta.global.tile.mbarrier::complete_tx::bytes.cta_group::2 [dstMem],
+          // [tensorMap, tensorCoords], [smem_bar];
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::space_shared_t,
+                                   cuda::ptx::space_global_t,
+                                   cuda::ptx::cta_group_2_t,
+                                   void*,
+                                   const void*,
+                                   const int32_t(&)[1],
+                                   uint64_t*)>(cuda::ptx::cp_async_bulk_tensor));));
+#endif // __cccl_ptx_isa >= 860
+
 #if __cccl_ptx_isa >= 800
   NV_IF_TARGET(
     NV_PROVIDES_SM_90,
     (
-        // cp.async.bulk.tensor.1d.global.shared::cta.tile.bulk_group [tensorMap, tensorCoords], [srcMem]; // 3a.
+        // cp.async.bulk.tensor.1d.global.shared::cta.tile.bulk_group [tensorMap, tensorCoords], [srcMem];
         * fn_ptr++ = reinterpret_cast<void*>(
           static_cast<void (*)(
             cuda::ptx::space_global_t, cuda::ptx::space_shared_t, const void*, const int32_t(&)[1], const void*)>(
@@ -44,18 +105,79 @@ __global__ void test_cp_async_bulk_tensor(void** fn_ptr)
     NV_PROVIDES_SM_90,
     (
         // cp.async.bulk.tensor.2d.shared::cluster.global.tile.mbarrier::complete_tx::bytes [dstMem], [tensorMap,
-        // tensorCoords], [smem_bar];// 1b.
+        // tensorCoords], [smem_bar];
         * fn_ptr++ = reinterpret_cast<void*>(
           static_cast<void (*)(
             cuda::ptx::space_cluster_t, cuda::ptx::space_global_t, void*, const void*, const int32_t(&)[2], uint64_t*)>(
             cuda::ptx::cp_async_bulk_tensor));));
 #endif // __cccl_ptx_isa >= 800
 
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_PROVIDES_SM_90,
+    (
+        // cp.async.bulk.tensor.2d.shared::cta.global.tile.mbarrier::complete_tx::bytes [dstMem], [tensorMap,
+        // tensorCoords], [smem_bar];
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(
+            cuda::ptx::space_shared_t, cuda::ptx::space_global_t, void*, const void*, const int32_t(&)[2], uint64_t*)>(
+            cuda::ptx::cp_async_bulk_tensor));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // cp.async.bulk.tensor.2d.shared::cta.global.tile.mbarrier::complete_tx::bytes.cta_group::1 [dstMem],
+        // [tensorMap, tensorCoords], [smem_bar];
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(cuda::ptx::space_shared_t,
+                               cuda::ptx::space_global_t,
+                               cuda::ptx::cta_group_1_t,
+                               void*,
+                               const void*,
+                               const int32_t(&)[2],
+                               uint64_t*)>(cuda::ptx::cp_async_bulk_tensor));
+          // cp.async.bulk.tensor.2d.shared::cta.global.tile.mbarrier::complete_tx::bytes.cta_group::2 [dstMem],
+          // [tensorMap, tensorCoords], [smem_bar];
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::space_shared_t,
+                                   cuda::ptx::space_global_t,
+                                   cuda::ptx::cta_group_2_t,
+                                   void*,
+                                   const void*,
+                                   const int32_t(&)[2],
+                                   uint64_t*)>(cuda::ptx::cp_async_bulk_tensor));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // cp.async.bulk.tensor.2d.shared::cta.global.tile.mbarrier::complete_tx::bytes.cta_group::1 [dstMem],
+        // [tensorMap, tensorCoords], [smem_bar];
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(cuda::ptx::space_shared_t,
+                               cuda::ptx::space_global_t,
+                               cuda::ptx::cta_group_1_t,
+                               void*,
+                               const void*,
+                               const int32_t(&)[2],
+                               uint64_t*)>(cuda::ptx::cp_async_bulk_tensor));
+          // cp.async.bulk.tensor.2d.shared::cta.global.tile.mbarrier::complete_tx::bytes.cta_group::2 [dstMem],
+          // [tensorMap, tensorCoords], [smem_bar];
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::space_shared_t,
+                                   cuda::ptx::space_global_t,
+                                   cuda::ptx::cta_group_2_t,
+                                   void*,
+                                   const void*,
+                                   const int32_t(&)[2],
+                                   uint64_t*)>(cuda::ptx::cp_async_bulk_tensor));));
+#endif // __cccl_ptx_isa >= 860
+
 #if __cccl_ptx_isa >= 800
   NV_IF_TARGET(
     NV_PROVIDES_SM_90,
     (
-        // cp.async.bulk.tensor.2d.global.shared::cta.tile.bulk_group [tensorMap, tensorCoords], [srcMem]; // 3b.
+        // cp.async.bulk.tensor.2d.global.shared::cta.tile.bulk_group [tensorMap, tensorCoords], [srcMem];
         * fn_ptr++ = reinterpret_cast<void*>(
           static_cast<void (*)(
             cuda::ptx::space_global_t, cuda::ptx::space_shared_t, const void*, const int32_t(&)[2], const void*)>(
@@ -67,18 +189,79 @@ __global__ void test_cp_async_bulk_tensor(void** fn_ptr)
     NV_PROVIDES_SM_90,
     (
         // cp.async.bulk.tensor.3d.shared::cluster.global.tile.mbarrier::complete_tx::bytes [dstMem], [tensorMap,
-        // tensorCoords], [smem_bar];// 1c.
+        // tensorCoords], [smem_bar];
         * fn_ptr++ = reinterpret_cast<void*>(
           static_cast<void (*)(
             cuda::ptx::space_cluster_t, cuda::ptx::space_global_t, void*, const void*, const int32_t(&)[3], uint64_t*)>(
             cuda::ptx::cp_async_bulk_tensor));));
 #endif // __cccl_ptx_isa >= 800
 
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_PROVIDES_SM_90,
+    (
+        // cp.async.bulk.tensor.3d.shared::cta.global.tile.mbarrier::complete_tx::bytes [dstMem], [tensorMap,
+        // tensorCoords], [smem_bar];
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(
+            cuda::ptx::space_shared_t, cuda::ptx::space_global_t, void*, const void*, const int32_t(&)[3], uint64_t*)>(
+            cuda::ptx::cp_async_bulk_tensor));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // cp.async.bulk.tensor.3d.shared::cta.global.tile.mbarrier::complete_tx::bytes.cta_group::1 [dstMem],
+        // [tensorMap, tensorCoords], [smem_bar];
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(cuda::ptx::space_shared_t,
+                               cuda::ptx::space_global_t,
+                               cuda::ptx::cta_group_1_t,
+                               void*,
+                               const void*,
+                               const int32_t(&)[3],
+                               uint64_t*)>(cuda::ptx::cp_async_bulk_tensor));
+          // cp.async.bulk.tensor.3d.shared::cta.global.tile.mbarrier::complete_tx::bytes.cta_group::2 [dstMem],
+          // [tensorMap, tensorCoords], [smem_bar];
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::space_shared_t,
+                                   cuda::ptx::space_global_t,
+                                   cuda::ptx::cta_group_2_t,
+                                   void*,
+                                   const void*,
+                                   const int32_t(&)[3],
+                                   uint64_t*)>(cuda::ptx::cp_async_bulk_tensor));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // cp.async.bulk.tensor.3d.shared::cta.global.tile.mbarrier::complete_tx::bytes.cta_group::1 [dstMem],
+        // [tensorMap, tensorCoords], [smem_bar];
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(cuda::ptx::space_shared_t,
+                               cuda::ptx::space_global_t,
+                               cuda::ptx::cta_group_1_t,
+                               void*,
+                               const void*,
+                               const int32_t(&)[3],
+                               uint64_t*)>(cuda::ptx::cp_async_bulk_tensor));
+          // cp.async.bulk.tensor.3d.shared::cta.global.tile.mbarrier::complete_tx::bytes.cta_group::2 [dstMem],
+          // [tensorMap, tensorCoords], [smem_bar];
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::space_shared_t,
+                                   cuda::ptx::space_global_t,
+                                   cuda::ptx::cta_group_2_t,
+                                   void*,
+                                   const void*,
+                                   const int32_t(&)[3],
+                                   uint64_t*)>(cuda::ptx::cp_async_bulk_tensor));));
+#endif // __cccl_ptx_isa >= 860
+
 #if __cccl_ptx_isa >= 800
   NV_IF_TARGET(
     NV_PROVIDES_SM_90,
     (
-        // cp.async.bulk.tensor.3d.global.shared::cta.tile.bulk_group [tensorMap, tensorCoords], [srcMem]; // 3c.
+        // cp.async.bulk.tensor.3d.global.shared::cta.tile.bulk_group [tensorMap, tensorCoords], [srcMem];
         * fn_ptr++ = reinterpret_cast<void*>(
           static_cast<void (*)(
             cuda::ptx::space_global_t, cuda::ptx::space_shared_t, const void*, const int32_t(&)[3], const void*)>(
@@ -90,18 +273,79 @@ __global__ void test_cp_async_bulk_tensor(void** fn_ptr)
     NV_PROVIDES_SM_90,
     (
         // cp.async.bulk.tensor.4d.shared::cluster.global.tile.mbarrier::complete_tx::bytes [dstMem], [tensorMap,
-        // tensorCoords], [smem_bar];// 1d.
+        // tensorCoords], [smem_bar];
         * fn_ptr++ = reinterpret_cast<void*>(
           static_cast<void (*)(
             cuda::ptx::space_cluster_t, cuda::ptx::space_global_t, void*, const void*, const int32_t(&)[4], uint64_t*)>(
             cuda::ptx::cp_async_bulk_tensor));));
 #endif // __cccl_ptx_isa >= 800
 
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_PROVIDES_SM_90,
+    (
+        // cp.async.bulk.tensor.4d.shared::cta.global.tile.mbarrier::complete_tx::bytes [dstMem], [tensorMap,
+        // tensorCoords], [smem_bar];
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(
+            cuda::ptx::space_shared_t, cuda::ptx::space_global_t, void*, const void*, const int32_t(&)[4], uint64_t*)>(
+            cuda::ptx::cp_async_bulk_tensor));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // cp.async.bulk.tensor.4d.shared::cta.global.tile.mbarrier::complete_tx::bytes.cta_group::1 [dstMem],
+        // [tensorMap, tensorCoords], [smem_bar];
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(cuda::ptx::space_shared_t,
+                               cuda::ptx::space_global_t,
+                               cuda::ptx::cta_group_1_t,
+                               void*,
+                               const void*,
+                               const int32_t(&)[4],
+                               uint64_t*)>(cuda::ptx::cp_async_bulk_tensor));
+          // cp.async.bulk.tensor.4d.shared::cta.global.tile.mbarrier::complete_tx::bytes.cta_group::2 [dstMem],
+          // [tensorMap, tensorCoords], [smem_bar];
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::space_shared_t,
+                                   cuda::ptx::space_global_t,
+                                   cuda::ptx::cta_group_2_t,
+                                   void*,
+                                   const void*,
+                                   const int32_t(&)[4],
+                                   uint64_t*)>(cuda::ptx::cp_async_bulk_tensor));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // cp.async.bulk.tensor.4d.shared::cta.global.tile.mbarrier::complete_tx::bytes.cta_group::1 [dstMem],
+        // [tensorMap, tensorCoords], [smem_bar];
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(cuda::ptx::space_shared_t,
+                               cuda::ptx::space_global_t,
+                               cuda::ptx::cta_group_1_t,
+                               void*,
+                               const void*,
+                               const int32_t(&)[4],
+                               uint64_t*)>(cuda::ptx::cp_async_bulk_tensor));
+          // cp.async.bulk.tensor.4d.shared::cta.global.tile.mbarrier::complete_tx::bytes.cta_group::2 [dstMem],
+          // [tensorMap, tensorCoords], [smem_bar];
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::space_shared_t,
+                                   cuda::ptx::space_global_t,
+                                   cuda::ptx::cta_group_2_t,
+                                   void*,
+                                   const void*,
+                                   const int32_t(&)[4],
+                                   uint64_t*)>(cuda::ptx::cp_async_bulk_tensor));));
+#endif // __cccl_ptx_isa >= 860
+
 #if __cccl_ptx_isa >= 800
   NV_IF_TARGET(
     NV_PROVIDES_SM_90,
     (
-        // cp.async.bulk.tensor.4d.global.shared::cta.tile.bulk_group [tensorMap, tensorCoords], [srcMem]; // 3d.
+        // cp.async.bulk.tensor.4d.global.shared::cta.tile.bulk_group [tensorMap, tensorCoords], [srcMem];
         * fn_ptr++ = reinterpret_cast<void*>(
           static_cast<void (*)(
             cuda::ptx::space_global_t, cuda::ptx::space_shared_t, const void*, const int32_t(&)[4], const void*)>(
@@ -113,18 +357,79 @@ __global__ void test_cp_async_bulk_tensor(void** fn_ptr)
     NV_PROVIDES_SM_90,
     (
         // cp.async.bulk.tensor.5d.shared::cluster.global.tile.mbarrier::complete_tx::bytes [dstMem], [tensorMap,
-        // tensorCoords], [smem_bar];// 1e.
+        // tensorCoords], [smem_bar];
         * fn_ptr++ = reinterpret_cast<void*>(
           static_cast<void (*)(
             cuda::ptx::space_cluster_t, cuda::ptx::space_global_t, void*, const void*, const int32_t(&)[5], uint64_t*)>(
             cuda::ptx::cp_async_bulk_tensor));));
 #endif // __cccl_ptx_isa >= 800
 
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_PROVIDES_SM_90,
+    (
+        // cp.async.bulk.tensor.5d.shared::cta.global.tile.mbarrier::complete_tx::bytes [dstMem], [tensorMap,
+        // tensorCoords], [smem_bar];
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(
+            cuda::ptx::space_shared_t, cuda::ptx::space_global_t, void*, const void*, const int32_t(&)[5], uint64_t*)>(
+            cuda::ptx::cp_async_bulk_tensor));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // cp.async.bulk.tensor.5d.shared::cta.global.tile.mbarrier::complete_tx::bytes.cta_group::1 [dstMem],
+        // [tensorMap, tensorCoords], [smem_bar];
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(cuda::ptx::space_shared_t,
+                               cuda::ptx::space_global_t,
+                               cuda::ptx::cta_group_1_t,
+                               void*,
+                               const void*,
+                               const int32_t(&)[5],
+                               uint64_t*)>(cuda::ptx::cp_async_bulk_tensor));
+          // cp.async.bulk.tensor.5d.shared::cta.global.tile.mbarrier::complete_tx::bytes.cta_group::2 [dstMem],
+          // [tensorMap, tensorCoords], [smem_bar];
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::space_shared_t,
+                                   cuda::ptx::space_global_t,
+                                   cuda::ptx::cta_group_2_t,
+                                   void*,
+                                   const void*,
+                                   const int32_t(&)[5],
+                                   uint64_t*)>(cuda::ptx::cp_async_bulk_tensor));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // cp.async.bulk.tensor.5d.shared::cta.global.tile.mbarrier::complete_tx::bytes.cta_group::1 [dstMem],
+        // [tensorMap, tensorCoords], [smem_bar];
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(cuda::ptx::space_shared_t,
+                               cuda::ptx::space_global_t,
+                               cuda::ptx::cta_group_1_t,
+                               void*,
+                               const void*,
+                               const int32_t(&)[5],
+                               uint64_t*)>(cuda::ptx::cp_async_bulk_tensor));
+          // cp.async.bulk.tensor.5d.shared::cta.global.tile.mbarrier::complete_tx::bytes.cta_group::2 [dstMem],
+          // [tensorMap, tensorCoords], [smem_bar];
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::space_shared_t,
+                                   cuda::ptx::space_global_t,
+                                   cuda::ptx::cta_group_2_t,
+                                   void*,
+                                   const void*,
+                                   const int32_t(&)[5],
+                                   uint64_t*)>(cuda::ptx::cp_async_bulk_tensor));));
+#endif // __cccl_ptx_isa >= 860
+
 #if __cccl_ptx_isa >= 800
   NV_IF_TARGET(
     NV_PROVIDES_SM_90,
     (
-        // cp.async.bulk.tensor.5d.global.shared::cta.tile.bulk_group [tensorMap, tensorCoords], [srcMem]; // 3e.
+        // cp.async.bulk.tensor.5d.global.shared::cta.tile.bulk_group [tensorMap, tensorCoords], [srcMem];
         * fn_ptr++ = reinterpret_cast<void*>(
           static_cast<void (*)(
             cuda::ptx::space_global_t, cuda::ptx::space_shared_t, const void*, const int32_t(&)[5], const void*)>(
diff --git a/libcudacxx/test/libcudacxx/cuda/ptx/generated/cp_async_bulk_tensor_gather_scatter.h b/libcudacxx/test/libcudacxx/cuda/ptx/generated/cp_async_bulk_tensor_gather_scatter.h
new file mode 100644
index 00000000000..930cfa09125
--- /dev/null
+++ b/libcudacxx/test/libcudacxx/cuda/ptx/generated/cp_async_bulk_tensor_gather_scatter.h
@@ -0,0 +1,180 @@
+// This file was automatically generated. Do not edit.
+
+// We use a special strategy to force the generation of the PTX. This is mainly
+// a fight against dead-code-elimination in the NVVM layer.
+//
+// The reason we need this strategy is because certain older versions of ptxas
+// segfault when a non-sensical sequence of PTX is generated. So instead, we try
+// to force the instantiation and compilation to PTX of all the overloads of the
+// PTX wrapping functions.
+//
+// We do this by writing a function pointer of each overload to the kernel
+// parameter `fn_ptr`.
+//
+// Because `fn_ptr` is possibly visible outside this translation unit, the
+// compiler must compile all the functions which are stored.
+
+__global__ void test_cp_async_bulk_tensor_gather_scatter(void** fn_ptr)
+{
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_PROVIDES_SM_100,
+    (
+        // cp.async.bulk.tensor.2d.shared::cta.global.tile::gather4.mbarrier::complete_tx::bytes [dstMem], [tensorMap,
+        // tensorCoords], [smem_bar];
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(
+            cuda::ptx::space_shared_t, cuda::ptx::space_global_t, void*, const void*, const int32_t(&)[5], uint64_t*)>(
+            cuda::ptx::cp_async_bulk_tensor_tile_gather4));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // cp.async.bulk.tensor.2d.shared::cta.global.tile::gather4.mbarrier::complete_tx::bytes.cta_group::1 [dstMem],
+        // [tensorMap, tensorCoords], [smem_bar];
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(cuda::ptx::space_shared_t,
+                               cuda::ptx::space_global_t,
+                               cuda::ptx::cta_group_1_t,
+                               void*,
+                               const void*,
+                               const int32_t(&)[5],
+                               uint64_t*)>(cuda::ptx::cp_async_bulk_tensor_tile_gather4));
+          // cp.async.bulk.tensor.2d.shared::cta.global.tile::gather4.mbarrier::complete_tx::bytes.cta_group::2
+          // [dstMem], [tensorMap, tensorCoords], [smem_bar];
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::space_shared_t,
+                                   cuda::ptx::space_global_t,
+                                   cuda::ptx::cta_group_2_t,
+                                   void*,
+                                   const void*,
+                                   const int32_t(&)[5],
+                                   uint64_t*)>(cuda::ptx::cp_async_bulk_tensor_tile_gather4));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // cp.async.bulk.tensor.2d.shared::cta.global.tile::gather4.mbarrier::complete_tx::bytes.cta_group::1 [dstMem],
+        // [tensorMap, tensorCoords], [smem_bar];
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(cuda::ptx::space_shared_t,
+                               cuda::ptx::space_global_t,
+                               cuda::ptx::cta_group_1_t,
+                               void*,
+                               const void*,
+                               const int32_t(&)[5],
+                               uint64_t*)>(cuda::ptx::cp_async_bulk_tensor_tile_gather4));
+          // cp.async.bulk.tensor.2d.shared::cta.global.tile::gather4.mbarrier::complete_tx::bytes.cta_group::2
+          // [dstMem], [tensorMap, tensorCoords], [smem_bar];
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::space_shared_t,
+                                   cuda::ptx::space_global_t,
+                                   cuda::ptx::cta_group_2_t,
+                                   void*,
+                                   const void*,
+                                   const int32_t(&)[5],
+                                   uint64_t*)>(cuda::ptx::cp_async_bulk_tensor_tile_gather4));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // cp.async.bulk.tensor.2d.shared::cluster.global.tile::gather4.mbarrier::complete_tx::bytes.multicast::cluster
+        // [dstMem], [tensorMap, tensorCoords], [smem_bar], ctaMask;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(cuda::ptx::space_cluster_t,
+                               cuda::ptx::space_global_t,
+                               void*,
+                               const void*,
+                               const int32_t(&)[5],
+                               uint64_t*,
+                               const uint16_t&)>(cuda::ptx::cp_async_bulk_tensor_tile_gather4));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // cp.async.bulk.tensor.2d.shared::cluster.global.tile::gather4.mbarrier::complete_tx::bytes.multicast::cluster
+        // [dstMem], [tensorMap, tensorCoords], [smem_bar], ctaMask;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(cuda::ptx::space_cluster_t,
+                               cuda::ptx::space_global_t,
+                               void*,
+                               const void*,
+                               const int32_t(&)[5],
+                               uint64_t*,
+                               const uint16_t&)>(cuda::ptx::cp_async_bulk_tensor_tile_gather4));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // cp.async.bulk.tensor.2d.shared::cluster.global.tile::gather4.mbarrier::complete_tx::bytes.multicast::cluster.cta_group::1
+        // [dstMem], [tensorMap, tensorCoords], [smem_bar], ctaMask;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(cuda::ptx::space_cluster_t,
+                               cuda::ptx::space_global_t,
+                               cuda::ptx::cta_group_1_t,
+                               void*,
+                               const void*,
+                               const int32_t(&)[5],
+                               uint64_t*,
+                               const uint16_t&)>(cuda::ptx::cp_async_bulk_tensor_tile_gather4));
+          // cp.async.bulk.tensor.2d.shared::cluster.global.tile::gather4.mbarrier::complete_tx::bytes.multicast::cluster.cta_group::2
+          // [dstMem], [tensorMap, tensorCoords], [smem_bar], ctaMask;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::space_cluster_t,
+                                   cuda::ptx::space_global_t,
+                                   cuda::ptx::cta_group_2_t,
+                                   void*,
+                                   const void*,
+                                   const int32_t(&)[5],
+                                   uint64_t*,
+                                   const uint16_t&)>(cuda::ptx::cp_async_bulk_tensor_tile_gather4));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // cp.async.bulk.tensor.2d.shared::cluster.global.tile::gather4.mbarrier::complete_tx::bytes.multicast::cluster.cta_group::1
+        // [dstMem], [tensorMap, tensorCoords], [smem_bar], ctaMask;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(cuda::ptx::space_cluster_t,
+                               cuda::ptx::space_global_t,
+                               cuda::ptx::cta_group_1_t,
+                               void*,
+                               const void*,
+                               const int32_t(&)[5],
+                               uint64_t*,
+                               const uint16_t&)>(cuda::ptx::cp_async_bulk_tensor_tile_gather4));
+          // cp.async.bulk.tensor.2d.shared::cluster.global.tile::gather4.mbarrier::complete_tx::bytes.multicast::cluster.cta_group::2
+          // [dstMem], [tensorMap, tensorCoords], [smem_bar], ctaMask;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::space_cluster_t,
+                                   cuda::ptx::space_global_t,
+                                   cuda::ptx::cta_group_2_t,
+                                   void*,
+                                   const void*,
+                                   const int32_t(&)[5],
+                                   uint64_t*,
+                                   const uint16_t&)>(cuda::ptx::cp_async_bulk_tensor_tile_gather4));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 800
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // cp.async.bulk.tensor.2d.global.shared::cta.tile::scatter4.bulk_group [tensorMap, tensorCoords], [srcMem];
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(
+            cuda::ptx::space_global_t, cuda::ptx::space_shared_t, const void*, const int32_t(&)[5], const void*)>(
+            cuda::ptx::cp_async_bulk_tensor_tile_scatter4));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // cp.async.bulk.tensor.2d.global.shared::cta.tile::scatter4.bulk_group [tensorMap, tensorCoords], [srcMem];
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(
+            cuda::ptx::space_global_t, cuda::ptx::space_shared_t, const void*, const int32_t(&)[5], const void*)>(
+            cuda::ptx::cp_async_bulk_tensor_tile_scatter4));));
+#endif // __cccl_ptx_isa >= 800
+}
diff --git a/libcudacxx/test/libcudacxx/cuda/ptx/generated/cp_async_bulk_tensor_multicast.h b/libcudacxx/test/libcudacxx/cuda/ptx/generated/cp_async_bulk_tensor_multicast.h
index 617bc9507bd..3f3a08764d2 100644
--- a/libcudacxx/test/libcudacxx/cuda/ptx/generated/cp_async_bulk_tensor_multicast.h
+++ b/libcudacxx/test/libcudacxx/cuda/ptx/generated/cp_async_bulk_tensor_multicast.h
@@ -21,7 +21,7 @@ __global__ void test_cp_async_bulk_tensor_multicast(void** fn_ptr)
     NV_HAS_FEATURE_SM_90a,
     (
         // cp.async.bulk.tensor.1d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.multicast::cluster [dstMem],
-        // [tensorMap, tensorCoords], [smem_bar], ctaMask; // 2a.
+        // [tensorMap, tensorCoords], [smem_bar], ctaMask;
         * fn_ptr++ = reinterpret_cast<void*>(
           static_cast<void (*)(cuda::ptx::space_cluster_t,
                                cuda::ptx::space_global_t,
@@ -30,6 +30,85 @@ __global__ void test_cp_async_bulk_tensor_multicast(void** fn_ptr)
                                const int32_t(&)[1],
                                uint64_t*,
                                const uint16_t&)>(cuda::ptx::cp_async_bulk_tensor));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // cp.async.bulk.tensor.1d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.multicast::cluster [dstMem],
+        // [tensorMap, tensorCoords], [smem_bar], ctaMask;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(cuda::ptx::space_cluster_t,
+                               cuda::ptx::space_global_t,
+                               void*,
+                               const void*,
+                               const int32_t(&)[1],
+                               uint64_t*,
+                               const uint16_t&)>(cuda::ptx::cp_async_bulk_tensor));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // cp.async.bulk.tensor.1d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.multicast::cluster [dstMem],
+        // [tensorMap, tensorCoords], [smem_bar], ctaMask;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(cuda::ptx::space_cluster_t,
+                               cuda::ptx::space_global_t,
+                               void*,
+                               const void*,
+                               const int32_t(&)[1],
+                               uint64_t*,
+                               const uint16_t&)>(cuda::ptx::cp_async_bulk_tensor));));
+#endif // __cccl_ptx_isa >= 800
+
+#if __cccl_ptx_isa >= 800
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // cp.async.bulk.tensor.1d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.multicast::cluster.cta_group::1
+        // [dstMem], [tensorMap, tensorCoords], [smem_bar], ctaMask;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(cuda::ptx::space_cluster_t,
+                               cuda::ptx::space_global_t,
+                               cuda::ptx::cta_group_1_t,
+                               void*,
+                               const void*,
+                               const int32_t(&)[1],
+                               uint64_t*,
+                               const uint16_t&)>(cuda::ptx::cp_async_bulk_tensor));
+          // cp.async.bulk.tensor.1d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.multicast::cluster.cta_group::2
+          // [dstMem], [tensorMap, tensorCoords], [smem_bar], ctaMask;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::space_cluster_t,
+                                   cuda::ptx::space_global_t,
+                                   cuda::ptx::cta_group_2_t,
+                                   void*,
+                                   const void*,
+                                   const int32_t(&)[1],
+                                   uint64_t*,
+                                   const uint16_t&)>(cuda::ptx::cp_async_bulk_tensor));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // cp.async.bulk.tensor.1d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.multicast::cluster.cta_group::1
+        // [dstMem], [tensorMap, tensorCoords], [smem_bar], ctaMask;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(cuda::ptx::space_cluster_t,
+                               cuda::ptx::space_global_t,
+                               cuda::ptx::cta_group_1_t,
+                               void*,
+                               const void*,
+                               const int32_t(&)[1],
+                               uint64_t*,
+                               const uint16_t&)>(cuda::ptx::cp_async_bulk_tensor));
+          // cp.async.bulk.tensor.1d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.multicast::cluster.cta_group::2
+          // [dstMem], [tensorMap, tensorCoords], [smem_bar], ctaMask;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::space_cluster_t,
+                                   cuda::ptx::space_global_t,
+                                   cuda::ptx::cta_group_2_t,
+                                   void*,
+                                   const void*,
+                                   const int32_t(&)[1],
+                                   uint64_t*,
+                                   const uint16_t&)>(cuda::ptx::cp_async_bulk_tensor));));
 #endif // __cccl_ptx_isa >= 800
 
 #if __cccl_ptx_isa >= 800
@@ -37,7 +116,20 @@ __global__ void test_cp_async_bulk_tensor_multicast(void** fn_ptr)
     NV_HAS_FEATURE_SM_90a,
     (
         // cp.async.bulk.tensor.2d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.multicast::cluster [dstMem],
-        // [tensorMap, tensorCoords], [smem_bar], ctaMask; // 2b.
+        // [tensorMap, tensorCoords], [smem_bar], ctaMask;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(cuda::ptx::space_cluster_t,
+                               cuda::ptx::space_global_t,
+                               void*,
+                               const void*,
+                               const int32_t(&)[2],
+                               uint64_t*,
+                               const uint16_t&)>(cuda::ptx::cp_async_bulk_tensor));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // cp.async.bulk.tensor.2d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.multicast::cluster [dstMem],
+        // [tensorMap, tensorCoords], [smem_bar], ctaMask;
         * fn_ptr++ = reinterpret_cast<void*>(
           static_cast<void (*)(cuda::ptx::space_cluster_t,
                                cuda::ptx::space_global_t,
@@ -46,6 +138,72 @@ __global__ void test_cp_async_bulk_tensor_multicast(void** fn_ptr)
                                const int32_t(&)[2],
                                uint64_t*,
                                const uint16_t&)>(cuda::ptx::cp_async_bulk_tensor));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // cp.async.bulk.tensor.2d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.multicast::cluster [dstMem],
+        // [tensorMap, tensorCoords], [smem_bar], ctaMask;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(cuda::ptx::space_cluster_t,
+                               cuda::ptx::space_global_t,
+                               void*,
+                               const void*,
+                               const int32_t(&)[2],
+                               uint64_t*,
+                               const uint16_t&)>(cuda::ptx::cp_async_bulk_tensor));));
+#endif // __cccl_ptx_isa >= 800
+
+#if __cccl_ptx_isa >= 800
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // cp.async.bulk.tensor.2d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.multicast::cluster.cta_group::1
+        // [dstMem], [tensorMap, tensorCoords], [smem_bar], ctaMask;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(cuda::ptx::space_cluster_t,
+                               cuda::ptx::space_global_t,
+                               cuda::ptx::cta_group_1_t,
+                               void*,
+                               const void*,
+                               const int32_t(&)[2],
+                               uint64_t*,
+                               const uint16_t&)>(cuda::ptx::cp_async_bulk_tensor));
+          // cp.async.bulk.tensor.2d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.multicast::cluster.cta_group::2
+          // [dstMem], [tensorMap, tensorCoords], [smem_bar], ctaMask;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::space_cluster_t,
+                                   cuda::ptx::space_global_t,
+                                   cuda::ptx::cta_group_2_t,
+                                   void*,
+                                   const void*,
+                                   const int32_t(&)[2],
+                                   uint64_t*,
+                                   const uint16_t&)>(cuda::ptx::cp_async_bulk_tensor));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // cp.async.bulk.tensor.2d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.multicast::cluster.cta_group::1
+        // [dstMem], [tensorMap, tensorCoords], [smem_bar], ctaMask;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(cuda::ptx::space_cluster_t,
+                               cuda::ptx::space_global_t,
+                               cuda::ptx::cta_group_1_t,
+                               void*,
+                               const void*,
+                               const int32_t(&)[2],
+                               uint64_t*,
+                               const uint16_t&)>(cuda::ptx::cp_async_bulk_tensor));
+          // cp.async.bulk.tensor.2d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.multicast::cluster.cta_group::2
+          // [dstMem], [tensorMap, tensorCoords], [smem_bar], ctaMask;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::space_cluster_t,
+                                   cuda::ptx::space_global_t,
+                                   cuda::ptx::cta_group_2_t,
+                                   void*,
+                                   const void*,
+                                   const int32_t(&)[2],
+                                   uint64_t*,
+                                   const uint16_t&)>(cuda::ptx::cp_async_bulk_tensor));));
 #endif // __cccl_ptx_isa >= 800
 
 #if __cccl_ptx_isa >= 800
@@ -53,7 +211,33 @@ __global__ void test_cp_async_bulk_tensor_multicast(void** fn_ptr)
     NV_HAS_FEATURE_SM_90a,
     (
         // cp.async.bulk.tensor.3d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.multicast::cluster [dstMem],
-        // [tensorMap, tensorCoords], [smem_bar], ctaMask; // 2c.
+        // [tensorMap, tensorCoords], [smem_bar], ctaMask;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(cuda::ptx::space_cluster_t,
+                               cuda::ptx::space_global_t,
+                               void*,
+                               const void*,
+                               const int32_t(&)[3],
+                               uint64_t*,
+                               const uint16_t&)>(cuda::ptx::cp_async_bulk_tensor));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // cp.async.bulk.tensor.3d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.multicast::cluster [dstMem],
+        // [tensorMap, tensorCoords], [smem_bar], ctaMask;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(cuda::ptx::space_cluster_t,
+                               cuda::ptx::space_global_t,
+                               void*,
+                               const void*,
+                               const int32_t(&)[3],
+                               uint64_t*,
+                               const uint16_t&)>(cuda::ptx::cp_async_bulk_tensor));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // cp.async.bulk.tensor.3d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.multicast::cluster [dstMem],
+        // [tensorMap, tensorCoords], [smem_bar], ctaMask;
         * fn_ptr++ = reinterpret_cast<void*>(
           static_cast<void (*)(cuda::ptx::space_cluster_t,
                                cuda::ptx::space_global_t,
@@ -64,12 +248,91 @@ __global__ void test_cp_async_bulk_tensor_multicast(void** fn_ptr)
                                const uint16_t&)>(cuda::ptx::cp_async_bulk_tensor));));
 #endif // __cccl_ptx_isa >= 800
 
+#if __cccl_ptx_isa >= 800
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // cp.async.bulk.tensor.3d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.multicast::cluster.cta_group::1
+        // [dstMem], [tensorMap, tensorCoords], [smem_bar], ctaMask;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(cuda::ptx::space_cluster_t,
+                               cuda::ptx::space_global_t,
+                               cuda::ptx::cta_group_1_t,
+                               void*,
+                               const void*,
+                               const int32_t(&)[3],
+                               uint64_t*,
+                               const uint16_t&)>(cuda::ptx::cp_async_bulk_tensor));
+          // cp.async.bulk.tensor.3d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.multicast::cluster.cta_group::2
+          // [dstMem], [tensorMap, tensorCoords], [smem_bar], ctaMask;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::space_cluster_t,
+                                   cuda::ptx::space_global_t,
+                                   cuda::ptx::cta_group_2_t,
+                                   void*,
+                                   const void*,
+                                   const int32_t(&)[3],
+                                   uint64_t*,
+                                   const uint16_t&)>(cuda::ptx::cp_async_bulk_tensor));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // cp.async.bulk.tensor.3d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.multicast::cluster.cta_group::1
+        // [dstMem], [tensorMap, tensorCoords], [smem_bar], ctaMask;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(cuda::ptx::space_cluster_t,
+                               cuda::ptx::space_global_t,
+                               cuda::ptx::cta_group_1_t,
+                               void*,
+                               const void*,
+                               const int32_t(&)[3],
+                               uint64_t*,
+                               const uint16_t&)>(cuda::ptx::cp_async_bulk_tensor));
+          // cp.async.bulk.tensor.3d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.multicast::cluster.cta_group::2
+          // [dstMem], [tensorMap, tensorCoords], [smem_bar], ctaMask;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::space_cluster_t,
+                                   cuda::ptx::space_global_t,
+                                   cuda::ptx::cta_group_2_t,
+                                   void*,
+                                   const void*,
+                                   const int32_t(&)[3],
+                                   uint64_t*,
+                                   const uint16_t&)>(cuda::ptx::cp_async_bulk_tensor));));
+#endif // __cccl_ptx_isa >= 800
+
 #if __cccl_ptx_isa >= 800
   NV_IF_TARGET(
     NV_HAS_FEATURE_SM_90a,
     (
         // cp.async.bulk.tensor.4d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.multicast::cluster [dstMem],
-        // [tensorMap, tensorCoords], [smem_bar], ctaMask; // 2d.
+        // [tensorMap, tensorCoords], [smem_bar], ctaMask;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(cuda::ptx::space_cluster_t,
+                               cuda::ptx::space_global_t,
+                               void*,
+                               const void*,
+                               const int32_t(&)[4],
+                               uint64_t*,
+                               const uint16_t&)>(cuda::ptx::cp_async_bulk_tensor));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // cp.async.bulk.tensor.4d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.multicast::cluster [dstMem],
+        // [tensorMap, tensorCoords], [smem_bar], ctaMask;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(cuda::ptx::space_cluster_t,
+                               cuda::ptx::space_global_t,
+                               void*,
+                               const void*,
+                               const int32_t(&)[4],
+                               uint64_t*,
+                               const uint16_t&)>(cuda::ptx::cp_async_bulk_tensor));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // cp.async.bulk.tensor.4d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.multicast::cluster [dstMem],
+        // [tensorMap, tensorCoords], [smem_bar], ctaMask;
         * fn_ptr++ = reinterpret_cast<void*>(
           static_cast<void (*)(cuda::ptx::space_cluster_t,
                                cuda::ptx::space_global_t,
@@ -80,12 +343,65 @@ __global__ void test_cp_async_bulk_tensor_multicast(void** fn_ptr)
                                const uint16_t&)>(cuda::ptx::cp_async_bulk_tensor));));
 #endif // __cccl_ptx_isa >= 800
 
+#if __cccl_ptx_isa >= 800
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // cp.async.bulk.tensor.4d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.multicast::cluster.cta_group::1
+        // [dstMem], [tensorMap, tensorCoords], [smem_bar], ctaMask;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(cuda::ptx::space_cluster_t,
+                               cuda::ptx::space_global_t,
+                               cuda::ptx::cta_group_1_t,
+                               void*,
+                               const void*,
+                               const int32_t(&)[4],
+                               uint64_t*,
+                               const uint16_t&)>(cuda::ptx::cp_async_bulk_tensor));
+          // cp.async.bulk.tensor.4d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.multicast::cluster.cta_group::2
+          // [dstMem], [tensorMap, tensorCoords], [smem_bar], ctaMask;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::space_cluster_t,
+                                   cuda::ptx::space_global_t,
+                                   cuda::ptx::cta_group_2_t,
+                                   void*,
+                                   const void*,
+                                   const int32_t(&)[4],
+                                   uint64_t*,
+                                   const uint16_t&)>(cuda::ptx::cp_async_bulk_tensor));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // cp.async.bulk.tensor.4d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.multicast::cluster.cta_group::1
+        // [dstMem], [tensorMap, tensorCoords], [smem_bar], ctaMask;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(cuda::ptx::space_cluster_t,
+                               cuda::ptx::space_global_t,
+                               cuda::ptx::cta_group_1_t,
+                               void*,
+                               const void*,
+                               const int32_t(&)[4],
+                               uint64_t*,
+                               const uint16_t&)>(cuda::ptx::cp_async_bulk_tensor));
+          // cp.async.bulk.tensor.4d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.multicast::cluster.cta_group::2
+          // [dstMem], [tensorMap, tensorCoords], [smem_bar], ctaMask;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::space_cluster_t,
+                                   cuda::ptx::space_global_t,
+                                   cuda::ptx::cta_group_2_t,
+                                   void*,
+                                   const void*,
+                                   const int32_t(&)[4],
+                                   uint64_t*,
+                                   const uint16_t&)>(cuda::ptx::cp_async_bulk_tensor));));
+#endif // __cccl_ptx_isa >= 800
+
 #if __cccl_ptx_isa >= 800
   NV_IF_TARGET(
     NV_HAS_FEATURE_SM_90a,
     (
         // cp.async.bulk.tensor.5d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.multicast::cluster [dstMem],
-        // [tensorMap, tensorCoords], [smem_bar], ctaMask; // 2e.
+        // [tensorMap, tensorCoords], [smem_bar], ctaMask;
         * fn_ptr++ = reinterpret_cast<void*>(
           static_cast<void (*)(cuda::ptx::space_cluster_t,
                                cuda::ptx::space_global_t,
@@ -94,5 +410,84 @@ __global__ void test_cp_async_bulk_tensor_multicast(void** fn_ptr)
                                const int32_t(&)[5],
                                uint64_t*,
                                const uint16_t&)>(cuda::ptx::cp_async_bulk_tensor));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // cp.async.bulk.tensor.5d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.multicast::cluster [dstMem],
+        // [tensorMap, tensorCoords], [smem_bar], ctaMask;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(cuda::ptx::space_cluster_t,
+                               cuda::ptx::space_global_t,
+                               void*,
+                               const void*,
+                               const int32_t(&)[5],
+                               uint64_t*,
+                               const uint16_t&)>(cuda::ptx::cp_async_bulk_tensor));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // cp.async.bulk.tensor.5d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.multicast::cluster [dstMem],
+        // [tensorMap, tensorCoords], [smem_bar], ctaMask;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(cuda::ptx::space_cluster_t,
+                               cuda::ptx::space_global_t,
+                               void*,
+                               const void*,
+                               const int32_t(&)[5],
+                               uint64_t*,
+                               const uint16_t&)>(cuda::ptx::cp_async_bulk_tensor));));
+#endif // __cccl_ptx_isa >= 800
+
+#if __cccl_ptx_isa >= 800
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // cp.async.bulk.tensor.5d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.multicast::cluster.cta_group::1
+        // [dstMem], [tensorMap, tensorCoords], [smem_bar], ctaMask;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(cuda::ptx::space_cluster_t,
+                               cuda::ptx::space_global_t,
+                               cuda::ptx::cta_group_1_t,
+                               void*,
+                               const void*,
+                               const int32_t(&)[5],
+                               uint64_t*,
+                               const uint16_t&)>(cuda::ptx::cp_async_bulk_tensor));
+          // cp.async.bulk.tensor.5d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.multicast::cluster.cta_group::2
+          // [dstMem], [tensorMap, tensorCoords], [smem_bar], ctaMask;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::space_cluster_t,
+                                   cuda::ptx::space_global_t,
+                                   cuda::ptx::cta_group_2_t,
+                                   void*,
+                                   const void*,
+                                   const int32_t(&)[5],
+                                   uint64_t*,
+                                   const uint16_t&)>(cuda::ptx::cp_async_bulk_tensor));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // cp.async.bulk.tensor.5d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.multicast::cluster.cta_group::1
+        // [dstMem], [tensorMap, tensorCoords], [smem_bar], ctaMask;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(cuda::ptx::space_cluster_t,
+                               cuda::ptx::space_global_t,
+                               cuda::ptx::cta_group_1_t,
+                               void*,
+                               const void*,
+                               const int32_t(&)[5],
+                               uint64_t*,
+                               const uint16_t&)>(cuda::ptx::cp_async_bulk_tensor));
+          // cp.async.bulk.tensor.5d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.multicast::cluster.cta_group::2
+          // [dstMem], [tensorMap, tensorCoords], [smem_bar], ctaMask;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::space_cluster_t,
+                                   cuda::ptx::space_global_t,
+                                   cuda::ptx::cta_group_2_t,
+                                   void*,
+                                   const void*,
+                                   const int32_t(&)[5],
+                                   uint64_t*,
+                                   const uint16_t&)>(cuda::ptx::cp_async_bulk_tensor));));
 #endif // __cccl_ptx_isa >= 800
 }
diff --git a/libcudacxx/test/libcudacxx/cuda/ptx/generated/cp_async_mbarrier_arrive.h b/libcudacxx/test/libcudacxx/cuda/ptx/generated/cp_async_mbarrier_arrive.h
new file mode 100644
index 00000000000..663c07b4121
--- /dev/null
+++ b/libcudacxx/test/libcudacxx/cuda/ptx/generated/cp_async_mbarrier_arrive.h
@@ -0,0 +1,26 @@
+// This file was automatically generated. Do not edit.
+
+// We use a special strategy to force the generation of the PTX. This is mainly
+// a fight against dead-code-elimination in the NVVM layer.
+//
+// The reason we need this strategy is because certain older versions of ptxas
+// segfault when a non-sensical sequence of PTX is generated. So instead, we try
+// to force the instantiation and compilation to PTX of all the overloads of the
+// PTX wrapping functions.
+//
+// We do this by writing a function pointer of each overload to the kernel
+// parameter `fn_ptr`.
+//
+// Because `fn_ptr` is possibly visible outside this translation unit, the
+// compiler must compile all the functions which are stored.
+
+__global__ void test_cp_async_mbarrier_arrive(void** fn_ptr)
+{
+#if __cccl_ptx_isa >= 700
+  NV_IF_TARGET(
+    NV_PROVIDES_SM_80,
+    (
+        // cp.async.mbarrier.arrive.b64 [addr];
+        * fn_ptr++ = reinterpret_cast<void*>(static_cast<void (*)(uint64_t*)>(cuda::ptx::cp_async_mbarrier_arrive));));
+#endif // __cccl_ptx_isa >= 700
+}
diff --git a/libcudacxx/test/libcudacxx/cuda/ptx/generated/cp_async_mbarrier_arrive_noinc.h b/libcudacxx/test/libcudacxx/cuda/ptx/generated/cp_async_mbarrier_arrive_noinc.h
new file mode 100644
index 00000000000..a089c727903
--- /dev/null
+++ b/libcudacxx/test/libcudacxx/cuda/ptx/generated/cp_async_mbarrier_arrive_noinc.h
@@ -0,0 +1,26 @@
+// This file was automatically generated. Do not edit.
+
+// We use a special strategy to force the generation of the PTX. This is mainly
+// a fight against dead-code-elimination in the NVVM layer.
+//
+// The reason we need this strategy is because certain older versions of ptxas
+// segfault when a non-sensical sequence of PTX is generated. So instead, we try
+// to force the instantiation and compilation to PTX of all the overloads of the
+// PTX wrapping functions.
+//
+// We do this by writing a function pointer of each overload to the kernel
+// parameter `fn_ptr`.
+//
+// Because `fn_ptr` is possibly visible outside this translation unit, the
+// compiler must compile all the functions which are stored.
+
+__global__ void test_cp_async_mbarrier_arrive_noinc(void** fn_ptr)
+{
+#if __cccl_ptx_isa >= 700
+  NV_IF_TARGET(NV_PROVIDES_SM_80,
+               (
+                   // cp.async.mbarrier.arrive.noinc.b64 [addr];
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(uint64_t*)>(cuda::ptx::cp_async_mbarrier_arrive_noinc));));
+#endif // __cccl_ptx_isa >= 700
+}
diff --git a/libcudacxx/test/libcudacxx/cuda/ptx/generated/elect_sync.h b/libcudacxx/test/libcudacxx/cuda/ptx/generated/elect_sync.h
new file mode 100644
index 00000000000..298225881d1
--- /dev/null
+++ b/libcudacxx/test/libcudacxx/cuda/ptx/generated/elect_sync.h
@@ -0,0 +1,26 @@
+// This file was automatically generated. Do not edit.
+
+// We use a special strategy to force the generation of the PTX. This is mainly
+// a fight against dead-code-elimination in the NVVM layer.
+//
+// The reason we need this strategy is because certain older versions of ptxas
+// segfault when a non-sensical sequence of PTX is generated. So instead, we try
+// to force the instantiation and compilation to PTX of all the overloads of the
+// PTX wrapping functions.
+//
+// We do this by writing a function pointer of each overload to the kernel
+// parameter `fn_ptr`.
+//
+// Because `fn_ptr` is possibly visible outside this translation unit, the
+// compiler must compile all the functions which are stored.
+
+__global__ void test_elect_sync(void** fn_ptr)
+{
+#if __cccl_ptx_isa >= 800
+  NV_IF_TARGET(
+    NV_PROVIDES_SM_90,
+    (
+        // elect.sync _|is_elected, membermask;
+        * fn_ptr++ = reinterpret_cast<void*>(static_cast<bool (*)(const uint32_t&)>(cuda::ptx::elect_sync));));
+#endif // __cccl_ptx_isa >= 800
+}
diff --git a/libcudacxx/test/libcudacxx/cuda/ptx/generated/fence.h b/libcudacxx/test/libcudacxx/cuda/ptx/generated/fence.h
index aecfcde5e01..0738677ed33 100644
--- a/libcudacxx/test/libcudacxx/cuda/ptx/generated/fence.h
+++ b/libcudacxx/test/libcudacxx/cuda/ptx/generated/fence.h
@@ -28,10 +28,24 @@ __global__ void test_fence(void** fn_ptr)
               static_cast<void (*)(cuda::ptx::sem_sc_t, cuda::ptx::scope_gpu_t)>(cuda::ptx::fence));
           // fence.sc.sys; // 1.
             * fn_ptr++ = reinterpret_cast<void*>(
-              static_cast<void (*)(cuda::ptx::sem_sc_t, cuda::ptx::scope_sys_t)>(cuda::ptx::fence));
-          // fence.acq_rel.cta; // 1.
-            * fn_ptr++ = reinterpret_cast<void*>(
-              static_cast<void (*)(cuda::ptx::sem_acq_rel_t, cuda::ptx::scope_cta_t)>(cuda::ptx::fence));
+              static_cast<void (*)(cuda::ptx::sem_sc_t, cuda::ptx::scope_sys_t)>(cuda::ptx::fence));));
+#endif // __cccl_ptx_isa >= 600
+
+#if __cccl_ptx_isa >= 780
+  NV_IF_TARGET(NV_PROVIDES_SM_90,
+               (
+                   // fence.sc.cluster; // 2.
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(cuda::ptx::sem_sc_t, cuda::ptx::scope_cluster_t)>(cuda::ptx::fence));));
+#endif // __cccl_ptx_isa >= 780
+
+#if __cccl_ptx_isa >= 600
+  NV_IF_TARGET(
+    NV_PROVIDES_SM_70,
+    (
+        // fence.acq_rel.cta; // 1.
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(cuda::ptx::sem_acq_rel_t, cuda::ptx::scope_cta_t)>(cuda::ptx::fence));
           // fence.acq_rel.gpu; // 1.
             * fn_ptr++ = reinterpret_cast<void*>(
               static_cast<void (*)(cuda::ptx::sem_acq_rel_t, cuda::ptx::scope_gpu_t)>(cuda::ptx::fence));
@@ -41,14 +55,46 @@ __global__ void test_fence(void** fn_ptr)
 #endif // __cccl_ptx_isa >= 600
 
 #if __cccl_ptx_isa >= 780
+  NV_IF_TARGET(NV_PROVIDES_SM_90,
+               (
+                   // fence.acq_rel.cluster; // 2.
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(cuda::ptx::sem_acq_rel_t, cuda::ptx::scope_cluster_t)>(cuda::ptx::fence));));
+#endif // __cccl_ptx_isa >= 780
+
+#if __cccl_ptx_isa >= 860
   NV_IF_TARGET(
     NV_PROVIDES_SM_90,
     (
-        // fence.sc.cluster; // 2.
+        // fence.acquire.cta;
         * fn_ptr++ = reinterpret_cast<void*>(
-          static_cast<void (*)(cuda::ptx::sem_sc_t, cuda::ptx::scope_cluster_t)>(cuda::ptx::fence));
-          // fence.acq_rel.cluster; // 2.
+          static_cast<void (*)(cuda::ptx::sem_acquire_t, cuda::ptx::scope_cta_t)>(cuda::ptx::fence));
+          // fence.acquire.cluster;
             * fn_ptr++ = reinterpret_cast<void*>(
-              static_cast<void (*)(cuda::ptx::sem_acq_rel_t, cuda::ptx::scope_cluster_t)>(cuda::ptx::fence));));
-#endif // __cccl_ptx_isa >= 780
+              static_cast<void (*)(cuda::ptx::sem_acquire_t, cuda::ptx::scope_cluster_t)>(cuda::ptx::fence));
+          // fence.acquire.gpu;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::sem_acquire_t, cuda::ptx::scope_gpu_t)>(cuda::ptx::fence));
+          // fence.acquire.sys;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::sem_acquire_t, cuda::ptx::scope_sys_t)>(cuda::ptx::fence));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_PROVIDES_SM_90,
+    (
+        // fence.release.cta;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(cuda::ptx::sem_release_t, cuda::ptx::scope_cta_t)>(cuda::ptx::fence));
+          // fence.release.cluster;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::sem_release_t, cuda::ptx::scope_cluster_t)>(cuda::ptx::fence));
+          // fence.release.gpu;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::sem_release_t, cuda::ptx::scope_gpu_t)>(cuda::ptx::fence));
+          // fence.release.sys;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::sem_release_t, cuda::ptx::scope_sys_t)>(cuda::ptx::fence));));
+#endif // __cccl_ptx_isa >= 860
 }
diff --git a/libcudacxx/test/libcudacxx/cuda/ptx/generated/fence_proxy_async_generic_sync_restrict.h b/libcudacxx/test/libcudacxx/cuda/ptx/generated/fence_proxy_async_generic_sync_restrict.h
new file mode 100644
index 00000000000..7af3a09ad2b
--- /dev/null
+++ b/libcudacxx/test/libcudacxx/cuda/ptx/generated/fence_proxy_async_generic_sync_restrict.h
@@ -0,0 +1,38 @@
+// This file was automatically generated. Do not edit.
+
+// We use a special strategy to force the generation of the PTX. This is mainly
+// a fight against dead-code-elimination in the NVVM layer.
+//
+// The reason we need this strategy is because certain older versions of ptxas
+// segfault when a non-sensical sequence of PTX is generated. So instead, we try
+// to force the instantiation and compilation to PTX of all the overloads of the
+// PTX wrapping functions.
+//
+// We do this by writing a function pointer of each overload to the kernel
+// parameter `fn_ptr`.
+//
+// Because `fn_ptr` is possibly visible outside this translation unit, the
+// compiler must compile all the functions which are stored.
+
+__global__ void test_fence_proxy_async_generic_sync_restrict(void** fn_ptr)
+{
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_PROVIDES_SM_90,
+    (
+        // fence.proxy.async::generic.acquire.sync_restrict::shared::cluster.cluster;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(cuda::ptx::sem_acquire_t, cuda::ptx::space_cluster_t, cuda::ptx::scope_cluster_t)>(
+            cuda::ptx::fence_proxy_async_generic_sync_restrict));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_PROVIDES_SM_90,
+    (
+        // fence.proxy.async::generic.release.sync_restrict::shared::cta.cluster;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(cuda::ptx::sem_release_t, cuda::ptx::space_shared_t, cuda::ptx::scope_cluster_t)>(
+            cuda::ptx::fence_proxy_async_generic_sync_restrict));));
+#endif // __cccl_ptx_isa >= 860
+}
diff --git a/libcudacxx/test/libcudacxx/cuda/ptx/generated/fence_sync_restrict.h b/libcudacxx/test/libcudacxx/cuda/ptx/generated/fence_sync_restrict.h
new file mode 100644
index 00000000000..c673d840428
--- /dev/null
+++ b/libcudacxx/test/libcudacxx/cuda/ptx/generated/fence_sync_restrict.h
@@ -0,0 +1,38 @@
+// This file was automatically generated. Do not edit.
+
+// We use a special strategy to force the generation of the PTX. This is mainly
+// a fight against dead-code-elimination in the NVVM layer.
+//
+// The reason we need this strategy is because certain older versions of ptxas
+// segfault when a non-sensical sequence of PTX is generated. So instead, we try
+// to force the instantiation and compilation to PTX of all the overloads of the
+// PTX wrapping functions.
+//
+// We do this by writing a function pointer of each overload to the kernel
+// parameter `fn_ptr`.
+//
+// Because `fn_ptr` is possibly visible outside this translation unit, the
+// compiler must compile all the functions which are stored.
+
+__global__ void test_fence_sync_restrict(void** fn_ptr)
+{
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_PROVIDES_SM_90,
+    (
+        // fence.acquire.sync_restrict::shared::cluster.cluster;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(cuda::ptx::sem_acquire_t, cuda::ptx::space_cluster_t, cuda::ptx::scope_cluster_t)>(
+            cuda::ptx::fence_sync_restrict));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_PROVIDES_SM_90,
+    (
+        // fence.release.sync_restrict::shared::cta.cluster;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(cuda::ptx::sem_release_t, cuda::ptx::space_shared_t, cuda::ptx::scope_cluster_t)>(
+            cuda::ptx::fence_sync_restrict));));
+#endif // __cccl_ptx_isa >= 860
+}
diff --git a/libcudacxx/test/libcudacxx/cuda/ptx/generated/mapa.h b/libcudacxx/test/libcudacxx/cuda/ptx/generated/mapa.h
new file mode 100644
index 00000000000..9160be1fe2d
--- /dev/null
+++ b/libcudacxx/test/libcudacxx/cuda/ptx/generated/mapa.h
@@ -0,0 +1,27 @@
+// This file was automatically generated. Do not edit.
+
+// We use a special strategy to force the generation of the PTX. This is mainly
+// a fight against dead-code-elimination in the NVVM layer.
+//
+// The reason we need this strategy is because certain older versions of ptxas
+// segfault when a non-sensical sequence of PTX is generated. So instead, we try
+// to force the instantiation and compilation to PTX of all the overloads of the
+// PTX wrapping functions.
+//
+// We do this by writing a function pointer of each overload to the kernel
+// parameter `fn_ptr`.
+//
+// Because `fn_ptr` is possibly visible outside this translation unit, the
+// compiler must compile all the functions which are stored.
+
+__global__ void test_mapa(void** fn_ptr)
+{
+#if __cccl_ptx_isa >= 780
+  NV_IF_TARGET(
+    NV_PROVIDES_SM_90,
+    (
+        // mapa.shared::cluster.u32  dest, addr, target_cta;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<uint64_t* (*) (cuda::ptx::space_cluster_t, const uint64_t*, uint32_t)>(cuda::ptx::mapa));));
+#endif // __cccl_ptx_isa >= 780
+}
diff --git a/libcudacxx/test/libcudacxx/cuda/ptx/generated/mbarrier_arrive.h b/libcudacxx/test/libcudacxx/cuda/ptx/generated/mbarrier_arrive.h
index 3cddcb3b54c..d32773c118d 100644
--- a/libcudacxx/test/libcudacxx/cuda/ptx/generated/mbarrier_arrive.h
+++ b/libcudacxx/test/libcudacxx/cuda/ptx/generated/mbarrier_arrive.h
@@ -87,4 +87,60 @@ __global__ void test_mbarrier_arrive(void** fn_ptr)
             cuda::ptx::sem_release_t, cuda::ptx::scope_cluster_t, cuda::ptx::space_cluster_t, uint64_t*, const uint32_t&)>(
             cuda::ptx::mbarrier_arrive));));
 #endif // __cccl_ptx_isa >= 800
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_PROVIDES_SM_90,
+    (
+        // mbarrier.arrive.relaxed.cta.shared::cta.b64 state, [addr], count;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<uint64_t (*)(
+            cuda::ptx::space_shared_t, cuda::ptx::sem_relaxed_t, cuda::ptx::scope_cta_t, uint64_t*, const uint32_t&)>(
+            cuda::ptx::mbarrier_arrive));
+          // mbarrier.arrive.relaxed.cluster.shared::cta.b64 state, [addr], count;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<uint64_t (*)(cuda::ptx::space_shared_t,
+                                       cuda::ptx::sem_relaxed_t,
+                                       cuda::ptx::scope_cluster_t,
+                                       uint64_t*,
+                                       const uint32_t&)>(cuda::ptx::mbarrier_arrive));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_PROVIDES_SM_90,
+    (
+        // mbarrier.arrive.relaxed.cta.shared::cta.b64 state, [addr];
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<uint64_t (*)(
+            cuda::ptx::space_shared_t, cuda::ptx::sem_relaxed_t, cuda::ptx::scope_cta_t, uint64_t*)>(
+            cuda::ptx::mbarrier_arrive));
+          // mbarrier.arrive.relaxed.cluster.shared::cta.b64 state, [addr];
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<uint64_t (*)(
+                cuda::ptx::space_shared_t, cuda::ptx::sem_relaxed_t, cuda::ptx::scope_cluster_t, uint64_t*)>(
+                cuda::ptx::mbarrier_arrive));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_PROVIDES_SM_90,
+    (
+        // mbarrier.arrive.relaxed.cluster.shared::cluster.b64 _, [addr], count;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(
+            cuda::ptx::space_cluster_t, cuda::ptx::sem_relaxed_t, cuda::ptx::scope_cluster_t, uint64_t*, const uint32_t&)>(
+            cuda::ptx::mbarrier_arrive));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_PROVIDES_SM_90,
+    (
+        // mbarrier.arrive.relaxed.cluster.shared::cluster.b64 _, [addr];
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(
+            cuda::ptx::space_cluster_t, cuda::ptx::sem_relaxed_t, cuda::ptx::scope_cluster_t, uint64_t*)>(
+            cuda::ptx::mbarrier_arrive));));
+#endif // __cccl_ptx_isa >= 860
 }
diff --git a/libcudacxx/test/libcudacxx/cuda/ptx/generated/mbarrier_arrive_expect_tx.h b/libcudacxx/test/libcudacxx/cuda/ptx/generated/mbarrier_arrive_expect_tx.h
index a2ef4b619bb..8ef925662ac 100644
--- a/libcudacxx/test/libcudacxx/cuda/ptx/generated/mbarrier_arrive_expect_tx.h
+++ b/libcudacxx/test/libcudacxx/cuda/ptx/generated/mbarrier_arrive_expect_tx.h
@@ -44,4 +44,33 @@ __global__ void test_mbarrier_arrive_expect_tx(void** fn_ptr)
             cuda::ptx::sem_release_t, cuda::ptx::scope_cluster_t, cuda::ptx::space_cluster_t, uint64_t*, const uint32_t&)>(
             cuda::ptx::mbarrier_arrive_expect_tx));));
 #endif // __cccl_ptx_isa >= 800
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_PROVIDES_SM_90,
+    (
+        // mbarrier.arrive.expect_tx.relaxed.cta.shared::cta.b64 state, [addr], txCount;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<uint64_t (*)(
+            cuda::ptx::space_shared_t, cuda::ptx::sem_relaxed_t, cuda::ptx::scope_cta_t, uint64_t*, const uint32_t&)>(
+            cuda::ptx::mbarrier_arrive_expect_tx));
+          // mbarrier.arrive.expect_tx.relaxed.cluster.shared::cta.b64 state, [addr], txCount;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<uint64_t (*)(cuda::ptx::space_shared_t,
+                                       cuda::ptx::sem_relaxed_t,
+                                       cuda::ptx::scope_cluster_t,
+                                       uint64_t*,
+                                       const uint32_t&)>(cuda::ptx::mbarrier_arrive_expect_tx));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_PROVIDES_SM_90,
+    (
+        // mbarrier.arrive.expect_tx.relaxed.cluster.shared::cluster.b64 _, [addr], txCount;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(
+            cuda::ptx::space_cluster_t, cuda::ptx::sem_relaxed_t, cuda::ptx::scope_cluster_t, uint64_t*, const uint32_t&)>(
+            cuda::ptx::mbarrier_arrive_expect_tx));));
+#endif // __cccl_ptx_isa >= 860
 }
diff --git a/libcudacxx/test/libcudacxx/cuda/ptx/generated/mbarrier_expect_tx.h b/libcudacxx/test/libcudacxx/cuda/ptx/generated/mbarrier_expect_tx.h
new file mode 100644
index 00000000000..8dd3b6a2037
--- /dev/null
+++ b/libcudacxx/test/libcudacxx/cuda/ptx/generated/mbarrier_expect_tx.h
@@ -0,0 +1,50 @@
+// This file was automatically generated. Do not edit.
+
+// We use a special strategy to force the generation of the PTX. This is mainly
+// a fight against dead-code-elimination in the NVVM layer.
+//
+// The reason we need this strategy is because certain older versions of ptxas
+// segfault when a non-sensical sequence of PTX is generated. So instead, we try
+// to force the instantiation and compilation to PTX of all the overloads of the
+// PTX wrapping functions.
+//
+// We do this by writing a function pointer of each overload to the kernel
+// parameter `fn_ptr`.
+//
+// Because `fn_ptr` is possibly visible outside this translation unit, the
+// compiler must compile all the functions which are stored.
+
+__global__ void test_mbarrier_expect_tx(void** fn_ptr)
+{
+#if __cccl_ptx_isa >= 800
+  NV_IF_TARGET(
+    NV_PROVIDES_SM_90,
+    (
+        // mbarrier.expect_tx.relaxed.cta.shared::cta.b64 [addr], txCount; // 1.
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(
+            cuda::ptx::sem_relaxed_t, cuda::ptx::scope_cta_t, cuda::ptx::space_shared_t, uint64_t*, uint32_t)>(
+            cuda::ptx::mbarrier_expect_tx));
+          // mbarrier.expect_tx.relaxed.cluster.shared::cta.b64 [addr], txCount; // 1.
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::sem_relaxed_t, cuda::ptx::scope_cluster_t, cuda::ptx::space_shared_t, uint64_t*, uint32_t)>(
+                cuda::ptx::mbarrier_expect_tx));));
+#endif // __cccl_ptx_isa >= 800
+
+#if __cccl_ptx_isa >= 800
+  NV_IF_TARGET(
+    NV_PROVIDES_SM_90,
+    (
+        // mbarrier.expect_tx.relaxed.cta.shared::cluster.b64 [addr], txCount; // 2.
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(
+            cuda::ptx::sem_relaxed_t, cuda::ptx::scope_cta_t, cuda::ptx::space_cluster_t, uint64_t*, uint32_t)>(
+            cuda::ptx::mbarrier_expect_tx));
+          // mbarrier.expect_tx.relaxed.cluster.shared::cluster.b64 [addr], txCount; // 2.
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::sem_relaxed_t, cuda::ptx::scope_cluster_t, cuda::ptx::space_cluster_t, uint64_t*, uint32_t)>(
+                cuda::ptx::mbarrier_expect_tx));));
+#endif // __cccl_ptx_isa >= 800
+}
diff --git a/libcudacxx/test/libcudacxx/cuda/ptx/generated/mbarrier_test_wait.h b/libcudacxx/test/libcudacxx/cuda/ptx/generated/mbarrier_test_wait.h
new file mode 100644
index 00000000000..c9c0d0d14fb
--- /dev/null
+++ b/libcudacxx/test/libcudacxx/cuda/ptx/generated/mbarrier_test_wait.h
@@ -0,0 +1,55 @@
+// This file was automatically generated. Do not edit.
+
+// We use a special strategy to force the generation of the PTX. This is mainly
+// a fight against dead-code-elimination in the NVVM layer.
+//
+// The reason we need this strategy is because certain older versions of ptxas
+// segfault when a non-sensical sequence of PTX is generated. So instead, we try
+// to force the instantiation and compilation to PTX of all the overloads of the
+// PTX wrapping functions.
+//
+// We do this by writing a function pointer of each overload to the kernel
+// parameter `fn_ptr`.
+//
+// Because `fn_ptr` is possibly visible outside this translation unit, the
+// compiler must compile all the functions which are stored.
+
+__global__ void test_mbarrier_test_wait(void** fn_ptr)
+{
+#if __cccl_ptx_isa >= 700
+  NV_IF_TARGET(NV_PROVIDES_SM_80,
+               (
+                   // mbarrier.test_wait.shared.b64 waitComplete, [addr], state; // 1.
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<bool (*)(uint64_t*, const uint64_t&)>(cuda::ptx::mbarrier_test_wait));));
+#endif // __cccl_ptx_isa >= 700
+
+#if __cccl_ptx_isa >= 800
+  NV_IF_TARGET(
+    NV_PROVIDES_SM_90,
+    (
+        // mbarrier.test_wait.acquire.cta.shared::cta.b64        waitComplete, [addr], state; // 2.
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<bool (*)(cuda::ptx::sem_acquire_t, cuda::ptx::scope_cta_t, uint64_t*, const uint64_t&)>(
+            cuda::ptx::mbarrier_test_wait));
+          // mbarrier.test_wait.acquire.cluster.shared::cta.b64        waitComplete, [addr], state; // 2.
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<bool (*)(cuda::ptx::sem_acquire_t, cuda::ptx::scope_cluster_t, uint64_t*, const uint64_t&)>(
+                cuda::ptx::mbarrier_test_wait));));
+#endif // __cccl_ptx_isa >= 800
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_PROVIDES_SM_90,
+    (
+        // mbarrier.test_wait.relaxed.cta.shared::cta.b64 waitComplete, [addr], state;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(cuda::ptx::sem_relaxed_t, cuda::ptx::scope_cta_t, bool, uint64_t*, const uint64_t&)>(
+            cuda::ptx::mbarrier_test_wait));
+          // mbarrier.test_wait.relaxed.cluster.shared::cta.b64 waitComplete, [addr], state;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::sem_relaxed_t, cuda::ptx::scope_cluster_t, bool, uint64_t*, const uint64_t&)>(
+                cuda::ptx::mbarrier_test_wait));));
+#endif // __cccl_ptx_isa >= 860
+}
diff --git a/libcudacxx/test/libcudacxx/cuda/ptx/generated/mbarrier_test_wait_parity.h b/libcudacxx/test/libcudacxx/cuda/ptx/generated/mbarrier_test_wait_parity.h
new file mode 100644
index 00000000000..f44c0554308
--- /dev/null
+++ b/libcudacxx/test/libcudacxx/cuda/ptx/generated/mbarrier_test_wait_parity.h
@@ -0,0 +1,55 @@
+// This file was automatically generated. Do not edit.
+
+// We use a special strategy to force the generation of the PTX. This is mainly
+// a fight against dead-code-elimination in the NVVM layer.
+//
+// The reason we need this strategy is because certain older versions of ptxas
+// segfault when a non-sensical sequence of PTX is generated. So instead, we try
+// to force the instantiation and compilation to PTX of all the overloads of the
+// PTX wrapping functions.
+//
+// We do this by writing a function pointer of each overload to the kernel
+// parameter `fn_ptr`.
+//
+// Because `fn_ptr` is possibly visible outside this translation unit, the
+// compiler must compile all the functions which are stored.
+
+__global__ void test_mbarrier_test_wait_parity(void** fn_ptr)
+{
+#if __cccl_ptx_isa >= 710
+  NV_IF_TARGET(NV_PROVIDES_SM_80,
+               (
+                   // mbarrier.test_wait.parity.shared.b64 waitComplete, [addr], phaseParity; // 3.
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<bool (*)(uint64_t*, const uint32_t&)>(cuda::ptx::mbarrier_test_wait_parity));));
+#endif // __cccl_ptx_isa >= 710
+
+#if __cccl_ptx_isa >= 800
+  NV_IF_TARGET(
+    NV_PROVIDES_SM_90,
+    (
+        // mbarrier.test_wait.parity.acquire.cta.shared::cta.b64 waitComplete, [addr], phaseParity; // 4.
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<bool (*)(cuda::ptx::sem_acquire_t, cuda::ptx::scope_cta_t, uint64_t*, const uint32_t&)>(
+            cuda::ptx::mbarrier_test_wait_parity));
+          // mbarrier.test_wait.parity.acquire.cluster.shared::cta.b64 waitComplete, [addr], phaseParity; // 4.
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<bool (*)(cuda::ptx::sem_acquire_t, cuda::ptx::scope_cluster_t, uint64_t*, const uint32_t&)>(
+                cuda::ptx::mbarrier_test_wait_parity));));
+#endif // __cccl_ptx_isa >= 800
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_PROVIDES_SM_90,
+    (
+        // mbarrier.test_wait.parity.relaxed.cta.shared::cta.b64 waitComplete, [addr], phaseParity;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(cuda::ptx::sem_relaxed_t, cuda::ptx::scope_cta_t, bool, uint64_t*, const uint32_t&)>(
+            cuda::ptx::mbarrier_test_wait_parity));
+          // mbarrier.test_wait.parity.relaxed.cluster.shared::cta.b64 waitComplete, [addr], phaseParity;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::sem_relaxed_t, cuda::ptx::scope_cluster_t, bool, uint64_t*, const uint32_t&)>(
+                cuda::ptx::mbarrier_test_wait_parity));));
+#endif // __cccl_ptx_isa >= 860
+}
diff --git a/libcudacxx/test/libcudacxx/cuda/ptx/generated/mbarrier_try_wait.h b/libcudacxx/test/libcudacxx/cuda/ptx/generated/mbarrier_try_wait.h
index 00166f8172c..1a1b347751c 100644
--- a/libcudacxx/test/libcudacxx/cuda/ptx/generated/mbarrier_try_wait.h
+++ b/libcudacxx/test/libcudacxx/cuda/ptx/generated/mbarrier_try_wait.h
@@ -66,4 +66,35 @@ __global__ void test_mbarrier_try_wait(void** fn_ptr)
                 cuda::ptx::sem_acquire_t, cuda::ptx::scope_cluster_t, uint64_t*, const uint64_t&, const uint32_t&)>(
                 cuda::ptx::mbarrier_try_wait));));
 #endif // __cccl_ptx_isa >= 800
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_PROVIDES_SM_90,
+    (
+        // mbarrier.try_wait.relaxed.cta.shared::cta.b64 waitComplete, [addr], state, suspendTimeHint;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(
+            cuda::ptx::sem_relaxed_t, cuda::ptx::scope_cta_t, bool, uint64_t*, const uint64_t&, const uint32_t&)>(
+            cuda::ptx::mbarrier_try_wait));
+          // mbarrier.try_wait.relaxed.cluster.shared::cta.b64 waitComplete, [addr], state, suspendTimeHint;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::sem_relaxed_t, cuda::ptx::scope_cluster_t, bool, uint64_t*, const uint64_t&, const uint32_t&)>(
+                cuda::ptx::mbarrier_try_wait));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_PROVIDES_SM_90,
+    (
+        // mbarrier.try_wait.relaxed.cta.shared::cta.b64 waitComplete, [addr], state;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(cuda::ptx::sem_relaxed_t, cuda::ptx::scope_cta_t, bool, uint64_t*, const uint64_t&)>(
+            cuda::ptx::mbarrier_try_wait));
+          // mbarrier.try_wait.relaxed.cluster.shared::cta.b64 waitComplete, [addr], state;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::sem_relaxed_t, cuda::ptx::scope_cluster_t, bool, uint64_t*, const uint64_t&)>(
+                cuda::ptx::mbarrier_try_wait));));
+#endif // __cccl_ptx_isa >= 860
 }
diff --git a/libcudacxx/test/libcudacxx/cuda/ptx/generated/mbarrier_try_wait_parity.h b/libcudacxx/test/libcudacxx/cuda/ptx/generated/mbarrier_try_wait_parity.h
index 8aa588fbab0..4a5ef3e926f 100644
--- a/libcudacxx/test/libcudacxx/cuda/ptx/generated/mbarrier_try_wait_parity.h
+++ b/libcudacxx/test/libcudacxx/cuda/ptx/generated/mbarrier_try_wait_parity.h
@@ -65,4 +65,36 @@ __global__ void test_mbarrier_try_wait_parity(void** fn_ptr)
                 cuda::ptx::sem_acquire_t, cuda::ptx::scope_cluster_t, uint64_t*, const uint32_t&, const uint32_t&)>(
                 cuda::ptx::mbarrier_try_wait_parity));));
 #endif // __cccl_ptx_isa >= 800
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_PROVIDES_SM_90,
+    (
+        // mbarrier.try_wait.parity.relaxed.cta.shared::cta.b64 waitComplete, [addr], phaseParity, suspendTimeHint;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(
+            cuda::ptx::sem_relaxed_t, cuda::ptx::scope_cta_t, bool, uint64_t*, const uint32_t&, const uint32_t&)>(
+            cuda::ptx::mbarrier_try_wait_parity));
+          // mbarrier.try_wait.parity.relaxed.cluster.shared::cta.b64 waitComplete, [addr], phaseParity,
+          // suspendTimeHint;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::sem_relaxed_t, cuda::ptx::scope_cluster_t, bool, uint64_t*, const uint32_t&, const uint32_t&)>(
+                cuda::ptx::mbarrier_try_wait_parity));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_PROVIDES_SM_90,
+    (
+        // mbarrier.try_wait.parity.relaxed.cta.shared::cta.b64 waitComplete, [addr], phaseParity;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(cuda::ptx::sem_relaxed_t, cuda::ptx::scope_cta_t, bool, uint64_t*, const uint32_t&)>(
+            cuda::ptx::mbarrier_try_wait_parity));
+          // mbarrier.try_wait.parity.relaxed.cluster.shared::cta.b64 waitComplete, [addr], phaseParity;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::sem_relaxed_t, cuda::ptx::scope_cluster_t, bool, uint64_t*, const uint32_t&)>(
+                cuda::ptx::mbarrier_try_wait_parity));));
+#endif // __cccl_ptx_isa >= 860
 }
diff --git a/libcudacxx/test/libcudacxx/cuda/ptx/generated/mbarrier_wait.h b/libcudacxx/test/libcudacxx/cuda/ptx/generated/mbarrier_wait.h
deleted file mode 100644
index 80129e5016c..00000000000
--- a/libcudacxx/test/libcudacxx/cuda/ptx/generated/mbarrier_wait.h
+++ /dev/null
@@ -1,24 +0,0 @@
-__global__ void test_mbarrier_test_wait(void** fn_ptr)
-{
-#if __cccl_ptx_isa >= 700
-  NV_IF_TARGET(NV_PROVIDES_SM_80,
-               (
-                   // mbarrier.test_wait.shared.b64 waitComplete, [addr], state; // 1.
-                   * fn_ptr++ = reinterpret_cast<void*>(
-                     static_cast<bool (*)(uint64_t*, const uint64_t&)>(cuda::ptx::mbarrier_test_wait));));
-#endif // __cccl_ptx_isa >= 700
-
-#if __cccl_ptx_isa >= 800
-  NV_IF_TARGET(
-    NV_PROVIDES_SM_90,
-    (
-        // mbarrier.test_wait.acquire.cta.shared::cta.b64        waitComplete, [addr], state; // 2.
-        * fn_ptr++ = reinterpret_cast<void*>(
-          static_cast<bool (*)(cuda::ptx::sem_acquire_t, cuda::ptx::scope_cta_t, uint64_t*, const uint64_t&)>(
-            cuda::ptx::mbarrier_test_wait));
-          // mbarrier.test_wait.acquire.cluster.shared::cta.b64        waitComplete, [addr], state; // 2.
-            * fn_ptr++ = reinterpret_cast<void*>(
-              static_cast<bool (*)(cuda::ptx::sem_acquire_t, cuda::ptx::scope_cluster_t, uint64_t*, const uint64_t&)>(
-                cuda::ptx::mbarrier_test_wait));));
-#endif // __cccl_ptx_isa >= 800
-}
diff --git a/libcudacxx/test/libcudacxx/cuda/ptx/generated/mbarrier_wait_parity.h b/libcudacxx/test/libcudacxx/cuda/ptx/generated/mbarrier_wait_parity.h
deleted file mode 100644
index 30902c58905..00000000000
--- a/libcudacxx/test/libcudacxx/cuda/ptx/generated/mbarrier_wait_parity.h
+++ /dev/null
@@ -1,24 +0,0 @@
-__global__ void test_mbarrier_test_wait_parity(void** fn_ptr)
-{
-#if __cccl_ptx_isa >= 710
-  NV_IF_TARGET(NV_PROVIDES_SM_80,
-               (
-                   // mbarrier.test_wait.parity.shared.b64 waitComplete, [addr], phaseParity; // 3.
-                   * fn_ptr++ = reinterpret_cast<void*>(
-                     static_cast<bool (*)(uint64_t*, const uint32_t&)>(cuda::ptx::mbarrier_test_wait_parity));));
-#endif // __cccl_ptx_isa >= 710
-
-#if __cccl_ptx_isa >= 800
-  NV_IF_TARGET(
-    NV_PROVIDES_SM_90,
-    (
-        // mbarrier.test_wait.parity.acquire.cta.shared::cta.b64 waitComplete, [addr], phaseParity; // 4.
-        * fn_ptr++ = reinterpret_cast<void*>(
-          static_cast<bool (*)(cuda::ptx::sem_acquire_t, cuda::ptx::scope_cta_t, uint64_t*, const uint32_t&)>(
-            cuda::ptx::mbarrier_test_wait_parity));
-          // mbarrier.test_wait.parity.acquire.cluster.shared::cta.b64 waitComplete, [addr], phaseParity; // 4.
-            * fn_ptr++ = reinterpret_cast<void*>(
-              static_cast<bool (*)(cuda::ptx::sem_acquire_t, cuda::ptx::scope_cluster_t, uint64_t*, const uint32_t&)>(
-                cuda::ptx::mbarrier_test_wait_parity));));
-#endif // __cccl_ptx_isa >= 800
-}
diff --git a/libcudacxx/test/libcudacxx/cuda/ptx/generated/multimem_ld_reduce.h b/libcudacxx/test/libcudacxx/cuda/ptx/generated/multimem_ld_reduce.h
new file mode 100644
index 00000000000..c0259451a1b
--- /dev/null
+++ b/libcudacxx/test/libcudacxx/cuda/ptx/generated/multimem_ld_reduce.h
@@ -0,0 +1,1020 @@
+// This file was automatically generated. Do not edit.
+
+// We use a special strategy to force the generation of the PTX. This is mainly
+// a fight against dead-code-elimination in the NVVM layer.
+//
+// The reason we need this strategy is because certain older versions of ptxas
+// segfault when a non-sensical sequence of PTX is generated. So instead, we try
+// to force the instantiation and compilation to PTX of all the overloads of the
+// PTX wrapping functions.
+//
+// We do this by writing a function pointer of each overload to the kernel
+// parameter `fn_ptr`.
+//
+// Because `fn_ptr` is possibly visible outside this translation unit, the
+// compiler must compile all the functions which are stored.
+
+__global__ void test_multimem_ld_reduce(void** fn_ptr)
+{
+#if __cccl_ptx_isa >= 810
+  NV_IF_TARGET(
+    NV_PROVIDES_SM_90,
+    (
+        // multimem.ld_reduce.weak.global.min.u32 dest, [addr];
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<uint32_t (*)(cuda::ptx::sem_weak_t, cuda::ptx::op_min_t, const uint32_t*)>(
+            cuda::ptx::multimem_ld_reduce));));
+#endif // __cccl_ptx_isa >= 810
+
+#if __cccl_ptx_isa >= 810
+  NV_IF_TARGET(
+    NV_PROVIDES_SM_90,
+    (
+        // multimem.ld_reduce.relaxed.cta.global.min.u32 dest, [addr];
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<uint32_t (*)(
+            cuda::ptx::sem_relaxed_t, cuda::ptx::scope_cta_t, cuda::ptx::op_min_t, const uint32_t*)>(
+            cuda::ptx::multimem_ld_reduce));
+          // multimem.ld_reduce.relaxed.cluster.global.min.u32 dest, [addr];
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<uint32_t (*)(
+                cuda::ptx::sem_relaxed_t, cuda::ptx::scope_cluster_t, cuda::ptx::op_min_t, const uint32_t*)>(
+                cuda::ptx::multimem_ld_reduce));
+          // multimem.ld_reduce.relaxed.gpu.global.min.u32 dest, [addr];
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<uint32_t (*)(
+                cuda::ptx::sem_relaxed_t, cuda::ptx::scope_gpu_t, cuda::ptx::op_min_t, const uint32_t*)>(
+                cuda::ptx::multimem_ld_reduce));
+          // multimem.ld_reduce.relaxed.sys.global.min.u32 dest, [addr];
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<uint32_t (*)(
+                cuda::ptx::sem_relaxed_t, cuda::ptx::scope_sys_t, cuda::ptx::op_min_t, const uint32_t*)>(
+                cuda::ptx::multimem_ld_reduce));
+          // multimem.ld_reduce.acquire.cta.global.min.u32 dest, [addr];
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<uint32_t (*)(
+                cuda::ptx::sem_acquire_t, cuda::ptx::scope_cta_t, cuda::ptx::op_min_t, const uint32_t*)>(
+                cuda::ptx::multimem_ld_reduce));
+          // multimem.ld_reduce.acquire.cluster.global.min.u32 dest, [addr];
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<uint32_t (*)(
+                cuda::ptx::sem_acquire_t, cuda::ptx::scope_cluster_t, cuda::ptx::op_min_t, const uint32_t*)>(
+                cuda::ptx::multimem_ld_reduce));
+          // multimem.ld_reduce.acquire.gpu.global.min.u32 dest, [addr];
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<uint32_t (*)(
+                cuda::ptx::sem_acquire_t, cuda::ptx::scope_gpu_t, cuda::ptx::op_min_t, const uint32_t*)>(
+                cuda::ptx::multimem_ld_reduce));
+          // multimem.ld_reduce.acquire.sys.global.min.u32 dest, [addr];
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<uint32_t (*)(
+                cuda::ptx::sem_acquire_t, cuda::ptx::scope_sys_t, cuda::ptx::op_min_t, const uint32_t*)>(
+                cuda::ptx::multimem_ld_reduce));));
+#endif // __cccl_ptx_isa >= 810
+
+#if __cccl_ptx_isa >= 810
+  NV_IF_TARGET(
+    NV_PROVIDES_SM_90,
+    (
+        // multimem.ld_reduce.weak.global.min.u64 dest, [addr];
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<uint64_t (*)(cuda::ptx::sem_weak_t, cuda::ptx::op_min_t, const uint64_t*)>(
+            cuda::ptx::multimem_ld_reduce));));
+#endif // __cccl_ptx_isa >= 810
+
+#if __cccl_ptx_isa >= 810
+  NV_IF_TARGET(
+    NV_PROVIDES_SM_90,
+    (
+        // multimem.ld_reduce.relaxed.cta.global.min.u64 dest, [addr];
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<uint64_t (*)(
+            cuda::ptx::sem_relaxed_t, cuda::ptx::scope_cta_t, cuda::ptx::op_min_t, const uint64_t*)>(
+            cuda::ptx::multimem_ld_reduce));
+          // multimem.ld_reduce.relaxed.cluster.global.min.u64 dest, [addr];
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<uint64_t (*)(
+                cuda::ptx::sem_relaxed_t, cuda::ptx::scope_cluster_t, cuda::ptx::op_min_t, const uint64_t*)>(
+                cuda::ptx::multimem_ld_reduce));
+          // multimem.ld_reduce.relaxed.gpu.global.min.u64 dest, [addr];
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<uint64_t (*)(
+                cuda::ptx::sem_relaxed_t, cuda::ptx::scope_gpu_t, cuda::ptx::op_min_t, const uint64_t*)>(
+                cuda::ptx::multimem_ld_reduce));
+          // multimem.ld_reduce.relaxed.sys.global.min.u64 dest, [addr];
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<uint64_t (*)(
+                cuda::ptx::sem_relaxed_t, cuda::ptx::scope_sys_t, cuda::ptx::op_min_t, const uint64_t*)>(
+                cuda::ptx::multimem_ld_reduce));
+          // multimem.ld_reduce.acquire.cta.global.min.u64 dest, [addr];
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<uint64_t (*)(
+                cuda::ptx::sem_acquire_t, cuda::ptx::scope_cta_t, cuda::ptx::op_min_t, const uint64_t*)>(
+                cuda::ptx::multimem_ld_reduce));
+          // multimem.ld_reduce.acquire.cluster.global.min.u64 dest, [addr];
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<uint64_t (*)(
+                cuda::ptx::sem_acquire_t, cuda::ptx::scope_cluster_t, cuda::ptx::op_min_t, const uint64_t*)>(
+                cuda::ptx::multimem_ld_reduce));
+          // multimem.ld_reduce.acquire.gpu.global.min.u64 dest, [addr];
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<uint64_t (*)(
+                cuda::ptx::sem_acquire_t, cuda::ptx::scope_gpu_t, cuda::ptx::op_min_t, const uint64_t*)>(
+                cuda::ptx::multimem_ld_reduce));
+          // multimem.ld_reduce.acquire.sys.global.min.u64 dest, [addr];
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<uint64_t (*)(
+                cuda::ptx::sem_acquire_t, cuda::ptx::scope_sys_t, cuda::ptx::op_min_t, const uint64_t*)>(
+                cuda::ptx::multimem_ld_reduce));));
+#endif // __cccl_ptx_isa >= 810
+
+#if __cccl_ptx_isa >= 810
+  NV_IF_TARGET(
+    NV_PROVIDES_SM_90,
+    (
+        // multimem.ld_reduce.weak.global.min.s32 dest, [addr];
+        * fn_ptr++ =
+          reinterpret_cast<void*>(static_cast<int32_t (*)(cuda::ptx::sem_weak_t, cuda::ptx::op_min_t, const int32_t*)>(
+            cuda::ptx::multimem_ld_reduce));));
+#endif // __cccl_ptx_isa >= 810
+
+#if __cccl_ptx_isa >= 810
+  NV_IF_TARGET(
+    NV_PROVIDES_SM_90,
+    (
+        // multimem.ld_reduce.relaxed.cta.global.min.s32 dest, [addr];
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<int32_t (*)(cuda::ptx::sem_relaxed_t, cuda::ptx::scope_cta_t, cuda::ptx::op_min_t, const int32_t*)>(
+            cuda::ptx::multimem_ld_reduce));
+          // multimem.ld_reduce.relaxed.cluster.global.min.s32 dest, [addr];
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<int32_t (*)(
+                cuda::ptx::sem_relaxed_t, cuda::ptx::scope_cluster_t, cuda::ptx::op_min_t, const int32_t*)>(
+                cuda::ptx::multimem_ld_reduce));
+          // multimem.ld_reduce.relaxed.gpu.global.min.s32 dest, [addr];
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<int32_t (*)(
+                cuda::ptx::sem_relaxed_t, cuda::ptx::scope_gpu_t, cuda::ptx::op_min_t, const int32_t*)>(
+                cuda::ptx::multimem_ld_reduce));
+          // multimem.ld_reduce.relaxed.sys.global.min.s32 dest, [addr];
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<int32_t (*)(
+                cuda::ptx::sem_relaxed_t, cuda::ptx::scope_sys_t, cuda::ptx::op_min_t, const int32_t*)>(
+                cuda::ptx::multimem_ld_reduce));
+          // multimem.ld_reduce.acquire.cta.global.min.s32 dest, [addr];
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<int32_t (*)(
+                cuda::ptx::sem_acquire_t, cuda::ptx::scope_cta_t, cuda::ptx::op_min_t, const int32_t*)>(
+                cuda::ptx::multimem_ld_reduce));
+          // multimem.ld_reduce.acquire.cluster.global.min.s32 dest, [addr];
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<int32_t (*)(
+                cuda::ptx::sem_acquire_t, cuda::ptx::scope_cluster_t, cuda::ptx::op_min_t, const int32_t*)>(
+                cuda::ptx::multimem_ld_reduce));
+          // multimem.ld_reduce.acquire.gpu.global.min.s32 dest, [addr];
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<int32_t (*)(
+                cuda::ptx::sem_acquire_t, cuda::ptx::scope_gpu_t, cuda::ptx::op_min_t, const int32_t*)>(
+                cuda::ptx::multimem_ld_reduce));
+          // multimem.ld_reduce.acquire.sys.global.min.s32 dest, [addr];
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<int32_t (*)(
+                cuda::ptx::sem_acquire_t, cuda::ptx::scope_sys_t, cuda::ptx::op_min_t, const int32_t*)>(
+                cuda::ptx::multimem_ld_reduce));));
+#endif // __cccl_ptx_isa >= 810
+
+#if __cccl_ptx_isa >= 810
+  NV_IF_TARGET(
+    NV_PROVIDES_SM_90,
+    (
+        // multimem.ld_reduce.weak.global.min.s64 dest, [addr];
+        * fn_ptr++ =
+          reinterpret_cast<void*>(static_cast<int64_t (*)(cuda::ptx::sem_weak_t, cuda::ptx::op_min_t, const int64_t*)>(
+            cuda::ptx::multimem_ld_reduce));));
+#endif // __cccl_ptx_isa >= 810
+
+#if __cccl_ptx_isa >= 810
+  NV_IF_TARGET(
+    NV_PROVIDES_SM_90,
+    (
+        // multimem.ld_reduce.relaxed.cta.global.min.s64 dest, [addr];
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<int64_t (*)(cuda::ptx::sem_relaxed_t, cuda::ptx::scope_cta_t, cuda::ptx::op_min_t, const int64_t*)>(
+            cuda::ptx::multimem_ld_reduce));
+          // multimem.ld_reduce.relaxed.cluster.global.min.s64 dest, [addr];
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<int64_t (*)(
+                cuda::ptx::sem_relaxed_t, cuda::ptx::scope_cluster_t, cuda::ptx::op_min_t, const int64_t*)>(
+                cuda::ptx::multimem_ld_reduce));
+          // multimem.ld_reduce.relaxed.gpu.global.min.s64 dest, [addr];
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<int64_t (*)(
+                cuda::ptx::sem_relaxed_t, cuda::ptx::scope_gpu_t, cuda::ptx::op_min_t, const int64_t*)>(
+                cuda::ptx::multimem_ld_reduce));
+          // multimem.ld_reduce.relaxed.sys.global.min.s64 dest, [addr];
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<int64_t (*)(
+                cuda::ptx::sem_relaxed_t, cuda::ptx::scope_sys_t, cuda::ptx::op_min_t, const int64_t*)>(
+                cuda::ptx::multimem_ld_reduce));
+          // multimem.ld_reduce.acquire.cta.global.min.s64 dest, [addr];
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<int64_t (*)(
+                cuda::ptx::sem_acquire_t, cuda::ptx::scope_cta_t, cuda::ptx::op_min_t, const int64_t*)>(
+                cuda::ptx::multimem_ld_reduce));
+          // multimem.ld_reduce.acquire.cluster.global.min.s64 dest, [addr];
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<int64_t (*)(
+                cuda::ptx::sem_acquire_t, cuda::ptx::scope_cluster_t, cuda::ptx::op_min_t, const int64_t*)>(
+                cuda::ptx::multimem_ld_reduce));
+          // multimem.ld_reduce.acquire.gpu.global.min.s64 dest, [addr];
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<int64_t (*)(
+                cuda::ptx::sem_acquire_t, cuda::ptx::scope_gpu_t, cuda::ptx::op_min_t, const int64_t*)>(
+                cuda::ptx::multimem_ld_reduce));
+          // multimem.ld_reduce.acquire.sys.global.min.s64 dest, [addr];
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<int64_t (*)(
+                cuda::ptx::sem_acquire_t, cuda::ptx::scope_sys_t, cuda::ptx::op_min_t, const int64_t*)>(
+                cuda::ptx::multimem_ld_reduce));));
+#endif // __cccl_ptx_isa >= 810
+
+#if __cccl_ptx_isa >= 810
+  NV_IF_TARGET(
+    NV_PROVIDES_SM_90,
+    (
+        // multimem.ld_reduce.weak.global.max.u32 dest, [addr];
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<uint32_t (*)(cuda::ptx::sem_weak_t, cuda::ptx::op_max_t, const uint32_t*)>(
+            cuda::ptx::multimem_ld_reduce));));
+#endif // __cccl_ptx_isa >= 810
+
+#if __cccl_ptx_isa >= 810
+  NV_IF_TARGET(
+    NV_PROVIDES_SM_90,
+    (
+        // multimem.ld_reduce.relaxed.cta.global.max.u32 dest, [addr];
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<uint32_t (*)(
+            cuda::ptx::sem_relaxed_t, cuda::ptx::scope_cta_t, cuda::ptx::op_max_t, const uint32_t*)>(
+            cuda::ptx::multimem_ld_reduce));
+          // multimem.ld_reduce.relaxed.cluster.global.max.u32 dest, [addr];
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<uint32_t (*)(
+                cuda::ptx::sem_relaxed_t, cuda::ptx::scope_cluster_t, cuda::ptx::op_max_t, const uint32_t*)>(
+                cuda::ptx::multimem_ld_reduce));
+          // multimem.ld_reduce.relaxed.gpu.global.max.u32 dest, [addr];
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<uint32_t (*)(
+                cuda::ptx::sem_relaxed_t, cuda::ptx::scope_gpu_t, cuda::ptx::op_max_t, const uint32_t*)>(
+                cuda::ptx::multimem_ld_reduce));
+          // multimem.ld_reduce.relaxed.sys.global.max.u32 dest, [addr];
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<uint32_t (*)(
+                cuda::ptx::sem_relaxed_t, cuda::ptx::scope_sys_t, cuda::ptx::op_max_t, const uint32_t*)>(
+                cuda::ptx::multimem_ld_reduce));
+          // multimem.ld_reduce.acquire.cta.global.max.u32 dest, [addr];
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<uint32_t (*)(
+                cuda::ptx::sem_acquire_t, cuda::ptx::scope_cta_t, cuda::ptx::op_max_t, const uint32_t*)>(
+                cuda::ptx::multimem_ld_reduce));
+          // multimem.ld_reduce.acquire.cluster.global.max.u32 dest, [addr];
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<uint32_t (*)(
+                cuda::ptx::sem_acquire_t, cuda::ptx::scope_cluster_t, cuda::ptx::op_max_t, const uint32_t*)>(
+                cuda::ptx::multimem_ld_reduce));
+          // multimem.ld_reduce.acquire.gpu.global.max.u32 dest, [addr];
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<uint32_t (*)(
+                cuda::ptx::sem_acquire_t, cuda::ptx::scope_gpu_t, cuda::ptx::op_max_t, const uint32_t*)>(
+                cuda::ptx::multimem_ld_reduce));
+          // multimem.ld_reduce.acquire.sys.global.max.u32 dest, [addr];
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<uint32_t (*)(
+                cuda::ptx::sem_acquire_t, cuda::ptx::scope_sys_t, cuda::ptx::op_max_t, const uint32_t*)>(
+                cuda::ptx::multimem_ld_reduce));));
+#endif // __cccl_ptx_isa >= 810
+
+#if __cccl_ptx_isa >= 810
+  NV_IF_TARGET(
+    NV_PROVIDES_SM_90,
+    (
+        // multimem.ld_reduce.weak.global.max.u64 dest, [addr];
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<uint64_t (*)(cuda::ptx::sem_weak_t, cuda::ptx::op_max_t, const uint64_t*)>(
+            cuda::ptx::multimem_ld_reduce));));
+#endif // __cccl_ptx_isa >= 810
+
+#if __cccl_ptx_isa >= 810
+  NV_IF_TARGET(
+    NV_PROVIDES_SM_90,
+    (
+        // multimem.ld_reduce.relaxed.cta.global.max.u64 dest, [addr];
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<uint64_t (*)(
+            cuda::ptx::sem_relaxed_t, cuda::ptx::scope_cta_t, cuda::ptx::op_max_t, const uint64_t*)>(
+            cuda::ptx::multimem_ld_reduce));
+          // multimem.ld_reduce.relaxed.cluster.global.max.u64 dest, [addr];
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<uint64_t (*)(
+                cuda::ptx::sem_relaxed_t, cuda::ptx::scope_cluster_t, cuda::ptx::op_max_t, const uint64_t*)>(
+                cuda::ptx::multimem_ld_reduce));
+          // multimem.ld_reduce.relaxed.gpu.global.max.u64 dest, [addr];
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<uint64_t (*)(
+                cuda::ptx::sem_relaxed_t, cuda::ptx::scope_gpu_t, cuda::ptx::op_max_t, const uint64_t*)>(
+                cuda::ptx::multimem_ld_reduce));
+          // multimem.ld_reduce.relaxed.sys.global.max.u64 dest, [addr];
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<uint64_t (*)(
+                cuda::ptx::sem_relaxed_t, cuda::ptx::scope_sys_t, cuda::ptx::op_max_t, const uint64_t*)>(
+                cuda::ptx::multimem_ld_reduce));
+          // multimem.ld_reduce.acquire.cta.global.max.u64 dest, [addr];
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<uint64_t (*)(
+                cuda::ptx::sem_acquire_t, cuda::ptx::scope_cta_t, cuda::ptx::op_max_t, const uint64_t*)>(
+                cuda::ptx::multimem_ld_reduce));
+          // multimem.ld_reduce.acquire.cluster.global.max.u64 dest, [addr];
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<uint64_t (*)(
+                cuda::ptx::sem_acquire_t, cuda::ptx::scope_cluster_t, cuda::ptx::op_max_t, const uint64_t*)>(
+                cuda::ptx::multimem_ld_reduce));
+          // multimem.ld_reduce.acquire.gpu.global.max.u64 dest, [addr];
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<uint64_t (*)(
+                cuda::ptx::sem_acquire_t, cuda::ptx::scope_gpu_t, cuda::ptx::op_max_t, const uint64_t*)>(
+                cuda::ptx::multimem_ld_reduce));
+          // multimem.ld_reduce.acquire.sys.global.max.u64 dest, [addr];
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<uint64_t (*)(
+                cuda::ptx::sem_acquire_t, cuda::ptx::scope_sys_t, cuda::ptx::op_max_t, const uint64_t*)>(
+                cuda::ptx::multimem_ld_reduce));));
+#endif // __cccl_ptx_isa >= 810
+
+#if __cccl_ptx_isa >= 810
+  NV_IF_TARGET(
+    NV_PROVIDES_SM_90,
+    (
+        // multimem.ld_reduce.weak.global.max.s32 dest, [addr];
+        * fn_ptr++ =
+          reinterpret_cast<void*>(static_cast<int32_t (*)(cuda::ptx::sem_weak_t, cuda::ptx::op_max_t, const int32_t*)>(
+            cuda::ptx::multimem_ld_reduce));));
+#endif // __cccl_ptx_isa >= 810
+
+#if __cccl_ptx_isa >= 810
+  NV_IF_TARGET(
+    NV_PROVIDES_SM_90,
+    (
+        // multimem.ld_reduce.relaxed.cta.global.max.s32 dest, [addr];
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<int32_t (*)(cuda::ptx::sem_relaxed_t, cuda::ptx::scope_cta_t, cuda::ptx::op_max_t, const int32_t*)>(
+            cuda::ptx::multimem_ld_reduce));
+          // multimem.ld_reduce.relaxed.cluster.global.max.s32 dest, [addr];
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<int32_t (*)(
+                cuda::ptx::sem_relaxed_t, cuda::ptx::scope_cluster_t, cuda::ptx::op_max_t, const int32_t*)>(
+                cuda::ptx::multimem_ld_reduce));
+          // multimem.ld_reduce.relaxed.gpu.global.max.s32 dest, [addr];
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<int32_t (*)(
+                cuda::ptx::sem_relaxed_t, cuda::ptx::scope_gpu_t, cuda::ptx::op_max_t, const int32_t*)>(
+                cuda::ptx::multimem_ld_reduce));
+          // multimem.ld_reduce.relaxed.sys.global.max.s32 dest, [addr];
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<int32_t (*)(
+                cuda::ptx::sem_relaxed_t, cuda::ptx::scope_sys_t, cuda::ptx::op_max_t, const int32_t*)>(
+                cuda::ptx::multimem_ld_reduce));
+          // multimem.ld_reduce.acquire.cta.global.max.s32 dest, [addr];
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<int32_t (*)(
+                cuda::ptx::sem_acquire_t, cuda::ptx::scope_cta_t, cuda::ptx::op_max_t, const int32_t*)>(
+                cuda::ptx::multimem_ld_reduce));
+          // multimem.ld_reduce.acquire.cluster.global.max.s32 dest, [addr];
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<int32_t (*)(
+                cuda::ptx::sem_acquire_t, cuda::ptx::scope_cluster_t, cuda::ptx::op_max_t, const int32_t*)>(
+                cuda::ptx::multimem_ld_reduce));
+          // multimem.ld_reduce.acquire.gpu.global.max.s32 dest, [addr];
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<int32_t (*)(
+                cuda::ptx::sem_acquire_t, cuda::ptx::scope_gpu_t, cuda::ptx::op_max_t, const int32_t*)>(
+                cuda::ptx::multimem_ld_reduce));
+          // multimem.ld_reduce.acquire.sys.global.max.s32 dest, [addr];
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<int32_t (*)(
+                cuda::ptx::sem_acquire_t, cuda::ptx::scope_sys_t, cuda::ptx::op_max_t, const int32_t*)>(
+                cuda::ptx::multimem_ld_reduce));));
+#endif // __cccl_ptx_isa >= 810
+
+#if __cccl_ptx_isa >= 810
+  NV_IF_TARGET(
+    NV_PROVIDES_SM_90,
+    (
+        // multimem.ld_reduce.weak.global.max.s64 dest, [addr];
+        * fn_ptr++ =
+          reinterpret_cast<void*>(static_cast<int64_t (*)(cuda::ptx::sem_weak_t, cuda::ptx::op_max_t, const int64_t*)>(
+            cuda::ptx::multimem_ld_reduce));));
+#endif // __cccl_ptx_isa >= 810
+
+#if __cccl_ptx_isa >= 810
+  NV_IF_TARGET(
+    NV_PROVIDES_SM_90,
+    (
+        // multimem.ld_reduce.relaxed.cta.global.max.s64 dest, [addr];
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<int64_t (*)(cuda::ptx::sem_relaxed_t, cuda::ptx::scope_cta_t, cuda::ptx::op_max_t, const int64_t*)>(
+            cuda::ptx::multimem_ld_reduce));
+          // multimem.ld_reduce.relaxed.cluster.global.max.s64 dest, [addr];
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<int64_t (*)(
+                cuda::ptx::sem_relaxed_t, cuda::ptx::scope_cluster_t, cuda::ptx::op_max_t, const int64_t*)>(
+                cuda::ptx::multimem_ld_reduce));
+          // multimem.ld_reduce.relaxed.gpu.global.max.s64 dest, [addr];
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<int64_t (*)(
+                cuda::ptx::sem_relaxed_t, cuda::ptx::scope_gpu_t, cuda::ptx::op_max_t, const int64_t*)>(
+                cuda::ptx::multimem_ld_reduce));
+          // multimem.ld_reduce.relaxed.sys.global.max.s64 dest, [addr];
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<int64_t (*)(
+                cuda::ptx::sem_relaxed_t, cuda::ptx::scope_sys_t, cuda::ptx::op_max_t, const int64_t*)>(
+                cuda::ptx::multimem_ld_reduce));
+          // multimem.ld_reduce.acquire.cta.global.max.s64 dest, [addr];
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<int64_t (*)(
+                cuda::ptx::sem_acquire_t, cuda::ptx::scope_cta_t, cuda::ptx::op_max_t, const int64_t*)>(
+                cuda::ptx::multimem_ld_reduce));
+          // multimem.ld_reduce.acquire.cluster.global.max.s64 dest, [addr];
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<int64_t (*)(
+                cuda::ptx::sem_acquire_t, cuda::ptx::scope_cluster_t, cuda::ptx::op_max_t, const int64_t*)>(
+                cuda::ptx::multimem_ld_reduce));
+          // multimem.ld_reduce.acquire.gpu.global.max.s64 dest, [addr];
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<int64_t (*)(
+                cuda::ptx::sem_acquire_t, cuda::ptx::scope_gpu_t, cuda::ptx::op_max_t, const int64_t*)>(
+                cuda::ptx::multimem_ld_reduce));
+          // multimem.ld_reduce.acquire.sys.global.max.s64 dest, [addr];
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<int64_t (*)(
+                cuda::ptx::sem_acquire_t, cuda::ptx::scope_sys_t, cuda::ptx::op_max_t, const int64_t*)>(
+                cuda::ptx::multimem_ld_reduce));));
+#endif // __cccl_ptx_isa >= 810
+
+#if __cccl_ptx_isa >= 810
+  NV_IF_TARGET(
+    NV_PROVIDES_SM_90,
+    (
+        // multimem.ld_reduce.weak.global.add.u32 dest, [addr];
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<uint32_t (*)(cuda::ptx::sem_weak_t, cuda::ptx::op_add_t, const uint32_t*)>(
+            cuda::ptx::multimem_ld_reduce));));
+#endif // __cccl_ptx_isa >= 810
+
+#if __cccl_ptx_isa >= 810
+  NV_IF_TARGET(
+    NV_PROVIDES_SM_90,
+    (
+        // multimem.ld_reduce.relaxed.cta.global.add.u32 dest, [addr];
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<uint32_t (*)(
+            cuda::ptx::sem_relaxed_t, cuda::ptx::scope_cta_t, cuda::ptx::op_add_t, const uint32_t*)>(
+            cuda::ptx::multimem_ld_reduce));
+          // multimem.ld_reduce.relaxed.cluster.global.add.u32 dest, [addr];
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<uint32_t (*)(
+                cuda::ptx::sem_relaxed_t, cuda::ptx::scope_cluster_t, cuda::ptx::op_add_t, const uint32_t*)>(
+                cuda::ptx::multimem_ld_reduce));
+          // multimem.ld_reduce.relaxed.gpu.global.add.u32 dest, [addr];
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<uint32_t (*)(
+                cuda::ptx::sem_relaxed_t, cuda::ptx::scope_gpu_t, cuda::ptx::op_add_t, const uint32_t*)>(
+                cuda::ptx::multimem_ld_reduce));
+          // multimem.ld_reduce.relaxed.sys.global.add.u32 dest, [addr];
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<uint32_t (*)(
+                cuda::ptx::sem_relaxed_t, cuda::ptx::scope_sys_t, cuda::ptx::op_add_t, const uint32_t*)>(
+                cuda::ptx::multimem_ld_reduce));
+          // multimem.ld_reduce.acquire.cta.global.add.u32 dest, [addr];
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<uint32_t (*)(
+                cuda::ptx::sem_acquire_t, cuda::ptx::scope_cta_t, cuda::ptx::op_add_t, const uint32_t*)>(
+                cuda::ptx::multimem_ld_reduce));
+          // multimem.ld_reduce.acquire.cluster.global.add.u32 dest, [addr];
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<uint32_t (*)(
+                cuda::ptx::sem_acquire_t, cuda::ptx::scope_cluster_t, cuda::ptx::op_add_t, const uint32_t*)>(
+                cuda::ptx::multimem_ld_reduce));
+          // multimem.ld_reduce.acquire.gpu.global.add.u32 dest, [addr];
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<uint32_t (*)(
+                cuda::ptx::sem_acquire_t, cuda::ptx::scope_gpu_t, cuda::ptx::op_add_t, const uint32_t*)>(
+                cuda::ptx::multimem_ld_reduce));
+          // multimem.ld_reduce.acquire.sys.global.add.u32 dest, [addr];
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<uint32_t (*)(
+                cuda::ptx::sem_acquire_t, cuda::ptx::scope_sys_t, cuda::ptx::op_add_t, const uint32_t*)>(
+                cuda::ptx::multimem_ld_reduce));));
+#endif // __cccl_ptx_isa >= 810
+
+#if __cccl_ptx_isa >= 810
+  NV_IF_TARGET(
+    NV_PROVIDES_SM_90,
+    (
+        // multimem.ld_reduce.weak.global.add.u64 dest, [addr];
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<uint64_t (*)(cuda::ptx::sem_weak_t, cuda::ptx::op_add_t, const uint64_t*)>(
+            cuda::ptx::multimem_ld_reduce));));
+#endif // __cccl_ptx_isa >= 810
+
+#if __cccl_ptx_isa >= 810
+  NV_IF_TARGET(
+    NV_PROVIDES_SM_90,
+    (
+        // multimem.ld_reduce.relaxed.cta.global.add.u64 dest, [addr];
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<uint64_t (*)(
+            cuda::ptx::sem_relaxed_t, cuda::ptx::scope_cta_t, cuda::ptx::op_add_t, const uint64_t*)>(
+            cuda::ptx::multimem_ld_reduce));
+          // multimem.ld_reduce.relaxed.cluster.global.add.u64 dest, [addr];
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<uint64_t (*)(
+                cuda::ptx::sem_relaxed_t, cuda::ptx::scope_cluster_t, cuda::ptx::op_add_t, const uint64_t*)>(
+                cuda::ptx::multimem_ld_reduce));
+          // multimem.ld_reduce.relaxed.gpu.global.add.u64 dest, [addr];
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<uint64_t (*)(
+                cuda::ptx::sem_relaxed_t, cuda::ptx::scope_gpu_t, cuda::ptx::op_add_t, const uint64_t*)>(
+                cuda::ptx::multimem_ld_reduce));
+          // multimem.ld_reduce.relaxed.sys.global.add.u64 dest, [addr];
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<uint64_t (*)(
+                cuda::ptx::sem_relaxed_t, cuda::ptx::scope_sys_t, cuda::ptx::op_add_t, const uint64_t*)>(
+                cuda::ptx::multimem_ld_reduce));
+          // multimem.ld_reduce.acquire.cta.global.add.u64 dest, [addr];
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<uint64_t (*)(
+                cuda::ptx::sem_acquire_t, cuda::ptx::scope_cta_t, cuda::ptx::op_add_t, const uint64_t*)>(
+                cuda::ptx::multimem_ld_reduce));
+          // multimem.ld_reduce.acquire.cluster.global.add.u64 dest, [addr];
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<uint64_t (*)(
+                cuda::ptx::sem_acquire_t, cuda::ptx::scope_cluster_t, cuda::ptx::op_add_t, const uint64_t*)>(
+                cuda::ptx::multimem_ld_reduce));
+          // multimem.ld_reduce.acquire.gpu.global.add.u64 dest, [addr];
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<uint64_t (*)(
+                cuda::ptx::sem_acquire_t, cuda::ptx::scope_gpu_t, cuda::ptx::op_add_t, const uint64_t*)>(
+                cuda::ptx::multimem_ld_reduce));
+          // multimem.ld_reduce.acquire.sys.global.add.u64 dest, [addr];
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<uint64_t (*)(
+                cuda::ptx::sem_acquire_t, cuda::ptx::scope_sys_t, cuda::ptx::op_add_t, const uint64_t*)>(
+                cuda::ptx::multimem_ld_reduce));));
+#endif // __cccl_ptx_isa >= 810
+
+#if __cccl_ptx_isa >= 810
+  NV_IF_TARGET(
+    NV_PROVIDES_SM_90,
+    (
+        // multimem.ld_reduce.weak.global.add.s32 dest, [addr];
+        * fn_ptr++ =
+          reinterpret_cast<void*>(static_cast<int32_t (*)(cuda::ptx::sem_weak_t, cuda::ptx::op_add_t, const int32_t*)>(
+            cuda::ptx::multimem_ld_reduce));));
+#endif // __cccl_ptx_isa >= 810
+
+#if __cccl_ptx_isa >= 810
+  NV_IF_TARGET(
+    NV_PROVIDES_SM_90,
+    (
+        // multimem.ld_reduce.relaxed.cta.global.add.s32 dest, [addr];
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<int32_t (*)(cuda::ptx::sem_relaxed_t, cuda::ptx::scope_cta_t, cuda::ptx::op_add_t, const int32_t*)>(
+            cuda::ptx::multimem_ld_reduce));
+          // multimem.ld_reduce.relaxed.cluster.global.add.s32 dest, [addr];
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<int32_t (*)(
+                cuda::ptx::sem_relaxed_t, cuda::ptx::scope_cluster_t, cuda::ptx::op_add_t, const int32_t*)>(
+                cuda::ptx::multimem_ld_reduce));
+          // multimem.ld_reduce.relaxed.gpu.global.add.s32 dest, [addr];
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<int32_t (*)(
+                cuda::ptx::sem_relaxed_t, cuda::ptx::scope_gpu_t, cuda::ptx::op_add_t, const int32_t*)>(
+                cuda::ptx::multimem_ld_reduce));
+          // multimem.ld_reduce.relaxed.sys.global.add.s32 dest, [addr];
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<int32_t (*)(
+                cuda::ptx::sem_relaxed_t, cuda::ptx::scope_sys_t, cuda::ptx::op_add_t, const int32_t*)>(
+                cuda::ptx::multimem_ld_reduce));
+          // multimem.ld_reduce.acquire.cta.global.add.s32 dest, [addr];
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<int32_t (*)(
+                cuda::ptx::sem_acquire_t, cuda::ptx::scope_cta_t, cuda::ptx::op_add_t, const int32_t*)>(
+                cuda::ptx::multimem_ld_reduce));
+          // multimem.ld_reduce.acquire.cluster.global.add.s32 dest, [addr];
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<int32_t (*)(
+                cuda::ptx::sem_acquire_t, cuda::ptx::scope_cluster_t, cuda::ptx::op_add_t, const int32_t*)>(
+                cuda::ptx::multimem_ld_reduce));
+          // multimem.ld_reduce.acquire.gpu.global.add.s32 dest, [addr];
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<int32_t (*)(
+                cuda::ptx::sem_acquire_t, cuda::ptx::scope_gpu_t, cuda::ptx::op_add_t, const int32_t*)>(
+                cuda::ptx::multimem_ld_reduce));
+          // multimem.ld_reduce.acquire.sys.global.add.s32 dest, [addr];
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<int32_t (*)(
+                cuda::ptx::sem_acquire_t, cuda::ptx::scope_sys_t, cuda::ptx::op_add_t, const int32_t*)>(
+                cuda::ptx::multimem_ld_reduce));));
+#endif // __cccl_ptx_isa >= 810
+
+#if __cccl_ptx_isa >= 810
+  NV_IF_TARGET(
+    NV_PROVIDES_SM_90,
+    (
+        // multimem.ld_reduce.weak.global.add.u64 dest, [addr];
+        * fn_ptr++ =
+          reinterpret_cast<void*>(static_cast<int64_t (*)(cuda::ptx::sem_weak_t, cuda::ptx::op_add_t, const int64_t*)>(
+            cuda::ptx::multimem_ld_reduce));));
+#endif // __cccl_ptx_isa >= 810
+
+#if __cccl_ptx_isa >= 810
+  NV_IF_TARGET(
+    NV_PROVIDES_SM_90,
+    (
+        // multimem.ld_reduce.relaxed.cta.global.add.u64 dest, [addr];
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<int64_t (*)(cuda::ptx::sem_relaxed_t, cuda::ptx::scope_cta_t, cuda::ptx::op_add_t, const int64_t*)>(
+            cuda::ptx::multimem_ld_reduce));
+          // multimem.ld_reduce.relaxed.cluster.global.add.u64 dest, [addr];
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<int64_t (*)(
+                cuda::ptx::sem_relaxed_t, cuda::ptx::scope_cluster_t, cuda::ptx::op_add_t, const int64_t*)>(
+                cuda::ptx::multimem_ld_reduce));
+          // multimem.ld_reduce.relaxed.gpu.global.add.u64 dest, [addr];
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<int64_t (*)(
+                cuda::ptx::sem_relaxed_t, cuda::ptx::scope_gpu_t, cuda::ptx::op_add_t, const int64_t*)>(
+                cuda::ptx::multimem_ld_reduce));
+          // multimem.ld_reduce.relaxed.sys.global.add.u64 dest, [addr];
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<int64_t (*)(
+                cuda::ptx::sem_relaxed_t, cuda::ptx::scope_sys_t, cuda::ptx::op_add_t, const int64_t*)>(
+                cuda::ptx::multimem_ld_reduce));
+          // multimem.ld_reduce.acquire.cta.global.add.u64 dest, [addr];
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<int64_t (*)(
+                cuda::ptx::sem_acquire_t, cuda::ptx::scope_cta_t, cuda::ptx::op_add_t, const int64_t*)>(
+                cuda::ptx::multimem_ld_reduce));
+          // multimem.ld_reduce.acquire.cluster.global.add.u64 dest, [addr];
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<int64_t (*)(
+                cuda::ptx::sem_acquire_t, cuda::ptx::scope_cluster_t, cuda::ptx::op_add_t, const int64_t*)>(
+                cuda::ptx::multimem_ld_reduce));
+          // multimem.ld_reduce.acquire.gpu.global.add.u64 dest, [addr];
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<int64_t (*)(
+                cuda::ptx::sem_acquire_t, cuda::ptx::scope_gpu_t, cuda::ptx::op_add_t, const int64_t*)>(
+                cuda::ptx::multimem_ld_reduce));
+          // multimem.ld_reduce.acquire.sys.global.add.u64 dest, [addr];
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<int64_t (*)(
+                cuda::ptx::sem_acquire_t, cuda::ptx::scope_sys_t, cuda::ptx::op_add_t, const int64_t*)>(
+                cuda::ptx::multimem_ld_reduce));));
+#endif // __cccl_ptx_isa >= 810
+
+#if __cccl_ptx_isa >= 810
+  NV_IF_TARGET(
+    NV_PROVIDES_SM_90,
+    (
+        // multimem.ld_reduce.weak.global.and.b32 dest, [addr];
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<int32_t (*)(cuda::ptx::sem_weak_t, cuda::ptx::op_and_op_t, const int32_t*)>(
+            cuda::ptx::multimem_ld_reduce));));
+#endif // __cccl_ptx_isa >= 810
+
+#if __cccl_ptx_isa >= 810
+  NV_IF_TARGET(
+    NV_PROVIDES_SM_90,
+    (
+        // multimem.ld_reduce.relaxed.cta.global.and.b32 dest, [addr];
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<int32_t (*)(
+            cuda::ptx::sem_relaxed_t, cuda::ptx::scope_cta_t, cuda::ptx::op_and_op_t, const int32_t*)>(
+            cuda::ptx::multimem_ld_reduce));
+          // multimem.ld_reduce.relaxed.cluster.global.and.b32 dest, [addr];
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<int32_t (*)(
+                cuda::ptx::sem_relaxed_t, cuda::ptx::scope_cluster_t, cuda::ptx::op_and_op_t, const int32_t*)>(
+                cuda::ptx::multimem_ld_reduce));
+          // multimem.ld_reduce.relaxed.gpu.global.and.b32 dest, [addr];
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<int32_t (*)(
+                cuda::ptx::sem_relaxed_t, cuda::ptx::scope_gpu_t, cuda::ptx::op_and_op_t, const int32_t*)>(
+                cuda::ptx::multimem_ld_reduce));
+          // multimem.ld_reduce.relaxed.sys.global.and.b32 dest, [addr];
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<int32_t (*)(
+                cuda::ptx::sem_relaxed_t, cuda::ptx::scope_sys_t, cuda::ptx::op_and_op_t, const int32_t*)>(
+                cuda::ptx::multimem_ld_reduce));
+          // multimem.ld_reduce.acquire.cta.global.and.b32 dest, [addr];
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<int32_t (*)(
+                cuda::ptx::sem_acquire_t, cuda::ptx::scope_cta_t, cuda::ptx::op_and_op_t, const int32_t*)>(
+                cuda::ptx::multimem_ld_reduce));
+          // multimem.ld_reduce.acquire.cluster.global.and.b32 dest, [addr];
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<int32_t (*)(
+                cuda::ptx::sem_acquire_t, cuda::ptx::scope_cluster_t, cuda::ptx::op_and_op_t, const int32_t*)>(
+                cuda::ptx::multimem_ld_reduce));
+          // multimem.ld_reduce.acquire.gpu.global.and.b32 dest, [addr];
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<int32_t (*)(
+                cuda::ptx::sem_acquire_t, cuda::ptx::scope_gpu_t, cuda::ptx::op_and_op_t, const int32_t*)>(
+                cuda::ptx::multimem_ld_reduce));
+          // multimem.ld_reduce.acquire.sys.global.and.b32 dest, [addr];
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<int32_t (*)(
+                cuda::ptx::sem_acquire_t, cuda::ptx::scope_sys_t, cuda::ptx::op_and_op_t, const int32_t*)>(
+                cuda::ptx::multimem_ld_reduce));));
+#endif // __cccl_ptx_isa >= 810
+
+#if __cccl_ptx_isa >= 810
+  NV_IF_TARGET(
+    NV_PROVIDES_SM_90,
+    (
+        // multimem.ld_reduce.weak.global.or.b32 dest, [addr];
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<int32_t (*)(cuda::ptx::sem_weak_t, cuda::ptx::op_or_op_t, const int32_t*)>(
+            cuda::ptx::multimem_ld_reduce));));
+#endif // __cccl_ptx_isa >= 810
+
+#if __cccl_ptx_isa >= 810
+  NV_IF_TARGET(
+    NV_PROVIDES_SM_90,
+    (
+        // multimem.ld_reduce.relaxed.cta.global.or.b32 dest, [addr];
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<int32_t (*)(
+            cuda::ptx::sem_relaxed_t, cuda::ptx::scope_cta_t, cuda::ptx::op_or_op_t, const int32_t*)>(
+            cuda::ptx::multimem_ld_reduce));
+          // multimem.ld_reduce.relaxed.cluster.global.or.b32 dest, [addr];
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<int32_t (*)(
+                cuda::ptx::sem_relaxed_t, cuda::ptx::scope_cluster_t, cuda::ptx::op_or_op_t, const int32_t*)>(
+                cuda::ptx::multimem_ld_reduce));
+          // multimem.ld_reduce.relaxed.gpu.global.or.b32 dest, [addr];
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<int32_t (*)(
+                cuda::ptx::sem_relaxed_t, cuda::ptx::scope_gpu_t, cuda::ptx::op_or_op_t, const int32_t*)>(
+                cuda::ptx::multimem_ld_reduce));
+          // multimem.ld_reduce.relaxed.sys.global.or.b32 dest, [addr];
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<int32_t (*)(
+                cuda::ptx::sem_relaxed_t, cuda::ptx::scope_sys_t, cuda::ptx::op_or_op_t, const int32_t*)>(
+                cuda::ptx::multimem_ld_reduce));
+          // multimem.ld_reduce.acquire.cta.global.or.b32 dest, [addr];
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<int32_t (*)(
+                cuda::ptx::sem_acquire_t, cuda::ptx::scope_cta_t, cuda::ptx::op_or_op_t, const int32_t*)>(
+                cuda::ptx::multimem_ld_reduce));
+          // multimem.ld_reduce.acquire.cluster.global.or.b32 dest, [addr];
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<int32_t (*)(
+                cuda::ptx::sem_acquire_t, cuda::ptx::scope_cluster_t, cuda::ptx::op_or_op_t, const int32_t*)>(
+                cuda::ptx::multimem_ld_reduce));
+          // multimem.ld_reduce.acquire.gpu.global.or.b32 dest, [addr];
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<int32_t (*)(
+                cuda::ptx::sem_acquire_t, cuda::ptx::scope_gpu_t, cuda::ptx::op_or_op_t, const int32_t*)>(
+                cuda::ptx::multimem_ld_reduce));
+          // multimem.ld_reduce.acquire.sys.global.or.b32 dest, [addr];
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<int32_t (*)(
+                cuda::ptx::sem_acquire_t, cuda::ptx::scope_sys_t, cuda::ptx::op_or_op_t, const int32_t*)>(
+                cuda::ptx::multimem_ld_reduce));));
+#endif // __cccl_ptx_isa >= 810
+
+#if __cccl_ptx_isa >= 810
+  NV_IF_TARGET(
+    NV_PROVIDES_SM_90,
+    (
+        // multimem.ld_reduce.weak.global.xor.b32 dest, [addr];
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<int32_t (*)(cuda::ptx::sem_weak_t, cuda::ptx::op_xor_op_t, const int32_t*)>(
+            cuda::ptx::multimem_ld_reduce));));
+#endif // __cccl_ptx_isa >= 810
+
+#if __cccl_ptx_isa >= 810
+  NV_IF_TARGET(
+    NV_PROVIDES_SM_90,
+    (
+        // multimem.ld_reduce.relaxed.cta.global.xor.b32 dest, [addr];
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<int32_t (*)(
+            cuda::ptx::sem_relaxed_t, cuda::ptx::scope_cta_t, cuda::ptx::op_xor_op_t, const int32_t*)>(
+            cuda::ptx::multimem_ld_reduce));
+          // multimem.ld_reduce.relaxed.cluster.global.xor.b32 dest, [addr];
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<int32_t (*)(
+                cuda::ptx::sem_relaxed_t, cuda::ptx::scope_cluster_t, cuda::ptx::op_xor_op_t, const int32_t*)>(
+                cuda::ptx::multimem_ld_reduce));
+          // multimem.ld_reduce.relaxed.gpu.global.xor.b32 dest, [addr];
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<int32_t (*)(
+                cuda::ptx::sem_relaxed_t, cuda::ptx::scope_gpu_t, cuda::ptx::op_xor_op_t, const int32_t*)>(
+                cuda::ptx::multimem_ld_reduce));
+          // multimem.ld_reduce.relaxed.sys.global.xor.b32 dest, [addr];
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<int32_t (*)(
+                cuda::ptx::sem_relaxed_t, cuda::ptx::scope_sys_t, cuda::ptx::op_xor_op_t, const int32_t*)>(
+                cuda::ptx::multimem_ld_reduce));
+          // multimem.ld_reduce.acquire.cta.global.xor.b32 dest, [addr];
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<int32_t (*)(
+                cuda::ptx::sem_acquire_t, cuda::ptx::scope_cta_t, cuda::ptx::op_xor_op_t, const int32_t*)>(
+                cuda::ptx::multimem_ld_reduce));
+          // multimem.ld_reduce.acquire.cluster.global.xor.b32 dest, [addr];
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<int32_t (*)(
+                cuda::ptx::sem_acquire_t, cuda::ptx::scope_cluster_t, cuda::ptx::op_xor_op_t, const int32_t*)>(
+                cuda::ptx::multimem_ld_reduce));
+          // multimem.ld_reduce.acquire.gpu.global.xor.b32 dest, [addr];
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<int32_t (*)(
+                cuda::ptx::sem_acquire_t, cuda::ptx::scope_gpu_t, cuda::ptx::op_xor_op_t, const int32_t*)>(
+                cuda::ptx::multimem_ld_reduce));
+          // multimem.ld_reduce.acquire.sys.global.xor.b32 dest, [addr];
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<int32_t (*)(
+                cuda::ptx::sem_acquire_t, cuda::ptx::scope_sys_t, cuda::ptx::op_xor_op_t, const int32_t*)>(
+                cuda::ptx::multimem_ld_reduce));));
+#endif // __cccl_ptx_isa >= 810
+
+#if __cccl_ptx_isa >= 810
+  NV_IF_TARGET(
+    NV_PROVIDES_SM_90,
+    (
+        // multimem.ld_reduce.weak.global.and.b64 dest, [addr];
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<int64_t (*)(cuda::ptx::sem_weak_t, cuda::ptx::op_and_op_t, const int64_t*)>(
+            cuda::ptx::multimem_ld_reduce));));
+#endif // __cccl_ptx_isa >= 810
+
+#if __cccl_ptx_isa >= 810
+  NV_IF_TARGET(
+    NV_PROVIDES_SM_90,
+    (
+        // multimem.ld_reduce.relaxed.cta.global.and.b64 dest, [addr];
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<int64_t (*)(
+            cuda::ptx::sem_relaxed_t, cuda::ptx::scope_cta_t, cuda::ptx::op_and_op_t, const int64_t*)>(
+            cuda::ptx::multimem_ld_reduce));
+          // multimem.ld_reduce.relaxed.cluster.global.and.b64 dest, [addr];
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<int64_t (*)(
+                cuda::ptx::sem_relaxed_t, cuda::ptx::scope_cluster_t, cuda::ptx::op_and_op_t, const int64_t*)>(
+                cuda::ptx::multimem_ld_reduce));
+          // multimem.ld_reduce.relaxed.gpu.global.and.b64 dest, [addr];
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<int64_t (*)(
+                cuda::ptx::sem_relaxed_t, cuda::ptx::scope_gpu_t, cuda::ptx::op_and_op_t, const int64_t*)>(
+                cuda::ptx::multimem_ld_reduce));
+          // multimem.ld_reduce.relaxed.sys.global.and.b64 dest, [addr];
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<int64_t (*)(
+                cuda::ptx::sem_relaxed_t, cuda::ptx::scope_sys_t, cuda::ptx::op_and_op_t, const int64_t*)>(
+                cuda::ptx::multimem_ld_reduce));
+          // multimem.ld_reduce.acquire.cta.global.and.b64 dest, [addr];
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<int64_t (*)(
+                cuda::ptx::sem_acquire_t, cuda::ptx::scope_cta_t, cuda::ptx::op_and_op_t, const int64_t*)>(
+                cuda::ptx::multimem_ld_reduce));
+          // multimem.ld_reduce.acquire.cluster.global.and.b64 dest, [addr];
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<int64_t (*)(
+                cuda::ptx::sem_acquire_t, cuda::ptx::scope_cluster_t, cuda::ptx::op_and_op_t, const int64_t*)>(
+                cuda::ptx::multimem_ld_reduce));
+          // multimem.ld_reduce.acquire.gpu.global.and.b64 dest, [addr];
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<int64_t (*)(
+                cuda::ptx::sem_acquire_t, cuda::ptx::scope_gpu_t, cuda::ptx::op_and_op_t, const int64_t*)>(
+                cuda::ptx::multimem_ld_reduce));
+          // multimem.ld_reduce.acquire.sys.global.and.b64 dest, [addr];
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<int64_t (*)(
+                cuda::ptx::sem_acquire_t, cuda::ptx::scope_sys_t, cuda::ptx::op_and_op_t, const int64_t*)>(
+                cuda::ptx::multimem_ld_reduce));));
+#endif // __cccl_ptx_isa >= 810
+
+#if __cccl_ptx_isa >= 810
+  NV_IF_TARGET(
+    NV_PROVIDES_SM_90,
+    (
+        // multimem.ld_reduce.weak.global.or.b64 dest, [addr];
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<int64_t (*)(cuda::ptx::sem_weak_t, cuda::ptx::op_or_op_t, const int64_t*)>(
+            cuda::ptx::multimem_ld_reduce));));
+#endif // __cccl_ptx_isa >= 810
+
+#if __cccl_ptx_isa >= 810
+  NV_IF_TARGET(
+    NV_PROVIDES_SM_90,
+    (
+        // multimem.ld_reduce.relaxed.cta.global.or.b64 dest, [addr];
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<int64_t (*)(
+            cuda::ptx::sem_relaxed_t, cuda::ptx::scope_cta_t, cuda::ptx::op_or_op_t, const int64_t*)>(
+            cuda::ptx::multimem_ld_reduce));
+          // multimem.ld_reduce.relaxed.cluster.global.or.b64 dest, [addr];
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<int64_t (*)(
+                cuda::ptx::sem_relaxed_t, cuda::ptx::scope_cluster_t, cuda::ptx::op_or_op_t, const int64_t*)>(
+                cuda::ptx::multimem_ld_reduce));
+          // multimem.ld_reduce.relaxed.gpu.global.or.b64 dest, [addr];
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<int64_t (*)(
+                cuda::ptx::sem_relaxed_t, cuda::ptx::scope_gpu_t, cuda::ptx::op_or_op_t, const int64_t*)>(
+                cuda::ptx::multimem_ld_reduce));
+          // multimem.ld_reduce.relaxed.sys.global.or.b64 dest, [addr];
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<int64_t (*)(
+                cuda::ptx::sem_relaxed_t, cuda::ptx::scope_sys_t, cuda::ptx::op_or_op_t, const int64_t*)>(
+                cuda::ptx::multimem_ld_reduce));
+          // multimem.ld_reduce.acquire.cta.global.or.b64 dest, [addr];
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<int64_t (*)(
+                cuda::ptx::sem_acquire_t, cuda::ptx::scope_cta_t, cuda::ptx::op_or_op_t, const int64_t*)>(
+                cuda::ptx::multimem_ld_reduce));
+          // multimem.ld_reduce.acquire.cluster.global.or.b64 dest, [addr];
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<int64_t (*)(
+                cuda::ptx::sem_acquire_t, cuda::ptx::scope_cluster_t, cuda::ptx::op_or_op_t, const int64_t*)>(
+                cuda::ptx::multimem_ld_reduce));
+          // multimem.ld_reduce.acquire.gpu.global.or.b64 dest, [addr];
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<int64_t (*)(
+                cuda::ptx::sem_acquire_t, cuda::ptx::scope_gpu_t, cuda::ptx::op_or_op_t, const int64_t*)>(
+                cuda::ptx::multimem_ld_reduce));
+          // multimem.ld_reduce.acquire.sys.global.or.b64 dest, [addr];
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<int64_t (*)(
+                cuda::ptx::sem_acquire_t, cuda::ptx::scope_sys_t, cuda::ptx::op_or_op_t, const int64_t*)>(
+                cuda::ptx::multimem_ld_reduce));));
+#endif // __cccl_ptx_isa >= 810
+
+#if __cccl_ptx_isa >= 810
+  NV_IF_TARGET(
+    NV_PROVIDES_SM_90,
+    (
+        // multimem.ld_reduce.weak.global.xor.b64 dest, [addr];
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<int64_t (*)(cuda::ptx::sem_weak_t, cuda::ptx::op_xor_op_t, const int64_t*)>(
+            cuda::ptx::multimem_ld_reduce));));
+#endif // __cccl_ptx_isa >= 810
+
+#if __cccl_ptx_isa >= 810
+  NV_IF_TARGET(
+    NV_PROVIDES_SM_90,
+    (
+        // multimem.ld_reduce.relaxed.cta.global.xor.b64 dest, [addr];
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<int64_t (*)(
+            cuda::ptx::sem_relaxed_t, cuda::ptx::scope_cta_t, cuda::ptx::op_xor_op_t, const int64_t*)>(
+            cuda::ptx::multimem_ld_reduce));
+          // multimem.ld_reduce.relaxed.cluster.global.xor.b64 dest, [addr];
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<int64_t (*)(
+                cuda::ptx::sem_relaxed_t, cuda::ptx::scope_cluster_t, cuda::ptx::op_xor_op_t, const int64_t*)>(
+                cuda::ptx::multimem_ld_reduce));
+          // multimem.ld_reduce.relaxed.gpu.global.xor.b64 dest, [addr];
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<int64_t (*)(
+                cuda::ptx::sem_relaxed_t, cuda::ptx::scope_gpu_t, cuda::ptx::op_xor_op_t, const int64_t*)>(
+                cuda::ptx::multimem_ld_reduce));
+          // multimem.ld_reduce.relaxed.sys.global.xor.b64 dest, [addr];
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<int64_t (*)(
+                cuda::ptx::sem_relaxed_t, cuda::ptx::scope_sys_t, cuda::ptx::op_xor_op_t, const int64_t*)>(
+                cuda::ptx::multimem_ld_reduce));
+          // multimem.ld_reduce.acquire.cta.global.xor.b64 dest, [addr];
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<int64_t (*)(
+                cuda::ptx::sem_acquire_t, cuda::ptx::scope_cta_t, cuda::ptx::op_xor_op_t, const int64_t*)>(
+                cuda::ptx::multimem_ld_reduce));
+          // multimem.ld_reduce.acquire.cluster.global.xor.b64 dest, [addr];
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<int64_t (*)(
+                cuda::ptx::sem_acquire_t, cuda::ptx::scope_cluster_t, cuda::ptx::op_xor_op_t, const int64_t*)>(
+                cuda::ptx::multimem_ld_reduce));
+          // multimem.ld_reduce.acquire.gpu.global.xor.b64 dest, [addr];
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<int64_t (*)(
+                cuda::ptx::sem_acquire_t, cuda::ptx::scope_gpu_t, cuda::ptx::op_xor_op_t, const int64_t*)>(
+                cuda::ptx::multimem_ld_reduce));
+          // multimem.ld_reduce.acquire.sys.global.xor.b64 dest, [addr];
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<int64_t (*)(
+                cuda::ptx::sem_acquire_t, cuda::ptx::scope_sys_t, cuda::ptx::op_xor_op_t, const int64_t*)>(
+                cuda::ptx::multimem_ld_reduce));));
+#endif // __cccl_ptx_isa >= 810
+}
diff --git a/libcudacxx/test/libcudacxx/cuda/ptx/generated/multimem_red.h b/libcudacxx/test/libcudacxx/cuda/ptx/generated/multimem_red.h
new file mode 100644
index 00000000000..dd0011e3fb2
--- /dev/null
+++ b/libcudacxx/test/libcudacxx/cuda/ptx/generated/multimem_red.h
@@ -0,0 +1,840 @@
+// This file was automatically generated. Do not edit.
+
+// We use a special strategy to force the generation of the PTX. This is mainly
+// a fight against dead-code-elimination in the NVVM layer.
+//
+// The reason we need this strategy is because certain older versions of ptxas
+// segfault when a non-sensical sequence of PTX is generated. So instead, we try
+// to force the instantiation and compilation to PTX of all the overloads of the
+// PTX wrapping functions.
+//
+// We do this by writing a function pointer of each overload to the kernel
+// parameter `fn_ptr`.
+//
+// Because `fn_ptr` is possibly visible outside this translation unit, the
+// compiler must compile all the functions which are stored.
+
+__global__ void test_multimem_red(void** fn_ptr)
+{
+#if __cccl_ptx_isa >= 810
+  NV_IF_TARGET(
+    NV_PROVIDES_SM_90,
+    (
+        // multimem.red.relaxed.cta.global.min.u32 [addr], val;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(
+            cuda::ptx::sem_relaxed_t, cuda::ptx::scope_cta_t, cuda::ptx::op_min_t, uint32_t*, uint32_t)>(
+            cuda::ptx::multimem_red));
+          // multimem.red.relaxed.cluster.global.min.u32 [addr], val;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::sem_relaxed_t, cuda::ptx::scope_cluster_t, cuda::ptx::op_min_t, uint32_t*, uint32_t)>(
+                cuda::ptx::multimem_red));
+          // multimem.red.relaxed.gpu.global.min.u32 [addr], val;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::sem_relaxed_t, cuda::ptx::scope_gpu_t, cuda::ptx::op_min_t, uint32_t*, uint32_t)>(
+                cuda::ptx::multimem_red));
+          // multimem.red.relaxed.sys.global.min.u32 [addr], val;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::sem_relaxed_t, cuda::ptx::scope_sys_t, cuda::ptx::op_min_t, uint32_t*, uint32_t)>(
+                cuda::ptx::multimem_red));
+          // multimem.red.release.cta.global.min.u32 [addr], val;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::sem_release_t, cuda::ptx::scope_cta_t, cuda::ptx::op_min_t, uint32_t*, uint32_t)>(
+                cuda::ptx::multimem_red));
+          // multimem.red.release.cluster.global.min.u32 [addr], val;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::sem_release_t, cuda::ptx::scope_cluster_t, cuda::ptx::op_min_t, uint32_t*, uint32_t)>(
+                cuda::ptx::multimem_red));
+          // multimem.red.release.gpu.global.min.u32 [addr], val;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::sem_release_t, cuda::ptx::scope_gpu_t, cuda::ptx::op_min_t, uint32_t*, uint32_t)>(
+                cuda::ptx::multimem_red));
+          // multimem.red.release.sys.global.min.u32 [addr], val;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::sem_release_t, cuda::ptx::scope_sys_t, cuda::ptx::op_min_t, uint32_t*, uint32_t)>(
+                cuda::ptx::multimem_red));));
+#endif // __cccl_ptx_isa >= 810
+
+#if __cccl_ptx_isa >= 810
+  NV_IF_TARGET(
+    NV_PROVIDES_SM_90,
+    (
+        // multimem.red.relaxed.cta.global.min.u64 [addr], val;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(
+            cuda::ptx::sem_relaxed_t, cuda::ptx::scope_cta_t, cuda::ptx::op_min_t, uint64_t*, uint64_t)>(
+            cuda::ptx::multimem_red));
+          // multimem.red.relaxed.cluster.global.min.u64 [addr], val;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::sem_relaxed_t, cuda::ptx::scope_cluster_t, cuda::ptx::op_min_t, uint64_t*, uint64_t)>(
+                cuda::ptx::multimem_red));
+          // multimem.red.relaxed.gpu.global.min.u64 [addr], val;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::sem_relaxed_t, cuda::ptx::scope_gpu_t, cuda::ptx::op_min_t, uint64_t*, uint64_t)>(
+                cuda::ptx::multimem_red));
+          // multimem.red.relaxed.sys.global.min.u64 [addr], val;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::sem_relaxed_t, cuda::ptx::scope_sys_t, cuda::ptx::op_min_t, uint64_t*, uint64_t)>(
+                cuda::ptx::multimem_red));
+          // multimem.red.release.cta.global.min.u64 [addr], val;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::sem_release_t, cuda::ptx::scope_cta_t, cuda::ptx::op_min_t, uint64_t*, uint64_t)>(
+                cuda::ptx::multimem_red));
+          // multimem.red.release.cluster.global.min.u64 [addr], val;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::sem_release_t, cuda::ptx::scope_cluster_t, cuda::ptx::op_min_t, uint64_t*, uint64_t)>(
+                cuda::ptx::multimem_red));
+          // multimem.red.release.gpu.global.min.u64 [addr], val;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::sem_release_t, cuda::ptx::scope_gpu_t, cuda::ptx::op_min_t, uint64_t*, uint64_t)>(
+                cuda::ptx::multimem_red));
+          // multimem.red.release.sys.global.min.u64 [addr], val;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::sem_release_t, cuda::ptx::scope_sys_t, cuda::ptx::op_min_t, uint64_t*, uint64_t)>(
+                cuda::ptx::multimem_red));));
+#endif // __cccl_ptx_isa >= 810
+
+#if __cccl_ptx_isa >= 810
+  NV_IF_TARGET(
+    NV_PROVIDES_SM_90,
+    (
+        // multimem.red.relaxed.cta.global.min.s32 [addr], val;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(cuda::ptx::sem_relaxed_t, cuda::ptx::scope_cta_t, cuda::ptx::op_min_t, int32_t*, int32_t)>(
+            cuda::ptx::multimem_red));
+          // multimem.red.relaxed.cluster.global.min.s32 [addr], val;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::sem_relaxed_t, cuda::ptx::scope_cluster_t, cuda::ptx::op_min_t, int32_t*, int32_t)>(
+                cuda::ptx::multimem_red));
+          // multimem.red.relaxed.gpu.global.min.s32 [addr], val;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::sem_relaxed_t, cuda::ptx::scope_gpu_t, cuda::ptx::op_min_t, int32_t*, int32_t)>(
+                cuda::ptx::multimem_red));
+          // multimem.red.relaxed.sys.global.min.s32 [addr], val;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::sem_relaxed_t, cuda::ptx::scope_sys_t, cuda::ptx::op_min_t, int32_t*, int32_t)>(
+                cuda::ptx::multimem_red));
+          // multimem.red.release.cta.global.min.s32 [addr], val;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::sem_release_t, cuda::ptx::scope_cta_t, cuda::ptx::op_min_t, int32_t*, int32_t)>(
+                cuda::ptx::multimem_red));
+          // multimem.red.release.cluster.global.min.s32 [addr], val;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::sem_release_t, cuda::ptx::scope_cluster_t, cuda::ptx::op_min_t, int32_t*, int32_t)>(
+                cuda::ptx::multimem_red));
+          // multimem.red.release.gpu.global.min.s32 [addr], val;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::sem_release_t, cuda::ptx::scope_gpu_t, cuda::ptx::op_min_t, int32_t*, int32_t)>(
+                cuda::ptx::multimem_red));
+          // multimem.red.release.sys.global.min.s32 [addr], val;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::sem_release_t, cuda::ptx::scope_sys_t, cuda::ptx::op_min_t, int32_t*, int32_t)>(
+                cuda::ptx::multimem_red));));
+#endif // __cccl_ptx_isa >= 810
+
+#if __cccl_ptx_isa >= 810
+  NV_IF_TARGET(
+    NV_PROVIDES_SM_90,
+    (
+        // multimem.red.relaxed.cta.global.min.s64 [addr], val;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(cuda::ptx::sem_relaxed_t, cuda::ptx::scope_cta_t, cuda::ptx::op_min_t, int64_t*, int64_t)>(
+            cuda::ptx::multimem_red));
+          // multimem.red.relaxed.cluster.global.min.s64 [addr], val;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::sem_relaxed_t, cuda::ptx::scope_cluster_t, cuda::ptx::op_min_t, int64_t*, int64_t)>(
+                cuda::ptx::multimem_red));
+          // multimem.red.relaxed.gpu.global.min.s64 [addr], val;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::sem_relaxed_t, cuda::ptx::scope_gpu_t, cuda::ptx::op_min_t, int64_t*, int64_t)>(
+                cuda::ptx::multimem_red));
+          // multimem.red.relaxed.sys.global.min.s64 [addr], val;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::sem_relaxed_t, cuda::ptx::scope_sys_t, cuda::ptx::op_min_t, int64_t*, int64_t)>(
+                cuda::ptx::multimem_red));
+          // multimem.red.release.cta.global.min.s64 [addr], val;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::sem_release_t, cuda::ptx::scope_cta_t, cuda::ptx::op_min_t, int64_t*, int64_t)>(
+                cuda::ptx::multimem_red));
+          // multimem.red.release.cluster.global.min.s64 [addr], val;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::sem_release_t, cuda::ptx::scope_cluster_t, cuda::ptx::op_min_t, int64_t*, int64_t)>(
+                cuda::ptx::multimem_red));
+          // multimem.red.release.gpu.global.min.s64 [addr], val;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::sem_release_t, cuda::ptx::scope_gpu_t, cuda::ptx::op_min_t, int64_t*, int64_t)>(
+                cuda::ptx::multimem_red));
+          // multimem.red.release.sys.global.min.s64 [addr], val;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::sem_release_t, cuda::ptx::scope_sys_t, cuda::ptx::op_min_t, int64_t*, int64_t)>(
+                cuda::ptx::multimem_red));));
+#endif // __cccl_ptx_isa >= 810
+
+#if __cccl_ptx_isa >= 810
+  NV_IF_TARGET(
+    NV_PROVIDES_SM_90,
+    (
+        // multimem.red.relaxed.cta.global.max.u32 [addr], val;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(
+            cuda::ptx::sem_relaxed_t, cuda::ptx::scope_cta_t, cuda::ptx::op_max_t, uint32_t*, uint32_t)>(
+            cuda::ptx::multimem_red));
+          // multimem.red.relaxed.cluster.global.max.u32 [addr], val;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::sem_relaxed_t, cuda::ptx::scope_cluster_t, cuda::ptx::op_max_t, uint32_t*, uint32_t)>(
+                cuda::ptx::multimem_red));
+          // multimem.red.relaxed.gpu.global.max.u32 [addr], val;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::sem_relaxed_t, cuda::ptx::scope_gpu_t, cuda::ptx::op_max_t, uint32_t*, uint32_t)>(
+                cuda::ptx::multimem_red));
+          // multimem.red.relaxed.sys.global.max.u32 [addr], val;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::sem_relaxed_t, cuda::ptx::scope_sys_t, cuda::ptx::op_max_t, uint32_t*, uint32_t)>(
+                cuda::ptx::multimem_red));
+          // multimem.red.release.cta.global.max.u32 [addr], val;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::sem_release_t, cuda::ptx::scope_cta_t, cuda::ptx::op_max_t, uint32_t*, uint32_t)>(
+                cuda::ptx::multimem_red));
+          // multimem.red.release.cluster.global.max.u32 [addr], val;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::sem_release_t, cuda::ptx::scope_cluster_t, cuda::ptx::op_max_t, uint32_t*, uint32_t)>(
+                cuda::ptx::multimem_red));
+          // multimem.red.release.gpu.global.max.u32 [addr], val;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::sem_release_t, cuda::ptx::scope_gpu_t, cuda::ptx::op_max_t, uint32_t*, uint32_t)>(
+                cuda::ptx::multimem_red));
+          // multimem.red.release.sys.global.max.u32 [addr], val;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::sem_release_t, cuda::ptx::scope_sys_t, cuda::ptx::op_max_t, uint32_t*, uint32_t)>(
+                cuda::ptx::multimem_red));));
+#endif // __cccl_ptx_isa >= 810
+
+#if __cccl_ptx_isa >= 810
+  NV_IF_TARGET(
+    NV_PROVIDES_SM_90,
+    (
+        // multimem.red.relaxed.cta.global.max.u64 [addr], val;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(
+            cuda::ptx::sem_relaxed_t, cuda::ptx::scope_cta_t, cuda::ptx::op_max_t, uint64_t*, uint64_t)>(
+            cuda::ptx::multimem_red));
+          // multimem.red.relaxed.cluster.global.max.u64 [addr], val;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::sem_relaxed_t, cuda::ptx::scope_cluster_t, cuda::ptx::op_max_t, uint64_t*, uint64_t)>(
+                cuda::ptx::multimem_red));
+          // multimem.red.relaxed.gpu.global.max.u64 [addr], val;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::sem_relaxed_t, cuda::ptx::scope_gpu_t, cuda::ptx::op_max_t, uint64_t*, uint64_t)>(
+                cuda::ptx::multimem_red));
+          // multimem.red.relaxed.sys.global.max.u64 [addr], val;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::sem_relaxed_t, cuda::ptx::scope_sys_t, cuda::ptx::op_max_t, uint64_t*, uint64_t)>(
+                cuda::ptx::multimem_red));
+          // multimem.red.release.cta.global.max.u64 [addr], val;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::sem_release_t, cuda::ptx::scope_cta_t, cuda::ptx::op_max_t, uint64_t*, uint64_t)>(
+                cuda::ptx::multimem_red));
+          // multimem.red.release.cluster.global.max.u64 [addr], val;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::sem_release_t, cuda::ptx::scope_cluster_t, cuda::ptx::op_max_t, uint64_t*, uint64_t)>(
+                cuda::ptx::multimem_red));
+          // multimem.red.release.gpu.global.max.u64 [addr], val;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::sem_release_t, cuda::ptx::scope_gpu_t, cuda::ptx::op_max_t, uint64_t*, uint64_t)>(
+                cuda::ptx::multimem_red));
+          // multimem.red.release.sys.global.max.u64 [addr], val;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::sem_release_t, cuda::ptx::scope_sys_t, cuda::ptx::op_max_t, uint64_t*, uint64_t)>(
+                cuda::ptx::multimem_red));));
+#endif // __cccl_ptx_isa >= 810
+
+#if __cccl_ptx_isa >= 810
+  NV_IF_TARGET(
+    NV_PROVIDES_SM_90,
+    (
+        // multimem.red.relaxed.cta.global.max.s32 [addr], val;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(cuda::ptx::sem_relaxed_t, cuda::ptx::scope_cta_t, cuda::ptx::op_max_t, int32_t*, int32_t)>(
+            cuda::ptx::multimem_red));
+          // multimem.red.relaxed.cluster.global.max.s32 [addr], val;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::sem_relaxed_t, cuda::ptx::scope_cluster_t, cuda::ptx::op_max_t, int32_t*, int32_t)>(
+                cuda::ptx::multimem_red));
+          // multimem.red.relaxed.gpu.global.max.s32 [addr], val;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::sem_relaxed_t, cuda::ptx::scope_gpu_t, cuda::ptx::op_max_t, int32_t*, int32_t)>(
+                cuda::ptx::multimem_red));
+          // multimem.red.relaxed.sys.global.max.s32 [addr], val;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::sem_relaxed_t, cuda::ptx::scope_sys_t, cuda::ptx::op_max_t, int32_t*, int32_t)>(
+                cuda::ptx::multimem_red));
+          // multimem.red.release.cta.global.max.s32 [addr], val;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::sem_release_t, cuda::ptx::scope_cta_t, cuda::ptx::op_max_t, int32_t*, int32_t)>(
+                cuda::ptx::multimem_red));
+          // multimem.red.release.cluster.global.max.s32 [addr], val;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::sem_release_t, cuda::ptx::scope_cluster_t, cuda::ptx::op_max_t, int32_t*, int32_t)>(
+                cuda::ptx::multimem_red));
+          // multimem.red.release.gpu.global.max.s32 [addr], val;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::sem_release_t, cuda::ptx::scope_gpu_t, cuda::ptx::op_max_t, int32_t*, int32_t)>(
+                cuda::ptx::multimem_red));
+          // multimem.red.release.sys.global.max.s32 [addr], val;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::sem_release_t, cuda::ptx::scope_sys_t, cuda::ptx::op_max_t, int32_t*, int32_t)>(
+                cuda::ptx::multimem_red));));
+#endif // __cccl_ptx_isa >= 810
+
+#if __cccl_ptx_isa >= 810
+  NV_IF_TARGET(
+    NV_PROVIDES_SM_90,
+    (
+        // multimem.red.relaxed.cta.global.max.s64 [addr], val;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(cuda::ptx::sem_relaxed_t, cuda::ptx::scope_cta_t, cuda::ptx::op_max_t, int64_t*, int64_t)>(
+            cuda::ptx::multimem_red));
+          // multimem.red.relaxed.cluster.global.max.s64 [addr], val;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::sem_relaxed_t, cuda::ptx::scope_cluster_t, cuda::ptx::op_max_t, int64_t*, int64_t)>(
+                cuda::ptx::multimem_red));
+          // multimem.red.relaxed.gpu.global.max.s64 [addr], val;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::sem_relaxed_t, cuda::ptx::scope_gpu_t, cuda::ptx::op_max_t, int64_t*, int64_t)>(
+                cuda::ptx::multimem_red));
+          // multimem.red.relaxed.sys.global.max.s64 [addr], val;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::sem_relaxed_t, cuda::ptx::scope_sys_t, cuda::ptx::op_max_t, int64_t*, int64_t)>(
+                cuda::ptx::multimem_red));
+          // multimem.red.release.cta.global.max.s64 [addr], val;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::sem_release_t, cuda::ptx::scope_cta_t, cuda::ptx::op_max_t, int64_t*, int64_t)>(
+                cuda::ptx::multimem_red));
+          // multimem.red.release.cluster.global.max.s64 [addr], val;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::sem_release_t, cuda::ptx::scope_cluster_t, cuda::ptx::op_max_t, int64_t*, int64_t)>(
+                cuda::ptx::multimem_red));
+          // multimem.red.release.gpu.global.max.s64 [addr], val;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::sem_release_t, cuda::ptx::scope_gpu_t, cuda::ptx::op_max_t, int64_t*, int64_t)>(
+                cuda::ptx::multimem_red));
+          // multimem.red.release.sys.global.max.s64 [addr], val;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::sem_release_t, cuda::ptx::scope_sys_t, cuda::ptx::op_max_t, int64_t*, int64_t)>(
+                cuda::ptx::multimem_red));));
+#endif // __cccl_ptx_isa >= 810
+
+#if __cccl_ptx_isa >= 810
+  NV_IF_TARGET(
+    NV_PROVIDES_SM_90,
+    (
+        // multimem.red.relaxed.cta.global.add.u32 [addr], val;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(
+            cuda::ptx::sem_relaxed_t, cuda::ptx::scope_cta_t, cuda::ptx::op_add_t, uint32_t*, uint32_t)>(
+            cuda::ptx::multimem_red));
+          // multimem.red.relaxed.cluster.global.add.u32 [addr], val;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::sem_relaxed_t, cuda::ptx::scope_cluster_t, cuda::ptx::op_add_t, uint32_t*, uint32_t)>(
+                cuda::ptx::multimem_red));
+          // multimem.red.relaxed.gpu.global.add.u32 [addr], val;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::sem_relaxed_t, cuda::ptx::scope_gpu_t, cuda::ptx::op_add_t, uint32_t*, uint32_t)>(
+                cuda::ptx::multimem_red));
+          // multimem.red.relaxed.sys.global.add.u32 [addr], val;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::sem_relaxed_t, cuda::ptx::scope_sys_t, cuda::ptx::op_add_t, uint32_t*, uint32_t)>(
+                cuda::ptx::multimem_red));
+          // multimem.red.release.cta.global.add.u32 [addr], val;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::sem_release_t, cuda::ptx::scope_cta_t, cuda::ptx::op_add_t, uint32_t*, uint32_t)>(
+                cuda::ptx::multimem_red));
+          // multimem.red.release.cluster.global.add.u32 [addr], val;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::sem_release_t, cuda::ptx::scope_cluster_t, cuda::ptx::op_add_t, uint32_t*, uint32_t)>(
+                cuda::ptx::multimem_red));
+          // multimem.red.release.gpu.global.add.u32 [addr], val;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::sem_release_t, cuda::ptx::scope_gpu_t, cuda::ptx::op_add_t, uint32_t*, uint32_t)>(
+                cuda::ptx::multimem_red));
+          // multimem.red.release.sys.global.add.u32 [addr], val;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::sem_release_t, cuda::ptx::scope_sys_t, cuda::ptx::op_add_t, uint32_t*, uint32_t)>(
+                cuda::ptx::multimem_red));));
+#endif // __cccl_ptx_isa >= 810
+
+#if __cccl_ptx_isa >= 810
+  NV_IF_TARGET(
+    NV_PROVIDES_SM_90,
+    (
+        // multimem.red.relaxed.cta.global.add.u64 [addr], val;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(
+            cuda::ptx::sem_relaxed_t, cuda::ptx::scope_cta_t, cuda::ptx::op_add_t, uint64_t*, uint64_t)>(
+            cuda::ptx::multimem_red));
+          // multimem.red.relaxed.cluster.global.add.u64 [addr], val;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::sem_relaxed_t, cuda::ptx::scope_cluster_t, cuda::ptx::op_add_t, uint64_t*, uint64_t)>(
+                cuda::ptx::multimem_red));
+          // multimem.red.relaxed.gpu.global.add.u64 [addr], val;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::sem_relaxed_t, cuda::ptx::scope_gpu_t, cuda::ptx::op_add_t, uint64_t*, uint64_t)>(
+                cuda::ptx::multimem_red));
+          // multimem.red.relaxed.sys.global.add.u64 [addr], val;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::sem_relaxed_t, cuda::ptx::scope_sys_t, cuda::ptx::op_add_t, uint64_t*, uint64_t)>(
+                cuda::ptx::multimem_red));
+          // multimem.red.release.cta.global.add.u64 [addr], val;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::sem_release_t, cuda::ptx::scope_cta_t, cuda::ptx::op_add_t, uint64_t*, uint64_t)>(
+                cuda::ptx::multimem_red));
+          // multimem.red.release.cluster.global.add.u64 [addr], val;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::sem_release_t, cuda::ptx::scope_cluster_t, cuda::ptx::op_add_t, uint64_t*, uint64_t)>(
+                cuda::ptx::multimem_red));
+          // multimem.red.release.gpu.global.add.u64 [addr], val;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::sem_release_t, cuda::ptx::scope_gpu_t, cuda::ptx::op_add_t, uint64_t*, uint64_t)>(
+                cuda::ptx::multimem_red));
+          // multimem.red.release.sys.global.add.u64 [addr], val;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::sem_release_t, cuda::ptx::scope_sys_t, cuda::ptx::op_add_t, uint64_t*, uint64_t)>(
+                cuda::ptx::multimem_red));));
+#endif // __cccl_ptx_isa >= 810
+
+#if __cccl_ptx_isa >= 810
+  NV_IF_TARGET(
+    NV_PROVIDES_SM_90,
+    (
+        // multimem.red.relaxed.cta.global.add.s32 [addr], val;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(cuda::ptx::sem_relaxed_t, cuda::ptx::scope_cta_t, cuda::ptx::op_add_t, int32_t*, int32_t)>(
+            cuda::ptx::multimem_red));
+          // multimem.red.relaxed.cluster.global.add.s32 [addr], val;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::sem_relaxed_t, cuda::ptx::scope_cluster_t, cuda::ptx::op_add_t, int32_t*, int32_t)>(
+                cuda::ptx::multimem_red));
+          // multimem.red.relaxed.gpu.global.add.s32 [addr], val;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::sem_relaxed_t, cuda::ptx::scope_gpu_t, cuda::ptx::op_add_t, int32_t*, int32_t)>(
+                cuda::ptx::multimem_red));
+          // multimem.red.relaxed.sys.global.add.s32 [addr], val;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::sem_relaxed_t, cuda::ptx::scope_sys_t, cuda::ptx::op_add_t, int32_t*, int32_t)>(
+                cuda::ptx::multimem_red));
+          // multimem.red.release.cta.global.add.s32 [addr], val;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::sem_release_t, cuda::ptx::scope_cta_t, cuda::ptx::op_add_t, int32_t*, int32_t)>(
+                cuda::ptx::multimem_red));
+          // multimem.red.release.cluster.global.add.s32 [addr], val;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::sem_release_t, cuda::ptx::scope_cluster_t, cuda::ptx::op_add_t, int32_t*, int32_t)>(
+                cuda::ptx::multimem_red));
+          // multimem.red.release.gpu.global.add.s32 [addr], val;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::sem_release_t, cuda::ptx::scope_gpu_t, cuda::ptx::op_add_t, int32_t*, int32_t)>(
+                cuda::ptx::multimem_red));
+          // multimem.red.release.sys.global.add.s32 [addr], val;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::sem_release_t, cuda::ptx::scope_sys_t, cuda::ptx::op_add_t, int32_t*, int32_t)>(
+                cuda::ptx::multimem_red));));
+#endif // __cccl_ptx_isa >= 810
+
+#if __cccl_ptx_isa >= 810
+  NV_IF_TARGET(
+    NV_PROVIDES_SM_90,
+    (
+        // multimem.red.relaxed.cta.global.add.u64 [addr], val;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(cuda::ptx::sem_relaxed_t, cuda::ptx::scope_cta_t, cuda::ptx::op_add_t, int64_t*, int64_t)>(
+            cuda::ptx::multimem_red));
+          // multimem.red.relaxed.cluster.global.add.u64 [addr], val;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::sem_relaxed_t, cuda::ptx::scope_cluster_t, cuda::ptx::op_add_t, int64_t*, int64_t)>(
+                cuda::ptx::multimem_red));
+          // multimem.red.relaxed.gpu.global.add.u64 [addr], val;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::sem_relaxed_t, cuda::ptx::scope_gpu_t, cuda::ptx::op_add_t, int64_t*, int64_t)>(
+                cuda::ptx::multimem_red));
+          // multimem.red.relaxed.sys.global.add.u64 [addr], val;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::sem_relaxed_t, cuda::ptx::scope_sys_t, cuda::ptx::op_add_t, int64_t*, int64_t)>(
+                cuda::ptx::multimem_red));
+          // multimem.red.release.cta.global.add.u64 [addr], val;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::sem_release_t, cuda::ptx::scope_cta_t, cuda::ptx::op_add_t, int64_t*, int64_t)>(
+                cuda::ptx::multimem_red));
+          // multimem.red.release.cluster.global.add.u64 [addr], val;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::sem_release_t, cuda::ptx::scope_cluster_t, cuda::ptx::op_add_t, int64_t*, int64_t)>(
+                cuda::ptx::multimem_red));
+          // multimem.red.release.gpu.global.add.u64 [addr], val;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::sem_release_t, cuda::ptx::scope_gpu_t, cuda::ptx::op_add_t, int64_t*, int64_t)>(
+                cuda::ptx::multimem_red));
+          // multimem.red.release.sys.global.add.u64 [addr], val;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::sem_release_t, cuda::ptx::scope_sys_t, cuda::ptx::op_add_t, int64_t*, int64_t)>(
+                cuda::ptx::multimem_red));));
+#endif // __cccl_ptx_isa >= 810
+
+#if __cccl_ptx_isa >= 810
+  NV_IF_TARGET(
+    NV_PROVIDES_SM_90,
+    (
+        // multimem.red.relaxed.cta.global.and.b32 [addr], val;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(
+            cuda::ptx::sem_relaxed_t, cuda::ptx::scope_cta_t, cuda::ptx::op_and_op_t, int32_t*, int32_t)>(
+            cuda::ptx::multimem_red));
+          // multimem.red.relaxed.cluster.global.and.b32 [addr], val;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::sem_relaxed_t, cuda::ptx::scope_cluster_t, cuda::ptx::op_and_op_t, int32_t*, int32_t)>(
+                cuda::ptx::multimem_red));
+          // multimem.red.relaxed.gpu.global.and.b32 [addr], val;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::sem_relaxed_t, cuda::ptx::scope_gpu_t, cuda::ptx::op_and_op_t, int32_t*, int32_t)>(
+                cuda::ptx::multimem_red));
+          // multimem.red.relaxed.sys.global.and.b32 [addr], val;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::sem_relaxed_t, cuda::ptx::scope_sys_t, cuda::ptx::op_and_op_t, int32_t*, int32_t)>(
+                cuda::ptx::multimem_red));
+          // multimem.red.release.cta.global.and.b32 [addr], val;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::sem_release_t, cuda::ptx::scope_cta_t, cuda::ptx::op_and_op_t, int32_t*, int32_t)>(
+                cuda::ptx::multimem_red));
+          // multimem.red.release.cluster.global.and.b32 [addr], val;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::sem_release_t, cuda::ptx::scope_cluster_t, cuda::ptx::op_and_op_t, int32_t*, int32_t)>(
+                cuda::ptx::multimem_red));
+          // multimem.red.release.gpu.global.and.b32 [addr], val;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::sem_release_t, cuda::ptx::scope_gpu_t, cuda::ptx::op_and_op_t, int32_t*, int32_t)>(
+                cuda::ptx::multimem_red));
+          // multimem.red.release.sys.global.and.b32 [addr], val;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::sem_release_t, cuda::ptx::scope_sys_t, cuda::ptx::op_and_op_t, int32_t*, int32_t)>(
+                cuda::ptx::multimem_red));));
+#endif // __cccl_ptx_isa >= 810
+
+#if __cccl_ptx_isa >= 810
+  NV_IF_TARGET(
+    NV_PROVIDES_SM_90,
+    (
+        // multimem.red.relaxed.cta.global.or.b32 [addr], val;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(
+            cuda::ptx::sem_relaxed_t, cuda::ptx::scope_cta_t, cuda::ptx::op_or_op_t, int32_t*, int32_t)>(
+            cuda::ptx::multimem_red));
+          // multimem.red.relaxed.cluster.global.or.b32 [addr], val;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::sem_relaxed_t, cuda::ptx::scope_cluster_t, cuda::ptx::op_or_op_t, int32_t*, int32_t)>(
+                cuda::ptx::multimem_red));
+          // multimem.red.relaxed.gpu.global.or.b32 [addr], val;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::sem_relaxed_t, cuda::ptx::scope_gpu_t, cuda::ptx::op_or_op_t, int32_t*, int32_t)>(
+                cuda::ptx::multimem_red));
+          // multimem.red.relaxed.sys.global.or.b32 [addr], val;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::sem_relaxed_t, cuda::ptx::scope_sys_t, cuda::ptx::op_or_op_t, int32_t*, int32_t)>(
+                cuda::ptx::multimem_red));
+          // multimem.red.release.cta.global.or.b32 [addr], val;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::sem_release_t, cuda::ptx::scope_cta_t, cuda::ptx::op_or_op_t, int32_t*, int32_t)>(
+                cuda::ptx::multimem_red));
+          // multimem.red.release.cluster.global.or.b32 [addr], val;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::sem_release_t, cuda::ptx::scope_cluster_t, cuda::ptx::op_or_op_t, int32_t*, int32_t)>(
+                cuda::ptx::multimem_red));
+          // multimem.red.release.gpu.global.or.b32 [addr], val;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::sem_release_t, cuda::ptx::scope_gpu_t, cuda::ptx::op_or_op_t, int32_t*, int32_t)>(
+                cuda::ptx::multimem_red));
+          // multimem.red.release.sys.global.or.b32 [addr], val;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::sem_release_t, cuda::ptx::scope_sys_t, cuda::ptx::op_or_op_t, int32_t*, int32_t)>(
+                cuda::ptx::multimem_red));));
+#endif // __cccl_ptx_isa >= 810
+
+#if __cccl_ptx_isa >= 810
+  NV_IF_TARGET(
+    NV_PROVIDES_SM_90,
+    (
+        // multimem.red.relaxed.cta.global.xor.b32 [addr], val;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(
+            cuda::ptx::sem_relaxed_t, cuda::ptx::scope_cta_t, cuda::ptx::op_xor_op_t, int32_t*, int32_t)>(
+            cuda::ptx::multimem_red));
+          // multimem.red.relaxed.cluster.global.xor.b32 [addr], val;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::sem_relaxed_t, cuda::ptx::scope_cluster_t, cuda::ptx::op_xor_op_t, int32_t*, int32_t)>(
+                cuda::ptx::multimem_red));
+          // multimem.red.relaxed.gpu.global.xor.b32 [addr], val;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::sem_relaxed_t, cuda::ptx::scope_gpu_t, cuda::ptx::op_xor_op_t, int32_t*, int32_t)>(
+                cuda::ptx::multimem_red));
+          // multimem.red.relaxed.sys.global.xor.b32 [addr], val;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::sem_relaxed_t, cuda::ptx::scope_sys_t, cuda::ptx::op_xor_op_t, int32_t*, int32_t)>(
+                cuda::ptx::multimem_red));
+          // multimem.red.release.cta.global.xor.b32 [addr], val;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::sem_release_t, cuda::ptx::scope_cta_t, cuda::ptx::op_xor_op_t, int32_t*, int32_t)>(
+                cuda::ptx::multimem_red));
+          // multimem.red.release.cluster.global.xor.b32 [addr], val;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::sem_release_t, cuda::ptx::scope_cluster_t, cuda::ptx::op_xor_op_t, int32_t*, int32_t)>(
+                cuda::ptx::multimem_red));
+          // multimem.red.release.gpu.global.xor.b32 [addr], val;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::sem_release_t, cuda::ptx::scope_gpu_t, cuda::ptx::op_xor_op_t, int32_t*, int32_t)>(
+                cuda::ptx::multimem_red));
+          // multimem.red.release.sys.global.xor.b32 [addr], val;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::sem_release_t, cuda::ptx::scope_sys_t, cuda::ptx::op_xor_op_t, int32_t*, int32_t)>(
+                cuda::ptx::multimem_red));));
+#endif // __cccl_ptx_isa >= 810
+
+#if __cccl_ptx_isa >= 810
+  NV_IF_TARGET(
+    NV_PROVIDES_SM_90,
+    (
+        // multimem.red.relaxed.cta.global.and.b64 [addr], val;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(
+            cuda::ptx::sem_relaxed_t, cuda::ptx::scope_cta_t, cuda::ptx::op_and_op_t, int64_t*, int64_t)>(
+            cuda::ptx::multimem_red));
+          // multimem.red.relaxed.cluster.global.and.b64 [addr], val;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::sem_relaxed_t, cuda::ptx::scope_cluster_t, cuda::ptx::op_and_op_t, int64_t*, int64_t)>(
+                cuda::ptx::multimem_red));
+          // multimem.red.relaxed.gpu.global.and.b64 [addr], val;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::sem_relaxed_t, cuda::ptx::scope_gpu_t, cuda::ptx::op_and_op_t, int64_t*, int64_t)>(
+                cuda::ptx::multimem_red));
+          // multimem.red.relaxed.sys.global.and.b64 [addr], val;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::sem_relaxed_t, cuda::ptx::scope_sys_t, cuda::ptx::op_and_op_t, int64_t*, int64_t)>(
+                cuda::ptx::multimem_red));
+          // multimem.red.release.cta.global.and.b64 [addr], val;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::sem_release_t, cuda::ptx::scope_cta_t, cuda::ptx::op_and_op_t, int64_t*, int64_t)>(
+                cuda::ptx::multimem_red));
+          // multimem.red.release.cluster.global.and.b64 [addr], val;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::sem_release_t, cuda::ptx::scope_cluster_t, cuda::ptx::op_and_op_t, int64_t*, int64_t)>(
+                cuda::ptx::multimem_red));
+          // multimem.red.release.gpu.global.and.b64 [addr], val;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::sem_release_t, cuda::ptx::scope_gpu_t, cuda::ptx::op_and_op_t, int64_t*, int64_t)>(
+                cuda::ptx::multimem_red));
+          // multimem.red.release.sys.global.and.b64 [addr], val;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::sem_release_t, cuda::ptx::scope_sys_t, cuda::ptx::op_and_op_t, int64_t*, int64_t)>(
+                cuda::ptx::multimem_red));));
+#endif // __cccl_ptx_isa >= 810
+
+#if __cccl_ptx_isa >= 810
+  NV_IF_TARGET(
+    NV_PROVIDES_SM_90,
+    (
+        // multimem.red.relaxed.cta.global.or.b64 [addr], val;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(
+            cuda::ptx::sem_relaxed_t, cuda::ptx::scope_cta_t, cuda::ptx::op_or_op_t, int64_t*, int64_t)>(
+            cuda::ptx::multimem_red));
+          // multimem.red.relaxed.cluster.global.or.b64 [addr], val;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::sem_relaxed_t, cuda::ptx::scope_cluster_t, cuda::ptx::op_or_op_t, int64_t*, int64_t)>(
+                cuda::ptx::multimem_red));
+          // multimem.red.relaxed.gpu.global.or.b64 [addr], val;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::sem_relaxed_t, cuda::ptx::scope_gpu_t, cuda::ptx::op_or_op_t, int64_t*, int64_t)>(
+                cuda::ptx::multimem_red));
+          // multimem.red.relaxed.sys.global.or.b64 [addr], val;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::sem_relaxed_t, cuda::ptx::scope_sys_t, cuda::ptx::op_or_op_t, int64_t*, int64_t)>(
+                cuda::ptx::multimem_red));
+          // multimem.red.release.cta.global.or.b64 [addr], val;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::sem_release_t, cuda::ptx::scope_cta_t, cuda::ptx::op_or_op_t, int64_t*, int64_t)>(
+                cuda::ptx::multimem_red));
+          // multimem.red.release.cluster.global.or.b64 [addr], val;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::sem_release_t, cuda::ptx::scope_cluster_t, cuda::ptx::op_or_op_t, int64_t*, int64_t)>(
+                cuda::ptx::multimem_red));
+          // multimem.red.release.gpu.global.or.b64 [addr], val;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::sem_release_t, cuda::ptx::scope_gpu_t, cuda::ptx::op_or_op_t, int64_t*, int64_t)>(
+                cuda::ptx::multimem_red));
+          // multimem.red.release.sys.global.or.b64 [addr], val;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::sem_release_t, cuda::ptx::scope_sys_t, cuda::ptx::op_or_op_t, int64_t*, int64_t)>(
+                cuda::ptx::multimem_red));));
+#endif // __cccl_ptx_isa >= 810
+
+#if __cccl_ptx_isa >= 810
+  NV_IF_TARGET(
+    NV_PROVIDES_SM_90,
+    (
+        // multimem.red.relaxed.cta.global.xor.b64 [addr], val;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(
+            cuda::ptx::sem_relaxed_t, cuda::ptx::scope_cta_t, cuda::ptx::op_xor_op_t, int64_t*, int64_t)>(
+            cuda::ptx::multimem_red));
+          // multimem.red.relaxed.cluster.global.xor.b64 [addr], val;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::sem_relaxed_t, cuda::ptx::scope_cluster_t, cuda::ptx::op_xor_op_t, int64_t*, int64_t)>(
+                cuda::ptx::multimem_red));
+          // multimem.red.relaxed.gpu.global.xor.b64 [addr], val;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::sem_relaxed_t, cuda::ptx::scope_gpu_t, cuda::ptx::op_xor_op_t, int64_t*, int64_t)>(
+                cuda::ptx::multimem_red));
+          // multimem.red.relaxed.sys.global.xor.b64 [addr], val;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::sem_relaxed_t, cuda::ptx::scope_sys_t, cuda::ptx::op_xor_op_t, int64_t*, int64_t)>(
+                cuda::ptx::multimem_red));
+          // multimem.red.release.cta.global.xor.b64 [addr], val;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::sem_release_t, cuda::ptx::scope_cta_t, cuda::ptx::op_xor_op_t, int64_t*, int64_t)>(
+                cuda::ptx::multimem_red));
+          // multimem.red.release.cluster.global.xor.b64 [addr], val;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::sem_release_t, cuda::ptx::scope_cluster_t, cuda::ptx::op_xor_op_t, int64_t*, int64_t)>(
+                cuda::ptx::multimem_red));
+          // multimem.red.release.gpu.global.xor.b64 [addr], val;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::sem_release_t, cuda::ptx::scope_gpu_t, cuda::ptx::op_xor_op_t, int64_t*, int64_t)>(
+                cuda::ptx::multimem_red));
+          // multimem.red.release.sys.global.xor.b64 [addr], val;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::sem_release_t, cuda::ptx::scope_sys_t, cuda::ptx::op_xor_op_t, int64_t*, int64_t)>(
+                cuda::ptx::multimem_red));));
+#endif // __cccl_ptx_isa >= 810
+}
diff --git a/libcudacxx/test/libcudacxx/cuda/ptx/generated/multimem_st.h b/libcudacxx/test/libcudacxx/cuda/ptx/generated/multimem_st.h
new file mode 100644
index 00000000000..b61c25430ed
--- /dev/null
+++ b/libcudacxx/test/libcudacxx/cuda/ptx/generated/multimem_st.h
@@ -0,0 +1,110 @@
+// This file was automatically generated. Do not edit.
+
+// We use a special strategy to force the generation of the PTX. This is mainly
+// a fight against dead-code-elimination in the NVVM layer.
+//
+// The reason we need this strategy is because certain older versions of ptxas
+// segfault when a non-sensical sequence of PTX is generated. So instead, we try
+// to force the instantiation and compilation to PTX of all the overloads of the
+// PTX wrapping functions.
+//
+// We do this by writing a function pointer of each overload to the kernel
+// parameter `fn_ptr`.
+//
+// Because `fn_ptr` is possibly visible outside this translation unit, the
+// compiler must compile all the functions which are stored.
+
+__global__ void test_multimem_st(void** fn_ptr)
+{
+#if __cccl_ptx_isa >= 810
+  NV_IF_TARGET(NV_PROVIDES_SM_90,
+               (
+                   // multimem.st.weak.global.b32 [addr], val;
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(cuda::ptx::sem_weak_t, int32_t*, int32_t)>(cuda::ptx::multimem_st));));
+#endif // __cccl_ptx_isa >= 810
+
+#if __cccl_ptx_isa >= 810
+  NV_IF_TARGET(
+    NV_PROVIDES_SM_90,
+    (
+        // multimem.st.relaxed.cta.global.b32 [addr], val;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(cuda::ptx::sem_relaxed_t, cuda::ptx::scope_cta_t, int32_t*, int32_t)>(
+            cuda::ptx::multimem_st));
+          // multimem.st.relaxed.cluster.global.b32 [addr], val;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::sem_relaxed_t, cuda::ptx::scope_cluster_t, int32_t*, int32_t)>(
+                cuda::ptx::multimem_st));
+          // multimem.st.relaxed.gpu.global.b32 [addr], val;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::sem_relaxed_t, cuda::ptx::scope_gpu_t, int32_t*, int32_t)>(
+                cuda::ptx::multimem_st));
+          // multimem.st.relaxed.sys.global.b32 [addr], val;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::sem_relaxed_t, cuda::ptx::scope_sys_t, int32_t*, int32_t)>(
+                cuda::ptx::multimem_st));
+          // multimem.st.release.cta.global.b32 [addr], val;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::sem_release_t, cuda::ptx::scope_cta_t, int32_t*, int32_t)>(
+                cuda::ptx::multimem_st));
+          // multimem.st.release.cluster.global.b32 [addr], val;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::sem_release_t, cuda::ptx::scope_cluster_t, int32_t*, int32_t)>(
+                cuda::ptx::multimem_st));
+          // multimem.st.release.gpu.global.b32 [addr], val;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::sem_release_t, cuda::ptx::scope_gpu_t, int32_t*, int32_t)>(
+                cuda::ptx::multimem_st));
+          // multimem.st.release.sys.global.b32 [addr], val;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::sem_release_t, cuda::ptx::scope_sys_t, int32_t*, int32_t)>(
+                cuda::ptx::multimem_st));));
+#endif // __cccl_ptx_isa >= 810
+
+#if __cccl_ptx_isa >= 810
+  NV_IF_TARGET(NV_PROVIDES_SM_90,
+               (
+                   // multimem.st.weak.global.b64 [addr], val;
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(cuda::ptx::sem_weak_t, int64_t*, int64_t)>(cuda::ptx::multimem_st));));
+#endif // __cccl_ptx_isa >= 810
+
+#if __cccl_ptx_isa >= 810
+  NV_IF_TARGET(
+    NV_PROVIDES_SM_90,
+    (
+        // multimem.st.relaxed.cta.global.b64 [addr], val;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(cuda::ptx::sem_relaxed_t, cuda::ptx::scope_cta_t, int64_t*, int64_t)>(
+            cuda::ptx::multimem_st));
+          // multimem.st.relaxed.cluster.global.b64 [addr], val;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::sem_relaxed_t, cuda::ptx::scope_cluster_t, int64_t*, int64_t)>(
+                cuda::ptx::multimem_st));
+          // multimem.st.relaxed.gpu.global.b64 [addr], val;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::sem_relaxed_t, cuda::ptx::scope_gpu_t, int64_t*, int64_t)>(
+                cuda::ptx::multimem_st));
+          // multimem.st.relaxed.sys.global.b64 [addr], val;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::sem_relaxed_t, cuda::ptx::scope_sys_t, int64_t*, int64_t)>(
+                cuda::ptx::multimem_st));
+          // multimem.st.release.cta.global.b64 [addr], val;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::sem_release_t, cuda::ptx::scope_cta_t, int64_t*, int64_t)>(
+                cuda::ptx::multimem_st));
+          // multimem.st.release.cluster.global.b64 [addr], val;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::sem_release_t, cuda::ptx::scope_cluster_t, int64_t*, int64_t)>(
+                cuda::ptx::multimem_st));
+          // multimem.st.release.gpu.global.b64 [addr], val;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::sem_release_t, cuda::ptx::scope_gpu_t, int64_t*, int64_t)>(
+                cuda::ptx::multimem_st));
+          // multimem.st.release.sys.global.b64 [addr], val;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::sem_release_t, cuda::ptx::scope_sys_t, int64_t*, int64_t)>(
+                cuda::ptx::multimem_st));));
+#endif // __cccl_ptx_isa >= 810
+}
diff --git a/libcudacxx/test/libcudacxx/cuda/ptx/generated/st_bulk.h b/libcudacxx/test/libcudacxx/cuda/ptx/generated/st_bulk.h
new file mode 100644
index 00000000000..d9203b625e8
--- /dev/null
+++ b/libcudacxx/test/libcudacxx/cuda/ptx/generated/st_bulk.h
@@ -0,0 +1,26 @@
+// This file was automatically generated. Do not edit.
+
+// We use a special strategy to force the generation of the PTX. This is mainly
+// a fight against dead-code-elimination in the NVVM layer.
+//
+// The reason we need this strategy is because certain older versions of ptxas
+// segfault when a non-sensical sequence of PTX is generated. So instead, we try
+// to force the instantiation and compilation to PTX of all the overloads of the
+// PTX wrapping functions.
+//
+// We do this by writing a function pointer of each overload to the kernel
+// parameter `fn_ptr`.
+//
+// Because `fn_ptr` is possibly visible outside this translation unit, the
+// compiler must compile all the functions which are stored.
+
+__global__ void test_st_bulk(void** fn_ptr)
+{
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(NV_PROVIDES_SM_100,
+               (
+                   // st.bulk.weak.shared::cta [addr], size, initval;
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(void*, uint64_t, cuda::ptx::n32_t<0>)>(cuda::ptx::st_bulk));));
+#endif // __cccl_ptx_isa >= 860
+}
diff --git a/libcudacxx/test/libcudacxx/cuda/ptx/generated/tcgen05_alloc.h b/libcudacxx/test/libcudacxx/cuda/ptx/generated/tcgen05_alloc.h
new file mode 100644
index 00000000000..48a40f6f23c
--- /dev/null
+++ b/libcudacxx/test/libcudacxx/cuda/ptx/generated/tcgen05_alloc.h
@@ -0,0 +1,81 @@
+// This file was automatically generated. Do not edit.
+
+// We use a special strategy to force the generation of the PTX. This is mainly
+// a fight against dead-code-elimination in the NVVM layer.
+//
+// The reason we need this strategy is because certain older versions of ptxas
+// segfault when a non-sensical sequence of PTX is generated. So instead, we try
+// to force the instantiation and compilation to PTX of all the overloads of the
+// PTX wrapping functions.
+//
+// We do this by writing a function pointer of each overload to the kernel
+// parameter `fn_ptr`.
+//
+// Because `fn_ptr` is possibly visible outside this translation unit, the
+// compiler must compile all the functions which are stored.
+
+__global__ void test_tcgen05_alloc(void** fn_ptr)
+{
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [dst], nCols;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(cuda::ptx::cta_group_1_t, uint32_t*, const uint32_t&)>(cuda::ptx::tcgen05_alloc));
+          // tcgen05.alloc.cta_group::2.sync.aligned.shared::cta.b32 [dst], nCols;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::cta_group_2_t, uint32_t*, const uint32_t&)>(cuda::ptx::tcgen05_alloc));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [dst], nCols;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(cuda::ptx::cta_group_1_t, uint32_t*, const uint32_t&)>(cuda::ptx::tcgen05_alloc));
+          // tcgen05.alloc.cta_group::2.sync.aligned.shared::cta.b32 [dst], nCols;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::cta_group_2_t, uint32_t*, const uint32_t&)>(cuda::ptx::tcgen05_alloc));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tcgen05.dealloc.cta_group::1.sync.aligned.b32 taddr, nCols;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(cuda::ptx::cta_group_1_t, uint32_t, const uint32_t&)>(cuda::ptx::tcgen05_dealloc));
+          // tcgen05.dealloc.cta_group::2.sync.aligned.b32 taddr, nCols;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::cta_group_2_t, uint32_t, const uint32_t&)>(cuda::ptx::tcgen05_dealloc));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // tcgen05.dealloc.cta_group::1.sync.aligned.b32 taddr, nCols;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(cuda::ptx::cta_group_1_t, uint32_t, const uint32_t&)>(cuda::ptx::tcgen05_dealloc));
+          // tcgen05.dealloc.cta_group::2.sync.aligned.b32 taddr, nCols;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::cta_group_2_t, uint32_t, const uint32_t&)>(cuda::ptx::tcgen05_dealloc));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(cuda::ptx::cta_group_1_t)>(cuda::ptx::tcgen05_relinquish_alloc_permit));
+          // tcgen05.relinquish_alloc_permit.cta_group::2.sync.aligned;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::cta_group_2_t)>(cuda::ptx::tcgen05_relinquish_alloc_permit));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(cuda::ptx::cta_group_1_t)>(cuda::ptx::tcgen05_relinquish_alloc_permit));
+          // tcgen05.relinquish_alloc_permit.cta_group::2.sync.aligned;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::cta_group_2_t)>(cuda::ptx::tcgen05_relinquish_alloc_permit));));
+#endif // __cccl_ptx_isa >= 860
+}
diff --git a/libcudacxx/test/libcudacxx/cuda/ptx/generated/tcgen05_commit.h b/libcudacxx/test/libcudacxx/cuda/ptx/generated/tcgen05_commit.h
new file mode 100644
index 00000000000..c41981e6917
--- /dev/null
+++ b/libcudacxx/test/libcudacxx/cuda/ptx/generated/tcgen05_commit.h
@@ -0,0 +1,62 @@
+// This file was automatically generated. Do not edit.
+
+// We use a special strategy to force the generation of the PTX. This is mainly
+// a fight against dead-code-elimination in the NVVM layer.
+//
+// The reason we need this strategy is because certain older versions of ptxas
+// segfault when a non-sensical sequence of PTX is generated. So instead, we try
+// to force the instantiation and compilation to PTX of all the overloads of the
+// PTX wrapping functions.
+//
+// We do this by writing a function pointer of each overload to the kernel
+// parameter `fn_ptr`.
+//
+// Because `fn_ptr` is possibly visible outside this translation unit, the
+// compiler must compile all the functions which are stored.
+
+__global__ void test_tcgen05_commit(void** fn_ptr)
+{
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tcgen05.commit.cta_group::1.mbarrier::arrive::one.shared::cluster.b64 [smem_bar];
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(cuda::ptx::cta_group_1_t, uint64_t*)>(cuda::ptx::tcgen05_commit));
+          // tcgen05.commit.cta_group::2.mbarrier::arrive::one.shared::cluster.b64 [smem_bar];
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::cta_group_2_t, uint64_t*)>(cuda::ptx::tcgen05_commit));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // tcgen05.commit.cta_group::1.mbarrier::arrive::one.shared::cluster.b64 [smem_bar];
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(cuda::ptx::cta_group_1_t, uint64_t*)>(cuda::ptx::tcgen05_commit));
+          // tcgen05.commit.cta_group::2.mbarrier::arrive::one.shared::cluster.b64 [smem_bar];
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::cta_group_2_t, uint64_t*)>(cuda::ptx::tcgen05_commit));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tcgen05.commit.cta_group::1.mbarrier::arrive::one.shared::cluster.multicast::cluster.b64 [smem_bar], ctaMask;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(cuda::ptx::cta_group_1_t, uint64_t*, uint16_t)>(cuda::ptx::tcgen05_commit_multicast));
+          // tcgen05.commit.cta_group::2.mbarrier::arrive::one.shared::cluster.multicast::cluster.b64 [smem_bar],
+          // ctaMask;
+            * fn_ptr++ = reinterpret_cast<void*>(static_cast<void (*)(cuda::ptx::cta_group_2_t, uint64_t*, uint16_t)>(
+              cuda::ptx::tcgen05_commit_multicast));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // tcgen05.commit.cta_group::1.mbarrier::arrive::one.shared::cluster.multicast::cluster.b64 [smem_bar], ctaMask;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(cuda::ptx::cta_group_1_t, uint64_t*, uint16_t)>(cuda::ptx::tcgen05_commit_multicast));
+          // tcgen05.commit.cta_group::2.mbarrier::arrive::one.shared::cluster.multicast::cluster.b64 [smem_bar],
+          // ctaMask;
+            * fn_ptr++ = reinterpret_cast<void*>(static_cast<void (*)(cuda::ptx::cta_group_2_t, uint64_t*, uint16_t)>(
+              cuda::ptx::tcgen05_commit_multicast));));
+#endif // __cccl_ptx_isa >= 860
+}
diff --git a/libcudacxx/test/libcudacxx/cuda/ptx/generated/tcgen05_cp.h b/libcudacxx/test/libcudacxx/cuda/ptx/generated/tcgen05_cp.h
new file mode 100644
index 00000000000..4c37cb11cfa
--- /dev/null
+++ b/libcudacxx/test/libcudacxx/cuda/ptx/generated/tcgen05_cp.h
@@ -0,0 +1,396 @@
+// This file was automatically generated. Do not edit.
+
+// We use a special strategy to force the generation of the PTX. This is mainly
+// a fight against dead-code-elimination in the NVVM layer.
+//
+// The reason we need this strategy is because certain older versions of ptxas
+// segfault when a non-sensical sequence of PTX is generated. So instead, we try
+// to force the instantiation and compilation to PTX of all the overloads of the
+// PTX wrapping functions.
+//
+// We do this by writing a function pointer of each overload to the kernel
+// parameter `fn_ptr`.
+//
+// Because `fn_ptr` is possibly visible outside this translation unit, the
+// compiler must compile all the functions which are stored.
+
+__global__ void test_tcgen05_cp(void** fn_ptr)
+{
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tcgen05.cp.cta_group::1.128x256b [taddr], s_desc;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(cuda::ptx::cta_group_1_t, uint32_t, uint64_t)>(cuda::ptx::tcgen05_cp_128x256b));
+          // tcgen05.cp.cta_group::2.128x256b [taddr], s_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::cta_group_2_t, uint32_t, uint64_t)>(cuda::ptx::tcgen05_cp_128x256b));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // tcgen05.cp.cta_group::1.128x256b [taddr], s_desc;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(cuda::ptx::cta_group_1_t, uint32_t, uint64_t)>(cuda::ptx::tcgen05_cp_128x256b));
+          // tcgen05.cp.cta_group::2.128x256b [taddr], s_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::cta_group_2_t, uint32_t, uint64_t)>(cuda::ptx::tcgen05_cp_128x256b));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tcgen05.cp.cta_group::1.4x256b [taddr], s_desc;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(cuda::ptx::cta_group_1_t, uint32_t, uint64_t)>(cuda::ptx::tcgen05_cp_4x256b));
+          // tcgen05.cp.cta_group::2.4x256b [taddr], s_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::cta_group_2_t, uint32_t, uint64_t)>(cuda::ptx::tcgen05_cp_4x256b));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // tcgen05.cp.cta_group::1.4x256b [taddr], s_desc;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(cuda::ptx::cta_group_1_t, uint32_t, uint64_t)>(cuda::ptx::tcgen05_cp_4x256b));
+          // tcgen05.cp.cta_group::2.4x256b [taddr], s_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::cta_group_2_t, uint32_t, uint64_t)>(cuda::ptx::tcgen05_cp_4x256b));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tcgen05.cp.cta_group::1.128x128b [taddr], s_desc;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(cuda::ptx::cta_group_1_t, uint32_t, uint64_t)>(cuda::ptx::tcgen05_cp_128x128b));
+          // tcgen05.cp.cta_group::2.128x128b [taddr], s_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::cta_group_2_t, uint32_t, uint64_t)>(cuda::ptx::tcgen05_cp_128x128b));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // tcgen05.cp.cta_group::1.128x128b [taddr], s_desc;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(cuda::ptx::cta_group_1_t, uint32_t, uint64_t)>(cuda::ptx::tcgen05_cp_128x128b));
+          // tcgen05.cp.cta_group::2.128x128b [taddr], s_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::cta_group_2_t, uint32_t, uint64_t)>(cuda::ptx::tcgen05_cp_128x128b));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tcgen05.cp.cta_group::1.64x128b.warpx2::02_13 [taddr], s_desc;
+        * fn_ptr++ = reinterpret_cast<void*>(static_cast<void (*)(cuda::ptx::cta_group_1_t, uint32_t, uint64_t)>(
+          cuda::ptx::tcgen05_cp_64x128b_warpx2_02_13));
+          // tcgen05.cp.cta_group::2.64x128b.warpx2::02_13 [taddr], s_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(static_cast<void (*)(cuda::ptx::cta_group_2_t, uint32_t, uint64_t)>(
+              cuda::ptx::tcgen05_cp_64x128b_warpx2_02_13));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // tcgen05.cp.cta_group::1.64x128b.warpx2::02_13 [taddr], s_desc;
+        * fn_ptr++ = reinterpret_cast<void*>(static_cast<void (*)(cuda::ptx::cta_group_1_t, uint32_t, uint64_t)>(
+          cuda::ptx::tcgen05_cp_64x128b_warpx2_02_13));
+          // tcgen05.cp.cta_group::2.64x128b.warpx2::02_13 [taddr], s_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(static_cast<void (*)(cuda::ptx::cta_group_2_t, uint32_t, uint64_t)>(
+              cuda::ptx::tcgen05_cp_64x128b_warpx2_02_13));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tcgen05.cp.cta_group::1.64x128b.warpx2::01_23 [taddr], s_desc;
+        * fn_ptr++ = reinterpret_cast<void*>(static_cast<void (*)(cuda::ptx::cta_group_1_t, uint32_t, uint64_t)>(
+          cuda::ptx::tcgen05_cp_64x128b_warpx2_01_23));
+          // tcgen05.cp.cta_group::2.64x128b.warpx2::01_23 [taddr], s_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(static_cast<void (*)(cuda::ptx::cta_group_2_t, uint32_t, uint64_t)>(
+              cuda::ptx::tcgen05_cp_64x128b_warpx2_01_23));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // tcgen05.cp.cta_group::1.64x128b.warpx2::01_23 [taddr], s_desc;
+        * fn_ptr++ = reinterpret_cast<void*>(static_cast<void (*)(cuda::ptx::cta_group_1_t, uint32_t, uint64_t)>(
+          cuda::ptx::tcgen05_cp_64x128b_warpx2_01_23));
+          // tcgen05.cp.cta_group::2.64x128b.warpx2::01_23 [taddr], s_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(static_cast<void (*)(cuda::ptx::cta_group_2_t, uint32_t, uint64_t)>(
+              cuda::ptx::tcgen05_cp_64x128b_warpx2_01_23));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tcgen05.cp.cta_group::1.32x128b.warpx4 [taddr], s_desc;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(cuda::ptx::cta_group_1_t, uint32_t, uint64_t)>(cuda::ptx::tcgen05_cp_32x128b_warpx4));
+          // tcgen05.cp.cta_group::2.32x128b.warpx4 [taddr], s_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(static_cast<void (*)(cuda::ptx::cta_group_2_t, uint32_t, uint64_t)>(
+              cuda::ptx::tcgen05_cp_32x128b_warpx4));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // tcgen05.cp.cta_group::1.32x128b.warpx4 [taddr], s_desc;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(cuda::ptx::cta_group_1_t, uint32_t, uint64_t)>(cuda::ptx::tcgen05_cp_32x128b_warpx4));
+          // tcgen05.cp.cta_group::2.32x128b.warpx4 [taddr], s_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(static_cast<void (*)(cuda::ptx::cta_group_2_t, uint32_t, uint64_t)>(
+              cuda::ptx::tcgen05_cp_32x128b_warpx4));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tcgen05.cp.cta_group::1.128x256b.b8x16.b6x16_p32 [taddr], s_desc;
+        * fn_ptr++ = reinterpret_cast<void*>(static_cast<void (*)(cuda::ptx::cta_group_1_t, uint32_t, uint64_t)>(
+          cuda::ptx::tcgen05_cp_128x256b_b8x16_b6x16_p32));
+          // tcgen05.cp.cta_group::2.128x256b.b8x16.b6x16_p32 [taddr], s_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(static_cast<void (*)(cuda::ptx::cta_group_2_t, uint32_t, uint64_t)>(
+              cuda::ptx::tcgen05_cp_128x256b_b8x16_b6x16_p32));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // tcgen05.cp.cta_group::1.128x256b.b8x16.b6x16_p32 [taddr], s_desc;
+        * fn_ptr++ = reinterpret_cast<void*>(static_cast<void (*)(cuda::ptx::cta_group_1_t, uint32_t, uint64_t)>(
+          cuda::ptx::tcgen05_cp_128x256b_b8x16_b6x16_p32));
+          // tcgen05.cp.cta_group::2.128x256b.b8x16.b6x16_p32 [taddr], s_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(static_cast<void (*)(cuda::ptx::cta_group_2_t, uint32_t, uint64_t)>(
+              cuda::ptx::tcgen05_cp_128x256b_b8x16_b6x16_p32));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tcgen05.cp.cta_group::1.4x256b.b8x16.b6x16_p32 [taddr], s_desc;
+        * fn_ptr++ = reinterpret_cast<void*>(static_cast<void (*)(cuda::ptx::cta_group_1_t, uint32_t, uint64_t)>(
+          cuda::ptx::tcgen05_cp_4x256b_b8x16_b6x16_p32));
+          // tcgen05.cp.cta_group::2.4x256b.b8x16.b6x16_p32 [taddr], s_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(static_cast<void (*)(cuda::ptx::cta_group_2_t, uint32_t, uint64_t)>(
+              cuda::ptx::tcgen05_cp_4x256b_b8x16_b6x16_p32));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // tcgen05.cp.cta_group::1.4x256b.b8x16.b6x16_p32 [taddr], s_desc;
+        * fn_ptr++ = reinterpret_cast<void*>(static_cast<void (*)(cuda::ptx::cta_group_1_t, uint32_t, uint64_t)>(
+          cuda::ptx::tcgen05_cp_4x256b_b8x16_b6x16_p32));
+          // tcgen05.cp.cta_group::2.4x256b.b8x16.b6x16_p32 [taddr], s_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(static_cast<void (*)(cuda::ptx::cta_group_2_t, uint32_t, uint64_t)>(
+              cuda::ptx::tcgen05_cp_4x256b_b8x16_b6x16_p32));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tcgen05.cp.cta_group::1.128x128b.b8x16.b6x16_p32 [taddr], s_desc;
+        * fn_ptr++ = reinterpret_cast<void*>(static_cast<void (*)(cuda::ptx::cta_group_1_t, uint32_t, uint64_t)>(
+          cuda::ptx::tcgen05_cp_128x128b_b8x16_b6x16_p32));
+          // tcgen05.cp.cta_group::2.128x128b.b8x16.b6x16_p32 [taddr], s_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(static_cast<void (*)(cuda::ptx::cta_group_2_t, uint32_t, uint64_t)>(
+              cuda::ptx::tcgen05_cp_128x128b_b8x16_b6x16_p32));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // tcgen05.cp.cta_group::1.128x128b.b8x16.b6x16_p32 [taddr], s_desc;
+        * fn_ptr++ = reinterpret_cast<void*>(static_cast<void (*)(cuda::ptx::cta_group_1_t, uint32_t, uint64_t)>(
+          cuda::ptx::tcgen05_cp_128x128b_b8x16_b6x16_p32));
+          // tcgen05.cp.cta_group::2.128x128b.b8x16.b6x16_p32 [taddr], s_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(static_cast<void (*)(cuda::ptx::cta_group_2_t, uint32_t, uint64_t)>(
+              cuda::ptx::tcgen05_cp_128x128b_b8x16_b6x16_p32));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tcgen05.cp.cta_group::1.64x128b.warpx2::02_13.b8x16.b6x16_p32 [taddr], s_desc;
+        * fn_ptr++ = reinterpret_cast<void*>(static_cast<void (*)(cuda::ptx::cta_group_1_t, uint32_t, uint64_t)>(
+          cuda::ptx::tcgen05_cp_64x128b_warpx2_02_13_b8x16_b6x16_p32));
+          // tcgen05.cp.cta_group::2.64x128b.warpx2::02_13.b8x16.b6x16_p32 [taddr], s_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(static_cast<void (*)(cuda::ptx::cta_group_2_t, uint32_t, uint64_t)>(
+              cuda::ptx::tcgen05_cp_64x128b_warpx2_02_13_b8x16_b6x16_p32));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // tcgen05.cp.cta_group::1.64x128b.warpx2::02_13.b8x16.b6x16_p32 [taddr], s_desc;
+        * fn_ptr++ = reinterpret_cast<void*>(static_cast<void (*)(cuda::ptx::cta_group_1_t, uint32_t, uint64_t)>(
+          cuda::ptx::tcgen05_cp_64x128b_warpx2_02_13_b8x16_b6x16_p32));
+          // tcgen05.cp.cta_group::2.64x128b.warpx2::02_13.b8x16.b6x16_p32 [taddr], s_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(static_cast<void (*)(cuda::ptx::cta_group_2_t, uint32_t, uint64_t)>(
+              cuda::ptx::tcgen05_cp_64x128b_warpx2_02_13_b8x16_b6x16_p32));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tcgen05.cp.cta_group::1.64x128b.warpx2::01_23.b8x16.b6x16_p32 [taddr], s_desc;
+        * fn_ptr++ = reinterpret_cast<void*>(static_cast<void (*)(cuda::ptx::cta_group_1_t, uint32_t, uint64_t)>(
+          cuda::ptx::tcgen05_cp_64x128b_warpx2_01_23_b8x16_b6x16_p32));
+          // tcgen05.cp.cta_group::2.64x128b.warpx2::01_23.b8x16.b6x16_p32 [taddr], s_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(static_cast<void (*)(cuda::ptx::cta_group_2_t, uint32_t, uint64_t)>(
+              cuda::ptx::tcgen05_cp_64x128b_warpx2_01_23_b8x16_b6x16_p32));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // tcgen05.cp.cta_group::1.64x128b.warpx2::01_23.b8x16.b6x16_p32 [taddr], s_desc;
+        * fn_ptr++ = reinterpret_cast<void*>(static_cast<void (*)(cuda::ptx::cta_group_1_t, uint32_t, uint64_t)>(
+          cuda::ptx::tcgen05_cp_64x128b_warpx2_01_23_b8x16_b6x16_p32));
+          // tcgen05.cp.cta_group::2.64x128b.warpx2::01_23.b8x16.b6x16_p32 [taddr], s_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(static_cast<void (*)(cuda::ptx::cta_group_2_t, uint32_t, uint64_t)>(
+              cuda::ptx::tcgen05_cp_64x128b_warpx2_01_23_b8x16_b6x16_p32));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tcgen05.cp.cta_group::1.32x128b.warpx4.b8x16.b6x16_p32 [taddr], s_desc;
+        * fn_ptr++ = reinterpret_cast<void*>(static_cast<void (*)(cuda::ptx::cta_group_1_t, uint32_t, uint64_t)>(
+          cuda::ptx::tcgen05_cp_32x128b_warpx4_b8x16_b6x16_p32));
+          // tcgen05.cp.cta_group::2.32x128b.warpx4.b8x16.b6x16_p32 [taddr], s_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(static_cast<void (*)(cuda::ptx::cta_group_2_t, uint32_t, uint64_t)>(
+              cuda::ptx::tcgen05_cp_32x128b_warpx4_b8x16_b6x16_p32));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // tcgen05.cp.cta_group::1.32x128b.warpx4.b8x16.b6x16_p32 [taddr], s_desc;
+        * fn_ptr++ = reinterpret_cast<void*>(static_cast<void (*)(cuda::ptx::cta_group_1_t, uint32_t, uint64_t)>(
+          cuda::ptx::tcgen05_cp_32x128b_warpx4_b8x16_b6x16_p32));
+          // tcgen05.cp.cta_group::2.32x128b.warpx4.b8x16.b6x16_p32 [taddr], s_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(static_cast<void (*)(cuda::ptx::cta_group_2_t, uint32_t, uint64_t)>(
+              cuda::ptx::tcgen05_cp_32x128b_warpx4_b8x16_b6x16_p32));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tcgen05.cp.cta_group::1.128x256b.b8x16.b4x16_p64 [taddr], s_desc;
+        * fn_ptr++ = reinterpret_cast<void*>(static_cast<void (*)(cuda::ptx::cta_group_1_t, uint32_t, uint64_t)>(
+          cuda::ptx::tcgen05_cp_128x256b_b8x16_b4x16_p64));
+          // tcgen05.cp.cta_group::2.128x256b.b8x16.b4x16_p64 [taddr], s_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(static_cast<void (*)(cuda::ptx::cta_group_2_t, uint32_t, uint64_t)>(
+              cuda::ptx::tcgen05_cp_128x256b_b8x16_b4x16_p64));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // tcgen05.cp.cta_group::1.128x256b.b8x16.b4x16_p64 [taddr], s_desc;
+        * fn_ptr++ = reinterpret_cast<void*>(static_cast<void (*)(cuda::ptx::cta_group_1_t, uint32_t, uint64_t)>(
+          cuda::ptx::tcgen05_cp_128x256b_b8x16_b4x16_p64));
+          // tcgen05.cp.cta_group::2.128x256b.b8x16.b4x16_p64 [taddr], s_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(static_cast<void (*)(cuda::ptx::cta_group_2_t, uint32_t, uint64_t)>(
+              cuda::ptx::tcgen05_cp_128x256b_b8x16_b4x16_p64));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tcgen05.cp.cta_group::1.4x256b.b8x16.b4x16_p64 [taddr], s_desc;
+        * fn_ptr++ = reinterpret_cast<void*>(static_cast<void (*)(cuda::ptx::cta_group_1_t, uint32_t, uint64_t)>(
+          cuda::ptx::tcgen05_cp_4x256b_b8x16_b4x16_p64));
+          // tcgen05.cp.cta_group::2.4x256b.b8x16.b4x16_p64 [taddr], s_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(static_cast<void (*)(cuda::ptx::cta_group_2_t, uint32_t, uint64_t)>(
+              cuda::ptx::tcgen05_cp_4x256b_b8x16_b4x16_p64));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // tcgen05.cp.cta_group::1.4x256b.b8x16.b4x16_p64 [taddr], s_desc;
+        * fn_ptr++ = reinterpret_cast<void*>(static_cast<void (*)(cuda::ptx::cta_group_1_t, uint32_t, uint64_t)>(
+          cuda::ptx::tcgen05_cp_4x256b_b8x16_b4x16_p64));
+          // tcgen05.cp.cta_group::2.4x256b.b8x16.b4x16_p64 [taddr], s_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(static_cast<void (*)(cuda::ptx::cta_group_2_t, uint32_t, uint64_t)>(
+              cuda::ptx::tcgen05_cp_4x256b_b8x16_b4x16_p64));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tcgen05.cp.cta_group::1.128x128b.b8x16.b4x16_p64 [taddr], s_desc;
+        * fn_ptr++ = reinterpret_cast<void*>(static_cast<void (*)(cuda::ptx::cta_group_1_t, uint32_t, uint64_t)>(
+          cuda::ptx::tcgen05_cp_128x128b_b8x16_b4x16_p64));
+          // tcgen05.cp.cta_group::2.128x128b.b8x16.b4x16_p64 [taddr], s_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(static_cast<void (*)(cuda::ptx::cta_group_2_t, uint32_t, uint64_t)>(
+              cuda::ptx::tcgen05_cp_128x128b_b8x16_b4x16_p64));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // tcgen05.cp.cta_group::1.128x128b.b8x16.b4x16_p64 [taddr], s_desc;
+        * fn_ptr++ = reinterpret_cast<void*>(static_cast<void (*)(cuda::ptx::cta_group_1_t, uint32_t, uint64_t)>(
+          cuda::ptx::tcgen05_cp_128x128b_b8x16_b4x16_p64));
+          // tcgen05.cp.cta_group::2.128x128b.b8x16.b4x16_p64 [taddr], s_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(static_cast<void (*)(cuda::ptx::cta_group_2_t, uint32_t, uint64_t)>(
+              cuda::ptx::tcgen05_cp_128x128b_b8x16_b4x16_p64));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tcgen05.cp.cta_group::1.64x128b.warpx2::02_13.b8x16.b4x16_p64 [taddr], s_desc;
+        * fn_ptr++ = reinterpret_cast<void*>(static_cast<void (*)(cuda::ptx::cta_group_1_t, uint32_t, uint64_t)>(
+          cuda::ptx::tcgen05_cp_64x128b_warpx2_02_13_b8x16_b4x16_p64));
+          // tcgen05.cp.cta_group::2.64x128b.warpx2::02_13.b8x16.b4x16_p64 [taddr], s_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(static_cast<void (*)(cuda::ptx::cta_group_2_t, uint32_t, uint64_t)>(
+              cuda::ptx::tcgen05_cp_64x128b_warpx2_02_13_b8x16_b4x16_p64));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // tcgen05.cp.cta_group::1.64x128b.warpx2::02_13.b8x16.b4x16_p64 [taddr], s_desc;
+        * fn_ptr++ = reinterpret_cast<void*>(static_cast<void (*)(cuda::ptx::cta_group_1_t, uint32_t, uint64_t)>(
+          cuda::ptx::tcgen05_cp_64x128b_warpx2_02_13_b8x16_b4x16_p64));
+          // tcgen05.cp.cta_group::2.64x128b.warpx2::02_13.b8x16.b4x16_p64 [taddr], s_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(static_cast<void (*)(cuda::ptx::cta_group_2_t, uint32_t, uint64_t)>(
+              cuda::ptx::tcgen05_cp_64x128b_warpx2_02_13_b8x16_b4x16_p64));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tcgen05.cp.cta_group::1.64x128b.warpx2::01_23.b8x16.b4x16_p64 [taddr], s_desc;
+        * fn_ptr++ = reinterpret_cast<void*>(static_cast<void (*)(cuda::ptx::cta_group_1_t, uint32_t, uint64_t)>(
+          cuda::ptx::tcgen05_cp_64x128b_warpx2_01_23_b8x16_b4x16_p64));
+          // tcgen05.cp.cta_group::2.64x128b.warpx2::01_23.b8x16.b4x16_p64 [taddr], s_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(static_cast<void (*)(cuda::ptx::cta_group_2_t, uint32_t, uint64_t)>(
+              cuda::ptx::tcgen05_cp_64x128b_warpx2_01_23_b8x16_b4x16_p64));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // tcgen05.cp.cta_group::1.64x128b.warpx2::01_23.b8x16.b4x16_p64 [taddr], s_desc;
+        * fn_ptr++ = reinterpret_cast<void*>(static_cast<void (*)(cuda::ptx::cta_group_1_t, uint32_t, uint64_t)>(
+          cuda::ptx::tcgen05_cp_64x128b_warpx2_01_23_b8x16_b4x16_p64));
+          // tcgen05.cp.cta_group::2.64x128b.warpx2::01_23.b8x16.b4x16_p64 [taddr], s_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(static_cast<void (*)(cuda::ptx::cta_group_2_t, uint32_t, uint64_t)>(
+              cuda::ptx::tcgen05_cp_64x128b_warpx2_01_23_b8x16_b4x16_p64));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tcgen05.cp.cta_group::1.32x128b.warpx4.b8x16.b4x16_p64 [taddr], s_desc;
+        * fn_ptr++ = reinterpret_cast<void*>(static_cast<void (*)(cuda::ptx::cta_group_1_t, uint32_t, uint64_t)>(
+          cuda::ptx::tcgen05_cp_32x128b_warpx4_b8x16_b4x16_p64));
+          // tcgen05.cp.cta_group::2.32x128b.warpx4.b8x16.b4x16_p64 [taddr], s_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(static_cast<void (*)(cuda::ptx::cta_group_2_t, uint32_t, uint64_t)>(
+              cuda::ptx::tcgen05_cp_32x128b_warpx4_b8x16_b4x16_p64));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // tcgen05.cp.cta_group::1.32x128b.warpx4.b8x16.b4x16_p64 [taddr], s_desc;
+        * fn_ptr++ = reinterpret_cast<void*>(static_cast<void (*)(cuda::ptx::cta_group_1_t, uint32_t, uint64_t)>(
+          cuda::ptx::tcgen05_cp_32x128b_warpx4_b8x16_b4x16_p64));
+          // tcgen05.cp.cta_group::2.32x128b.warpx4.b8x16.b4x16_p64 [taddr], s_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(static_cast<void (*)(cuda::ptx::cta_group_2_t, uint32_t, uint64_t)>(
+              cuda::ptx::tcgen05_cp_32x128b_warpx4_b8x16_b4x16_p64));));
+#endif // __cccl_ptx_isa >= 860
+}
diff --git a/libcudacxx/test/libcudacxx/cuda/ptx/generated/tcgen05_fence.h b/libcudacxx/test/libcudacxx/cuda/ptx/generated/tcgen05_fence.h
new file mode 100644
index 00000000000..75b2ec35fa5
--- /dev/null
+++ b/libcudacxx/test/libcudacxx/cuda/ptx/generated/tcgen05_fence.h
@@ -0,0 +1,44 @@
+// This file was automatically generated. Do not edit.
+
+// We use a special strategy to force the generation of the PTX. This is mainly
+// a fight against dead-code-elimination in the NVVM layer.
+//
+// The reason we need this strategy is because certain older versions of ptxas
+// segfault when a non-sensical sequence of PTX is generated. So instead, we try
+// to force the instantiation and compilation to PTX of all the overloads of the
+// PTX wrapping functions.
+//
+// We do this by writing a function pointer of each overload to the kernel
+// parameter `fn_ptr`.
+//
+// Because `fn_ptr` is possibly visible outside this translation unit, the
+// compiler must compile all the functions which are stored.
+
+__global__ void test_tcgen05_fence(void** fn_ptr)
+{
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tcgen05.fence::before_thread_sync;
+        * fn_ptr++ = reinterpret_cast<void*>(static_cast<void (*)()>(cuda::ptx::tcgen05_fence_before_thread_sync));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // tcgen05.fence::before_thread_sync;
+        * fn_ptr++ = reinterpret_cast<void*>(static_cast<void (*)()>(cuda::ptx::tcgen05_fence_before_thread_sync));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tcgen05.fence::after_thread_sync;
+        * fn_ptr++ = reinterpret_cast<void*>(static_cast<void (*)()>(cuda::ptx::tcgen05_fence_after_thread_sync));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // tcgen05.fence::after_thread_sync;
+        * fn_ptr++ = reinterpret_cast<void*>(static_cast<void (*)()>(cuda::ptx::tcgen05_fence_after_thread_sync));));
+#endif // __cccl_ptx_isa >= 860
+}
diff --git a/libcudacxx/test/libcudacxx/cuda/ptx/generated/tcgen05_ld.h b/libcudacxx/test/libcudacxx/cuda/ptx/generated/tcgen05_ld.h
new file mode 100644
index 00000000000..48ecce5869e
--- /dev/null
+++ b/libcudacxx/test/libcudacxx/cuda/ptx/generated/tcgen05_ld.h
@@ -0,0 +1,1012 @@
+// This file was automatically generated. Do not edit.
+
+// We use a special strategy to force the generation of the PTX. This is mainly
+// a fight against dead-code-elimination in the NVVM layer.
+//
+// The reason we need this strategy is because certain older versions of ptxas
+// segfault when a non-sensical sequence of PTX is generated. So instead, we try
+// to force the instantiation and compilation to PTX of all the overloads of the
+// PTX wrapping functions.
+//
+// We do this by writing a function pointer of each overload to the kernel
+// parameter `fn_ptr`.
+//
+// Because `fn_ptr` is possibly visible outside this translation unit, the
+// compiler must compile all the functions which are stored.
+
+__global__ void test_tcgen05_ld(void** fn_ptr)
+{
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_100a,
+               (
+                   // tcgen05.ld.sync.aligned.16x64b.x1.b32 out, [taddr];
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(int32_t(&out)[1], uint32_t)>(cuda::ptx::tcgen05_ld_16x64b));));
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_101a,
+               (
+                   // tcgen05.ld.sync.aligned.16x64b.x1.b32 out, [taddr];
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(int32_t(&out)[1], uint32_t)>(cuda::ptx::tcgen05_ld_16x64b));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_100a,
+               (
+                   // tcgen05.ld.sync.aligned.16x64b.x1.pack::16b.b32 out, [taddr];
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(int32_t(&out)[1], uint32_t)>(cuda::ptx::tcgen05_ld_16x64b_pack_16b));));
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_101a,
+               (
+                   // tcgen05.ld.sync.aligned.16x64b.x1.pack::16b.b32 out, [taddr];
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(int32_t(&out)[1], uint32_t)>(cuda::ptx::tcgen05_ld_16x64b_pack_16b));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_100a,
+               (
+                   // tcgen05.ld.sync.aligned.16x64b.x2.b32 out, [taddr];
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(int32_t(&out)[2], uint32_t)>(cuda::ptx::tcgen05_ld_16x64b));));
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_101a,
+               (
+                   // tcgen05.ld.sync.aligned.16x64b.x2.b32 out, [taddr];
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(int32_t(&out)[2], uint32_t)>(cuda::ptx::tcgen05_ld_16x64b));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_100a,
+               (
+                   // tcgen05.ld.sync.aligned.16x64b.x2.pack::16b.b32 out, [taddr];
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(int32_t(&out)[2], uint32_t)>(cuda::ptx::tcgen05_ld_16x64b_pack_16b));));
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_101a,
+               (
+                   // tcgen05.ld.sync.aligned.16x64b.x2.pack::16b.b32 out, [taddr];
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(int32_t(&out)[2], uint32_t)>(cuda::ptx::tcgen05_ld_16x64b_pack_16b));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_100a,
+               (
+                   // tcgen05.ld.sync.aligned.16x64b.x4.b32 out, [taddr];
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(int32_t(&out)[4], uint32_t)>(cuda::ptx::tcgen05_ld_16x64b));));
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_101a,
+               (
+                   // tcgen05.ld.sync.aligned.16x64b.x4.b32 out, [taddr];
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(int32_t(&out)[4], uint32_t)>(cuda::ptx::tcgen05_ld_16x64b));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_100a,
+               (
+                   // tcgen05.ld.sync.aligned.16x64b.x4.pack::16b.b32 out, [taddr];
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(int32_t(&out)[4], uint32_t)>(cuda::ptx::tcgen05_ld_16x64b_pack_16b));));
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_101a,
+               (
+                   // tcgen05.ld.sync.aligned.16x64b.x4.pack::16b.b32 out, [taddr];
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(int32_t(&out)[4], uint32_t)>(cuda::ptx::tcgen05_ld_16x64b_pack_16b));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_100a,
+               (
+                   // tcgen05.ld.sync.aligned.16x64b.x8.b32 out, [taddr];
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(int32_t(&out)[8], uint32_t)>(cuda::ptx::tcgen05_ld_16x64b));));
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_101a,
+               (
+                   // tcgen05.ld.sync.aligned.16x64b.x8.b32 out, [taddr];
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(int32_t(&out)[8], uint32_t)>(cuda::ptx::tcgen05_ld_16x64b));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_100a,
+               (
+                   // tcgen05.ld.sync.aligned.16x64b.x8.pack::16b.b32 out, [taddr];
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(int32_t(&out)[8], uint32_t)>(cuda::ptx::tcgen05_ld_16x64b_pack_16b));));
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_101a,
+               (
+                   // tcgen05.ld.sync.aligned.16x64b.x8.pack::16b.b32 out, [taddr];
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(int32_t(&out)[8], uint32_t)>(cuda::ptx::tcgen05_ld_16x64b_pack_16b));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_100a,
+               (
+                   // tcgen05.ld.sync.aligned.16x64b.x16.b32 out, [taddr];
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(int32_t(&out)[16], uint32_t)>(cuda::ptx::tcgen05_ld_16x64b));));
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_101a,
+               (
+                   // tcgen05.ld.sync.aligned.16x64b.x16.b32 out, [taddr];
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(int32_t(&out)[16], uint32_t)>(cuda::ptx::tcgen05_ld_16x64b));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_100a,
+               (
+                   // tcgen05.ld.sync.aligned.16x64b.x16.pack::16b.b32 out, [taddr];
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(int32_t(&out)[16], uint32_t)>(cuda::ptx::tcgen05_ld_16x64b_pack_16b));));
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_101a,
+               (
+                   // tcgen05.ld.sync.aligned.16x64b.x16.pack::16b.b32 out, [taddr];
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(int32_t(&out)[16], uint32_t)>(cuda::ptx::tcgen05_ld_16x64b_pack_16b));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_100a,
+               (
+                   // tcgen05.ld.sync.aligned.16x64b.x32.b32 out, [taddr];
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(int32_t(&out)[32], uint32_t)>(cuda::ptx::tcgen05_ld_16x64b));));
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_101a,
+               (
+                   // tcgen05.ld.sync.aligned.16x64b.x32.b32 out, [taddr];
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(int32_t(&out)[32], uint32_t)>(cuda::ptx::tcgen05_ld_16x64b));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_100a,
+               (
+                   // tcgen05.ld.sync.aligned.16x64b.x32.pack::16b.b32 out, [taddr];
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(int32_t(&out)[32], uint32_t)>(cuda::ptx::tcgen05_ld_16x64b_pack_16b));));
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_101a,
+               (
+                   // tcgen05.ld.sync.aligned.16x64b.x32.pack::16b.b32 out, [taddr];
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(int32_t(&out)[32], uint32_t)>(cuda::ptx::tcgen05_ld_16x64b_pack_16b));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_100a,
+               (
+                   // tcgen05.ld.sync.aligned.16x64b.x64.b32 out, [taddr];
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(int32_t(&out)[64], uint32_t)>(cuda::ptx::tcgen05_ld_16x64b));));
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_101a,
+               (
+                   // tcgen05.ld.sync.aligned.16x64b.x64.b32 out, [taddr];
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(int32_t(&out)[64], uint32_t)>(cuda::ptx::tcgen05_ld_16x64b));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_100a,
+               (
+                   // tcgen05.ld.sync.aligned.16x64b.x64.pack::16b.b32 out, [taddr];
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(int32_t(&out)[64], uint32_t)>(cuda::ptx::tcgen05_ld_16x64b_pack_16b));));
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_101a,
+               (
+                   // tcgen05.ld.sync.aligned.16x64b.x64.pack::16b.b32 out, [taddr];
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(int32_t(&out)[64], uint32_t)>(cuda::ptx::tcgen05_ld_16x64b_pack_16b));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_100a,
+               (
+                   // tcgen05.ld.sync.aligned.16x64b.x128.b32 out, [taddr];
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(int32_t(&out)[128], uint32_t)>(cuda::ptx::tcgen05_ld_16x64b));));
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_101a,
+               (
+                   // tcgen05.ld.sync.aligned.16x64b.x128.b32 out, [taddr];
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(int32_t(&out)[128], uint32_t)>(cuda::ptx::tcgen05_ld_16x64b));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_100a,
+               (
+                   // tcgen05.ld.sync.aligned.16x64b.x128.pack::16b.b32 out, [taddr];
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(int32_t(&out)[128], uint32_t)>(cuda::ptx::tcgen05_ld_16x64b_pack_16b));));
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_101a,
+               (
+                   // tcgen05.ld.sync.aligned.16x64b.x128.pack::16b.b32 out, [taddr];
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(int32_t(&out)[128], uint32_t)>(cuda::ptx::tcgen05_ld_16x64b_pack_16b));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_100a,
+               (
+                   // tcgen05.ld.sync.aligned.16x128b.x1.b32 out, [taddr];
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(int32_t(&out)[2], uint32_t)>(cuda::ptx::tcgen05_ld_16x128b));));
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_101a,
+               (
+                   // tcgen05.ld.sync.aligned.16x128b.x1.b32 out, [taddr];
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(int32_t(&out)[2], uint32_t)>(cuda::ptx::tcgen05_ld_16x128b));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_100a,
+               (
+                   // tcgen05.ld.sync.aligned.16x128b.x1.pack::16b.b32 out, [taddr];
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(int32_t(&out)[2], uint32_t)>(cuda::ptx::tcgen05_ld_16x128b_pack_16b));));
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_101a,
+               (
+                   // tcgen05.ld.sync.aligned.16x128b.x1.pack::16b.b32 out, [taddr];
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(int32_t(&out)[2], uint32_t)>(cuda::ptx::tcgen05_ld_16x128b_pack_16b));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_100a,
+               (
+                   // tcgen05.ld.sync.aligned.16x128b.x2.b32 out, [taddr];
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(int32_t(&out)[4], uint32_t)>(cuda::ptx::tcgen05_ld_16x128b));));
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_101a,
+               (
+                   // tcgen05.ld.sync.aligned.16x128b.x2.b32 out, [taddr];
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(int32_t(&out)[4], uint32_t)>(cuda::ptx::tcgen05_ld_16x128b));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_100a,
+               (
+                   // tcgen05.ld.sync.aligned.16x128b.x2.pack::16b.b32 out, [taddr];
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(int32_t(&out)[4], uint32_t)>(cuda::ptx::tcgen05_ld_16x128b_pack_16b));));
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_101a,
+               (
+                   // tcgen05.ld.sync.aligned.16x128b.x2.pack::16b.b32 out, [taddr];
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(int32_t(&out)[4], uint32_t)>(cuda::ptx::tcgen05_ld_16x128b_pack_16b));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_100a,
+               (
+                   // tcgen05.ld.sync.aligned.16x128b.x4.b32 out, [taddr];
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(int32_t(&out)[8], uint32_t)>(cuda::ptx::tcgen05_ld_16x128b));));
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_101a,
+               (
+                   // tcgen05.ld.sync.aligned.16x128b.x4.b32 out, [taddr];
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(int32_t(&out)[8], uint32_t)>(cuda::ptx::tcgen05_ld_16x128b));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_100a,
+               (
+                   // tcgen05.ld.sync.aligned.16x128b.x4.pack::16b.b32 out, [taddr];
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(int32_t(&out)[8], uint32_t)>(cuda::ptx::tcgen05_ld_16x128b_pack_16b));));
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_101a,
+               (
+                   // tcgen05.ld.sync.aligned.16x128b.x4.pack::16b.b32 out, [taddr];
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(int32_t(&out)[8], uint32_t)>(cuda::ptx::tcgen05_ld_16x128b_pack_16b));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_100a,
+               (
+                   // tcgen05.ld.sync.aligned.16x128b.x8.b32 out, [taddr];
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(int32_t(&out)[16], uint32_t)>(cuda::ptx::tcgen05_ld_16x128b));));
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_101a,
+               (
+                   // tcgen05.ld.sync.aligned.16x128b.x8.b32 out, [taddr];
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(int32_t(&out)[16], uint32_t)>(cuda::ptx::tcgen05_ld_16x128b));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_100a,
+               (
+                   // tcgen05.ld.sync.aligned.16x128b.x8.pack::16b.b32 out, [taddr];
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(int32_t(&out)[16], uint32_t)>(cuda::ptx::tcgen05_ld_16x128b_pack_16b));));
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_101a,
+               (
+                   // tcgen05.ld.sync.aligned.16x128b.x8.pack::16b.b32 out, [taddr];
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(int32_t(&out)[16], uint32_t)>(cuda::ptx::tcgen05_ld_16x128b_pack_16b));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_100a,
+               (
+                   // tcgen05.ld.sync.aligned.16x128b.x16.b32 out, [taddr];
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(int32_t(&out)[32], uint32_t)>(cuda::ptx::tcgen05_ld_16x128b));));
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_101a,
+               (
+                   // tcgen05.ld.sync.aligned.16x128b.x16.b32 out, [taddr];
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(int32_t(&out)[32], uint32_t)>(cuda::ptx::tcgen05_ld_16x128b));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_100a,
+               (
+                   // tcgen05.ld.sync.aligned.16x128b.x16.pack::16b.b32 out, [taddr];
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(int32_t(&out)[32], uint32_t)>(cuda::ptx::tcgen05_ld_16x128b_pack_16b));));
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_101a,
+               (
+                   // tcgen05.ld.sync.aligned.16x128b.x16.pack::16b.b32 out, [taddr];
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(int32_t(&out)[32], uint32_t)>(cuda::ptx::tcgen05_ld_16x128b_pack_16b));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_100a,
+               (
+                   // tcgen05.ld.sync.aligned.16x128b.x32.b32 out, [taddr];
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(int32_t(&out)[64], uint32_t)>(cuda::ptx::tcgen05_ld_16x128b));));
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_101a,
+               (
+                   // tcgen05.ld.sync.aligned.16x128b.x32.b32 out, [taddr];
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(int32_t(&out)[64], uint32_t)>(cuda::ptx::tcgen05_ld_16x128b));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_100a,
+               (
+                   // tcgen05.ld.sync.aligned.16x128b.x32.pack::16b.b32 out, [taddr];
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(int32_t(&out)[64], uint32_t)>(cuda::ptx::tcgen05_ld_16x128b_pack_16b));));
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_101a,
+               (
+                   // tcgen05.ld.sync.aligned.16x128b.x32.pack::16b.b32 out, [taddr];
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(int32_t(&out)[64], uint32_t)>(cuda::ptx::tcgen05_ld_16x128b_pack_16b));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_100a,
+               (
+                   // tcgen05.ld.sync.aligned.16x128b.x64.b32 out, [taddr];
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(int32_t(&out)[128], uint32_t)>(cuda::ptx::tcgen05_ld_16x128b));));
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_101a,
+               (
+                   // tcgen05.ld.sync.aligned.16x128b.x64.b32 out, [taddr];
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(int32_t(&out)[128], uint32_t)>(cuda::ptx::tcgen05_ld_16x128b));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_100a,
+               (
+                   // tcgen05.ld.sync.aligned.16x128b.x64.pack::16b.b32 out, [taddr];
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(int32_t(&out)[128], uint32_t)>(cuda::ptx::tcgen05_ld_16x128b_pack_16b));));
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_101a,
+               (
+                   // tcgen05.ld.sync.aligned.16x128b.x64.pack::16b.b32 out, [taddr];
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(int32_t(&out)[128], uint32_t)>(cuda::ptx::tcgen05_ld_16x128b_pack_16b));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_100a,
+               (
+                   // tcgen05.ld.sync.aligned.16x256b.x1.b32 out, [taddr];
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(int32_t(&out)[4], uint32_t)>(cuda::ptx::tcgen05_ld_16x256b));));
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_101a,
+               (
+                   // tcgen05.ld.sync.aligned.16x256b.x1.b32 out, [taddr];
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(int32_t(&out)[4], uint32_t)>(cuda::ptx::tcgen05_ld_16x256b));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_100a,
+               (
+                   // tcgen05.ld.sync.aligned.16x256b.x1.pack::16b.b32 out, [taddr];
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(int32_t(&out)[4], uint32_t)>(cuda::ptx::tcgen05_ld_16x256b_pack_16b));));
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_101a,
+               (
+                   // tcgen05.ld.sync.aligned.16x256b.x1.pack::16b.b32 out, [taddr];
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(int32_t(&out)[4], uint32_t)>(cuda::ptx::tcgen05_ld_16x256b_pack_16b));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_100a,
+               (
+                   // tcgen05.ld.sync.aligned.16x256b.x2.b32 out, [taddr];
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(int32_t(&out)[8], uint32_t)>(cuda::ptx::tcgen05_ld_16x256b));));
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_101a,
+               (
+                   // tcgen05.ld.sync.aligned.16x256b.x2.b32 out, [taddr];
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(int32_t(&out)[8], uint32_t)>(cuda::ptx::tcgen05_ld_16x256b));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_100a,
+               (
+                   // tcgen05.ld.sync.aligned.16x256b.x2.pack::16b.b32 out, [taddr];
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(int32_t(&out)[8], uint32_t)>(cuda::ptx::tcgen05_ld_16x256b_pack_16b));));
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_101a,
+               (
+                   // tcgen05.ld.sync.aligned.16x256b.x2.pack::16b.b32 out, [taddr];
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(int32_t(&out)[8], uint32_t)>(cuda::ptx::tcgen05_ld_16x256b_pack_16b));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_100a,
+               (
+                   // tcgen05.ld.sync.aligned.16x256b.x4.b32 out, [taddr];
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(int32_t(&out)[16], uint32_t)>(cuda::ptx::tcgen05_ld_16x256b));));
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_101a,
+               (
+                   // tcgen05.ld.sync.aligned.16x256b.x4.b32 out, [taddr];
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(int32_t(&out)[16], uint32_t)>(cuda::ptx::tcgen05_ld_16x256b));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_100a,
+               (
+                   // tcgen05.ld.sync.aligned.16x256b.x4.pack::16b.b32 out, [taddr];
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(int32_t(&out)[16], uint32_t)>(cuda::ptx::tcgen05_ld_16x256b_pack_16b));));
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_101a,
+               (
+                   // tcgen05.ld.sync.aligned.16x256b.x4.pack::16b.b32 out, [taddr];
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(int32_t(&out)[16], uint32_t)>(cuda::ptx::tcgen05_ld_16x256b_pack_16b));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_100a,
+               (
+                   // tcgen05.ld.sync.aligned.16x256b.x8.b32 out, [taddr];
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(int32_t(&out)[32], uint32_t)>(cuda::ptx::tcgen05_ld_16x256b));));
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_101a,
+               (
+                   // tcgen05.ld.sync.aligned.16x256b.x8.b32 out, [taddr];
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(int32_t(&out)[32], uint32_t)>(cuda::ptx::tcgen05_ld_16x256b));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_100a,
+               (
+                   // tcgen05.ld.sync.aligned.16x256b.x8.pack::16b.b32 out, [taddr];
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(int32_t(&out)[32], uint32_t)>(cuda::ptx::tcgen05_ld_16x256b_pack_16b));));
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_101a,
+               (
+                   // tcgen05.ld.sync.aligned.16x256b.x8.pack::16b.b32 out, [taddr];
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(int32_t(&out)[32], uint32_t)>(cuda::ptx::tcgen05_ld_16x256b_pack_16b));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_100a,
+               (
+                   // tcgen05.ld.sync.aligned.16x256b.x16.b32 out, [taddr];
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(int32_t(&out)[64], uint32_t)>(cuda::ptx::tcgen05_ld_16x256b));));
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_101a,
+               (
+                   // tcgen05.ld.sync.aligned.16x256b.x16.b32 out, [taddr];
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(int32_t(&out)[64], uint32_t)>(cuda::ptx::tcgen05_ld_16x256b));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_100a,
+               (
+                   // tcgen05.ld.sync.aligned.16x256b.x16.pack::16b.b32 out, [taddr];
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(int32_t(&out)[64], uint32_t)>(cuda::ptx::tcgen05_ld_16x256b_pack_16b));));
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_101a,
+               (
+                   // tcgen05.ld.sync.aligned.16x256b.x16.pack::16b.b32 out, [taddr];
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(int32_t(&out)[64], uint32_t)>(cuda::ptx::tcgen05_ld_16x256b_pack_16b));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_100a,
+               (
+                   // tcgen05.ld.sync.aligned.16x256b.x32.b32 out, [taddr];
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(int32_t(&out)[128], uint32_t)>(cuda::ptx::tcgen05_ld_16x256b));));
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_101a,
+               (
+                   // tcgen05.ld.sync.aligned.16x256b.x32.b32 out, [taddr];
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(int32_t(&out)[128], uint32_t)>(cuda::ptx::tcgen05_ld_16x256b));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_100a,
+               (
+                   // tcgen05.ld.sync.aligned.16x256b.x32.pack::16b.b32 out, [taddr];
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(int32_t(&out)[128], uint32_t)>(cuda::ptx::tcgen05_ld_16x256b_pack_16b));));
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_101a,
+               (
+                   // tcgen05.ld.sync.aligned.16x256b.x32.pack::16b.b32 out, [taddr];
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(int32_t(&out)[128], uint32_t)>(cuda::ptx::tcgen05_ld_16x256b_pack_16b));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_100a,
+               (
+                   // tcgen05.ld.sync.aligned.32x32b.x1.b32 out, [taddr];
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(int32_t(&out)[1], uint32_t)>(cuda::ptx::tcgen05_ld_32x32b));));
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_101a,
+               (
+                   // tcgen05.ld.sync.aligned.32x32b.x1.b32 out, [taddr];
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(int32_t(&out)[1], uint32_t)>(cuda::ptx::tcgen05_ld_32x32b));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_100a,
+               (
+                   // tcgen05.ld.sync.aligned.32x32b.x1.pack::16b.b32 out, [taddr];
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(int32_t(&out)[1], uint32_t)>(cuda::ptx::tcgen05_ld_32x32b_pack_16b));));
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_101a,
+               (
+                   // tcgen05.ld.sync.aligned.32x32b.x1.pack::16b.b32 out, [taddr];
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(int32_t(&out)[1], uint32_t)>(cuda::ptx::tcgen05_ld_32x32b_pack_16b));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_100a,
+               (
+                   // tcgen05.ld.sync.aligned.32x32b.x2.b32 out, [taddr];
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(int32_t(&out)[2], uint32_t)>(cuda::ptx::tcgen05_ld_32x32b));));
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_101a,
+               (
+                   // tcgen05.ld.sync.aligned.32x32b.x2.b32 out, [taddr];
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(int32_t(&out)[2], uint32_t)>(cuda::ptx::tcgen05_ld_32x32b));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_100a,
+               (
+                   // tcgen05.ld.sync.aligned.32x32b.x2.pack::16b.b32 out, [taddr];
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(int32_t(&out)[2], uint32_t)>(cuda::ptx::tcgen05_ld_32x32b_pack_16b));));
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_101a,
+               (
+                   // tcgen05.ld.sync.aligned.32x32b.x2.pack::16b.b32 out, [taddr];
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(int32_t(&out)[2], uint32_t)>(cuda::ptx::tcgen05_ld_32x32b_pack_16b));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_100a,
+               (
+                   // tcgen05.ld.sync.aligned.32x32b.x4.b32 out, [taddr];
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(int32_t(&out)[4], uint32_t)>(cuda::ptx::tcgen05_ld_32x32b));));
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_101a,
+               (
+                   // tcgen05.ld.sync.aligned.32x32b.x4.b32 out, [taddr];
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(int32_t(&out)[4], uint32_t)>(cuda::ptx::tcgen05_ld_32x32b));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_100a,
+               (
+                   // tcgen05.ld.sync.aligned.32x32b.x4.pack::16b.b32 out, [taddr];
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(int32_t(&out)[4], uint32_t)>(cuda::ptx::tcgen05_ld_32x32b_pack_16b));));
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_101a,
+               (
+                   // tcgen05.ld.sync.aligned.32x32b.x4.pack::16b.b32 out, [taddr];
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(int32_t(&out)[4], uint32_t)>(cuda::ptx::tcgen05_ld_32x32b_pack_16b));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_100a,
+               (
+                   // tcgen05.ld.sync.aligned.32x32b.x8.b32 out, [taddr];
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(int32_t(&out)[8], uint32_t)>(cuda::ptx::tcgen05_ld_32x32b));));
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_101a,
+               (
+                   // tcgen05.ld.sync.aligned.32x32b.x8.b32 out, [taddr];
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(int32_t(&out)[8], uint32_t)>(cuda::ptx::tcgen05_ld_32x32b));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_100a,
+               (
+                   // tcgen05.ld.sync.aligned.32x32b.x8.pack::16b.b32 out, [taddr];
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(int32_t(&out)[8], uint32_t)>(cuda::ptx::tcgen05_ld_32x32b_pack_16b));));
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_101a,
+               (
+                   // tcgen05.ld.sync.aligned.32x32b.x8.pack::16b.b32 out, [taddr];
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(int32_t(&out)[8], uint32_t)>(cuda::ptx::tcgen05_ld_32x32b_pack_16b));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_100a,
+               (
+                   // tcgen05.ld.sync.aligned.32x32b.x16.b32 out, [taddr];
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(int32_t(&out)[16], uint32_t)>(cuda::ptx::tcgen05_ld_32x32b));));
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_101a,
+               (
+                   // tcgen05.ld.sync.aligned.32x32b.x16.b32 out, [taddr];
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(int32_t(&out)[16], uint32_t)>(cuda::ptx::tcgen05_ld_32x32b));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_100a,
+               (
+                   // tcgen05.ld.sync.aligned.32x32b.x16.pack::16b.b32 out, [taddr];
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(int32_t(&out)[16], uint32_t)>(cuda::ptx::tcgen05_ld_32x32b_pack_16b));));
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_101a,
+               (
+                   // tcgen05.ld.sync.aligned.32x32b.x16.pack::16b.b32 out, [taddr];
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(int32_t(&out)[16], uint32_t)>(cuda::ptx::tcgen05_ld_32x32b_pack_16b));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_100a,
+               (
+                   // tcgen05.ld.sync.aligned.32x32b.x32.b32 out, [taddr];
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(int32_t(&out)[32], uint32_t)>(cuda::ptx::tcgen05_ld_32x32b));));
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_101a,
+               (
+                   // tcgen05.ld.sync.aligned.32x32b.x32.b32 out, [taddr];
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(int32_t(&out)[32], uint32_t)>(cuda::ptx::tcgen05_ld_32x32b));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_100a,
+               (
+                   // tcgen05.ld.sync.aligned.32x32b.x32.pack::16b.b32 out, [taddr];
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(int32_t(&out)[32], uint32_t)>(cuda::ptx::tcgen05_ld_32x32b_pack_16b));));
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_101a,
+               (
+                   // tcgen05.ld.sync.aligned.32x32b.x32.pack::16b.b32 out, [taddr];
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(int32_t(&out)[32], uint32_t)>(cuda::ptx::tcgen05_ld_32x32b_pack_16b));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_100a,
+               (
+                   // tcgen05.ld.sync.aligned.32x32b.x64.b32 out, [taddr];
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(int32_t(&out)[64], uint32_t)>(cuda::ptx::tcgen05_ld_32x32b));));
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_101a,
+               (
+                   // tcgen05.ld.sync.aligned.32x32b.x64.b32 out, [taddr];
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(int32_t(&out)[64], uint32_t)>(cuda::ptx::tcgen05_ld_32x32b));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_100a,
+               (
+                   // tcgen05.ld.sync.aligned.32x32b.x64.pack::16b.b32 out, [taddr];
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(int32_t(&out)[64], uint32_t)>(cuda::ptx::tcgen05_ld_32x32b_pack_16b));));
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_101a,
+               (
+                   // tcgen05.ld.sync.aligned.32x32b.x64.pack::16b.b32 out, [taddr];
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(int32_t(&out)[64], uint32_t)>(cuda::ptx::tcgen05_ld_32x32b_pack_16b));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_100a,
+               (
+                   // tcgen05.ld.sync.aligned.32x32b.x128.b32 out, [taddr];
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(int32_t(&out)[128], uint32_t)>(cuda::ptx::tcgen05_ld_32x32b));));
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_101a,
+               (
+                   // tcgen05.ld.sync.aligned.32x32b.x128.b32 out, [taddr];
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(int32_t(&out)[128], uint32_t)>(cuda::ptx::tcgen05_ld_32x32b));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_100a,
+               (
+                   // tcgen05.ld.sync.aligned.32x32b.x128.pack::16b.b32 out, [taddr];
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(int32_t(&out)[128], uint32_t)>(cuda::ptx::tcgen05_ld_32x32b_pack_16b));));
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_101a,
+               (
+                   // tcgen05.ld.sync.aligned.32x32b.x128.pack::16b.b32 out, [taddr];
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(int32_t(&out)[128], uint32_t)>(cuda::ptx::tcgen05_ld_32x32b_pack_16b));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tcgen05.ld.sync.aligned.16x32bx2.x1.b32 out, [taddr], immHalfSplitoff;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(int32_t(&out)[1], uint32_t, cuda::ptx::n32_t<0>)>(cuda::ptx::tcgen05_ld_16x32bx2));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // tcgen05.ld.sync.aligned.16x32bx2.x1.b32 out, [taddr], immHalfSplitoff;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(int32_t(&out)[1], uint32_t, cuda::ptx::n32_t<0>)>(cuda::ptx::tcgen05_ld_16x32bx2));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tcgen05.ld.sync.aligned.16x32bx2.x1.pack::16b.b32 out, [taddr], immHalfSplitoff;
+        * fn_ptr++ = reinterpret_cast<void*>(static_cast<void (*)(int32_t(&out)[1], uint32_t, cuda::ptx::n32_t<0>)>(
+          cuda::ptx::tcgen05_ld_16x32bx2_pack_16b));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // tcgen05.ld.sync.aligned.16x32bx2.x1.pack::16b.b32 out, [taddr], immHalfSplitoff;
+        * fn_ptr++ = reinterpret_cast<void*>(static_cast<void (*)(int32_t(&out)[1], uint32_t, cuda::ptx::n32_t<0>)>(
+          cuda::ptx::tcgen05_ld_16x32bx2_pack_16b));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tcgen05.ld.sync.aligned.16x32bx2.x2.b32 out, [taddr], immHalfSplitoff;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(int32_t(&out)[2], uint32_t, cuda::ptx::n32_t<0>)>(cuda::ptx::tcgen05_ld_16x32bx2));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // tcgen05.ld.sync.aligned.16x32bx2.x2.b32 out, [taddr], immHalfSplitoff;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(int32_t(&out)[2], uint32_t, cuda::ptx::n32_t<0>)>(cuda::ptx::tcgen05_ld_16x32bx2));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tcgen05.ld.sync.aligned.16x32bx2.x2.pack::16b.b32 out, [taddr], immHalfSplitoff;
+        * fn_ptr++ = reinterpret_cast<void*>(static_cast<void (*)(int32_t(&out)[2], uint32_t, cuda::ptx::n32_t<0>)>(
+          cuda::ptx::tcgen05_ld_16x32bx2_pack_16b));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // tcgen05.ld.sync.aligned.16x32bx2.x2.pack::16b.b32 out, [taddr], immHalfSplitoff;
+        * fn_ptr++ = reinterpret_cast<void*>(static_cast<void (*)(int32_t(&out)[2], uint32_t, cuda::ptx::n32_t<0>)>(
+          cuda::ptx::tcgen05_ld_16x32bx2_pack_16b));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tcgen05.ld.sync.aligned.16x32bx2.x4.b32 out, [taddr], immHalfSplitoff;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(int32_t(&out)[4], uint32_t, cuda::ptx::n32_t<0>)>(cuda::ptx::tcgen05_ld_16x32bx2));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // tcgen05.ld.sync.aligned.16x32bx2.x4.b32 out, [taddr], immHalfSplitoff;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(int32_t(&out)[4], uint32_t, cuda::ptx::n32_t<0>)>(cuda::ptx::tcgen05_ld_16x32bx2));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tcgen05.ld.sync.aligned.16x32bx2.x4.pack::16b.b32 out, [taddr], immHalfSplitoff;
+        * fn_ptr++ = reinterpret_cast<void*>(static_cast<void (*)(int32_t(&out)[4], uint32_t, cuda::ptx::n32_t<0>)>(
+          cuda::ptx::tcgen05_ld_16x32bx2_pack_16b));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // tcgen05.ld.sync.aligned.16x32bx2.x4.pack::16b.b32 out, [taddr], immHalfSplitoff;
+        * fn_ptr++ = reinterpret_cast<void*>(static_cast<void (*)(int32_t(&out)[4], uint32_t, cuda::ptx::n32_t<0>)>(
+          cuda::ptx::tcgen05_ld_16x32bx2_pack_16b));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tcgen05.ld.sync.aligned.16x32bx2.x8.b32 out, [taddr], immHalfSplitoff;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(int32_t(&out)[8], uint32_t, cuda::ptx::n32_t<0>)>(cuda::ptx::tcgen05_ld_16x32bx2));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // tcgen05.ld.sync.aligned.16x32bx2.x8.b32 out, [taddr], immHalfSplitoff;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(int32_t(&out)[8], uint32_t, cuda::ptx::n32_t<0>)>(cuda::ptx::tcgen05_ld_16x32bx2));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tcgen05.ld.sync.aligned.16x32bx2.x8.pack::16b.b32 out, [taddr], immHalfSplitoff;
+        * fn_ptr++ = reinterpret_cast<void*>(static_cast<void (*)(int32_t(&out)[8], uint32_t, cuda::ptx::n32_t<0>)>(
+          cuda::ptx::tcgen05_ld_16x32bx2_pack_16b));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // tcgen05.ld.sync.aligned.16x32bx2.x8.pack::16b.b32 out, [taddr], immHalfSplitoff;
+        * fn_ptr++ = reinterpret_cast<void*>(static_cast<void (*)(int32_t(&out)[8], uint32_t, cuda::ptx::n32_t<0>)>(
+          cuda::ptx::tcgen05_ld_16x32bx2_pack_16b));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tcgen05.ld.sync.aligned.16x32bx2.x16.b32 out, [taddr], immHalfSplitoff;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(int32_t(&out)[16], uint32_t, cuda::ptx::n32_t<0>)>(cuda::ptx::tcgen05_ld_16x32bx2));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // tcgen05.ld.sync.aligned.16x32bx2.x16.b32 out, [taddr], immHalfSplitoff;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(int32_t(&out)[16], uint32_t, cuda::ptx::n32_t<0>)>(cuda::ptx::tcgen05_ld_16x32bx2));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tcgen05.ld.sync.aligned.16x32bx2.x16.pack::16b.b32 out, [taddr], immHalfSplitoff;
+        * fn_ptr++ = reinterpret_cast<void*>(static_cast<void (*)(int32_t(&out)[16], uint32_t, cuda::ptx::n32_t<0>)>(
+          cuda::ptx::tcgen05_ld_16x32bx2_pack_16b));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // tcgen05.ld.sync.aligned.16x32bx2.x16.pack::16b.b32 out, [taddr], immHalfSplitoff;
+        * fn_ptr++ = reinterpret_cast<void*>(static_cast<void (*)(int32_t(&out)[16], uint32_t, cuda::ptx::n32_t<0>)>(
+          cuda::ptx::tcgen05_ld_16x32bx2_pack_16b));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tcgen05.ld.sync.aligned.16x32bx2.x32.b32 out, [taddr], immHalfSplitoff;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(int32_t(&out)[32], uint32_t, cuda::ptx::n32_t<0>)>(cuda::ptx::tcgen05_ld_16x32bx2));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // tcgen05.ld.sync.aligned.16x32bx2.x32.b32 out, [taddr], immHalfSplitoff;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(int32_t(&out)[32], uint32_t, cuda::ptx::n32_t<0>)>(cuda::ptx::tcgen05_ld_16x32bx2));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tcgen05.ld.sync.aligned.16x32bx2.x32.pack::16b.b32 out, [taddr], immHalfSplitoff;
+        * fn_ptr++ = reinterpret_cast<void*>(static_cast<void (*)(int32_t(&out)[32], uint32_t, cuda::ptx::n32_t<0>)>(
+          cuda::ptx::tcgen05_ld_16x32bx2_pack_16b));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // tcgen05.ld.sync.aligned.16x32bx2.x32.pack::16b.b32 out, [taddr], immHalfSplitoff;
+        * fn_ptr++ = reinterpret_cast<void*>(static_cast<void (*)(int32_t(&out)[32], uint32_t, cuda::ptx::n32_t<0>)>(
+          cuda::ptx::tcgen05_ld_16x32bx2_pack_16b));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tcgen05.ld.sync.aligned.16x32bx2.x64.b32 out, [taddr], immHalfSplitoff;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(int32_t(&out)[64], uint32_t, cuda::ptx::n32_t<0>)>(cuda::ptx::tcgen05_ld_16x32bx2));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // tcgen05.ld.sync.aligned.16x32bx2.x64.b32 out, [taddr], immHalfSplitoff;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(int32_t(&out)[64], uint32_t, cuda::ptx::n32_t<0>)>(cuda::ptx::tcgen05_ld_16x32bx2));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tcgen05.ld.sync.aligned.16x32bx2.x64.pack::16b.b32 out, [taddr], immHalfSplitoff;
+        * fn_ptr++ = reinterpret_cast<void*>(static_cast<void (*)(int32_t(&out)[64], uint32_t, cuda::ptx::n32_t<0>)>(
+          cuda::ptx::tcgen05_ld_16x32bx2_pack_16b));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // tcgen05.ld.sync.aligned.16x32bx2.x64.pack::16b.b32 out, [taddr], immHalfSplitoff;
+        * fn_ptr++ = reinterpret_cast<void*>(static_cast<void (*)(int32_t(&out)[64], uint32_t, cuda::ptx::n32_t<0>)>(
+          cuda::ptx::tcgen05_ld_16x32bx2_pack_16b));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tcgen05.ld.sync.aligned.16x32bx2.x128.b32 out, [taddr], immHalfSplitoff;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(int32_t(&out)[128], uint32_t, cuda::ptx::n32_t<0>)>(cuda::ptx::tcgen05_ld_16x32bx2));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // tcgen05.ld.sync.aligned.16x32bx2.x128.b32 out, [taddr], immHalfSplitoff;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(int32_t(&out)[128], uint32_t, cuda::ptx::n32_t<0>)>(cuda::ptx::tcgen05_ld_16x32bx2));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tcgen05.ld.sync.aligned.16x32bx2.x128.pack::16b.b32 out, [taddr], immHalfSplitoff;
+        * fn_ptr++ = reinterpret_cast<void*>(static_cast<void (*)(int32_t(&out)[128], uint32_t, cuda::ptx::n32_t<0>)>(
+          cuda::ptx::tcgen05_ld_16x32bx2_pack_16b));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // tcgen05.ld.sync.aligned.16x32bx2.x128.pack::16b.b32 out, [taddr], immHalfSplitoff;
+        * fn_ptr++ = reinterpret_cast<void*>(static_cast<void (*)(int32_t(&out)[128], uint32_t, cuda::ptx::n32_t<0>)>(
+          cuda::ptx::tcgen05_ld_16x32bx2_pack_16b));));
+#endif // __cccl_ptx_isa >= 860
+}
diff --git a/libcudacxx/test/libcudacxx/cuda/ptx/generated/tcgen05_mma.h b/libcudacxx/test/libcudacxx/cuda/ptx/generated/tcgen05_mma.h
new file mode 100644
index 00000000000..7146c395fa7
--- /dev/null
+++ b/libcudacxx/test/libcudacxx/cuda/ptx/generated/tcgen05_mma.h
@@ -0,0 +1,2928 @@
+// This file was automatically generated. Do not edit.
+
+// We use a special strategy to force the generation of the PTX. This is mainly
+// a fight against dead-code-elimination in the NVVM layer.
+//
+// The reason we need this strategy is because certain older versions of ptxas
+// segfault when a non-sensical sequence of PTX is generated. So instead, we try
+// to force the instantiation and compilation to PTX of all the overloads of the
+// PTX wrapping functions.
+//
+// We do this by writing a function pointer of each overload to the kernel
+// parameter `fn_ptr`.
+//
+// Because `fn_ptr` is possibly visible outside this translation unit, the
+// compiler must compile all the functions which are stored.
+
+__global__ void test_tcgen05_mma(void** fn_ptr)
+{
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tcgen05.mma.cta_group::1.kind::f16 [d_tmem], a_desc, b_desc, idesc, disable_output_lane, enable_input_d,
+        // scale_input_d;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(cuda::ptx::kind_f16_t,
+                               cuda::ptx::cta_group_1_t,
+                               uint32_t,
+                               uint64_t,
+                               uint64_t,
+                               uint32_t,
+                               const uint32_t(&)[4],
+                               bool,
+                               cuda::ptx::n32_t<0>)>(cuda::ptx::tcgen05_mma));
+          // tcgen05.mma.cta_group::2.kind::f16 [d_tmem], a_desc, b_desc, idesc, disable_output_lane, enable_input_d,
+          // scale_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::kind_f16_t,
+                                   cuda::ptx::cta_group_2_t,
+                                   uint32_t,
+                                   uint64_t,
+                                   uint64_t,
+                                   uint32_t,
+                                   const uint32_t(&)[4],
+                                   bool,
+                                   cuda::ptx::n32_t<0>)>(cuda::ptx::tcgen05_mma));
+          // tcgen05.mma.cta_group::1.kind::tf32 [d_tmem], a_desc, b_desc, idesc, disable_output_lane, enable_input_d,
+          // scale_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::kind_tf32_t,
+                                   cuda::ptx::cta_group_1_t,
+                                   uint32_t,
+                                   uint64_t,
+                                   uint64_t,
+                                   uint32_t,
+                                   const uint32_t(&)[4],
+                                   bool,
+                                   cuda::ptx::n32_t<0>)>(cuda::ptx::tcgen05_mma));
+          // tcgen05.mma.cta_group::2.kind::tf32 [d_tmem], a_desc, b_desc, idesc, disable_output_lane, enable_input_d,
+          // scale_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::kind_tf32_t,
+                                   cuda::ptx::cta_group_2_t,
+                                   uint32_t,
+                                   uint64_t,
+                                   uint64_t,
+                                   uint32_t,
+                                   const uint32_t(&)[4],
+                                   bool,
+                                   cuda::ptx::n32_t<0>)>(cuda::ptx::tcgen05_mma));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tcgen05.mma.cta_group::1.kind::f16 [d_tmem], a_desc, b_desc, idesc, disable_output_lane, enable_input_d;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(cuda::ptx::kind_f16_t,
+                               cuda::ptx::cta_group_1_t,
+                               uint32_t,
+                               uint64_t,
+                               uint64_t,
+                               uint32_t,
+                               const uint32_t(&)[4],
+                               bool)>(cuda::ptx::tcgen05_mma));
+          // tcgen05.mma.cta_group::2.kind::f16 [d_tmem], a_desc, b_desc, idesc, disable_output_lane, enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::kind_f16_t,
+                                   cuda::ptx::cta_group_2_t,
+                                   uint32_t,
+                                   uint64_t,
+                                   uint64_t,
+                                   uint32_t,
+                                   const uint32_t(&)[4],
+                                   bool)>(cuda::ptx::tcgen05_mma));
+          // tcgen05.mma.cta_group::1.kind::tf32 [d_tmem], a_desc, b_desc, idesc, disable_output_lane, enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::kind_tf32_t,
+                                   cuda::ptx::cta_group_1_t,
+                                   uint32_t,
+                                   uint64_t,
+                                   uint64_t,
+                                   uint32_t,
+                                   const uint32_t(&)[4],
+                                   bool)>(cuda::ptx::tcgen05_mma));
+          // tcgen05.mma.cta_group::2.kind::tf32 [d_tmem], a_desc, b_desc, idesc, disable_output_lane, enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::kind_tf32_t,
+                                   cuda::ptx::cta_group_2_t,
+                                   uint32_t,
+                                   uint64_t,
+                                   uint64_t,
+                                   uint32_t,
+                                   const uint32_t(&)[4],
+                                   bool)>(cuda::ptx::tcgen05_mma));
+          // tcgen05.mma.cta_group::1.kind::f8f6f4 [d_tmem], a_desc, b_desc, idesc, disable_output_lane, enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::kind_f8f6f4_t,
+                                   cuda::ptx::cta_group_1_t,
+                                   uint32_t,
+                                   uint64_t,
+                                   uint64_t,
+                                   uint32_t,
+                                   const uint32_t(&)[4],
+                                   bool)>(cuda::ptx::tcgen05_mma));
+          // tcgen05.mma.cta_group::2.kind::f8f6f4 [d_tmem], a_desc, b_desc, idesc, disable_output_lane, enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::kind_f8f6f4_t,
+                                   cuda::ptx::cta_group_2_t,
+                                   uint32_t,
+                                   uint64_t,
+                                   uint64_t,
+                                   uint32_t,
+                                   const uint32_t(&)[4],
+                                   bool)>(cuda::ptx::tcgen05_mma));
+          // tcgen05.mma.cta_group::1.kind::i8 [d_tmem], a_desc, b_desc, idesc, disable_output_lane, enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::kind_i8_t,
+                                   cuda::ptx::cta_group_1_t,
+                                   uint32_t,
+                                   uint64_t,
+                                   uint64_t,
+                                   uint32_t,
+                                   const uint32_t(&)[4],
+                                   bool)>(cuda::ptx::tcgen05_mma));
+          // tcgen05.mma.cta_group::2.kind::i8 [d_tmem], a_desc, b_desc, idesc, disable_output_lane, enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::kind_i8_t,
+                                   cuda::ptx::cta_group_2_t,
+                                   uint32_t,
+                                   uint64_t,
+                                   uint64_t,
+                                   uint32_t,
+                                   const uint32_t(&)[4],
+                                   bool)>(cuda::ptx::tcgen05_mma));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // tcgen05.mma.cta_group::1.kind::f16 [d_tmem], a_desc, b_desc, idesc, disable_output_lane, enable_input_d;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(cuda::ptx::kind_f16_t,
+                               cuda::ptx::cta_group_1_t,
+                               uint32_t,
+                               uint64_t,
+                               uint64_t,
+                               uint32_t,
+                               const uint32_t(&)[4],
+                               bool)>(cuda::ptx::tcgen05_mma));
+          // tcgen05.mma.cta_group::2.kind::f16 [d_tmem], a_desc, b_desc, idesc, disable_output_lane, enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::kind_f16_t,
+                                   cuda::ptx::cta_group_2_t,
+                                   uint32_t,
+                                   uint64_t,
+                                   uint64_t,
+                                   uint32_t,
+                                   const uint32_t(&)[4],
+                                   bool)>(cuda::ptx::tcgen05_mma));
+          // tcgen05.mma.cta_group::1.kind::tf32 [d_tmem], a_desc, b_desc, idesc, disable_output_lane, enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::kind_tf32_t,
+                                   cuda::ptx::cta_group_1_t,
+                                   uint32_t,
+                                   uint64_t,
+                                   uint64_t,
+                                   uint32_t,
+                                   const uint32_t(&)[4],
+                                   bool)>(cuda::ptx::tcgen05_mma));
+          // tcgen05.mma.cta_group::2.kind::tf32 [d_tmem], a_desc, b_desc, idesc, disable_output_lane, enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::kind_tf32_t,
+                                   cuda::ptx::cta_group_2_t,
+                                   uint32_t,
+                                   uint64_t,
+                                   uint64_t,
+                                   uint32_t,
+                                   const uint32_t(&)[4],
+                                   bool)>(cuda::ptx::tcgen05_mma));
+          // tcgen05.mma.cta_group::1.kind::f8f6f4 [d_tmem], a_desc, b_desc, idesc, disable_output_lane, enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::kind_f8f6f4_t,
+                                   cuda::ptx::cta_group_1_t,
+                                   uint32_t,
+                                   uint64_t,
+                                   uint64_t,
+                                   uint32_t,
+                                   const uint32_t(&)[4],
+                                   bool)>(cuda::ptx::tcgen05_mma));
+          // tcgen05.mma.cta_group::2.kind::f8f6f4 [d_tmem], a_desc, b_desc, idesc, disable_output_lane, enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::kind_f8f6f4_t,
+                                   cuda::ptx::cta_group_2_t,
+                                   uint32_t,
+                                   uint64_t,
+                                   uint64_t,
+                                   uint32_t,
+                                   const uint32_t(&)[4],
+                                   bool)>(cuda::ptx::tcgen05_mma));
+          // tcgen05.mma.cta_group::1.kind::i8 [d_tmem], a_desc, b_desc, idesc, disable_output_lane, enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::kind_i8_t,
+                                   cuda::ptx::cta_group_1_t,
+                                   uint32_t,
+                                   uint64_t,
+                                   uint64_t,
+                                   uint32_t,
+                                   const uint32_t(&)[4],
+                                   bool)>(cuda::ptx::tcgen05_mma));
+          // tcgen05.mma.cta_group::2.kind::i8 [d_tmem], a_desc, b_desc, idesc, disable_output_lane, enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::kind_i8_t,
+                                   cuda::ptx::cta_group_2_t,
+                                   uint32_t,
+                                   uint64_t,
+                                   uint64_t,
+                                   uint32_t,
+                                   const uint32_t(&)[4],
+                                   bool)>(cuda::ptx::tcgen05_mma));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tcgen05.mma.cta_group::1.kind::f16 [d_tmem], a_desc, b_desc, idesc, enable_input_d, scale_input_d;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(cuda::ptx::kind_f16_t,
+                               cuda::ptx::cta_group_1_t,
+                               uint32_t,
+                               uint64_t,
+                               uint64_t,
+                               uint32_t,
+                               bool,
+                               cuda::ptx::n32_t<0>)>(cuda::ptx::tcgen05_mma));
+          // tcgen05.mma.cta_group::2.kind::f16 [d_tmem], a_desc, b_desc, idesc, enable_input_d, scale_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::kind_f16_t,
+                                   cuda::ptx::cta_group_2_t,
+                                   uint32_t,
+                                   uint64_t,
+                                   uint64_t,
+                                   uint32_t,
+                                   bool,
+                                   cuda::ptx::n32_t<0>)>(cuda::ptx::tcgen05_mma));
+          // tcgen05.mma.cta_group::1.kind::tf32 [d_tmem], a_desc, b_desc, idesc, enable_input_d, scale_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::kind_tf32_t,
+                                   cuda::ptx::cta_group_1_t,
+                                   uint32_t,
+                                   uint64_t,
+                                   uint64_t,
+                                   uint32_t,
+                                   bool,
+                                   cuda::ptx::n32_t<0>)>(cuda::ptx::tcgen05_mma));
+          // tcgen05.mma.cta_group::2.kind::tf32 [d_tmem], a_desc, b_desc, idesc, enable_input_d, scale_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::kind_tf32_t,
+                                   cuda::ptx::cta_group_2_t,
+                                   uint32_t,
+                                   uint64_t,
+                                   uint64_t,
+                                   uint32_t,
+                                   bool,
+                                   cuda::ptx::n32_t<0>)>(cuda::ptx::tcgen05_mma));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tcgen05.mma.cta_group::1.kind::f16 [d_tmem], a_desc, b_desc, idesc, enable_input_d;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(
+            cuda::ptx::kind_f16_t, cuda::ptx::cta_group_1_t, uint32_t, uint64_t, uint64_t, uint32_t, bool)>(
+            cuda::ptx::tcgen05_mma));
+          // tcgen05.mma.cta_group::2.kind::f16 [d_tmem], a_desc, b_desc, idesc, enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::kind_f16_t, cuda::ptx::cta_group_2_t, uint32_t, uint64_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma));
+          // tcgen05.mma.cta_group::1.kind::tf32 [d_tmem], a_desc, b_desc, idesc, enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::kind_tf32_t, cuda::ptx::cta_group_1_t, uint32_t, uint64_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma));
+          // tcgen05.mma.cta_group::2.kind::tf32 [d_tmem], a_desc, b_desc, idesc, enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::kind_tf32_t, cuda::ptx::cta_group_2_t, uint32_t, uint64_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma));
+          // tcgen05.mma.cta_group::1.kind::f8f6f4 [d_tmem], a_desc, b_desc, idesc, enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::kind_f8f6f4_t, cuda::ptx::cta_group_1_t, uint32_t, uint64_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma));
+          // tcgen05.mma.cta_group::2.kind::f8f6f4 [d_tmem], a_desc, b_desc, idesc, enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::kind_f8f6f4_t, cuda::ptx::cta_group_2_t, uint32_t, uint64_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma));
+          // tcgen05.mma.cta_group::1.kind::i8 [d_tmem], a_desc, b_desc, idesc, enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::kind_i8_t, cuda::ptx::cta_group_1_t, uint32_t, uint64_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma));
+          // tcgen05.mma.cta_group::2.kind::i8 [d_tmem], a_desc, b_desc, idesc, enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::kind_i8_t, cuda::ptx::cta_group_2_t, uint32_t, uint64_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // tcgen05.mma.cta_group::1.kind::f16 [d_tmem], a_desc, b_desc, idesc, enable_input_d;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(
+            cuda::ptx::kind_f16_t, cuda::ptx::cta_group_1_t, uint32_t, uint64_t, uint64_t, uint32_t, bool)>(
+            cuda::ptx::tcgen05_mma));
+          // tcgen05.mma.cta_group::2.kind::f16 [d_tmem], a_desc, b_desc, idesc, enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::kind_f16_t, cuda::ptx::cta_group_2_t, uint32_t, uint64_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma));
+          // tcgen05.mma.cta_group::1.kind::tf32 [d_tmem], a_desc, b_desc, idesc, enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::kind_tf32_t, cuda::ptx::cta_group_1_t, uint32_t, uint64_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma));
+          // tcgen05.mma.cta_group::2.kind::tf32 [d_tmem], a_desc, b_desc, idesc, enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::kind_tf32_t, cuda::ptx::cta_group_2_t, uint32_t, uint64_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma));
+          // tcgen05.mma.cta_group::1.kind::f8f6f4 [d_tmem], a_desc, b_desc, idesc, enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::kind_f8f6f4_t, cuda::ptx::cta_group_1_t, uint32_t, uint64_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma));
+          // tcgen05.mma.cta_group::2.kind::f8f6f4 [d_tmem], a_desc, b_desc, idesc, enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::kind_f8f6f4_t, cuda::ptx::cta_group_2_t, uint32_t, uint64_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma));
+          // tcgen05.mma.cta_group::1.kind::i8 [d_tmem], a_desc, b_desc, idesc, enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::kind_i8_t, cuda::ptx::cta_group_1_t, uint32_t, uint64_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma));
+          // tcgen05.mma.cta_group::2.kind::i8 [d_tmem], a_desc, b_desc, idesc, enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::kind_i8_t, cuda::ptx::cta_group_2_t, uint32_t, uint64_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tcgen05.mma.cta_group::1.kind::f16 [d_tmem], [a_tmem], b_desc, idesc, disable_output_lane, enable_input_d,
+        // scale_input_d;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(cuda::ptx::kind_f16_t,
+                               cuda::ptx::cta_group_1_t,
+                               uint32_t,
+                               uint32_t,
+                               uint64_t,
+                               uint32_t,
+                               const uint32_t(&)[4],
+                               bool,
+                               cuda::ptx::n32_t<0>)>(cuda::ptx::tcgen05_mma_tmem_a));
+          // tcgen05.mma.cta_group::2.kind::f16 [d_tmem], [a_tmem], b_desc, idesc, disable_output_lane,
+          // enable_input_d, scale_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::kind_f16_t,
+                                   cuda::ptx::cta_group_2_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   uint64_t,
+                                   uint32_t,
+                                   const uint32_t(&)[4],
+                                   bool,
+                                   cuda::ptx::n32_t<0>)>(cuda::ptx::tcgen05_mma_tmem_a));
+          // tcgen05.mma.cta_group::1.kind::tf32 [d_tmem], [a_tmem], b_desc, idesc, disable_output_lane,
+          // enable_input_d, scale_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::kind_tf32_t,
+                                   cuda::ptx::cta_group_1_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   uint64_t,
+                                   uint32_t,
+                                   const uint32_t(&)[4],
+                                   bool,
+                                   cuda::ptx::n32_t<0>)>(cuda::ptx::tcgen05_mma_tmem_a));
+          // tcgen05.mma.cta_group::2.kind::tf32 [d_tmem], [a_tmem], b_desc, idesc, disable_output_lane,
+          // enable_input_d, scale_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::kind_tf32_t,
+                                   cuda::ptx::cta_group_2_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   uint64_t,
+                                   uint32_t,
+                                   const uint32_t(&)[4],
+                                   bool,
+                                   cuda::ptx::n32_t<0>)>(cuda::ptx::tcgen05_mma_tmem_a));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tcgen05.mma.cta_group::1.kind::f16 [d_tmem], [a_tmem], b_desc, idesc, disable_output_lane, enable_input_d;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(cuda::ptx::kind_f16_t,
+                               cuda::ptx::cta_group_1_t,
+                               uint32_t,
+                               uint32_t,
+                               uint64_t,
+                               uint32_t,
+                               const uint32_t(&)[4],
+                               bool)>(cuda::ptx::tcgen05_mma_tmem_a));
+          // tcgen05.mma.cta_group::2.kind::f16 [d_tmem], [a_tmem], b_desc, idesc, disable_output_lane, enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::kind_f16_t,
+                                   cuda::ptx::cta_group_2_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   uint64_t,
+                                   uint32_t,
+                                   const uint32_t(&)[4],
+                                   bool)>(cuda::ptx::tcgen05_mma_tmem_a));
+          // tcgen05.mma.cta_group::1.kind::tf32 [d_tmem], [a_tmem], b_desc, idesc, disable_output_lane, enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::kind_tf32_t,
+                                   cuda::ptx::cta_group_1_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   uint64_t,
+                                   uint32_t,
+                                   const uint32_t(&)[4],
+                                   bool)>(cuda::ptx::tcgen05_mma_tmem_a));
+          // tcgen05.mma.cta_group::2.kind::tf32 [d_tmem], [a_tmem], b_desc, idesc, disable_output_lane, enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::kind_tf32_t,
+                                   cuda::ptx::cta_group_2_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   uint64_t,
+                                   uint32_t,
+                                   const uint32_t(&)[4],
+                                   bool)>(cuda::ptx::tcgen05_mma_tmem_a));
+          // tcgen05.mma.cta_group::1.kind::f8f6f4 [d_tmem], [a_tmem], b_desc, idesc, disable_output_lane,
+          // enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::kind_f8f6f4_t,
+                                   cuda::ptx::cta_group_1_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   uint64_t,
+                                   uint32_t,
+                                   const uint32_t(&)[4],
+                                   bool)>(cuda::ptx::tcgen05_mma_tmem_a));
+          // tcgen05.mma.cta_group::2.kind::f8f6f4 [d_tmem], [a_tmem], b_desc, idesc, disable_output_lane,
+          // enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::kind_f8f6f4_t,
+                                   cuda::ptx::cta_group_2_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   uint64_t,
+                                   uint32_t,
+                                   const uint32_t(&)[4],
+                                   bool)>(cuda::ptx::tcgen05_mma_tmem_a));
+          // tcgen05.mma.cta_group::1.kind::i8 [d_tmem], [a_tmem], b_desc, idesc, disable_output_lane, enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::kind_i8_t,
+                                   cuda::ptx::cta_group_1_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   uint64_t,
+                                   uint32_t,
+                                   const uint32_t(&)[4],
+                                   bool)>(cuda::ptx::tcgen05_mma_tmem_a));
+          // tcgen05.mma.cta_group::2.kind::i8 [d_tmem], [a_tmem], b_desc, idesc, disable_output_lane, enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::kind_i8_t,
+                                   cuda::ptx::cta_group_2_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   uint64_t,
+                                   uint32_t,
+                                   const uint32_t(&)[4],
+                                   bool)>(cuda::ptx::tcgen05_mma_tmem_a));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // tcgen05.mma.cta_group::1.kind::f16 [d_tmem], [a_tmem], b_desc, idesc, disable_output_lane, enable_input_d;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(cuda::ptx::kind_f16_t,
+                               cuda::ptx::cta_group_1_t,
+                               uint32_t,
+                               uint32_t,
+                               uint64_t,
+                               uint32_t,
+                               const uint32_t(&)[4],
+                               bool)>(cuda::ptx::tcgen05_mma_tmem_a));
+          // tcgen05.mma.cta_group::2.kind::f16 [d_tmem], [a_tmem], b_desc, idesc, disable_output_lane, enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::kind_f16_t,
+                                   cuda::ptx::cta_group_2_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   uint64_t,
+                                   uint32_t,
+                                   const uint32_t(&)[4],
+                                   bool)>(cuda::ptx::tcgen05_mma_tmem_a));
+          // tcgen05.mma.cta_group::1.kind::tf32 [d_tmem], [a_tmem], b_desc, idesc, disable_output_lane, enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::kind_tf32_t,
+                                   cuda::ptx::cta_group_1_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   uint64_t,
+                                   uint32_t,
+                                   const uint32_t(&)[4],
+                                   bool)>(cuda::ptx::tcgen05_mma_tmem_a));
+          // tcgen05.mma.cta_group::2.kind::tf32 [d_tmem], [a_tmem], b_desc, idesc, disable_output_lane, enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::kind_tf32_t,
+                                   cuda::ptx::cta_group_2_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   uint64_t,
+                                   uint32_t,
+                                   const uint32_t(&)[4],
+                                   bool)>(cuda::ptx::tcgen05_mma_tmem_a));
+          // tcgen05.mma.cta_group::1.kind::f8f6f4 [d_tmem], [a_tmem], b_desc, idesc, disable_output_lane,
+          // enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::kind_f8f6f4_t,
+                                   cuda::ptx::cta_group_1_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   uint64_t,
+                                   uint32_t,
+                                   const uint32_t(&)[4],
+                                   bool)>(cuda::ptx::tcgen05_mma_tmem_a));
+          // tcgen05.mma.cta_group::2.kind::f8f6f4 [d_tmem], [a_tmem], b_desc, idesc, disable_output_lane,
+          // enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::kind_f8f6f4_t,
+                                   cuda::ptx::cta_group_2_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   uint64_t,
+                                   uint32_t,
+                                   const uint32_t(&)[4],
+                                   bool)>(cuda::ptx::tcgen05_mma_tmem_a));
+          // tcgen05.mma.cta_group::1.kind::i8 [d_tmem], [a_tmem], b_desc, idesc, disable_output_lane, enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::kind_i8_t,
+                                   cuda::ptx::cta_group_1_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   uint64_t,
+                                   uint32_t,
+                                   const uint32_t(&)[4],
+                                   bool)>(cuda::ptx::tcgen05_mma_tmem_a));
+          // tcgen05.mma.cta_group::2.kind::i8 [d_tmem], [a_tmem], b_desc, idesc, disable_output_lane, enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::kind_i8_t,
+                                   cuda::ptx::cta_group_2_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   uint64_t,
+                                   uint32_t,
+                                   const uint32_t(&)[4],
+                                   bool)>(cuda::ptx::tcgen05_mma_tmem_a));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tcgen05.mma.cta_group::1.kind::f16 [d_tmem], [a_tmem], b_desc, idesc, enable_input_d, scale_input_d;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(cuda::ptx::kind_f16_t,
+                               cuda::ptx::cta_group_1_t,
+                               uint32_t,
+                               uint32_t,
+                               uint64_t,
+                               uint32_t,
+                               bool,
+                               cuda::ptx::n32_t<0>)>(cuda::ptx::tcgen05_mma_tmem_a));
+          // tcgen05.mma.cta_group::2.kind::f16 [d_tmem], [a_tmem], b_desc, idesc, enable_input_d, scale_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::kind_f16_t,
+                                   cuda::ptx::cta_group_2_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   uint64_t,
+                                   uint32_t,
+                                   bool,
+                                   cuda::ptx::n32_t<0>)>(cuda::ptx::tcgen05_mma_tmem_a));
+          // tcgen05.mma.cta_group::1.kind::tf32 [d_tmem], [a_tmem], b_desc, idesc, enable_input_d, scale_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::kind_tf32_t,
+                                   cuda::ptx::cta_group_1_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   uint64_t,
+                                   uint32_t,
+                                   bool,
+                                   cuda::ptx::n32_t<0>)>(cuda::ptx::tcgen05_mma_tmem_a));
+          // tcgen05.mma.cta_group::2.kind::tf32 [d_tmem], [a_tmem], b_desc, idesc, enable_input_d, scale_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::kind_tf32_t,
+                                   cuda::ptx::cta_group_2_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   uint64_t,
+                                   uint32_t,
+                                   bool,
+                                   cuda::ptx::n32_t<0>)>(cuda::ptx::tcgen05_mma_tmem_a));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tcgen05.mma.cta_group::1.kind::f16 [d_tmem], [a_tmem], b_desc, idesc, enable_input_d;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(
+            cuda::ptx::kind_f16_t, cuda::ptx::cta_group_1_t, uint32_t, uint32_t, uint64_t, uint32_t, bool)>(
+            cuda::ptx::tcgen05_mma_tmem_a));
+          // tcgen05.mma.cta_group::2.kind::f16 [d_tmem], [a_tmem], b_desc, idesc, enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::kind_f16_t, cuda::ptx::cta_group_2_t, uint32_t, uint32_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_tmem_a));
+          // tcgen05.mma.cta_group::1.kind::tf32 [d_tmem], [a_tmem], b_desc, idesc, enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::kind_tf32_t, cuda::ptx::cta_group_1_t, uint32_t, uint32_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_tmem_a));
+          // tcgen05.mma.cta_group::2.kind::tf32 [d_tmem], [a_tmem], b_desc, idesc, enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::kind_tf32_t, cuda::ptx::cta_group_2_t, uint32_t, uint32_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_tmem_a));
+          // tcgen05.mma.cta_group::1.kind::f8f6f4 [d_tmem], [a_tmem], b_desc, idesc, enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::kind_f8f6f4_t, cuda::ptx::cta_group_1_t, uint32_t, uint32_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_tmem_a));
+          // tcgen05.mma.cta_group::2.kind::f8f6f4 [d_tmem], [a_tmem], b_desc, idesc, enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::kind_f8f6f4_t, cuda::ptx::cta_group_2_t, uint32_t, uint32_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_tmem_a));
+          // tcgen05.mma.cta_group::1.kind::i8 [d_tmem], [a_tmem], b_desc, idesc, enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::kind_i8_t, cuda::ptx::cta_group_1_t, uint32_t, uint32_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_tmem_a));
+          // tcgen05.mma.cta_group::2.kind::i8 [d_tmem], [a_tmem], b_desc, idesc, enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::kind_i8_t, cuda::ptx::cta_group_2_t, uint32_t, uint32_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_tmem_a));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // tcgen05.mma.cta_group::1.kind::f16 [d_tmem], [a_tmem], b_desc, idesc, enable_input_d;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(
+            cuda::ptx::kind_f16_t, cuda::ptx::cta_group_1_t, uint32_t, uint32_t, uint64_t, uint32_t, bool)>(
+            cuda::ptx::tcgen05_mma_tmem_a));
+          // tcgen05.mma.cta_group::2.kind::f16 [d_tmem], [a_tmem], b_desc, idesc, enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::kind_f16_t, cuda::ptx::cta_group_2_t, uint32_t, uint32_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_tmem_a));
+          // tcgen05.mma.cta_group::1.kind::tf32 [d_tmem], [a_tmem], b_desc, idesc, enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::kind_tf32_t, cuda::ptx::cta_group_1_t, uint32_t, uint32_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_tmem_a));
+          // tcgen05.mma.cta_group::2.kind::tf32 [d_tmem], [a_tmem], b_desc, idesc, enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::kind_tf32_t, cuda::ptx::cta_group_2_t, uint32_t, uint32_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_tmem_a));
+          // tcgen05.mma.cta_group::1.kind::f8f6f4 [d_tmem], [a_tmem], b_desc, idesc, enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::kind_f8f6f4_t, cuda::ptx::cta_group_1_t, uint32_t, uint32_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_tmem_a));
+          // tcgen05.mma.cta_group::2.kind::f8f6f4 [d_tmem], [a_tmem], b_desc, idesc, enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::kind_f8f6f4_t, cuda::ptx::cta_group_2_t, uint32_t, uint32_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_tmem_a));
+          // tcgen05.mma.cta_group::1.kind::i8 [d_tmem], [a_tmem], b_desc, idesc, enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::kind_i8_t, cuda::ptx::cta_group_1_t, uint32_t, uint32_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_tmem_a));
+          // tcgen05.mma.cta_group::2.kind::i8 [d_tmem], [a_tmem], b_desc, idesc, enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::kind_i8_t, cuda::ptx::cta_group_2_t, uint32_t, uint32_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_tmem_a));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tcgen05.mma.cta_group::1.kind::mxf8f6f4.block_scale.scale_vec::1X [d_tmem], a_desc, b_desc, idesc,
+        // [scale_A_tmem], [scale_B_tmem], enable_input_d;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(cuda::ptx::kind_mxf8f6f4_t,
+                               cuda::ptx::cta_group_1_t,
+                               uint32_t,
+                               uint64_t,
+                               uint64_t,
+                               uint32_t,
+                               uint32_t,
+                               uint32_t,
+                               bool)>(cuda::ptx::tcgen05_mma_block_scale_vec_1x));
+          // tcgen05.mma.cta_group::2.kind::mxf8f6f4.block_scale.scale_vec::1X [d_tmem], a_desc, b_desc, idesc,
+          // [scale_A_tmem], [scale_B_tmem], enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::kind_mxf8f6f4_t,
+                                   cuda::ptx::cta_group_2_t,
+                                   uint32_t,
+                                   uint64_t,
+                                   uint64_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   bool)>(cuda::ptx::tcgen05_mma_block_scale_vec_1x));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // tcgen05.mma.cta_group::1.kind::mxf8f6f4.block_scale.scale_vec::1X [d_tmem], a_desc, b_desc, idesc,
+        // [scale_A_tmem], [scale_B_tmem], enable_input_d;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(cuda::ptx::kind_mxf8f6f4_t,
+                               cuda::ptx::cta_group_1_t,
+                               uint32_t,
+                               uint64_t,
+                               uint64_t,
+                               uint32_t,
+                               uint32_t,
+                               uint32_t,
+                               bool)>(cuda::ptx::tcgen05_mma_block_scale_vec_1x));
+          // tcgen05.mma.cta_group::2.kind::mxf8f6f4.block_scale.scale_vec::1X [d_tmem], a_desc, b_desc, idesc,
+          // [scale_A_tmem], [scale_B_tmem], enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::kind_mxf8f6f4_t,
+                                   cuda::ptx::cta_group_2_t,
+                                   uint32_t,
+                                   uint64_t,
+                                   uint64_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   bool)>(cuda::ptx::tcgen05_mma_block_scale_vec_1x));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tcgen05.mma.cta_group::1.kind::mxf4.block_scale.scale_vec::2X [d_tmem], a_desc, b_desc, idesc,
+        // [scale_A_tmem], [scale_B_tmem], enable_input_d;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(cuda::ptx::kind_mxf4_t,
+                               cuda::ptx::cta_group_1_t,
+                               uint32_t,
+                               uint64_t,
+                               uint64_t,
+                               uint32_t,
+                               uint32_t,
+                               uint32_t,
+                               bool)>(cuda::ptx::tcgen05_mma_block_scale_vec_2x));
+          // tcgen05.mma.cta_group::2.kind::mxf4.block_scale.scale_vec::2X [d_tmem], a_desc, b_desc, idesc,
+          // [scale_A_tmem], [scale_B_tmem], enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::kind_mxf4_t,
+                                   cuda::ptx::cta_group_2_t,
+                                   uint32_t,
+                                   uint64_t,
+                                   uint64_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   bool)>(cuda::ptx::tcgen05_mma_block_scale_vec_2x));
+          // tcgen05.mma.cta_group::1.kind::mxf4nvf4.block_scale.scale_vec::2X [d_tmem], a_desc, b_desc, idesc,
+          // [scale_A_tmem], [scale_B_tmem], enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::kind_mxf4nvf4_t,
+                                   cuda::ptx::cta_group_1_t,
+                                   uint32_t,
+                                   uint64_t,
+                                   uint64_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   bool)>(cuda::ptx::tcgen05_mma_block_scale_vec_2x));
+          // tcgen05.mma.cta_group::2.kind::mxf4nvf4.block_scale.scale_vec::2X [d_tmem], a_desc, b_desc, idesc,
+          // [scale_A_tmem], [scale_B_tmem], enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::kind_mxf4nvf4_t,
+                                   cuda::ptx::cta_group_2_t,
+                                   uint32_t,
+                                   uint64_t,
+                                   uint64_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   bool)>(cuda::ptx::tcgen05_mma_block_scale_vec_2x));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // tcgen05.mma.cta_group::1.kind::mxf4.block_scale.scale_vec::2X [d_tmem], a_desc, b_desc, idesc,
+        // [scale_A_tmem], [scale_B_tmem], enable_input_d;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(cuda::ptx::kind_mxf4_t,
+                               cuda::ptx::cta_group_1_t,
+                               uint32_t,
+                               uint64_t,
+                               uint64_t,
+                               uint32_t,
+                               uint32_t,
+                               uint32_t,
+                               bool)>(cuda::ptx::tcgen05_mma_block_scale_vec_2x));
+          // tcgen05.mma.cta_group::2.kind::mxf4.block_scale.scale_vec::2X [d_tmem], a_desc, b_desc, idesc,
+          // [scale_A_tmem], [scale_B_tmem], enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::kind_mxf4_t,
+                                   cuda::ptx::cta_group_2_t,
+                                   uint32_t,
+                                   uint64_t,
+                                   uint64_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   bool)>(cuda::ptx::tcgen05_mma_block_scale_vec_2x));
+          // tcgen05.mma.cta_group::1.kind::mxf4nvf4.block_scale.scale_vec::2X [d_tmem], a_desc, b_desc, idesc,
+          // [scale_A_tmem], [scale_B_tmem], enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::kind_mxf4nvf4_t,
+                                   cuda::ptx::cta_group_1_t,
+                                   uint32_t,
+                                   uint64_t,
+                                   uint64_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   bool)>(cuda::ptx::tcgen05_mma_block_scale_vec_2x));
+          // tcgen05.mma.cta_group::2.kind::mxf4nvf4.block_scale.scale_vec::2X [d_tmem], a_desc, b_desc, idesc,
+          // [scale_A_tmem], [scale_B_tmem], enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::kind_mxf4nvf4_t,
+                                   cuda::ptx::cta_group_2_t,
+                                   uint32_t,
+                                   uint64_t,
+                                   uint64_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   bool)>(cuda::ptx::tcgen05_mma_block_scale_vec_2x));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tcgen05.mma.cta_group::1.kind::mxf4nvf4.block_scale.scale_vec::4X [d_tmem], a_desc, b_desc, idesc,
+        // [scale_A_tmem], [scale_B_tmem], enable_input_d;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(cuda::ptx::kind_mxf4nvf4_t,
+                               cuda::ptx::cta_group_1_t,
+                               uint32_t,
+                               uint64_t,
+                               uint64_t,
+                               uint32_t,
+                               uint32_t,
+                               uint32_t,
+                               bool)>(cuda::ptx::tcgen05_mma_block_scale_vec_4x));
+          // tcgen05.mma.cta_group::2.kind::mxf4nvf4.block_scale.scale_vec::4X [d_tmem], a_desc, b_desc, idesc,
+          // [scale_A_tmem], [scale_B_tmem], enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::kind_mxf4nvf4_t,
+                                   cuda::ptx::cta_group_2_t,
+                                   uint32_t,
+                                   uint64_t,
+                                   uint64_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   bool)>(cuda::ptx::tcgen05_mma_block_scale_vec_4x));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // tcgen05.mma.cta_group::1.kind::mxf4nvf4.block_scale.scale_vec::4X [d_tmem], a_desc, b_desc, idesc,
+        // [scale_A_tmem], [scale_B_tmem], enable_input_d;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(cuda::ptx::kind_mxf4nvf4_t,
+                               cuda::ptx::cta_group_1_t,
+                               uint32_t,
+                               uint64_t,
+                               uint64_t,
+                               uint32_t,
+                               uint32_t,
+                               uint32_t,
+                               bool)>(cuda::ptx::tcgen05_mma_block_scale_vec_4x));
+          // tcgen05.mma.cta_group::2.kind::mxf4nvf4.block_scale.scale_vec::4X [d_tmem], a_desc, b_desc, idesc,
+          // [scale_A_tmem], [scale_B_tmem], enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::kind_mxf4nvf4_t,
+                                   cuda::ptx::cta_group_2_t,
+                                   uint32_t,
+                                   uint64_t,
+                                   uint64_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   bool)>(cuda::ptx::tcgen05_mma_block_scale_vec_4x));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tcgen05.mma.cta_group::1.kind::mxf8f6f4.block_scale.scale_vec::1X [d_tmem], a_desc, b_desc, idesc,
+        // [scale_A_tmem], [scale_B_tmem], enable_input_d;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(cuda::ptx::kind_mxf8f6f4_t,
+                               cuda::ptx::cta_group_1_t,
+                               uint32_t,
+                               uint64_t,
+                               uint64_t,
+                               uint32_t,
+                               uint32_t,
+                               uint32_t,
+                               bool)>(cuda::ptx::tcgen05_mma_block_scale_vec_1x_tmem_a));
+          // tcgen05.mma.cta_group::2.kind::mxf8f6f4.block_scale.scale_vec::1X [d_tmem], a_desc, b_desc, idesc,
+          // [scale_A_tmem], [scale_B_tmem], enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::kind_mxf8f6f4_t,
+                                   cuda::ptx::cta_group_2_t,
+                                   uint32_t,
+                                   uint64_t,
+                                   uint64_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   bool)>(cuda::ptx::tcgen05_mma_block_scale_vec_1x_tmem_a));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // tcgen05.mma.cta_group::1.kind::mxf8f6f4.block_scale.scale_vec::1X [d_tmem], a_desc, b_desc, idesc,
+        // [scale_A_tmem], [scale_B_tmem], enable_input_d;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(cuda::ptx::kind_mxf8f6f4_t,
+                               cuda::ptx::cta_group_1_t,
+                               uint32_t,
+                               uint64_t,
+                               uint64_t,
+                               uint32_t,
+                               uint32_t,
+                               uint32_t,
+                               bool)>(cuda::ptx::tcgen05_mma_block_scale_vec_1x_tmem_a));
+          // tcgen05.mma.cta_group::2.kind::mxf8f6f4.block_scale.scale_vec::1X [d_tmem], a_desc, b_desc, idesc,
+          // [scale_A_tmem], [scale_B_tmem], enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::kind_mxf8f6f4_t,
+                                   cuda::ptx::cta_group_2_t,
+                                   uint32_t,
+                                   uint64_t,
+                                   uint64_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   bool)>(cuda::ptx::tcgen05_mma_block_scale_vec_1x_tmem_a));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tcgen05.mma.cta_group::1.kind::mxf4.block_scale.scale_vec::2X [d_tmem], a_desc, b_desc, idesc,
+        // [scale_A_tmem], [scale_B_tmem], enable_input_d;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(cuda::ptx::kind_mxf4_t,
+                               cuda::ptx::cta_group_1_t,
+                               uint32_t,
+                               uint64_t,
+                               uint64_t,
+                               uint32_t,
+                               uint32_t,
+                               uint32_t,
+                               bool)>(cuda::ptx::tcgen05_mma_block_scale_vec_2_tmem_a));
+          // tcgen05.mma.cta_group::2.kind::mxf4.block_scale.scale_vec::2X [d_tmem], a_desc, b_desc, idesc,
+          // [scale_A_tmem], [scale_B_tmem], enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::kind_mxf4_t,
+                                   cuda::ptx::cta_group_2_t,
+                                   uint32_t,
+                                   uint64_t,
+                                   uint64_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   bool)>(cuda::ptx::tcgen05_mma_block_scale_vec_2_tmem_a));
+          // tcgen05.mma.cta_group::1.kind::mxf4nvf4.block_scale.scale_vec::2X [d_tmem], a_desc, b_desc, idesc,
+          // [scale_A_tmem], [scale_B_tmem], enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::kind_mxf4nvf4_t,
+                                   cuda::ptx::cta_group_1_t,
+                                   uint32_t,
+                                   uint64_t,
+                                   uint64_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   bool)>(cuda::ptx::tcgen05_mma_block_scale_vec_2_tmem_a));
+          // tcgen05.mma.cta_group::2.kind::mxf4nvf4.block_scale.scale_vec::2X [d_tmem], a_desc, b_desc, idesc,
+          // [scale_A_tmem], [scale_B_tmem], enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::kind_mxf4nvf4_t,
+                                   cuda::ptx::cta_group_2_t,
+                                   uint32_t,
+                                   uint64_t,
+                                   uint64_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   bool)>(cuda::ptx::tcgen05_mma_block_scale_vec_2_tmem_a));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // tcgen05.mma.cta_group::1.kind::mxf4.block_scale.scale_vec::2X [d_tmem], a_desc, b_desc, idesc,
+        // [scale_A_tmem], [scale_B_tmem], enable_input_d;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(cuda::ptx::kind_mxf4_t,
+                               cuda::ptx::cta_group_1_t,
+                               uint32_t,
+                               uint64_t,
+                               uint64_t,
+                               uint32_t,
+                               uint32_t,
+                               uint32_t,
+                               bool)>(cuda::ptx::tcgen05_mma_block_scale_vec_2_tmem_a));
+          // tcgen05.mma.cta_group::2.kind::mxf4.block_scale.scale_vec::2X [d_tmem], a_desc, b_desc, idesc,
+          // [scale_A_tmem], [scale_B_tmem], enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::kind_mxf4_t,
+                                   cuda::ptx::cta_group_2_t,
+                                   uint32_t,
+                                   uint64_t,
+                                   uint64_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   bool)>(cuda::ptx::tcgen05_mma_block_scale_vec_2_tmem_a));
+          // tcgen05.mma.cta_group::1.kind::mxf4nvf4.block_scale.scale_vec::2X [d_tmem], a_desc, b_desc, idesc,
+          // [scale_A_tmem], [scale_B_tmem], enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::kind_mxf4nvf4_t,
+                                   cuda::ptx::cta_group_1_t,
+                                   uint32_t,
+                                   uint64_t,
+                                   uint64_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   bool)>(cuda::ptx::tcgen05_mma_block_scale_vec_2_tmem_a));
+          // tcgen05.mma.cta_group::2.kind::mxf4nvf4.block_scale.scale_vec::2X [d_tmem], a_desc, b_desc, idesc,
+          // [scale_A_tmem], [scale_B_tmem], enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::kind_mxf4nvf4_t,
+                                   cuda::ptx::cta_group_2_t,
+                                   uint32_t,
+                                   uint64_t,
+                                   uint64_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   bool)>(cuda::ptx::tcgen05_mma_block_scale_vec_2_tmem_a));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tcgen05.mma.cta_group::1.kind::mxf4nvf4.block_scale.scale_vec::4X [d_tmem], a_desc, b_desc, idesc,
+        // [scale_A_tmem], [scale_B_tmem], enable_input_d;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(cuda::ptx::kind_mxf4nvf4_t,
+                               cuda::ptx::cta_group_1_t,
+                               uint32_t,
+                               uint64_t,
+                               uint64_t,
+                               uint32_t,
+                               uint32_t,
+                               uint32_t,
+                               bool)>(cuda::ptx::tcgen05_mma_block_scale_vec_4x_tmem_a));
+          // tcgen05.mma.cta_group::2.kind::mxf4nvf4.block_scale.scale_vec::4X [d_tmem], a_desc, b_desc, idesc,
+          // [scale_A_tmem], [scale_B_tmem], enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::kind_mxf4nvf4_t,
+                                   cuda::ptx::cta_group_2_t,
+                                   uint32_t,
+                                   uint64_t,
+                                   uint64_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   bool)>(cuda::ptx::tcgen05_mma_block_scale_vec_4x_tmem_a));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // tcgen05.mma.cta_group::1.kind::mxf4nvf4.block_scale.scale_vec::4X [d_tmem], a_desc, b_desc, idesc,
+        // [scale_A_tmem], [scale_B_tmem], enable_input_d;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(cuda::ptx::kind_mxf4nvf4_t,
+                               cuda::ptx::cta_group_1_t,
+                               uint32_t,
+                               uint64_t,
+                               uint64_t,
+                               uint32_t,
+                               uint32_t,
+                               uint32_t,
+                               bool)>(cuda::ptx::tcgen05_mma_block_scale_vec_4x_tmem_a));
+          // tcgen05.mma.cta_group::2.kind::mxf4nvf4.block_scale.scale_vec::4X [d_tmem], a_desc, b_desc, idesc,
+          // [scale_A_tmem], [scale_B_tmem], enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::kind_mxf4nvf4_t,
+                                   cuda::ptx::cta_group_2_t,
+                                   uint32_t,
+                                   uint64_t,
+                                   uint64_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   bool)>(cuda::ptx::tcgen05_mma_block_scale_vec_4x_tmem_a));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tcgen05.mma.cta_group::1.kind::mxf8f6f4.block_scale.scale_vec::1X.collector::a::fill [d_tmem], a_desc,
+        // b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(cuda::ptx::kind_mxf8f6f4_t,
+                               cuda::ptx::cta_group_1_t,
+                               uint32_t,
+                               uint64_t,
+                               uint64_t,
+                               uint32_t,
+                               uint32_t,
+                               uint32_t,
+                               bool)>(cuda::ptx::tcgen05_mma_block_scale_vec_1x_collector_a_fill));
+          // tcgen05.mma.cta_group::2.kind::mxf8f6f4.block_scale.scale_vec::1X.collector::a::fill [d_tmem], a_desc,
+          // b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::kind_mxf8f6f4_t,
+                                   cuda::ptx::cta_group_2_t,
+                                   uint32_t,
+                                   uint64_t,
+                                   uint64_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   bool)>(cuda::ptx::tcgen05_mma_block_scale_vec_1x_collector_a_fill));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // tcgen05.mma.cta_group::1.kind::mxf8f6f4.block_scale.scale_vec::1X.collector::a::fill [d_tmem], a_desc,
+        // b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(cuda::ptx::kind_mxf8f6f4_t,
+                               cuda::ptx::cta_group_1_t,
+                               uint32_t,
+                               uint64_t,
+                               uint64_t,
+                               uint32_t,
+                               uint32_t,
+                               uint32_t,
+                               bool)>(cuda::ptx::tcgen05_mma_block_scale_vec_1x_collector_a_fill));
+          // tcgen05.mma.cta_group::2.kind::mxf8f6f4.block_scale.scale_vec::1X.collector::a::fill [d_tmem], a_desc,
+          // b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::kind_mxf8f6f4_t,
+                                   cuda::ptx::cta_group_2_t,
+                                   uint32_t,
+                                   uint64_t,
+                                   uint64_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   bool)>(cuda::ptx::tcgen05_mma_block_scale_vec_1x_collector_a_fill));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tcgen05.mma.cta_group::1.kind::mxf4.block_scale.scale_vec::2X.collector::a::fill [d_tmem], a_desc, b_desc,
+        // idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(cuda::ptx::kind_mxf4_t,
+                               cuda::ptx::cta_group_1_t,
+                               uint32_t,
+                               uint64_t,
+                               uint64_t,
+                               uint32_t,
+                               uint32_t,
+                               uint32_t,
+                               bool)>(cuda::ptx::tcgen05_mma_block_scale_vec_2x_collector_a_fill));
+          // tcgen05.mma.cta_group::2.kind::mxf4.block_scale.scale_vec::2X.collector::a::fill [d_tmem], a_desc,
+          // b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::kind_mxf4_t,
+                                   cuda::ptx::cta_group_2_t,
+                                   uint32_t,
+                                   uint64_t,
+                                   uint64_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   bool)>(cuda::ptx::tcgen05_mma_block_scale_vec_2x_collector_a_fill));
+          // tcgen05.mma.cta_group::1.kind::mxf4nvf4.block_scale.scale_vec::2X.collector::a::fill [d_tmem], a_desc,
+          // b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::kind_mxf4nvf4_t,
+                                   cuda::ptx::cta_group_1_t,
+                                   uint32_t,
+                                   uint64_t,
+                                   uint64_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   bool)>(cuda::ptx::tcgen05_mma_block_scale_vec_2x_collector_a_fill));
+          // tcgen05.mma.cta_group::2.kind::mxf4nvf4.block_scale.scale_vec::2X.collector::a::fill [d_tmem], a_desc,
+          // b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::kind_mxf4nvf4_t,
+                                   cuda::ptx::cta_group_2_t,
+                                   uint32_t,
+                                   uint64_t,
+                                   uint64_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   bool)>(cuda::ptx::tcgen05_mma_block_scale_vec_2x_collector_a_fill));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // tcgen05.mma.cta_group::1.kind::mxf4.block_scale.scale_vec::2X.collector::a::fill [d_tmem], a_desc, b_desc,
+        // idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(cuda::ptx::kind_mxf4_t,
+                               cuda::ptx::cta_group_1_t,
+                               uint32_t,
+                               uint64_t,
+                               uint64_t,
+                               uint32_t,
+                               uint32_t,
+                               uint32_t,
+                               bool)>(cuda::ptx::tcgen05_mma_block_scale_vec_2x_collector_a_fill));
+          // tcgen05.mma.cta_group::2.kind::mxf4.block_scale.scale_vec::2X.collector::a::fill [d_tmem], a_desc,
+          // b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::kind_mxf4_t,
+                                   cuda::ptx::cta_group_2_t,
+                                   uint32_t,
+                                   uint64_t,
+                                   uint64_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   bool)>(cuda::ptx::tcgen05_mma_block_scale_vec_2x_collector_a_fill));
+          // tcgen05.mma.cta_group::1.kind::mxf4nvf4.block_scale.scale_vec::2X.collector::a::fill [d_tmem], a_desc,
+          // b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::kind_mxf4nvf4_t,
+                                   cuda::ptx::cta_group_1_t,
+                                   uint32_t,
+                                   uint64_t,
+                                   uint64_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   bool)>(cuda::ptx::tcgen05_mma_block_scale_vec_2x_collector_a_fill));
+          // tcgen05.mma.cta_group::2.kind::mxf4nvf4.block_scale.scale_vec::2X.collector::a::fill [d_tmem], a_desc,
+          // b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::kind_mxf4nvf4_t,
+                                   cuda::ptx::cta_group_2_t,
+                                   uint32_t,
+                                   uint64_t,
+                                   uint64_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   bool)>(cuda::ptx::tcgen05_mma_block_scale_vec_2x_collector_a_fill));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tcgen05.mma.cta_group::1.kind::mxf4nvf4.block_scale.scale_vec::4X.collector::a::fill [d_tmem], a_desc,
+        // b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(cuda::ptx::kind_mxf4nvf4_t,
+                               cuda::ptx::cta_group_1_t,
+                               uint32_t,
+                               uint64_t,
+                               uint64_t,
+                               uint32_t,
+                               uint32_t,
+                               uint32_t,
+                               bool)>(cuda::ptx::tcgen05_mma_block_scale_vec_4x_collector_a_fill));
+          // tcgen05.mma.cta_group::2.kind::mxf4nvf4.block_scale.scale_vec::4X.collector::a::fill [d_tmem], a_desc,
+          // b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::kind_mxf4nvf4_t,
+                                   cuda::ptx::cta_group_2_t,
+                                   uint32_t,
+                                   uint64_t,
+                                   uint64_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   bool)>(cuda::ptx::tcgen05_mma_block_scale_vec_4x_collector_a_fill));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // tcgen05.mma.cta_group::1.kind::mxf4nvf4.block_scale.scale_vec::4X.collector::a::fill [d_tmem], a_desc,
+        // b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(cuda::ptx::kind_mxf4nvf4_t,
+                               cuda::ptx::cta_group_1_t,
+                               uint32_t,
+                               uint64_t,
+                               uint64_t,
+                               uint32_t,
+                               uint32_t,
+                               uint32_t,
+                               bool)>(cuda::ptx::tcgen05_mma_block_scale_vec_4x_collector_a_fill));
+          // tcgen05.mma.cta_group::2.kind::mxf4nvf4.block_scale.scale_vec::4X.collector::a::fill [d_tmem], a_desc,
+          // b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::kind_mxf4nvf4_t,
+                                   cuda::ptx::cta_group_2_t,
+                                   uint32_t,
+                                   uint64_t,
+                                   uint64_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   bool)>(cuda::ptx::tcgen05_mma_block_scale_vec_4x_collector_a_fill));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tcgen05.mma.cta_group::1.kind::mxf8f6f4.block_scale.scale_vec::1X.collector::a::fill [d_tmem], a_desc,
+        // b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(cuda::ptx::kind_mxf8f6f4_t,
+                               cuda::ptx::cta_group_1_t,
+                               uint32_t,
+                               uint64_t,
+                               uint64_t,
+                               uint32_t,
+                               uint32_t,
+                               uint32_t,
+                               bool)>(cuda::ptx::tcgen05_mma_block_scale_vec_1x_tmem_a_collector_a_fill));
+          // tcgen05.mma.cta_group::2.kind::mxf8f6f4.block_scale.scale_vec::1X.collector::a::fill [d_tmem], a_desc,
+          // b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::kind_mxf8f6f4_t,
+                                   cuda::ptx::cta_group_2_t,
+                                   uint32_t,
+                                   uint64_t,
+                                   uint64_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   bool)>(cuda::ptx::tcgen05_mma_block_scale_vec_1x_tmem_a_collector_a_fill));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // tcgen05.mma.cta_group::1.kind::mxf8f6f4.block_scale.scale_vec::1X.collector::a::fill [d_tmem], a_desc,
+        // b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(cuda::ptx::kind_mxf8f6f4_t,
+                               cuda::ptx::cta_group_1_t,
+                               uint32_t,
+                               uint64_t,
+                               uint64_t,
+                               uint32_t,
+                               uint32_t,
+                               uint32_t,
+                               bool)>(cuda::ptx::tcgen05_mma_block_scale_vec_1x_tmem_a_collector_a_fill));
+          // tcgen05.mma.cta_group::2.kind::mxf8f6f4.block_scale.scale_vec::1X.collector::a::fill [d_tmem], a_desc,
+          // b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::kind_mxf8f6f4_t,
+                                   cuda::ptx::cta_group_2_t,
+                                   uint32_t,
+                                   uint64_t,
+                                   uint64_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   bool)>(cuda::ptx::tcgen05_mma_block_scale_vec_1x_tmem_a_collector_a_fill));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tcgen05.mma.cta_group::1.kind::mxf4.block_scale.scale_vec::2X.collector::a::fill [d_tmem], a_desc, b_desc,
+        // idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(cuda::ptx::kind_mxf4_t,
+                               cuda::ptx::cta_group_1_t,
+                               uint32_t,
+                               uint64_t,
+                               uint64_t,
+                               uint32_t,
+                               uint32_t,
+                               uint32_t,
+                               bool)>(cuda::ptx::tcgen05_mma_block_scale_vec_2_tmem_a_collector_a_fill));
+          // tcgen05.mma.cta_group::2.kind::mxf4.block_scale.scale_vec::2X.collector::a::fill [d_tmem], a_desc,
+          // b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::kind_mxf4_t,
+                                   cuda::ptx::cta_group_2_t,
+                                   uint32_t,
+                                   uint64_t,
+                                   uint64_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   bool)>(cuda::ptx::tcgen05_mma_block_scale_vec_2_tmem_a_collector_a_fill));
+          // tcgen05.mma.cta_group::1.kind::mxf4nvf4.block_scale.scale_vec::2X.collector::a::fill [d_tmem], a_desc,
+          // b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::kind_mxf4nvf4_t,
+                                   cuda::ptx::cta_group_1_t,
+                                   uint32_t,
+                                   uint64_t,
+                                   uint64_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   bool)>(cuda::ptx::tcgen05_mma_block_scale_vec_2_tmem_a_collector_a_fill));
+          // tcgen05.mma.cta_group::2.kind::mxf4nvf4.block_scale.scale_vec::2X.collector::a::fill [d_tmem], a_desc,
+          // b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::kind_mxf4nvf4_t,
+                                   cuda::ptx::cta_group_2_t,
+                                   uint32_t,
+                                   uint64_t,
+                                   uint64_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   bool)>(cuda::ptx::tcgen05_mma_block_scale_vec_2_tmem_a_collector_a_fill));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // tcgen05.mma.cta_group::1.kind::mxf4.block_scale.scale_vec::2X.collector::a::fill [d_tmem], a_desc, b_desc,
+        // idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(cuda::ptx::kind_mxf4_t,
+                               cuda::ptx::cta_group_1_t,
+                               uint32_t,
+                               uint64_t,
+                               uint64_t,
+                               uint32_t,
+                               uint32_t,
+                               uint32_t,
+                               bool)>(cuda::ptx::tcgen05_mma_block_scale_vec_2_tmem_a_collector_a_fill));
+          // tcgen05.mma.cta_group::2.kind::mxf4.block_scale.scale_vec::2X.collector::a::fill [d_tmem], a_desc,
+          // b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::kind_mxf4_t,
+                                   cuda::ptx::cta_group_2_t,
+                                   uint32_t,
+                                   uint64_t,
+                                   uint64_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   bool)>(cuda::ptx::tcgen05_mma_block_scale_vec_2_tmem_a_collector_a_fill));
+          // tcgen05.mma.cta_group::1.kind::mxf4nvf4.block_scale.scale_vec::2X.collector::a::fill [d_tmem], a_desc,
+          // b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::kind_mxf4nvf4_t,
+                                   cuda::ptx::cta_group_1_t,
+                                   uint32_t,
+                                   uint64_t,
+                                   uint64_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   bool)>(cuda::ptx::tcgen05_mma_block_scale_vec_2_tmem_a_collector_a_fill));
+          // tcgen05.mma.cta_group::2.kind::mxf4nvf4.block_scale.scale_vec::2X.collector::a::fill [d_tmem], a_desc,
+          // b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::kind_mxf4nvf4_t,
+                                   cuda::ptx::cta_group_2_t,
+                                   uint32_t,
+                                   uint64_t,
+                                   uint64_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   bool)>(cuda::ptx::tcgen05_mma_block_scale_vec_2_tmem_a_collector_a_fill));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tcgen05.mma.cta_group::1.kind::mxf4nvf4.block_scale.scale_vec::4X.collector::a::fill [d_tmem], a_desc,
+        // b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(cuda::ptx::kind_mxf4nvf4_t,
+                               cuda::ptx::cta_group_1_t,
+                               uint32_t,
+                               uint64_t,
+                               uint64_t,
+                               uint32_t,
+                               uint32_t,
+                               uint32_t,
+                               bool)>(cuda::ptx::tcgen05_mma_block_scale_vec_4x_tmem_a_collector_a_fill));
+          // tcgen05.mma.cta_group::2.kind::mxf4nvf4.block_scale.scale_vec::4X.collector::a::fill [d_tmem], a_desc,
+          // b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::kind_mxf4nvf4_t,
+                                   cuda::ptx::cta_group_2_t,
+                                   uint32_t,
+                                   uint64_t,
+                                   uint64_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   bool)>(cuda::ptx::tcgen05_mma_block_scale_vec_4x_tmem_a_collector_a_fill));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // tcgen05.mma.cta_group::1.kind::mxf4nvf4.block_scale.scale_vec::4X.collector::a::fill [d_tmem], a_desc,
+        // b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(cuda::ptx::kind_mxf4nvf4_t,
+                               cuda::ptx::cta_group_1_t,
+                               uint32_t,
+                               uint64_t,
+                               uint64_t,
+                               uint32_t,
+                               uint32_t,
+                               uint32_t,
+                               bool)>(cuda::ptx::tcgen05_mma_block_scale_vec_4x_tmem_a_collector_a_fill));
+          // tcgen05.mma.cta_group::2.kind::mxf4nvf4.block_scale.scale_vec::4X.collector::a::fill [d_tmem], a_desc,
+          // b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::kind_mxf4nvf4_t,
+                                   cuda::ptx::cta_group_2_t,
+                                   uint32_t,
+                                   uint64_t,
+                                   uint64_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   bool)>(cuda::ptx::tcgen05_mma_block_scale_vec_4x_tmem_a_collector_a_fill));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tcgen05.mma.cta_group::1.kind::mxf8f6f4.block_scale.scale_vec::1X.collector::a::use [d_tmem], a_desc, b_desc,
+        // idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(cuda::ptx::kind_mxf8f6f4_t,
+                               cuda::ptx::cta_group_1_t,
+                               uint32_t,
+                               uint64_t,
+                               uint64_t,
+                               uint32_t,
+                               uint32_t,
+                               uint32_t,
+                               bool)>(cuda::ptx::tcgen05_mma_block_scale_vec_1x_collector_a_use));
+          // tcgen05.mma.cta_group::2.kind::mxf8f6f4.block_scale.scale_vec::1X.collector::a::use [d_tmem], a_desc,
+          // b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::kind_mxf8f6f4_t,
+                                   cuda::ptx::cta_group_2_t,
+                                   uint32_t,
+                                   uint64_t,
+                                   uint64_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   bool)>(cuda::ptx::tcgen05_mma_block_scale_vec_1x_collector_a_use));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // tcgen05.mma.cta_group::1.kind::mxf8f6f4.block_scale.scale_vec::1X.collector::a::use [d_tmem], a_desc, b_desc,
+        // idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(cuda::ptx::kind_mxf8f6f4_t,
+                               cuda::ptx::cta_group_1_t,
+                               uint32_t,
+                               uint64_t,
+                               uint64_t,
+                               uint32_t,
+                               uint32_t,
+                               uint32_t,
+                               bool)>(cuda::ptx::tcgen05_mma_block_scale_vec_1x_collector_a_use));
+          // tcgen05.mma.cta_group::2.kind::mxf8f6f4.block_scale.scale_vec::1X.collector::a::use [d_tmem], a_desc,
+          // b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::kind_mxf8f6f4_t,
+                                   cuda::ptx::cta_group_2_t,
+                                   uint32_t,
+                                   uint64_t,
+                                   uint64_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   bool)>(cuda::ptx::tcgen05_mma_block_scale_vec_1x_collector_a_use));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tcgen05.mma.cta_group::1.kind::mxf4.block_scale.scale_vec::2X.collector::a::use [d_tmem], a_desc, b_desc,
+        // idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(cuda::ptx::kind_mxf4_t,
+                               cuda::ptx::cta_group_1_t,
+                               uint32_t,
+                               uint64_t,
+                               uint64_t,
+                               uint32_t,
+                               uint32_t,
+                               uint32_t,
+                               bool)>(cuda::ptx::tcgen05_mma_block_scale_vec_2x_collector_a_use));
+          // tcgen05.mma.cta_group::2.kind::mxf4.block_scale.scale_vec::2X.collector::a::use [d_tmem], a_desc, b_desc,
+          // idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::kind_mxf4_t,
+                                   cuda::ptx::cta_group_2_t,
+                                   uint32_t,
+                                   uint64_t,
+                                   uint64_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   bool)>(cuda::ptx::tcgen05_mma_block_scale_vec_2x_collector_a_use));
+          // tcgen05.mma.cta_group::1.kind::mxf4nvf4.block_scale.scale_vec::2X.collector::a::use [d_tmem], a_desc,
+          // b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::kind_mxf4nvf4_t,
+                                   cuda::ptx::cta_group_1_t,
+                                   uint32_t,
+                                   uint64_t,
+                                   uint64_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   bool)>(cuda::ptx::tcgen05_mma_block_scale_vec_2x_collector_a_use));
+          // tcgen05.mma.cta_group::2.kind::mxf4nvf4.block_scale.scale_vec::2X.collector::a::use [d_tmem], a_desc,
+          // b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::kind_mxf4nvf4_t,
+                                   cuda::ptx::cta_group_2_t,
+                                   uint32_t,
+                                   uint64_t,
+                                   uint64_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   bool)>(cuda::ptx::tcgen05_mma_block_scale_vec_2x_collector_a_use));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // tcgen05.mma.cta_group::1.kind::mxf4.block_scale.scale_vec::2X.collector::a::use [d_tmem], a_desc, b_desc,
+        // idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(cuda::ptx::kind_mxf4_t,
+                               cuda::ptx::cta_group_1_t,
+                               uint32_t,
+                               uint64_t,
+                               uint64_t,
+                               uint32_t,
+                               uint32_t,
+                               uint32_t,
+                               bool)>(cuda::ptx::tcgen05_mma_block_scale_vec_2x_collector_a_use));
+          // tcgen05.mma.cta_group::2.kind::mxf4.block_scale.scale_vec::2X.collector::a::use [d_tmem], a_desc, b_desc,
+          // idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::kind_mxf4_t,
+                                   cuda::ptx::cta_group_2_t,
+                                   uint32_t,
+                                   uint64_t,
+                                   uint64_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   bool)>(cuda::ptx::tcgen05_mma_block_scale_vec_2x_collector_a_use));
+          // tcgen05.mma.cta_group::1.kind::mxf4nvf4.block_scale.scale_vec::2X.collector::a::use [d_tmem], a_desc,
+          // b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::kind_mxf4nvf4_t,
+                                   cuda::ptx::cta_group_1_t,
+                                   uint32_t,
+                                   uint64_t,
+                                   uint64_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   bool)>(cuda::ptx::tcgen05_mma_block_scale_vec_2x_collector_a_use));
+          // tcgen05.mma.cta_group::2.kind::mxf4nvf4.block_scale.scale_vec::2X.collector::a::use [d_tmem], a_desc,
+          // b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::kind_mxf4nvf4_t,
+                                   cuda::ptx::cta_group_2_t,
+                                   uint32_t,
+                                   uint64_t,
+                                   uint64_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   bool)>(cuda::ptx::tcgen05_mma_block_scale_vec_2x_collector_a_use));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tcgen05.mma.cta_group::1.kind::mxf4nvf4.block_scale.scale_vec::4X.collector::a::use [d_tmem], a_desc, b_desc,
+        // idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(cuda::ptx::kind_mxf4nvf4_t,
+                               cuda::ptx::cta_group_1_t,
+                               uint32_t,
+                               uint64_t,
+                               uint64_t,
+                               uint32_t,
+                               uint32_t,
+                               uint32_t,
+                               bool)>(cuda::ptx::tcgen05_mma_block_scale_vec_4x_collector_a_use));
+          // tcgen05.mma.cta_group::2.kind::mxf4nvf4.block_scale.scale_vec::4X.collector::a::use [d_tmem], a_desc,
+          // b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::kind_mxf4nvf4_t,
+                                   cuda::ptx::cta_group_2_t,
+                                   uint32_t,
+                                   uint64_t,
+                                   uint64_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   bool)>(cuda::ptx::tcgen05_mma_block_scale_vec_4x_collector_a_use));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // tcgen05.mma.cta_group::1.kind::mxf4nvf4.block_scale.scale_vec::4X.collector::a::use [d_tmem], a_desc, b_desc,
+        // idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(cuda::ptx::kind_mxf4nvf4_t,
+                               cuda::ptx::cta_group_1_t,
+                               uint32_t,
+                               uint64_t,
+                               uint64_t,
+                               uint32_t,
+                               uint32_t,
+                               uint32_t,
+                               bool)>(cuda::ptx::tcgen05_mma_block_scale_vec_4x_collector_a_use));
+          // tcgen05.mma.cta_group::2.kind::mxf4nvf4.block_scale.scale_vec::4X.collector::a::use [d_tmem], a_desc,
+          // b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::kind_mxf4nvf4_t,
+                                   cuda::ptx::cta_group_2_t,
+                                   uint32_t,
+                                   uint64_t,
+                                   uint64_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   bool)>(cuda::ptx::tcgen05_mma_block_scale_vec_4x_collector_a_use));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tcgen05.mma.cta_group::1.kind::mxf8f6f4.block_scale.scale_vec::1X.collector::a::use [d_tmem], a_desc, b_desc,
+        // idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(cuda::ptx::kind_mxf8f6f4_t,
+                               cuda::ptx::cta_group_1_t,
+                               uint32_t,
+                               uint64_t,
+                               uint64_t,
+                               uint32_t,
+                               uint32_t,
+                               uint32_t,
+                               bool)>(cuda::ptx::tcgen05_mma_block_scale_vec_1x_tmem_a_collector_a_use));
+          // tcgen05.mma.cta_group::2.kind::mxf8f6f4.block_scale.scale_vec::1X.collector::a::use [d_tmem], a_desc,
+          // b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::kind_mxf8f6f4_t,
+                                   cuda::ptx::cta_group_2_t,
+                                   uint32_t,
+                                   uint64_t,
+                                   uint64_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   bool)>(cuda::ptx::tcgen05_mma_block_scale_vec_1x_tmem_a_collector_a_use));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // tcgen05.mma.cta_group::1.kind::mxf8f6f4.block_scale.scale_vec::1X.collector::a::use [d_tmem], a_desc, b_desc,
+        // idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(cuda::ptx::kind_mxf8f6f4_t,
+                               cuda::ptx::cta_group_1_t,
+                               uint32_t,
+                               uint64_t,
+                               uint64_t,
+                               uint32_t,
+                               uint32_t,
+                               uint32_t,
+                               bool)>(cuda::ptx::tcgen05_mma_block_scale_vec_1x_tmem_a_collector_a_use));
+          // tcgen05.mma.cta_group::2.kind::mxf8f6f4.block_scale.scale_vec::1X.collector::a::use [d_tmem], a_desc,
+          // b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::kind_mxf8f6f4_t,
+                                   cuda::ptx::cta_group_2_t,
+                                   uint32_t,
+                                   uint64_t,
+                                   uint64_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   bool)>(cuda::ptx::tcgen05_mma_block_scale_vec_1x_tmem_a_collector_a_use));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tcgen05.mma.cta_group::1.kind::mxf4.block_scale.scale_vec::2X.collector::a::use [d_tmem], a_desc, b_desc,
+        // idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(cuda::ptx::kind_mxf4_t,
+                               cuda::ptx::cta_group_1_t,
+                               uint32_t,
+                               uint64_t,
+                               uint64_t,
+                               uint32_t,
+                               uint32_t,
+                               uint32_t,
+                               bool)>(cuda::ptx::tcgen05_mma_block_scale_vec_2_tmem_a_collector_a_use));
+          // tcgen05.mma.cta_group::2.kind::mxf4.block_scale.scale_vec::2X.collector::a::use [d_tmem], a_desc, b_desc,
+          // idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::kind_mxf4_t,
+                                   cuda::ptx::cta_group_2_t,
+                                   uint32_t,
+                                   uint64_t,
+                                   uint64_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   bool)>(cuda::ptx::tcgen05_mma_block_scale_vec_2_tmem_a_collector_a_use));
+          // tcgen05.mma.cta_group::1.kind::mxf4nvf4.block_scale.scale_vec::2X.collector::a::use [d_tmem], a_desc,
+          // b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::kind_mxf4nvf4_t,
+                                   cuda::ptx::cta_group_1_t,
+                                   uint32_t,
+                                   uint64_t,
+                                   uint64_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   bool)>(cuda::ptx::tcgen05_mma_block_scale_vec_2_tmem_a_collector_a_use));
+          // tcgen05.mma.cta_group::2.kind::mxf4nvf4.block_scale.scale_vec::2X.collector::a::use [d_tmem], a_desc,
+          // b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::kind_mxf4nvf4_t,
+                                   cuda::ptx::cta_group_2_t,
+                                   uint32_t,
+                                   uint64_t,
+                                   uint64_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   bool)>(cuda::ptx::tcgen05_mma_block_scale_vec_2_tmem_a_collector_a_use));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // tcgen05.mma.cta_group::1.kind::mxf4.block_scale.scale_vec::2X.collector::a::use [d_tmem], a_desc, b_desc,
+        // idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(cuda::ptx::kind_mxf4_t,
+                               cuda::ptx::cta_group_1_t,
+                               uint32_t,
+                               uint64_t,
+                               uint64_t,
+                               uint32_t,
+                               uint32_t,
+                               uint32_t,
+                               bool)>(cuda::ptx::tcgen05_mma_block_scale_vec_2_tmem_a_collector_a_use));
+          // tcgen05.mma.cta_group::2.kind::mxf4.block_scale.scale_vec::2X.collector::a::use [d_tmem], a_desc, b_desc,
+          // idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::kind_mxf4_t,
+                                   cuda::ptx::cta_group_2_t,
+                                   uint32_t,
+                                   uint64_t,
+                                   uint64_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   bool)>(cuda::ptx::tcgen05_mma_block_scale_vec_2_tmem_a_collector_a_use));
+          // tcgen05.mma.cta_group::1.kind::mxf4nvf4.block_scale.scale_vec::2X.collector::a::use [d_tmem], a_desc,
+          // b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::kind_mxf4nvf4_t,
+                                   cuda::ptx::cta_group_1_t,
+                                   uint32_t,
+                                   uint64_t,
+                                   uint64_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   bool)>(cuda::ptx::tcgen05_mma_block_scale_vec_2_tmem_a_collector_a_use));
+          // tcgen05.mma.cta_group::2.kind::mxf4nvf4.block_scale.scale_vec::2X.collector::a::use [d_tmem], a_desc,
+          // b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::kind_mxf4nvf4_t,
+                                   cuda::ptx::cta_group_2_t,
+                                   uint32_t,
+                                   uint64_t,
+                                   uint64_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   bool)>(cuda::ptx::tcgen05_mma_block_scale_vec_2_tmem_a_collector_a_use));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tcgen05.mma.cta_group::1.kind::mxf4nvf4.block_scale.scale_vec::4X.collector::a::use [d_tmem], a_desc, b_desc,
+        // idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(cuda::ptx::kind_mxf4nvf4_t,
+                               cuda::ptx::cta_group_1_t,
+                               uint32_t,
+                               uint64_t,
+                               uint64_t,
+                               uint32_t,
+                               uint32_t,
+                               uint32_t,
+                               bool)>(cuda::ptx::tcgen05_mma_block_scale_vec_4x_tmem_a_collector_a_use));
+          // tcgen05.mma.cta_group::2.kind::mxf4nvf4.block_scale.scale_vec::4X.collector::a::use [d_tmem], a_desc,
+          // b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::kind_mxf4nvf4_t,
+                                   cuda::ptx::cta_group_2_t,
+                                   uint32_t,
+                                   uint64_t,
+                                   uint64_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   bool)>(cuda::ptx::tcgen05_mma_block_scale_vec_4x_tmem_a_collector_a_use));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // tcgen05.mma.cta_group::1.kind::mxf4nvf4.block_scale.scale_vec::4X.collector::a::use [d_tmem], a_desc, b_desc,
+        // idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(cuda::ptx::kind_mxf4nvf4_t,
+                               cuda::ptx::cta_group_1_t,
+                               uint32_t,
+                               uint64_t,
+                               uint64_t,
+                               uint32_t,
+                               uint32_t,
+                               uint32_t,
+                               bool)>(cuda::ptx::tcgen05_mma_block_scale_vec_4x_tmem_a_collector_a_use));
+          // tcgen05.mma.cta_group::2.kind::mxf4nvf4.block_scale.scale_vec::4X.collector::a::use [d_tmem], a_desc,
+          // b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::kind_mxf4nvf4_t,
+                                   cuda::ptx::cta_group_2_t,
+                                   uint32_t,
+                                   uint64_t,
+                                   uint64_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   bool)>(cuda::ptx::tcgen05_mma_block_scale_vec_4x_tmem_a_collector_a_use));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tcgen05.mma.cta_group::1.kind::mxf8f6f4.block_scale.scale_vec::1X.collector::a::lastuse [d_tmem], a_desc,
+        // b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(cuda::ptx::kind_mxf8f6f4_t,
+                               cuda::ptx::cta_group_1_t,
+                               uint32_t,
+                               uint64_t,
+                               uint64_t,
+                               uint32_t,
+                               uint32_t,
+                               uint32_t,
+                               bool)>(cuda::ptx::tcgen05_mma_block_scale_vec_1x_collector_a_lastuse));
+          // tcgen05.mma.cta_group::2.kind::mxf8f6f4.block_scale.scale_vec::1X.collector::a::lastuse [d_tmem], a_desc,
+          // b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::kind_mxf8f6f4_t,
+                                   cuda::ptx::cta_group_2_t,
+                                   uint32_t,
+                                   uint64_t,
+                                   uint64_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   bool)>(cuda::ptx::tcgen05_mma_block_scale_vec_1x_collector_a_lastuse));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // tcgen05.mma.cta_group::1.kind::mxf8f6f4.block_scale.scale_vec::1X.collector::a::lastuse [d_tmem], a_desc,
+        // b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(cuda::ptx::kind_mxf8f6f4_t,
+                               cuda::ptx::cta_group_1_t,
+                               uint32_t,
+                               uint64_t,
+                               uint64_t,
+                               uint32_t,
+                               uint32_t,
+                               uint32_t,
+                               bool)>(cuda::ptx::tcgen05_mma_block_scale_vec_1x_collector_a_lastuse));
+          // tcgen05.mma.cta_group::2.kind::mxf8f6f4.block_scale.scale_vec::1X.collector::a::lastuse [d_tmem], a_desc,
+          // b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::kind_mxf8f6f4_t,
+                                   cuda::ptx::cta_group_2_t,
+                                   uint32_t,
+                                   uint64_t,
+                                   uint64_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   bool)>(cuda::ptx::tcgen05_mma_block_scale_vec_1x_collector_a_lastuse));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tcgen05.mma.cta_group::1.kind::mxf4.block_scale.scale_vec::2X.collector::a::lastuse [d_tmem], a_desc, b_desc,
+        // idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(cuda::ptx::kind_mxf4_t,
+                               cuda::ptx::cta_group_1_t,
+                               uint32_t,
+                               uint64_t,
+                               uint64_t,
+                               uint32_t,
+                               uint32_t,
+                               uint32_t,
+                               bool)>(cuda::ptx::tcgen05_mma_block_scale_vec_2x_collector_a_lastuse));
+          // tcgen05.mma.cta_group::2.kind::mxf4.block_scale.scale_vec::2X.collector::a::lastuse [d_tmem], a_desc,
+          // b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::kind_mxf4_t,
+                                   cuda::ptx::cta_group_2_t,
+                                   uint32_t,
+                                   uint64_t,
+                                   uint64_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   bool)>(cuda::ptx::tcgen05_mma_block_scale_vec_2x_collector_a_lastuse));
+          // tcgen05.mma.cta_group::1.kind::mxf4nvf4.block_scale.scale_vec::2X.collector::a::lastuse [d_tmem], a_desc,
+          // b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::kind_mxf4nvf4_t,
+                                   cuda::ptx::cta_group_1_t,
+                                   uint32_t,
+                                   uint64_t,
+                                   uint64_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   bool)>(cuda::ptx::tcgen05_mma_block_scale_vec_2x_collector_a_lastuse));
+          // tcgen05.mma.cta_group::2.kind::mxf4nvf4.block_scale.scale_vec::2X.collector::a::lastuse [d_tmem], a_desc,
+          // b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::kind_mxf4nvf4_t,
+                                   cuda::ptx::cta_group_2_t,
+                                   uint32_t,
+                                   uint64_t,
+                                   uint64_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   bool)>(cuda::ptx::tcgen05_mma_block_scale_vec_2x_collector_a_lastuse));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // tcgen05.mma.cta_group::1.kind::mxf4.block_scale.scale_vec::2X.collector::a::lastuse [d_tmem], a_desc, b_desc,
+        // idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(cuda::ptx::kind_mxf4_t,
+                               cuda::ptx::cta_group_1_t,
+                               uint32_t,
+                               uint64_t,
+                               uint64_t,
+                               uint32_t,
+                               uint32_t,
+                               uint32_t,
+                               bool)>(cuda::ptx::tcgen05_mma_block_scale_vec_2x_collector_a_lastuse));
+          // tcgen05.mma.cta_group::2.kind::mxf4.block_scale.scale_vec::2X.collector::a::lastuse [d_tmem], a_desc,
+          // b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::kind_mxf4_t,
+                                   cuda::ptx::cta_group_2_t,
+                                   uint32_t,
+                                   uint64_t,
+                                   uint64_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   bool)>(cuda::ptx::tcgen05_mma_block_scale_vec_2x_collector_a_lastuse));
+          // tcgen05.mma.cta_group::1.kind::mxf4nvf4.block_scale.scale_vec::2X.collector::a::lastuse [d_tmem], a_desc,
+          // b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::kind_mxf4nvf4_t,
+                                   cuda::ptx::cta_group_1_t,
+                                   uint32_t,
+                                   uint64_t,
+                                   uint64_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   bool)>(cuda::ptx::tcgen05_mma_block_scale_vec_2x_collector_a_lastuse));
+          // tcgen05.mma.cta_group::2.kind::mxf4nvf4.block_scale.scale_vec::2X.collector::a::lastuse [d_tmem], a_desc,
+          // b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::kind_mxf4nvf4_t,
+                                   cuda::ptx::cta_group_2_t,
+                                   uint32_t,
+                                   uint64_t,
+                                   uint64_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   bool)>(cuda::ptx::tcgen05_mma_block_scale_vec_2x_collector_a_lastuse));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tcgen05.mma.cta_group::1.kind::mxf4nvf4.block_scale.scale_vec::4X.collector::a::lastuse [d_tmem], a_desc,
+        // b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(cuda::ptx::kind_mxf4nvf4_t,
+                               cuda::ptx::cta_group_1_t,
+                               uint32_t,
+                               uint64_t,
+                               uint64_t,
+                               uint32_t,
+                               uint32_t,
+                               uint32_t,
+                               bool)>(cuda::ptx::tcgen05_mma_block_scale_vec_4x_collector_a_lastuse));
+          // tcgen05.mma.cta_group::2.kind::mxf4nvf4.block_scale.scale_vec::4X.collector::a::lastuse [d_tmem], a_desc,
+          // b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::kind_mxf4nvf4_t,
+                                   cuda::ptx::cta_group_2_t,
+                                   uint32_t,
+                                   uint64_t,
+                                   uint64_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   bool)>(cuda::ptx::tcgen05_mma_block_scale_vec_4x_collector_a_lastuse));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // tcgen05.mma.cta_group::1.kind::mxf4nvf4.block_scale.scale_vec::4X.collector::a::lastuse [d_tmem], a_desc,
+        // b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(cuda::ptx::kind_mxf4nvf4_t,
+                               cuda::ptx::cta_group_1_t,
+                               uint32_t,
+                               uint64_t,
+                               uint64_t,
+                               uint32_t,
+                               uint32_t,
+                               uint32_t,
+                               bool)>(cuda::ptx::tcgen05_mma_block_scale_vec_4x_collector_a_lastuse));
+          // tcgen05.mma.cta_group::2.kind::mxf4nvf4.block_scale.scale_vec::4X.collector::a::lastuse [d_tmem], a_desc,
+          // b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::kind_mxf4nvf4_t,
+                                   cuda::ptx::cta_group_2_t,
+                                   uint32_t,
+                                   uint64_t,
+                                   uint64_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   bool)>(cuda::ptx::tcgen05_mma_block_scale_vec_4x_collector_a_lastuse));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tcgen05.mma.cta_group::1.kind::mxf8f6f4.block_scale.scale_vec::1X.collector::a::lastuse [d_tmem], a_desc,
+        // b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(cuda::ptx::kind_mxf8f6f4_t,
+                               cuda::ptx::cta_group_1_t,
+                               uint32_t,
+                               uint64_t,
+                               uint64_t,
+                               uint32_t,
+                               uint32_t,
+                               uint32_t,
+                               bool)>(cuda::ptx::tcgen05_mma_block_scale_vec_1x_tmem_a_collector_a_lastuse));
+          // tcgen05.mma.cta_group::2.kind::mxf8f6f4.block_scale.scale_vec::1X.collector::a::lastuse [d_tmem], a_desc,
+          // b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::kind_mxf8f6f4_t,
+                                   cuda::ptx::cta_group_2_t,
+                                   uint32_t,
+                                   uint64_t,
+                                   uint64_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   bool)>(cuda::ptx::tcgen05_mma_block_scale_vec_1x_tmem_a_collector_a_lastuse));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // tcgen05.mma.cta_group::1.kind::mxf8f6f4.block_scale.scale_vec::1X.collector::a::lastuse [d_tmem], a_desc,
+        // b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(cuda::ptx::kind_mxf8f6f4_t,
+                               cuda::ptx::cta_group_1_t,
+                               uint32_t,
+                               uint64_t,
+                               uint64_t,
+                               uint32_t,
+                               uint32_t,
+                               uint32_t,
+                               bool)>(cuda::ptx::tcgen05_mma_block_scale_vec_1x_tmem_a_collector_a_lastuse));
+          // tcgen05.mma.cta_group::2.kind::mxf8f6f4.block_scale.scale_vec::1X.collector::a::lastuse [d_tmem], a_desc,
+          // b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::kind_mxf8f6f4_t,
+                                   cuda::ptx::cta_group_2_t,
+                                   uint32_t,
+                                   uint64_t,
+                                   uint64_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   bool)>(cuda::ptx::tcgen05_mma_block_scale_vec_1x_tmem_a_collector_a_lastuse));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tcgen05.mma.cta_group::1.kind::mxf4.block_scale.scale_vec::2X.collector::a::lastuse [d_tmem], a_desc, b_desc,
+        // idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(cuda::ptx::kind_mxf4_t,
+                               cuda::ptx::cta_group_1_t,
+                               uint32_t,
+                               uint64_t,
+                               uint64_t,
+                               uint32_t,
+                               uint32_t,
+                               uint32_t,
+                               bool)>(cuda::ptx::tcgen05_mma_block_scale_vec_2_tmem_a_collector_a_lastuse));
+          // tcgen05.mma.cta_group::2.kind::mxf4.block_scale.scale_vec::2X.collector::a::lastuse [d_tmem], a_desc,
+          // b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::kind_mxf4_t,
+                                   cuda::ptx::cta_group_2_t,
+                                   uint32_t,
+                                   uint64_t,
+                                   uint64_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   bool)>(cuda::ptx::tcgen05_mma_block_scale_vec_2_tmem_a_collector_a_lastuse));
+          // tcgen05.mma.cta_group::1.kind::mxf4nvf4.block_scale.scale_vec::2X.collector::a::lastuse [d_tmem], a_desc,
+          // b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::kind_mxf4nvf4_t,
+                                   cuda::ptx::cta_group_1_t,
+                                   uint32_t,
+                                   uint64_t,
+                                   uint64_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   bool)>(cuda::ptx::tcgen05_mma_block_scale_vec_2_tmem_a_collector_a_lastuse));
+          // tcgen05.mma.cta_group::2.kind::mxf4nvf4.block_scale.scale_vec::2X.collector::a::lastuse [d_tmem], a_desc,
+          // b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::kind_mxf4nvf4_t,
+                                   cuda::ptx::cta_group_2_t,
+                                   uint32_t,
+                                   uint64_t,
+                                   uint64_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   bool)>(cuda::ptx::tcgen05_mma_block_scale_vec_2_tmem_a_collector_a_lastuse));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // tcgen05.mma.cta_group::1.kind::mxf4.block_scale.scale_vec::2X.collector::a::lastuse [d_tmem], a_desc, b_desc,
+        // idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(cuda::ptx::kind_mxf4_t,
+                               cuda::ptx::cta_group_1_t,
+                               uint32_t,
+                               uint64_t,
+                               uint64_t,
+                               uint32_t,
+                               uint32_t,
+                               uint32_t,
+                               bool)>(cuda::ptx::tcgen05_mma_block_scale_vec_2_tmem_a_collector_a_lastuse));
+          // tcgen05.mma.cta_group::2.kind::mxf4.block_scale.scale_vec::2X.collector::a::lastuse [d_tmem], a_desc,
+          // b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::kind_mxf4_t,
+                                   cuda::ptx::cta_group_2_t,
+                                   uint32_t,
+                                   uint64_t,
+                                   uint64_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   bool)>(cuda::ptx::tcgen05_mma_block_scale_vec_2_tmem_a_collector_a_lastuse));
+          // tcgen05.mma.cta_group::1.kind::mxf4nvf4.block_scale.scale_vec::2X.collector::a::lastuse [d_tmem], a_desc,
+          // b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::kind_mxf4nvf4_t,
+                                   cuda::ptx::cta_group_1_t,
+                                   uint32_t,
+                                   uint64_t,
+                                   uint64_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   bool)>(cuda::ptx::tcgen05_mma_block_scale_vec_2_tmem_a_collector_a_lastuse));
+          // tcgen05.mma.cta_group::2.kind::mxf4nvf4.block_scale.scale_vec::2X.collector::a::lastuse [d_tmem], a_desc,
+          // b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::kind_mxf4nvf4_t,
+                                   cuda::ptx::cta_group_2_t,
+                                   uint32_t,
+                                   uint64_t,
+                                   uint64_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   bool)>(cuda::ptx::tcgen05_mma_block_scale_vec_2_tmem_a_collector_a_lastuse));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tcgen05.mma.cta_group::1.kind::mxf4nvf4.block_scale.scale_vec::4X.collector::a::lastuse [d_tmem], a_desc,
+        // b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(cuda::ptx::kind_mxf4nvf4_t,
+                               cuda::ptx::cta_group_1_t,
+                               uint32_t,
+                               uint64_t,
+                               uint64_t,
+                               uint32_t,
+                               uint32_t,
+                               uint32_t,
+                               bool)>(cuda::ptx::tcgen05_mma_block_scale_vec_4x_tmem_a_collector_a_lastuse));
+          // tcgen05.mma.cta_group::2.kind::mxf4nvf4.block_scale.scale_vec::4X.collector::a::lastuse [d_tmem], a_desc,
+          // b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::kind_mxf4nvf4_t,
+                                   cuda::ptx::cta_group_2_t,
+                                   uint32_t,
+                                   uint64_t,
+                                   uint64_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   bool)>(cuda::ptx::tcgen05_mma_block_scale_vec_4x_tmem_a_collector_a_lastuse));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // tcgen05.mma.cta_group::1.kind::mxf4nvf4.block_scale.scale_vec::4X.collector::a::lastuse [d_tmem], a_desc,
+        // b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(cuda::ptx::kind_mxf4nvf4_t,
+                               cuda::ptx::cta_group_1_t,
+                               uint32_t,
+                               uint64_t,
+                               uint64_t,
+                               uint32_t,
+                               uint32_t,
+                               uint32_t,
+                               bool)>(cuda::ptx::tcgen05_mma_block_scale_vec_4x_tmem_a_collector_a_lastuse));
+          // tcgen05.mma.cta_group::2.kind::mxf4nvf4.block_scale.scale_vec::4X.collector::a::lastuse [d_tmem], a_desc,
+          // b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::kind_mxf4nvf4_t,
+                                   cuda::ptx::cta_group_2_t,
+                                   uint32_t,
+                                   uint64_t,
+                                   uint64_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   bool)>(cuda::ptx::tcgen05_mma_block_scale_vec_4x_tmem_a_collector_a_lastuse));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tcgen05.mma.cta_group::1.kind::mxf8f6f4.block_scale.scale_vec::1X.collector::a::discard [d_tmem], a_desc,
+        // b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(cuda::ptx::kind_mxf8f6f4_t,
+                               cuda::ptx::cta_group_1_t,
+                               uint32_t,
+                               uint64_t,
+                               uint64_t,
+                               uint32_t,
+                               uint32_t,
+                               uint32_t,
+                               bool)>(cuda::ptx::tcgen05_mma_block_scale_vec_1x_collector_a_discard));
+          // tcgen05.mma.cta_group::2.kind::mxf8f6f4.block_scale.scale_vec::1X.collector::a::discard [d_tmem], a_desc,
+          // b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::kind_mxf8f6f4_t,
+                                   cuda::ptx::cta_group_2_t,
+                                   uint32_t,
+                                   uint64_t,
+                                   uint64_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   bool)>(cuda::ptx::tcgen05_mma_block_scale_vec_1x_collector_a_discard));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // tcgen05.mma.cta_group::1.kind::mxf8f6f4.block_scale.scale_vec::1X.collector::a::discard [d_tmem], a_desc,
+        // b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(cuda::ptx::kind_mxf8f6f4_t,
+                               cuda::ptx::cta_group_1_t,
+                               uint32_t,
+                               uint64_t,
+                               uint64_t,
+                               uint32_t,
+                               uint32_t,
+                               uint32_t,
+                               bool)>(cuda::ptx::tcgen05_mma_block_scale_vec_1x_collector_a_discard));
+          // tcgen05.mma.cta_group::2.kind::mxf8f6f4.block_scale.scale_vec::1X.collector::a::discard [d_tmem], a_desc,
+          // b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::kind_mxf8f6f4_t,
+                                   cuda::ptx::cta_group_2_t,
+                                   uint32_t,
+                                   uint64_t,
+                                   uint64_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   bool)>(cuda::ptx::tcgen05_mma_block_scale_vec_1x_collector_a_discard));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tcgen05.mma.cta_group::1.kind::mxf4.block_scale.scale_vec::2X.collector::a::discard [d_tmem], a_desc, b_desc,
+        // idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(cuda::ptx::kind_mxf4_t,
+                               cuda::ptx::cta_group_1_t,
+                               uint32_t,
+                               uint64_t,
+                               uint64_t,
+                               uint32_t,
+                               uint32_t,
+                               uint32_t,
+                               bool)>(cuda::ptx::tcgen05_mma_block_scale_vec_2x_collector_a_discard));
+          // tcgen05.mma.cta_group::2.kind::mxf4.block_scale.scale_vec::2X.collector::a::discard [d_tmem], a_desc,
+          // b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::kind_mxf4_t,
+                                   cuda::ptx::cta_group_2_t,
+                                   uint32_t,
+                                   uint64_t,
+                                   uint64_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   bool)>(cuda::ptx::tcgen05_mma_block_scale_vec_2x_collector_a_discard));
+          // tcgen05.mma.cta_group::1.kind::mxf4nvf4.block_scale.scale_vec::2X.collector::a::discard [d_tmem], a_desc,
+          // b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::kind_mxf4nvf4_t,
+                                   cuda::ptx::cta_group_1_t,
+                                   uint32_t,
+                                   uint64_t,
+                                   uint64_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   bool)>(cuda::ptx::tcgen05_mma_block_scale_vec_2x_collector_a_discard));
+          // tcgen05.mma.cta_group::2.kind::mxf4nvf4.block_scale.scale_vec::2X.collector::a::discard [d_tmem], a_desc,
+          // b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::kind_mxf4nvf4_t,
+                                   cuda::ptx::cta_group_2_t,
+                                   uint32_t,
+                                   uint64_t,
+                                   uint64_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   bool)>(cuda::ptx::tcgen05_mma_block_scale_vec_2x_collector_a_discard));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // tcgen05.mma.cta_group::1.kind::mxf4.block_scale.scale_vec::2X.collector::a::discard [d_tmem], a_desc, b_desc,
+        // idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(cuda::ptx::kind_mxf4_t,
+                               cuda::ptx::cta_group_1_t,
+                               uint32_t,
+                               uint64_t,
+                               uint64_t,
+                               uint32_t,
+                               uint32_t,
+                               uint32_t,
+                               bool)>(cuda::ptx::tcgen05_mma_block_scale_vec_2x_collector_a_discard));
+          // tcgen05.mma.cta_group::2.kind::mxf4.block_scale.scale_vec::2X.collector::a::discard [d_tmem], a_desc,
+          // b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::kind_mxf4_t,
+                                   cuda::ptx::cta_group_2_t,
+                                   uint32_t,
+                                   uint64_t,
+                                   uint64_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   bool)>(cuda::ptx::tcgen05_mma_block_scale_vec_2x_collector_a_discard));
+          // tcgen05.mma.cta_group::1.kind::mxf4nvf4.block_scale.scale_vec::2X.collector::a::discard [d_tmem], a_desc,
+          // b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::kind_mxf4nvf4_t,
+                                   cuda::ptx::cta_group_1_t,
+                                   uint32_t,
+                                   uint64_t,
+                                   uint64_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   bool)>(cuda::ptx::tcgen05_mma_block_scale_vec_2x_collector_a_discard));
+          // tcgen05.mma.cta_group::2.kind::mxf4nvf4.block_scale.scale_vec::2X.collector::a::discard [d_tmem], a_desc,
+          // b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::kind_mxf4nvf4_t,
+                                   cuda::ptx::cta_group_2_t,
+                                   uint32_t,
+                                   uint64_t,
+                                   uint64_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   bool)>(cuda::ptx::tcgen05_mma_block_scale_vec_2x_collector_a_discard));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tcgen05.mma.cta_group::1.kind::mxf4nvf4.block_scale.scale_vec::4X.collector::a::discard [d_tmem], a_desc,
+        // b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(cuda::ptx::kind_mxf4nvf4_t,
+                               cuda::ptx::cta_group_1_t,
+                               uint32_t,
+                               uint64_t,
+                               uint64_t,
+                               uint32_t,
+                               uint32_t,
+                               uint32_t,
+                               bool)>(cuda::ptx::tcgen05_mma_block_scale_vec_4x_collector_a_discard));
+          // tcgen05.mma.cta_group::2.kind::mxf4nvf4.block_scale.scale_vec::4X.collector::a::discard [d_tmem], a_desc,
+          // b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::kind_mxf4nvf4_t,
+                                   cuda::ptx::cta_group_2_t,
+                                   uint32_t,
+                                   uint64_t,
+                                   uint64_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   bool)>(cuda::ptx::tcgen05_mma_block_scale_vec_4x_collector_a_discard));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // tcgen05.mma.cta_group::1.kind::mxf4nvf4.block_scale.scale_vec::4X.collector::a::discard [d_tmem], a_desc,
+        // b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(cuda::ptx::kind_mxf4nvf4_t,
+                               cuda::ptx::cta_group_1_t,
+                               uint32_t,
+                               uint64_t,
+                               uint64_t,
+                               uint32_t,
+                               uint32_t,
+                               uint32_t,
+                               bool)>(cuda::ptx::tcgen05_mma_block_scale_vec_4x_collector_a_discard));
+          // tcgen05.mma.cta_group::2.kind::mxf4nvf4.block_scale.scale_vec::4X.collector::a::discard [d_tmem], a_desc,
+          // b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::kind_mxf4nvf4_t,
+                                   cuda::ptx::cta_group_2_t,
+                                   uint32_t,
+                                   uint64_t,
+                                   uint64_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   bool)>(cuda::ptx::tcgen05_mma_block_scale_vec_4x_collector_a_discard));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tcgen05.mma.cta_group::1.kind::mxf8f6f4.block_scale.scale_vec::1X.collector::a::discard [d_tmem], a_desc,
+        // b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(cuda::ptx::kind_mxf8f6f4_t,
+                               cuda::ptx::cta_group_1_t,
+                               uint32_t,
+                               uint64_t,
+                               uint64_t,
+                               uint32_t,
+                               uint32_t,
+                               uint32_t,
+                               bool)>(cuda::ptx::tcgen05_mma_block_scale_vec_1x_tmem_a_collector_a_discard));
+          // tcgen05.mma.cta_group::2.kind::mxf8f6f4.block_scale.scale_vec::1X.collector::a::discard [d_tmem], a_desc,
+          // b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::kind_mxf8f6f4_t,
+                                   cuda::ptx::cta_group_2_t,
+                                   uint32_t,
+                                   uint64_t,
+                                   uint64_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   bool)>(cuda::ptx::tcgen05_mma_block_scale_vec_1x_tmem_a_collector_a_discard));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // tcgen05.mma.cta_group::1.kind::mxf8f6f4.block_scale.scale_vec::1X.collector::a::discard [d_tmem], a_desc,
+        // b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(cuda::ptx::kind_mxf8f6f4_t,
+                               cuda::ptx::cta_group_1_t,
+                               uint32_t,
+                               uint64_t,
+                               uint64_t,
+                               uint32_t,
+                               uint32_t,
+                               uint32_t,
+                               bool)>(cuda::ptx::tcgen05_mma_block_scale_vec_1x_tmem_a_collector_a_discard));
+          // tcgen05.mma.cta_group::2.kind::mxf8f6f4.block_scale.scale_vec::1X.collector::a::discard [d_tmem], a_desc,
+          // b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::kind_mxf8f6f4_t,
+                                   cuda::ptx::cta_group_2_t,
+                                   uint32_t,
+                                   uint64_t,
+                                   uint64_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   bool)>(cuda::ptx::tcgen05_mma_block_scale_vec_1x_tmem_a_collector_a_discard));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tcgen05.mma.cta_group::1.kind::mxf4.block_scale.scale_vec::2X.collector::a::discard [d_tmem], a_desc, b_desc,
+        // idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(cuda::ptx::kind_mxf4_t,
+                               cuda::ptx::cta_group_1_t,
+                               uint32_t,
+                               uint64_t,
+                               uint64_t,
+                               uint32_t,
+                               uint32_t,
+                               uint32_t,
+                               bool)>(cuda::ptx::tcgen05_mma_block_scale_vec_2_tmem_a_collector_a_discard));
+          // tcgen05.mma.cta_group::2.kind::mxf4.block_scale.scale_vec::2X.collector::a::discard [d_tmem], a_desc,
+          // b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::kind_mxf4_t,
+                                   cuda::ptx::cta_group_2_t,
+                                   uint32_t,
+                                   uint64_t,
+                                   uint64_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   bool)>(cuda::ptx::tcgen05_mma_block_scale_vec_2_tmem_a_collector_a_discard));
+          // tcgen05.mma.cta_group::1.kind::mxf4nvf4.block_scale.scale_vec::2X.collector::a::discard [d_tmem], a_desc,
+          // b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::kind_mxf4nvf4_t,
+                                   cuda::ptx::cta_group_1_t,
+                                   uint32_t,
+                                   uint64_t,
+                                   uint64_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   bool)>(cuda::ptx::tcgen05_mma_block_scale_vec_2_tmem_a_collector_a_discard));
+          // tcgen05.mma.cta_group::2.kind::mxf4nvf4.block_scale.scale_vec::2X.collector::a::discard [d_tmem], a_desc,
+          // b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::kind_mxf4nvf4_t,
+                                   cuda::ptx::cta_group_2_t,
+                                   uint32_t,
+                                   uint64_t,
+                                   uint64_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   bool)>(cuda::ptx::tcgen05_mma_block_scale_vec_2_tmem_a_collector_a_discard));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // tcgen05.mma.cta_group::1.kind::mxf4.block_scale.scale_vec::2X.collector::a::discard [d_tmem], a_desc, b_desc,
+        // idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(cuda::ptx::kind_mxf4_t,
+                               cuda::ptx::cta_group_1_t,
+                               uint32_t,
+                               uint64_t,
+                               uint64_t,
+                               uint32_t,
+                               uint32_t,
+                               uint32_t,
+                               bool)>(cuda::ptx::tcgen05_mma_block_scale_vec_2_tmem_a_collector_a_discard));
+          // tcgen05.mma.cta_group::2.kind::mxf4.block_scale.scale_vec::2X.collector::a::discard [d_tmem], a_desc,
+          // b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::kind_mxf4_t,
+                                   cuda::ptx::cta_group_2_t,
+                                   uint32_t,
+                                   uint64_t,
+                                   uint64_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   bool)>(cuda::ptx::tcgen05_mma_block_scale_vec_2_tmem_a_collector_a_discard));
+          // tcgen05.mma.cta_group::1.kind::mxf4nvf4.block_scale.scale_vec::2X.collector::a::discard [d_tmem], a_desc,
+          // b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::kind_mxf4nvf4_t,
+                                   cuda::ptx::cta_group_1_t,
+                                   uint32_t,
+                                   uint64_t,
+                                   uint64_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   bool)>(cuda::ptx::tcgen05_mma_block_scale_vec_2_tmem_a_collector_a_discard));
+          // tcgen05.mma.cta_group::2.kind::mxf4nvf4.block_scale.scale_vec::2X.collector::a::discard [d_tmem], a_desc,
+          // b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::kind_mxf4nvf4_t,
+                                   cuda::ptx::cta_group_2_t,
+                                   uint32_t,
+                                   uint64_t,
+                                   uint64_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   bool)>(cuda::ptx::tcgen05_mma_block_scale_vec_2_tmem_a_collector_a_discard));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tcgen05.mma.cta_group::1.kind::mxf4nvf4.block_scale.scale_vec::4X.collector::a::discard [d_tmem], a_desc,
+        // b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(cuda::ptx::kind_mxf4nvf4_t,
+                               cuda::ptx::cta_group_1_t,
+                               uint32_t,
+                               uint64_t,
+                               uint64_t,
+                               uint32_t,
+                               uint32_t,
+                               uint32_t,
+                               bool)>(cuda::ptx::tcgen05_mma_block_scale_vec_4x_tmem_a_collector_a_discard));
+          // tcgen05.mma.cta_group::2.kind::mxf4nvf4.block_scale.scale_vec::4X.collector::a::discard [d_tmem], a_desc,
+          // b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::kind_mxf4nvf4_t,
+                                   cuda::ptx::cta_group_2_t,
+                                   uint32_t,
+                                   uint64_t,
+                                   uint64_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   bool)>(cuda::ptx::tcgen05_mma_block_scale_vec_4x_tmem_a_collector_a_discard));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // tcgen05.mma.cta_group::1.kind::mxf4nvf4.block_scale.scale_vec::4X.collector::a::discard [d_tmem], a_desc,
+        // b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(cuda::ptx::kind_mxf4nvf4_t,
+                               cuda::ptx::cta_group_1_t,
+                               uint32_t,
+                               uint64_t,
+                               uint64_t,
+                               uint32_t,
+                               uint32_t,
+                               uint32_t,
+                               bool)>(cuda::ptx::tcgen05_mma_block_scale_vec_4x_tmem_a_collector_a_discard));
+          // tcgen05.mma.cta_group::2.kind::mxf4nvf4.block_scale.scale_vec::4X.collector::a::discard [d_tmem], a_desc,
+          // b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::kind_mxf4nvf4_t,
+                                   cuda::ptx::cta_group_2_t,
+                                   uint32_t,
+                                   uint64_t,
+                                   uint64_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   uint32_t,
+                                   bool)>(cuda::ptx::tcgen05_mma_block_scale_vec_4x_tmem_a_collector_a_discard));));
+#endif // __cccl_ptx_isa >= 860
+}
diff --git a/libcudacxx/test/libcudacxx/cuda/ptx/generated/tcgen05_mma_ws.h b/libcudacxx/test/libcudacxx/cuda/ptx/generated/tcgen05_mma_ws.h
new file mode 100644
index 00000000000..7e1674f39fc
--- /dev/null
+++ b/libcudacxx/test/libcudacxx/cuda/ptx/generated/tcgen05_mma_ws.h
@@ -0,0 +1,3570 @@
+// This file was automatically generated. Do not edit.
+
+// We use a special strategy to force the generation of the PTX. This is mainly
+// a fight against dead-code-elimination in the NVVM layer.
+//
+// The reason we need this strategy is because certain older versions of ptxas
+// segfault when a non-sensical sequence of PTX is generated. So instead, we try
+// to force the instantiation and compilation to PTX of all the overloads of the
+// PTX wrapping functions.
+//
+// We do this by writing a function pointer of each overload to the kernel
+// parameter `fn_ptr`.
+//
+// Because `fn_ptr` is possibly visible outside this translation unit, the
+// compiler must compile all the functions which are stored.
+
+__global__ void test_tcgen05_mma_ws(void** fn_ptr)
+{
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tcgen05.mma.ws.cta_group::1.kind::f16.collector::b0::fill [d_tmem], a_desc, b_desc, idesc, enable_input_d,
+        // zero_column_mask_desc;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(
+            cuda::ptx::cta_group_1_t, cuda::ptx::kind_f16_t, uint32_t, uint64_t, uint64_t, uint32_t, bool, uint64_t)>(
+            cuda::ptx::tcgen05_mma_ws_collector_b0_fill));
+          // tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b0::fill [d_tmem], a_desc, b_desc, idesc,
+          // enable_input_d, zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_tf32_t, uint32_t, uint64_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b0_fill));
+          // tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b0::fill [d_tmem], a_desc, b_desc, idesc,
+          // enable_input_d, zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_f8f6f4_t, uint32_t, uint64_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b0_fill));
+          // tcgen05.mma.ws.cta_group::1.kind::i8.collector::b0::fill [d_tmem], a_desc, b_desc, idesc, enable_input_d,
+          // zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_i8_t, uint32_t, uint64_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b0_fill));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // tcgen05.mma.ws.cta_group::1.kind::f16.collector::b0::fill [d_tmem], a_desc, b_desc, idesc, enable_input_d,
+        // zero_column_mask_desc;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(
+            cuda::ptx::cta_group_1_t, cuda::ptx::kind_f16_t, uint32_t, uint64_t, uint64_t, uint32_t, bool, uint64_t)>(
+            cuda::ptx::tcgen05_mma_ws_collector_b0_fill));
+          // tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b0::fill [d_tmem], a_desc, b_desc, idesc,
+          // enable_input_d, zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_tf32_t, uint32_t, uint64_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b0_fill));
+          // tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b0::fill [d_tmem], a_desc, b_desc, idesc,
+          // enable_input_d, zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_f8f6f4_t, uint32_t, uint64_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b0_fill));
+          // tcgen05.mma.ws.cta_group::1.kind::i8.collector::b0::fill [d_tmem], a_desc, b_desc, idesc, enable_input_d,
+          // zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_i8_t, uint32_t, uint64_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b0_fill));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tcgen05.mma.ws.cta_group::1.kind::f16.collector::b0::fill [d_tmem], a_desc, b_desc, idesc, enable_input_d;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(
+            cuda::ptx::cta_group_1_t, cuda::ptx::kind_f16_t, uint32_t, uint64_t, uint64_t, uint32_t, bool)>(
+            cuda::ptx::tcgen05_mma_ws_collector_b0_fill));
+          // tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b0::fill [d_tmem], a_desc, b_desc, idesc, enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_tf32_t, uint32_t, uint64_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b0_fill));
+          // tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b0::fill [d_tmem], a_desc, b_desc, idesc,
+          // enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_f8f6f4_t, uint32_t, uint64_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b0_fill));
+          // tcgen05.mma.ws.cta_group::1.kind::i8.collector::b0::fill [d_tmem], a_desc, b_desc, idesc, enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_i8_t, uint32_t, uint64_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b0_fill));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // tcgen05.mma.ws.cta_group::1.kind::f16.collector::b0::fill [d_tmem], a_desc, b_desc, idesc, enable_input_d;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(
+            cuda::ptx::cta_group_1_t, cuda::ptx::kind_f16_t, uint32_t, uint64_t, uint64_t, uint32_t, bool)>(
+            cuda::ptx::tcgen05_mma_ws_collector_b0_fill));
+          // tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b0::fill [d_tmem], a_desc, b_desc, idesc, enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_tf32_t, uint32_t, uint64_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b0_fill));
+          // tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b0::fill [d_tmem], a_desc, b_desc, idesc,
+          // enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_f8f6f4_t, uint32_t, uint64_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b0_fill));
+          // tcgen05.mma.ws.cta_group::1.kind::i8.collector::b0::fill [d_tmem], a_desc, b_desc, idesc, enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_i8_t, uint32_t, uint64_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b0_fill));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tcgen05.mma.ws.cta_group::1.kind::f16.collector::b0::fill [d_tmem], [a_tmem], b_desc, idesc, enable_input_d,
+        // zero_column_mask_desc;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(
+            cuda::ptx::cta_group_1_t, cuda::ptx::kind_f16_t, uint32_t, uint32_t, uint64_t, uint32_t, bool, uint64_t)>(
+            cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b0_fill));
+          // tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b0::fill [d_tmem], [a_tmem], b_desc, idesc,
+          // enable_input_d, zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_tf32_t, uint32_t, uint32_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b0_fill));
+          // tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b0::fill [d_tmem], [a_tmem], b_desc, idesc,
+          // enable_input_d, zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_f8f6f4_t, uint32_t, uint32_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b0_fill));
+          // tcgen05.mma.ws.cta_group::1.kind::i8.collector::b0::fill [d_tmem], [a_tmem], b_desc, idesc,
+          // enable_input_d, zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_i8_t, uint32_t, uint32_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b0_fill));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // tcgen05.mma.ws.cta_group::1.kind::f16.collector::b0::fill [d_tmem], [a_tmem], b_desc, idesc, enable_input_d,
+        // zero_column_mask_desc;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(
+            cuda::ptx::cta_group_1_t, cuda::ptx::kind_f16_t, uint32_t, uint32_t, uint64_t, uint32_t, bool, uint64_t)>(
+            cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b0_fill));
+          // tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b0::fill [d_tmem], [a_tmem], b_desc, idesc,
+          // enable_input_d, zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_tf32_t, uint32_t, uint32_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b0_fill));
+          // tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b0::fill [d_tmem], [a_tmem], b_desc, idesc,
+          // enable_input_d, zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_f8f6f4_t, uint32_t, uint32_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b0_fill));
+          // tcgen05.mma.ws.cta_group::1.kind::i8.collector::b0::fill [d_tmem], [a_tmem], b_desc, idesc,
+          // enable_input_d, zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_i8_t, uint32_t, uint32_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b0_fill));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tcgen05.mma.ws.cta_group::1.kind::f16.collector::b0::fill [d_tmem], [a_tmem], b_desc, idesc, enable_input_d;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(
+            cuda::ptx::cta_group_1_t, cuda::ptx::kind_f16_t, uint32_t, uint32_t, uint64_t, uint32_t, bool)>(
+            cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b0_fill));
+          // tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b0::fill [d_tmem], [a_tmem], b_desc, idesc,
+          // enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_tf32_t, uint32_t, uint32_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b0_fill));
+          // tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b0::fill [d_tmem], [a_tmem], b_desc, idesc,
+          // enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_f8f6f4_t, uint32_t, uint32_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b0_fill));
+          // tcgen05.mma.ws.cta_group::1.kind::i8.collector::b0::fill [d_tmem], [a_tmem], b_desc, idesc, enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_i8_t, uint32_t, uint32_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b0_fill));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // tcgen05.mma.ws.cta_group::1.kind::f16.collector::b0::fill [d_tmem], [a_tmem], b_desc, idesc, enable_input_d;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(
+            cuda::ptx::cta_group_1_t, cuda::ptx::kind_f16_t, uint32_t, uint32_t, uint64_t, uint32_t, bool)>(
+            cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b0_fill));
+          // tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b0::fill [d_tmem], [a_tmem], b_desc, idesc,
+          // enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_tf32_t, uint32_t, uint32_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b0_fill));
+          // tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b0::fill [d_tmem], [a_tmem], b_desc, idesc,
+          // enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_f8f6f4_t, uint32_t, uint32_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b0_fill));
+          // tcgen05.mma.ws.cta_group::1.kind::i8.collector::b0::fill [d_tmem], [a_tmem], b_desc, idesc, enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_i8_t, uint32_t, uint32_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b0_fill));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tcgen05.mma.ws.cta_group::1.kind::f16.collector::b0::use [d_tmem], a_desc, b_desc, idesc, enable_input_d,
+        // zero_column_mask_desc;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(
+            cuda::ptx::cta_group_1_t, cuda::ptx::kind_f16_t, uint32_t, uint64_t, uint64_t, uint32_t, bool, uint64_t)>(
+            cuda::ptx::tcgen05_mma_ws_collector_b0_use));
+          // tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b0::use [d_tmem], a_desc, b_desc, idesc,
+          // enable_input_d, zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_tf32_t, uint32_t, uint64_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b0_use));
+          // tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b0::use [d_tmem], a_desc, b_desc, idesc,
+          // enable_input_d, zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_f8f6f4_t, uint32_t, uint64_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b0_use));
+          // tcgen05.mma.ws.cta_group::1.kind::i8.collector::b0::use [d_tmem], a_desc, b_desc, idesc, enable_input_d,
+          // zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_i8_t, uint32_t, uint64_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b0_use));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // tcgen05.mma.ws.cta_group::1.kind::f16.collector::b0::use [d_tmem], a_desc, b_desc, idesc, enable_input_d,
+        // zero_column_mask_desc;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(
+            cuda::ptx::cta_group_1_t, cuda::ptx::kind_f16_t, uint32_t, uint64_t, uint64_t, uint32_t, bool, uint64_t)>(
+            cuda::ptx::tcgen05_mma_ws_collector_b0_use));
+          // tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b0::use [d_tmem], a_desc, b_desc, idesc,
+          // enable_input_d, zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_tf32_t, uint32_t, uint64_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b0_use));
+          // tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b0::use [d_tmem], a_desc, b_desc, idesc,
+          // enable_input_d, zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_f8f6f4_t, uint32_t, uint64_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b0_use));
+          // tcgen05.mma.ws.cta_group::1.kind::i8.collector::b0::use [d_tmem], a_desc, b_desc, idesc, enable_input_d,
+          // zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_i8_t, uint32_t, uint64_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b0_use));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tcgen05.mma.ws.cta_group::1.kind::f16.collector::b0::use [d_tmem], a_desc, b_desc, idesc, enable_input_d;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(
+            cuda::ptx::cta_group_1_t, cuda::ptx::kind_f16_t, uint32_t, uint64_t, uint64_t, uint32_t, bool)>(
+            cuda::ptx::tcgen05_mma_ws_collector_b0_use));
+          // tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b0::use [d_tmem], a_desc, b_desc, idesc, enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_tf32_t, uint32_t, uint64_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b0_use));
+          // tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b0::use [d_tmem], a_desc, b_desc, idesc,
+          // enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_f8f6f4_t, uint32_t, uint64_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b0_use));
+          // tcgen05.mma.ws.cta_group::1.kind::i8.collector::b0::use [d_tmem], a_desc, b_desc, idesc, enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_i8_t, uint32_t, uint64_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b0_use));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // tcgen05.mma.ws.cta_group::1.kind::f16.collector::b0::use [d_tmem], a_desc, b_desc, idesc, enable_input_d;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(
+            cuda::ptx::cta_group_1_t, cuda::ptx::kind_f16_t, uint32_t, uint64_t, uint64_t, uint32_t, bool)>(
+            cuda::ptx::tcgen05_mma_ws_collector_b0_use));
+          // tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b0::use [d_tmem], a_desc, b_desc, idesc, enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_tf32_t, uint32_t, uint64_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b0_use));
+          // tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b0::use [d_tmem], a_desc, b_desc, idesc,
+          // enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_f8f6f4_t, uint32_t, uint64_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b0_use));
+          // tcgen05.mma.ws.cta_group::1.kind::i8.collector::b0::use [d_tmem], a_desc, b_desc, idesc, enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_i8_t, uint32_t, uint64_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b0_use));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tcgen05.mma.ws.cta_group::1.kind::f16.collector::b0::use [d_tmem], [a_tmem], b_desc, idesc, enable_input_d,
+        // zero_column_mask_desc;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(
+            cuda::ptx::cta_group_1_t, cuda::ptx::kind_f16_t, uint32_t, uint32_t, uint64_t, uint32_t, bool, uint64_t)>(
+            cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b0_use));
+          // tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b0::use [d_tmem], [a_tmem], b_desc, idesc,
+          // enable_input_d, zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_tf32_t, uint32_t, uint32_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b0_use));
+          // tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b0::use [d_tmem], [a_tmem], b_desc, idesc,
+          // enable_input_d, zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_f8f6f4_t, uint32_t, uint32_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b0_use));
+          // tcgen05.mma.ws.cta_group::1.kind::i8.collector::b0::use [d_tmem], [a_tmem], b_desc, idesc,
+          // enable_input_d, zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_i8_t, uint32_t, uint32_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b0_use));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // tcgen05.mma.ws.cta_group::1.kind::f16.collector::b0::use [d_tmem], [a_tmem], b_desc, idesc, enable_input_d,
+        // zero_column_mask_desc;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(
+            cuda::ptx::cta_group_1_t, cuda::ptx::kind_f16_t, uint32_t, uint32_t, uint64_t, uint32_t, bool, uint64_t)>(
+            cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b0_use));
+          // tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b0::use [d_tmem], [a_tmem], b_desc, idesc,
+          // enable_input_d, zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_tf32_t, uint32_t, uint32_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b0_use));
+          // tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b0::use [d_tmem], [a_tmem], b_desc, idesc,
+          // enable_input_d, zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_f8f6f4_t, uint32_t, uint32_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b0_use));
+          // tcgen05.mma.ws.cta_group::1.kind::i8.collector::b0::use [d_tmem], [a_tmem], b_desc, idesc,
+          // enable_input_d, zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_i8_t, uint32_t, uint32_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b0_use));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tcgen05.mma.ws.cta_group::1.kind::f16.collector::b0::use [d_tmem], [a_tmem], b_desc, idesc, enable_input_d;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(
+            cuda::ptx::cta_group_1_t, cuda::ptx::kind_f16_t, uint32_t, uint32_t, uint64_t, uint32_t, bool)>(
+            cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b0_use));
+          // tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b0::use [d_tmem], [a_tmem], b_desc, idesc,
+          // enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_tf32_t, uint32_t, uint32_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b0_use));
+          // tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b0::use [d_tmem], [a_tmem], b_desc, idesc,
+          // enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_f8f6f4_t, uint32_t, uint32_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b0_use));
+          // tcgen05.mma.ws.cta_group::1.kind::i8.collector::b0::use [d_tmem], [a_tmem], b_desc, idesc, enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_i8_t, uint32_t, uint32_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b0_use));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // tcgen05.mma.ws.cta_group::1.kind::f16.collector::b0::use [d_tmem], [a_tmem], b_desc, idesc, enable_input_d;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(
+            cuda::ptx::cta_group_1_t, cuda::ptx::kind_f16_t, uint32_t, uint32_t, uint64_t, uint32_t, bool)>(
+            cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b0_use));
+          // tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b0::use [d_tmem], [a_tmem], b_desc, idesc,
+          // enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_tf32_t, uint32_t, uint32_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b0_use));
+          // tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b0::use [d_tmem], [a_tmem], b_desc, idesc,
+          // enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_f8f6f4_t, uint32_t, uint32_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b0_use));
+          // tcgen05.mma.ws.cta_group::1.kind::i8.collector::b0::use [d_tmem], [a_tmem], b_desc, idesc, enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_i8_t, uint32_t, uint32_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b0_use));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tcgen05.mma.ws.cta_group::1.kind::f16.collector::b0::lastuse [d_tmem], a_desc, b_desc, idesc, enable_input_d,
+        // zero_column_mask_desc;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(
+            cuda::ptx::cta_group_1_t, cuda::ptx::kind_f16_t, uint32_t, uint64_t, uint64_t, uint32_t, bool, uint64_t)>(
+            cuda::ptx::tcgen05_mma_ws_collector_b0_lastuse));
+          // tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b0::lastuse [d_tmem], a_desc, b_desc, idesc,
+          // enable_input_d, zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_tf32_t, uint32_t, uint64_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b0_lastuse));
+          // tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b0::lastuse [d_tmem], a_desc, b_desc, idesc,
+          // enable_input_d, zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_f8f6f4_t, uint32_t, uint64_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b0_lastuse));
+          // tcgen05.mma.ws.cta_group::1.kind::i8.collector::b0::lastuse [d_tmem], a_desc, b_desc, idesc,
+          // enable_input_d, zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_i8_t, uint32_t, uint64_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b0_lastuse));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // tcgen05.mma.ws.cta_group::1.kind::f16.collector::b0::lastuse [d_tmem], a_desc, b_desc, idesc, enable_input_d,
+        // zero_column_mask_desc;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(
+            cuda::ptx::cta_group_1_t, cuda::ptx::kind_f16_t, uint32_t, uint64_t, uint64_t, uint32_t, bool, uint64_t)>(
+            cuda::ptx::tcgen05_mma_ws_collector_b0_lastuse));
+          // tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b0::lastuse [d_tmem], a_desc, b_desc, idesc,
+          // enable_input_d, zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_tf32_t, uint32_t, uint64_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b0_lastuse));
+          // tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b0::lastuse [d_tmem], a_desc, b_desc, idesc,
+          // enable_input_d, zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_f8f6f4_t, uint32_t, uint64_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b0_lastuse));
+          // tcgen05.mma.ws.cta_group::1.kind::i8.collector::b0::lastuse [d_tmem], a_desc, b_desc, idesc,
+          // enable_input_d, zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_i8_t, uint32_t, uint64_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b0_lastuse));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tcgen05.mma.ws.cta_group::1.kind::f16.collector::b0::lastuse [d_tmem], a_desc, b_desc, idesc, enable_input_d;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(
+            cuda::ptx::cta_group_1_t, cuda::ptx::kind_f16_t, uint32_t, uint64_t, uint64_t, uint32_t, bool)>(
+            cuda::ptx::tcgen05_mma_ws_collector_b0_lastuse));
+          // tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b0::lastuse [d_tmem], a_desc, b_desc, idesc,
+          // enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_tf32_t, uint32_t, uint64_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b0_lastuse));
+          // tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b0::lastuse [d_tmem], a_desc, b_desc, idesc,
+          // enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_f8f6f4_t, uint32_t, uint64_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b0_lastuse));
+          // tcgen05.mma.ws.cta_group::1.kind::i8.collector::b0::lastuse [d_tmem], a_desc, b_desc, idesc,
+          // enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_i8_t, uint32_t, uint64_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b0_lastuse));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // tcgen05.mma.ws.cta_group::1.kind::f16.collector::b0::lastuse [d_tmem], a_desc, b_desc, idesc, enable_input_d;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(
+            cuda::ptx::cta_group_1_t, cuda::ptx::kind_f16_t, uint32_t, uint64_t, uint64_t, uint32_t, bool)>(
+            cuda::ptx::tcgen05_mma_ws_collector_b0_lastuse));
+          // tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b0::lastuse [d_tmem], a_desc, b_desc, idesc,
+          // enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_tf32_t, uint32_t, uint64_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b0_lastuse));
+          // tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b0::lastuse [d_tmem], a_desc, b_desc, idesc,
+          // enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_f8f6f4_t, uint32_t, uint64_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b0_lastuse));
+          // tcgen05.mma.ws.cta_group::1.kind::i8.collector::b0::lastuse [d_tmem], a_desc, b_desc, idesc,
+          // enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_i8_t, uint32_t, uint64_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b0_lastuse));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tcgen05.mma.ws.cta_group::1.kind::f16.collector::b0::lastuse [d_tmem], [a_tmem], b_desc, idesc,
+        // enable_input_d, zero_column_mask_desc;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(
+            cuda::ptx::cta_group_1_t, cuda::ptx::kind_f16_t, uint32_t, uint32_t, uint64_t, uint32_t, bool, uint64_t)>(
+            cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b0_lastuse));
+          // tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b0::lastuse [d_tmem], [a_tmem], b_desc, idesc,
+          // enable_input_d, zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_tf32_t, uint32_t, uint32_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b0_lastuse));
+          // tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b0::lastuse [d_tmem], [a_tmem], b_desc, idesc,
+          // enable_input_d, zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_f8f6f4_t, uint32_t, uint32_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b0_lastuse));
+          // tcgen05.mma.ws.cta_group::1.kind::i8.collector::b0::lastuse [d_tmem], [a_tmem], b_desc, idesc,
+          // enable_input_d, zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_i8_t, uint32_t, uint32_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b0_lastuse));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // tcgen05.mma.ws.cta_group::1.kind::f16.collector::b0::lastuse [d_tmem], [a_tmem], b_desc, idesc,
+        // enable_input_d, zero_column_mask_desc;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(
+            cuda::ptx::cta_group_1_t, cuda::ptx::kind_f16_t, uint32_t, uint32_t, uint64_t, uint32_t, bool, uint64_t)>(
+            cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b0_lastuse));
+          // tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b0::lastuse [d_tmem], [a_tmem], b_desc, idesc,
+          // enable_input_d, zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_tf32_t, uint32_t, uint32_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b0_lastuse));
+          // tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b0::lastuse [d_tmem], [a_tmem], b_desc, idesc,
+          // enable_input_d, zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_f8f6f4_t, uint32_t, uint32_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b0_lastuse));
+          // tcgen05.mma.ws.cta_group::1.kind::i8.collector::b0::lastuse [d_tmem], [a_tmem], b_desc, idesc,
+          // enable_input_d, zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_i8_t, uint32_t, uint32_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b0_lastuse));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tcgen05.mma.ws.cta_group::1.kind::f16.collector::b0::lastuse [d_tmem], [a_tmem], b_desc, idesc,
+        // enable_input_d;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(
+            cuda::ptx::cta_group_1_t, cuda::ptx::kind_f16_t, uint32_t, uint32_t, uint64_t, uint32_t, bool)>(
+            cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b0_lastuse));
+          // tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b0::lastuse [d_tmem], [a_tmem], b_desc, idesc,
+          // enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_tf32_t, uint32_t, uint32_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b0_lastuse));
+          // tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b0::lastuse [d_tmem], [a_tmem], b_desc, idesc,
+          // enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_f8f6f4_t, uint32_t, uint32_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b0_lastuse));
+          // tcgen05.mma.ws.cta_group::1.kind::i8.collector::b0::lastuse [d_tmem], [a_tmem], b_desc, idesc,
+          // enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_i8_t, uint32_t, uint32_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b0_lastuse));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // tcgen05.mma.ws.cta_group::1.kind::f16.collector::b0::lastuse [d_tmem], [a_tmem], b_desc, idesc,
+        // enable_input_d;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(
+            cuda::ptx::cta_group_1_t, cuda::ptx::kind_f16_t, uint32_t, uint32_t, uint64_t, uint32_t, bool)>(
+            cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b0_lastuse));
+          // tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b0::lastuse [d_tmem], [a_tmem], b_desc, idesc,
+          // enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_tf32_t, uint32_t, uint32_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b0_lastuse));
+          // tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b0::lastuse [d_tmem], [a_tmem], b_desc, idesc,
+          // enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_f8f6f4_t, uint32_t, uint32_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b0_lastuse));
+          // tcgen05.mma.ws.cta_group::1.kind::i8.collector::b0::lastuse [d_tmem], [a_tmem], b_desc, idesc,
+          // enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_i8_t, uint32_t, uint32_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b0_lastuse));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tcgen05.mma.ws.cta_group::1.kind::f16.collector::b0::discard [d_tmem], a_desc, b_desc, idesc, enable_input_d,
+        // zero_column_mask_desc;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(
+            cuda::ptx::cta_group_1_t, cuda::ptx::kind_f16_t, uint32_t, uint64_t, uint64_t, uint32_t, bool, uint64_t)>(
+            cuda::ptx::tcgen05_mma_ws_collector_b0_discard));
+          // tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b0::discard [d_tmem], a_desc, b_desc, idesc,
+          // enable_input_d, zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_tf32_t, uint32_t, uint64_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b0_discard));
+          // tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b0::discard [d_tmem], a_desc, b_desc, idesc,
+          // enable_input_d, zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_f8f6f4_t, uint32_t, uint64_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b0_discard));
+          // tcgen05.mma.ws.cta_group::1.kind::i8.collector::b0::discard [d_tmem], a_desc, b_desc, idesc,
+          // enable_input_d, zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_i8_t, uint32_t, uint64_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b0_discard));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // tcgen05.mma.ws.cta_group::1.kind::f16.collector::b0::discard [d_tmem], a_desc, b_desc, idesc, enable_input_d,
+        // zero_column_mask_desc;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(
+            cuda::ptx::cta_group_1_t, cuda::ptx::kind_f16_t, uint32_t, uint64_t, uint64_t, uint32_t, bool, uint64_t)>(
+            cuda::ptx::tcgen05_mma_ws_collector_b0_discard));
+          // tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b0::discard [d_tmem], a_desc, b_desc, idesc,
+          // enable_input_d, zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_tf32_t, uint32_t, uint64_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b0_discard));
+          // tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b0::discard [d_tmem], a_desc, b_desc, idesc,
+          // enable_input_d, zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_f8f6f4_t, uint32_t, uint64_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b0_discard));
+          // tcgen05.mma.ws.cta_group::1.kind::i8.collector::b0::discard [d_tmem], a_desc, b_desc, idesc,
+          // enable_input_d, zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_i8_t, uint32_t, uint64_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b0_discard));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tcgen05.mma.ws.cta_group::1.kind::f16.collector::b0::discard [d_tmem], a_desc, b_desc, idesc, enable_input_d;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(
+            cuda::ptx::cta_group_1_t, cuda::ptx::kind_f16_t, uint32_t, uint64_t, uint64_t, uint32_t, bool)>(
+            cuda::ptx::tcgen05_mma_ws_collector_b0_discard));
+          // tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b0::discard [d_tmem], a_desc, b_desc, idesc,
+          // enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_tf32_t, uint32_t, uint64_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b0_discard));
+          // tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b0::discard [d_tmem], a_desc, b_desc, idesc,
+          // enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_f8f6f4_t, uint32_t, uint64_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b0_discard));
+          // tcgen05.mma.ws.cta_group::1.kind::i8.collector::b0::discard [d_tmem], a_desc, b_desc, idesc,
+          // enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_i8_t, uint32_t, uint64_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b0_discard));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // tcgen05.mma.ws.cta_group::1.kind::f16.collector::b0::discard [d_tmem], a_desc, b_desc, idesc, enable_input_d;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(
+            cuda::ptx::cta_group_1_t, cuda::ptx::kind_f16_t, uint32_t, uint64_t, uint64_t, uint32_t, bool)>(
+            cuda::ptx::tcgen05_mma_ws_collector_b0_discard));
+          // tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b0::discard [d_tmem], a_desc, b_desc, idesc,
+          // enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_tf32_t, uint32_t, uint64_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b0_discard));
+          // tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b0::discard [d_tmem], a_desc, b_desc, idesc,
+          // enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_f8f6f4_t, uint32_t, uint64_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b0_discard));
+          // tcgen05.mma.ws.cta_group::1.kind::i8.collector::b0::discard [d_tmem], a_desc, b_desc, idesc,
+          // enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_i8_t, uint32_t, uint64_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b0_discard));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tcgen05.mma.ws.cta_group::1.kind::f16.collector::b0::discard [d_tmem], [a_tmem], b_desc, idesc,
+        // enable_input_d, zero_column_mask_desc;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(
+            cuda::ptx::cta_group_1_t, cuda::ptx::kind_f16_t, uint32_t, uint32_t, uint64_t, uint32_t, bool, uint64_t)>(
+            cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b0_discard));
+          // tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b0::discard [d_tmem], [a_tmem], b_desc, idesc,
+          // enable_input_d, zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_tf32_t, uint32_t, uint32_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b0_discard));
+          // tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b0::discard [d_tmem], [a_tmem], b_desc, idesc,
+          // enable_input_d, zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_f8f6f4_t, uint32_t, uint32_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b0_discard));
+          // tcgen05.mma.ws.cta_group::1.kind::i8.collector::b0::discard [d_tmem], [a_tmem], b_desc, idesc,
+          // enable_input_d, zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_i8_t, uint32_t, uint32_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b0_discard));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // tcgen05.mma.ws.cta_group::1.kind::f16.collector::b0::discard [d_tmem], [a_tmem], b_desc, idesc,
+        // enable_input_d, zero_column_mask_desc;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(
+            cuda::ptx::cta_group_1_t, cuda::ptx::kind_f16_t, uint32_t, uint32_t, uint64_t, uint32_t, bool, uint64_t)>(
+            cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b0_discard));
+          // tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b0::discard [d_tmem], [a_tmem], b_desc, idesc,
+          // enable_input_d, zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_tf32_t, uint32_t, uint32_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b0_discard));
+          // tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b0::discard [d_tmem], [a_tmem], b_desc, idesc,
+          // enable_input_d, zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_f8f6f4_t, uint32_t, uint32_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b0_discard));
+          // tcgen05.mma.ws.cta_group::1.kind::i8.collector::b0::discard [d_tmem], [a_tmem], b_desc, idesc,
+          // enable_input_d, zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_i8_t, uint32_t, uint32_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b0_discard));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tcgen05.mma.ws.cta_group::1.kind::f16.collector::b0::discard [d_tmem], [a_tmem], b_desc, idesc,
+        // enable_input_d;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(
+            cuda::ptx::cta_group_1_t, cuda::ptx::kind_f16_t, uint32_t, uint32_t, uint64_t, uint32_t, bool)>(
+            cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b0_discard));
+          // tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b0::discard [d_tmem], [a_tmem], b_desc, idesc,
+          // enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_tf32_t, uint32_t, uint32_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b0_discard));
+          // tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b0::discard [d_tmem], [a_tmem], b_desc, idesc,
+          // enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_f8f6f4_t, uint32_t, uint32_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b0_discard));
+          // tcgen05.mma.ws.cta_group::1.kind::i8.collector::b0::discard [d_tmem], [a_tmem], b_desc, idesc,
+          // enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_i8_t, uint32_t, uint32_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b0_discard));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // tcgen05.mma.ws.cta_group::1.kind::f16.collector::b0::discard [d_tmem], [a_tmem], b_desc, idesc,
+        // enable_input_d;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(
+            cuda::ptx::cta_group_1_t, cuda::ptx::kind_f16_t, uint32_t, uint32_t, uint64_t, uint32_t, bool)>(
+            cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b0_discard));
+          // tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b0::discard [d_tmem], [a_tmem], b_desc, idesc,
+          // enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_tf32_t, uint32_t, uint32_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b0_discard));
+          // tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b0::discard [d_tmem], [a_tmem], b_desc, idesc,
+          // enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_f8f6f4_t, uint32_t, uint32_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b0_discard));
+          // tcgen05.mma.ws.cta_group::1.kind::i8.collector::b0::discard [d_tmem], [a_tmem], b_desc, idesc,
+          // enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_i8_t, uint32_t, uint32_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b0_discard));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tcgen05.mma.ws.cta_group::1.kind::f16.collector::b1::fill [d_tmem], a_desc, b_desc, idesc, enable_input_d,
+        // zero_column_mask_desc;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(
+            cuda::ptx::cta_group_1_t, cuda::ptx::kind_f16_t, uint32_t, uint64_t, uint64_t, uint32_t, bool, uint64_t)>(
+            cuda::ptx::tcgen05_mma_ws_collector_b1_fill));
+          // tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b1::fill [d_tmem], a_desc, b_desc, idesc,
+          // enable_input_d, zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_tf32_t, uint32_t, uint64_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b1_fill));
+          // tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b1::fill [d_tmem], a_desc, b_desc, idesc,
+          // enable_input_d, zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_f8f6f4_t, uint32_t, uint64_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b1_fill));
+          // tcgen05.mma.ws.cta_group::1.kind::i8.collector::b1::fill [d_tmem], a_desc, b_desc, idesc, enable_input_d,
+          // zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_i8_t, uint32_t, uint64_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b1_fill));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // tcgen05.mma.ws.cta_group::1.kind::f16.collector::b1::fill [d_tmem], a_desc, b_desc, idesc, enable_input_d,
+        // zero_column_mask_desc;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(
+            cuda::ptx::cta_group_1_t, cuda::ptx::kind_f16_t, uint32_t, uint64_t, uint64_t, uint32_t, bool, uint64_t)>(
+            cuda::ptx::tcgen05_mma_ws_collector_b1_fill));
+          // tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b1::fill [d_tmem], a_desc, b_desc, idesc,
+          // enable_input_d, zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_tf32_t, uint32_t, uint64_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b1_fill));
+          // tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b1::fill [d_tmem], a_desc, b_desc, idesc,
+          // enable_input_d, zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_f8f6f4_t, uint32_t, uint64_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b1_fill));
+          // tcgen05.mma.ws.cta_group::1.kind::i8.collector::b1::fill [d_tmem], a_desc, b_desc, idesc, enable_input_d,
+          // zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_i8_t, uint32_t, uint64_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b1_fill));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tcgen05.mma.ws.cta_group::1.kind::f16.collector::b1::fill [d_tmem], a_desc, b_desc, idesc, enable_input_d;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(
+            cuda::ptx::cta_group_1_t, cuda::ptx::kind_f16_t, uint32_t, uint64_t, uint64_t, uint32_t, bool)>(
+            cuda::ptx::tcgen05_mma_ws_collector_b1_fill));
+          // tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b1::fill [d_tmem], a_desc, b_desc, idesc, enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_tf32_t, uint32_t, uint64_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b1_fill));
+          // tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b1::fill [d_tmem], a_desc, b_desc, idesc,
+          // enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_f8f6f4_t, uint32_t, uint64_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b1_fill));
+          // tcgen05.mma.ws.cta_group::1.kind::i8.collector::b1::fill [d_tmem], a_desc, b_desc, idesc, enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_i8_t, uint32_t, uint64_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b1_fill));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // tcgen05.mma.ws.cta_group::1.kind::f16.collector::b1::fill [d_tmem], a_desc, b_desc, idesc, enable_input_d;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(
+            cuda::ptx::cta_group_1_t, cuda::ptx::kind_f16_t, uint32_t, uint64_t, uint64_t, uint32_t, bool)>(
+            cuda::ptx::tcgen05_mma_ws_collector_b1_fill));
+          // tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b1::fill [d_tmem], a_desc, b_desc, idesc, enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_tf32_t, uint32_t, uint64_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b1_fill));
+          // tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b1::fill [d_tmem], a_desc, b_desc, idesc,
+          // enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_f8f6f4_t, uint32_t, uint64_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b1_fill));
+          // tcgen05.mma.ws.cta_group::1.kind::i8.collector::b1::fill [d_tmem], a_desc, b_desc, idesc, enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_i8_t, uint32_t, uint64_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b1_fill));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tcgen05.mma.ws.cta_group::1.kind::f16.collector::b1::fill [d_tmem], [a_tmem], b_desc, idesc, enable_input_d,
+        // zero_column_mask_desc;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(
+            cuda::ptx::cta_group_1_t, cuda::ptx::kind_f16_t, uint32_t, uint32_t, uint64_t, uint32_t, bool, uint64_t)>(
+            cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b1_fill));
+          // tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b1::fill [d_tmem], [a_tmem], b_desc, idesc,
+          // enable_input_d, zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_tf32_t, uint32_t, uint32_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b1_fill));
+          // tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b1::fill [d_tmem], [a_tmem], b_desc, idesc,
+          // enable_input_d, zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_f8f6f4_t, uint32_t, uint32_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b1_fill));
+          // tcgen05.mma.ws.cta_group::1.kind::i8.collector::b1::fill [d_tmem], [a_tmem], b_desc, idesc,
+          // enable_input_d, zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_i8_t, uint32_t, uint32_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b1_fill));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // tcgen05.mma.ws.cta_group::1.kind::f16.collector::b1::fill [d_tmem], [a_tmem], b_desc, idesc, enable_input_d,
+        // zero_column_mask_desc;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(
+            cuda::ptx::cta_group_1_t, cuda::ptx::kind_f16_t, uint32_t, uint32_t, uint64_t, uint32_t, bool, uint64_t)>(
+            cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b1_fill));
+          // tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b1::fill [d_tmem], [a_tmem], b_desc, idesc,
+          // enable_input_d, zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_tf32_t, uint32_t, uint32_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b1_fill));
+          // tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b1::fill [d_tmem], [a_tmem], b_desc, idesc,
+          // enable_input_d, zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_f8f6f4_t, uint32_t, uint32_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b1_fill));
+          // tcgen05.mma.ws.cta_group::1.kind::i8.collector::b1::fill [d_tmem], [a_tmem], b_desc, idesc,
+          // enable_input_d, zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_i8_t, uint32_t, uint32_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b1_fill));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tcgen05.mma.ws.cta_group::1.kind::f16.collector::b1::fill [d_tmem], [a_tmem], b_desc, idesc, enable_input_d;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(
+            cuda::ptx::cta_group_1_t, cuda::ptx::kind_f16_t, uint32_t, uint32_t, uint64_t, uint32_t, bool)>(
+            cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b1_fill));
+          // tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b1::fill [d_tmem], [a_tmem], b_desc, idesc,
+          // enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_tf32_t, uint32_t, uint32_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b1_fill));
+          // tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b1::fill [d_tmem], [a_tmem], b_desc, idesc,
+          // enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_f8f6f4_t, uint32_t, uint32_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b1_fill));
+          // tcgen05.mma.ws.cta_group::1.kind::i8.collector::b1::fill [d_tmem], [a_tmem], b_desc, idesc, enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_i8_t, uint32_t, uint32_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b1_fill));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // tcgen05.mma.ws.cta_group::1.kind::f16.collector::b1::fill [d_tmem], [a_tmem], b_desc, idesc, enable_input_d;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(
+            cuda::ptx::cta_group_1_t, cuda::ptx::kind_f16_t, uint32_t, uint32_t, uint64_t, uint32_t, bool)>(
+            cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b1_fill));
+          // tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b1::fill [d_tmem], [a_tmem], b_desc, idesc,
+          // enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_tf32_t, uint32_t, uint32_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b1_fill));
+          // tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b1::fill [d_tmem], [a_tmem], b_desc, idesc,
+          // enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_f8f6f4_t, uint32_t, uint32_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b1_fill));
+          // tcgen05.mma.ws.cta_group::1.kind::i8.collector::b1::fill [d_tmem], [a_tmem], b_desc, idesc, enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_i8_t, uint32_t, uint32_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b1_fill));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tcgen05.mma.ws.cta_group::1.kind::f16.collector::b1::use [d_tmem], a_desc, b_desc, idesc, enable_input_d,
+        // zero_column_mask_desc;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(
+            cuda::ptx::cta_group_1_t, cuda::ptx::kind_f16_t, uint32_t, uint64_t, uint64_t, uint32_t, bool, uint64_t)>(
+            cuda::ptx::tcgen05_mma_ws_collector_b1_use));
+          // tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b1::use [d_tmem], a_desc, b_desc, idesc,
+          // enable_input_d, zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_tf32_t, uint32_t, uint64_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b1_use));
+          // tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b1::use [d_tmem], a_desc, b_desc, idesc,
+          // enable_input_d, zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_f8f6f4_t, uint32_t, uint64_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b1_use));
+          // tcgen05.mma.ws.cta_group::1.kind::i8.collector::b1::use [d_tmem], a_desc, b_desc, idesc, enable_input_d,
+          // zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_i8_t, uint32_t, uint64_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b1_use));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // tcgen05.mma.ws.cta_group::1.kind::f16.collector::b1::use [d_tmem], a_desc, b_desc, idesc, enable_input_d,
+        // zero_column_mask_desc;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(
+            cuda::ptx::cta_group_1_t, cuda::ptx::kind_f16_t, uint32_t, uint64_t, uint64_t, uint32_t, bool, uint64_t)>(
+            cuda::ptx::tcgen05_mma_ws_collector_b1_use));
+          // tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b1::use [d_tmem], a_desc, b_desc, idesc,
+          // enable_input_d, zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_tf32_t, uint32_t, uint64_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b1_use));
+          // tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b1::use [d_tmem], a_desc, b_desc, idesc,
+          // enable_input_d, zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_f8f6f4_t, uint32_t, uint64_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b1_use));
+          // tcgen05.mma.ws.cta_group::1.kind::i8.collector::b1::use [d_tmem], a_desc, b_desc, idesc, enable_input_d,
+          // zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_i8_t, uint32_t, uint64_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b1_use));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tcgen05.mma.ws.cta_group::1.kind::f16.collector::b1::use [d_tmem], a_desc, b_desc, idesc, enable_input_d;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(
+            cuda::ptx::cta_group_1_t, cuda::ptx::kind_f16_t, uint32_t, uint64_t, uint64_t, uint32_t, bool)>(
+            cuda::ptx::tcgen05_mma_ws_collector_b1_use));
+          // tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b1::use [d_tmem], a_desc, b_desc, idesc, enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_tf32_t, uint32_t, uint64_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b1_use));
+          // tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b1::use [d_tmem], a_desc, b_desc, idesc,
+          // enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_f8f6f4_t, uint32_t, uint64_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b1_use));
+          // tcgen05.mma.ws.cta_group::1.kind::i8.collector::b1::use [d_tmem], a_desc, b_desc, idesc, enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_i8_t, uint32_t, uint64_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b1_use));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // tcgen05.mma.ws.cta_group::1.kind::f16.collector::b1::use [d_tmem], a_desc, b_desc, idesc, enable_input_d;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(
+            cuda::ptx::cta_group_1_t, cuda::ptx::kind_f16_t, uint32_t, uint64_t, uint64_t, uint32_t, bool)>(
+            cuda::ptx::tcgen05_mma_ws_collector_b1_use));
+          // tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b1::use [d_tmem], a_desc, b_desc, idesc, enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_tf32_t, uint32_t, uint64_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b1_use));
+          // tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b1::use [d_tmem], a_desc, b_desc, idesc,
+          // enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_f8f6f4_t, uint32_t, uint64_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b1_use));
+          // tcgen05.mma.ws.cta_group::1.kind::i8.collector::b1::use [d_tmem], a_desc, b_desc, idesc, enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_i8_t, uint32_t, uint64_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b1_use));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tcgen05.mma.ws.cta_group::1.kind::f16.collector::b1::use [d_tmem], [a_tmem], b_desc, idesc, enable_input_d,
+        // zero_column_mask_desc;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(
+            cuda::ptx::cta_group_1_t, cuda::ptx::kind_f16_t, uint32_t, uint32_t, uint64_t, uint32_t, bool, uint64_t)>(
+            cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b1_use));
+          // tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b1::use [d_tmem], [a_tmem], b_desc, idesc,
+          // enable_input_d, zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_tf32_t, uint32_t, uint32_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b1_use));
+          // tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b1::use [d_tmem], [a_tmem], b_desc, idesc,
+          // enable_input_d, zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_f8f6f4_t, uint32_t, uint32_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b1_use));
+          // tcgen05.mma.ws.cta_group::1.kind::i8.collector::b1::use [d_tmem], [a_tmem], b_desc, idesc,
+          // enable_input_d, zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_i8_t, uint32_t, uint32_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b1_use));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // tcgen05.mma.ws.cta_group::1.kind::f16.collector::b1::use [d_tmem], [a_tmem], b_desc, idesc, enable_input_d,
+        // zero_column_mask_desc;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(
+            cuda::ptx::cta_group_1_t, cuda::ptx::kind_f16_t, uint32_t, uint32_t, uint64_t, uint32_t, bool, uint64_t)>(
+            cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b1_use));
+          // tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b1::use [d_tmem], [a_tmem], b_desc, idesc,
+          // enable_input_d, zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_tf32_t, uint32_t, uint32_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b1_use));
+          // tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b1::use [d_tmem], [a_tmem], b_desc, idesc,
+          // enable_input_d, zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_f8f6f4_t, uint32_t, uint32_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b1_use));
+          // tcgen05.mma.ws.cta_group::1.kind::i8.collector::b1::use [d_tmem], [a_tmem], b_desc, idesc,
+          // enable_input_d, zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_i8_t, uint32_t, uint32_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b1_use));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tcgen05.mma.ws.cta_group::1.kind::f16.collector::b1::use [d_tmem], [a_tmem], b_desc, idesc, enable_input_d;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(
+            cuda::ptx::cta_group_1_t, cuda::ptx::kind_f16_t, uint32_t, uint32_t, uint64_t, uint32_t, bool)>(
+            cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b1_use));
+          // tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b1::use [d_tmem], [a_tmem], b_desc, idesc,
+          // enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_tf32_t, uint32_t, uint32_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b1_use));
+          // tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b1::use [d_tmem], [a_tmem], b_desc, idesc,
+          // enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_f8f6f4_t, uint32_t, uint32_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b1_use));
+          // tcgen05.mma.ws.cta_group::1.kind::i8.collector::b1::use [d_tmem], [a_tmem], b_desc, idesc, enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_i8_t, uint32_t, uint32_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b1_use));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // tcgen05.mma.ws.cta_group::1.kind::f16.collector::b1::use [d_tmem], [a_tmem], b_desc, idesc, enable_input_d;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(
+            cuda::ptx::cta_group_1_t, cuda::ptx::kind_f16_t, uint32_t, uint32_t, uint64_t, uint32_t, bool)>(
+            cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b1_use));
+          // tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b1::use [d_tmem], [a_tmem], b_desc, idesc,
+          // enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_tf32_t, uint32_t, uint32_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b1_use));
+          // tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b1::use [d_tmem], [a_tmem], b_desc, idesc,
+          // enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_f8f6f4_t, uint32_t, uint32_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b1_use));
+          // tcgen05.mma.ws.cta_group::1.kind::i8.collector::b1::use [d_tmem], [a_tmem], b_desc, idesc, enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_i8_t, uint32_t, uint32_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b1_use));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tcgen05.mma.ws.cta_group::1.kind::f16.collector::b1::lastuse [d_tmem], a_desc, b_desc, idesc, enable_input_d,
+        // zero_column_mask_desc;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(
+            cuda::ptx::cta_group_1_t, cuda::ptx::kind_f16_t, uint32_t, uint64_t, uint64_t, uint32_t, bool, uint64_t)>(
+            cuda::ptx::tcgen05_mma_ws_collector_b1_lastuse));
+          // tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b1::lastuse [d_tmem], a_desc, b_desc, idesc,
+          // enable_input_d, zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_tf32_t, uint32_t, uint64_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b1_lastuse));
+          // tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b1::lastuse [d_tmem], a_desc, b_desc, idesc,
+          // enable_input_d, zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_f8f6f4_t, uint32_t, uint64_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b1_lastuse));
+          // tcgen05.mma.ws.cta_group::1.kind::i8.collector::b1::lastuse [d_tmem], a_desc, b_desc, idesc,
+          // enable_input_d, zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_i8_t, uint32_t, uint64_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b1_lastuse));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // tcgen05.mma.ws.cta_group::1.kind::f16.collector::b1::lastuse [d_tmem], a_desc, b_desc, idesc, enable_input_d,
+        // zero_column_mask_desc;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(
+            cuda::ptx::cta_group_1_t, cuda::ptx::kind_f16_t, uint32_t, uint64_t, uint64_t, uint32_t, bool, uint64_t)>(
+            cuda::ptx::tcgen05_mma_ws_collector_b1_lastuse));
+          // tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b1::lastuse [d_tmem], a_desc, b_desc, idesc,
+          // enable_input_d, zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_tf32_t, uint32_t, uint64_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b1_lastuse));
+          // tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b1::lastuse [d_tmem], a_desc, b_desc, idesc,
+          // enable_input_d, zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_f8f6f4_t, uint32_t, uint64_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b1_lastuse));
+          // tcgen05.mma.ws.cta_group::1.kind::i8.collector::b1::lastuse [d_tmem], a_desc, b_desc, idesc,
+          // enable_input_d, zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_i8_t, uint32_t, uint64_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b1_lastuse));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tcgen05.mma.ws.cta_group::1.kind::f16.collector::b1::lastuse [d_tmem], a_desc, b_desc, idesc, enable_input_d;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(
+            cuda::ptx::cta_group_1_t, cuda::ptx::kind_f16_t, uint32_t, uint64_t, uint64_t, uint32_t, bool)>(
+            cuda::ptx::tcgen05_mma_ws_collector_b1_lastuse));
+          // tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b1::lastuse [d_tmem], a_desc, b_desc, idesc,
+          // enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_tf32_t, uint32_t, uint64_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b1_lastuse));
+          // tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b1::lastuse [d_tmem], a_desc, b_desc, idesc,
+          // enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_f8f6f4_t, uint32_t, uint64_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b1_lastuse));
+          // tcgen05.mma.ws.cta_group::1.kind::i8.collector::b1::lastuse [d_tmem], a_desc, b_desc, idesc,
+          // enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_i8_t, uint32_t, uint64_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b1_lastuse));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // tcgen05.mma.ws.cta_group::1.kind::f16.collector::b1::lastuse [d_tmem], a_desc, b_desc, idesc, enable_input_d;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(
+            cuda::ptx::cta_group_1_t, cuda::ptx::kind_f16_t, uint32_t, uint64_t, uint64_t, uint32_t, bool)>(
+            cuda::ptx::tcgen05_mma_ws_collector_b1_lastuse));
+          // tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b1::lastuse [d_tmem], a_desc, b_desc, idesc,
+          // enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_tf32_t, uint32_t, uint64_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b1_lastuse));
+          // tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b1::lastuse [d_tmem], a_desc, b_desc, idesc,
+          // enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_f8f6f4_t, uint32_t, uint64_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b1_lastuse));
+          // tcgen05.mma.ws.cta_group::1.kind::i8.collector::b1::lastuse [d_tmem], a_desc, b_desc, idesc,
+          // enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_i8_t, uint32_t, uint64_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b1_lastuse));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tcgen05.mma.ws.cta_group::1.kind::f16.collector::b1::lastuse [d_tmem], [a_tmem], b_desc, idesc,
+        // enable_input_d, zero_column_mask_desc;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(
+            cuda::ptx::cta_group_1_t, cuda::ptx::kind_f16_t, uint32_t, uint32_t, uint64_t, uint32_t, bool, uint64_t)>(
+            cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b1_lastuse));
+          // tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b1::lastuse [d_tmem], [a_tmem], b_desc, idesc,
+          // enable_input_d, zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_tf32_t, uint32_t, uint32_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b1_lastuse));
+          // tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b1::lastuse [d_tmem], [a_tmem], b_desc, idesc,
+          // enable_input_d, zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_f8f6f4_t, uint32_t, uint32_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b1_lastuse));
+          // tcgen05.mma.ws.cta_group::1.kind::i8.collector::b1::lastuse [d_tmem], [a_tmem], b_desc, idesc,
+          // enable_input_d, zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_i8_t, uint32_t, uint32_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b1_lastuse));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // tcgen05.mma.ws.cta_group::1.kind::f16.collector::b1::lastuse [d_tmem], [a_tmem], b_desc, idesc,
+        // enable_input_d, zero_column_mask_desc;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(
+            cuda::ptx::cta_group_1_t, cuda::ptx::kind_f16_t, uint32_t, uint32_t, uint64_t, uint32_t, bool, uint64_t)>(
+            cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b1_lastuse));
+          // tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b1::lastuse [d_tmem], [a_tmem], b_desc, idesc,
+          // enable_input_d, zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_tf32_t, uint32_t, uint32_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b1_lastuse));
+          // tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b1::lastuse [d_tmem], [a_tmem], b_desc, idesc,
+          // enable_input_d, zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_f8f6f4_t, uint32_t, uint32_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b1_lastuse));
+          // tcgen05.mma.ws.cta_group::1.kind::i8.collector::b1::lastuse [d_tmem], [a_tmem], b_desc, idesc,
+          // enable_input_d, zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_i8_t, uint32_t, uint32_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b1_lastuse));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tcgen05.mma.ws.cta_group::1.kind::f16.collector::b1::lastuse [d_tmem], [a_tmem], b_desc, idesc,
+        // enable_input_d;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(
+            cuda::ptx::cta_group_1_t, cuda::ptx::kind_f16_t, uint32_t, uint32_t, uint64_t, uint32_t, bool)>(
+            cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b1_lastuse));
+          // tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b1::lastuse [d_tmem], [a_tmem], b_desc, idesc,
+          // enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_tf32_t, uint32_t, uint32_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b1_lastuse));
+          // tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b1::lastuse [d_tmem], [a_tmem], b_desc, idesc,
+          // enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_f8f6f4_t, uint32_t, uint32_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b1_lastuse));
+          // tcgen05.mma.ws.cta_group::1.kind::i8.collector::b1::lastuse [d_tmem], [a_tmem], b_desc, idesc,
+          // enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_i8_t, uint32_t, uint32_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b1_lastuse));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // tcgen05.mma.ws.cta_group::1.kind::f16.collector::b1::lastuse [d_tmem], [a_tmem], b_desc, idesc,
+        // enable_input_d;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(
+            cuda::ptx::cta_group_1_t, cuda::ptx::kind_f16_t, uint32_t, uint32_t, uint64_t, uint32_t, bool)>(
+            cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b1_lastuse));
+          // tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b1::lastuse [d_tmem], [a_tmem], b_desc, idesc,
+          // enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_tf32_t, uint32_t, uint32_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b1_lastuse));
+          // tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b1::lastuse [d_tmem], [a_tmem], b_desc, idesc,
+          // enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_f8f6f4_t, uint32_t, uint32_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b1_lastuse));
+          // tcgen05.mma.ws.cta_group::1.kind::i8.collector::b1::lastuse [d_tmem], [a_tmem], b_desc, idesc,
+          // enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_i8_t, uint32_t, uint32_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b1_lastuse));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tcgen05.mma.ws.cta_group::1.kind::f16.collector::b1::discard [d_tmem], a_desc, b_desc, idesc, enable_input_d,
+        // zero_column_mask_desc;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(
+            cuda::ptx::cta_group_1_t, cuda::ptx::kind_f16_t, uint32_t, uint64_t, uint64_t, uint32_t, bool, uint64_t)>(
+            cuda::ptx::tcgen05_mma_ws_collector_b1_discard));
+          // tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b1::discard [d_tmem], a_desc, b_desc, idesc,
+          // enable_input_d, zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_tf32_t, uint32_t, uint64_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b1_discard));
+          // tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b1::discard [d_tmem], a_desc, b_desc, idesc,
+          // enable_input_d, zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_f8f6f4_t, uint32_t, uint64_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b1_discard));
+          // tcgen05.mma.ws.cta_group::1.kind::i8.collector::b1::discard [d_tmem], a_desc, b_desc, idesc,
+          // enable_input_d, zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_i8_t, uint32_t, uint64_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b1_discard));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // tcgen05.mma.ws.cta_group::1.kind::f16.collector::b1::discard [d_tmem], a_desc, b_desc, idesc, enable_input_d,
+        // zero_column_mask_desc;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(
+            cuda::ptx::cta_group_1_t, cuda::ptx::kind_f16_t, uint32_t, uint64_t, uint64_t, uint32_t, bool, uint64_t)>(
+            cuda::ptx::tcgen05_mma_ws_collector_b1_discard));
+          // tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b1::discard [d_tmem], a_desc, b_desc, idesc,
+          // enable_input_d, zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_tf32_t, uint32_t, uint64_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b1_discard));
+          // tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b1::discard [d_tmem], a_desc, b_desc, idesc,
+          // enable_input_d, zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_f8f6f4_t, uint32_t, uint64_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b1_discard));
+          // tcgen05.mma.ws.cta_group::1.kind::i8.collector::b1::discard [d_tmem], a_desc, b_desc, idesc,
+          // enable_input_d, zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_i8_t, uint32_t, uint64_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b1_discard));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tcgen05.mma.ws.cta_group::1.kind::f16.collector::b1::discard [d_tmem], a_desc, b_desc, idesc, enable_input_d;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(
+            cuda::ptx::cta_group_1_t, cuda::ptx::kind_f16_t, uint32_t, uint64_t, uint64_t, uint32_t, bool)>(
+            cuda::ptx::tcgen05_mma_ws_collector_b1_discard));
+          // tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b1::discard [d_tmem], a_desc, b_desc, idesc,
+          // enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_tf32_t, uint32_t, uint64_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b1_discard));
+          // tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b1::discard [d_tmem], a_desc, b_desc, idesc,
+          // enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_f8f6f4_t, uint32_t, uint64_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b1_discard));
+          // tcgen05.mma.ws.cta_group::1.kind::i8.collector::b1::discard [d_tmem], a_desc, b_desc, idesc,
+          // enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_i8_t, uint32_t, uint64_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b1_discard));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // tcgen05.mma.ws.cta_group::1.kind::f16.collector::b1::discard [d_tmem], a_desc, b_desc, idesc, enable_input_d;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(
+            cuda::ptx::cta_group_1_t, cuda::ptx::kind_f16_t, uint32_t, uint64_t, uint64_t, uint32_t, bool)>(
+            cuda::ptx::tcgen05_mma_ws_collector_b1_discard));
+          // tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b1::discard [d_tmem], a_desc, b_desc, idesc,
+          // enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_tf32_t, uint32_t, uint64_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b1_discard));
+          // tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b1::discard [d_tmem], a_desc, b_desc, idesc,
+          // enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_f8f6f4_t, uint32_t, uint64_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b1_discard));
+          // tcgen05.mma.ws.cta_group::1.kind::i8.collector::b1::discard [d_tmem], a_desc, b_desc, idesc,
+          // enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_i8_t, uint32_t, uint64_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b1_discard));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tcgen05.mma.ws.cta_group::1.kind::f16.collector::b1::discard [d_tmem], [a_tmem], b_desc, idesc,
+        // enable_input_d, zero_column_mask_desc;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(
+            cuda::ptx::cta_group_1_t, cuda::ptx::kind_f16_t, uint32_t, uint32_t, uint64_t, uint32_t, bool, uint64_t)>(
+            cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b1_discard));
+          // tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b1::discard [d_tmem], [a_tmem], b_desc, idesc,
+          // enable_input_d, zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_tf32_t, uint32_t, uint32_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b1_discard));
+          // tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b1::discard [d_tmem], [a_tmem], b_desc, idesc,
+          // enable_input_d, zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_f8f6f4_t, uint32_t, uint32_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b1_discard));
+          // tcgen05.mma.ws.cta_group::1.kind::i8.collector::b1::discard [d_tmem], [a_tmem], b_desc, idesc,
+          // enable_input_d, zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_i8_t, uint32_t, uint32_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b1_discard));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // tcgen05.mma.ws.cta_group::1.kind::f16.collector::b1::discard [d_tmem], [a_tmem], b_desc, idesc,
+        // enable_input_d, zero_column_mask_desc;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(
+            cuda::ptx::cta_group_1_t, cuda::ptx::kind_f16_t, uint32_t, uint32_t, uint64_t, uint32_t, bool, uint64_t)>(
+            cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b1_discard));
+          // tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b1::discard [d_tmem], [a_tmem], b_desc, idesc,
+          // enable_input_d, zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_tf32_t, uint32_t, uint32_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b1_discard));
+          // tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b1::discard [d_tmem], [a_tmem], b_desc, idesc,
+          // enable_input_d, zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_f8f6f4_t, uint32_t, uint32_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b1_discard));
+          // tcgen05.mma.ws.cta_group::1.kind::i8.collector::b1::discard [d_tmem], [a_tmem], b_desc, idesc,
+          // enable_input_d, zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_i8_t, uint32_t, uint32_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b1_discard));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tcgen05.mma.ws.cta_group::1.kind::f16.collector::b1::discard [d_tmem], [a_tmem], b_desc, idesc,
+        // enable_input_d;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(
+            cuda::ptx::cta_group_1_t, cuda::ptx::kind_f16_t, uint32_t, uint32_t, uint64_t, uint32_t, bool)>(
+            cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b1_discard));
+          // tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b1::discard [d_tmem], [a_tmem], b_desc, idesc,
+          // enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_tf32_t, uint32_t, uint32_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b1_discard));
+          // tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b1::discard [d_tmem], [a_tmem], b_desc, idesc,
+          // enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_f8f6f4_t, uint32_t, uint32_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b1_discard));
+          // tcgen05.mma.ws.cta_group::1.kind::i8.collector::b1::discard [d_tmem], [a_tmem], b_desc, idesc,
+          // enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_i8_t, uint32_t, uint32_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b1_discard));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // tcgen05.mma.ws.cta_group::1.kind::f16.collector::b1::discard [d_tmem], [a_tmem], b_desc, idesc,
+        // enable_input_d;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(
+            cuda::ptx::cta_group_1_t, cuda::ptx::kind_f16_t, uint32_t, uint32_t, uint64_t, uint32_t, bool)>(
+            cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b1_discard));
+          // tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b1::discard [d_tmem], [a_tmem], b_desc, idesc,
+          // enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_tf32_t, uint32_t, uint32_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b1_discard));
+          // tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b1::discard [d_tmem], [a_tmem], b_desc, idesc,
+          // enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_f8f6f4_t, uint32_t, uint32_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b1_discard));
+          // tcgen05.mma.ws.cta_group::1.kind::i8.collector::b1::discard [d_tmem], [a_tmem], b_desc, idesc,
+          // enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_i8_t, uint32_t, uint32_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b1_discard));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tcgen05.mma.ws.cta_group::1.kind::f16.collector::b2::fill [d_tmem], a_desc, b_desc, idesc, enable_input_d,
+        // zero_column_mask_desc;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(
+            cuda::ptx::cta_group_1_t, cuda::ptx::kind_f16_t, uint32_t, uint64_t, uint64_t, uint32_t, bool, uint64_t)>(
+            cuda::ptx::tcgen05_mma_ws_collector_b2_fill));
+          // tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b2::fill [d_tmem], a_desc, b_desc, idesc,
+          // enable_input_d, zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_tf32_t, uint32_t, uint64_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b2_fill));
+          // tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b2::fill [d_tmem], a_desc, b_desc, idesc,
+          // enable_input_d, zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_f8f6f4_t, uint32_t, uint64_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b2_fill));
+          // tcgen05.mma.ws.cta_group::1.kind::i8.collector::b2::fill [d_tmem], a_desc, b_desc, idesc, enable_input_d,
+          // zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_i8_t, uint32_t, uint64_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b2_fill));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // tcgen05.mma.ws.cta_group::1.kind::f16.collector::b2::fill [d_tmem], a_desc, b_desc, idesc, enable_input_d,
+        // zero_column_mask_desc;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(
+            cuda::ptx::cta_group_1_t, cuda::ptx::kind_f16_t, uint32_t, uint64_t, uint64_t, uint32_t, bool, uint64_t)>(
+            cuda::ptx::tcgen05_mma_ws_collector_b2_fill));
+          // tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b2::fill [d_tmem], a_desc, b_desc, idesc,
+          // enable_input_d, zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_tf32_t, uint32_t, uint64_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b2_fill));
+          // tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b2::fill [d_tmem], a_desc, b_desc, idesc,
+          // enable_input_d, zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_f8f6f4_t, uint32_t, uint64_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b2_fill));
+          // tcgen05.mma.ws.cta_group::1.kind::i8.collector::b2::fill [d_tmem], a_desc, b_desc, idesc, enable_input_d,
+          // zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_i8_t, uint32_t, uint64_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b2_fill));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tcgen05.mma.ws.cta_group::1.kind::f16.collector::b2::fill [d_tmem], a_desc, b_desc, idesc, enable_input_d;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(
+            cuda::ptx::cta_group_1_t, cuda::ptx::kind_f16_t, uint32_t, uint64_t, uint64_t, uint32_t, bool)>(
+            cuda::ptx::tcgen05_mma_ws_collector_b2_fill));
+          // tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b2::fill [d_tmem], a_desc, b_desc, idesc, enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_tf32_t, uint32_t, uint64_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b2_fill));
+          // tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b2::fill [d_tmem], a_desc, b_desc, idesc,
+          // enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_f8f6f4_t, uint32_t, uint64_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b2_fill));
+          // tcgen05.mma.ws.cta_group::1.kind::i8.collector::b2::fill [d_tmem], a_desc, b_desc, idesc, enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_i8_t, uint32_t, uint64_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b2_fill));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // tcgen05.mma.ws.cta_group::1.kind::f16.collector::b2::fill [d_tmem], a_desc, b_desc, idesc, enable_input_d;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(
+            cuda::ptx::cta_group_1_t, cuda::ptx::kind_f16_t, uint32_t, uint64_t, uint64_t, uint32_t, bool)>(
+            cuda::ptx::tcgen05_mma_ws_collector_b2_fill));
+          // tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b2::fill [d_tmem], a_desc, b_desc, idesc, enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_tf32_t, uint32_t, uint64_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b2_fill));
+          // tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b2::fill [d_tmem], a_desc, b_desc, idesc,
+          // enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_f8f6f4_t, uint32_t, uint64_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b2_fill));
+          // tcgen05.mma.ws.cta_group::1.kind::i8.collector::b2::fill [d_tmem], a_desc, b_desc, idesc, enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_i8_t, uint32_t, uint64_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b2_fill));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tcgen05.mma.ws.cta_group::1.kind::f16.collector::b2::fill [d_tmem], [a_tmem], b_desc, idesc, enable_input_d,
+        // zero_column_mask_desc;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(
+            cuda::ptx::cta_group_1_t, cuda::ptx::kind_f16_t, uint32_t, uint32_t, uint64_t, uint32_t, bool, uint64_t)>(
+            cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b2_fill));
+          // tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b2::fill [d_tmem], [a_tmem], b_desc, idesc,
+          // enable_input_d, zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_tf32_t, uint32_t, uint32_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b2_fill));
+          // tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b2::fill [d_tmem], [a_tmem], b_desc, idesc,
+          // enable_input_d, zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_f8f6f4_t, uint32_t, uint32_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b2_fill));
+          // tcgen05.mma.ws.cta_group::1.kind::i8.collector::b2::fill [d_tmem], [a_tmem], b_desc, idesc,
+          // enable_input_d, zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_i8_t, uint32_t, uint32_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b2_fill));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // tcgen05.mma.ws.cta_group::1.kind::f16.collector::b2::fill [d_tmem], [a_tmem], b_desc, idesc, enable_input_d,
+        // zero_column_mask_desc;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(
+            cuda::ptx::cta_group_1_t, cuda::ptx::kind_f16_t, uint32_t, uint32_t, uint64_t, uint32_t, bool, uint64_t)>(
+            cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b2_fill));
+          // tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b2::fill [d_tmem], [a_tmem], b_desc, idesc,
+          // enable_input_d, zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_tf32_t, uint32_t, uint32_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b2_fill));
+          // tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b2::fill [d_tmem], [a_tmem], b_desc, idesc,
+          // enable_input_d, zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_f8f6f4_t, uint32_t, uint32_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b2_fill));
+          // tcgen05.mma.ws.cta_group::1.kind::i8.collector::b2::fill [d_tmem], [a_tmem], b_desc, idesc,
+          // enable_input_d, zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_i8_t, uint32_t, uint32_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b2_fill));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tcgen05.mma.ws.cta_group::1.kind::f16.collector::b2::fill [d_tmem], [a_tmem], b_desc, idesc, enable_input_d;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(
+            cuda::ptx::cta_group_1_t, cuda::ptx::kind_f16_t, uint32_t, uint32_t, uint64_t, uint32_t, bool)>(
+            cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b2_fill));
+          // tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b2::fill [d_tmem], [a_tmem], b_desc, idesc,
+          // enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_tf32_t, uint32_t, uint32_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b2_fill));
+          // tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b2::fill [d_tmem], [a_tmem], b_desc, idesc,
+          // enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_f8f6f4_t, uint32_t, uint32_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b2_fill));
+          // tcgen05.mma.ws.cta_group::1.kind::i8.collector::b2::fill [d_tmem], [a_tmem], b_desc, idesc, enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_i8_t, uint32_t, uint32_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b2_fill));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // tcgen05.mma.ws.cta_group::1.kind::f16.collector::b2::fill [d_tmem], [a_tmem], b_desc, idesc, enable_input_d;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(
+            cuda::ptx::cta_group_1_t, cuda::ptx::kind_f16_t, uint32_t, uint32_t, uint64_t, uint32_t, bool)>(
+            cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b2_fill));
+          // tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b2::fill [d_tmem], [a_tmem], b_desc, idesc,
+          // enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_tf32_t, uint32_t, uint32_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b2_fill));
+          // tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b2::fill [d_tmem], [a_tmem], b_desc, idesc,
+          // enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_f8f6f4_t, uint32_t, uint32_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b2_fill));
+          // tcgen05.mma.ws.cta_group::1.kind::i8.collector::b2::fill [d_tmem], [a_tmem], b_desc, idesc, enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_i8_t, uint32_t, uint32_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b2_fill));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tcgen05.mma.ws.cta_group::1.kind::f16.collector::b2::use [d_tmem], a_desc, b_desc, idesc, enable_input_d,
+        // zero_column_mask_desc;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(
+            cuda::ptx::cta_group_1_t, cuda::ptx::kind_f16_t, uint32_t, uint64_t, uint64_t, uint32_t, bool, uint64_t)>(
+            cuda::ptx::tcgen05_mma_ws_collector_b2_use));
+          // tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b2::use [d_tmem], a_desc, b_desc, idesc,
+          // enable_input_d, zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_tf32_t, uint32_t, uint64_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b2_use));
+          // tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b2::use [d_tmem], a_desc, b_desc, idesc,
+          // enable_input_d, zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_f8f6f4_t, uint32_t, uint64_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b2_use));
+          // tcgen05.mma.ws.cta_group::1.kind::i8.collector::b2::use [d_tmem], a_desc, b_desc, idesc, enable_input_d,
+          // zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_i8_t, uint32_t, uint64_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b2_use));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // tcgen05.mma.ws.cta_group::1.kind::f16.collector::b2::use [d_tmem], a_desc, b_desc, idesc, enable_input_d,
+        // zero_column_mask_desc;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(
+            cuda::ptx::cta_group_1_t, cuda::ptx::kind_f16_t, uint32_t, uint64_t, uint64_t, uint32_t, bool, uint64_t)>(
+            cuda::ptx::tcgen05_mma_ws_collector_b2_use));
+          // tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b2::use [d_tmem], a_desc, b_desc, idesc,
+          // enable_input_d, zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_tf32_t, uint32_t, uint64_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b2_use));
+          // tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b2::use [d_tmem], a_desc, b_desc, idesc,
+          // enable_input_d, zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_f8f6f4_t, uint32_t, uint64_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b2_use));
+          // tcgen05.mma.ws.cta_group::1.kind::i8.collector::b2::use [d_tmem], a_desc, b_desc, idesc, enable_input_d,
+          // zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_i8_t, uint32_t, uint64_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b2_use));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tcgen05.mma.ws.cta_group::1.kind::f16.collector::b2::use [d_tmem], a_desc, b_desc, idesc, enable_input_d;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(
+            cuda::ptx::cta_group_1_t, cuda::ptx::kind_f16_t, uint32_t, uint64_t, uint64_t, uint32_t, bool)>(
+            cuda::ptx::tcgen05_mma_ws_collector_b2_use));
+          // tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b2::use [d_tmem], a_desc, b_desc, idesc, enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_tf32_t, uint32_t, uint64_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b2_use));
+          // tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b2::use [d_tmem], a_desc, b_desc, idesc,
+          // enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_f8f6f4_t, uint32_t, uint64_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b2_use));
+          // tcgen05.mma.ws.cta_group::1.kind::i8.collector::b2::use [d_tmem], a_desc, b_desc, idesc, enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_i8_t, uint32_t, uint64_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b2_use));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // tcgen05.mma.ws.cta_group::1.kind::f16.collector::b2::use [d_tmem], a_desc, b_desc, idesc, enable_input_d;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(
+            cuda::ptx::cta_group_1_t, cuda::ptx::kind_f16_t, uint32_t, uint64_t, uint64_t, uint32_t, bool)>(
+            cuda::ptx::tcgen05_mma_ws_collector_b2_use));
+          // tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b2::use [d_tmem], a_desc, b_desc, idesc, enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_tf32_t, uint32_t, uint64_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b2_use));
+          // tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b2::use [d_tmem], a_desc, b_desc, idesc,
+          // enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_f8f6f4_t, uint32_t, uint64_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b2_use));
+          // tcgen05.mma.ws.cta_group::1.kind::i8.collector::b2::use [d_tmem], a_desc, b_desc, idesc, enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_i8_t, uint32_t, uint64_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b2_use));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tcgen05.mma.ws.cta_group::1.kind::f16.collector::b2::use [d_tmem], [a_tmem], b_desc, idesc, enable_input_d,
+        // zero_column_mask_desc;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(
+            cuda::ptx::cta_group_1_t, cuda::ptx::kind_f16_t, uint32_t, uint32_t, uint64_t, uint32_t, bool, uint64_t)>(
+            cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b2_use));
+          // tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b2::use [d_tmem], [a_tmem], b_desc, idesc,
+          // enable_input_d, zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_tf32_t, uint32_t, uint32_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b2_use));
+          // tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b2::use [d_tmem], [a_tmem], b_desc, idesc,
+          // enable_input_d, zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_f8f6f4_t, uint32_t, uint32_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b2_use));
+          // tcgen05.mma.ws.cta_group::1.kind::i8.collector::b2::use [d_tmem], [a_tmem], b_desc, idesc,
+          // enable_input_d, zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_i8_t, uint32_t, uint32_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b2_use));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // tcgen05.mma.ws.cta_group::1.kind::f16.collector::b2::use [d_tmem], [a_tmem], b_desc, idesc, enable_input_d,
+        // zero_column_mask_desc;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(
+            cuda::ptx::cta_group_1_t, cuda::ptx::kind_f16_t, uint32_t, uint32_t, uint64_t, uint32_t, bool, uint64_t)>(
+            cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b2_use));
+          // tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b2::use [d_tmem], [a_tmem], b_desc, idesc,
+          // enable_input_d, zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_tf32_t, uint32_t, uint32_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b2_use));
+          // tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b2::use [d_tmem], [a_tmem], b_desc, idesc,
+          // enable_input_d, zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_f8f6f4_t, uint32_t, uint32_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b2_use));
+          // tcgen05.mma.ws.cta_group::1.kind::i8.collector::b2::use [d_tmem], [a_tmem], b_desc, idesc,
+          // enable_input_d, zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_i8_t, uint32_t, uint32_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b2_use));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tcgen05.mma.ws.cta_group::1.kind::f16.collector::b2::use [d_tmem], [a_tmem], b_desc, idesc, enable_input_d;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(
+            cuda::ptx::cta_group_1_t, cuda::ptx::kind_f16_t, uint32_t, uint32_t, uint64_t, uint32_t, bool)>(
+            cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b2_use));
+          // tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b2::use [d_tmem], [a_tmem], b_desc, idesc,
+          // enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_tf32_t, uint32_t, uint32_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b2_use));
+          // tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b2::use [d_tmem], [a_tmem], b_desc, idesc,
+          // enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_f8f6f4_t, uint32_t, uint32_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b2_use));
+          // tcgen05.mma.ws.cta_group::1.kind::i8.collector::b2::use [d_tmem], [a_tmem], b_desc, idesc, enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_i8_t, uint32_t, uint32_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b2_use));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // tcgen05.mma.ws.cta_group::1.kind::f16.collector::b2::use [d_tmem], [a_tmem], b_desc, idesc, enable_input_d;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(
+            cuda::ptx::cta_group_1_t, cuda::ptx::kind_f16_t, uint32_t, uint32_t, uint64_t, uint32_t, bool)>(
+            cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b2_use));
+          // tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b2::use [d_tmem], [a_tmem], b_desc, idesc,
+          // enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_tf32_t, uint32_t, uint32_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b2_use));
+          // tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b2::use [d_tmem], [a_tmem], b_desc, idesc,
+          // enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_f8f6f4_t, uint32_t, uint32_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b2_use));
+          // tcgen05.mma.ws.cta_group::1.kind::i8.collector::b2::use [d_tmem], [a_tmem], b_desc, idesc, enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_i8_t, uint32_t, uint32_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b2_use));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tcgen05.mma.ws.cta_group::1.kind::f16.collector::b2::lastuse [d_tmem], a_desc, b_desc, idesc, enable_input_d,
+        // zero_column_mask_desc;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(
+            cuda::ptx::cta_group_1_t, cuda::ptx::kind_f16_t, uint32_t, uint64_t, uint64_t, uint32_t, bool, uint64_t)>(
+            cuda::ptx::tcgen05_mma_ws_collector_b2_lastuse));
+          // tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b2::lastuse [d_tmem], a_desc, b_desc, idesc,
+          // enable_input_d, zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_tf32_t, uint32_t, uint64_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b2_lastuse));
+          // tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b2::lastuse [d_tmem], a_desc, b_desc, idesc,
+          // enable_input_d, zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_f8f6f4_t, uint32_t, uint64_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b2_lastuse));
+          // tcgen05.mma.ws.cta_group::1.kind::i8.collector::b2::lastuse [d_tmem], a_desc, b_desc, idesc,
+          // enable_input_d, zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_i8_t, uint32_t, uint64_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b2_lastuse));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // tcgen05.mma.ws.cta_group::1.kind::f16.collector::b2::lastuse [d_tmem], a_desc, b_desc, idesc, enable_input_d,
+        // zero_column_mask_desc;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(
+            cuda::ptx::cta_group_1_t, cuda::ptx::kind_f16_t, uint32_t, uint64_t, uint64_t, uint32_t, bool, uint64_t)>(
+            cuda::ptx::tcgen05_mma_ws_collector_b2_lastuse));
+          // tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b2::lastuse [d_tmem], a_desc, b_desc, idesc,
+          // enable_input_d, zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_tf32_t, uint32_t, uint64_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b2_lastuse));
+          // tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b2::lastuse [d_tmem], a_desc, b_desc, idesc,
+          // enable_input_d, zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_f8f6f4_t, uint32_t, uint64_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b2_lastuse));
+          // tcgen05.mma.ws.cta_group::1.kind::i8.collector::b2::lastuse [d_tmem], a_desc, b_desc, idesc,
+          // enable_input_d, zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_i8_t, uint32_t, uint64_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b2_lastuse));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tcgen05.mma.ws.cta_group::1.kind::f16.collector::b2::lastuse [d_tmem], a_desc, b_desc, idesc, enable_input_d;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(
+            cuda::ptx::cta_group_1_t, cuda::ptx::kind_f16_t, uint32_t, uint64_t, uint64_t, uint32_t, bool)>(
+            cuda::ptx::tcgen05_mma_ws_collector_b2_lastuse));
+          // tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b2::lastuse [d_tmem], a_desc, b_desc, idesc,
+          // enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_tf32_t, uint32_t, uint64_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b2_lastuse));
+          // tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b2::lastuse [d_tmem], a_desc, b_desc, idesc,
+          // enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_f8f6f4_t, uint32_t, uint64_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b2_lastuse));
+          // tcgen05.mma.ws.cta_group::1.kind::i8.collector::b2::lastuse [d_tmem], a_desc, b_desc, idesc,
+          // enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_i8_t, uint32_t, uint64_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b2_lastuse));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // tcgen05.mma.ws.cta_group::1.kind::f16.collector::b2::lastuse [d_tmem], a_desc, b_desc, idesc, enable_input_d;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(
+            cuda::ptx::cta_group_1_t, cuda::ptx::kind_f16_t, uint32_t, uint64_t, uint64_t, uint32_t, bool)>(
+            cuda::ptx::tcgen05_mma_ws_collector_b2_lastuse));
+          // tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b2::lastuse [d_tmem], a_desc, b_desc, idesc,
+          // enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_tf32_t, uint32_t, uint64_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b2_lastuse));
+          // tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b2::lastuse [d_tmem], a_desc, b_desc, idesc,
+          // enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_f8f6f4_t, uint32_t, uint64_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b2_lastuse));
+          // tcgen05.mma.ws.cta_group::1.kind::i8.collector::b2::lastuse [d_tmem], a_desc, b_desc, idesc,
+          // enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_i8_t, uint32_t, uint64_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b2_lastuse));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tcgen05.mma.ws.cta_group::1.kind::f16.collector::b2::lastuse [d_tmem], [a_tmem], b_desc, idesc,
+        // enable_input_d, zero_column_mask_desc;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(
+            cuda::ptx::cta_group_1_t, cuda::ptx::kind_f16_t, uint32_t, uint32_t, uint64_t, uint32_t, bool, uint64_t)>(
+            cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b2_lastuse));
+          // tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b2::lastuse [d_tmem], [a_tmem], b_desc, idesc,
+          // enable_input_d, zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_tf32_t, uint32_t, uint32_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b2_lastuse));
+          // tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b2::lastuse [d_tmem], [a_tmem], b_desc, idesc,
+          // enable_input_d, zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_f8f6f4_t, uint32_t, uint32_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b2_lastuse));
+          // tcgen05.mma.ws.cta_group::1.kind::i8.collector::b2::lastuse [d_tmem], [a_tmem], b_desc, idesc,
+          // enable_input_d, zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_i8_t, uint32_t, uint32_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b2_lastuse));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // tcgen05.mma.ws.cta_group::1.kind::f16.collector::b2::lastuse [d_tmem], [a_tmem], b_desc, idesc,
+        // enable_input_d, zero_column_mask_desc;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(
+            cuda::ptx::cta_group_1_t, cuda::ptx::kind_f16_t, uint32_t, uint32_t, uint64_t, uint32_t, bool, uint64_t)>(
+            cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b2_lastuse));
+          // tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b2::lastuse [d_tmem], [a_tmem], b_desc, idesc,
+          // enable_input_d, zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_tf32_t, uint32_t, uint32_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b2_lastuse));
+          // tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b2::lastuse [d_tmem], [a_tmem], b_desc, idesc,
+          // enable_input_d, zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_f8f6f4_t, uint32_t, uint32_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b2_lastuse));
+          // tcgen05.mma.ws.cta_group::1.kind::i8.collector::b2::lastuse [d_tmem], [a_tmem], b_desc, idesc,
+          // enable_input_d, zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_i8_t, uint32_t, uint32_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b2_lastuse));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tcgen05.mma.ws.cta_group::1.kind::f16.collector::b2::lastuse [d_tmem], [a_tmem], b_desc, idesc,
+        // enable_input_d;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(
+            cuda::ptx::cta_group_1_t, cuda::ptx::kind_f16_t, uint32_t, uint32_t, uint64_t, uint32_t, bool)>(
+            cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b2_lastuse));
+          // tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b2::lastuse [d_tmem], [a_tmem], b_desc, idesc,
+          // enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_tf32_t, uint32_t, uint32_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b2_lastuse));
+          // tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b2::lastuse [d_tmem], [a_tmem], b_desc, idesc,
+          // enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_f8f6f4_t, uint32_t, uint32_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b2_lastuse));
+          // tcgen05.mma.ws.cta_group::1.kind::i8.collector::b2::lastuse [d_tmem], [a_tmem], b_desc, idesc,
+          // enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_i8_t, uint32_t, uint32_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b2_lastuse));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // tcgen05.mma.ws.cta_group::1.kind::f16.collector::b2::lastuse [d_tmem], [a_tmem], b_desc, idesc,
+        // enable_input_d;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(
+            cuda::ptx::cta_group_1_t, cuda::ptx::kind_f16_t, uint32_t, uint32_t, uint64_t, uint32_t, bool)>(
+            cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b2_lastuse));
+          // tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b2::lastuse [d_tmem], [a_tmem], b_desc, idesc,
+          // enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_tf32_t, uint32_t, uint32_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b2_lastuse));
+          // tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b2::lastuse [d_tmem], [a_tmem], b_desc, idesc,
+          // enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_f8f6f4_t, uint32_t, uint32_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b2_lastuse));
+          // tcgen05.mma.ws.cta_group::1.kind::i8.collector::b2::lastuse [d_tmem], [a_tmem], b_desc, idesc,
+          // enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_i8_t, uint32_t, uint32_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b2_lastuse));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tcgen05.mma.ws.cta_group::1.kind::f16.collector::b2::discard [d_tmem], a_desc, b_desc, idesc, enable_input_d,
+        // zero_column_mask_desc;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(
+            cuda::ptx::cta_group_1_t, cuda::ptx::kind_f16_t, uint32_t, uint64_t, uint64_t, uint32_t, bool, uint64_t)>(
+            cuda::ptx::tcgen05_mma_ws_collector_b2_discard));
+          // tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b2::discard [d_tmem], a_desc, b_desc, idesc,
+          // enable_input_d, zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_tf32_t, uint32_t, uint64_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b2_discard));
+          // tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b2::discard [d_tmem], a_desc, b_desc, idesc,
+          // enable_input_d, zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_f8f6f4_t, uint32_t, uint64_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b2_discard));
+          // tcgen05.mma.ws.cta_group::1.kind::i8.collector::b2::discard [d_tmem], a_desc, b_desc, idesc,
+          // enable_input_d, zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_i8_t, uint32_t, uint64_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b2_discard));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // tcgen05.mma.ws.cta_group::1.kind::f16.collector::b2::discard [d_tmem], a_desc, b_desc, idesc, enable_input_d,
+        // zero_column_mask_desc;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(
+            cuda::ptx::cta_group_1_t, cuda::ptx::kind_f16_t, uint32_t, uint64_t, uint64_t, uint32_t, bool, uint64_t)>(
+            cuda::ptx::tcgen05_mma_ws_collector_b2_discard));
+          // tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b2::discard [d_tmem], a_desc, b_desc, idesc,
+          // enable_input_d, zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_tf32_t, uint32_t, uint64_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b2_discard));
+          // tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b2::discard [d_tmem], a_desc, b_desc, idesc,
+          // enable_input_d, zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_f8f6f4_t, uint32_t, uint64_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b2_discard));
+          // tcgen05.mma.ws.cta_group::1.kind::i8.collector::b2::discard [d_tmem], a_desc, b_desc, idesc,
+          // enable_input_d, zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_i8_t, uint32_t, uint64_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b2_discard));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tcgen05.mma.ws.cta_group::1.kind::f16.collector::b2::discard [d_tmem], a_desc, b_desc, idesc, enable_input_d;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(
+            cuda::ptx::cta_group_1_t, cuda::ptx::kind_f16_t, uint32_t, uint64_t, uint64_t, uint32_t, bool)>(
+            cuda::ptx::tcgen05_mma_ws_collector_b2_discard));
+          // tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b2::discard [d_tmem], a_desc, b_desc, idesc,
+          // enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_tf32_t, uint32_t, uint64_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b2_discard));
+          // tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b2::discard [d_tmem], a_desc, b_desc, idesc,
+          // enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_f8f6f4_t, uint32_t, uint64_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b2_discard));
+          // tcgen05.mma.ws.cta_group::1.kind::i8.collector::b2::discard [d_tmem], a_desc, b_desc, idesc,
+          // enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_i8_t, uint32_t, uint64_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b2_discard));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // tcgen05.mma.ws.cta_group::1.kind::f16.collector::b2::discard [d_tmem], a_desc, b_desc, idesc, enable_input_d;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(
+            cuda::ptx::cta_group_1_t, cuda::ptx::kind_f16_t, uint32_t, uint64_t, uint64_t, uint32_t, bool)>(
+            cuda::ptx::tcgen05_mma_ws_collector_b2_discard));
+          // tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b2::discard [d_tmem], a_desc, b_desc, idesc,
+          // enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_tf32_t, uint32_t, uint64_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b2_discard));
+          // tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b2::discard [d_tmem], a_desc, b_desc, idesc,
+          // enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_f8f6f4_t, uint32_t, uint64_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b2_discard));
+          // tcgen05.mma.ws.cta_group::1.kind::i8.collector::b2::discard [d_tmem], a_desc, b_desc, idesc,
+          // enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_i8_t, uint32_t, uint64_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b2_discard));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tcgen05.mma.ws.cta_group::1.kind::f16.collector::b2::discard [d_tmem], [a_tmem], b_desc, idesc,
+        // enable_input_d, zero_column_mask_desc;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(
+            cuda::ptx::cta_group_1_t, cuda::ptx::kind_f16_t, uint32_t, uint32_t, uint64_t, uint32_t, bool, uint64_t)>(
+            cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b2_discard));
+          // tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b2::discard [d_tmem], [a_tmem], b_desc, idesc,
+          // enable_input_d, zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_tf32_t, uint32_t, uint32_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b2_discard));
+          // tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b2::discard [d_tmem], [a_tmem], b_desc, idesc,
+          // enable_input_d, zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_f8f6f4_t, uint32_t, uint32_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b2_discard));
+          // tcgen05.mma.ws.cta_group::1.kind::i8.collector::b2::discard [d_tmem], [a_tmem], b_desc, idesc,
+          // enable_input_d, zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_i8_t, uint32_t, uint32_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b2_discard));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // tcgen05.mma.ws.cta_group::1.kind::f16.collector::b2::discard [d_tmem], [a_tmem], b_desc, idesc,
+        // enable_input_d, zero_column_mask_desc;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(
+            cuda::ptx::cta_group_1_t, cuda::ptx::kind_f16_t, uint32_t, uint32_t, uint64_t, uint32_t, bool, uint64_t)>(
+            cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b2_discard));
+          // tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b2::discard [d_tmem], [a_tmem], b_desc, idesc,
+          // enable_input_d, zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_tf32_t, uint32_t, uint32_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b2_discard));
+          // tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b2::discard [d_tmem], [a_tmem], b_desc, idesc,
+          // enable_input_d, zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_f8f6f4_t, uint32_t, uint32_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b2_discard));
+          // tcgen05.mma.ws.cta_group::1.kind::i8.collector::b2::discard [d_tmem], [a_tmem], b_desc, idesc,
+          // enable_input_d, zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_i8_t, uint32_t, uint32_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b2_discard));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tcgen05.mma.ws.cta_group::1.kind::f16.collector::b2::discard [d_tmem], [a_tmem], b_desc, idesc,
+        // enable_input_d;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(
+            cuda::ptx::cta_group_1_t, cuda::ptx::kind_f16_t, uint32_t, uint32_t, uint64_t, uint32_t, bool)>(
+            cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b2_discard));
+          // tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b2::discard [d_tmem], [a_tmem], b_desc, idesc,
+          // enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_tf32_t, uint32_t, uint32_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b2_discard));
+          // tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b2::discard [d_tmem], [a_tmem], b_desc, idesc,
+          // enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_f8f6f4_t, uint32_t, uint32_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b2_discard));
+          // tcgen05.mma.ws.cta_group::1.kind::i8.collector::b2::discard [d_tmem], [a_tmem], b_desc, idesc,
+          // enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_i8_t, uint32_t, uint32_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b2_discard));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // tcgen05.mma.ws.cta_group::1.kind::f16.collector::b2::discard [d_tmem], [a_tmem], b_desc, idesc,
+        // enable_input_d;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(
+            cuda::ptx::cta_group_1_t, cuda::ptx::kind_f16_t, uint32_t, uint32_t, uint64_t, uint32_t, bool)>(
+            cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b2_discard));
+          // tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b2::discard [d_tmem], [a_tmem], b_desc, idesc,
+          // enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_tf32_t, uint32_t, uint32_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b2_discard));
+          // tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b2::discard [d_tmem], [a_tmem], b_desc, idesc,
+          // enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_f8f6f4_t, uint32_t, uint32_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b2_discard));
+          // tcgen05.mma.ws.cta_group::1.kind::i8.collector::b2::discard [d_tmem], [a_tmem], b_desc, idesc,
+          // enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_i8_t, uint32_t, uint32_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b2_discard));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tcgen05.mma.ws.cta_group::1.kind::f16.collector::b3::fill [d_tmem], a_desc, b_desc, idesc, enable_input_d,
+        // zero_column_mask_desc;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(
+            cuda::ptx::cta_group_1_t, cuda::ptx::kind_f16_t, uint32_t, uint64_t, uint64_t, uint32_t, bool, uint64_t)>(
+            cuda::ptx::tcgen05_mma_ws_collector_b3_fill));
+          // tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b3::fill [d_tmem], a_desc, b_desc, idesc,
+          // enable_input_d, zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_tf32_t, uint32_t, uint64_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b3_fill));
+          // tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b3::fill [d_tmem], a_desc, b_desc, idesc,
+          // enable_input_d, zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_f8f6f4_t, uint32_t, uint64_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b3_fill));
+          // tcgen05.mma.ws.cta_group::1.kind::i8.collector::b3::fill [d_tmem], a_desc, b_desc, idesc, enable_input_d,
+          // zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_i8_t, uint32_t, uint64_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b3_fill));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // tcgen05.mma.ws.cta_group::1.kind::f16.collector::b3::fill [d_tmem], a_desc, b_desc, idesc, enable_input_d,
+        // zero_column_mask_desc;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(
+            cuda::ptx::cta_group_1_t, cuda::ptx::kind_f16_t, uint32_t, uint64_t, uint64_t, uint32_t, bool, uint64_t)>(
+            cuda::ptx::tcgen05_mma_ws_collector_b3_fill));
+          // tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b3::fill [d_tmem], a_desc, b_desc, idesc,
+          // enable_input_d, zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_tf32_t, uint32_t, uint64_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b3_fill));
+          // tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b3::fill [d_tmem], a_desc, b_desc, idesc,
+          // enable_input_d, zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_f8f6f4_t, uint32_t, uint64_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b3_fill));
+          // tcgen05.mma.ws.cta_group::1.kind::i8.collector::b3::fill [d_tmem], a_desc, b_desc, idesc, enable_input_d,
+          // zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_i8_t, uint32_t, uint64_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b3_fill));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tcgen05.mma.ws.cta_group::1.kind::f16.collector::b3::fill [d_tmem], a_desc, b_desc, idesc, enable_input_d;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(
+            cuda::ptx::cta_group_1_t, cuda::ptx::kind_f16_t, uint32_t, uint64_t, uint64_t, uint32_t, bool)>(
+            cuda::ptx::tcgen05_mma_ws_collector_b3_fill));
+          // tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b3::fill [d_tmem], a_desc, b_desc, idesc, enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_tf32_t, uint32_t, uint64_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b3_fill));
+          // tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b3::fill [d_tmem], a_desc, b_desc, idesc,
+          // enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_f8f6f4_t, uint32_t, uint64_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b3_fill));
+          // tcgen05.mma.ws.cta_group::1.kind::i8.collector::b3::fill [d_tmem], a_desc, b_desc, idesc, enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_i8_t, uint32_t, uint64_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b3_fill));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // tcgen05.mma.ws.cta_group::1.kind::f16.collector::b3::fill [d_tmem], a_desc, b_desc, idesc, enable_input_d;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(
+            cuda::ptx::cta_group_1_t, cuda::ptx::kind_f16_t, uint32_t, uint64_t, uint64_t, uint32_t, bool)>(
+            cuda::ptx::tcgen05_mma_ws_collector_b3_fill));
+          // tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b3::fill [d_tmem], a_desc, b_desc, idesc, enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_tf32_t, uint32_t, uint64_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b3_fill));
+          // tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b3::fill [d_tmem], a_desc, b_desc, idesc,
+          // enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_f8f6f4_t, uint32_t, uint64_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b3_fill));
+          // tcgen05.mma.ws.cta_group::1.kind::i8.collector::b3::fill [d_tmem], a_desc, b_desc, idesc, enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_i8_t, uint32_t, uint64_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b3_fill));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tcgen05.mma.ws.cta_group::1.kind::f16.collector::b3::fill [d_tmem], [a_tmem], b_desc, idesc, enable_input_d,
+        // zero_column_mask_desc;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(
+            cuda::ptx::cta_group_1_t, cuda::ptx::kind_f16_t, uint32_t, uint32_t, uint64_t, uint32_t, bool, uint64_t)>(
+            cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b3_fill));
+          // tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b3::fill [d_tmem], [a_tmem], b_desc, idesc,
+          // enable_input_d, zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_tf32_t, uint32_t, uint32_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b3_fill));
+          // tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b3::fill [d_tmem], [a_tmem], b_desc, idesc,
+          // enable_input_d, zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_f8f6f4_t, uint32_t, uint32_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b3_fill));
+          // tcgen05.mma.ws.cta_group::1.kind::i8.collector::b3::fill [d_tmem], [a_tmem], b_desc, idesc,
+          // enable_input_d, zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_i8_t, uint32_t, uint32_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b3_fill));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // tcgen05.mma.ws.cta_group::1.kind::f16.collector::b3::fill [d_tmem], [a_tmem], b_desc, idesc, enable_input_d,
+        // zero_column_mask_desc;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(
+            cuda::ptx::cta_group_1_t, cuda::ptx::kind_f16_t, uint32_t, uint32_t, uint64_t, uint32_t, bool, uint64_t)>(
+            cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b3_fill));
+          // tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b3::fill [d_tmem], [a_tmem], b_desc, idesc,
+          // enable_input_d, zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_tf32_t, uint32_t, uint32_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b3_fill));
+          // tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b3::fill [d_tmem], [a_tmem], b_desc, idesc,
+          // enable_input_d, zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_f8f6f4_t, uint32_t, uint32_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b3_fill));
+          // tcgen05.mma.ws.cta_group::1.kind::i8.collector::b3::fill [d_tmem], [a_tmem], b_desc, idesc,
+          // enable_input_d, zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_i8_t, uint32_t, uint32_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b3_fill));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tcgen05.mma.ws.cta_group::1.kind::f16.collector::b3::fill [d_tmem], [a_tmem], b_desc, idesc, enable_input_d;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(
+            cuda::ptx::cta_group_1_t, cuda::ptx::kind_f16_t, uint32_t, uint32_t, uint64_t, uint32_t, bool)>(
+            cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b3_fill));
+          // tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b3::fill [d_tmem], [a_tmem], b_desc, idesc,
+          // enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_tf32_t, uint32_t, uint32_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b3_fill));
+          // tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b3::fill [d_tmem], [a_tmem], b_desc, idesc,
+          // enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_f8f6f4_t, uint32_t, uint32_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b3_fill));
+          // tcgen05.mma.ws.cta_group::1.kind::i8.collector::b3::fill [d_tmem], [a_tmem], b_desc, idesc, enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_i8_t, uint32_t, uint32_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b3_fill));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // tcgen05.mma.ws.cta_group::1.kind::f16.collector::b3::fill [d_tmem], [a_tmem], b_desc, idesc, enable_input_d;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(
+            cuda::ptx::cta_group_1_t, cuda::ptx::kind_f16_t, uint32_t, uint32_t, uint64_t, uint32_t, bool)>(
+            cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b3_fill));
+          // tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b3::fill [d_tmem], [a_tmem], b_desc, idesc,
+          // enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_tf32_t, uint32_t, uint32_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b3_fill));
+          // tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b3::fill [d_tmem], [a_tmem], b_desc, idesc,
+          // enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_f8f6f4_t, uint32_t, uint32_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b3_fill));
+          // tcgen05.mma.ws.cta_group::1.kind::i8.collector::b3::fill [d_tmem], [a_tmem], b_desc, idesc, enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_i8_t, uint32_t, uint32_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b3_fill));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tcgen05.mma.ws.cta_group::1.kind::f16.collector::b3::use [d_tmem], a_desc, b_desc, idesc, enable_input_d,
+        // zero_column_mask_desc;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(
+            cuda::ptx::cta_group_1_t, cuda::ptx::kind_f16_t, uint32_t, uint64_t, uint64_t, uint32_t, bool, uint64_t)>(
+            cuda::ptx::tcgen05_mma_ws_collector_b3_use));
+          // tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b3::use [d_tmem], a_desc, b_desc, idesc,
+          // enable_input_d, zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_tf32_t, uint32_t, uint64_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b3_use));
+          // tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b3::use [d_tmem], a_desc, b_desc, idesc,
+          // enable_input_d, zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_f8f6f4_t, uint32_t, uint64_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b3_use));
+          // tcgen05.mma.ws.cta_group::1.kind::i8.collector::b3::use [d_tmem], a_desc, b_desc, idesc, enable_input_d,
+          // zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_i8_t, uint32_t, uint64_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b3_use));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // tcgen05.mma.ws.cta_group::1.kind::f16.collector::b3::use [d_tmem], a_desc, b_desc, idesc, enable_input_d,
+        // zero_column_mask_desc;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(
+            cuda::ptx::cta_group_1_t, cuda::ptx::kind_f16_t, uint32_t, uint64_t, uint64_t, uint32_t, bool, uint64_t)>(
+            cuda::ptx::tcgen05_mma_ws_collector_b3_use));
+          // tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b3::use [d_tmem], a_desc, b_desc, idesc,
+          // enable_input_d, zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_tf32_t, uint32_t, uint64_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b3_use));
+          // tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b3::use [d_tmem], a_desc, b_desc, idesc,
+          // enable_input_d, zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_f8f6f4_t, uint32_t, uint64_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b3_use));
+          // tcgen05.mma.ws.cta_group::1.kind::i8.collector::b3::use [d_tmem], a_desc, b_desc, idesc, enable_input_d,
+          // zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_i8_t, uint32_t, uint64_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b3_use));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tcgen05.mma.ws.cta_group::1.kind::f16.collector::b3::use [d_tmem], a_desc, b_desc, idesc, enable_input_d;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(
+            cuda::ptx::cta_group_1_t, cuda::ptx::kind_f16_t, uint32_t, uint64_t, uint64_t, uint32_t, bool)>(
+            cuda::ptx::tcgen05_mma_ws_collector_b3_use));
+          // tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b3::use [d_tmem], a_desc, b_desc, idesc, enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_tf32_t, uint32_t, uint64_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b3_use));
+          // tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b3::use [d_tmem], a_desc, b_desc, idesc,
+          // enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_f8f6f4_t, uint32_t, uint64_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b3_use));
+          // tcgen05.mma.ws.cta_group::1.kind::i8.collector::b3::use [d_tmem], a_desc, b_desc, idesc, enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_i8_t, uint32_t, uint64_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b3_use));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // tcgen05.mma.ws.cta_group::1.kind::f16.collector::b3::use [d_tmem], a_desc, b_desc, idesc, enable_input_d;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(
+            cuda::ptx::cta_group_1_t, cuda::ptx::kind_f16_t, uint32_t, uint64_t, uint64_t, uint32_t, bool)>(
+            cuda::ptx::tcgen05_mma_ws_collector_b3_use));
+          // tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b3::use [d_tmem], a_desc, b_desc, idesc, enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_tf32_t, uint32_t, uint64_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b3_use));
+          // tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b3::use [d_tmem], a_desc, b_desc, idesc,
+          // enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_f8f6f4_t, uint32_t, uint64_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b3_use));
+          // tcgen05.mma.ws.cta_group::1.kind::i8.collector::b3::use [d_tmem], a_desc, b_desc, idesc, enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_i8_t, uint32_t, uint64_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b3_use));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tcgen05.mma.ws.cta_group::1.kind::f16.collector::b3::use [d_tmem], [a_tmem], b_desc, idesc, enable_input_d,
+        // zero_column_mask_desc;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(
+            cuda::ptx::cta_group_1_t, cuda::ptx::kind_f16_t, uint32_t, uint32_t, uint64_t, uint32_t, bool, uint64_t)>(
+            cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b3_use));
+          // tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b3::use [d_tmem], [a_tmem], b_desc, idesc,
+          // enable_input_d, zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_tf32_t, uint32_t, uint32_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b3_use));
+          // tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b3::use [d_tmem], [a_tmem], b_desc, idesc,
+          // enable_input_d, zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_f8f6f4_t, uint32_t, uint32_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b3_use));
+          // tcgen05.mma.ws.cta_group::1.kind::i8.collector::b3::use [d_tmem], [a_tmem], b_desc, idesc,
+          // enable_input_d, zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_i8_t, uint32_t, uint32_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b3_use));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // tcgen05.mma.ws.cta_group::1.kind::f16.collector::b3::use [d_tmem], [a_tmem], b_desc, idesc, enable_input_d,
+        // zero_column_mask_desc;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(
+            cuda::ptx::cta_group_1_t, cuda::ptx::kind_f16_t, uint32_t, uint32_t, uint64_t, uint32_t, bool, uint64_t)>(
+            cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b3_use));
+          // tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b3::use [d_tmem], [a_tmem], b_desc, idesc,
+          // enable_input_d, zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_tf32_t, uint32_t, uint32_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b3_use));
+          // tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b3::use [d_tmem], [a_tmem], b_desc, idesc,
+          // enable_input_d, zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_f8f6f4_t, uint32_t, uint32_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b3_use));
+          // tcgen05.mma.ws.cta_group::1.kind::i8.collector::b3::use [d_tmem], [a_tmem], b_desc, idesc,
+          // enable_input_d, zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_i8_t, uint32_t, uint32_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b3_use));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tcgen05.mma.ws.cta_group::1.kind::f16.collector::b3::use [d_tmem], [a_tmem], b_desc, idesc, enable_input_d;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(
+            cuda::ptx::cta_group_1_t, cuda::ptx::kind_f16_t, uint32_t, uint32_t, uint64_t, uint32_t, bool)>(
+            cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b3_use));
+          // tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b3::use [d_tmem], [a_tmem], b_desc, idesc,
+          // enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_tf32_t, uint32_t, uint32_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b3_use));
+          // tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b3::use [d_tmem], [a_tmem], b_desc, idesc,
+          // enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_f8f6f4_t, uint32_t, uint32_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b3_use));
+          // tcgen05.mma.ws.cta_group::1.kind::i8.collector::b3::use [d_tmem], [a_tmem], b_desc, idesc, enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_i8_t, uint32_t, uint32_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b3_use));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // tcgen05.mma.ws.cta_group::1.kind::f16.collector::b3::use [d_tmem], [a_tmem], b_desc, idesc, enable_input_d;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(
+            cuda::ptx::cta_group_1_t, cuda::ptx::kind_f16_t, uint32_t, uint32_t, uint64_t, uint32_t, bool)>(
+            cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b3_use));
+          // tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b3::use [d_tmem], [a_tmem], b_desc, idesc,
+          // enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_tf32_t, uint32_t, uint32_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b3_use));
+          // tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b3::use [d_tmem], [a_tmem], b_desc, idesc,
+          // enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_f8f6f4_t, uint32_t, uint32_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b3_use));
+          // tcgen05.mma.ws.cta_group::1.kind::i8.collector::b3::use [d_tmem], [a_tmem], b_desc, idesc, enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_i8_t, uint32_t, uint32_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b3_use));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tcgen05.mma.ws.cta_group::1.kind::f16.collector::b3::lastuse [d_tmem], a_desc, b_desc, idesc, enable_input_d,
+        // zero_column_mask_desc;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(
+            cuda::ptx::cta_group_1_t, cuda::ptx::kind_f16_t, uint32_t, uint64_t, uint64_t, uint32_t, bool, uint64_t)>(
+            cuda::ptx::tcgen05_mma_ws_collector_b3_lastuse));
+          // tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b3::lastuse [d_tmem], a_desc, b_desc, idesc,
+          // enable_input_d, zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_tf32_t, uint32_t, uint64_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b3_lastuse));
+          // tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b3::lastuse [d_tmem], a_desc, b_desc, idesc,
+          // enable_input_d, zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_f8f6f4_t, uint32_t, uint64_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b3_lastuse));
+          // tcgen05.mma.ws.cta_group::1.kind::i8.collector::b3::lastuse [d_tmem], a_desc, b_desc, idesc,
+          // enable_input_d, zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_i8_t, uint32_t, uint64_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b3_lastuse));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // tcgen05.mma.ws.cta_group::1.kind::f16.collector::b3::lastuse [d_tmem], a_desc, b_desc, idesc, enable_input_d,
+        // zero_column_mask_desc;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(
+            cuda::ptx::cta_group_1_t, cuda::ptx::kind_f16_t, uint32_t, uint64_t, uint64_t, uint32_t, bool, uint64_t)>(
+            cuda::ptx::tcgen05_mma_ws_collector_b3_lastuse));
+          // tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b3::lastuse [d_tmem], a_desc, b_desc, idesc,
+          // enable_input_d, zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_tf32_t, uint32_t, uint64_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b3_lastuse));
+          // tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b3::lastuse [d_tmem], a_desc, b_desc, idesc,
+          // enable_input_d, zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_f8f6f4_t, uint32_t, uint64_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b3_lastuse));
+          // tcgen05.mma.ws.cta_group::1.kind::i8.collector::b3::lastuse [d_tmem], a_desc, b_desc, idesc,
+          // enable_input_d, zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_i8_t, uint32_t, uint64_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b3_lastuse));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tcgen05.mma.ws.cta_group::1.kind::f16.collector::b3::lastuse [d_tmem], a_desc, b_desc, idesc, enable_input_d;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(
+            cuda::ptx::cta_group_1_t, cuda::ptx::kind_f16_t, uint32_t, uint64_t, uint64_t, uint32_t, bool)>(
+            cuda::ptx::tcgen05_mma_ws_collector_b3_lastuse));
+          // tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b3::lastuse [d_tmem], a_desc, b_desc, idesc,
+          // enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_tf32_t, uint32_t, uint64_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b3_lastuse));
+          // tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b3::lastuse [d_tmem], a_desc, b_desc, idesc,
+          // enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_f8f6f4_t, uint32_t, uint64_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b3_lastuse));
+          // tcgen05.mma.ws.cta_group::1.kind::i8.collector::b3::lastuse [d_tmem], a_desc, b_desc, idesc,
+          // enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_i8_t, uint32_t, uint64_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b3_lastuse));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // tcgen05.mma.ws.cta_group::1.kind::f16.collector::b3::lastuse [d_tmem], a_desc, b_desc, idesc, enable_input_d;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(
+            cuda::ptx::cta_group_1_t, cuda::ptx::kind_f16_t, uint32_t, uint64_t, uint64_t, uint32_t, bool)>(
+            cuda::ptx::tcgen05_mma_ws_collector_b3_lastuse));
+          // tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b3::lastuse [d_tmem], a_desc, b_desc, idesc,
+          // enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_tf32_t, uint32_t, uint64_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b3_lastuse));
+          // tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b3::lastuse [d_tmem], a_desc, b_desc, idesc,
+          // enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_f8f6f4_t, uint32_t, uint64_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b3_lastuse));
+          // tcgen05.mma.ws.cta_group::1.kind::i8.collector::b3::lastuse [d_tmem], a_desc, b_desc, idesc,
+          // enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_i8_t, uint32_t, uint64_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b3_lastuse));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tcgen05.mma.ws.cta_group::1.kind::f16.collector::b3::lastuse [d_tmem], [a_tmem], b_desc, idesc,
+        // enable_input_d, zero_column_mask_desc;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(
+            cuda::ptx::cta_group_1_t, cuda::ptx::kind_f16_t, uint32_t, uint32_t, uint64_t, uint32_t, bool, uint64_t)>(
+            cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b3_lastuse));
+          // tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b3::lastuse [d_tmem], [a_tmem], b_desc, idesc,
+          // enable_input_d, zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_tf32_t, uint32_t, uint32_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b3_lastuse));
+          // tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b3::lastuse [d_tmem], [a_tmem], b_desc, idesc,
+          // enable_input_d, zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_f8f6f4_t, uint32_t, uint32_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b3_lastuse));
+          // tcgen05.mma.ws.cta_group::1.kind::i8.collector::b3::lastuse [d_tmem], [a_tmem], b_desc, idesc,
+          // enable_input_d, zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_i8_t, uint32_t, uint32_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b3_lastuse));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // tcgen05.mma.ws.cta_group::1.kind::f16.collector::b3::lastuse [d_tmem], [a_tmem], b_desc, idesc,
+        // enable_input_d, zero_column_mask_desc;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(
+            cuda::ptx::cta_group_1_t, cuda::ptx::kind_f16_t, uint32_t, uint32_t, uint64_t, uint32_t, bool, uint64_t)>(
+            cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b3_lastuse));
+          // tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b3::lastuse [d_tmem], [a_tmem], b_desc, idesc,
+          // enable_input_d, zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_tf32_t, uint32_t, uint32_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b3_lastuse));
+          // tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b3::lastuse [d_tmem], [a_tmem], b_desc, idesc,
+          // enable_input_d, zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_f8f6f4_t, uint32_t, uint32_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b3_lastuse));
+          // tcgen05.mma.ws.cta_group::1.kind::i8.collector::b3::lastuse [d_tmem], [a_tmem], b_desc, idesc,
+          // enable_input_d, zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_i8_t, uint32_t, uint32_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b3_lastuse));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tcgen05.mma.ws.cta_group::1.kind::f16.collector::b3::lastuse [d_tmem], [a_tmem], b_desc, idesc,
+        // enable_input_d;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(
+            cuda::ptx::cta_group_1_t, cuda::ptx::kind_f16_t, uint32_t, uint32_t, uint64_t, uint32_t, bool)>(
+            cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b3_lastuse));
+          // tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b3::lastuse [d_tmem], [a_tmem], b_desc, idesc,
+          // enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_tf32_t, uint32_t, uint32_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b3_lastuse));
+          // tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b3::lastuse [d_tmem], [a_tmem], b_desc, idesc,
+          // enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_f8f6f4_t, uint32_t, uint32_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b3_lastuse));
+          // tcgen05.mma.ws.cta_group::1.kind::i8.collector::b3::lastuse [d_tmem], [a_tmem], b_desc, idesc,
+          // enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_i8_t, uint32_t, uint32_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b3_lastuse));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // tcgen05.mma.ws.cta_group::1.kind::f16.collector::b3::lastuse [d_tmem], [a_tmem], b_desc, idesc,
+        // enable_input_d;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(
+            cuda::ptx::cta_group_1_t, cuda::ptx::kind_f16_t, uint32_t, uint32_t, uint64_t, uint32_t, bool)>(
+            cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b3_lastuse));
+          // tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b3::lastuse [d_tmem], [a_tmem], b_desc, idesc,
+          // enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_tf32_t, uint32_t, uint32_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b3_lastuse));
+          // tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b3::lastuse [d_tmem], [a_tmem], b_desc, idesc,
+          // enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_f8f6f4_t, uint32_t, uint32_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b3_lastuse));
+          // tcgen05.mma.ws.cta_group::1.kind::i8.collector::b3::lastuse [d_tmem], [a_tmem], b_desc, idesc,
+          // enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_i8_t, uint32_t, uint32_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b3_lastuse));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tcgen05.mma.ws.cta_group::1.kind::f16.collector::b3::discard [d_tmem], a_desc, b_desc, idesc, enable_input_d,
+        // zero_column_mask_desc;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(
+            cuda::ptx::cta_group_1_t, cuda::ptx::kind_f16_t, uint32_t, uint64_t, uint64_t, uint32_t, bool, uint64_t)>(
+            cuda::ptx::tcgen05_mma_ws_collector_b3_discard));
+          // tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b3::discard [d_tmem], a_desc, b_desc, idesc,
+          // enable_input_d, zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_tf32_t, uint32_t, uint64_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b3_discard));
+          // tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b3::discard [d_tmem], a_desc, b_desc, idesc,
+          // enable_input_d, zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_f8f6f4_t, uint32_t, uint64_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b3_discard));
+          // tcgen05.mma.ws.cta_group::1.kind::i8.collector::b3::discard [d_tmem], a_desc, b_desc, idesc,
+          // enable_input_d, zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_i8_t, uint32_t, uint64_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b3_discard));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // tcgen05.mma.ws.cta_group::1.kind::f16.collector::b3::discard [d_tmem], a_desc, b_desc, idesc, enable_input_d,
+        // zero_column_mask_desc;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(
+            cuda::ptx::cta_group_1_t, cuda::ptx::kind_f16_t, uint32_t, uint64_t, uint64_t, uint32_t, bool, uint64_t)>(
+            cuda::ptx::tcgen05_mma_ws_collector_b3_discard));
+          // tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b3::discard [d_tmem], a_desc, b_desc, idesc,
+          // enable_input_d, zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_tf32_t, uint32_t, uint64_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b3_discard));
+          // tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b3::discard [d_tmem], a_desc, b_desc, idesc,
+          // enable_input_d, zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_f8f6f4_t, uint32_t, uint64_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b3_discard));
+          // tcgen05.mma.ws.cta_group::1.kind::i8.collector::b3::discard [d_tmem], a_desc, b_desc, idesc,
+          // enable_input_d, zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_i8_t, uint32_t, uint64_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b3_discard));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tcgen05.mma.ws.cta_group::1.kind::f16.collector::b3::discard [d_tmem], a_desc, b_desc, idesc, enable_input_d;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(
+            cuda::ptx::cta_group_1_t, cuda::ptx::kind_f16_t, uint32_t, uint64_t, uint64_t, uint32_t, bool)>(
+            cuda::ptx::tcgen05_mma_ws_collector_b3_discard));
+          // tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b3::discard [d_tmem], a_desc, b_desc, idesc,
+          // enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_tf32_t, uint32_t, uint64_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b3_discard));
+          // tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b3::discard [d_tmem], a_desc, b_desc, idesc,
+          // enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_f8f6f4_t, uint32_t, uint64_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b3_discard));
+          // tcgen05.mma.ws.cta_group::1.kind::i8.collector::b3::discard [d_tmem], a_desc, b_desc, idesc,
+          // enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_i8_t, uint32_t, uint64_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b3_discard));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // tcgen05.mma.ws.cta_group::1.kind::f16.collector::b3::discard [d_tmem], a_desc, b_desc, idesc, enable_input_d;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(
+            cuda::ptx::cta_group_1_t, cuda::ptx::kind_f16_t, uint32_t, uint64_t, uint64_t, uint32_t, bool)>(
+            cuda::ptx::tcgen05_mma_ws_collector_b3_discard));
+          // tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b3::discard [d_tmem], a_desc, b_desc, idesc,
+          // enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_tf32_t, uint32_t, uint64_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b3_discard));
+          // tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b3::discard [d_tmem], a_desc, b_desc, idesc,
+          // enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_f8f6f4_t, uint32_t, uint64_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b3_discard));
+          // tcgen05.mma.ws.cta_group::1.kind::i8.collector::b3::discard [d_tmem], a_desc, b_desc, idesc,
+          // enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_i8_t, uint32_t, uint64_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_collector_b3_discard));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tcgen05.mma.ws.cta_group::1.kind::f16.collector::b3::discard [d_tmem], [a_tmem], b_desc, idesc,
+        // enable_input_d, zero_column_mask_desc;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(
+            cuda::ptx::cta_group_1_t, cuda::ptx::kind_f16_t, uint32_t, uint32_t, uint64_t, uint32_t, bool, uint64_t)>(
+            cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b3_discard));
+          // tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b3::discard [d_tmem], [a_tmem], b_desc, idesc,
+          // enable_input_d, zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_tf32_t, uint32_t, uint32_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b3_discard));
+          // tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b3::discard [d_tmem], [a_tmem], b_desc, idesc,
+          // enable_input_d, zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_f8f6f4_t, uint32_t, uint32_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b3_discard));
+          // tcgen05.mma.ws.cta_group::1.kind::i8.collector::b3::discard [d_tmem], [a_tmem], b_desc, idesc,
+          // enable_input_d, zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_i8_t, uint32_t, uint32_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b3_discard));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // tcgen05.mma.ws.cta_group::1.kind::f16.collector::b3::discard [d_tmem], [a_tmem], b_desc, idesc,
+        // enable_input_d, zero_column_mask_desc;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(
+            cuda::ptx::cta_group_1_t, cuda::ptx::kind_f16_t, uint32_t, uint32_t, uint64_t, uint32_t, bool, uint64_t)>(
+            cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b3_discard));
+          // tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b3::discard [d_tmem], [a_tmem], b_desc, idesc,
+          // enable_input_d, zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_tf32_t, uint32_t, uint32_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b3_discard));
+          // tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b3::discard [d_tmem], [a_tmem], b_desc, idesc,
+          // enable_input_d, zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_f8f6f4_t, uint32_t, uint32_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b3_discard));
+          // tcgen05.mma.ws.cta_group::1.kind::i8.collector::b3::discard [d_tmem], [a_tmem], b_desc, idesc,
+          // enable_input_d, zero_column_mask_desc;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_i8_t, uint32_t, uint32_t, uint64_t, uint32_t, bool, uint64_t)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b3_discard));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tcgen05.mma.ws.cta_group::1.kind::f16.collector::b3::discard [d_tmem], [a_tmem], b_desc, idesc,
+        // enable_input_d;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(
+            cuda::ptx::cta_group_1_t, cuda::ptx::kind_f16_t, uint32_t, uint32_t, uint64_t, uint32_t, bool)>(
+            cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b3_discard));
+          // tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b3::discard [d_tmem], [a_tmem], b_desc, idesc,
+          // enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_tf32_t, uint32_t, uint32_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b3_discard));
+          // tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b3::discard [d_tmem], [a_tmem], b_desc, idesc,
+          // enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_f8f6f4_t, uint32_t, uint32_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b3_discard));
+          // tcgen05.mma.ws.cta_group::1.kind::i8.collector::b3::discard [d_tmem], [a_tmem], b_desc, idesc,
+          // enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_i8_t, uint32_t, uint32_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b3_discard));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // tcgen05.mma.ws.cta_group::1.kind::f16.collector::b3::discard [d_tmem], [a_tmem], b_desc, idesc,
+        // enable_input_d;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(
+            cuda::ptx::cta_group_1_t, cuda::ptx::kind_f16_t, uint32_t, uint32_t, uint64_t, uint32_t, bool)>(
+            cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b3_discard));
+          // tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b3::discard [d_tmem], [a_tmem], b_desc, idesc,
+          // enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_tf32_t, uint32_t, uint32_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b3_discard));
+          // tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b3::discard [d_tmem], [a_tmem], b_desc, idesc,
+          // enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_f8f6f4_t, uint32_t, uint32_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b3_discard));
+          // tcgen05.mma.ws.cta_group::1.kind::i8.collector::b3::discard [d_tmem], [a_tmem], b_desc, idesc,
+          // enable_input_d;
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(
+                cuda::ptx::cta_group_1_t, cuda::ptx::kind_i8_t, uint32_t, uint32_t, uint64_t, uint32_t, bool)>(
+                cuda::ptx::tcgen05_mma_ws_tmem_a_collector_b3_discard));));
+#endif // __cccl_ptx_isa >= 860
+}
diff --git a/libcudacxx/test/libcudacxx/cuda/ptx/generated/tcgen05_shift.h b/libcudacxx/test/libcudacxx/cuda/ptx/generated/tcgen05_shift.h
new file mode 100644
index 00000000000..293d2787a87
--- /dev/null
+++ b/libcudacxx/test/libcudacxx/cuda/ptx/generated/tcgen05_shift.h
@@ -0,0 +1,39 @@
+// This file was automatically generated. Do not edit.
+
+// We use a special strategy to force the generation of the PTX. This is mainly
+// a fight against dead-code-elimination in the NVVM layer.
+//
+// The reason we need this strategy is because certain older versions of ptxas
+// segfault when a non-sensical sequence of PTX is generated. So instead, we try
+// to force the instantiation and compilation to PTX of all the overloads of the
+// PTX wrapping functions.
+//
+// We do this by writing a function pointer of each overload to the kernel
+// parameter `fn_ptr`.
+//
+// Because `fn_ptr` is possibly visible outside this translation unit, the
+// compiler must compile all the functions which are stored.
+
+__global__ void test_tcgen05_shift(void** fn_ptr)
+{
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tcgen05.shift.cta_group::1.down [taddr];
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(cuda::ptx::cta_group_1_t, uint32_t)>(cuda::ptx::tcgen05_shift_down));
+          // tcgen05.shift.cta_group::2.down [taddr];
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::cta_group_2_t, uint32_t)>(cuda::ptx::tcgen05_shift_down));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // tcgen05.shift.cta_group::1.down [taddr];
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(cuda::ptx::cta_group_1_t, uint32_t)>(cuda::ptx::tcgen05_shift_down));
+          // tcgen05.shift.cta_group::2.down [taddr];
+            * fn_ptr++ = reinterpret_cast<void*>(
+              static_cast<void (*)(cuda::ptx::cta_group_2_t, uint32_t)>(cuda::ptx::tcgen05_shift_down));));
+#endif // __cccl_ptx_isa >= 860
+}
diff --git a/libcudacxx/test/libcudacxx/cuda/ptx/generated/tcgen05_st.h b/libcudacxx/test/libcudacxx/cuda/ptx/generated/tcgen05_st.h
new file mode 100644
index 00000000000..ec8cb758e5d
--- /dev/null
+++ b/libcudacxx/test/libcudacxx/cuda/ptx/generated/tcgen05_st.h
@@ -0,0 +1,1012 @@
+// This file was automatically generated. Do not edit.
+
+// We use a special strategy to force the generation of the PTX. This is mainly
+// a fight against dead-code-elimination in the NVVM layer.
+//
+// The reason we need this strategy is because certain older versions of ptxas
+// segfault when a non-sensical sequence of PTX is generated. So instead, we try
+// to force the instantiation and compilation to PTX of all the overloads of the
+// PTX wrapping functions.
+//
+// We do this by writing a function pointer of each overload to the kernel
+// parameter `fn_ptr`.
+//
+// Because `fn_ptr` is possibly visible outside this translation unit, the
+// compiler must compile all the functions which are stored.
+
+__global__ void test_tcgen05_st(void** fn_ptr)
+{
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_100a,
+               (
+                   // tcgen05.st.sync.aligned.16x64b.x1.b32 [taddr], values;
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(uint32_t, const int32_t(&)[1])>(cuda::ptx::tcgen05_st_16x64b));));
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_101a,
+               (
+                   // tcgen05.st.sync.aligned.16x64b.x1.b32 [taddr], values;
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(uint32_t, const int32_t(&)[1])>(cuda::ptx::tcgen05_st_16x64b));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_100a,
+               (
+                   // tcgen05.st.sync.aligned.16x64b.x1.unpack::16b.b32 [taddr], values;
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(uint32_t, const int32_t(&)[1])>(cuda::ptx::tcgen05_st_16x64b_unpack_16b));));
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_101a,
+               (
+                   // tcgen05.st.sync.aligned.16x64b.x1.unpack::16b.b32 [taddr], values;
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(uint32_t, const int32_t(&)[1])>(cuda::ptx::tcgen05_st_16x64b_unpack_16b));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_100a,
+               (
+                   // tcgen05.st.sync.aligned.16x64b.x2.b32 [taddr], values;
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(uint32_t, const int32_t(&)[2])>(cuda::ptx::tcgen05_st_16x64b));));
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_101a,
+               (
+                   // tcgen05.st.sync.aligned.16x64b.x2.b32 [taddr], values;
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(uint32_t, const int32_t(&)[2])>(cuda::ptx::tcgen05_st_16x64b));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_100a,
+               (
+                   // tcgen05.st.sync.aligned.16x64b.x2.unpack::16b.b32 [taddr], values;
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(uint32_t, const int32_t(&)[2])>(cuda::ptx::tcgen05_st_16x64b_unpack_16b));));
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_101a,
+               (
+                   // tcgen05.st.sync.aligned.16x64b.x2.unpack::16b.b32 [taddr], values;
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(uint32_t, const int32_t(&)[2])>(cuda::ptx::tcgen05_st_16x64b_unpack_16b));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_100a,
+               (
+                   // tcgen05.st.sync.aligned.16x64b.x4.b32 [taddr], values;
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(uint32_t, const int32_t(&)[4])>(cuda::ptx::tcgen05_st_16x64b));));
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_101a,
+               (
+                   // tcgen05.st.sync.aligned.16x64b.x4.b32 [taddr], values;
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(uint32_t, const int32_t(&)[4])>(cuda::ptx::tcgen05_st_16x64b));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_100a,
+               (
+                   // tcgen05.st.sync.aligned.16x64b.x4.unpack::16b.b32 [taddr], values;
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(uint32_t, const int32_t(&)[4])>(cuda::ptx::tcgen05_st_16x64b_unpack_16b));));
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_101a,
+               (
+                   // tcgen05.st.sync.aligned.16x64b.x4.unpack::16b.b32 [taddr], values;
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(uint32_t, const int32_t(&)[4])>(cuda::ptx::tcgen05_st_16x64b_unpack_16b));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_100a,
+               (
+                   // tcgen05.st.sync.aligned.16x64b.x8.b32 [taddr], values;
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(uint32_t, const int32_t(&)[8])>(cuda::ptx::tcgen05_st_16x64b));));
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_101a,
+               (
+                   // tcgen05.st.sync.aligned.16x64b.x8.b32 [taddr], values;
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(uint32_t, const int32_t(&)[8])>(cuda::ptx::tcgen05_st_16x64b));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_100a,
+               (
+                   // tcgen05.st.sync.aligned.16x64b.x8.unpack::16b.b32 [taddr], values;
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(uint32_t, const int32_t(&)[8])>(cuda::ptx::tcgen05_st_16x64b_unpack_16b));));
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_101a,
+               (
+                   // tcgen05.st.sync.aligned.16x64b.x8.unpack::16b.b32 [taddr], values;
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(uint32_t, const int32_t(&)[8])>(cuda::ptx::tcgen05_st_16x64b_unpack_16b));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_100a,
+               (
+                   // tcgen05.st.sync.aligned.16x64b.x16.b32 [taddr], values;
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(uint32_t, const int32_t(&)[16])>(cuda::ptx::tcgen05_st_16x64b));));
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_101a,
+               (
+                   // tcgen05.st.sync.aligned.16x64b.x16.b32 [taddr], values;
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(uint32_t, const int32_t(&)[16])>(cuda::ptx::tcgen05_st_16x64b));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_100a,
+               (
+                   // tcgen05.st.sync.aligned.16x64b.x16.unpack::16b.b32 [taddr], values;
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(uint32_t, const int32_t(&)[16])>(cuda::ptx::tcgen05_st_16x64b_unpack_16b));));
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_101a,
+               (
+                   // tcgen05.st.sync.aligned.16x64b.x16.unpack::16b.b32 [taddr], values;
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(uint32_t, const int32_t(&)[16])>(cuda::ptx::tcgen05_st_16x64b_unpack_16b));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_100a,
+               (
+                   // tcgen05.st.sync.aligned.16x64b.x32.b32 [taddr], values;
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(uint32_t, const int32_t(&)[32])>(cuda::ptx::tcgen05_st_16x64b));));
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_101a,
+               (
+                   // tcgen05.st.sync.aligned.16x64b.x32.b32 [taddr], values;
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(uint32_t, const int32_t(&)[32])>(cuda::ptx::tcgen05_st_16x64b));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_100a,
+               (
+                   // tcgen05.st.sync.aligned.16x64b.x32.unpack::16b.b32 [taddr], values;
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(uint32_t, const int32_t(&)[32])>(cuda::ptx::tcgen05_st_16x64b_unpack_16b));));
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_101a,
+               (
+                   // tcgen05.st.sync.aligned.16x64b.x32.unpack::16b.b32 [taddr], values;
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(uint32_t, const int32_t(&)[32])>(cuda::ptx::tcgen05_st_16x64b_unpack_16b));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_100a,
+               (
+                   // tcgen05.st.sync.aligned.16x64b.x64.b32 [taddr], values;
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(uint32_t, const int32_t(&)[64])>(cuda::ptx::tcgen05_st_16x64b));));
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_101a,
+               (
+                   // tcgen05.st.sync.aligned.16x64b.x64.b32 [taddr], values;
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(uint32_t, const int32_t(&)[64])>(cuda::ptx::tcgen05_st_16x64b));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_100a,
+               (
+                   // tcgen05.st.sync.aligned.16x64b.x64.unpack::16b.b32 [taddr], values;
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(uint32_t, const int32_t(&)[64])>(cuda::ptx::tcgen05_st_16x64b_unpack_16b));));
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_101a,
+               (
+                   // tcgen05.st.sync.aligned.16x64b.x64.unpack::16b.b32 [taddr], values;
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(uint32_t, const int32_t(&)[64])>(cuda::ptx::tcgen05_st_16x64b_unpack_16b));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_100a,
+               (
+                   // tcgen05.st.sync.aligned.16x64b.x128.b32 [taddr], values;
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(uint32_t, const int32_t(&)[128])>(cuda::ptx::tcgen05_st_16x64b));));
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_101a,
+               (
+                   // tcgen05.st.sync.aligned.16x64b.x128.b32 [taddr], values;
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(uint32_t, const int32_t(&)[128])>(cuda::ptx::tcgen05_st_16x64b));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_100a,
+               (
+                   // tcgen05.st.sync.aligned.16x64b.x128.unpack::16b.b32 [taddr], values;
+                   * fn_ptr++ = reinterpret_cast<void*>(static_cast<void (*)(uint32_t, const int32_t(&)[128])>(
+                     cuda::ptx::tcgen05_st_16x64b_unpack_16b));));
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_101a,
+               (
+                   // tcgen05.st.sync.aligned.16x64b.x128.unpack::16b.b32 [taddr], values;
+                   * fn_ptr++ = reinterpret_cast<void*>(static_cast<void (*)(uint32_t, const int32_t(&)[128])>(
+                     cuda::ptx::tcgen05_st_16x64b_unpack_16b));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_100a,
+               (
+                   // tcgen05.st.sync.aligned.16x128b.x1.b32 [taddr], values;
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(uint32_t, const int32_t(&)[2])>(cuda::ptx::tcgen05_st_16x128b));));
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_101a,
+               (
+                   // tcgen05.st.sync.aligned.16x128b.x1.b32 [taddr], values;
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(uint32_t, const int32_t(&)[2])>(cuda::ptx::tcgen05_st_16x128b));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_100a,
+               (
+                   // tcgen05.st.sync.aligned.16x128b.x1.unpack::16b.b32 [taddr], values;
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(uint32_t, const int32_t(&)[2])>(cuda::ptx::tcgen05_st_16x128b_unpack_16b));));
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_101a,
+               (
+                   // tcgen05.st.sync.aligned.16x128b.x1.unpack::16b.b32 [taddr], values;
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(uint32_t, const int32_t(&)[2])>(cuda::ptx::tcgen05_st_16x128b_unpack_16b));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_100a,
+               (
+                   // tcgen05.st.sync.aligned.16x128b.x2.b32 [taddr], values;
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(uint32_t, const int32_t(&)[4])>(cuda::ptx::tcgen05_st_16x128b));));
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_101a,
+               (
+                   // tcgen05.st.sync.aligned.16x128b.x2.b32 [taddr], values;
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(uint32_t, const int32_t(&)[4])>(cuda::ptx::tcgen05_st_16x128b));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_100a,
+               (
+                   // tcgen05.st.sync.aligned.16x128b.x2.unpack::16b.b32 [taddr], values;
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(uint32_t, const int32_t(&)[4])>(cuda::ptx::tcgen05_st_16x128b_unpack_16b));));
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_101a,
+               (
+                   // tcgen05.st.sync.aligned.16x128b.x2.unpack::16b.b32 [taddr], values;
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(uint32_t, const int32_t(&)[4])>(cuda::ptx::tcgen05_st_16x128b_unpack_16b));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_100a,
+               (
+                   // tcgen05.st.sync.aligned.16x128b.x4.b32 [taddr], values;
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(uint32_t, const int32_t(&)[8])>(cuda::ptx::tcgen05_st_16x128b));));
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_101a,
+               (
+                   // tcgen05.st.sync.aligned.16x128b.x4.b32 [taddr], values;
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(uint32_t, const int32_t(&)[8])>(cuda::ptx::tcgen05_st_16x128b));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_100a,
+               (
+                   // tcgen05.st.sync.aligned.16x128b.x4.unpack::16b.b32 [taddr], values;
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(uint32_t, const int32_t(&)[8])>(cuda::ptx::tcgen05_st_16x128b_unpack_16b));));
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_101a,
+               (
+                   // tcgen05.st.sync.aligned.16x128b.x4.unpack::16b.b32 [taddr], values;
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(uint32_t, const int32_t(&)[8])>(cuda::ptx::tcgen05_st_16x128b_unpack_16b));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_100a,
+               (
+                   // tcgen05.st.sync.aligned.16x128b.x8.b32 [taddr], values;
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(uint32_t, const int32_t(&)[16])>(cuda::ptx::tcgen05_st_16x128b));));
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_101a,
+               (
+                   // tcgen05.st.sync.aligned.16x128b.x8.b32 [taddr], values;
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(uint32_t, const int32_t(&)[16])>(cuda::ptx::tcgen05_st_16x128b));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_100a,
+               (
+                   // tcgen05.st.sync.aligned.16x128b.x8.unpack::16b.b32 [taddr], values;
+                   * fn_ptr++ = reinterpret_cast<void*>(static_cast<void (*)(uint32_t, const int32_t(&)[16])>(
+                     cuda::ptx::tcgen05_st_16x128b_unpack_16b));));
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_101a,
+               (
+                   // tcgen05.st.sync.aligned.16x128b.x8.unpack::16b.b32 [taddr], values;
+                   * fn_ptr++ = reinterpret_cast<void*>(static_cast<void (*)(uint32_t, const int32_t(&)[16])>(
+                     cuda::ptx::tcgen05_st_16x128b_unpack_16b));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_100a,
+               (
+                   // tcgen05.st.sync.aligned.16x128b.x16.b32 [taddr], values;
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(uint32_t, const int32_t(&)[32])>(cuda::ptx::tcgen05_st_16x128b));));
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_101a,
+               (
+                   // tcgen05.st.sync.aligned.16x128b.x16.b32 [taddr], values;
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(uint32_t, const int32_t(&)[32])>(cuda::ptx::tcgen05_st_16x128b));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_100a,
+               (
+                   // tcgen05.st.sync.aligned.16x128b.x16.unpack::16b.b32 [taddr], values;
+                   * fn_ptr++ = reinterpret_cast<void*>(static_cast<void (*)(uint32_t, const int32_t(&)[32])>(
+                     cuda::ptx::tcgen05_st_16x128b_unpack_16b));));
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_101a,
+               (
+                   // tcgen05.st.sync.aligned.16x128b.x16.unpack::16b.b32 [taddr], values;
+                   * fn_ptr++ = reinterpret_cast<void*>(static_cast<void (*)(uint32_t, const int32_t(&)[32])>(
+                     cuda::ptx::tcgen05_st_16x128b_unpack_16b));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_100a,
+               (
+                   // tcgen05.st.sync.aligned.16x128b.x32.b32 [taddr], values;
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(uint32_t, const int32_t(&)[64])>(cuda::ptx::tcgen05_st_16x128b));));
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_101a,
+               (
+                   // tcgen05.st.sync.aligned.16x128b.x32.b32 [taddr], values;
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(uint32_t, const int32_t(&)[64])>(cuda::ptx::tcgen05_st_16x128b));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_100a,
+               (
+                   // tcgen05.st.sync.aligned.16x128b.x32.unpack::16b.b32 [taddr], values;
+                   * fn_ptr++ = reinterpret_cast<void*>(static_cast<void (*)(uint32_t, const int32_t(&)[64])>(
+                     cuda::ptx::tcgen05_st_16x128b_unpack_16b));));
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_101a,
+               (
+                   // tcgen05.st.sync.aligned.16x128b.x32.unpack::16b.b32 [taddr], values;
+                   * fn_ptr++ = reinterpret_cast<void*>(static_cast<void (*)(uint32_t, const int32_t(&)[64])>(
+                     cuda::ptx::tcgen05_st_16x128b_unpack_16b));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_100a,
+               (
+                   // tcgen05.st.sync.aligned.16x128b.x64.b32 [taddr], values;
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(uint32_t, const int32_t(&)[128])>(cuda::ptx::tcgen05_st_16x128b));));
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_101a,
+               (
+                   // tcgen05.st.sync.aligned.16x128b.x64.b32 [taddr], values;
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(uint32_t, const int32_t(&)[128])>(cuda::ptx::tcgen05_st_16x128b));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_100a,
+               (
+                   // tcgen05.st.sync.aligned.16x128b.x64.unpack::16b.b32 [taddr], values;
+                   * fn_ptr++ = reinterpret_cast<void*>(static_cast<void (*)(uint32_t, const int32_t(&)[128])>(
+                     cuda::ptx::tcgen05_st_16x128b_unpack_16b));));
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_101a,
+               (
+                   // tcgen05.st.sync.aligned.16x128b.x64.unpack::16b.b32 [taddr], values;
+                   * fn_ptr++ = reinterpret_cast<void*>(static_cast<void (*)(uint32_t, const int32_t(&)[128])>(
+                     cuda::ptx::tcgen05_st_16x128b_unpack_16b));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_100a,
+               (
+                   // tcgen05.st.sync.aligned.16x256b.x1.b32 [taddr], values;
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(uint32_t, const int32_t(&)[4])>(cuda::ptx::tcgen05_st_16x256b));));
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_101a,
+               (
+                   // tcgen05.st.sync.aligned.16x256b.x1.b32 [taddr], values;
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(uint32_t, const int32_t(&)[4])>(cuda::ptx::tcgen05_st_16x256b));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_100a,
+               (
+                   // tcgen05.st.sync.aligned.16x256b.x1.unpack::16b.b32 [taddr], values;
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(uint32_t, const int32_t(&)[4])>(cuda::ptx::tcgen05_st_16x256b_unpack_16b));));
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_101a,
+               (
+                   // tcgen05.st.sync.aligned.16x256b.x1.unpack::16b.b32 [taddr], values;
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(uint32_t, const int32_t(&)[4])>(cuda::ptx::tcgen05_st_16x256b_unpack_16b));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_100a,
+               (
+                   // tcgen05.st.sync.aligned.16x256b.x2.b32 [taddr], values;
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(uint32_t, const int32_t(&)[8])>(cuda::ptx::tcgen05_st_16x256b));));
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_101a,
+               (
+                   // tcgen05.st.sync.aligned.16x256b.x2.b32 [taddr], values;
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(uint32_t, const int32_t(&)[8])>(cuda::ptx::tcgen05_st_16x256b));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_100a,
+               (
+                   // tcgen05.st.sync.aligned.16x256b.x2.unpack::16b.b32 [taddr], values;
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(uint32_t, const int32_t(&)[8])>(cuda::ptx::tcgen05_st_16x256b_unpack_16b));));
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_101a,
+               (
+                   // tcgen05.st.sync.aligned.16x256b.x2.unpack::16b.b32 [taddr], values;
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(uint32_t, const int32_t(&)[8])>(cuda::ptx::tcgen05_st_16x256b_unpack_16b));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_100a,
+               (
+                   // tcgen05.st.sync.aligned.16x256b.x4.b32 [taddr], values;
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(uint32_t, const int32_t(&)[16])>(cuda::ptx::tcgen05_st_16x256b));));
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_101a,
+               (
+                   // tcgen05.st.sync.aligned.16x256b.x4.b32 [taddr], values;
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(uint32_t, const int32_t(&)[16])>(cuda::ptx::tcgen05_st_16x256b));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_100a,
+               (
+                   // tcgen05.st.sync.aligned.16x256b.x4.unpack::16b.b32 [taddr], values;
+                   * fn_ptr++ = reinterpret_cast<void*>(static_cast<void (*)(uint32_t, const int32_t(&)[16])>(
+                     cuda::ptx::tcgen05_st_16x256b_unpack_16b));));
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_101a,
+               (
+                   // tcgen05.st.sync.aligned.16x256b.x4.unpack::16b.b32 [taddr], values;
+                   * fn_ptr++ = reinterpret_cast<void*>(static_cast<void (*)(uint32_t, const int32_t(&)[16])>(
+                     cuda::ptx::tcgen05_st_16x256b_unpack_16b));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_100a,
+               (
+                   // tcgen05.st.sync.aligned.16x256b.x8.b32 [taddr], values;
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(uint32_t, const int32_t(&)[32])>(cuda::ptx::tcgen05_st_16x256b));));
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_101a,
+               (
+                   // tcgen05.st.sync.aligned.16x256b.x8.b32 [taddr], values;
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(uint32_t, const int32_t(&)[32])>(cuda::ptx::tcgen05_st_16x256b));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_100a,
+               (
+                   // tcgen05.st.sync.aligned.16x256b.x8.unpack::16b.b32 [taddr], values;
+                   * fn_ptr++ = reinterpret_cast<void*>(static_cast<void (*)(uint32_t, const int32_t(&)[32])>(
+                     cuda::ptx::tcgen05_st_16x256b_unpack_16b));));
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_101a,
+               (
+                   // tcgen05.st.sync.aligned.16x256b.x8.unpack::16b.b32 [taddr], values;
+                   * fn_ptr++ = reinterpret_cast<void*>(static_cast<void (*)(uint32_t, const int32_t(&)[32])>(
+                     cuda::ptx::tcgen05_st_16x256b_unpack_16b));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_100a,
+               (
+                   // tcgen05.st.sync.aligned.16x256b.x16.b32 [taddr], values;
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(uint32_t, const int32_t(&)[64])>(cuda::ptx::tcgen05_st_16x256b));));
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_101a,
+               (
+                   // tcgen05.st.sync.aligned.16x256b.x16.b32 [taddr], values;
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(uint32_t, const int32_t(&)[64])>(cuda::ptx::tcgen05_st_16x256b));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_100a,
+               (
+                   // tcgen05.st.sync.aligned.16x256b.x16.unpack::16b.b32 [taddr], values;
+                   * fn_ptr++ = reinterpret_cast<void*>(static_cast<void (*)(uint32_t, const int32_t(&)[64])>(
+                     cuda::ptx::tcgen05_st_16x256b_unpack_16b));));
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_101a,
+               (
+                   // tcgen05.st.sync.aligned.16x256b.x16.unpack::16b.b32 [taddr], values;
+                   * fn_ptr++ = reinterpret_cast<void*>(static_cast<void (*)(uint32_t, const int32_t(&)[64])>(
+                     cuda::ptx::tcgen05_st_16x256b_unpack_16b));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_100a,
+               (
+                   // tcgen05.st.sync.aligned.16x256b.x32.b32 [taddr], values;
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(uint32_t, const int32_t(&)[128])>(cuda::ptx::tcgen05_st_16x256b));));
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_101a,
+               (
+                   // tcgen05.st.sync.aligned.16x256b.x32.b32 [taddr], values;
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(uint32_t, const int32_t(&)[128])>(cuda::ptx::tcgen05_st_16x256b));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_100a,
+               (
+                   // tcgen05.st.sync.aligned.16x256b.x32.unpack::16b.b32 [taddr], values;
+                   * fn_ptr++ = reinterpret_cast<void*>(static_cast<void (*)(uint32_t, const int32_t(&)[128])>(
+                     cuda::ptx::tcgen05_st_16x256b_unpack_16b));));
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_101a,
+               (
+                   // tcgen05.st.sync.aligned.16x256b.x32.unpack::16b.b32 [taddr], values;
+                   * fn_ptr++ = reinterpret_cast<void*>(static_cast<void (*)(uint32_t, const int32_t(&)[128])>(
+                     cuda::ptx::tcgen05_st_16x256b_unpack_16b));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_100a,
+               (
+                   // tcgen05.st.sync.aligned.32x32b.x1.b32 [taddr], values;
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(uint32_t, const int32_t(&)[1])>(cuda::ptx::tcgen05_st_32x32b));));
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_101a,
+               (
+                   // tcgen05.st.sync.aligned.32x32b.x1.b32 [taddr], values;
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(uint32_t, const int32_t(&)[1])>(cuda::ptx::tcgen05_st_32x32b));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_100a,
+               (
+                   // tcgen05.st.sync.aligned.32x32b.x1.unpack::16b.b32 [taddr], values;
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(uint32_t, const int32_t(&)[1])>(cuda::ptx::tcgen05_st_32x32b_unpack_16b));));
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_101a,
+               (
+                   // tcgen05.st.sync.aligned.32x32b.x1.unpack::16b.b32 [taddr], values;
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(uint32_t, const int32_t(&)[1])>(cuda::ptx::tcgen05_st_32x32b_unpack_16b));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_100a,
+               (
+                   // tcgen05.st.sync.aligned.32x32b.x2.b32 [taddr], values;
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(uint32_t, const int32_t(&)[2])>(cuda::ptx::tcgen05_st_32x32b));));
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_101a,
+               (
+                   // tcgen05.st.sync.aligned.32x32b.x2.b32 [taddr], values;
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(uint32_t, const int32_t(&)[2])>(cuda::ptx::tcgen05_st_32x32b));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_100a,
+               (
+                   // tcgen05.st.sync.aligned.32x32b.x2.unpack::16b.b32 [taddr], values;
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(uint32_t, const int32_t(&)[2])>(cuda::ptx::tcgen05_st_32x32b_unpack_16b));));
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_101a,
+               (
+                   // tcgen05.st.sync.aligned.32x32b.x2.unpack::16b.b32 [taddr], values;
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(uint32_t, const int32_t(&)[2])>(cuda::ptx::tcgen05_st_32x32b_unpack_16b));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_100a,
+               (
+                   // tcgen05.st.sync.aligned.32x32b.x4.b32 [taddr], values;
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(uint32_t, const int32_t(&)[4])>(cuda::ptx::tcgen05_st_32x32b));));
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_101a,
+               (
+                   // tcgen05.st.sync.aligned.32x32b.x4.b32 [taddr], values;
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(uint32_t, const int32_t(&)[4])>(cuda::ptx::tcgen05_st_32x32b));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_100a,
+               (
+                   // tcgen05.st.sync.aligned.32x32b.x4.unpack::16b.b32 [taddr], values;
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(uint32_t, const int32_t(&)[4])>(cuda::ptx::tcgen05_st_32x32b_unpack_16b));));
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_101a,
+               (
+                   // tcgen05.st.sync.aligned.32x32b.x4.unpack::16b.b32 [taddr], values;
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(uint32_t, const int32_t(&)[4])>(cuda::ptx::tcgen05_st_32x32b_unpack_16b));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_100a,
+               (
+                   // tcgen05.st.sync.aligned.32x32b.x8.b32 [taddr], values;
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(uint32_t, const int32_t(&)[8])>(cuda::ptx::tcgen05_st_32x32b));));
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_101a,
+               (
+                   // tcgen05.st.sync.aligned.32x32b.x8.b32 [taddr], values;
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(uint32_t, const int32_t(&)[8])>(cuda::ptx::tcgen05_st_32x32b));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_100a,
+               (
+                   // tcgen05.st.sync.aligned.32x32b.x8.unpack::16b.b32 [taddr], values;
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(uint32_t, const int32_t(&)[8])>(cuda::ptx::tcgen05_st_32x32b_unpack_16b));));
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_101a,
+               (
+                   // tcgen05.st.sync.aligned.32x32b.x8.unpack::16b.b32 [taddr], values;
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(uint32_t, const int32_t(&)[8])>(cuda::ptx::tcgen05_st_32x32b_unpack_16b));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_100a,
+               (
+                   // tcgen05.st.sync.aligned.32x32b.x16.b32 [taddr], values;
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(uint32_t, const int32_t(&)[16])>(cuda::ptx::tcgen05_st_32x32b));));
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_101a,
+               (
+                   // tcgen05.st.sync.aligned.32x32b.x16.b32 [taddr], values;
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(uint32_t, const int32_t(&)[16])>(cuda::ptx::tcgen05_st_32x32b));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_100a,
+               (
+                   // tcgen05.st.sync.aligned.32x32b.x16.unpack::16b.b32 [taddr], values;
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(uint32_t, const int32_t(&)[16])>(cuda::ptx::tcgen05_st_32x32b_unpack_16b));));
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_101a,
+               (
+                   // tcgen05.st.sync.aligned.32x32b.x16.unpack::16b.b32 [taddr], values;
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(uint32_t, const int32_t(&)[16])>(cuda::ptx::tcgen05_st_32x32b_unpack_16b));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_100a,
+               (
+                   // tcgen05.st.sync.aligned.32x32b.x32.b32 [taddr], values;
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(uint32_t, const int32_t(&)[32])>(cuda::ptx::tcgen05_st_32x32b));));
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_101a,
+               (
+                   // tcgen05.st.sync.aligned.32x32b.x32.b32 [taddr], values;
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(uint32_t, const int32_t(&)[32])>(cuda::ptx::tcgen05_st_32x32b));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_100a,
+               (
+                   // tcgen05.st.sync.aligned.32x32b.x32.unpack::16b.b32 [taddr], values;
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(uint32_t, const int32_t(&)[32])>(cuda::ptx::tcgen05_st_32x32b_unpack_16b));));
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_101a,
+               (
+                   // tcgen05.st.sync.aligned.32x32b.x32.unpack::16b.b32 [taddr], values;
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(uint32_t, const int32_t(&)[32])>(cuda::ptx::tcgen05_st_32x32b_unpack_16b));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_100a,
+               (
+                   // tcgen05.st.sync.aligned.32x32b.x64.b32 [taddr], values;
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(uint32_t, const int32_t(&)[64])>(cuda::ptx::tcgen05_st_32x32b));));
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_101a,
+               (
+                   // tcgen05.st.sync.aligned.32x32b.x64.b32 [taddr], values;
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(uint32_t, const int32_t(&)[64])>(cuda::ptx::tcgen05_st_32x32b));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_100a,
+               (
+                   // tcgen05.st.sync.aligned.32x32b.x64.unpack::16b.b32 [taddr], values;
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(uint32_t, const int32_t(&)[64])>(cuda::ptx::tcgen05_st_32x32b_unpack_16b));));
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_101a,
+               (
+                   // tcgen05.st.sync.aligned.32x32b.x64.unpack::16b.b32 [taddr], values;
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(uint32_t, const int32_t(&)[64])>(cuda::ptx::tcgen05_st_32x32b_unpack_16b));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_100a,
+               (
+                   // tcgen05.st.sync.aligned.32x32b.x128.b32 [taddr], values;
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(uint32_t, const int32_t(&)[128])>(cuda::ptx::tcgen05_st_32x32b));));
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_101a,
+               (
+                   // tcgen05.st.sync.aligned.32x32b.x128.b32 [taddr], values;
+                   * fn_ptr++ = reinterpret_cast<void*>(
+                     static_cast<void (*)(uint32_t, const int32_t(&)[128])>(cuda::ptx::tcgen05_st_32x32b));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_100a,
+               (
+                   // tcgen05.st.sync.aligned.32x32b.x128.unpack::16b.b32 [taddr], values;
+                   * fn_ptr++ = reinterpret_cast<void*>(static_cast<void (*)(uint32_t, const int32_t(&)[128])>(
+                     cuda::ptx::tcgen05_st_32x32b_unpack_16b));));
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_101a,
+               (
+                   // tcgen05.st.sync.aligned.32x32b.x128.unpack::16b.b32 [taddr], values;
+                   * fn_ptr++ = reinterpret_cast<void*>(static_cast<void (*)(uint32_t, const int32_t(&)[128])>(
+                     cuda::ptx::tcgen05_st_32x32b_unpack_16b));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tcgen05.st.sync.aligned.16x32bx2.x1.b32 [taddr], immHalfSplitoff, values;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(uint32_t, cuda::ptx::n32_t<0>, const int32_t(&)[1])>(cuda::ptx::tcgen05_st_16x32bx2));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // tcgen05.st.sync.aligned.16x32bx2.x1.b32 [taddr], immHalfSplitoff, values;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(uint32_t, cuda::ptx::n32_t<0>, const int32_t(&)[1])>(cuda::ptx::tcgen05_st_16x32bx2));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tcgen05.st.sync.aligned.16x32bx2.x1.unpack::16b.b32 [taddr], immHalfSplitoff, values;
+        * fn_ptr++ = reinterpret_cast<void*>(static_cast<void (*)(uint32_t, cuda::ptx::n32_t<0>, const int32_t(&)[1])>(
+          cuda::ptx::tcgen05_st_16x32bx2_unpack_16b));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // tcgen05.st.sync.aligned.16x32bx2.x1.unpack::16b.b32 [taddr], immHalfSplitoff, values;
+        * fn_ptr++ = reinterpret_cast<void*>(static_cast<void (*)(uint32_t, cuda::ptx::n32_t<0>, const int32_t(&)[1])>(
+          cuda::ptx::tcgen05_st_16x32bx2_unpack_16b));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tcgen05.st.sync.aligned.16x32bx2.x2.b32 [taddr], immHalfSplitoff, values;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(uint32_t, cuda::ptx::n32_t<0>, const int32_t(&)[2])>(cuda::ptx::tcgen05_st_16x32bx2));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // tcgen05.st.sync.aligned.16x32bx2.x2.b32 [taddr], immHalfSplitoff, values;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(uint32_t, cuda::ptx::n32_t<0>, const int32_t(&)[2])>(cuda::ptx::tcgen05_st_16x32bx2));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tcgen05.st.sync.aligned.16x32bx2.x2.unpack::16b.b32 [taddr], immHalfSplitoff, values;
+        * fn_ptr++ = reinterpret_cast<void*>(static_cast<void (*)(uint32_t, cuda::ptx::n32_t<0>, const int32_t(&)[2])>(
+          cuda::ptx::tcgen05_st_16x32bx2_unpack_16b));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // tcgen05.st.sync.aligned.16x32bx2.x2.unpack::16b.b32 [taddr], immHalfSplitoff, values;
+        * fn_ptr++ = reinterpret_cast<void*>(static_cast<void (*)(uint32_t, cuda::ptx::n32_t<0>, const int32_t(&)[2])>(
+          cuda::ptx::tcgen05_st_16x32bx2_unpack_16b));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tcgen05.st.sync.aligned.16x32bx2.x4.b32 [taddr], immHalfSplitoff, values;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(uint32_t, cuda::ptx::n32_t<0>, const int32_t(&)[4])>(cuda::ptx::tcgen05_st_16x32bx2));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // tcgen05.st.sync.aligned.16x32bx2.x4.b32 [taddr], immHalfSplitoff, values;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(uint32_t, cuda::ptx::n32_t<0>, const int32_t(&)[4])>(cuda::ptx::tcgen05_st_16x32bx2));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tcgen05.st.sync.aligned.16x32bx2.x4.unpack::16b.b32 [taddr], immHalfSplitoff, values;
+        * fn_ptr++ = reinterpret_cast<void*>(static_cast<void (*)(uint32_t, cuda::ptx::n32_t<0>, const int32_t(&)[4])>(
+          cuda::ptx::tcgen05_st_16x32bx2_unpack_16b));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // tcgen05.st.sync.aligned.16x32bx2.x4.unpack::16b.b32 [taddr], immHalfSplitoff, values;
+        * fn_ptr++ = reinterpret_cast<void*>(static_cast<void (*)(uint32_t, cuda::ptx::n32_t<0>, const int32_t(&)[4])>(
+          cuda::ptx::tcgen05_st_16x32bx2_unpack_16b));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tcgen05.st.sync.aligned.16x32bx2.x8.b32 [taddr], immHalfSplitoff, values;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(uint32_t, cuda::ptx::n32_t<0>, const int32_t(&)[8])>(cuda::ptx::tcgen05_st_16x32bx2));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // tcgen05.st.sync.aligned.16x32bx2.x8.b32 [taddr], immHalfSplitoff, values;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(uint32_t, cuda::ptx::n32_t<0>, const int32_t(&)[8])>(cuda::ptx::tcgen05_st_16x32bx2));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tcgen05.st.sync.aligned.16x32bx2.x8.unpack::16b.b32 [taddr], immHalfSplitoff, values;
+        * fn_ptr++ = reinterpret_cast<void*>(static_cast<void (*)(uint32_t, cuda::ptx::n32_t<0>, const int32_t(&)[8])>(
+          cuda::ptx::tcgen05_st_16x32bx2_unpack_16b));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // tcgen05.st.sync.aligned.16x32bx2.x8.unpack::16b.b32 [taddr], immHalfSplitoff, values;
+        * fn_ptr++ = reinterpret_cast<void*>(static_cast<void (*)(uint32_t, cuda::ptx::n32_t<0>, const int32_t(&)[8])>(
+          cuda::ptx::tcgen05_st_16x32bx2_unpack_16b));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tcgen05.st.sync.aligned.16x32bx2.x16.b32 [taddr], immHalfSplitoff, values;
+        * fn_ptr++ = reinterpret_cast<void*>(static_cast<void (*)(uint32_t, cuda::ptx::n32_t<0>, const int32_t(&)[16])>(
+          cuda::ptx::tcgen05_st_16x32bx2));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // tcgen05.st.sync.aligned.16x32bx2.x16.b32 [taddr], immHalfSplitoff, values;
+        * fn_ptr++ = reinterpret_cast<void*>(static_cast<void (*)(uint32_t, cuda::ptx::n32_t<0>, const int32_t(&)[16])>(
+          cuda::ptx::tcgen05_st_16x32bx2));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tcgen05.st.sync.aligned.16x32bx2.x16.unpack::16b.b32 [taddr], immHalfSplitoff, values;
+        * fn_ptr++ = reinterpret_cast<void*>(static_cast<void (*)(uint32_t, cuda::ptx::n32_t<0>, const int32_t(&)[16])>(
+          cuda::ptx::tcgen05_st_16x32bx2_unpack_16b));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // tcgen05.st.sync.aligned.16x32bx2.x16.unpack::16b.b32 [taddr], immHalfSplitoff, values;
+        * fn_ptr++ = reinterpret_cast<void*>(static_cast<void (*)(uint32_t, cuda::ptx::n32_t<0>, const int32_t(&)[16])>(
+          cuda::ptx::tcgen05_st_16x32bx2_unpack_16b));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tcgen05.st.sync.aligned.16x32bx2.x32.b32 [taddr], immHalfSplitoff, values;
+        * fn_ptr++ = reinterpret_cast<void*>(static_cast<void (*)(uint32_t, cuda::ptx::n32_t<0>, const int32_t(&)[32])>(
+          cuda::ptx::tcgen05_st_16x32bx2));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // tcgen05.st.sync.aligned.16x32bx2.x32.b32 [taddr], immHalfSplitoff, values;
+        * fn_ptr++ = reinterpret_cast<void*>(static_cast<void (*)(uint32_t, cuda::ptx::n32_t<0>, const int32_t(&)[32])>(
+          cuda::ptx::tcgen05_st_16x32bx2));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tcgen05.st.sync.aligned.16x32bx2.x32.unpack::16b.b32 [taddr], immHalfSplitoff, values;
+        * fn_ptr++ = reinterpret_cast<void*>(static_cast<void (*)(uint32_t, cuda::ptx::n32_t<0>, const int32_t(&)[32])>(
+          cuda::ptx::tcgen05_st_16x32bx2_unpack_16b));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // tcgen05.st.sync.aligned.16x32bx2.x32.unpack::16b.b32 [taddr], immHalfSplitoff, values;
+        * fn_ptr++ = reinterpret_cast<void*>(static_cast<void (*)(uint32_t, cuda::ptx::n32_t<0>, const int32_t(&)[32])>(
+          cuda::ptx::tcgen05_st_16x32bx2_unpack_16b));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tcgen05.st.sync.aligned.16x32bx2.x64.b32 [taddr], immHalfSplitoff, values;
+        * fn_ptr++ = reinterpret_cast<void*>(static_cast<void (*)(uint32_t, cuda::ptx::n32_t<0>, const int32_t(&)[64])>(
+          cuda::ptx::tcgen05_st_16x32bx2));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // tcgen05.st.sync.aligned.16x32bx2.x64.b32 [taddr], immHalfSplitoff, values;
+        * fn_ptr++ = reinterpret_cast<void*>(static_cast<void (*)(uint32_t, cuda::ptx::n32_t<0>, const int32_t(&)[64])>(
+          cuda::ptx::tcgen05_st_16x32bx2));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tcgen05.st.sync.aligned.16x32bx2.x64.unpack::16b.b32 [taddr], immHalfSplitoff, values;
+        * fn_ptr++ = reinterpret_cast<void*>(static_cast<void (*)(uint32_t, cuda::ptx::n32_t<0>, const int32_t(&)[64])>(
+          cuda::ptx::tcgen05_st_16x32bx2_unpack_16b));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // tcgen05.st.sync.aligned.16x32bx2.x64.unpack::16b.b32 [taddr], immHalfSplitoff, values;
+        * fn_ptr++ = reinterpret_cast<void*>(static_cast<void (*)(uint32_t, cuda::ptx::n32_t<0>, const int32_t(&)[64])>(
+          cuda::ptx::tcgen05_st_16x32bx2_unpack_16b));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tcgen05.st.sync.aligned.16x32bx2.x128.b32 [taddr], immHalfSplitoff, values;
+        * fn_ptr++ = reinterpret_cast<void*>(static_cast<void (*)(uint32_t, cuda::ptx::n32_t<0>, const int32_t(&)[128])>(
+          cuda::ptx::tcgen05_st_16x32bx2));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // tcgen05.st.sync.aligned.16x32bx2.x128.b32 [taddr], immHalfSplitoff, values;
+        * fn_ptr++ = reinterpret_cast<void*>(static_cast<void (*)(uint32_t, cuda::ptx::n32_t<0>, const int32_t(&)[128])>(
+          cuda::ptx::tcgen05_st_16x32bx2));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tcgen05.st.sync.aligned.16x32bx2.x128.unpack::16b.b32 [taddr], immHalfSplitoff, values;
+        * fn_ptr++ = reinterpret_cast<void*>(static_cast<void (*)(uint32_t, cuda::ptx::n32_t<0>, const int32_t(&)[128])>(
+          cuda::ptx::tcgen05_st_16x32bx2_unpack_16b));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // tcgen05.st.sync.aligned.16x32bx2.x128.unpack::16b.b32 [taddr], immHalfSplitoff, values;
+        * fn_ptr++ = reinterpret_cast<void*>(static_cast<void (*)(uint32_t, cuda::ptx::n32_t<0>, const int32_t(&)[128])>(
+          cuda::ptx::tcgen05_st_16x32bx2_unpack_16b));));
+#endif // __cccl_ptx_isa >= 860
+}
diff --git a/libcudacxx/test/libcudacxx/cuda/ptx/generated/tcgen05_wait.h b/libcudacxx/test/libcudacxx/cuda/ptx/generated/tcgen05_wait.h
new file mode 100644
index 00000000000..424d884049c
--- /dev/null
+++ b/libcudacxx/test/libcudacxx/cuda/ptx/generated/tcgen05_wait.h
@@ -0,0 +1,40 @@
+// This file was automatically generated. Do not edit.
+
+// We use a special strategy to force the generation of the PTX. This is mainly
+// a fight against dead-code-elimination in the NVVM layer.
+//
+// The reason we need this strategy is because certain older versions of ptxas
+// segfault when a non-sensical sequence of PTX is generated. So instead, we try
+// to force the instantiation and compilation to PTX of all the overloads of the
+// PTX wrapping functions.
+//
+// We do this by writing a function pointer of each overload to the kernel
+// parameter `fn_ptr`.
+//
+// Because `fn_ptr` is possibly visible outside this translation unit, the
+// compiler must compile all the functions which are stored.
+
+__global__ void test_tcgen05_wait(void** fn_ptr)
+{
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_100a,
+               (
+                   // tcgen05.wait::ld.sync.aligned;
+                   * fn_ptr++ = reinterpret_cast<void*>(static_cast<void (*)()>(cuda::ptx::tcgen05_wait_ld));));
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_101a,
+               (
+                   // tcgen05.wait::ld.sync.aligned;
+                   * fn_ptr++ = reinterpret_cast<void*>(static_cast<void (*)()>(cuda::ptx::tcgen05_wait_ld));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_100a,
+               (
+                   // tcgen05.wait::st.sync.aligned;
+                   * fn_ptr++ = reinterpret_cast<void*>(static_cast<void (*)()>(cuda::ptx::tcgen05_wait_st));));
+  NV_IF_TARGET(NV_HAS_FEATURE_SM_101a,
+               (
+                   // tcgen05.wait::st.sync.aligned;
+                   * fn_ptr++ = reinterpret_cast<void*>(static_cast<void (*)()>(cuda::ptx::tcgen05_wait_st));));
+#endif // __cccl_ptx_isa >= 860
+}
diff --git a/libcudacxx/test/libcudacxx/cuda/ptx/generated/tensormap_replace.h b/libcudacxx/test/libcudacxx/cuda/ptx/generated/tensormap_replace.h
index 95446eb81fa..1439bc84bd0 100644
--- a/libcudacxx/test/libcudacxx/cuda/ptx/generated/tensormap_replace.h
+++ b/libcudacxx/test/libcudacxx/cuda/ptx/generated/tensormap_replace.h
@@ -20,7 +20,19 @@ __global__ void test_tensormap_replace(void** fn_ptr)
   NV_IF_TARGET(
     NV_HAS_FEATURE_SM_90a,
     (
-        // tensormap.replace.tile.global_address.global.b1024.b64    [tm_addr], new_val;
+        // tensormap.replace.tile.global_address.global.b1024.b64 [tm_addr], new_val;
+        * fn_ptr++ = reinterpret_cast<void*>(static_cast<void (*)(cuda::ptx::space_global_t, void*, int64_t)>(
+          cuda::ptx::tensormap_replace_global_address));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tensormap.replace.tile.global_address.global.b1024.b64 [tm_addr], new_val;
+        * fn_ptr++ = reinterpret_cast<void*>(static_cast<void (*)(cuda::ptx::space_global_t, void*, int64_t)>(
+          cuda::ptx::tensormap_replace_global_address));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // tensormap.replace.tile.global_address.global.b1024.b64 [tm_addr], new_val;
         * fn_ptr++ = reinterpret_cast<void*>(static_cast<void (*)(cuda::ptx::space_global_t, void*, int64_t)>(
           cuda::ptx::tensormap_replace_global_address));));
 #endif // __cccl_ptx_isa >= 830
@@ -29,7 +41,19 @@ __global__ void test_tensormap_replace(void** fn_ptr)
   NV_IF_TARGET(
     NV_HAS_FEATURE_SM_90a,
     (
-        // tensormap.replace.tile.global_address.shared::cta.b1024.b64    [tm_addr], new_val;
+        // tensormap.replace.tile.global_address.shared::cta.b1024.b64 [tm_addr], new_val;
+        * fn_ptr++ = reinterpret_cast<void*>(static_cast<void (*)(cuda::ptx::space_shared_t, void*, int64_t)>(
+          cuda::ptx::tensormap_replace_global_address));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tensormap.replace.tile.global_address.shared::cta.b1024.b64 [tm_addr], new_val;
+        * fn_ptr++ = reinterpret_cast<void*>(static_cast<void (*)(cuda::ptx::space_shared_t, void*, int64_t)>(
+          cuda::ptx::tensormap_replace_global_address));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // tensormap.replace.tile.global_address.shared::cta.b1024.b64 [tm_addr], new_val;
         * fn_ptr++ = reinterpret_cast<void*>(static_cast<void (*)(cuda::ptx::space_shared_t, void*, int64_t)>(
           cuda::ptx::tensormap_replace_global_address));));
 #endif // __cccl_ptx_isa >= 830
@@ -38,7 +62,19 @@ __global__ void test_tensormap_replace(void** fn_ptr)
   NV_IF_TARGET(
     NV_HAS_FEATURE_SM_90a,
     (
-        // tensormap.replace.tile.rank.global.b1024.b32              [tm_addr], new_val;
+        // tensormap.replace.tile.rank.global.b1024.b32 [tm_addr], new_val;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(cuda::ptx::space_global_t, void*, int32_t)>(cuda::ptx::tensormap_replace_rank));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tensormap.replace.tile.rank.global.b1024.b32 [tm_addr], new_val;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(cuda::ptx::space_global_t, void*, int32_t)>(cuda::ptx::tensormap_replace_rank));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // tensormap.replace.tile.rank.global.b1024.b32 [tm_addr], new_val;
         * fn_ptr++ = reinterpret_cast<void*>(
           static_cast<void (*)(cuda::ptx::space_global_t, void*, int32_t)>(cuda::ptx::tensormap_replace_rank));));
 #endif // __cccl_ptx_isa >= 830
@@ -47,7 +83,19 @@ __global__ void test_tensormap_replace(void** fn_ptr)
   NV_IF_TARGET(
     NV_HAS_FEATURE_SM_90a,
     (
-        // tensormap.replace.tile.rank.shared::cta.b1024.b32              [tm_addr], new_val;
+        // tensormap.replace.tile.rank.shared::cta.b1024.b32 [tm_addr], new_val;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(cuda::ptx::space_shared_t, void*, int32_t)>(cuda::ptx::tensormap_replace_rank));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tensormap.replace.tile.rank.shared::cta.b1024.b32 [tm_addr], new_val;
+        * fn_ptr++ = reinterpret_cast<void*>(
+          static_cast<void (*)(cuda::ptx::space_shared_t, void*, int32_t)>(cuda::ptx::tensormap_replace_rank));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // tensormap.replace.tile.rank.shared::cta.b1024.b32 [tm_addr], new_val;
         * fn_ptr++ = reinterpret_cast<void*>(
           static_cast<void (*)(cuda::ptx::space_shared_t, void*, int32_t)>(cuda::ptx::tensormap_replace_rank));));
 #endif // __cccl_ptx_isa >= 830
@@ -56,7 +104,21 @@ __global__ void test_tensormap_replace(void** fn_ptr)
   NV_IF_TARGET(
     NV_HAS_FEATURE_SM_90a,
     (
-        // tensormap.replace.tile.box_dim.global.b1024.b32           [tm_addr], ord, new_val;
+        // tensormap.replace.tile.box_dim.global.b1024.b32 [tm_addr], ord, new_val;
+        * fn_ptr++ =
+          reinterpret_cast<void*>(static_cast<void (*)(cuda::ptx::space_global_t, void*, cuda::ptx::n32_t<0>, int32_t)>(
+            cuda::ptx::tensormap_replace_box_dim));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tensormap.replace.tile.box_dim.global.b1024.b32 [tm_addr], ord, new_val;
+        * fn_ptr++ =
+          reinterpret_cast<void*>(static_cast<void (*)(cuda::ptx::space_global_t, void*, cuda::ptx::n32_t<0>, int32_t)>(
+            cuda::ptx::tensormap_replace_box_dim));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // tensormap.replace.tile.box_dim.global.b1024.b32 [tm_addr], ord, new_val;
         * fn_ptr++ =
           reinterpret_cast<void*>(static_cast<void (*)(cuda::ptx::space_global_t, void*, cuda::ptx::n32_t<0>, int32_t)>(
             cuda::ptx::tensormap_replace_box_dim));));
@@ -66,7 +128,21 @@ __global__ void test_tensormap_replace(void** fn_ptr)
   NV_IF_TARGET(
     NV_HAS_FEATURE_SM_90a,
     (
-        // tensormap.replace.tile.box_dim.shared::cta.b1024.b32           [tm_addr], ord, new_val;
+        // tensormap.replace.tile.box_dim.shared::cta.b1024.b32 [tm_addr], ord, new_val;
+        * fn_ptr++ =
+          reinterpret_cast<void*>(static_cast<void (*)(cuda::ptx::space_shared_t, void*, cuda::ptx::n32_t<0>, int32_t)>(
+            cuda::ptx::tensormap_replace_box_dim));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tensormap.replace.tile.box_dim.shared::cta.b1024.b32 [tm_addr], ord, new_val;
+        * fn_ptr++ =
+          reinterpret_cast<void*>(static_cast<void (*)(cuda::ptx::space_shared_t, void*, cuda::ptx::n32_t<0>, int32_t)>(
+            cuda::ptx::tensormap_replace_box_dim));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // tensormap.replace.tile.box_dim.shared::cta.b1024.b32 [tm_addr], ord, new_val;
         * fn_ptr++ =
           reinterpret_cast<void*>(static_cast<void (*)(cuda::ptx::space_shared_t, void*, cuda::ptx::n32_t<0>, int32_t)>(
             cuda::ptx::tensormap_replace_box_dim));));
@@ -76,7 +152,21 @@ __global__ void test_tensormap_replace(void** fn_ptr)
   NV_IF_TARGET(
     NV_HAS_FEATURE_SM_90a,
     (
-        // tensormap.replace.tile.global_dim.global.b1024.b32        [tm_addr], ord, new_val;
+        // tensormap.replace.tile.global_dim.global.b1024.b32 [tm_addr], ord, new_val;
+        * fn_ptr++ =
+          reinterpret_cast<void*>(static_cast<void (*)(cuda::ptx::space_global_t, void*, cuda::ptx::n32_t<0>, int32_t)>(
+            cuda::ptx::tensormap_replace_global_dim));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tensormap.replace.tile.global_dim.global.b1024.b32 [tm_addr], ord, new_val;
+        * fn_ptr++ =
+          reinterpret_cast<void*>(static_cast<void (*)(cuda::ptx::space_global_t, void*, cuda::ptx::n32_t<0>, int32_t)>(
+            cuda::ptx::tensormap_replace_global_dim));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // tensormap.replace.tile.global_dim.global.b1024.b32 [tm_addr], ord, new_val;
         * fn_ptr++ =
           reinterpret_cast<void*>(static_cast<void (*)(cuda::ptx::space_global_t, void*, cuda::ptx::n32_t<0>, int32_t)>(
             cuda::ptx::tensormap_replace_global_dim));));
@@ -86,7 +176,21 @@ __global__ void test_tensormap_replace(void** fn_ptr)
   NV_IF_TARGET(
     NV_HAS_FEATURE_SM_90a,
     (
-        // tensormap.replace.tile.global_dim.shared::cta.b1024.b32        [tm_addr], ord, new_val;
+        // tensormap.replace.tile.global_dim.shared::cta.b1024.b32 [tm_addr], ord, new_val;
+        * fn_ptr++ =
+          reinterpret_cast<void*>(static_cast<void (*)(cuda::ptx::space_shared_t, void*, cuda::ptx::n32_t<0>, int32_t)>(
+            cuda::ptx::tensormap_replace_global_dim));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tensormap.replace.tile.global_dim.shared::cta.b1024.b32 [tm_addr], ord, new_val;
+        * fn_ptr++ =
+          reinterpret_cast<void*>(static_cast<void (*)(cuda::ptx::space_shared_t, void*, cuda::ptx::n32_t<0>, int32_t)>(
+            cuda::ptx::tensormap_replace_global_dim));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // tensormap.replace.tile.global_dim.shared::cta.b1024.b32 [tm_addr], ord, new_val;
         * fn_ptr++ =
           reinterpret_cast<void*>(static_cast<void (*)(cuda::ptx::space_shared_t, void*, cuda::ptx::n32_t<0>, int32_t)>(
             cuda::ptx::tensormap_replace_global_dim));));
@@ -96,7 +200,21 @@ __global__ void test_tensormap_replace(void** fn_ptr)
   NV_IF_TARGET(
     NV_HAS_FEATURE_SM_90a,
     (
-        // tensormap.replace.tile.global_stride.global.b1024.b64     [tm_addr], ord, new_val;
+        // tensormap.replace.tile.global_stride.global.b1024.b64 [tm_addr], ord, new_val;
+        * fn_ptr++ =
+          reinterpret_cast<void*>(static_cast<void (*)(cuda::ptx::space_global_t, void*, cuda::ptx::n32_t<0>, int64_t)>(
+            cuda::ptx::tensormap_replace_global_stride));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tensormap.replace.tile.global_stride.global.b1024.b64 [tm_addr], ord, new_val;
+        * fn_ptr++ =
+          reinterpret_cast<void*>(static_cast<void (*)(cuda::ptx::space_global_t, void*, cuda::ptx::n32_t<0>, int64_t)>(
+            cuda::ptx::tensormap_replace_global_stride));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // tensormap.replace.tile.global_stride.global.b1024.b64 [tm_addr], ord, new_val;
         * fn_ptr++ =
           reinterpret_cast<void*>(static_cast<void (*)(cuda::ptx::space_global_t, void*, cuda::ptx::n32_t<0>, int64_t)>(
             cuda::ptx::tensormap_replace_global_stride));));
@@ -106,17 +224,93 @@ __global__ void test_tensormap_replace(void** fn_ptr)
   NV_IF_TARGET(
     NV_HAS_FEATURE_SM_90a,
     (
-        // tensormap.replace.tile.global_stride.shared::cta.b1024.b64     [tm_addr], ord, new_val;
+        // tensormap.replace.tile.global_stride.shared::cta.b1024.b64 [tm_addr], ord, new_val;
         * fn_ptr++ =
           reinterpret_cast<void*>(static_cast<void (*)(cuda::ptx::space_shared_t, void*, cuda::ptx::n32_t<0>, int64_t)>(
             cuda::ptx::tensormap_replace_global_stride));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tensormap.replace.tile.global_stride.shared::cta.b1024.b64 [tm_addr], ord, new_val;
+        * fn_ptr++ =
+          reinterpret_cast<void*>(static_cast<void (*)(cuda::ptx::space_shared_t, void*, cuda::ptx::n32_t<0>, int64_t)>(
+            cuda::ptx::tensormap_replace_global_stride));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // tensormap.replace.tile.global_stride.shared::cta.b1024.b64 [tm_addr], ord, new_val;
+        * fn_ptr++ =
+          reinterpret_cast<void*>(static_cast<void (*)(cuda::ptx::space_shared_t, void*, cuda::ptx::n32_t<0>, int64_t)>(
+            cuda::ptx::tensormap_replace_global_stride));));
+#endif // __cccl_ptx_isa >= 830
+
+#if __cccl_ptx_isa >= 830
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_90a,
+    (
+        // tensormap.replace.tile.element_stride.global.b1024.b32 [tm_addr], ord, new_val;
+        * fn_ptr++ =
+          reinterpret_cast<void*>(static_cast<void (*)(cuda::ptx::space_global_t, void*, cuda::ptx::n32_t<0>, int32_t)>(
+            cuda::ptx::tensormap_replace_element_stride));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tensormap.replace.tile.element_stride.global.b1024.b32 [tm_addr], ord, new_val;
+        * fn_ptr++ =
+          reinterpret_cast<void*>(static_cast<void (*)(cuda::ptx::space_global_t, void*, cuda::ptx::n32_t<0>, int32_t)>(
+            cuda::ptx::tensormap_replace_element_stride));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // tensormap.replace.tile.element_stride.global.b1024.b32 [tm_addr], ord, new_val;
+        * fn_ptr++ =
+          reinterpret_cast<void*>(static_cast<void (*)(cuda::ptx::space_global_t, void*, cuda::ptx::n32_t<0>, int32_t)>(
+            cuda::ptx::tensormap_replace_element_stride));));
+#endif // __cccl_ptx_isa >= 830
+
+#if __cccl_ptx_isa >= 830
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_90a,
+    (
+        // tensormap.replace.tile.element_stride.shared::cta.b1024.b32 [tm_addr], ord, new_val;
+        * fn_ptr++ =
+          reinterpret_cast<void*>(static_cast<void (*)(cuda::ptx::space_shared_t, void*, cuda::ptx::n32_t<0>, int32_t)>(
+            cuda::ptx::tensormap_replace_element_stride));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tensormap.replace.tile.element_stride.shared::cta.b1024.b32 [tm_addr], ord, new_val;
+        * fn_ptr++ =
+          reinterpret_cast<void*>(static_cast<void (*)(cuda::ptx::space_shared_t, void*, cuda::ptx::n32_t<0>, int32_t)>(
+            cuda::ptx::tensormap_replace_element_stride));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // tensormap.replace.tile.element_stride.shared::cta.b1024.b32 [tm_addr], ord, new_val;
+        * fn_ptr++ =
+          reinterpret_cast<void*>(static_cast<void (*)(cuda::ptx::space_shared_t, void*, cuda::ptx::n32_t<0>, int32_t)>(
+            cuda::ptx::tensormap_replace_element_stride));));
 #endif // __cccl_ptx_isa >= 830
 
 #if __cccl_ptx_isa >= 830
   NV_IF_TARGET(
     NV_HAS_FEATURE_SM_90a,
     (
-        // tensormap.replace.tile.element_stride.global.b1024.b32    [tm_addr], ord, new_val;
+        // tensormap.replace.tile.element_stride.global.b1024.b32 [tm_addr], ord, new_val;
+        * fn_ptr++ =
+          reinterpret_cast<void*>(static_cast<void (*)(cuda::ptx::space_global_t, void*, cuda::ptx::n32_t<0>, int32_t)>(
+            cuda::ptx::tensormap_replace_element_size));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tensormap.replace.tile.element_stride.global.b1024.b32 [tm_addr], ord, new_val;
+        * fn_ptr++ =
+          reinterpret_cast<void*>(static_cast<void (*)(cuda::ptx::space_global_t, void*, cuda::ptx::n32_t<0>, int32_t)>(
+            cuda::ptx::tensormap_replace_element_size));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // tensormap.replace.tile.element_stride.global.b1024.b32 [tm_addr], ord, new_val;
         * fn_ptr++ =
           reinterpret_cast<void*>(static_cast<void (*)(cuda::ptx::space_global_t, void*, cuda::ptx::n32_t<0>, int32_t)>(
             cuda::ptx::tensormap_replace_element_size));));
@@ -126,7 +320,21 @@ __global__ void test_tensormap_replace(void** fn_ptr)
   NV_IF_TARGET(
     NV_HAS_FEATURE_SM_90a,
     (
-        // tensormap.replace.tile.element_stride.shared::cta.b1024.b32    [tm_addr], ord, new_val;
+        // tensormap.replace.tile.element_stride.shared::cta.b1024.b32 [tm_addr], ord, new_val;
+        * fn_ptr++ =
+          reinterpret_cast<void*>(static_cast<void (*)(cuda::ptx::space_shared_t, void*, cuda::ptx::n32_t<0>, int32_t)>(
+            cuda::ptx::tensormap_replace_element_size));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tensormap.replace.tile.element_stride.shared::cta.b1024.b32 [tm_addr], ord, new_val;
+        * fn_ptr++ =
+          reinterpret_cast<void*>(static_cast<void (*)(cuda::ptx::space_shared_t, void*, cuda::ptx::n32_t<0>, int32_t)>(
+            cuda::ptx::tensormap_replace_element_size));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // tensormap.replace.tile.element_stride.shared::cta.b1024.b32 [tm_addr], ord, new_val;
         * fn_ptr++ =
           reinterpret_cast<void*>(static_cast<void (*)(cuda::ptx::space_shared_t, void*, cuda::ptx::n32_t<0>, int32_t)>(
             cuda::ptx::tensormap_replace_element_size));));
@@ -136,7 +344,21 @@ __global__ void test_tensormap_replace(void** fn_ptr)
   NV_IF_TARGET(
     NV_HAS_FEATURE_SM_90a,
     (
-        // tensormap.replace.tile.elemtype.global.b1024.b32          [tm_addr], new_val;
+        // tensormap.replace.tile.elemtype.global.b1024.b32 [tm_addr], new_val;
+        * fn_ptr++ =
+          reinterpret_cast<void*>(static_cast<void (*)(cuda::ptx::space_global_t, void*, cuda::ptx::n32_t<0>)>(
+            cuda::ptx::tensormap_replace_elemtype));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tensormap.replace.tile.elemtype.global.b1024.b32 [tm_addr], new_val;
+        * fn_ptr++ =
+          reinterpret_cast<void*>(static_cast<void (*)(cuda::ptx::space_global_t, void*, cuda::ptx::n32_t<0>)>(
+            cuda::ptx::tensormap_replace_elemtype));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // tensormap.replace.tile.elemtype.global.b1024.b32 [tm_addr], new_val;
         * fn_ptr++ =
           reinterpret_cast<void*>(static_cast<void (*)(cuda::ptx::space_global_t, void*, cuda::ptx::n32_t<0>)>(
             cuda::ptx::tensormap_replace_elemtype));));
@@ -146,7 +368,21 @@ __global__ void test_tensormap_replace(void** fn_ptr)
   NV_IF_TARGET(
     NV_HAS_FEATURE_SM_90a,
     (
-        // tensormap.replace.tile.elemtype.shared::cta.b1024.b32          [tm_addr], new_val;
+        // tensormap.replace.tile.elemtype.shared::cta.b1024.b32 [tm_addr], new_val;
+        * fn_ptr++ =
+          reinterpret_cast<void*>(static_cast<void (*)(cuda::ptx::space_shared_t, void*, cuda::ptx::n32_t<0>)>(
+            cuda::ptx::tensormap_replace_elemtype));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tensormap.replace.tile.elemtype.shared::cta.b1024.b32 [tm_addr], new_val;
+        * fn_ptr++ =
+          reinterpret_cast<void*>(static_cast<void (*)(cuda::ptx::space_shared_t, void*, cuda::ptx::n32_t<0>)>(
+            cuda::ptx::tensormap_replace_elemtype));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // tensormap.replace.tile.elemtype.shared::cta.b1024.b32 [tm_addr], new_val;
         * fn_ptr++ =
           reinterpret_cast<void*>(static_cast<void (*)(cuda::ptx::space_shared_t, void*, cuda::ptx::n32_t<0>)>(
             cuda::ptx::tensormap_replace_elemtype));));
@@ -160,6 +396,20 @@ __global__ void test_tensormap_replace(void** fn_ptr)
         * fn_ptr++ =
           reinterpret_cast<void*>(static_cast<void (*)(cuda::ptx::space_global_t, void*, cuda::ptx::n32_t<0>)>(
             cuda::ptx::tensormap_replace_interleave_layout));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tensormap.replace.tile.interleave_layout.global.b1024.b32 [tm_addr], new_val;
+        * fn_ptr++ =
+          reinterpret_cast<void*>(static_cast<void (*)(cuda::ptx::space_global_t, void*, cuda::ptx::n32_t<0>)>(
+            cuda::ptx::tensormap_replace_interleave_layout));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // tensormap.replace.tile.interleave_layout.global.b1024.b32 [tm_addr], new_val;
+        * fn_ptr++ =
+          reinterpret_cast<void*>(static_cast<void (*)(cuda::ptx::space_global_t, void*, cuda::ptx::n32_t<0>)>(
+            cuda::ptx::tensormap_replace_interleave_layout));));
 #endif // __cccl_ptx_isa >= 830
 
 #if __cccl_ptx_isa >= 830
@@ -170,13 +420,41 @@ __global__ void test_tensormap_replace(void** fn_ptr)
         * fn_ptr++ =
           reinterpret_cast<void*>(static_cast<void (*)(cuda::ptx::space_shared_t, void*, cuda::ptx::n32_t<0>)>(
             cuda::ptx::tensormap_replace_interleave_layout));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tensormap.replace.tile.interleave_layout.shared::cta.b1024.b32 [tm_addr], new_val;
+        * fn_ptr++ =
+          reinterpret_cast<void*>(static_cast<void (*)(cuda::ptx::space_shared_t, void*, cuda::ptx::n32_t<0>)>(
+            cuda::ptx::tensormap_replace_interleave_layout));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // tensormap.replace.tile.interleave_layout.shared::cta.b1024.b32 [tm_addr], new_val;
+        * fn_ptr++ =
+          reinterpret_cast<void*>(static_cast<void (*)(cuda::ptx::space_shared_t, void*, cuda::ptx::n32_t<0>)>(
+            cuda::ptx::tensormap_replace_interleave_layout));));
 #endif // __cccl_ptx_isa >= 830
 
 #if __cccl_ptx_isa >= 830
   NV_IF_TARGET(
     NV_HAS_FEATURE_SM_90a,
     (
-        // tensormap.replace.tile.swizzle_mode.global.b1024.b32      [tm_addr], new_val;
+        // tensormap.replace.tile.swizzle_mode.global.b1024.b32 [tm_addr], new_val;
+        * fn_ptr++ =
+          reinterpret_cast<void*>(static_cast<void (*)(cuda::ptx::space_global_t, void*, cuda::ptx::n32_t<0>)>(
+            cuda::ptx::tensormap_replace_swizzle_mode));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tensormap.replace.tile.swizzle_mode.global.b1024.b32 [tm_addr], new_val;
+        * fn_ptr++ =
+          reinterpret_cast<void*>(static_cast<void (*)(cuda::ptx::space_global_t, void*, cuda::ptx::n32_t<0>)>(
+            cuda::ptx::tensormap_replace_swizzle_mode));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // tensormap.replace.tile.swizzle_mode.global.b1024.b32 [tm_addr], new_val;
         * fn_ptr++ =
           reinterpret_cast<void*>(static_cast<void (*)(cuda::ptx::space_global_t, void*, cuda::ptx::n32_t<0>)>(
             cuda::ptx::tensormap_replace_swizzle_mode));));
@@ -186,7 +464,21 @@ __global__ void test_tensormap_replace(void** fn_ptr)
   NV_IF_TARGET(
     NV_HAS_FEATURE_SM_90a,
     (
-        // tensormap.replace.tile.swizzle_mode.shared::cta.b1024.b32      [tm_addr], new_val;
+        // tensormap.replace.tile.swizzle_mode.shared::cta.b1024.b32 [tm_addr], new_val;
+        * fn_ptr++ =
+          reinterpret_cast<void*>(static_cast<void (*)(cuda::ptx::space_shared_t, void*, cuda::ptx::n32_t<0>)>(
+            cuda::ptx::tensormap_replace_swizzle_mode));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tensormap.replace.tile.swizzle_mode.shared::cta.b1024.b32 [tm_addr], new_val;
+        * fn_ptr++ =
+          reinterpret_cast<void*>(static_cast<void (*)(cuda::ptx::space_shared_t, void*, cuda::ptx::n32_t<0>)>(
+            cuda::ptx::tensormap_replace_swizzle_mode));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // tensormap.replace.tile.swizzle_mode.shared::cta.b1024.b32 [tm_addr], new_val;
         * fn_ptr++ =
           reinterpret_cast<void*>(static_cast<void (*)(cuda::ptx::space_shared_t, void*, cuda::ptx::n32_t<0>)>(
             cuda::ptx::tensormap_replace_swizzle_mode));));
@@ -196,7 +488,21 @@ __global__ void test_tensormap_replace(void** fn_ptr)
   NV_IF_TARGET(
     NV_HAS_FEATURE_SM_90a,
     (
-        // tensormap.replace.tile.fill_mode.global.b1024.b32         [tm_addr], new_val;
+        // tensormap.replace.tile.fill_mode.global.b1024.b32 [tm_addr], new_val;
+        * fn_ptr++ =
+          reinterpret_cast<void*>(static_cast<void (*)(cuda::ptx::space_global_t, void*, cuda::ptx::n32_t<0>)>(
+            cuda::ptx::tensormap_replace_fill_mode));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tensormap.replace.tile.fill_mode.global.b1024.b32 [tm_addr], new_val;
+        * fn_ptr++ =
+          reinterpret_cast<void*>(static_cast<void (*)(cuda::ptx::space_global_t, void*, cuda::ptx::n32_t<0>)>(
+            cuda::ptx::tensormap_replace_fill_mode));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // tensormap.replace.tile.fill_mode.global.b1024.b32 [tm_addr], new_val;
         * fn_ptr++ =
           reinterpret_cast<void*>(static_cast<void (*)(cuda::ptx::space_global_t, void*, cuda::ptx::n32_t<0>)>(
             cuda::ptx::tensormap_replace_fill_mode));));
@@ -206,9 +512,57 @@ __global__ void test_tensormap_replace(void** fn_ptr)
   NV_IF_TARGET(
     NV_HAS_FEATURE_SM_90a,
     (
-        // tensormap.replace.tile.fill_mode.shared::cta.b1024.b32         [tm_addr], new_val;
+        // tensormap.replace.tile.fill_mode.shared::cta.b1024.b32 [tm_addr], new_val;
+        * fn_ptr++ =
+          reinterpret_cast<void*>(static_cast<void (*)(cuda::ptx::space_shared_t, void*, cuda::ptx::n32_t<0>)>(
+            cuda::ptx::tensormap_replace_fill_mode));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tensormap.replace.tile.fill_mode.shared::cta.b1024.b32 [tm_addr], new_val;
+        * fn_ptr++ =
+          reinterpret_cast<void*>(static_cast<void (*)(cuda::ptx::space_shared_t, void*, cuda::ptx::n32_t<0>)>(
+            cuda::ptx::tensormap_replace_fill_mode));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // tensormap.replace.tile.fill_mode.shared::cta.b1024.b32 [tm_addr], new_val;
         * fn_ptr++ =
           reinterpret_cast<void*>(static_cast<void (*)(cuda::ptx::space_shared_t, void*, cuda::ptx::n32_t<0>)>(
             cuda::ptx::tensormap_replace_fill_mode));));
 #endif // __cccl_ptx_isa >= 830
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tensormap.replace.tile.swizzle_atomicity.global.b1024.b32 [tm_addr], new_val;
+        * fn_ptr++ =
+          reinterpret_cast<void*>(static_cast<void (*)(cuda::ptx::space_global_t, void*, cuda::ptx::n32_t<0>)>(
+            cuda::ptx::tensormap_replace_swizzle_atomicity));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // tensormap.replace.tile.swizzle_atomicity.global.b1024.b32 [tm_addr], new_val;
+        * fn_ptr++ =
+          reinterpret_cast<void*>(static_cast<void (*)(cuda::ptx::space_global_t, void*, cuda::ptx::n32_t<0>)>(
+            cuda::ptx::tensormap_replace_swizzle_atomicity));));
+#endif // __cccl_ptx_isa >= 860
+
+#if __cccl_ptx_isa >= 860
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_100a,
+    (
+        // tensormap.replace.tile.swizzle_atomicity.shared::cta.b1024.b32 [tm_addr], new_val;
+        * fn_ptr++ =
+          reinterpret_cast<void*>(static_cast<void (*)(cuda::ptx::space_shared_t, void*, cuda::ptx::n32_t<0>)>(
+            cuda::ptx::tensormap_replace_swizzle_atomicity));));
+  NV_IF_TARGET(
+    NV_HAS_FEATURE_SM_101a,
+    (
+        // tensormap.replace.tile.swizzle_atomicity.shared::cta.b1024.b32 [tm_addr], new_val;
+        * fn_ptr++ =
+          reinterpret_cast<void*>(static_cast<void (*)(cuda::ptx::space_shared_t, void*, cuda::ptx::n32_t<0>)>(
+            cuda::ptx::tensormap_replace_swizzle_atomicity));));
+#endif // __cccl_ptx_isa >= 860
 }
diff --git a/libcudacxx/test/libcudacxx/cuda/ptx/nvrtc_workaround.h b/libcudacxx/test/libcudacxx/cuda/ptx/nvrtc_workaround.h
new file mode 100644
index 00000000000..fef34f25ef4
--- /dev/null
+++ b/libcudacxx/test/libcudacxx/cuda/ptx/nvrtc_workaround.h
@@ -0,0 +1,34 @@
+//===----------------------------------------------------------------------===//
+//
+// Part of libcu++, the C++ Standard Library for your entire system,
+// under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+// SPDX-FileCopyrightText: Copyright (c) 2025 NVIDIA CORPORATION & AFFILIATES.
+//
+//===----------------------------------------------------------------------===//
+
+// NVRTC ships a built-in copy of <nv/detail/__target_macros>, so including CCCL's version of this header will omit the
+// content since the header guards are already defined. To make older NVRTC versions have a few newer feature macros
+// required for the PTX tests, we define them here outside the header guards.
+// TODO(bgruber): limit this workaround to NVRTC versions older than the first one shipping those macros
+#ifdef __CUDACC_RTC__
+#  ifndef NV_HAS_FEATURE_SM_100a
+#    define NV_HAS_FEATURE_SM_100a __NV_HAS_FEATURE_SM_100a
+#    if (defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 1000) && defined(__CUDA_ARCH_FEAT_SM100_ALL))
+#      define _NV_TARGET_BOOL___NV_HAS_FEATURE_SM_100a 1
+#    else
+#      define _NV_TARGET_BOOL___NV_HAS_FEATURE_SM_100a 0
+#    endif
+#  endif // NV_HAS_FEATURE_SM_100a
+
+// Re-enable sm_101a support in nvcc.
+#  ifndef NV_HAS_FEATURE_SM_101a
+#    define NV_HAS_FEATURE_SM_101a __NV_HAS_FEATURE_SM_101a
+#    if (defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 1010) && defined(__CUDA_ARCH_FEAT_SM101_ALL))
+#      define _NV_TARGET_BOOL___NV_HAS_FEATURE_SM_101a 1
+#    else
+#      define _NV_TARGET_BOOL___NV_HAS_FEATURE_SM_101a 0
+#    endif
+#  endif // NV_HAS_FEATURE_SM_101a
+#endif // __CUDACC_RTC__
diff --git a/libcudacxx/test/libcudacxx/cuda/ptx/ptx.barrier.cluster.compile.pass.cpp b/libcudacxx/test/libcudacxx/cuda/ptx/ptx.barrier.cluster.compile.pass.cpp
index 33d08621ef4..003d8f97017 100644
--- a/libcudacxx/test/libcudacxx/cuda/ptx/ptx.barrier.cluster.compile.pass.cpp
+++ b/libcudacxx/test/libcudacxx/cuda/ptx/ptx.barrier.cluster.compile.pass.cpp
@@ -14,6 +14,8 @@
 #include <cuda/ptx>
 #include <cuda/std/utility>
 
+#include "nvrtc_workaround.h"
+// above header needs to be included before the generated test header
 #include "generated/barrier_cluster.h"
 
 int main(int, char**)
diff --git a/libcudacxx/test/libcudacxx/cuda/ptx/ptx.cp.async.bulk.commit_group.compile.pass.cpp b/libcudacxx/test/libcudacxx/cuda/ptx/ptx.cp.async.bulk.commit_group.compile.pass.cpp
index e7ff21c2730..1bf931109ed 100644
--- a/libcudacxx/test/libcudacxx/cuda/ptx/ptx.cp.async.bulk.commit_group.compile.pass.cpp
+++ b/libcudacxx/test/libcudacxx/cuda/ptx/ptx.cp.async.bulk.commit_group.compile.pass.cpp
@@ -14,6 +14,8 @@
 #include <cuda/ptx>
 #include <cuda/std/utility>
 
+#include "nvrtc_workaround.h"
+// above header needs to be included before the generated test header
 #include "generated/cp_async_bulk_commit_group.h"
 
 int main(int, char**)
diff --git a/libcudacxx/test/libcudacxx/cuda/ptx/ptx.cp.async.bulk.compile.pass.cpp b/libcudacxx/test/libcudacxx/cuda/ptx/ptx.cp.async.bulk.compile.pass.cpp
index fdd35749cc6..be56b1b922c 100644
--- a/libcudacxx/test/libcudacxx/cuda/ptx/ptx.cp.async.bulk.compile.pass.cpp
+++ b/libcudacxx/test/libcudacxx/cuda/ptx/ptx.cp.async.bulk.compile.pass.cpp
@@ -14,6 +14,8 @@
 #include <cuda/ptx>
 #include <cuda/std/utility>
 
+#include "nvrtc_workaround.h"
+// above header needs to be included before the generated test header
 #include "generated/cp_async_bulk.h"
 
 int main(int, char**)
diff --git a/libcudacxx/test/libcudacxx/cuda/ptx/ptx.cp.async.bulk.multicast.compile.pass.cpp b/libcudacxx/test/libcudacxx/cuda/ptx/ptx.cp.async.bulk.multicast.compile.pass.cpp
index ae1546828ae..226dbe5cf47 100644
--- a/libcudacxx/test/libcudacxx/cuda/ptx/ptx.cp.async.bulk.multicast.compile.pass.cpp
+++ b/libcudacxx/test/libcudacxx/cuda/ptx/ptx.cp.async.bulk.multicast.compile.pass.cpp
@@ -16,6 +16,8 @@
 #include <cuda/ptx>
 #include <cuda/std/utility>
 
+#include "nvrtc_workaround.h"
+// above header needs to be included before the generated test header
 #include "generated/cp_async_bulk_multicast.h"
 
 int main(int, char**)
diff --git a/libcudacxx/test/libcudacxx/cuda/ptx/ptx.cp.async.bulk.tensor.compile.pass.cpp b/libcudacxx/test/libcudacxx/cuda/ptx/ptx.cp.async.bulk.tensor.compile.pass.cpp
index eeb7b4bf5a5..42bc5b8e355 100644
--- a/libcudacxx/test/libcudacxx/cuda/ptx/ptx.cp.async.bulk.tensor.compile.pass.cpp
+++ b/libcudacxx/test/libcudacxx/cuda/ptx/ptx.cp.async.bulk.tensor.compile.pass.cpp
@@ -14,6 +14,8 @@
 #include <cuda/ptx>
 #include <cuda/std/utility>
 
+#include "nvrtc_workaround.h"
+// above header needs to be included before the generated test header
 #include "generated/cp_async_bulk_tensor.h"
 
 int main(int, char**)
diff --git a/libcudacxx/test/libcudacxx/cuda/ptx/ptx.cp.async.bulk.tensor.multicast.compile.pass.cpp b/libcudacxx/test/libcudacxx/cuda/ptx/ptx.cp.async.bulk.tensor.multicast.compile.pass.cpp
index d07351a2275..65172d72897 100644
--- a/libcudacxx/test/libcudacxx/cuda/ptx/ptx.cp.async.bulk.tensor.multicast.compile.pass.cpp
+++ b/libcudacxx/test/libcudacxx/cuda/ptx/ptx.cp.async.bulk.tensor.multicast.compile.pass.cpp
@@ -16,6 +16,8 @@
 #include <cuda/ptx>
 #include <cuda/std/utility>
 
+#include "nvrtc_workaround.h"
+// above header needs to be included before the generated test header
 #include "generated/cp_async_bulk_tensor_multicast.h"
 
 int main(int, char**)
diff --git a/libcudacxx/test/libcudacxx/cuda/ptx/ptx.cp.async.bulk.wait_group.compile.pass.cpp b/libcudacxx/test/libcudacxx/cuda/ptx/ptx.cp.async.bulk.wait_group.compile.pass.cpp
index 87910d04941..b31a9fb6a81 100644
--- a/libcudacxx/test/libcudacxx/cuda/ptx/ptx.cp.async.bulk.wait_group.compile.pass.cpp
+++ b/libcudacxx/test/libcudacxx/cuda/ptx/ptx.cp.async.bulk.wait_group.compile.pass.cpp
@@ -14,6 +14,8 @@
 #include <cuda/ptx>
 #include <cuda/std/utility>
 
+#include "nvrtc_workaround.h"
+// above header needs to be included before the generated test header
 #include "generated/cp_async_bulk_wait_group.h"
 
 int main(int, char**)
diff --git a/libcudacxx/test/libcudacxx/cuda/ptx/ptx.cp.reduce.async.bulk.compile.pass.cpp b/libcudacxx/test/libcudacxx/cuda/ptx/ptx.cp.reduce.async.bulk.compile.pass.cpp
index 8b916d74bf9..76a9357ae2f 100644
--- a/libcudacxx/test/libcudacxx/cuda/ptx/ptx.cp.reduce.async.bulk.compile.pass.cpp
+++ b/libcudacxx/test/libcudacxx/cuda/ptx/ptx.cp.reduce.async.bulk.compile.pass.cpp
@@ -14,6 +14,8 @@
 #include <cuda/ptx>
 #include <cuda/std/utility>
 
+#include "nvrtc_workaround.h"
+// above header needs to be included before the generated test header
 #include "generated/cp_reduce_async_bulk.h"
 
 #ifdef _LIBCUDACXX_HAS_NVF16
diff --git a/libcudacxx/test/libcudacxx/cuda/ptx/ptx.cp.reduce.async.bulk.tensor.compile.pass.cpp b/libcudacxx/test/libcudacxx/cuda/ptx/ptx.cp.reduce.async.bulk.tensor.compile.pass.cpp
index f6a6fd61735..289f3dd9411 100644
--- a/libcudacxx/test/libcudacxx/cuda/ptx/ptx.cp.reduce.async.bulk.tensor.compile.pass.cpp
+++ b/libcudacxx/test/libcudacxx/cuda/ptx/ptx.cp.reduce.async.bulk.tensor.compile.pass.cpp
@@ -14,6 +14,8 @@
 #include <cuda/ptx>
 #include <cuda/std/utility>
 
+#include "nvrtc_workaround.h"
+// above header needs to be included before the generated test header
 #include "generated/cp_reduce_async_bulk_tensor.h"
 
 int main(int, char**)
diff --git a/libcudacxx/test/libcudacxx/cuda/ptx/ptx.fence.compile.pass.cpp b/libcudacxx/test/libcudacxx/cuda/ptx/ptx.fence.compile.pass.cpp
index 56f54b345f7..c439720b8f8 100644
--- a/libcudacxx/test/libcudacxx/cuda/ptx/ptx.fence.compile.pass.cpp
+++ b/libcudacxx/test/libcudacxx/cuda/ptx/ptx.fence.compile.pass.cpp
@@ -14,6 +14,8 @@
 #include <cuda/ptx>
 #include <cuda/std/utility>
 
+#include "nvrtc_workaround.h"
+// above header needs to be included before the generated test header
 #include "generated/fence.h"
 #include "generated/fence_mbarrier_init.h"
 #include "generated/fence_proxy_alias.h"
diff --git a/libcudacxx/test/libcudacxx/cuda/ptx/ptx.get_sreg.compile.pass.cpp b/libcudacxx/test/libcudacxx/cuda/ptx/ptx.get_sreg.compile.pass.cpp
index 91a6dd94bf1..adf6bb3e769 100644
--- a/libcudacxx/test/libcudacxx/cuda/ptx/ptx.get_sreg.compile.pass.cpp
+++ b/libcudacxx/test/libcudacxx/cuda/ptx/ptx.get_sreg.compile.pass.cpp
@@ -15,6 +15,8 @@
 #include <cuda/ptx>
 #include <cuda/std/utility>
 
+#include "nvrtc_workaround.h"
+// above header needs to be included before the generated test header
 #include "generated/get_sreg.h"
 
 int main(int, char**)
diff --git a/libcudacxx/test/libcudacxx/cuda/ptx/ptx.getctarank.compile.pass.cpp b/libcudacxx/test/libcudacxx/cuda/ptx/ptx.getctarank.compile.pass.cpp
index ed39816b7d6..9935b0563d2 100644
--- a/libcudacxx/test/libcudacxx/cuda/ptx/ptx.getctarank.compile.pass.cpp
+++ b/libcudacxx/test/libcudacxx/cuda/ptx/ptx.getctarank.compile.pass.cpp
@@ -14,6 +14,8 @@
 #include <cuda/ptx>
 #include <cuda/std/utility>
 
+#include "nvrtc_workaround.h"
+// above header needs to be included before the generated test header
 #include "generated/getctarank.h"
 
 int main(int, char**)
diff --git a/libcudacxx/test/libcudacxx/cuda/ptx/ptx.mbarrier.arrive.compile.pass.cpp b/libcudacxx/test/libcudacxx/cuda/ptx/ptx.mbarrier.arrive.compile.pass.cpp
index 93263910906..a0948e86b18 100644
--- a/libcudacxx/test/libcudacxx/cuda/ptx/ptx.mbarrier.arrive.compile.pass.cpp
+++ b/libcudacxx/test/libcudacxx/cuda/ptx/ptx.mbarrier.arrive.compile.pass.cpp
@@ -14,6 +14,8 @@
 #include <cuda/ptx>
 #include <cuda/std/utility>
 
+#include "nvrtc_workaround.h"
+// above header needs to be included before the generated test header
 #include "generated/mbarrier_arrive.h"
 #include "generated/mbarrier_arrive_expect_tx.h"
 #include "generated/mbarrier_arrive_no_complete.h"
diff --git a/libcudacxx/test/libcudacxx/cuda/ptx/ptx.mbarrier.init.compile.pass.cpp b/libcudacxx/test/libcudacxx/cuda/ptx/ptx.mbarrier.init.compile.pass.cpp
index 7af0db56b70..0583b4f6e29 100644
--- a/libcudacxx/test/libcudacxx/cuda/ptx/ptx.mbarrier.init.compile.pass.cpp
+++ b/libcudacxx/test/libcudacxx/cuda/ptx/ptx.mbarrier.init.compile.pass.cpp
@@ -14,6 +14,8 @@
 #include <cuda/ptx>
 #include <cuda/std/utility>
 
+#include "nvrtc_workaround.h"
+// above header needs to be included before the generated test header
 #include "generated/mbarrier_init.h"
 
 int main(int, char**)
diff --git a/libcudacxx/test/libcudacxx/cuda/ptx/ptx.mbarrier.wait.compile.pass.cpp b/libcudacxx/test/libcudacxx/cuda/ptx/ptx.mbarrier.wait.compile.pass.cpp
index 896abb8a7d8..732db4f16a1 100644
--- a/libcudacxx/test/libcudacxx/cuda/ptx/ptx.mbarrier.wait.compile.pass.cpp
+++ b/libcudacxx/test/libcudacxx/cuda/ptx/ptx.mbarrier.wait.compile.pass.cpp
@@ -14,10 +14,12 @@
 #include <cuda/ptx>
 #include <cuda/std/utility>
 
+#include "nvrtc_workaround.h"
+// above header needs to be included before the generated test header
+#include "generated/mbarrier_test_wait.h"
+#include "generated/mbarrier_test_wait_parity.h"
 #include "generated/mbarrier_try_wait.h"
 #include "generated/mbarrier_try_wait_parity.h"
-#include "generated/mbarrier_wait.h"
-#include "generated/mbarrier_wait_parity.h"
 
 int main(int, char**)
 {
diff --git a/libcudacxx/test/libcudacxx/cuda/ptx/ptx.red.async.compile.pass.cpp b/libcudacxx/test/libcudacxx/cuda/ptx/ptx.red.async.compile.pass.cpp
index c6f66503b1f..2993ba3893d 100644
--- a/libcudacxx/test/libcudacxx/cuda/ptx/ptx.red.async.compile.pass.cpp
+++ b/libcudacxx/test/libcudacxx/cuda/ptx/ptx.red.async.compile.pass.cpp
@@ -14,6 +14,8 @@
 #include <cuda/ptx>
 #include <cuda/std/utility>
 
+#include "nvrtc_workaround.h"
+// above header needs to be included before the generated test header
 #include "generated/red_async.h"
 
 int main(int, char**)
diff --git a/libcudacxx/test/libcudacxx/cuda/ptx/ptx.st.async.compile.pass.cpp b/libcudacxx/test/libcudacxx/cuda/ptx/ptx.st.async.compile.pass.cpp
index 7c008b77126..a833a3770f4 100644
--- a/libcudacxx/test/libcudacxx/cuda/ptx/ptx.st.async.compile.pass.cpp
+++ b/libcudacxx/test/libcudacxx/cuda/ptx/ptx.st.async.compile.pass.cpp
@@ -14,6 +14,8 @@
 #include <cuda/ptx>
 #include <cuda/std/utility>
 
+#include "nvrtc_workaround.h"
+// above header needs to be included before the generated test header
 #include "generated/st_async.h"
 
 int main(int, char**)
diff --git a/libcudacxx/test/libcudacxx/cuda/ptx/ptx.tensormap.cp_fenceproxy.compile.pass.cpp b/libcudacxx/test/libcudacxx/cuda/ptx/ptx.tensormap.cp_fenceproxy.compile.pass.cpp
index bb5578fc730..5d8566be5b5 100644
--- a/libcudacxx/test/libcudacxx/cuda/ptx/ptx.tensormap.cp_fenceproxy.compile.pass.cpp
+++ b/libcudacxx/test/libcudacxx/cuda/ptx/ptx.tensormap.cp_fenceproxy.compile.pass.cpp
@@ -14,6 +14,8 @@
 #include <cuda/ptx>
 #include <cuda/std/utility>
 
+#include "nvrtc_workaround.h"
+// above header needs to be included before the generated test header
 #include "generated/tensormap_cp_fenceproxy.h"
 
 int main(int, char**)
diff --git a/libcudacxx/test/libcudacxx/cuda/ptx/ptx.tensormap.replace.compile.pass.cpp b/libcudacxx/test/libcudacxx/cuda/ptx/ptx.tensormap.replace.compile.pass.cpp
index 264b7956fbb..f0c91aa2296 100644
--- a/libcudacxx/test/libcudacxx/cuda/ptx/ptx.tensormap.replace.compile.pass.cpp
+++ b/libcudacxx/test/libcudacxx/cuda/ptx/ptx.tensormap.replace.compile.pass.cpp
@@ -14,6 +14,8 @@
 #include <cuda/ptx>
 #include <cuda/std/utility>
 
+#include "nvrtc_workaround.h"
+// above header needs to be included before the generated test header
 #include "generated/tensormap_replace.h"
 
 int main(int, char**)

From 671ee2fc626f609bfae3f744ff4fb3d6b7109d47 Mon Sep 17 00:00:00 2001
From: Allison Piper <alliepiper16@gmail.com>
Date: Wed, 29 Jan 2025 19:44:57 -0500
Subject: [PATCH 10/33] Update CI matrix to use NVKS nodes. (#3572)

* Update CI matrix to use NVKS nodes.
* Update windows CI scripts to accept -arch.
* Move all non-Catch2 device algo tests to lid0/lid1.
This makes sure that they run in the correct CI config on appropriate hardware.
* Switch to all rtx queues:
CUB -> RTXA6000 (48GiB)
Thrust -> RTX4090 (24GiB)
Others -> RTX2080 (8GiB)
---
 ci/matrix.yaml                  | 73 ++++++++++++++-------------------
 ci/windows/build_common.psm1    | 15 ++++++-
 ci/windows/build_cub.ps1        |  8 +++-
 ci/windows/build_cudax.ps1      |  8 +++-
 ci/windows/build_libcudacxx.ps1 |  8 +++-
 ci/windows/build_thrust.ps1     |  8 +++-
 ci/windows/test_thrust.ps1      |  8 +++-
 cub/test/CMakeLists.txt         |  9 ++++
 8 files changed, 83 insertions(+), 54 deletions(-)

diff --git a/ci/matrix.yaml b/ci/matrix.yaml
index c3f03d323ab..5ec715fb59b 100644
--- a/ci/matrix.yaml
+++ b/ci/matrix.yaml
@@ -19,49 +19,51 @@ workflows:
     - {jobs: ['build'], std: 'max', cxx: ['msvc2019']}
     - {jobs: ['build'], std: 'all', cxx: ['gcc', 'clang', 'msvc']}
     # Current CTK testing:
-    - {jobs: ['test'],  project: ['libcudacxx', 'thrust'], std: 'max', cxx: ['gcc', 'clang']}
+    - {jobs: ['test'],  project: ['thrust'],     std: 'max', cxx: ['gcc', 'clang'], gpu: 'rtx4090'}
+    - {jobs: ['test'],  project: ['libcudacxx'], std: 'max', cxx: ['gcc', 'clang'], gpu: 'rtx2080'}
     # Disabled until we figure out the issue with the TBB dll
-    #- {jobs: ['test'],  project: ['libcudacxx', 'thrust'], std: 'max', cxx: ['msvc']}
+   #- {jobs: ['test'],  project: ['thrust'],     std: 'max', cxx: ['msvc'], gpu: 'rtx4090'}
+    - {jobs: ['test'],  project: ['libcudacxx'], std: 'max', cxx: ['msvc'], gpu: 'rtx2080'}
     # Split up cub tests:
-    - {jobs: ['test_nolid', 'test_lid0'], project: ['cub'], std: 'max', cxx: ['gcc']}
-    - {jobs: ['test_lid1',  'test_lid2'], project: ['cub'], std: 'max', cxx: ['gcc']}
-    - {jobs: ['test_nolid', 'test_lid0'], project: ['cub'], std: 'max', cxx: ['clang', 'msvc']}
-    - {jobs: ['test_lid0'],               project: ['cub'], std: 'max', cxx: 'gcc12', gpu: 'h100',  sm: 'gpu' }
+    - {jobs: ['test_nolid', 'test_lid0'], project: ['cub'], std: 'max', cxx: ['gcc'],           gpu: 'rtxa6000'}
+    - {jobs: ['test_lid1', 'test_lid2'],  project: ['cub'], std: 'max', cxx: ['gcc'],           gpu: 'rtxa6000'}
+    - {jobs: ['test_nolid', 'test_lid0'], project: ['cub'], std: 'max', cxx: ['clang', 'msvc'], gpu: 'rtxa6000'}
+    - {jobs: ['test_lid0'],               project: ['cub'], std: 'max', cxx: 'gcc12',           gpu: 'h100', sm: 'gpu' }
     # Modded builds:
     - {jobs: ['build'], std: 'all', ctk: '12.5', cxx: 'nvhpc'}
     - {jobs: ['build'], std: 'max', cxx: ['gcc', 'clang'], cpu: 'arm64'}
     - {jobs: ['build'], std: 'max', cxx: ['gcc'], sm: '90a'}
     # Test Thrust 32-bit-only dispatch here, since it's most likely to break. 64-bit-only is tested in nightly.
-    - {jobs: ['test_gpu'],  project: 'thrust', cmake_options: '-DTHRUST_DISPATCH_TYPE=Force32bit'}
+    - {jobs: ['test_gpu'],  project: 'thrust', cmake_options: '-DTHRUST_DISPATCH_TYPE=Force32bit', gpu: 'rtx4090'}
     # default_projects: clang-cuda
     - {jobs: ['build'], std: 'all', cudacxx: 'clang', cxx: 'clang'}
     - {jobs: ['build'], project: 'libcudacxx', std: 'max', cudacxx: 'clang', cxx: 'clang', sm: '90'}
     - {jobs: ['build'], project: 'libcudacxx', std: 'max', cudacxx: 'clang', cxx: 'clang', sm: '90a'}
     # nvrtc:
-    - {jobs: ['nvrtc'], project: 'libcudacxx', std: 'all'}
+    - {jobs: ['nvrtc'], project: 'libcudacxx', std: 'all', gpu: 'rtx2080', sm: 'gpu'}
     # verify-codegen:
     - {jobs: ['verify_codegen'], project: 'libcudacxx'}
     # cudax has different CTK reqs:
-    - {jobs: ['build'], project: 'cudax', ctk: ['12.0'], std: 20,       cxx: ['msvc14.36']}
-    - {jobs: ['build'], project: 'cudax', ctk: ['curr'], std: 20,       cxx: ['gcc10', 'gcc11', 'gcc12']}
-    - {jobs: ['build'], project: 'cudax', ctk: ['curr'], std: 20,       cxx: ['clang14', 'clang15', 'clang16', 'clang17']}
+    - {jobs: ['build'], project: 'cudax', ctk: ['12.0'], std: 20,    cxx: ['msvc14.36']}
+    - {jobs: ['build'], project: 'cudax', ctk: ['curr'], std: 20,    cxx: ['gcc10', 'gcc11', 'gcc12']}
+    - {jobs: ['build'], project: 'cudax', ctk: ['curr'], std: 20,    cxx: ['clang14', 'clang15', 'clang16', 'clang17']}
     - {jobs: ['build'], project: 'cudax', ctk: ['12.5'], std: 'all', cxx: ['nvhpc']}
-    - {jobs: ['build'], project: 'cudax', ctk: ['curr'], std: 20,       cxx: ['msvc2022']}
-    - {jobs: ['build'], project: 'cudax', ctk: ['curr'], std: 17,       cxx: ['gcc'], sm: "90"}
-    - {jobs: ['build'], project: 'cudax', ctk: ['curr'], std: 20,       cxx: ['gcc'], sm: "90a"}
+    - {jobs: ['build'], project: 'cudax', ctk: ['curr'], std: 20,    cxx: ['msvc2022']}
+    - {jobs: ['build'], project: 'cudax', ctk: ['curr'], std: 17,    cxx: ['gcc'], sm: "90"}
+    - {jobs: ['build'], project: 'cudax', ctk: ['curr'], std: 20,    cxx: ['gcc'], sm: "90a"}
     - {jobs: ['build'], project: 'cudax', ctk: ['curr'], std: 'all', cxx: ['gcc', 'clang'], cpu: 'arm64'}
-    - {jobs: ['test'],  project: 'cudax', ctk: ['curr'], std: 20,       cxx: ['gcc12', 'clang', 'msvc']}
+    - {jobs: ['test'],  project: 'cudax', ctk: ['curr'], std: 20,    cxx: ['gcc12', 'clang', 'msvc'], gpu: 'rtx2080'}
     # Python and c/parallel jobs:
-    - {jobs: ['test'], project: ['cccl_c_parallel', 'python'], ctk: '12.6'}
+    - {jobs: ['test'], project: ['cccl_c_parallel', 'python'], ctk: '12.6', gpu: 'rtx2080'}
     # cccl-infra:
-    - {jobs: ['infra'], project: 'cccl', ctk: '12.0', cxx: ['gcc12', 'clang14']}
-    - {jobs: ['infra'], project: 'cccl', ctk: 'curr', cxx: ['gcc',   'clang']}
+    - {jobs: ['infra'], project: 'cccl', ctk: '12.0', cxx: ['gcc12', 'clang14'], gpu: 'rtx2080'}
+    - {jobs: ['infra'], project: 'cccl', ctk: 'curr', cxx: ['gcc',   'clang'],   gpu: 'rtx2080'}
 
   nightly:
     # Edge-case jobs
-    - {jobs: ['limited'], project: 'cub', std: 17}
-    - {jobs: ['test_gpu'],  project: 'thrust', cmake_options: '-DTHRUST_DISPATCH_TYPE=Force32bit'}
-    - {jobs: ['test_gpu'],  project: 'thrust', cmake_options: '-DTHRUST_DISPATCH_TYPE=Force64bit'}
+    - {jobs: ['limited'], project: 'cub', std: 17, gpu: 'rtx2080'}
+    - {jobs: ['test_gpu'],  project: 'thrust', cmake_options: '-DTHRUST_DISPATCH_TYPE=Force32bit', gpu: 'rtx4090'}
+    - {jobs: ['test_gpu'],  project: 'thrust', cmake_options: '-DTHRUST_DISPATCH_TYPE=Force64bit', gpu: 'rtx4090'}
     # Old CTK/compiler
     - {jobs: ['build'], std: 'all', ctk: '12.0', cxx: ['gcc7', 'gcc8', 'gcc9', 'clang14', 'msvc2019']}
     - {jobs: ['build'], std: 'all', ctk: '12.0', cxx: ['gcc11'], sm: '60;70;80;90'}
@@ -70,7 +72,11 @@ workflows:
     - {jobs: ['build'], std: 'all', cxx: ['clang14', 'clang15', 'clang16', 'clang17']}
     - {jobs: ['build'], std: 'all', cxx: ['msvc2019']}
     # Test current CTK
-    - {jobs: ['test'],  std: 'all', cxx: ['gcc13', 'clang18', 'msvc2022']}
+    - {jobs: ['test'],      project: 'cub',        std: 'all', cxx: ['gcc', 'clang', 'msvc'], gpu: 'rtxa6000'}
+    - {jobs: ['test_lid0'], project: 'cub',        std: 'max', cxx: 'gcc',                    gpu: 'v100'}
+    - {jobs: ['test_lid0'], project: 'cub',        std: 'max', cxx: 'gcc',                    gpu: 'h100', sm: 'gpu' }
+    - {jobs: ['test'],      project: 'thrust',     std: 'all', cxx: ['gcc', 'clang', 'msvc'], gpu: 'rtx4090'}
+    - {jobs: ['test'],      project: 'libcudacxx', std: 'all', cxx: ['gcc', 'clang', 'msvc'], gpu: 'rtx2080'}
     # Modded builds:
     - {jobs: ['build'], std: 'all', ctk: '12.5', cxx: 'nvhpc'}
     - {jobs: ['build'], std: 'all', cxx: ['gcc', 'clang'], cpu: 'arm64'}
@@ -88,26 +94,9 @@ workflows:
     - {jobs: ['build'], project: 'cudax', ctk: ['12.0'        ], std: 'all', cxx: ['gcc12'], sm: "90"}
     - {jobs: ['build'], project: 'cudax', ctk: [        'curr'], std: 'all', cxx: ['gcc13'], sm: "90a"}
     - {jobs: ['build'], project: 'cudax', ctk: [        'curr'], std: 'all', cxx: ['gcc13', 'clang16'], cpu: 'arm64'}
-    - {jobs: ['test'],  project: 'cudax', ctk: ['12.0', 'curr'], std: 'all', cxx: ['gcc12']}
-    - {jobs: ['test'],  project: 'cudax', ctk: ['12.0'        ], std: 'all', cxx: ['clang14']}
-    - {jobs: ['test'],  project: 'cudax', ctk: [        'curr'], std: 'all', cxx: ['clang18']}
-
-#  # These are waiting on the NVKS nodes:
-#    - {jobs: ['test'],  ctk: '11.1', gpu: 'v100',     sm: 'gpu', cxx: 'gcc7',    std: [11]}
-#    - {jobs: ['test'],  ctk: '11.1', gpu: 't4',       sm: 'gpu', cxx: 'clang14',  std: [17]}
-#    - {jobs: ['test'],  ctk: '11.8', gpu: 'rtx2080',  sm: 'gpu', cxx: 'gcc11',   std: [17]}
-#    - {jobs: ['test'],  ctk: 'curr', gpu: 'rtxa6000', sm: 'gpu', cxx: 'gcc7',    std: [14]}
-#    - {jobs: ['test'],  ctk: 'curr', gpu: 'l4',       sm: 'gpu', cxx: 'gcc13',   std: 'all'}
-#    - {jobs: ['test'],  ctk: 'curr', gpu: 'rtx4090',  sm: 'gpu', cxx: 'clang14',  std: [11]}
-#    # H100 runners are currently flakey, only build since those use CPU-only runners:
-#    - {jobs: ['build'], ctk: 'curr', gpu: 'h100',     sm: 'gpu', cxx: 'gcc12',   std: [11, 20]}
-#    - {jobs: ['build'], ctk: 'curr', gpu: 'h100',     sm: 'gpu', cxx: 'clang18', std: [17]}
-#
-#   # nvrtc:
-#    - {jobs: ['nvrtc'], ctk: 'curr', gpu: 't4',       sm: 'gpu', cxx: 'gcc13',  std: [20],     project: ['libcudacxx']}
-#    - {jobs: ['nvrtc'], ctk: 'curr', gpu: 'rtxa6000', sm: 'gpu', cxx: 'gcc13',  std: [20],     project: ['libcudacxx']}
-#    - {jobs: ['nvrtc'], ctk: 'curr', gpu: 'l4',       sm: 'gpu', cxx: 'gcc13',  std: 'all',    project: ['libcudacxx']}
-#    - {jobs: ['nvrtc'], ctk: 'curr', gpu: 'h100',     sm: 'gpu', cxx: 'gcc13',  std: [11, 20], project: ['libcudacxx']}
+    - {jobs: ['test'],  project: 'cudax', ctk: ['12.0', 'curr'], std: 'all', cxx: ['gcc12']  , gpu: 'rtx2080'}
+    - {jobs: ['test'],  project: 'cudax', ctk: ['12.0'        ], std: 'all', cxx: ['clang14'], gpu: 'rtx2080'}
+    - {jobs: ['test'],  project: 'cudax', ctk: [        'curr'], std: 'all', cxx: ['clang18'], gpu: 'rtx2080'}
 
   # Any generated jobs that match the entries in `exclude` will be removed from the final matrix for all workflows.
   exclude:
diff --git a/ci/windows/build_common.psm1 b/ci/windows/build_common.psm1
index 1eb5f1a9d63..151bb1f112e 100644
--- a/ci/windows/build_common.psm1
+++ b/ci/windows/build_common.psm1
@@ -3,7 +3,11 @@ Param(
     [Alias("std")]
     [ValidateNotNullOrEmpty()]
     [ValidateSet(11, 14, 17, 20)]
-    [int]$CXX_STANDARD = 17
+    [int]$CXX_STANDARD = 17,
+    [Parameter(Mandatory = $false)]
+    [ValidateNotNullOrEmpty()]
+    [Alias("arch")]
+    [int]$CUDA_ARCH = 0
 )
 
 $ErrorActionPreference = "Stop"
@@ -20,6 +24,12 @@ if ($script:CL_VERSION_STRING -match "Version (\d+\.\d+)\.\d+") {
     Write-Host "Detected cl.exe version: $CL_VERSION"
 }
 
+$script:GLOBAL_CMAKE_OPTIONS = ""
+if ($CUDA_ARCH -ne 0) {
+    $script:GLOBAL_CMAKE_OPTIONS += "-DCMAKE_CUDA_ARCHITECTURES=$CUDA_ARCH"
+}
+
+
 if (-not $env:CCCL_BUILD_INFIX) {
     $env:CCCL_BUILD_INFIX = ""
 }
@@ -56,6 +66,7 @@ Write-Host "NVCC_VERSION=$NVCC_VERSION"
 Write-Host "CMAKE_BUILD_PARALLEL_LEVEL=$env:CMAKE_BUILD_PARALLEL_LEVEL"
 Write-Host "CTEST_PARALLEL_LEVEL=$env:CTEST_PARALLEL_LEVEL"
 Write-Host "CCCL_BUILD_INFIX=$env:CCCL_BUILD_INFIX"
+Write-Host "GLOBAL_CMAKE_OPTIONS=$script:GLOBAL_CMAKE_OPTIONS"
 Write-Host "Current commit is:"
 Write-Host "$(git log -1 --format=short)"
 Write-Host "========================================"
@@ -82,7 +93,7 @@ function configure_preset {
     pushd ".."
 
     # Echo and execute command to stdout:
-    $configure_command = "cmake --preset $PRESET $CMAKE_OPTIONS --log-level VERBOSE"
+    $configure_command = "cmake --preset $PRESET $script:GLOBAL_CMAKE_OPTIONS $CMAKE_OPTIONS --log-level VERBOSE"
     Write-Host $configure_command
     Invoke-Expression $configure_command
     $test_result = $LastExitCode
diff --git a/ci/windows/build_cub.ps1 b/ci/windows/build_cub.ps1
index 32e4f71ee9a..27c5360ded9 100644
--- a/ci/windows/build_cub.ps1
+++ b/ci/windows/build_cub.ps1
@@ -3,7 +3,11 @@ Param(
     [Alias("std")]
     [ValidateNotNullOrEmpty()]
     [ValidateSet(11, 14, 17, 20)]
-    [int]$CXX_STANDARD = 17
+    [int]$CXX_STANDARD = 17,
+    [Parameter(Mandatory = $false)]
+    [ValidateNotNullOrEmpty()]
+    [Alias("arch")]
+    [int]$CUDA_ARCH = 0
 )
 
 $ErrorActionPreference = "Stop"
@@ -14,7 +18,7 @@ If($CURRENT_PATH -ne "ci") {
     pushd "$PSScriptRoot/.."
 }
 
-Import-Module $PSScriptRoot/build_common.psm1 -ArgumentList $CXX_STANDARD
+Import-Module $PSScriptRoot/build_common.psm1 -ArgumentList $CXX_STANDARD, $CUDA_ARCH
 
 $PRESET = "cub-cpp$CXX_STANDARD"
 $CMAKE_OPTIONS = ""
diff --git a/ci/windows/build_cudax.ps1 b/ci/windows/build_cudax.ps1
index ca7bd578291..7b8cd0ff771 100644
--- a/ci/windows/build_cudax.ps1
+++ b/ci/windows/build_cudax.ps1
@@ -4,7 +4,11 @@ Param(
     [Alias("std")]
     [ValidateNotNullOrEmpty()]
     [ValidateSet(20)]
-    [int]$CXX_STANDARD = 20
+    [int]$CXX_STANDARD = 20,
+    [Parameter(Mandatory = $false)]
+    [ValidateNotNullOrEmpty()]
+    [Alias("arch")]
+    [int]$CUDA_ARCH = 0
 )
 
 $CURRENT_PATH = Split-Path $pwd -leaf
@@ -14,7 +18,7 @@ If($CURRENT_PATH -ne "ci") {
 }
 
 Remove-Module -Name build_common
-Import-Module $PSScriptRoot/build_common.psm1 -ArgumentList $CXX_STANDARD
+Import-Module $PSScriptRoot/build_common.psm1 -ArgumentList $CXX_STANDARD, $CUDA_ARCH
 
 $PRESET = "cudax-cpp$CXX_STANDARD"
 $CMAKE_OPTIONS = ""
diff --git a/ci/windows/build_libcudacxx.ps1 b/ci/windows/build_libcudacxx.ps1
index a57e2280de7..2f80619f76b 100644
--- a/ci/windows/build_libcudacxx.ps1
+++ b/ci/windows/build_libcudacxx.ps1
@@ -3,7 +3,11 @@ Param(
     [Alias("std")]
     [ValidateNotNullOrEmpty()]
     [ValidateSet(11, 14, 17, 20)]
-    [int]$CXX_STANDARD = 17
+    [int]$CXX_STANDARD = 17,
+    [Parameter(Mandatory = $false)]
+    [ValidateNotNullOrEmpty()]
+    [Alias("arch")]
+    [int]$CUDA_ARCH = 0
 )
 
 $ErrorActionPreference = "Stop"
@@ -14,7 +18,7 @@ If($CURRENT_PATH -ne "ci") {
     pushd "$PSScriptRoot/.."
 }
 
-Import-Module $PSScriptRoot/build_common.psm1 -ArgumentList $CXX_STANDARD, $GPU_ARCHS
+Import-Module $PSScriptRoot/build_common.psm1 -ArgumentList $CXX_STANDARD, $CUDA_ARCH
 
 $PRESET = "libcudacxx-cpp${CXX_STANDARD}"
 $CMAKE_OPTIONS = ""
diff --git a/ci/windows/build_thrust.ps1 b/ci/windows/build_thrust.ps1
index 186ed94eace..bda86859fd4 100644
--- a/ci/windows/build_thrust.ps1
+++ b/ci/windows/build_thrust.ps1
@@ -3,7 +3,11 @@ Param(
     [Alias("std")]
     [ValidateNotNullOrEmpty()]
     [ValidateSet(11, 14, 17, 20)]
-    [int]$CXX_STANDARD = 17
+    [int]$CXX_STANDARD = 17,
+    [Parameter(Mandatory = $false)]
+    [ValidateNotNullOrEmpty()]
+    [Alias("arch")]
+    [int]$CUDA_ARCH = 0
 )
 
 $ErrorActionPreference = "Stop"
@@ -14,7 +18,7 @@ If($CURRENT_PATH -ne "ci") {
     pushd "$PSScriptRoot/.."
 }
 
-Import-Module $PSScriptRoot/build_common.psm1 -ArgumentList $CXX_STANDARD
+Import-Module $PSScriptRoot/build_common.psm1 -ArgumentList $CXX_STANDARD, $CUDA_ARCH
 
 $PRESET = "thrust-cpp$CXX_STANDARD"
 $CMAKE_OPTIONS = ""
diff --git a/ci/windows/test_thrust.ps1 b/ci/windows/test_thrust.ps1
index 7c020714208..eabda06df5b 100644
--- a/ci/windows/test_thrust.ps1
+++ b/ci/windows/test_thrust.ps1
@@ -5,6 +5,10 @@ Param(
     [ValidateSet(11, 14, 17, 20)]
     [int]$CXX_STANDARD = 17,
     [Parameter(Mandatory = $false)]
+    [ValidateNotNullOrEmpty()]
+    [Alias("arch")]
+    [int]$CUDA_ARCH = 0,
+    [Parameter(Mandatory = $false)]
     [Alias("cpu-only")]
     [switch]$CPU_ONLY = $false
 )
@@ -24,11 +28,11 @@ If($CURRENT_PATH -ne "ci") {
 }
 
 # Execute the build script:
-$build_command = "$PSScriptRoot/build_thrust.ps1 -std $CXX_STANDARD"
+$build_command = "$PSScriptRoot/build_thrust.ps1 -std $CXX_STANDARD -arch $CUDA_ARCH"
 Write-Host "Executing: $build_command"
 Invoke-Expression $build_command
 
-Import-Module $PSScriptRoot/build_common.psm1 -ArgumentList $CXX_STANDARD
+Import-Module -Name "$PSScriptRoot/build_common.psm1" -ArgumentList $CXX_STANDARD, $CUDA_ARCH
 
 $PRESET = "thrust-cpu-cpp$CXX_STANDARD"
 
diff --git a/cub/test/CMakeLists.txt b/cub/test/CMakeLists.txt
index 5a093526edd..aaab1984e21 100644
--- a/cub/test/CMakeLists.txt
+++ b/cub/test/CMakeLists.txt
@@ -370,6 +370,15 @@ foreach (test_src IN LISTS test_srcs)
         set(launcher 0)
       endif()
 
+      # FIXME: There are a few remaining device algorithm tests that have not been ported to
+      # use Catch2 and lid variants. Mark these as `lid_0/1` so they'll run in the appropriate
+      # CI configs:
+      string(REGEX MATCH "^device_" is_device_test "${test_name}")
+      _cub_is_fail_test(is_fail_test "%{test_name}")
+      if (is_device_test AND NOT is_fail_test)
+        string(APPEND test_name ".lid_${launcher}")
+      endif()
+
       # Only one version of this test.
       cub_add_test(test_target ${test_name} "${test_src}" ${cub_target} ${launcher})
       cub_configure_cuda_target(${test_target} RDC ${CUB_FORCE_RDC})

From 0c17dbd005a934ffe2f83cf0b73a6a9aa5383852 Mon Sep 17 00:00:00 2001
From: Federico Busato <50413820+fbusato@users.noreply.github.com>
Date: Wed, 29 Jan 2025 17:28:19 -0800
Subject: [PATCH 11/33] Deprecate and replace `CUB_IS_INT128_ENABLED` (#3427)

Co-authored-by: Bernhard Manfred Gruber <bernhardmgruber@gmail.com>
---
 cub/cub/detail/fast_modulo_division.cuh       |  6 +++---
 .../device/dispatch/dispatch_histogram.cuh    | 12 +++++------
 .../tuning/tuning_run_length_encode.cuh       |  8 ++++----
 .../device/dispatch/tuning/tuning_scan.cuh    |  4 ++--
 .../dispatch/tuning/tuning_scan_by_key.cuh    | 20 +++++++++----------
 .../dispatch/tuning/tuning_select_if.cuh      | 16 +++++++--------
 cub/cub/util_ptx.cuh                          |  2 +-
 cub/cub/util_type.cuh                         | 13 ++----------
 .../catch2_test_device_for_each_in_extents.cu |  4 ++--
 cub/test/catch2_test_printing.cu              |  2 +-
 cub/test/internal/catch2_test_fast_div_mod.cu |  2 +-
 cub/test/test_util.h                          |  2 +-
 12 files changed, 41 insertions(+), 50 deletions(-)

diff --git a/cub/cub/detail/fast_modulo_division.cuh b/cub/cub/detail/fast_modulo_division.cuh
index 4a5f2048e32..09068d87be0 100644
--- a/cub/cub/detail/fast_modulo_division.cuh
+++ b/cub/cub/detail/fast_modulo_division.cuh
@@ -38,7 +38,7 @@
 #endif // no system header
 
 #include <cub/detail/type_traits.cuh> // implicit_prom_t
-#include <cub/util_type.cuh> // CUB_IS_INT128_ENABLED
+#include <cub/util_type.cuh> // _CCCL_HAS_INT128()
 
 #include <cuda/cmath> // cuda::std::ceil_div
 #include <cuda/std/bit> // std::has_single_bit
@@ -79,7 +79,7 @@ struct larger_unsigned_type<T, typename ::cuda::std::enable_if<(sizeof(T) == 4)>
   using type = ::cuda::std::uint64_t;
 };
 
-#if CUB_IS_INT128_ENABLED
+#if _CCCL_HAS_INT128()
 
 template <typename T>
 struct larger_unsigned_type<T, typename ::cuda::std::enable_if<(sizeof(T) == 8)>::type>
@@ -87,7 +87,7 @@ struct larger_unsigned_type<T, typename ::cuda::std::enable_if<(sizeof(T) == 8)>
   using type = __uint128_t;
 };
 
-#endif // CUB_IS_INT128_ENABLED
+#endif // _CCCL_HAS_INT128()
 
 template <typename T>
 using larger_unsigned_type_t = typename larger_unsigned_type<T>::type;
diff --git a/cub/cub/device/dispatch/dispatch_histogram.cuh b/cub/cub/device/dispatch/dispatch_histogram.cuh
index 2ac4e160220..2c2d0a2a9ca 100644
--- a/cub/cub/device/dispatch/dispatch_histogram.cuh
+++ b/cub/cub/device/dispatch/dispatch_histogram.cuh
@@ -646,27 +646,27 @@ public:
     using IntArithmeticT = ::cuda::std::_If< //
       sizeof(SampleT) + sizeof(CommonT) <= sizeof(uint32_t), //
       uint32_t, //
-#if CUB_IS_INT128_ENABLED
+#if _CCCL_HAS_INT128()
       ::cuda::std::_If< //
         (::cuda::std::is_same<CommonT, __int128_t>::value || //
          ::cuda::std::is_same<CommonT, __uint128_t>::value), //
         CommonT, //
         uint64_t> //
-#else // ^^^ CUB_IS_INT128_ENABLED ^^^ / vvv !CUB_IS_INT128_ENABLED vvv
+#else // ^^^ _CCCL_HAS_INT128() ^^^ / vvv !_CCCL_HAS_INT128() vvv
       uint64_t
-#endif // !CUB_IS_INT128_ENABLED
+#endif // !_CCCL_HAS_INT128()
       >;
 
     // Alias template that excludes __[u]int128 from the integral types
     template <typename T>
     using is_integral_excl_int128 =
-#if CUB_IS_INT128_ENABLED
+#if _CCCL_HAS_INT128()
       ::cuda::std::_If<::cuda::std::is_same<T, __int128_t>::value&& ::cuda::std::is_same<T, __uint128_t>::value,
                        ::cuda::std::false_type,
                        ::cuda::std::is_integral<T>>;
-#else // ^^^ CUB_IS_INT128_ENABLED ^^^ / vvv !CUB_IS_INT128_ENABLED vvv
+#else // ^^^ _CCCL_HAS_INT128() ^^^ / vvv !_CCCL_HAS_INT128() vvv
       ::cuda::std::is_integral<T>;
-#endif // !CUB_IS_INT128_ENABLED
+#endif // !_CCCL_HAS_INT128()
 
     union ScaleT
     {
diff --git a/cub/cub/device/dispatch/tuning/tuning_run_length_encode.cuh b/cub/cub/device/dispatch/tuning/tuning_run_length_encode.cuh
index d938209dcf2..12f07f3f366 100644
--- a/cub/cub/device/dispatch/tuning/tuning_run_length_encode.cuh
+++ b/cub/cub/device/dispatch/tuning/tuning_run_length_encode.cuh
@@ -156,7 +156,7 @@ struct sm80_tuning<LengthT, KeyT, primitive_length::yes, primitive_key::yes, len
   using delay_constructor                            = detail::no_delay_constructor_t<1075>;
 };
 
-#if CUB_IS_INT128_ENABLED
+#if _CCCL_HAS_INT128()
 template <class LengthT>
 struct sm80_tuning<LengthT, __int128_t, primitive_length::yes, primitive_key::no, length_size::_4, key_size::_16>
 {
@@ -216,7 +216,7 @@ struct sm90_tuning<LengthT, KeyT, primitive_length::yes, primitive_key::yes, len
   using delay_constructor                            = detail::no_delay_constructor_t<515>;
 };
 
-#if CUB_IS_INT128_ENABLED
+#if _CCCL_HAS_INT128()
 template <class LengthT>
 struct sm90_tuning<LengthT, __int128_t, primitive_length::yes, primitive_key::no, length_size::_4, key_size::_16>
 {
@@ -349,7 +349,7 @@ struct sm80_tuning<LengthT, KeyT, primitive_length::yes, primitive_key::yes, len
   using delay_constructor                            = detail::no_delay_constructor_t<1065>;
 };
 
-#if CUB_IS_INT128_ENABLED
+#if _CCCL_HAS_INT128()
 template <class LengthT>
 struct sm80_tuning<LengthT, __int128_t, primitive_length::yes, primitive_key::no, length_size::_4, key_size::_16>
 {
@@ -414,7 +414,7 @@ struct sm90_tuning<LengthT, KeyT, primitive_length::yes, primitive_key::yes, len
   using delay_constructor                            = detail::no_delay_constructor_t<840>;
 };
 
-#if CUB_IS_INT128_ENABLED
+#if _CCCL_HAS_INT128()
 template <class LengthT>
 struct sm90_tuning<LengthT, __int128_t, primitive_length::yes, primitive_key::no, length_size::_4, key_size::_16>
 {
diff --git a/cub/cub/device/dispatch/tuning/tuning_scan.cuh b/cub/cub/device/dispatch/tuning/tuning_scan.cuh
index 7b076507341..165a17cae52 100644
--- a/cub/cub/device/dispatch/tuning/tuning_scan.cuh
+++ b/cub/cub/device/dispatch/tuning/tuning_scan.cuh
@@ -175,7 +175,7 @@ struct sm80_tuning<double, primitive_op::yes, primitive_accum::yes, accum_size::
   static constexpr BlockStoreAlgorithm store_algorithm = BLOCK_STORE_WARP_TRANSPOSE;
 };
 
-#if CUB_IS_INT128_ENABLED
+#if _CCCL_HAS_INT128()
 template <>
 struct sm80_tuning<__int128_t, primitive_op::yes, primitive_accum::no, accum_size::_16>
 {
@@ -221,7 +221,7 @@ template <class T> struct sm90_tuning<T, primitive_op::yes, primitive_accum::yes
 template <> struct sm90_tuning<float,  primitive_op::yes, primitive_accum::yes, accum_size::_4> : sm90_tuning_vals<float,  128, 24, 688, 1140> {};
 template <> struct sm90_tuning<double, primitive_op::yes, primitive_accum::yes, accum_size::_8> : sm90_tuning_vals<double, 224, 24, 576, 1215> {};
 
-#if CUB_IS_INT128_ENABLED
+#if _CCCL_HAS_INT128()
 template <> struct sm90_tuning<__int128_t, primitive_op::yes, primitive_accum::no, accum_size::_16> : sm90_tuning_vals<__int128_t, 576, 21, 860, 630> {};
 template <>
 struct sm90_tuning<__uint128_t, primitive_op::yes, primitive_accum::no, accum_size::_16>
diff --git a/cub/cub/device/dispatch/tuning/tuning_scan_by_key.cuh b/cub/cub/device/dispatch/tuning/tuning_scan_by_key.cuh
index f8e29201eea..2bc31ef6697 100644
--- a/cub/cub/device/dispatch/tuning/tuning_scan_by_key.cuh
+++ b/cub/cub/device/dispatch/tuning/tuning_scan_by_key.cuh
@@ -172,7 +172,7 @@ struct sm80_tuning<KeyT, ValueT, primitive_op::yes, key_size::_1, val_size::_8,
   using delay_constructor                              = fixed_delay_constructor_t<124, 1040>;
 };
 
-#if CUB_IS_INT128_ENABLED
+#if _CCCL_HAS_INT128()
 template <class KeyT>
 struct sm80_tuning<KeyT, __int128_t, primitive_op::yes, key_size::_1, val_size::_16, primitive_accum::no>
 {
@@ -229,7 +229,7 @@ struct sm80_tuning<KeyT, ValueT, primitive_op::yes, key_size::_2, val_size::_8,
   using delay_constructor                              = fixed_delay_constructor_t<160, 695>;
 };
 
-#if CUB_IS_INT128_ENABLED
+#if _CCCL_HAS_INT128()
 template <class KeyT>
 struct sm80_tuning<KeyT, __int128_t, primitive_op::yes, key_size::_2, val_size::_16, primitive_accum::no>
 {
@@ -286,7 +286,7 @@ struct sm80_tuning<KeyT, ValueT, primitive_op::yes, key_size::_4, val_size::_8,
   using delay_constructor                              = fixed_delay_constructor_t<888, 635>;
 };
 
-#if CUB_IS_INT128_ENABLED
+#if _CCCL_HAS_INT128()
 template <class KeyT>
 struct sm80_tuning<KeyT, __int128_t, primitive_op::yes, key_size::_4, val_size::_16, primitive_accum::no>
 {
@@ -343,7 +343,7 @@ struct sm80_tuning<KeyT, ValueT, primitive_op::yes, key_size::_8, val_size::_8,
   using delay_constructor                              = no_delay_constructor_t<1160>;
 };
 
-#if CUB_IS_INT128_ENABLED
+#if _CCCL_HAS_INT128()
 template <class KeyT>
 struct sm80_tuning<KeyT, __int128_t, primitive_op::yes, key_size::_8, val_size::_16, primitive_accum::no>
 {
@@ -400,7 +400,7 @@ struct sm80_tuning<KeyT, ValueT, primitive_op::yes, key_size::_16, val_size::_8,
   using delay_constructor                              = no_delay_constructor_t<1030>;
 };
 
-#if CUB_IS_INT128_ENABLED
+#if _CCCL_HAS_INT128()
 template <class KeyT>
 struct sm80_tuning<KeyT, __int128_t, primitive_op::yes, key_size::_16, val_size::_16, primitive_accum::no>
 {
@@ -465,7 +465,7 @@ struct sm90_tuning<KeyT, ValueT, primitive_op::yes, key_size::_1, val_size::_8,
   using delay_constructor                              = fixed_delay_constructor_t<488, 1070>;
 };
 
-#if CUB_IS_INT128_ENABLED
+#if _CCCL_HAS_INT128()
 template <class KeyT>
 struct sm90_tuning<KeyT, __int128_t, primitive_op::yes, key_size::_1, val_size::_16, primitive_accum::no>
 {
@@ -522,7 +522,7 @@ struct sm90_tuning<KeyT, ValueT, primitive_op::yes, key_size::_2, val_size::_8,
   using delay_constructor                              = fixed_delay_constructor_t<352, 1170>;
 };
 
-#if CUB_IS_INT128_ENABLED
+#if _CCCL_HAS_INT128()
 template <class KeyT>
 struct sm90_tuning<KeyT, __int128_t, primitive_op::yes, key_size::_2, val_size::_16, primitive_accum::no>
 {
@@ -579,7 +579,7 @@ struct sm90_tuning<KeyT, ValueT, primitive_op::yes, key_size::_4, val_size::_8,
   using delay_constructor                              = fixed_delay_constructor_t<556, 1195>;
 };
 
-#if CUB_IS_INT128_ENABLED
+#if _CCCL_HAS_INT128()
 template <class KeyT>
 struct sm90_tuning<KeyT, __int128_t, primitive_op::yes, key_size::_4, val_size::_16, primitive_accum::no>
 {
@@ -636,7 +636,7 @@ struct sm90_tuning<KeyT, ValueT, primitive_op::yes, key_size::_8, val_size::_8,
   using delay_constructor                              = fixed_delay_constructor_t<600, 930>;
 };
 
-#if CUB_IS_INT128_ENABLED
+#if _CCCL_HAS_INT128()
 template <class KeyT>
 struct sm90_tuning<KeyT, __int128_t, primitive_op::yes, key_size::_8, val_size::_16, primitive_accum::no>
 {
@@ -693,7 +693,7 @@ struct sm90_tuning<KeyT, ValueT, primitive_op::yes, key_size::_16, val_size::_8,
   using delay_constructor                              = fixed_delay_constructor_t<320, 1200>;
 };
 
-#if CUB_IS_INT128_ENABLED
+#if _CCCL_HAS_INT128()
 template <class KeyT>
 struct sm90_tuning<KeyT, __int128_t, primitive_op::yes, key_size::_16, val_size::_16, primitive_accum::no>
 {
diff --git a/cub/cub/device/dispatch/tuning/tuning_select_if.cuh b/cub/cub/device/dispatch/tuning/tuning_select_if.cuh
index 10d22286068..c1b74b4ae09 100644
--- a/cub/cub/device/dispatch/tuning/tuning_select_if.cuh
+++ b/cub/cub/device/dispatch/tuning/tuning_select_if.cuh
@@ -121,7 +121,7 @@ struct sm80_tuning<Input, flagged::no, keep_rejects::no, offset_size::_4, primit
   using delay_constructor                            = detail::fixed_delay_constructor_t<832, 1165>;
 };
 
-#if CUB_IS_INT128_ENABLED
+#if _CCCL_HAS_INT128()
 template <>
 struct sm80_tuning<__int128_t, flagged::no, keep_rejects::no, offset_size::_4, primitive::no, input_size::_16>
 {
@@ -174,7 +174,7 @@ struct sm80_tuning<Input, flagged::yes, keep_rejects::no, offset_size::_4, primi
   using delay_constructor                            = detail::no_delay_constructor_t<1130>;
 };
 
-#if CUB_IS_INT128_ENABLED
+#if _CCCL_HAS_INT128()
 template <>
 struct sm80_tuning<__int128_t, flagged::yes, keep_rejects::no, offset_size::_4, primitive::no, input_size::_16>
 {
@@ -227,7 +227,7 @@ struct sm80_tuning<Input, flagged::no, keep_rejects::yes, offset_size::_4, primi
   using delay_constructor                            = detail::fixed_delay_constructor_t<68, 1160>;
 };
 
-#if CUB_IS_INT128_ENABLED
+#if _CCCL_HAS_INT128()
 template <>
 struct sm80_tuning<__int128_t, flagged::no, keep_rejects::yes, offset_size::_4, primitive::no, input_size::_16>
 {
@@ -280,7 +280,7 @@ struct sm80_tuning<Input, flagged::yes, keep_rejects::yes, offset_size::_4, prim
   using delay_constructor                            = detail::fixed_delay_constructor_t<884, 1130>;
 };
 
-#if CUB_IS_INT128_ENABLED
+#if _CCCL_HAS_INT128()
 template <>
 struct sm80_tuning<__int128_t, flagged::yes, keep_rejects::yes, offset_size::_4, primitive::no, input_size::_16>
 {
@@ -336,7 +336,7 @@ struct sm90_tuning<Input, flagged::no, keep_rejects::no, offset_size::_4, primit
   using delay_constructor                            = detail::fixed_delay_constructor_t<380, 1140>;
 };
 
-#if CUB_IS_INT128_ENABLED
+#if _CCCL_HAS_INT128()
 template <>
 struct sm90_tuning<__int128_t, flagged::no, keep_rejects::no, offset_size::_4, primitive::no, input_size::_16>
 {
@@ -389,7 +389,7 @@ struct sm90_tuning<Input, flagged::yes, keep_rejects::no, offset_size::_4, primi
   using delay_constructor                            = detail::fixed_delay_constructor_t<360, 1170>;
 };
 
-#if CUB_IS_INT128_ENABLED
+#if _CCCL_HAS_INT128()
 template <>
 struct sm90_tuning<__int128_t, flagged::yes, keep_rejects::no, offset_size::_4, primitive::no, input_size::_16>
 {
@@ -442,7 +442,7 @@ struct sm90_tuning<Input, flagged::no, keep_rejects::yes, offset_size::_4, primi
   using delay_constructor                            = detail::fixed_delay_constructor_t<512, 1075>;
 };
 
-#if CUB_IS_INT128_ENABLED
+#if _CCCL_HAS_INT128()
 template <>
 struct sm90_tuning<__int128_t, flagged::no, keep_rejects::yes, offset_size::_4, primitive::no, input_size::_16>
 {
@@ -495,7 +495,7 @@ struct sm90_tuning<Input, flagged::yes, keep_rejects::yes, offset_size::_4, prim
   using delay_constructor                            = detail::fixed_delay_constructor_t<532, 1180>;
 };
 
-#if CUB_IS_INT128_ENABLED
+#if _CCCL_HAS_INT128()
 template <>
 struct sm90_tuning<__int128_t, flagged::yes, keep_rejects::yes, offset_size::_4, primitive::no, input_size::_16>
 {
diff --git a/cub/cub/util_ptx.cuh b/cub/cub/util_ptx.cuh
index 99beeed313e..e6bb45c4a31 100644
--- a/cub/cub/util_ptx.cuh
+++ b/cub/cub/util_ptx.cuh
@@ -99,7 +99,7 @@ BFE(UnsignedBits source, unsigned int bit_start, unsigned int num_bits, Int2Type
   return (source >> bit_start) & MASK;
 }
 
-#  if CUB_IS_INT128_ENABLED
+#  if _CCCL_HAS_INT128()
 /**
  * Bitfield-extract for 128-bit types.
  */
diff --git a/cub/cub/util_type.cuh b/cub/cub/util_type.cuh
index 4d1db99a821..a89cd159309 100644
--- a/cub/cub/util_type.cuh
+++ b/cub/cub/util_type.cuh
@@ -76,17 +76,8 @@ _CCCL_DIAG_POP
 CUB_NAMESPACE_BEGIN
 
 #ifndef CUB_IS_INT128_ENABLED
-#  if defined(__CUDACC_RTC__)
-#    if defined(__CUDACC_RTC_INT128__)
-#      define CUB_IS_INT128_ENABLED 1
-#    endif // !defined(__CUDACC_RTC_INT128__)
-#  else // !defined(__CUDACC_RTC__)
-#    if _CCCL_CUDACC_AT_LEAST(11, 5)
-#      if _CCCL_COMPILER(GCC) || _CCCL_COMPILER(CLANG) || _CCCL_COMPILER(NVHPC)
-#        define CUB_IS_INT128_ENABLED 1
-#      endif // GCC || CLANG || NVHPC
-#    endif // _CCCL_CUDACC_AT_LEAST(11, 5)
-#  endif // !defined(__CUDACC_RTC__)
+// Deprecated [Since 2.8]
+#  define CUB_IS_INT128_ENABLED _CCCL_HAS_INT128()
 #endif // !defined(CUB_IS_INT128_ENABLED)
 
 /******************************************************************************
diff --git a/cub/test/catch2_test_device_for_each_in_extents.cu b/cub/test/catch2_test_device_for_each_in_extents.cu
index 3e5a6c6689a..313b9e58b38 100644
--- a/cub/test/catch2_test_device_for_each_in_extents.cu
+++ b/cub/test/catch2_test_device_for_each_in_extents.cu
@@ -107,7 +107,7 @@ using index_types =
                  uint16_t,
                  int32_t,
                  uint32_t
-#  if CUB_IS_INT128_ENABLED
+#  if _CCCL_HAS_INT128()
                  ,
                  int64_t,
                  uint64_t
@@ -120,7 +120,7 @@ using index_types_dynamic =
                  uint16_t,
                  int32_t,
                  uint32_t
-#  if CUB_IS_INT128_ENABLED
+#  if _CCCL_HAS_INT128()
                  ,
                  int64_t,
                  uint64_t
diff --git a/cub/test/catch2_test_printing.cu b/cub/test/catch2_test_printing.cu
index 6f93515114a..63b622f3554 100644
--- a/cub/test/catch2_test_printing.cu
+++ b/cub/test/catch2_test_printing.cu
@@ -11,7 +11,7 @@ std::string print(T val)
   return ss.str();
 }
 
-#if CUB_IS_INT128_ENABLED
+#if _CCCL_HAS_INT128()
 TEST_CASE("Test utils can print __int128", "[test][utils]")
 {
   REQUIRE(print(__int128_t{0}) == "0");
diff --git a/cub/test/internal/catch2_test_fast_div_mod.cu b/cub/test/internal/catch2_test_fast_div_mod.cu
index 8a1a3e96a27..ec3b5e20d68 100644
--- a/cub/test/internal/catch2_test_fast_div_mod.cu
+++ b/cub/test/internal/catch2_test_fast_div_mod.cu
@@ -42,7 +42,7 @@ using index_types =
                  uint16_t,
                  int32_t,
                  uint32_t
-#  if CUB_IS_INT128_ENABLED
+#  if _CCCL_HAS_INT128()
                  ,
                  int64_t,
                  uint64_t
diff --git a/cub/test/test_util.h b/cub/test/test_util.h
index 031298120dc..9a5fefcc69c 100644
--- a/cub/test/test_util.h
+++ b/cub/test/test_util.h
@@ -717,7 +717,7 @@ std::ostream& operator<<(std::ostream& os, const CUB_NS_QUALIFIER::KeyValuePair<
   return os;
 }
 
-#if CUB_IS_INT128_ENABLED
+#if _CCCL_HAS_INT128()
 inline std::ostream& operator<<(std::ostream& os, __uint128_t val)
 {
   constexpr int max_digits      = 40;

From c02e845e7f40dc748777638ce70e9893560e473c Mon Sep 17 00:00:00 2001
From: Elias Stehle <3958403+elstehle@users.noreply.github.com>
Date: Thu, 30 Jan 2025 07:39:35 +0100
Subject: [PATCH 12/33] Adds support for large num items to `DeviceMerge`
 (#3530)

* adds support for large num items

* re-enable vsmem tests

* rephrases test description
---
 cub/cub/device/device_merge.cuh      |  18 ++--
 cub/test/catch2_test_device_merge.cu | 129 +++++----------------------
 2 files changed, 33 insertions(+), 114 deletions(-)

diff --git a/cub/cub/device/device_merge.cuh b/cub/cub/device/device_merge.cuh
index 7135546a0e6..814bad75248 100644
--- a/cub/cub/device/device_merge.cuh
+++ b/cub/cub/device/device_merge.cuh
@@ -76,16 +76,19 @@ struct DeviceMerge
     void* d_temp_storage,
     std::size_t& temp_storage_bytes,
     KeyIteratorIn1 keys_in1,
-    int num_keys1,
+    ::cuda::std::int64_t num_keys1,
     KeyIteratorIn2 keys_in2,
-    int num_keys2,
+    ::cuda::std::int64_t num_keys2,
     KeyIteratorOut keys_out,
     CompareOp compare_op = {},
     cudaStream_t stream  = nullptr)
   {
     CUB_DETAIL_NVTX_RANGE_SCOPE_IF(d_temp_storage, "cub::DeviceMerge::MergeKeys");
+
+    using offset_t = ::cuda::std::int64_t;
+
     return detail::merge::
-      dispatch_t<KeyIteratorIn1, NullType*, KeyIteratorIn2, NullType*, KeyIteratorOut, NullType*, int, CompareOp>::
+      dispatch_t<KeyIteratorIn1, NullType*, KeyIteratorIn2, NullType*, KeyIteratorOut, NullType*, offset_t, CompareOp>::
         dispatch(
           d_temp_storage,
           temp_storage_bytes,
@@ -161,16 +164,19 @@ struct DeviceMerge
     std::size_t& temp_storage_bytes,
     KeyIteratorIn1 keys_in1,
     ValueIteratorIn1 values_in1,
-    int num_pairs1,
+    ::cuda::std::int64_t num_pairs1,
     KeyIteratorIn2 keys_in2,
     ValueIteratorIn2 values_in2,
-    int num_pairs2,
+    ::cuda::std::int64_t num_pairs2,
     KeyIteratorOut keys_out,
     ValueIteratorOut values_out,
     CompareOp compare_op = {},
     cudaStream_t stream  = nullptr)
   {
     CUB_DETAIL_NVTX_RANGE_SCOPE_IF(d_temp_storage, "cub::DeviceMerge::MergePairs");
+
+    using offset_t = ::cuda::std::int64_t;
+
     return detail::merge::dispatch_t<
       KeyIteratorIn1,
       ValueIteratorIn1,
@@ -178,7 +184,7 @@ struct DeviceMerge
       ValueIteratorIn2,
       KeyIteratorOut,
       ValueIteratorOut,
-      int,
+      offset_t,
       CompareOp>::dispatch(d_temp_storage,
                            temp_storage_bytes,
                            keys_in1,
diff --git a/cub/test/catch2_test_device_merge.cu b/cub/test/catch2_test_device_merge.cu
index ae0d3f84baa..4835f597710 100644
--- a/cub/test/catch2_test_device_merge.cu
+++ b/cub/test/catch2_test_device_merge.cu
@@ -20,103 +20,8 @@
 DECLARE_LAUNCH_WRAPPER(cub::DeviceMerge::MergePairs, merge_pairs);
 DECLARE_LAUNCH_WRAPPER(cub::DeviceMerge::MergeKeys, merge_keys);
 
-// TODO(bgruber): replace the following by the CUB device API directly, once we have figured out how to handle different
-// offset types
-namespace detail
-{
-template <typename KeyIteratorIn1,
-          typename KeyIteratorIn2,
-          typename KeyIteratorOut,
-          typename Offset,
-          typename CompareOp = ::cuda::std::less<>>
-CUB_RUNTIME_FUNCTION static cudaError_t merge_keys_custom_offset_type(
-  void* d_temp_storage,
-  std::size_t& temp_storage_bytes,
-  KeyIteratorIn1 keys_in1,
-  Offset num_keys1,
-  KeyIteratorIn2 keys_in2,
-  Offset num_keys2,
-  KeyIteratorOut keys_out,
-  CompareOp compare_op = {},
-  cudaStream_t stream  = 0)
-{
-  CUB_DETAIL_NVTX_RANGE_SCOPE_IF(d_temp_storage, "cub::DeviceMerge::MergeKeys");
-  return cub::detail::merge::dispatch_t<
-    KeyIteratorIn1,
-    cub::NullType*,
-    KeyIteratorIn2,
-    cub::NullType*,
-    KeyIteratorOut,
-    cub::NullType*,
-    Offset,
-    CompareOp>::dispatch(d_temp_storage,
-                         temp_storage_bytes,
-                         keys_in1,
-                         nullptr,
-                         num_keys1,
-                         keys_in2,
-                         nullptr,
-                         num_keys2,
-                         keys_out,
-                         nullptr,
-                         compare_op,
-                         stream);
-}
-
-template <typename KeyIteratorIn1,
-          typename ValueIteratorIn1,
-          typename KeyIteratorIn2,
-          typename ValueIteratorIn2,
-          typename KeyIteratorOut,
-          typename ValueIteratorOut,
-          typename Offset,
-          typename CompareOp = ::cuda::std::less<>>
-CUB_RUNTIME_FUNCTION static cudaError_t merge_pairs_custom_offset_type(
-  void* d_temp_storage,
-  std::size_t& temp_storage_bytes,
-  KeyIteratorIn1 keys_in1,
-  ValueIteratorIn1 values_in1,
-  Offset num_pairs1,
-  KeyIteratorIn2 keys_in2,
-  ValueIteratorIn2 values_in2,
-  Offset num_pairs2,
-  KeyIteratorOut keys_out,
-  ValueIteratorOut values_out,
-  CompareOp compare_op = {},
-  cudaStream_t stream  = 0)
-{
-  CUB_DETAIL_NVTX_RANGE_SCOPE_IF(d_temp_storage, "cub::DeviceMerge::MergePairs");
-  return cub::detail::merge::dispatch_t<
-    KeyIteratorIn1,
-    ValueIteratorIn1,
-    KeyIteratorIn2,
-    ValueIteratorIn2,
-    KeyIteratorOut,
-    ValueIteratorOut,
-    Offset,
-    CompareOp>::dispatch(d_temp_storage,
-                         temp_storage_bytes,
-                         keys_in1,
-                         values_in1,
-                         num_pairs1,
-                         keys_in2,
-                         values_in2,
-                         num_pairs2,
-                         keys_out,
-                         values_out,
-                         compare_op,
-                         stream);
-}
-} // namespace detail
-
-DECLARE_LAUNCH_WRAPPER(detail::merge_keys_custom_offset_type, merge_keys_custom_offset_type);
-DECLARE_LAUNCH_WRAPPER(detail::merge_pairs_custom_offset_type, merge_pairs_custom_offset_type);
-
 using types = c2h::type_list<std::uint8_t, std::int16_t, std::uint32_t, double>;
 
-// gevtushenko: there is no code path in CUB and Thrust that leads to unsigned offsets, so let's safe some compile time
-using offset_types = c2h::type_list<std::int32_t, std::int64_t>;
-
 template <typename Key,
           typename Offset,
           typename CompareOp = ::cuda::std::less<Key>,
@@ -223,11 +128,27 @@ C2H_TEST("DeviceMerge::MergeKeys large key types", "[merge][device]", c2h::type_
     });
 }
 
-C2H_TEST("DeviceMerge::MergeKeys offset types", "[merge][device]", offset_types)
+C2H_TEST("DeviceMerge::MergeKeys works for large number of items", "[merge][device]")
+
+try
+{
+  using key_t    = char;
+  using offset_t = int64_t;
+
+  // Clamp 64-bit offset type problem sizes to just slightly larger than 2^32 items
+  const auto num_items_int_max = static_cast<offset_t>(::cuda::std::numeric_limits<std::int32_t>::max());
+
+  // Generate the input sizes to test for
+  const offset_t num_items_lhs =
+    GENERATE_COPY(values({num_items_int_max + offset_t{1000000}, num_items_int_max - 1, offset_t{3}}));
+  const offset_t num_items_rhs =
+    GENERATE_COPY(values({num_items_int_max + offset_t{1000000}, num_items_int_max, offset_t{3}}));
+
+  test_keys<key_t, offset_t>(num_items_lhs, num_items_rhs, ::cuda::std::less<>{});
+}
+catch (const std::bad_alloc&)
 {
-  using key_t    = int;
-  using offset_t = c2h::get<0, TestType>;
-  test_keys<key_t, offset_t>(3623, 6346, ::cuda::std::less<>{}, merge_keys_custom_offset_type);
+  // allocation failure is not a test failure, so we can run tests on smaller GPUs
 }
 
 C2H_TEST("DeviceMerge::MergeKeys input sizes", "[merge][device]")
@@ -385,14 +306,6 @@ C2H_TEST("DeviceMerge::MergePairs value types", "[merge][device]", types)
   test_pairs<key_t, value_t, offset_t>();
 }
 
-C2H_TEST("DeviceMerge::MergePairs offset types", "[merge][device]", offset_types)
-{
-  using key_t    = int;
-  using value_t  = int;
-  using offset_t = c2h::get<0, TestType>;
-  test_pairs<key_t, value_t, offset_t>(3623, 6346, ::cuda::std::less<>{}, merge_pairs_custom_offset_type);
-}
-
 C2H_TEST("DeviceMerge::MergePairs input sizes", "[merge][device]")
 {
   using key_t      = int;
@@ -410,7 +323,7 @@ try
   using key_t     = char;
   using value_t   = char;
   const auto size = std::int64_t{1} << GENERATE(30, 31, 32, 33);
-  test_pairs<key_t, value_t>(size, size, ::cuda::std::less<>{}, merge_pairs_custom_offset_type);
+  test_pairs<key_t, value_t>(size, size, ::cuda::std::less<>{});
 }
 catch (const std::bad_alloc&)
 {

From a654bc6e0fec3937ddd597dc44adaec61a40701f Mon Sep 17 00:00:00 2001
From: Bernhard Manfred Gruber <bernhardmgruber@gmail.com>
Date: Thu, 30 Jan 2025 08:33:22 +0100
Subject: [PATCH 13/33] Support FP16 traits on CTK 12.0 (#3535)

* Support FP16 traits on CTK 12.0
* Only enable constexpr limits when supported
* Support float_eq on CTK < 12.2
---
 .../is_extended_floating_point.h              | 16 ++---
 libcudacxx/include/cuda/std/limits            | 58 ++++++++++++-------
 .../meta.unary.cat/is_floating_point.pass.cpp |  8 +--
 .../limits/is_specialized.pass.cpp            |  8 +--
 .../limits/numeric.limits.members/common.h    | 25 ++++++--
 .../const_data_members.pass.cpp               |  8 +--
 .../denorm_min.pass.cpp                       |  8 +--
 .../numeric.limits.members/digits.pass.cpp    |  8 +--
 .../numeric.limits.members/digits10.pass.cpp  |  8 +--
 .../numeric.limits.members/epsilon.pass.cpp   |  8 +--
 .../has_denorm.pass.cpp                       |  8 +--
 .../has_denorm_loss.pass.cpp                  |  8 +--
 .../has_infinity.pass.cpp                     |  8 +--
 .../has_quiet_NaN.pass.cpp                    |  8 +--
 .../has_signaling_NaN.pass.cpp                |  8 +--
 .../numeric.limits.members/infinity.pass.cpp  | 16 ++---
 .../is_bounded.pass.cpp                       |  8 +--
 .../numeric.limits.members/is_exact.pass.cpp  |  8 +--
 .../numeric.limits.members/is_iec559.pass.cpp |  8 +--
 .../is_integer.pass.cpp                       |  8 +--
 .../numeric.limits.members/is_modulo.pass.cpp |  8 +--
 .../numeric.limits.members/is_signed.pass.cpp |  8 +--
 .../numeric.limits.members/lowest.pass.cpp    |  8 +--
 .../numeric.limits.members/max.pass.cpp       |  8 +--
 .../max_digits10.pass.cpp                     |  8 +--
 .../max_exponent.pass.cpp                     |  8 +--
 .../max_exponent10.pass.cpp                   |  8 +--
 .../numeric.limits.members/min.pass.cpp       |  8 +--
 .../min_exponent.pass.cpp                     |  8 +--
 .../min_exponent10.pass.cpp                   |  8 +--
 .../numeric.limits.members/quiet_NaN.pass.cpp |  8 +--
 .../numeric.limits.members/radix.pass.cpp     |  8 +--
 .../round_error.pass.cpp                      |  8 +--
 .../round_style.pass.cpp                      |  8 +--
 .../signaling_NaN.pass.cpp                    |  8 +--
 .../tinyness_before.pass.cpp                  |  8 +--
 .../numeric.limits.members/traps.pass.cpp     |  8 +--
 37 files changed, 205 insertions(+), 174 deletions(-)

diff --git a/libcudacxx/include/cuda/std/__type_traits/is_extended_floating_point.h b/libcudacxx/include/cuda/std/__type_traits/is_extended_floating_point.h
index b9700a87066..040418f5fe7 100644
--- a/libcudacxx/include/cuda/std/__type_traits/is_extended_floating_point.h
+++ b/libcudacxx/include/cuda/std/__type_traits/is_extended_floating_point.h
@@ -22,16 +22,16 @@
 
 #include <cuda/std/__type_traits/integral_constant.h>
 
-#if defined(_LIBCUDACXX_HAS_NVFP16)
+#if defined(_CCCL_HAS_NVFP16)
 #  include <cuda_fp16.h>
-#endif // _LIBCUDACXX_HAS_NVFP16
+#endif // _CCCL_HAS_NVFP16
 
-#if defined(_LIBCUDACXX_HAS_NVBF16)
+#if defined(_CCCL_HAS_NVBF16)
 _CCCL_DIAG_PUSH
 _CCCL_DIAG_SUPPRESS_CLANG("-Wunused-function")
 #  include <cuda_bf16.h>
 _CCCL_DIAG_POP
-#endif // _LIBCUDACXX_HAS_NVBF16
+#endif // _CCCL_HAS_NVBF16
 
 #if _CCCL_HAS_NVFP8()
 #  include <cuda_fp8.h>
@@ -53,7 +53,7 @@ _CCCL_INLINE_VAR constexpr bool __is_extended_floating_point_v
 #  endif // !_CCCL_NO_INLINE_VARIABLES
 #endif // !_CCCL_NO_VARIABLE_TEMPLATES
 
-#if defined(_LIBCUDACXX_HAS_NVFP16)
+#if defined(_CCCL_HAS_NVFP16)
 template <>
 struct __is_extended_floating_point<__half> : true_type
 {};
@@ -62,9 +62,9 @@ struct __is_extended_floating_point<__half> : true_type
 template <>
 _CCCL_INLINE_VAR constexpr bool __is_extended_floating_point_v<__half> = true;
 #  endif // !_CCCL_NO_INLINE_VARIABLES
-#endif // _LIBCUDACXX_HAS_NVFP16
+#endif // _CCCL_HAS_NVFP16
 
-#if defined(_LIBCUDACXX_HAS_NVBF16)
+#if defined(_CCCL_HAS_NVBF16)
 template <>
 struct __is_extended_floating_point<__nv_bfloat16> : true_type
 {};
@@ -73,7 +73,7 @@ struct __is_extended_floating_point<__nv_bfloat16> : true_type
 template <>
 _CCCL_INLINE_VAR constexpr bool __is_extended_floating_point_v<__nv_bfloat16> = true;
 #  endif // !_CCCL_NO_INLINE_VARIABLES
-#endif // _LIBCUDACXX_HAS_NVBF16
+#endif // _CCCL_HAS_NVBF16
 
 #if _CCCL_HAS_NVFP8()
 template <>
diff --git a/libcudacxx/include/cuda/std/limits b/libcudacxx/include/cuda/std/limits
index 9d0cbc81108..29f4bf24ec3 100644
--- a/libcudacxx/include/cuda/std/limits
+++ b/libcudacxx/include/cuda/std/limits
@@ -608,7 +608,13 @@ public:
 #endif // !_LIBCUDACXX_HAS_NO_LONG_DOUBLE
 };
 
-#if defined(_LIBCUDACXX_HAS_NVFP16)
+#if defined(_CCCL_HAS_NVFP16)
+#  ifdef _LIBCUDACXX_HAS_NVFP16
+#    define _LIBCUDACXX_FP16_CONSTEXPR constexpr
+#  else //_LIBCUDACXX_HAS_NVFP16
+#    define _LIBCUDACXX_FP16_CONSTEXPR
+#  endif //_LIBCUDACXX_HAS_NVFP16
+
 template <>
 class __numeric_limits_impl<__half, __numeric_limits_type::__floating_point>
 {
@@ -621,15 +627,15 @@ public:
   static constexpr int digits       = 11;
   static constexpr int digits10     = 3;
   static constexpr int max_digits10 = 5;
-  _LIBCUDACXX_HIDE_FROM_ABI static constexpr type min() noexcept
+  _LIBCUDACXX_HIDE_FROM_ABI static _LIBCUDACXX_FP16_CONSTEXPR type min() noexcept
   {
     return type(__half_raw{0x0400u});
   }
-  _LIBCUDACXX_HIDE_FROM_ABI static constexpr type max() noexcept
+  _LIBCUDACXX_HIDE_FROM_ABI static _LIBCUDACXX_FP16_CONSTEXPR type max() noexcept
   {
     return type(__half_raw{0x7bffu});
   }
-  _LIBCUDACXX_HIDE_FROM_ABI static constexpr type lowest() noexcept
+  _LIBCUDACXX_HIDE_FROM_ABI static _LIBCUDACXX_FP16_CONSTEXPR type lowest() noexcept
   {
     return type(__half_raw{0xfbffu});
   }
@@ -637,11 +643,11 @@ public:
   static constexpr bool is_integer = false;
   static constexpr bool is_exact   = false;
   static constexpr int radix       = __FLT_RADIX__;
-  _LIBCUDACXX_HIDE_FROM_ABI static constexpr type epsilon() noexcept
+  _LIBCUDACXX_HIDE_FROM_ABI static _LIBCUDACXX_FP16_CONSTEXPR type epsilon() noexcept
   {
     return type(__half_raw{0x1400u});
   }
-  _LIBCUDACXX_HIDE_FROM_ABI static constexpr type round_error() noexcept
+  _LIBCUDACXX_HIDE_FROM_ABI static _LIBCUDACXX_FP16_CONSTEXPR type round_error() noexcept
   {
     return type(__half_raw{0x3800u});
   }
@@ -656,19 +662,19 @@ public:
   static constexpr bool has_signaling_NaN        = true;
   static constexpr float_denorm_style has_denorm = denorm_present;
   static constexpr bool has_denorm_loss          = false;
-  _LIBCUDACXX_HIDE_FROM_ABI static constexpr type infinity() noexcept
+  _LIBCUDACXX_HIDE_FROM_ABI static _LIBCUDACXX_FP16_CONSTEXPR type infinity() noexcept
   {
     return type(__half_raw{0x7c00u});
   }
-  _LIBCUDACXX_HIDE_FROM_ABI static constexpr type quiet_NaN() noexcept
+  _LIBCUDACXX_HIDE_FROM_ABI static _LIBCUDACXX_FP16_CONSTEXPR type quiet_NaN() noexcept
   {
     return type(__half_raw{0x7e00u});
   }
-  _LIBCUDACXX_HIDE_FROM_ABI static constexpr type signaling_NaN() noexcept
+  _LIBCUDACXX_HIDE_FROM_ABI static _LIBCUDACXX_FP16_CONSTEXPR type signaling_NaN() noexcept
   {
     return type(__half_raw{0x7d00u});
   }
-  _LIBCUDACXX_HIDE_FROM_ABI static constexpr type denorm_min() noexcept
+  _LIBCUDACXX_HIDE_FROM_ABI static _LIBCUDACXX_FP16_CONSTEXPR type denorm_min() noexcept
   {
     return type(__half_raw{0x0001u});
   }
@@ -681,9 +687,16 @@ public:
   static constexpr bool tinyness_before          = false;
   static constexpr float_round_style round_style = round_to_nearest;
 };
-#endif // _LIBCUDACXX_HAS_NVFP16
+#  undef _LIBCUDACXX_FP16_CONSTEXPR
+#endif // _CCCL_HAS_NVFP16
+
+#if defined(_CCCL_HAS_NVBF16)
+#  ifdef _LIBCUDACXX_HAS_NVBF16
+#    define _LIBCUDACXX_BF16_CONSTEXPR constexpr
+#  else //_LIBCUDACXX_HAS_NVBF16
+#    define _LIBCUDACXX_BF16_CONSTEXPR
+#  endif //_LIBCUDACXX_HAS_NVBF16
 
-#if defined(_LIBCUDACXX_HAS_NVBF16)
 template <>
 class __numeric_limits_impl<__nv_bfloat16, __numeric_limits_type::__floating_point>
 {
@@ -696,15 +709,15 @@ public:
   static constexpr int digits       = 8;
   static constexpr int digits10     = 2;
   static constexpr int max_digits10 = 4;
-  _LIBCUDACXX_HIDE_FROM_ABI static constexpr type min() noexcept
+  _LIBCUDACXX_HIDE_FROM_ABI static _LIBCUDACXX_BF16_CONSTEXPR type min() noexcept
   {
     return type(__nv_bfloat16_raw{0x0080u});
   }
-  _LIBCUDACXX_HIDE_FROM_ABI static constexpr type max() noexcept
+  _LIBCUDACXX_HIDE_FROM_ABI static _LIBCUDACXX_BF16_CONSTEXPR type max() noexcept
   {
     return type(__nv_bfloat16_raw{0x7f7fu});
   }
-  _LIBCUDACXX_HIDE_FROM_ABI static constexpr type lowest() noexcept
+  _LIBCUDACXX_HIDE_FROM_ABI static _LIBCUDACXX_BF16_CONSTEXPR type lowest() noexcept
   {
     return type(__nv_bfloat16_raw{0xff7fu});
   }
@@ -712,11 +725,11 @@ public:
   static constexpr bool is_integer = false;
   static constexpr bool is_exact   = false;
   static constexpr int radix       = __FLT_RADIX__;
-  _LIBCUDACXX_HIDE_FROM_ABI static constexpr type epsilon() noexcept
+  _LIBCUDACXX_HIDE_FROM_ABI static _LIBCUDACXX_BF16_CONSTEXPR type epsilon() noexcept
   {
     return type(__nv_bfloat16_raw{0x3c00u});
   }
-  _LIBCUDACXX_HIDE_FROM_ABI static constexpr type round_error() noexcept
+  _LIBCUDACXX_HIDE_FROM_ABI static _LIBCUDACXX_BF16_CONSTEXPR type round_error() noexcept
   {
     return type(__nv_bfloat16_raw{0x3f00u});
   }
@@ -731,19 +744,19 @@ public:
   static constexpr bool has_signaling_NaN        = true;
   static constexpr float_denorm_style has_denorm = denorm_present;
   static constexpr bool has_denorm_loss          = false;
-  _LIBCUDACXX_HIDE_FROM_ABI static constexpr type infinity() noexcept
+  _LIBCUDACXX_HIDE_FROM_ABI static _LIBCUDACXX_BF16_CONSTEXPR type infinity() noexcept
   {
     return type(__nv_bfloat16_raw{0x7f80u});
   }
-  _LIBCUDACXX_HIDE_FROM_ABI static constexpr type quiet_NaN() noexcept
+  _LIBCUDACXX_HIDE_FROM_ABI static _LIBCUDACXX_BF16_CONSTEXPR type quiet_NaN() noexcept
   {
     return type(__nv_bfloat16_raw{0x7fc0u});
   }
-  _LIBCUDACXX_HIDE_FROM_ABI static constexpr type signaling_NaN() noexcept
+  _LIBCUDACXX_HIDE_FROM_ABI static _LIBCUDACXX_BF16_CONSTEXPR type signaling_NaN() noexcept
   {
     return type(__nv_bfloat16_raw{0x7fa0u});
   }
-  _LIBCUDACXX_HIDE_FROM_ABI static constexpr type denorm_min() noexcept
+  _LIBCUDACXX_HIDE_FROM_ABI static _LIBCUDACXX_BF16_CONSTEXPR type denorm_min() noexcept
   {
     return type(__nv_bfloat16_raw{0x0001u});
   }
@@ -756,7 +769,8 @@ public:
   static constexpr bool tinyness_before          = false;
   static constexpr float_round_style round_style = round_to_nearest;
 };
-#endif // _LIBCUDACXX_HAS_NVBF16
+#  undef _LIBCUDACXX_BF16_CONSTEXPR
+#endif // _CCCL_HAS_NVBF16
 
 #if _CCCL_HAS_NVFP8()
 #  if defined(_CCCL_BUILTIN_BIT_CAST) || _CCCL_STD_VER >= 2014
diff --git a/libcudacxx/test/libcudacxx/libcxx/utilities/meta/meta.unary/meta.unary.cat/is_floating_point.pass.cpp b/libcudacxx/test/libcudacxx/libcxx/utilities/meta/meta.unary/meta.unary.cat/is_floating_point.pass.cpp
index b0b7a3f3b69..5a04070c598 100644
--- a/libcudacxx/test/libcudacxx/libcxx/utilities/meta/meta.unary/meta.unary.cat/is_floating_point.pass.cpp
+++ b/libcudacxx/test/libcudacxx/libcxx/utilities/meta/meta.unary/meta.unary.cat/is_floating_point.pass.cpp
@@ -80,12 +80,12 @@ int main(int, char**)
   test_is_floating_point<float>();
   test_is_floating_point<double>();
   test_is_floating_point<long double>();
-#ifdef _LIBCUDACXX_HAS_NVFP16
+#ifdef _CCCL_HAS_NVFP16
   test_is_floating_point<__half>();
-#endif // _LIBCUDACXX_HAS_NVFP16
-#ifdef _LIBCUDACXX_HAS_NVBF16
+#endif // _CCCL_HAS_NVFP16
+#ifdef _CCCL_HAS_NVBF16
   test_is_floating_point<__nv_bfloat16>();
-#endif // _LIBCUDACXX_HAS_NVBF16
+#endif // _CCCL_HAS_NVBF16
 #if _CCCL_HAS_NVFP8()
   test_is_floating_point<__nv_fp8_e4m3>();
   test_is_floating_point<__nv_fp8_e5m2>();
diff --git a/libcudacxx/test/libcudacxx/std/language.support/support.limits/limits/is_specialized.pass.cpp b/libcudacxx/test/libcudacxx/std/language.support/support.limits/limits/is_specialized.pass.cpp
index 7113c0e2772..adb30091033 100644
--- a/libcudacxx/test/libcudacxx/std/language.support/support.limits/limits/is_specialized.pass.cpp
+++ b/libcudacxx/test/libcudacxx/std/language.support/support.limits/limits/is_specialized.pass.cpp
@@ -68,12 +68,12 @@ int main(int, char**)
 #ifndef _LIBCUDACXX_HAS_NO_LONG_DOUBLE
   test<long double>();
 #endif
-#if defined(_LIBCUDACXX_HAS_NVFP16)
+#if defined(_CCCL_HAS_NVFP16)
   test<__half>();
-#endif // _LIBCUDACXX_HAS_NVFP16
-#if defined(_LIBCUDACXX_HAS_NVBF16)
+#endif // _CCCL_HAS_NVFP16
+#if defined(_CCCL_HAS_NVBF16)
   test<__nv_bfloat16>();
-#endif // _LIBCUDACXX_HAS_NVBF16
+#endif // _CCCL_HAS_NVBF16
 
   static_assert(!cuda::std::numeric_limits<cuda::std::complex<double>>::is_specialized,
                 "!cuda::std::numeric_limits<cuda::std::complex<double> >::is_specialized");
diff --git a/libcudacxx/test/libcudacxx/std/language.support/support.limits/limits/numeric.limits.members/common.h b/libcudacxx/test/libcudacxx/std/language.support/support.limits/limits/numeric.limits.members/common.h
index 8400071611c..7d15f2ba6b6 100644
--- a/libcudacxx/test/libcudacxx/std/language.support/support.limits/limits/numeric.limits.members/common.h
+++ b/libcudacxx/test/libcudacxx/std/language.support/support.limits/limits/numeric.limits.members/common.h
@@ -17,6 +17,7 @@
 #define __CUDA_NO_BFLOAT16_CONVERSIONS__ 1
 #define __CUDA_NO_BFLOAT16_OPERATORS__   1
 
+#include <cuda/std/__bit/bit_cast.h>
 #include <cuda/std/limits>
 
 template <class T>
@@ -42,27 +43,43 @@ __host__ __device__ inline __nv_fp8_e5m2 make_fp8_e5m2(double x, __nv_saturation
 
 __host__ __device__ inline bool float_eq(__nv_fp8_e4m3 x, __nv_fp8_e4m3 y)
 {
+#  if _CCCL_CUDACC_AT_LEAST(12, 2)
   return float_eq(__half{__nv_cvt_fp8_to_halfraw(x.__x, __NV_E4M3)}, __half{__nv_cvt_fp8_to_halfraw(y.__x, __NV_E4M3)});
+#  else
+  return ::cuda::std::bit_cast<unsigned char>(x) == ::cuda::std::bit_cast<unsigned char>(y);
+#  endif
 }
 
 __host__ __device__ inline bool float_eq(__nv_fp8_e5m2 x, __nv_fp8_e5m2 y)
 {
+#  if _CCCL_CUDACC_AT_LEAST(12, 2)
   return float_eq(__half{__nv_cvt_fp8_to_halfraw(x.__x, __NV_E5M2)}, __half{__nv_cvt_fp8_to_halfraw(y.__x, __NV_E5M2)});
+#  else
+  return ::cuda::std::bit_cast<unsigned char>(x) == ::cuda::std::bit_cast<unsigned char>(y);
+#  endif
 }
 #endif // _CCCL_HAS_NVFP8
 
-#if defined(_LIBCUDACXX_HAS_NVFP16)
+#if defined(_CCCL_HAS_NVFP16)
 __host__ __device__ inline bool float_eq(__half x, __half y)
 {
+#  if _CCCL_CUDACC_AT_LEAST(12, 2)
   return __heq(x, y);
+#  else
+  return __half2float(x) == __half2float(y);
+#  endif
 }
-#endif // _LIBCUDACXX_HAS_NVFP16
+#endif // _CCCL_HAS_NVFP16
 
-#if defined(_LIBCUDACXX_HAS_NVBF16)
+#if defined(_CCCL_HAS_NVBF16)
 __host__ __device__ inline bool float_eq(__nv_bfloat16 x, __nv_bfloat16 y)
 {
+#  if _CCCL_CUDACC_AT_LEAST(12, 2)
   return __heq(x, y);
+#  else
+  return __bfloat162float(x) == __bfloat162float(y);
+#  endif
 }
-#endif // _LIBCUDACXX_HAS_NVBF16
+#endif // _CCCL_HAS_NVBF16
 
 #endif // NUMERIC_LIMITS_MEMBERS_COMMON_H
diff --git a/libcudacxx/test/libcudacxx/std/language.support/support.limits/limits/numeric.limits.members/const_data_members.pass.cpp b/libcudacxx/test/libcudacxx/std/language.support/support.limits/limits/numeric.limits.members/const_data_members.pass.cpp
index b095d63afcd..093b5d331be 100644
--- a/libcudacxx/test/libcudacxx/std/language.support/support.limits/limits/numeric.limits.members/const_data_members.pass.cpp
+++ b/libcudacxx/test/libcudacxx/std/language.support/support.limits/limits/numeric.limits.members/const_data_members.pass.cpp
@@ -110,12 +110,12 @@ int main(int, char**)
 #ifndef _LIBCUDACXX_HAS_NO_LONG_DOUBLE
   test_type<long double>();
 #endif // _LIBCUDACXX_HAS_NO_LONG_DOUBLE
-#if defined(_LIBCUDACXX_HAS_NVFP16)
+#if defined(_CCCL_HAS_NVFP16)
   test_type<__half>();
-#endif // _LIBCUDACXX_HAS_NVFP16
-#if defined(_LIBCUDACXX_HAS_NVBF16)
+#endif // _CCCL_HAS_NVFP16
+#if defined(_CCCL_HAS_NVBF16)
   test_type<__nv_bfloat16>();
-#endif // _LIBCUDACXX_HAS_NVBF16
+#endif // _CCCL_HAS_NVBF16
 #if _CCCL_HAS_NVFP8()
   test_type<__nv_fp8_e4m3>();
   test_type<__nv_fp8_e5m2>();
diff --git a/libcudacxx/test/libcudacxx/std/language.support/support.limits/limits/numeric.limits.members/denorm_min.pass.cpp b/libcudacxx/test/libcudacxx/std/language.support/support.limits/limits/numeric.limits.members/denorm_min.pass.cpp
index 475f41a3388..9ea232eaad6 100644
--- a/libcudacxx/test/libcudacxx/std/language.support/support.limits/limits/numeric.limits.members/denorm_min.pass.cpp
+++ b/libcudacxx/test/libcudacxx/std/language.support/support.limits/limits/numeric.limits.members/denorm_min.pass.cpp
@@ -66,12 +66,12 @@ int main(int, char**)
   test<long double>(LDBL_TRUE_MIN);
 #  endif
 #endif
-#if defined(_LIBCUDACXX_HAS_NVFP16)
+#if defined(_CCCL_HAS_NVFP16)
   test<__half>(__double2half(5.9604644775390625e-08));
-#endif // _LIBCUDACXX_HAS_NVFP16
-#if defined(_LIBCUDACXX_HAS_NVBF16)
+#endif // _CCCL_HAS_NVFP16
+#if defined(_CCCL_HAS_NVBF16)
   test<__nv_bfloat16>(__double2bfloat16(9.18354961579912115600575419705e-41));
-#endif // _LIBCUDACXX_HAS_NVBF16
+#endif // _CCCL_HAS_NVBF16
 #if _CCCL_HAS_NVFP8()
   test<__nv_fp8_e4m3>(make_fp8_e4m3(0.001953125));
   test<__nv_fp8_e5m2>(make_fp8_e5m2(0.0000152587890625));
diff --git a/libcudacxx/test/libcudacxx/std/language.support/support.limits/limits/numeric.limits.members/digits.pass.cpp b/libcudacxx/test/libcudacxx/std/language.support/support.limits/limits/numeric.limits.members/digits.pass.cpp
index 0d3c910b672..01f6b05543b 100644
--- a/libcudacxx/test/libcudacxx/std/language.support/support.limits/limits/numeric.limits.members/digits.pass.cpp
+++ b/libcudacxx/test/libcudacxx/std/language.support/support.limits/limits/numeric.limits.members/digits.pass.cpp
@@ -55,12 +55,12 @@ int main(int, char**)
 #ifndef _LIBCUDACXX_HAS_NO_LONG_DOUBLE
   test<long double, LDBL_MANT_DIG>();
 #endif
-#if defined(_LIBCUDACXX_HAS_NVFP16)
+#if defined(_CCCL_HAS_NVFP16)
   test<__half, 11>();
-#endif // _LIBCUDACXX_HAS_NVFP16
-#if defined(_LIBCUDACXX_HAS_NVBF16)
+#endif // _CCCL_HAS_NVFP16
+#if defined(_CCCL_HAS_NVBF16)
   test<__nv_bfloat16, 8>();
-#endif // _LIBCUDACXX_HAS_NVBF16
+#endif // _CCCL_HAS_NVBF16
 #if _CCCL_HAS_NVFP8()
   test<__nv_fp8_e4m3, 3>();
   test<__nv_fp8_e5m2, 2>();
diff --git a/libcudacxx/test/libcudacxx/std/language.support/support.limits/limits/numeric.limits.members/digits10.pass.cpp b/libcudacxx/test/libcudacxx/std/language.support/support.limits/limits/numeric.limits.members/digits10.pass.cpp
index bd66aeecfeb..24c53725738 100644
--- a/libcudacxx/test/libcudacxx/std/language.support/support.limits/limits/numeric.limits.members/digits10.pass.cpp
+++ b/libcudacxx/test/libcudacxx/std/language.support/support.limits/limits/numeric.limits.members/digits10.pass.cpp
@@ -74,12 +74,12 @@ int main(int, char**)
 #ifndef _LIBCUDACXX_HAS_NO_LONG_DOUBLE
   test<long double>();
 #endif
-#if defined(_LIBCUDACXX_HAS_NVFP16)
+#if defined(_CCCL_HAS_NVFP16)
   test<__half>();
-#endif // _LIBCUDACXX_HAS_NVFP16
-#if defined(_LIBCUDACXX_HAS_NVBF16)
+#endif // _CCCL_HAS_NVFP16
+#if defined(_CCCL_HAS_NVBF16)
   test<__nv_bfloat16>();
-#endif // _LIBCUDACXX_HAS_NVBF16
+#endif // _CCCL_HAS_NVBF16
 #if _CCCL_HAS_NVFP8()
   test<__nv_fp8_e4m3>();
   test<__nv_fp8_e5m2>();
diff --git a/libcudacxx/test/libcudacxx/std/language.support/support.limits/limits/numeric.limits.members/epsilon.pass.cpp b/libcudacxx/test/libcudacxx/std/language.support/support.limits/limits/numeric.limits.members/epsilon.pass.cpp
index 15366bdf308..bb65847df33 100644
--- a/libcudacxx/test/libcudacxx/std/language.support/support.limits/limits/numeric.limits.members/epsilon.pass.cpp
+++ b/libcudacxx/test/libcudacxx/std/language.support/support.limits/limits/numeric.limits.members/epsilon.pass.cpp
@@ -57,12 +57,12 @@ int main(int, char**)
 #ifndef _LIBCUDACXX_HAS_NO_LONG_DOUBLE
   test<long double>(LDBL_EPSILON);
 #endif
-#if defined(_LIBCUDACXX_HAS_NVFP16)
+#if defined(_CCCL_HAS_NVFP16)
   test<__half>(__double2half(0.0009765625));
-#endif // _LIBCUDACXX_HAS_NVFP16
-#if defined(_LIBCUDACXX_HAS_NVBF16)
+#endif // _CCCL_HAS_NVFP16
+#if defined(_CCCL_HAS_NVBF16)
   test<__nv_bfloat16>(__double2bfloat16(0.0078125));
-#endif // _LIBCUDACXX_HAS_NVBF16
+#endif // _CCCL_HAS_NVBF16
 #if _CCCL_HAS_NVFP8()
   test<__nv_fp8_e4m3>(make_fp8_e4m3(0.125));
   test<__nv_fp8_e5m2>(make_fp8_e5m2(0.25));
diff --git a/libcudacxx/test/libcudacxx/std/language.support/support.limits/limits/numeric.limits.members/has_denorm.pass.cpp b/libcudacxx/test/libcudacxx/std/language.support/support.limits/limits/numeric.limits.members/has_denorm.pass.cpp
index 8fa506b93ce..8d9881580bf 100644
--- a/libcudacxx/test/libcudacxx/std/language.support/support.limits/limits/numeric.limits.members/has_denorm.pass.cpp
+++ b/libcudacxx/test/libcudacxx/std/language.support/support.limits/limits/numeric.limits.members/has_denorm.pass.cpp
@@ -54,12 +54,12 @@ int main(int, char**)
 #ifndef _LIBCUDACXX_HAS_NO_LONG_DOUBLE
   test<long double, cuda::std::denorm_present>();
 #endif
-#if defined(_LIBCUDACXX_HAS_NVFP16)
+#if defined(_CCCL_HAS_NVFP16)
   test<__half, cuda::std::denorm_present>();
-#endif // _LIBCUDACXX_HAS_NVFP16
-#if defined(_LIBCUDACXX_HAS_NVBF16)
+#endif // _CCCL_HAS_NVFP16
+#if defined(_CCCL_HAS_NVBF16)
   test<__nv_bfloat16, cuda::std::denorm_present>();
-#endif // _LIBCUDACXX_HAS_NVBF16
+#endif // _CCCL_HAS_NVBF16
 #if _CCCL_HAS_NVFP8()
   test<__nv_fp8_e4m3, cuda::std::denorm_present>();
   test<__nv_fp8_e5m2, cuda::std::denorm_present>();
diff --git a/libcudacxx/test/libcudacxx/std/language.support/support.limits/limits/numeric.limits.members/has_denorm_loss.pass.cpp b/libcudacxx/test/libcudacxx/std/language.support/support.limits/limits/numeric.limits.members/has_denorm_loss.pass.cpp
index 3b7722acd8b..5a046a9b339 100644
--- a/libcudacxx/test/libcudacxx/std/language.support/support.limits/limits/numeric.limits.members/has_denorm_loss.pass.cpp
+++ b/libcudacxx/test/libcudacxx/std/language.support/support.limits/limits/numeric.limits.members/has_denorm_loss.pass.cpp
@@ -54,12 +54,12 @@ int main(int, char**)
 #ifndef _LIBCUDACXX_HAS_NO_LONG_DOUBLE
   test<long double, false>();
 #endif
-#if defined(_LIBCUDACXX_HAS_NVFP16)
+#if defined(_CCCL_HAS_NVFP16)
   test<__half, false>();
-#endif // _LIBCUDACXX_HAS_NVFP16
-#if defined(_LIBCUDACXX_HAS_NVBF16)
+#endif // _CCCL_HAS_NVFP16
+#if defined(_CCCL_HAS_NVBF16)
   test<__nv_bfloat16, false>();
-#endif // _LIBCUDACXX_HAS_NVBF16
+#endif // _CCCL_HAS_NVBF16
 #if _CCCL_HAS_NVFP8()
   test<__nv_fp8_e4m3, false>();
   test<__nv_fp8_e5m2, false>();
diff --git a/libcudacxx/test/libcudacxx/std/language.support/support.limits/limits/numeric.limits.members/has_infinity.pass.cpp b/libcudacxx/test/libcudacxx/std/language.support/support.limits/limits/numeric.limits.members/has_infinity.pass.cpp
index ebddcb4421e..768e53d1c88 100644
--- a/libcudacxx/test/libcudacxx/std/language.support/support.limits/limits/numeric.limits.members/has_infinity.pass.cpp
+++ b/libcudacxx/test/libcudacxx/std/language.support/support.limits/limits/numeric.limits.members/has_infinity.pass.cpp
@@ -54,12 +54,12 @@ int main(int, char**)
 #ifndef _LIBCUDACXX_HAS_NO_LONG_DOUBLE
   test<long double, true>();
 #endif
-#if defined(_LIBCUDACXX_HAS_NVFP16)
+#if defined(_CCCL_HAS_NVFP16)
   test<__half, true>();
-#endif // _LIBCUDACXX_HAS_NVFP16
-#if defined(_LIBCUDACXX_HAS_NVBF16)
+#endif // _CCCL_HAS_NVFP16
+#if defined(_CCCL_HAS_NVBF16)
   test<__nv_bfloat16, true>();
-#endif // _LIBCUDACXX_HAS_NVBF16
+#endif // _CCCL_HAS_NVBF16
 #if _CCCL_HAS_NVFP8()
   test<__nv_fp8_e4m3, false>();
   test<__nv_fp8_e5m2, true>();
diff --git a/libcudacxx/test/libcudacxx/std/language.support/support.limits/limits/numeric.limits.members/has_quiet_NaN.pass.cpp b/libcudacxx/test/libcudacxx/std/language.support/support.limits/limits/numeric.limits.members/has_quiet_NaN.pass.cpp
index 908f2d7fa4a..4c3e11a9b05 100644
--- a/libcudacxx/test/libcudacxx/std/language.support/support.limits/limits/numeric.limits.members/has_quiet_NaN.pass.cpp
+++ b/libcudacxx/test/libcudacxx/std/language.support/support.limits/limits/numeric.limits.members/has_quiet_NaN.pass.cpp
@@ -54,12 +54,12 @@ int main(int, char**)
 #ifndef _LIBCUDACXX_HAS_NO_LONG_DOUBLE
   test<long double, true>();
 #endif
-#if defined(_LIBCUDACXX_HAS_NVFP16)
+#if defined(_CCCL_HAS_NVFP16)
   test<__half, true>();
-#endif // _LIBCUDACXX_HAS_NVFP16
-#if defined(_LIBCUDACXX_HAS_NVBF16)
+#endif // _CCCL_HAS_NVFP16
+#if defined(_CCCL_HAS_NVBF16)
   test<__nv_bfloat16, true>();
-#endif // _LIBCUDACXX_HAS_NVBF16
+#endif // _CCCL_HAS_NVBF16
 #if _CCCL_HAS_NVFP8()
   test<__nv_fp8_e4m3, true>();
   test<__nv_fp8_e5m2, true>();
diff --git a/libcudacxx/test/libcudacxx/std/language.support/support.limits/limits/numeric.limits.members/has_signaling_NaN.pass.cpp b/libcudacxx/test/libcudacxx/std/language.support/support.limits/limits/numeric.limits.members/has_signaling_NaN.pass.cpp
index 62d81c8a524..1b80d1869e6 100644
--- a/libcudacxx/test/libcudacxx/std/language.support/support.limits/limits/numeric.limits.members/has_signaling_NaN.pass.cpp
+++ b/libcudacxx/test/libcudacxx/std/language.support/support.limits/limits/numeric.limits.members/has_signaling_NaN.pass.cpp
@@ -54,12 +54,12 @@ int main(int, char**)
 #ifndef _LIBCUDACXX_HAS_NO_LONG_DOUBLE
   test<long double, true>();
 #endif
-#if defined(_LIBCUDACXX_HAS_NVFP16)
+#if defined(_CCCL_HAS_NVFP16)
   test<__half, true>();
-#endif // _LIBCUDACXX_HAS_NVFP16
-#if defined(_LIBCUDACXX_HAS_NVBF16)
+#endif // _CCCL_HAS_NVFP16
+#if defined(_CCCL_HAS_NVBF16)
   test<__nv_bfloat16, true>();
-#endif // _LIBCUDACXX_HAS_NVBF16
+#endif // _CCCL_HAS_NVBF16
 #if _CCCL_HAS_NVFP8()
   test<__nv_fp8_e4m3, false>();
   test<__nv_fp8_e5m2, true>();
diff --git a/libcudacxx/test/libcudacxx/std/language.support/support.limits/limits/numeric.limits.members/infinity.pass.cpp b/libcudacxx/test/libcudacxx/std/language.support/support.limits/limits/numeric.limits.members/infinity.pass.cpp
index 627105a4a8c..8dd611556c5 100644
--- a/libcudacxx/test/libcudacxx/std/language.support/support.limits/limits/numeric.limits.members/infinity.pass.cpp
+++ b/libcudacxx/test/libcudacxx/std/language.support/support.limits/limits/numeric.limits.members/infinity.pass.cpp
@@ -64,12 +64,12 @@ int main(int, char**)
 #  ifndef _LIBCUDACXX_HAS_NO_LONG_DOUBLE
   test<long double>(1. / 0.);
 #  endif
-#  if defined(_LIBCUDACXX_HAS_NVFP16)
+#  if defined(_CCCL_HAS_NVFP16)
   test<__half>(__double2half(1.0 / 0.0));
-#  endif // _LIBCUDACXX_HAS_NVFP16
-#  if defined(_LIBCUDACXX_HAS_NVBF16)
+#  endif // _CCCL_HAS_NVFP16
+#  if defined(_CCCL_HAS_NVBF16)
   test<__nv_bfloat16>(__double2bfloat16(1.0 / 0.0));
-#  endif // _LIBCUDACXX_HAS_NVBF16
+#  endif // _CCCL_HAS_NVBF16
 #  if _CCCL_HAS_NVFP8()
   test<__nv_fp8_e4m3>(__nv_fp8_e4m3{});
   test<__nv_fp8_e5m2>(make_fp8_e5m2(1.0 / 0.0));
@@ -81,12 +81,12 @@ int main(int, char**)
 #  ifndef _LIBCUDACXX_HAS_NO_LONG_DOUBLE
   test<long double>(INFINITY);
 #  endif
-#  if defined(_LIBCUDACXX_HAS_NVFP16)
+#  if defined(_CCCL_HAS_NVFP16)
   test<__half>(__double2half(INFINITY));
-#  endif // _LIBCUDACXX_HAS_NVFP16
-#  if defined(_LIBCUDACXX_HAS_NVBF16)
+#  endif // _CCCL_HAS_NVFP16
+#  if defined(_CCCL_HAS_NVBF16)
   test<__nv_bfloat16>(__double2bfloat16(INFINITY));
-#  endif // _LIBCUDACXX_HAS_NVBF16
+#  endif // _CCCL_HAS_NVBF16
 #  if _CCCL_HAS_NVFP8()
   test<__nv_fp8_e4m3>(__nv_fp8_e4m3{});
   test<__nv_fp8_e5m2>(make_fp8_e5m2(INFINITY));
diff --git a/libcudacxx/test/libcudacxx/std/language.support/support.limits/limits/numeric.limits.members/is_bounded.pass.cpp b/libcudacxx/test/libcudacxx/std/language.support/support.limits/limits/numeric.limits.members/is_bounded.pass.cpp
index eeb9740e4e2..e28ab8313b6 100644
--- a/libcudacxx/test/libcudacxx/std/language.support/support.limits/limits/numeric.limits.members/is_bounded.pass.cpp
+++ b/libcudacxx/test/libcudacxx/std/language.support/support.limits/limits/numeric.limits.members/is_bounded.pass.cpp
@@ -54,12 +54,12 @@ int main(int, char**)
 #ifndef _LIBCUDACXX_HAS_NO_LONG_DOUBLE
   test<long double, true>();
 #endif
-#if defined(_LIBCUDACXX_HAS_NVFP16)
+#if defined(_CCCL_HAS_NVFP16)
   test<__half, true>();
-#endif // _LIBCUDACXX_HAS_NVFP16
-#if defined(_LIBCUDACXX_HAS_NVBF16)
+#endif // _CCCL_HAS_NVFP16
+#if defined(_CCCL_HAS_NVBF16)
   test<__nv_bfloat16, true>();
-#endif // _LIBCUDACXX_HAS_NVBF16
+#endif // _CCCL_HAS_NVBF16
 #if _CCCL_HAS_NVFP8()
   test<__nv_fp8_e4m3, true>();
   test<__nv_fp8_e5m2, true>();
diff --git a/libcudacxx/test/libcudacxx/std/language.support/support.limits/limits/numeric.limits.members/is_exact.pass.cpp b/libcudacxx/test/libcudacxx/std/language.support/support.limits/limits/numeric.limits.members/is_exact.pass.cpp
index c3c2e027c72..e6038f1589b 100644
--- a/libcudacxx/test/libcudacxx/std/language.support/support.limits/limits/numeric.limits.members/is_exact.pass.cpp
+++ b/libcudacxx/test/libcudacxx/std/language.support/support.limits/limits/numeric.limits.members/is_exact.pass.cpp
@@ -54,12 +54,12 @@ int main(int, char**)
 #ifndef _LIBCUDACXX_HAS_NO_LONG_DOUBLE
   test<long double, false>();
 #endif
-#if defined(_LIBCUDACXX_HAS_NVFP16)
+#if defined(_CCCL_HAS_NVFP16)
   test<__half, false>();
-#endif // _LIBCUDACXX_HAS_NVFP16
-#if defined(_LIBCUDACXX_HAS_NVBF16)
+#endif // _CCCL_HAS_NVFP16
+#if defined(_CCCL_HAS_NVBF16)
   test<__nv_bfloat16, false>();
-#endif // _LIBCUDACXX_HAS_NVBF16
+#endif // _CCCL_HAS_NVBF16
 #if _CCCL_HAS_NVFP8()
   test<__nv_fp8_e4m3, false>();
   test<__nv_fp8_e5m2, false>();
diff --git a/libcudacxx/test/libcudacxx/std/language.support/support.limits/limits/numeric.limits.members/is_iec559.pass.cpp b/libcudacxx/test/libcudacxx/std/language.support/support.limits/limits/numeric.limits.members/is_iec559.pass.cpp
index 7bab40e8826..1ff809bad09 100644
--- a/libcudacxx/test/libcudacxx/std/language.support/support.limits/limits/numeric.limits.members/is_iec559.pass.cpp
+++ b/libcudacxx/test/libcudacxx/std/language.support/support.limits/limits/numeric.limits.members/is_iec559.pass.cpp
@@ -54,12 +54,12 @@ int main(int, char**)
 #ifndef _LIBCUDACXX_HAS_NO_LONG_DOUBLE
   test<long double, true>();
 #endif // _LIBCUDACXX_HAS_NO_LONG_DOUBLE
-#if defined(_LIBCUDACXX_HAS_NVFP16)
+#if defined(_CCCL_HAS_NVFP16)
   test<__half, true>();
-#endif // _LIBCUDACXX_HAS_NVFP16
-#if defined(_LIBCUDACXX_HAS_NVBF16)
+#endif // _CCCL_HAS_NVFP16
+#if defined(_CCCL_HAS_NVBF16)
   test<__nv_bfloat16, true>();
-#endif // _LIBCUDACXX_HAS_NVBF16
+#endif // _CCCL_HAS_NVBF16
 #if _CCCL_HAS_NVFP8()
   test<__nv_fp8_e4m3, false>();
   test<__nv_fp8_e5m2, false>();
diff --git a/libcudacxx/test/libcudacxx/std/language.support/support.limits/limits/numeric.limits.members/is_integer.pass.cpp b/libcudacxx/test/libcudacxx/std/language.support/support.limits/limits/numeric.limits.members/is_integer.pass.cpp
index 68e7437f1e0..eed9d38c050 100644
--- a/libcudacxx/test/libcudacxx/std/language.support/support.limits/limits/numeric.limits.members/is_integer.pass.cpp
+++ b/libcudacxx/test/libcudacxx/std/language.support/support.limits/limits/numeric.limits.members/is_integer.pass.cpp
@@ -54,12 +54,12 @@ int main(int, char**)
 #ifndef _LIBCUDACXX_HAS_NO_LONG_DOUBLE
   test<long double, false>();
 #endif
-#if defined(_LIBCUDACXX_HAS_NVFP16)
+#if defined(_CCCL_HAS_NVFP16)
   test<__half, false>();
-#endif // _LIBCUDACXX_HAS_NVFP16
-#if defined(_LIBCUDACXX_HAS_NVBF16)
+#endif // _CCCL_HAS_NVFP16
+#if defined(_CCCL_HAS_NVBF16)
   test<__nv_bfloat16, false>();
-#endif // _LIBCUDACXX_HAS_NVBF16
+#endif // _CCCL_HAS_NVBF16
 #if _CCCL_HAS_NVFP8()
   test<__nv_fp8_e4m3, false>();
   test<__nv_fp8_e5m2, false>();
diff --git a/libcudacxx/test/libcudacxx/std/language.support/support.limits/limits/numeric.limits.members/is_modulo.pass.cpp b/libcudacxx/test/libcudacxx/std/language.support/support.limits/limits/numeric.limits.members/is_modulo.pass.cpp
index 992be2b18b7..fc3ca9dbb4e 100644
--- a/libcudacxx/test/libcudacxx/std/language.support/support.limits/limits/numeric.limits.members/is_modulo.pass.cpp
+++ b/libcudacxx/test/libcudacxx/std/language.support/support.limits/limits/numeric.limits.members/is_modulo.pass.cpp
@@ -54,12 +54,12 @@ int main(int, char**)
 #ifndef _LIBCUDACXX_HAS_NO_LONG_DOUBLE
   test<long double, false>();
 #endif
-#if defined(_LIBCUDACXX_HAS_NVFP16)
+#if defined(_CCCL_HAS_NVFP16)
   test<__half, false>();
-#endif // _LIBCUDACXX_HAS_NVFP16
-#if defined(_LIBCUDACXX_HAS_NVBF16)
+#endif // _CCCL_HAS_NVFP16
+#if defined(_CCCL_HAS_NVBF16)
   test<__nv_bfloat16, false>();
-#endif // _LIBCUDACXX_HAS_NVBF16
+#endif // _CCCL_HAS_NVBF16
 #if _CCCL_HAS_NVFP8()
   test<__nv_fp8_e4m3, false>();
   test<__nv_fp8_e5m2, false>();
diff --git a/libcudacxx/test/libcudacxx/std/language.support/support.limits/limits/numeric.limits.members/is_signed.pass.cpp b/libcudacxx/test/libcudacxx/std/language.support/support.limits/limits/numeric.limits.members/is_signed.pass.cpp
index be7e4f235a7..54005f6c0b9 100644
--- a/libcudacxx/test/libcudacxx/std/language.support/support.limits/limits/numeric.limits.members/is_signed.pass.cpp
+++ b/libcudacxx/test/libcudacxx/std/language.support/support.limits/limits/numeric.limits.members/is_signed.pass.cpp
@@ -54,12 +54,12 @@ int main(int, char**)
 #ifndef _LIBCUDACXX_HAS_NO_LONG_DOUBLE
   test<long double, true>();
 #endif
-#if defined(_LIBCUDACXX_HAS_NVFP16)
+#if defined(_CCCL_HAS_NVFP16)
   test<__half, true>();
-#endif // _LIBCUDACXX_HAS_NVFP16
-#if defined(_LIBCUDACXX_HAS_NVBF16)
+#endif // _CCCL_HAS_NVFP16
+#if defined(_CCCL_HAS_NVBF16)
   test<__nv_bfloat16, true>();
-#endif // _LIBCUDACXX_HAS_NVBF16
+#endif // _CCCL_HAS_NVBF16
 #if _CCCL_HAS_NVFP8()
   test<__nv_fp8_e4m3, true>();
   test<__nv_fp8_e5m2, true>();
diff --git a/libcudacxx/test/libcudacxx/std/language.support/support.limits/limits/numeric.limits.members/lowest.pass.cpp b/libcudacxx/test/libcudacxx/std/language.support/support.limits/limits/numeric.limits.members/lowest.pass.cpp
index 6a8b2a9c181..72190bd2ad7 100644
--- a/libcudacxx/test/libcudacxx/std/language.support/support.limits/limits/numeric.limits.members/lowest.pass.cpp
+++ b/libcudacxx/test/libcudacxx/std/language.support/support.limits/limits/numeric.limits.members/lowest.pass.cpp
@@ -66,12 +66,12 @@ int main(int, char**)
 #ifndef _LIBCUDACXX_HAS_NO_LONG_DOUBLE
   test<long double>(-LDBL_MAX);
 #endif
-#if defined(_LIBCUDACXX_HAS_NVFP16)
+#if defined(_CCCL_HAS_NVFP16)
   test<__half>(__double2half(-65504.0));
-#endif // _LIBCUDACXX_HAS_NVFP16
-#if defined(_LIBCUDACXX_HAS_NVBF16)
+#endif // _CCCL_HAS_NVFP16
+#if defined(_CCCL_HAS_NVBF16)
   test<__nv_bfloat16>(__double2bfloat16(-3.3895313892515355e+38));
-#endif // _LIBCUDACXX_HAS_NVBF16
+#endif // _CCCL_HAS_NVBF16
 #if _CCCL_HAS_NVFP8()
   test<__nv_fp8_e4m3>(make_fp8_e4m3(-448.0));
   test<__nv_fp8_e5m2>(make_fp8_e5m2(-57344.0));
diff --git a/libcudacxx/test/libcudacxx/std/language.support/support.limits/limits/numeric.limits.members/max.pass.cpp b/libcudacxx/test/libcudacxx/std/language.support/support.limits/limits/numeric.limits.members/max.pass.cpp
index a1582e41b22..5039f773a2f 100644
--- a/libcudacxx/test/libcudacxx/std/language.support/support.limits/limits/numeric.limits.members/max.pass.cpp
+++ b/libcudacxx/test/libcudacxx/std/language.support/support.limits/limits/numeric.limits.members/max.pass.cpp
@@ -65,12 +65,12 @@ int main(int, char**)
 #ifndef _LIBCUDACXX_HAS_NO_LONG_DOUBLE
   test<long double>(LDBL_MAX);
 #endif
-#if defined(_LIBCUDACXX_HAS_NVFP16)
+#if defined(_CCCL_HAS_NVFP16)
   test<__half>(__double2half(65504.0));
-#endif // _LIBCUDACXX_HAS_NVFP16
-#if defined(_LIBCUDACXX_HAS_NVBF16)
+#endif // _CCCL_HAS_NVFP16
+#if defined(_CCCL_HAS_NVBF16)
   test<__nv_bfloat16>(__double2bfloat16(3.3895313892515355e+38));
-#endif // _LIBCUDACXX_HAS_NVBF16
+#endif // _CCCL_HAS_NVBF16
 #if _CCCL_HAS_NVFP8()
   test<__nv_fp8_e4m3>(make_fp8_e4m3(448.0));
   test<__nv_fp8_e5m2>(make_fp8_e5m2(57344.0));
diff --git a/libcudacxx/test/libcudacxx/std/language.support/support.limits/limits/numeric.limits.members/max_digits10.pass.cpp b/libcudacxx/test/libcudacxx/std/language.support/support.limits/limits/numeric.limits.members/max_digits10.pass.cpp
index d01a4aa099c..309279bc79c 100644
--- a/libcudacxx/test/libcudacxx/std/language.support/support.limits/limits/numeric.limits.members/max_digits10.pass.cpp
+++ b/libcudacxx/test/libcudacxx/std/language.support/support.limits/limits/numeric.limits.members/max_digits10.pass.cpp
@@ -69,12 +69,12 @@ int main(int, char**)
 #ifndef _LIBCUDACXX_HAS_NO_LONG_DOUBLE
   test<long double>();
 #endif
-#if defined(_LIBCUDACXX_HAS_NVFP16)
+#if defined(_CCCL_HAS_NVFP16)
   test<__half>();
-#endif // _LIBCUDACXX_HAS_NVFP16
-#if defined(_LIBCUDACXX_HAS_NVBF16)
+#endif // _CCCL_HAS_NVFP16
+#if defined(_CCCL_HAS_NVBF16)
   test<__nv_bfloat16>();
-#endif // _LIBCUDACXX_HAS_NVBF16
+#endif // _CCCL_HAS_NVBF16
 #if _CCCL_HAS_NVFP8()
   test<__nv_fp8_e4m3>();
   test<__nv_fp8_e5m2>();
diff --git a/libcudacxx/test/libcudacxx/std/language.support/support.limits/limits/numeric.limits.members/max_exponent.pass.cpp b/libcudacxx/test/libcudacxx/std/language.support/support.limits/limits/numeric.limits.members/max_exponent.pass.cpp
index 3027e9f06f5..606e9c52b7f 100644
--- a/libcudacxx/test/libcudacxx/std/language.support/support.limits/limits/numeric.limits.members/max_exponent.pass.cpp
+++ b/libcudacxx/test/libcudacxx/std/language.support/support.limits/limits/numeric.limits.members/max_exponent.pass.cpp
@@ -62,12 +62,12 @@ int main(int, char**)
 #ifndef _LIBCUDACXX_HAS_NO_LONG_DOUBLE
   test<long double, LDBL_MAX_EXP>();
 #endif
-#if defined(_LIBCUDACXX_HAS_NVFP16)
+#if defined(_CCCL_HAS_NVFP16)
   test<__half, 16>();
-#endif // _LIBCUDACXX_HAS_NVFP16
-#if defined(_LIBCUDACXX_HAS_NVBF16)
+#endif // _CCCL_HAS_NVFP16
+#if defined(_CCCL_HAS_NVBF16)
   test<__nv_bfloat16, 128>();
-#endif // _LIBCUDACXX_HAS_NVBF16
+#endif // _CCCL_HAS_NVBF16
 #if _CCCL_HAS_NVFP8()
   test<__nv_fp8_e4m3, 8>();
   test<__nv_fp8_e5m2, 15>();
diff --git a/libcudacxx/test/libcudacxx/std/language.support/support.limits/limits/numeric.limits.members/max_exponent10.pass.cpp b/libcudacxx/test/libcudacxx/std/language.support/support.limits/limits/numeric.limits.members/max_exponent10.pass.cpp
index 5924aee173d..61145deec86 100644
--- a/libcudacxx/test/libcudacxx/std/language.support/support.limits/limits/numeric.limits.members/max_exponent10.pass.cpp
+++ b/libcudacxx/test/libcudacxx/std/language.support/support.limits/limits/numeric.limits.members/max_exponent10.pass.cpp
@@ -62,12 +62,12 @@ int main(int, char**)
 #ifndef _LIBCUDACXX_HAS_NO_LONG_DOUBLE
   test<long double, LDBL_MAX_10_EXP>();
 #endif
-#if defined(_LIBCUDACXX_HAS_NVFP16)
+#if defined(_CCCL_HAS_NVFP16)
   test<__half, 4>();
-#endif // _LIBCUDACXX_HAS_NVFP16
-#if defined(_LIBCUDACXX_HAS_NVBF16)
+#endif // _CCCL_HAS_NVFP16
+#if defined(_CCCL_HAS_NVBF16)
   test<__nv_bfloat16, 38>();
-#endif // _LIBCUDACXX_HAS_NVBF16
+#endif // _CCCL_HAS_NVBF16
 #if _CCCL_HAS_NVFP8()
   test<__nv_fp8_e4m3, 2>();
   test<__nv_fp8_e5m2, 4>();
diff --git a/libcudacxx/test/libcudacxx/std/language.support/support.limits/limits/numeric.limits.members/min.pass.cpp b/libcudacxx/test/libcudacxx/std/language.support/support.limits/limits/numeric.limits.members/min.pass.cpp
index 15f470909df..ccab08a38f5 100644
--- a/libcudacxx/test/libcudacxx/std/language.support/support.limits/limits/numeric.limits.members/min.pass.cpp
+++ b/libcudacxx/test/libcudacxx/std/language.support/support.limits/limits/numeric.limits.members/min.pass.cpp
@@ -66,12 +66,12 @@ int main(int, char**)
 #ifndef _LIBCUDACXX_HAS_NO_LONG_DOUBLE
   test<long double>(LDBL_MIN);
 #endif
-#if defined(_LIBCUDACXX_HAS_NVFP16)
+#if defined(_CCCL_HAS_NVFP16)
   test<__half>(__double2half(6.103515625e-05));
-#endif // _LIBCUDACXX_HAS_NVFP16
-#if defined(_LIBCUDACXX_HAS_NVBF16)
+#endif // _CCCL_HAS_NVFP16
+#if defined(_CCCL_HAS_NVBF16)
   test<__nv_bfloat16>(__double2bfloat16(1.17549435082228750796873653722e-38));
-#endif // _LIBCUDACXX_HAS_NVBF16
+#endif // _CCCL_HAS_NVBF16
 #if _CCCL_HAS_NVFP8()
   test<__nv_fp8_e4m3>(make_fp8_e4m3(0.015625));
   test<__nv_fp8_e5m2>(make_fp8_e5m2(0.000061035));
diff --git a/libcudacxx/test/libcudacxx/std/language.support/support.limits/limits/numeric.limits.members/min_exponent.pass.cpp b/libcudacxx/test/libcudacxx/std/language.support/support.limits/limits/numeric.limits.members/min_exponent.pass.cpp
index b63d653a7c3..c942a6288be 100644
--- a/libcudacxx/test/libcudacxx/std/language.support/support.limits/limits/numeric.limits.members/min_exponent.pass.cpp
+++ b/libcudacxx/test/libcudacxx/std/language.support/support.limits/limits/numeric.limits.members/min_exponent.pass.cpp
@@ -62,12 +62,12 @@ int main(int, char**)
 #ifndef _LIBCUDACXX_HAS_NO_LONG_DOUBLE
   test<long double, LDBL_MIN_EXP>();
 #endif
-#if defined(_LIBCUDACXX_HAS_NVFP16)
+#if defined(_CCCL_HAS_NVFP16)
   test<__half, -13>();
-#endif // _LIBCUDACXX_HAS_NVFP16
-#if defined(_LIBCUDACXX_HAS_NVBF16)
+#endif // _CCCL_HAS_NVFP16
+#if defined(_CCCL_HAS_NVBF16)
   test<__nv_bfloat16, -125>();
-#endif // _LIBCUDACXX_HAS_NVBF16
+#endif // _CCCL_HAS_NVBF16
 #if _CCCL_HAS_NVFP8()
   test<__nv_fp8_e4m3, -6>();
   test<__nv_fp8_e5m2, -15>();
diff --git a/libcudacxx/test/libcudacxx/std/language.support/support.limits/limits/numeric.limits.members/min_exponent10.pass.cpp b/libcudacxx/test/libcudacxx/std/language.support/support.limits/limits/numeric.limits.members/min_exponent10.pass.cpp
index a6ff20e7fde..e9b6f29d25f 100644
--- a/libcudacxx/test/libcudacxx/std/language.support/support.limits/limits/numeric.limits.members/min_exponent10.pass.cpp
+++ b/libcudacxx/test/libcudacxx/std/language.support/support.limits/limits/numeric.limits.members/min_exponent10.pass.cpp
@@ -62,12 +62,12 @@ int main(int, char**)
 #ifndef _LIBCUDACXX_HAS_NO_LONG_DOUBLE
   test<long double, LDBL_MIN_10_EXP>();
 #endif
-#if defined(_LIBCUDACXX_HAS_NVFP16)
+#if defined(_CCCL_HAS_NVFP16)
   test<__half, -4>();
-#endif // _LIBCUDACXX_HAS_NVFP16
-#if defined(_LIBCUDACXX_HAS_NVBF16)
+#endif // _CCCL_HAS_NVFP16
+#if defined(_CCCL_HAS_NVBF16)
   test<__nv_bfloat16, -37>();
-#endif // _LIBCUDACXX_HAS_NVBF16
+#endif // _CCCL_HAS_NVBF16
 #if _CCCL_HAS_NVFP8()
   test<__nv_fp8_e4m3, -2>();
   test<__nv_fp8_e5m2, -5>();
diff --git a/libcudacxx/test/libcudacxx/std/language.support/support.limits/limits/numeric.limits.members/quiet_NaN.pass.cpp b/libcudacxx/test/libcudacxx/std/language.support/support.limits/limits/numeric.limits.members/quiet_NaN.pass.cpp
index 2d6d9582f5c..a8b076fbeee 100644
--- a/libcudacxx/test/libcudacxx/std/language.support/support.limits/limits/numeric.limits.members/quiet_NaN.pass.cpp
+++ b/libcudacxx/test/libcudacxx/std/language.support/support.limits/limits/numeric.limits.members/quiet_NaN.pass.cpp
@@ -108,12 +108,12 @@ int main(int, char**)
 #ifndef _LIBCUDACXX_HAS_NO_LONG_DOUBLE
   test<long double>();
 #endif
-#if defined(_LIBCUDACXX_HAS_NVFP16)
+#if defined(_CCCL_HAS_NVFP16)
   test<__half>();
-#endif // _LIBCUDACXX_HAS_NVFP16
-#if defined(_LIBCUDACXX_HAS_NVBF16)
+#endif // _CCCL_HAS_NVFP16
+#if defined(_CCCL_HAS_NVBF16)
   test<__nv_bfloat16>();
-#endif // _LIBCUDACXX_HAS_NVBF16
+#endif // _CCCL_HAS_NVBF16
 #if _CCCL_HAS_NVFP8()
   test<__nv_fp8_e4m3>();
   test<__nv_fp8_e5m2>();
diff --git a/libcudacxx/test/libcudacxx/std/language.support/support.limits/limits/numeric.limits.members/radix.pass.cpp b/libcudacxx/test/libcudacxx/std/language.support/support.limits/limits/numeric.limits.members/radix.pass.cpp
index 7e5c87927aa..dd15c391180 100644
--- a/libcudacxx/test/libcudacxx/std/language.support/support.limits/limits/numeric.limits.members/radix.pass.cpp
+++ b/libcudacxx/test/libcudacxx/std/language.support/support.limits/limits/numeric.limits.members/radix.pass.cpp
@@ -55,12 +55,12 @@ int main(int, char**)
 #ifndef _LIBCUDACXX_HAS_NO_LONG_DOUBLE
   test<long double, FLT_RADIX>();
 #endif
-#if defined(_LIBCUDACXX_HAS_NVFP16)
+#if defined(_CCCL_HAS_NVFP16)
   test<__half, FLT_RADIX>();
-#endif // _LIBCUDACXX_HAS_NVFP16
-#if defined(_LIBCUDACXX_HAS_NVBF16)
+#endif // _CCCL_HAS_NVFP16
+#if defined(_CCCL_HAS_NVBF16)
   test<__nv_bfloat16, FLT_RADIX>();
-#endif // _LIBCUDACXX_HAS_NVBF16
+#endif // _CCCL_HAS_NVBF16
 #if _CCCL_HAS_NVFP8()
   test<__nv_fp8_e4m3, FLT_RADIX>();
   test<__nv_fp8_e5m2, FLT_RADIX>();
diff --git a/libcudacxx/test/libcudacxx/std/language.support/support.limits/limits/numeric.limits.members/round_error.pass.cpp b/libcudacxx/test/libcudacxx/std/language.support/support.limits/limits/numeric.limits.members/round_error.pass.cpp
index d4faf373a09..95ed80eb951 100644
--- a/libcudacxx/test/libcudacxx/std/language.support/support.limits/limits/numeric.limits.members/round_error.pass.cpp
+++ b/libcudacxx/test/libcudacxx/std/language.support/support.limits/limits/numeric.limits.members/round_error.pass.cpp
@@ -57,12 +57,12 @@ int main(int, char**)
 #ifndef _LIBCUDACXX_HAS_NO_LONG_DOUBLE
   test<long double>(0.5);
 #endif
-#if defined(_LIBCUDACXX_HAS_NVFP16)
+#if defined(_CCCL_HAS_NVFP16)
   test<__half>(__double2half(0.5));
-#endif // _LIBCUDACXX_HAS_NVFP16
-#if defined(_LIBCUDACXX_HAS_NVBF16)
+#endif // _CCCL_HAS_NVFP16
+#if defined(_CCCL_HAS_NVBF16)
   test<__nv_bfloat16>(__double2bfloat16(0.5));
-#endif // _LIBCUDACXX_HAS_NVBF16
+#endif // _CCCL_HAS_NVBF16
 #if _CCCL_HAS_NVFP8()
   test<__nv_fp8_e4m3>(make_fp8_e4m3(0.5));
   test<__nv_fp8_e5m2>(make_fp8_e5m2(0.5));
diff --git a/libcudacxx/test/libcudacxx/std/language.support/support.limits/limits/numeric.limits.members/round_style.pass.cpp b/libcudacxx/test/libcudacxx/std/language.support/support.limits/limits/numeric.limits.members/round_style.pass.cpp
index 8515581d650..1eb5c0b0f5a 100644
--- a/libcudacxx/test/libcudacxx/std/language.support/support.limits/limits/numeric.limits.members/round_style.pass.cpp
+++ b/libcudacxx/test/libcudacxx/std/language.support/support.limits/limits/numeric.limits.members/round_style.pass.cpp
@@ -54,12 +54,12 @@ int main(int, char**)
 #ifndef _LIBCUDACXX_HAS_NO_LONG_DOUBLE
   test<long double, cuda::std::round_to_nearest>();
 #endif
-#if defined(_LIBCUDACXX_HAS_NVFP16)
+#if defined(_CCCL_HAS_NVFP16)
   test<__half, cuda::std::round_to_nearest>();
-#endif // _LIBCUDACXX_HAS_NVFP16
-#if defined(_LIBCUDACXX_HAS_NVBF16)
+#endif // _CCCL_HAS_NVFP16
+#if defined(_CCCL_HAS_NVBF16)
   test<__nv_bfloat16, cuda::std::round_to_nearest>();
-#endif // _LIBCUDACXX_HAS_NVBF16
+#endif // _CCCL_HAS_NVBF16
 #if _CCCL_HAS_NVFP8()
   test<__nv_fp8_e4m3, cuda::std::round_to_nearest>();
   test<__nv_fp8_e5m2, cuda::std::round_to_nearest>();
diff --git a/libcudacxx/test/libcudacxx/std/language.support/support.limits/limits/numeric.limits.members/signaling_NaN.pass.cpp b/libcudacxx/test/libcudacxx/std/language.support/support.limits/limits/numeric.limits.members/signaling_NaN.pass.cpp
index 19ace1b3d2c..0ec70976b32 100644
--- a/libcudacxx/test/libcudacxx/std/language.support/support.limits/limits/numeric.limits.members/signaling_NaN.pass.cpp
+++ b/libcudacxx/test/libcudacxx/std/language.support/support.limits/limits/numeric.limits.members/signaling_NaN.pass.cpp
@@ -108,12 +108,12 @@ int main(int, char**)
 #ifndef _LIBCUDACXX_HAS_NO_LONG_DOUBLE
   test<long double>();
 #endif
-#if defined(_LIBCUDACXX_HAS_NVFP16)
+#if defined(_CCCL_HAS_NVFP16)
   test<__half>();
-#endif // _LIBCUDACXX_HAS_NVFP16
-#if defined(_LIBCUDACXX_HAS_NVBF16)
+#endif // _CCCL_HAS_NVFP16
+#if defined(_CCCL_HAS_NVBF16)
   test<__nv_bfloat16>();
-#endif // _LIBCUDACXX_HAS_NVBF16
+#endif // _CCCL_HAS_NVBF16
 #if _CCCL_HAS_NVFP8()
   test<__nv_fp8_e4m3>();
   test<__nv_fp8_e5m2>();
diff --git a/libcudacxx/test/libcudacxx/std/language.support/support.limits/limits/numeric.limits.members/tinyness_before.pass.cpp b/libcudacxx/test/libcudacxx/std/language.support/support.limits/limits/numeric.limits.members/tinyness_before.pass.cpp
index 38dec8c872b..1da28874b06 100644
--- a/libcudacxx/test/libcudacxx/std/language.support/support.limits/limits/numeric.limits.members/tinyness_before.pass.cpp
+++ b/libcudacxx/test/libcudacxx/std/language.support/support.limits/limits/numeric.limits.members/tinyness_before.pass.cpp
@@ -54,12 +54,12 @@ int main(int, char**)
 #ifndef _LIBCUDACXX_HAS_NO_LONG_DOUBLE
   test<long double, false>();
 #endif
-#if defined(_LIBCUDACXX_HAS_NVFP16)
+#if defined(_CCCL_HAS_NVFP16)
   test<__half, false>();
-#endif // _LIBCUDACXX_HAS_NVFP16
-#if defined(_LIBCUDACXX_HAS_NVBF16)
+#endif // _CCCL_HAS_NVFP16
+#if defined(_CCCL_HAS_NVBF16)
   test<__nv_bfloat16, false>();
-#endif // _LIBCUDACXX_HAS_NVBF16
+#endif // _CCCL_HAS_NVBF16
 #if _CCCL_HAS_NVFP8()
   test<__nv_fp8_e4m3, false>();
   test<__nv_fp8_e5m2, false>();
diff --git a/libcudacxx/test/libcudacxx/std/language.support/support.limits/limits/numeric.limits.members/traps.pass.cpp b/libcudacxx/test/libcudacxx/std/language.support/support.limits/limits/numeric.limits.members/traps.pass.cpp
index 55d7eb990db..4cb627a4b77 100644
--- a/libcudacxx/test/libcudacxx/std/language.support/support.limits/limits/numeric.limits.members/traps.pass.cpp
+++ b/libcudacxx/test/libcudacxx/std/language.support/support.limits/limits/numeric.limits.members/traps.pass.cpp
@@ -60,12 +60,12 @@ int main(int, char**)
 #ifndef _LIBCUDACXX_HAS_NO_LONG_DOUBLE
   test<long double, false>();
 #endif
-#if defined(_LIBCUDACXX_HAS_NVFP16)
+#if defined(_CCCL_HAS_NVFP16)
   test<__half, false>();
-#endif // _LIBCUDACXX_HAS_NVFP16
-#if defined(_LIBCUDACXX_HAS_NVBF16)
+#endif // _CCCL_HAS_NVFP16
+#if defined(_CCCL_HAS_NVBF16)
   test<__nv_bfloat16, false>();
-#endif // _LIBCUDACXX_HAS_NVBF16
+#endif // _CCCL_HAS_NVBF16
 #if _CCCL_HAS_NVFP8()
   test<__nv_fp8_e4m3, false>();
   test<__nv_fp8_e5m2, false>();

From b6209e841a72eb7def4ba2aace30eff8a9b539a4 Mon Sep 17 00:00:00 2001
From: Michael Schellenberger Costa <miscco@nvidia.com>
Date: Thu, 30 Jan 2025 09:06:31 +0100
Subject: [PATCH 14/33] Suppress execution checks for vocabulary types (#3578)

* Suppress execution checks for optional
* Suppress execution checks for `expected`
* Suppress execution checks for `pair`
* Suppress execution checks for `variant`
---
 .../cuda/std/__expected/bad_expected_access.h |  21 +-
 .../include/cuda/std/__expected/expected.h    |  20 ++
 .../cuda/std/__expected/expected_base.h       |  18 ++
 .../include/cuda/std/__expected/unexpected.h  |   7 +
 .../include/cuda/std/__memory/construct_at.h  |   1 +
 libcudacxx/include/cuda/std/__utility/pair.h  |  19 +-
 .../cuda/std/detail/libcxx/include/optional   |  25 +++
 .../cuda/std/detail/libcxx/include/tuple      |   2 +
 .../cuda/std/detail/libcxx/include/variant    |  20 ++
 .../expected/device_only_types.pass.cpp       | 201 ++++++++++++++++++
 .../expected/host_only_types.pass.cpp         | 199 +++++++++++++++++
 .../optional/device_only_types.pass.cpp       | 136 ++++++++++++
 .../optional/host_only_types.pass.cpp         | 134 ++++++++++++
 .../tuple/device_only_types.pass.cpp          |  81 +++++++
 .../tuple/forward_as_tuple_interop.pass.cpp   |   0
 .../utilities/tuple/host_only_types.pass.cpp  |  90 ++++++++
 .../tuple/vector_types_get.pass.cpp           |   0
 .../vector_types_structured_bindings.pass.cpp |   0
 .../tuple/vector_types_tuple_element.pass.cpp |   0
 .../tuple/vector_types_tuple_size.pass.cpp    |   0
 .../unexpected/device_only_types.pass.cpp     |  82 +++++++
 .../unexpected/host_only_types.pass.cpp       |  85 ++++++++
 .../utility/pair/device_only_types.pass.cpp   |  93 ++++++++
 .../utility/pair/host_only_types.pass.cpp     |  93 ++++++++
 .../pair/interop}/pair.assign.pass.cpp        |   0
 .../utility/pair/interop}/pair.cons.pass.cpp  |   0
 .../utility/pair/interop}/pair.conv.pass.cpp  |   0
 .../variant/device_only_types.pass.cpp        | 120 +++++++++++
 .../variant/host_only_types.pass.cpp          | 129 +++++++++++
 libcudacxx/test/support/host_device_types.h   | 148 +++++++++++++
 30 files changed, 1714 insertions(+), 10 deletions(-)
 create mode 100644 libcudacxx/test/libcudacxx/cuda/utilities/expected/device_only_types.pass.cpp
 create mode 100644 libcudacxx/test/libcudacxx/cuda/utilities/expected/host_only_types.pass.cpp
 create mode 100644 libcudacxx/test/libcudacxx/cuda/utilities/optional/device_only_types.pass.cpp
 create mode 100644 libcudacxx/test/libcudacxx/cuda/utilities/optional/host_only_types.pass.cpp
 create mode 100644 libcudacxx/test/libcudacxx/cuda/utilities/tuple/device_only_types.pass.cpp
 rename libcudacxx/test/libcudacxx/cuda/{ => utilities}/tuple/forward_as_tuple_interop.pass.cpp (100%)
 create mode 100644 libcudacxx/test/libcudacxx/cuda/utilities/tuple/host_only_types.pass.cpp
 rename libcudacxx/test/libcudacxx/cuda/{ => utilities}/tuple/vector_types_get.pass.cpp (100%)
 rename libcudacxx/test/libcudacxx/cuda/{ => utilities}/tuple/vector_types_structured_bindings.pass.cpp (100%)
 rename libcudacxx/test/libcudacxx/cuda/{ => utilities}/tuple/vector_types_tuple_element.pass.cpp (100%)
 rename libcudacxx/test/libcudacxx/cuda/{ => utilities}/tuple/vector_types_tuple_size.pass.cpp (100%)
 create mode 100644 libcudacxx/test/libcudacxx/cuda/utilities/unexpected/device_only_types.pass.cpp
 create mode 100644 libcudacxx/test/libcudacxx/cuda/utilities/unexpected/host_only_types.pass.cpp
 create mode 100644 libcudacxx/test/libcudacxx/cuda/utilities/utility/pair/device_only_types.pass.cpp
 create mode 100644 libcudacxx/test/libcudacxx/cuda/utilities/utility/pair/host_only_types.pass.cpp
 rename libcudacxx/test/libcudacxx/cuda/{pair_interop => utilities/utility/pair/interop}/pair.assign.pass.cpp (100%)
 rename libcudacxx/test/libcudacxx/cuda/{pair_interop => utilities/utility/pair/interop}/pair.cons.pass.cpp (100%)
 rename libcudacxx/test/libcudacxx/cuda/{pair_interop => utilities/utility/pair/interop}/pair.conv.pass.cpp (100%)
 create mode 100644 libcudacxx/test/libcudacxx/cuda/utilities/variant/device_only_types.pass.cpp
 create mode 100644 libcudacxx/test/libcudacxx/cuda/utilities/variant/host_only_types.pass.cpp
 create mode 100644 libcudacxx/test/support/host_device_types.h

diff --git a/libcudacxx/include/cuda/std/__expected/bad_expected_access.h b/libcudacxx/include/cuda/std/__expected/bad_expected_access.h
index 5600402e429..0f10f546be6 100644
--- a/libcudacxx/include/cuda/std/__expected/bad_expected_access.h
+++ b/libcudacxx/include/cuda/std/__expected/bad_expected_access.h
@@ -51,14 +51,6 @@ class bad_expected_access;
 template <>
 class bad_expected_access<void> : public ::std::exception
 {
-protected:
-  _CCCL_HIDE_FROM_ABI bad_expected_access() noexcept                             = default;
-  _CCCL_HIDE_FROM_ABI bad_expected_access(const bad_expected_access&)            = default;
-  _CCCL_HIDE_FROM_ABI bad_expected_access(bad_expected_access&&)                 = default;
-  _CCCL_HIDE_FROM_ABI bad_expected_access& operator=(const bad_expected_access&) = default;
-  _CCCL_HIDE_FROM_ABI bad_expected_access& operator=(bad_expected_access&&)      = default;
-  ~bad_expected_access() noexcept override                                       = default;
-
 public:
   // The way this has been designed (by using a class template below) means that we'll already
   // have a profusion of these vtables in TUs, and the dynamic linker will already have a bunch
@@ -74,10 +66,21 @@ template <class _Err>
 class bad_expected_access : public bad_expected_access<void>
 {
 public:
-  explicit bad_expected_access(_Err __e)
+#      if _CCCL_CUDA_COMPILER(CLANG) // Clang needs this or it breaks with device only types
+  _CCCL_HOST_DEVICE
+#      endif // _CCCL_CUDA_COMPILER(CLANG)
+  _CCCL_HIDE_FROM_ABI explicit bad_expected_access(_Err __e)
       : __unex_(_CUDA_VSTD::move(__e))
   {}
 
+#      if _CCCL_CUDA_COMPILER(CLANG) // Clang needs this or it breaks with device only types
+  _CCCL_HOST_DEVICE
+#      endif // _CCCL_CUDA_COMPILER(CLANG)
+  _CCCL_HIDE_FROM_ABI ~bad_expected_access() noexcept
+  {
+    __unex_.~_Err();
+  }
+
   _LIBCUDACXX_HIDE_FROM_ABI _Err& error() & noexcept
   {
     return __unex_;
diff --git a/libcudacxx/include/cuda/std/__expected/expected.h b/libcudacxx/include/cuda/std/__expected/expected.h
index cc5ddfc03f0..f618ff57c92 100644
--- a/libcudacxx/include/cuda/std/__expected/expected.h
+++ b/libcudacxx/include/cuda/std/__expected/expected.h
@@ -1070,6 +1070,7 @@ class expected : private __expected_move_assign<_Tp, _Err>
   }
 
   // [expected.object.eq], equality operators
+  _CCCL_EXEC_CHECK_DISABLE
   friend _LIBCUDACXX_HIDE_FROM_ABI constexpr bool operator==(const expected& __x, const expected& __y)
   {
     if (__x.__has_val_ != __y.has_value())
@@ -1090,12 +1091,14 @@ class expected : private __expected_move_assign<_Tp, _Err>
   }
 
 #  if _CCCL_STD_VER < 2020
+  _CCCL_EXEC_CHECK_DISABLE
   friend _LIBCUDACXX_HIDE_FROM_ABI constexpr bool operator!=(const expected& __x, const expected& __y)
   {
     return !(__x == __y);
   }
 #  endif // _CCCL_STD_VER < 2020
 
+  _CCCL_EXEC_CHECK_DISABLE
   _CCCL_TEMPLATE(class _T2, class _E2)
   _CCCL_REQUIRES((!_CCCL_TRAIT(is_void, _T2)))
   friend _LIBCUDACXX_HIDE_FROM_ABI constexpr bool operator==(const expected& __x, const expected<_T2, _E2>& __y)
@@ -1118,6 +1121,7 @@ class expected : private __expected_move_assign<_Tp, _Err>
   }
 
 #  if _CCCL_STD_VER < 2020
+  _CCCL_EXEC_CHECK_DISABLE
   _CCCL_TEMPLATE(class _T2, class _E2)
   _CCCL_REQUIRES((!_CCCL_TRAIT(is_void, _T2)))
   friend _LIBCUDACXX_HIDE_FROM_ABI constexpr bool operator!=(const expected& __x, const expected<_T2, _E2>& __y)
@@ -1126,6 +1130,7 @@ class expected : private __expected_move_assign<_Tp, _Err>
   }
 #  endif // _CCCL_STD_VER < 2020
 
+  _CCCL_EXEC_CHECK_DISABLE
   _CCCL_TEMPLATE(class _T2)
   _CCCL_REQUIRES((!__expected::__is_expected_nonvoid<_T2>) )
   friend _LIBCUDACXX_HIDE_FROM_ABI constexpr bool operator==(const expected& __x, const _T2& __v)
@@ -1133,18 +1138,21 @@ class expected : private __expected_move_assign<_Tp, _Err>
     return __x.__has_val_ && static_cast<bool>(__x.__union_.__val_ == __v);
   }
 #  if _CCCL_STD_VER < 2020
+  _CCCL_EXEC_CHECK_DISABLE
   _CCCL_TEMPLATE(class _T2)
   _CCCL_REQUIRES((!__expected::__is_expected_nonvoid<_T2>) )
   friend _LIBCUDACXX_HIDE_FROM_ABI constexpr bool operator==(const _T2& __v, const expected& __x)
   {
     return __x.__has_val_ && static_cast<bool>(__x.__union_.__val_ == __v);
   }
+  _CCCL_EXEC_CHECK_DISABLE
   _CCCL_TEMPLATE(class _T2)
   _CCCL_REQUIRES((!__expected::__is_expected_nonvoid<_T2>) )
   friend _LIBCUDACXX_HIDE_FROM_ABI constexpr bool operator!=(const expected& __x, const _T2& __v)
   {
     return !__x.__has_val_ || static_cast<bool>(__x.__union_.__val_ != __v);
   }
+  _CCCL_EXEC_CHECK_DISABLE
   _CCCL_TEMPLATE(class _T2)
   _CCCL_REQUIRES((!__expected::__is_expected_nonvoid<_T2>) )
   friend _LIBCUDACXX_HIDE_FROM_ABI constexpr bool operator!=(const _T2& __v, const expected& __x)
@@ -1153,22 +1161,26 @@ class expected : private __expected_move_assign<_Tp, _Err>
   }
 #  endif // _CCCL_STD_VER < 2020
 
+  _CCCL_EXEC_CHECK_DISABLE
   template <class _E2>
   friend _LIBCUDACXX_HIDE_FROM_ABI constexpr bool operator==(const expected& __x, const unexpected<_E2>& __e)
   {
     return !__x.__has_val_ && static_cast<bool>(__x.__union_.__unex_ == __e.error());
   }
 #  if _CCCL_STD_VER < 2020
+  _CCCL_EXEC_CHECK_DISABLE
   template <class _E2>
   friend _LIBCUDACXX_HIDE_FROM_ABI constexpr bool operator==(const unexpected<_E2>& __e, const expected& __x)
   {
     return !__x.__has_val_ && static_cast<bool>(__x.__union_.__unex_ == __e.error());
   }
+  _CCCL_EXEC_CHECK_DISABLE
   template <class _E2>
   friend _LIBCUDACXX_HIDE_FROM_ABI constexpr bool operator!=(const expected& __x, const unexpected<_E2>& __e)
   {
     return __x.__has_val_ || static_cast<bool>(__x.__union_.__unex_ != __e.error());
   }
+  _CCCL_EXEC_CHECK_DISABLE
   template <class _E2>
   friend _LIBCUDACXX_HIDE_FROM_ABI constexpr bool operator!=(const unexpected<_E2>& __e, const expected& __x)
   {
@@ -1906,6 +1918,7 @@ class expected<void, _Err> : private __expected_move_assign<void, _Err>
   }
 
   // [expected.void.eq], equality operators
+  _CCCL_EXEC_CHECK_DISABLE
   friend _LIBCUDACXX_HIDE_FROM_ABI constexpr bool operator==(const expected& __x, const expected& __y) noexcept
   {
     if (__x.__has_val_ != __y.has_value())
@@ -1918,12 +1931,14 @@ class expected<void, _Err> : private __expected_move_assign<void, _Err>
     }
   }
 #  if _CCCL_STD_VER < 2020
+  _CCCL_EXEC_CHECK_DISABLE
   friend _LIBCUDACXX_HIDE_FROM_ABI constexpr bool operator!=(const expected& __x, const expected& __y) noexcept
   {
     return !(__x == __y);
   }
 #  endif
 
+  _CCCL_EXEC_CHECK_DISABLE
   template <class _E2>
   friend _LIBCUDACXX_HIDE_FROM_ABI constexpr bool
   operator==(const expected& __x, const expected<void, _E2>& __y) noexcept
@@ -1938,6 +1953,7 @@ class expected<void, _Err> : private __expected_move_assign<void, _Err>
     }
   }
 #  if _CCCL_STD_VER < 2020
+  _CCCL_EXEC_CHECK_DISABLE
   template <class _E2>
   friend _LIBCUDACXX_HIDE_FROM_ABI constexpr bool
   operator!=(const expected& __x, const expected<void, _E2>& __y) noexcept
@@ -1946,22 +1962,26 @@ class expected<void, _Err> : private __expected_move_assign<void, _Err>
   }
 #  endif
 
+  _CCCL_EXEC_CHECK_DISABLE
   template <class _E2>
   friend _LIBCUDACXX_HIDE_FROM_ABI constexpr bool operator==(const expected& __x, const unexpected<_E2>& __y) noexcept
   {
     return !__x.__has_val_ && static_cast<bool>(__x.__union_.__unex_ == __y.error());
   }
 #  if _CCCL_STD_VER < 2020
+  _CCCL_EXEC_CHECK_DISABLE
   template <class _E2>
   friend _LIBCUDACXX_HIDE_FROM_ABI constexpr bool operator==(const unexpected<_E2>& __y, const expected& __x) noexcept
   {
     return !__x.__has_val_ && static_cast<bool>(__x.__union_.__unex_ == __y.error());
   }
+  _CCCL_EXEC_CHECK_DISABLE
   template <class _E2>
   _LIBCUDACXX_HIDE_FROM_ABI friend constexpr bool operator!=(const expected& __x, const unexpected<_E2>& __y) noexcept
   {
     return __x.__has_val_ || static_cast<bool>(__x.__union_.__unex_ != __y.error());
   }
+  _CCCL_EXEC_CHECK_DISABLE
   template <class _E2>
   _LIBCUDACXX_HIDE_FROM_ABI friend constexpr bool operator!=(const unexpected<_E2>& __y, const expected& __x) noexcept
   {
diff --git a/libcudacxx/include/cuda/std/__expected/expected_base.h b/libcudacxx/include/cuda/std/__expected/expected_base.h
index 31de97e3f50..0de6cc29158 100644
--- a/libcudacxx/include/cuda/std/__expected/expected_base.h
+++ b/libcudacxx/include/cuda/std/__expected/expected_base.h
@@ -71,30 +71,35 @@ union __expected_union_t
   struct __empty_t
   {};
 
+  _CCCL_EXEC_CHECK_DISABLE
   _CCCL_TEMPLATE(class _Tp2 = _Tp)
   _CCCL_REQUIRES(_CCCL_TRAIT(is_default_constructible, _Tp2))
   _LIBCUDACXX_HIDE_FROM_ABI constexpr __expected_union_t() noexcept(_CCCL_TRAIT(is_nothrow_default_constructible, _Tp2))
       : __val_()
   {}
 
+  _CCCL_EXEC_CHECK_DISABLE
   _CCCL_TEMPLATE(class _Tp2 = _Tp)
   _CCCL_REQUIRES((!_CCCL_TRAIT(is_default_constructible, _Tp2)))
   _LIBCUDACXX_HIDE_FROM_ABI constexpr __expected_union_t() noexcept
       : __empty_()
   {}
 
+  _CCCL_EXEC_CHECK_DISABLE
   template <class... _Args>
   _LIBCUDACXX_HIDE_FROM_ABI constexpr __expected_union_t(in_place_t, _Args&&... __args) noexcept(
     _CCCL_TRAIT(is_nothrow_constructible, _Tp, _Args...))
       : __val_(_CUDA_VSTD::forward<_Args>(__args)...)
   {}
 
+  _CCCL_EXEC_CHECK_DISABLE
   template <class... _Args>
   _LIBCUDACXX_HIDE_FROM_ABI constexpr __expected_union_t(unexpect_t, _Args&&... __args) noexcept(
     _CCCL_TRAIT(is_nothrow_constructible, _Err, _Args...))
       : __unex_(_CUDA_VSTD::forward<_Args>(__args)...)
   {}
 
+  _CCCL_EXEC_CHECK_DISABLE
   template <class _Fun, class... _Args>
   _LIBCUDACXX_HIDE_FROM_ABI constexpr __expected_union_t(
     __expected_construct_from_invoke_tag,
@@ -104,6 +109,7 @@ union __expected_union_t
       : __val_(_CUDA_VSTD::invoke(_CUDA_VSTD::forward<_Fun>(__fun), _CUDA_VSTD::forward<_Args>(__args)...))
   {}
 
+  _CCCL_EXEC_CHECK_DISABLE
   template <class _Fun, class... _Args>
   _LIBCUDACXX_HIDE_FROM_ABI constexpr __expected_union_t(
     __expected_construct_from_invoke_tag,
@@ -128,18 +134,21 @@ union __expected_union_t<_Tp, _Err, true>
   struct __empty_t
   {};
 
+  _CCCL_EXEC_CHECK_DISABLE
   _CCCL_TEMPLATE(class _Tp2 = _Tp)
   _CCCL_REQUIRES(_CCCL_TRAIT(is_default_constructible, _Tp2))
   _LIBCUDACXX_HIDE_FROM_ABI constexpr __expected_union_t() noexcept(_CCCL_TRAIT(is_nothrow_default_constructible, _Tp2))
       : __val_()
   {}
 
+  _CCCL_EXEC_CHECK_DISABLE
   _CCCL_TEMPLATE(class _Tp2 = _Tp)
   _CCCL_REQUIRES((!_CCCL_TRAIT(is_default_constructible, _Tp2)))
   _LIBCUDACXX_HIDE_FROM_ABI constexpr __expected_union_t() noexcept
       : __empty_()
   {}
 
+  _CCCL_EXEC_CHECK_DISABLE
   template <class... _Args>
   _LIBCUDACXX_HIDE_FROM_ABI constexpr __expected_union_t(in_place_t, _Args&&... __args) noexcept(
     _CCCL_TRAIT(is_nothrow_constructible, _Tp, _Args...))
@@ -152,6 +161,7 @@ union __expected_union_t<_Tp, _Err, true>
       : __unex_(_CUDA_VSTD::forward<_Args>(__args)...)
   {}
 
+  _CCCL_EXEC_CHECK_DISABLE
   template <class _Fun, class... _Args>
   _LIBCUDACXX_HIDE_FROM_ABI constexpr __expected_union_t(
     __expected_construct_from_invoke_tag,
@@ -161,6 +171,7 @@ union __expected_union_t<_Tp, _Err, true>
       : __val_(_CUDA_VSTD::invoke(_CUDA_VSTD::forward<_Fun>(__fun), _CUDA_VSTD::forward<_Args>(__args)...))
   {}
 
+  _CCCL_EXEC_CHECK_DISABLE
   template <class _Fun, class... _Args>
   _LIBCUDACXX_HIDE_FROM_ABI constexpr __expected_union_t(
     __expected_construct_from_invoke_tag,
@@ -436,6 +447,7 @@ struct __expected_storage : __expected_destruct<_Tp, _Err>
 {
   _LIBCUDACXX_DELEGATE_CONSTRUCTORS(__expected_storage, __expected_destruct, _Tp, _Err);
 
+  _CCCL_EXEC_CHECK_DISABLE
   _CCCL_TEMPLATE(class _T1, class _T2, class... _Args)
   _CCCL_REQUIRES(_CCCL_TRAIT(is_nothrow_constructible, _T1, _Args...))
   static _LIBCUDACXX_HIDE_FROM_ABI _CCCL_CONSTEXPR_CXX20 void
@@ -445,6 +457,7 @@ struct __expected_storage : __expected_destruct<_Tp, _Err>
     _LIBCUDACXX_CONSTRUCT_AT(__newval, _CUDA_VSTD::forward<_Args>(__args)...);
   }
 
+  _CCCL_EXEC_CHECK_DISABLE
   _CCCL_TEMPLATE(class _T1, class _T2, class... _Args)
   _CCCL_REQUIRES(
     (!_CCCL_TRAIT(is_nothrow_constructible, _T1, _Args...)) _CCCL_AND _CCCL_TRAIT(is_nothrow_move_constructible, _T1))
@@ -456,6 +469,7 @@ struct __expected_storage : __expected_destruct<_Tp, _Err>
     _LIBCUDACXX_CONSTRUCT_AT(__newval, _CUDA_VSTD::move(__tmp));
   }
 
+  _CCCL_EXEC_CHECK_DISABLE
   _CCCL_TEMPLATE(class _T1, class _T2, class... _Args)
   _CCCL_REQUIRES(
     (!_CCCL_TRAIT(is_nothrow_constructible, _T1, _Args...)) _CCCL_AND(!_CCCL_TRAIT(is_nothrow_move_constructible, _T1)))
@@ -475,6 +489,7 @@ struct __expected_storage : __expected_destruct<_Tp, _Err>
     __trans.__complete();
   }
 
+  _CCCL_EXEC_CHECK_DISABLE
   _CCCL_TEMPLATE(class _Err2 = _Err)
   _CCCL_REQUIRES(_CCCL_TRAIT(is_nothrow_move_constructible, _Err2))
   static _LIBCUDACXX_HIDE_FROM_ABI _CCCL_CONSTEXPR_CXX20 void
@@ -493,6 +508,7 @@ struct __expected_storage : __expected_destruct<_Tp, _Err>
     __with_err.__has_val_ = true;
   }
 
+  _CCCL_EXEC_CHECK_DISABLE
   _CCCL_TEMPLATE(class _Err2 = _Err)
   _CCCL_REQUIRES((!_CCCL_TRAIT(is_nothrow_move_constructible, _Err2)))
   static _LIBCUDACXX_HIDE_FROM_ABI _CCCL_CONSTEXPR_CXX20 void
@@ -653,6 +669,7 @@ struct __expected_copy_assign<_Tp, _Err, __smf_availability::__available> : __ex
   _CCCL_HIDE_FROM_ABI __expected_copy_assign(const __expected_copy_assign&) = default;
   _CCCL_HIDE_FROM_ABI __expected_copy_assign(__expected_copy_assign&&)      = default;
 
+  _CCCL_EXEC_CHECK_DISABLE
   _LIBCUDACXX_HIDE_FROM_ABI _CCCL_CONSTEXPR_CXX20 __expected_copy_assign&
   operator=(const __expected_copy_assign& __other) noexcept(
     _CCCL_TRAIT(is_nothrow_copy_assignable, _Tp) && _CCCL_TRAIT(is_nothrow_copy_constructible, _Tp)
@@ -917,6 +934,7 @@ struct __expected_storage<void, _Err> : __expected_destruct<void, _Err>
 {
   _LIBCUDACXX_DELEGATE_CONSTRUCTORS(__expected_storage, __expected_destruct, void, _Err);
 
+  _CCCL_EXEC_CHECK_DISABLE
   static _LIBCUDACXX_HIDE_FROM_ABI _CCCL_CONSTEXPR_CXX20 void __swap_val_unex_impl(
     __expected_storage& __with_val,
     __expected_storage& __with_err) noexcept(_CCCL_TRAIT(is_nothrow_move_constructible, _Err))
diff --git a/libcudacxx/include/cuda/std/__expected/unexpected.h b/libcudacxx/include/cuda/std/__expected/unexpected.h
index 0f8f3784374..0da94402a85 100644
--- a/libcudacxx/include/cuda/std/__expected/unexpected.h
+++ b/libcudacxx/include/cuda/std/__expected/unexpected.h
@@ -73,6 +73,7 @@ class unexpected
   _CCCL_HIDE_FROM_ABI unexpected(const unexpected&) = default;
   _CCCL_HIDE_FROM_ABI unexpected(unexpected&&)      = default;
 
+  _CCCL_EXEC_CHECK_DISABLE
   _CCCL_TEMPLATE(class _Error = _Err)
   _CCCL_REQUIRES((!_CCCL_TRAIT(is_same, remove_cvref_t<_Error>, unexpected)
                   && !_CCCL_TRAIT(is_same, remove_cvref_t<_Error>, in_place_t)
@@ -82,6 +83,7 @@ class unexpected
       : __unex_(_CUDA_VSTD::forward<_Error>(__error))
   {}
 
+  _CCCL_EXEC_CHECK_DISABLE
   _CCCL_TEMPLATE(class... _Args)
   _CCCL_REQUIRES(_CCCL_TRAIT(is_constructible, _Err, _Args...))
   _LIBCUDACXX_HIDE_FROM_ABI constexpr explicit unexpected(in_place_t, _Args&&... __args) noexcept(
@@ -89,6 +91,7 @@ class unexpected
       : __unex_(_CUDA_VSTD::forward<_Args>(__args)...)
   {}
 
+  _CCCL_EXEC_CHECK_DISABLE
   _CCCL_TEMPLATE(class _Up, class... _Args)
   _CCCL_REQUIRES(_CCCL_TRAIT(is_constructible, _Err, initializer_list<_Up>&, _Args...))
   _LIBCUDACXX_HIDE_FROM_ABI constexpr explicit unexpected(
@@ -123,6 +126,7 @@ class unexpected
   }
 
   // [expected.un.swap]
+  _CCCL_EXEC_CHECK_DISABLE
   _LIBCUDACXX_HIDE_FROM_ABI constexpr void swap(unexpected& __other) noexcept(_CCCL_TRAIT(is_nothrow_swappable, _Err))
   {
     static_assert(_CCCL_TRAIT(is_swappable, _Err), "E must be swappable");
@@ -130,6 +134,7 @@ class unexpected
     swap(__unex_, __other.__unex_);
   }
 
+  _CCCL_EXEC_CHECK_DISABLE
   _CCCL_TEMPLATE(class _Err2 = _Err)
   _CCCL_REQUIRES(_CCCL_TRAIT(is_swappable, _Err2))
   friend _LIBCUDACXX_HIDE_FROM_ABI constexpr void
@@ -140,6 +145,7 @@ class unexpected
   }
 
   // [expected.un.eq]
+  _CCCL_EXEC_CHECK_DISABLE
   template <class _UErr>
   _CCCL_NODISCARD_FRIEND _LIBCUDACXX_HIDE_FROM_ABI constexpr bool
   operator==(const unexpected& __lhs,
@@ -148,6 +154,7 @@ class unexpected
     return __lhs.error() == __rhs.error();
   }
 #  if _CCCL_STD_VER < 2020
+  _CCCL_EXEC_CHECK_DISABLE
   template <class _UErr>
   _CCCL_NODISCARD_FRIEND _LIBCUDACXX_HIDE_FROM_ABI constexpr bool
   operator!=(const unexpected& __lhs,
diff --git a/libcudacxx/include/cuda/std/__memory/construct_at.h b/libcudacxx/include/cuda/std/__memory/construct_at.h
index bc231cd27d7..a78314c6479 100644
--- a/libcudacxx/include/cuda/std/__memory/construct_at.h
+++ b/libcudacxx/include/cuda/std/__memory/construct_at.h
@@ -50,6 +50,7 @@
 #  ifndef __cpp_lib_constexpr_dynamic_alloc
 namespace std
 {
+_CCCL_EXEC_CHECK_DISABLE
 template <class _Tp,
           class... _Args,
           class = decltype(::new(_CUDA_VSTD::declval<void*>()) _Tp(_CUDA_VSTD::declval<_Args>()...))>
diff --git a/libcudacxx/include/cuda/std/__utility/pair.h b/libcudacxx/include/cuda/std/__utility/pair.h
index e725cf4b001..e8678f58767 100644
--- a/libcudacxx/include/cuda/std/__utility/pair.h
+++ b/libcudacxx/include/cuda/std/__utility/pair.h
@@ -124,6 +124,7 @@ struct __pair_base
   _T1 first;
   _T2 second;
 
+  _CCCL_EXEC_CHECK_DISABLE
   template <class _Constraints                                               = __pair_constraints<_T1, _T2>,
             enable_if_t<_Constraints::__explicit_default_constructible, int> = 0>
   _LIBCUDACXX_HIDE_FROM_ABI explicit constexpr __pair_base() noexcept(
@@ -132,6 +133,7 @@ struct __pair_base
       , second()
   {}
 
+  _CCCL_EXEC_CHECK_DISABLE
   template <class _Constraints                                               = __pair_constraints<_T1, _T2>,
             enable_if_t<_Constraints::__implicit_default_constructible, int> = 0>
   _LIBCUDACXX_HIDE_FROM_ABI constexpr __pair_base() noexcept(
@@ -140,6 +142,7 @@ struct __pair_base
       , second()
   {}
 
+  _CCCL_EXEC_CHECK_DISABLE
   template <class _U1, class _U2>
   _LIBCUDACXX_HIDE_FROM_ABI constexpr __pair_base(_U1&& __t1, _U2&& __t2) noexcept(
     _CCCL_TRAIT(is_nothrow_constructible, _T1, _U1) && _CCCL_TRAIT(is_nothrow_constructible, _T2, _U2))
@@ -163,6 +166,7 @@ struct __pair_base<_T1, _T2, true>
   _T1 first;
   _T2 second;
 
+  _CCCL_EXEC_CHECK_DISABLE
   template <class _Constraints                                               = __pair_constraints<_T1, _T2>,
             enable_if_t<_Constraints::__explicit_default_constructible, int> = 0>
   _LIBCUDACXX_HIDE_FROM_ABI explicit constexpr __pair_base() noexcept(
@@ -171,6 +175,7 @@ struct __pair_base<_T1, _T2, true>
       , second()
   {}
 
+  _CCCL_EXEC_CHECK_DISABLE
   template <class _Constraints                                               = __pair_constraints<_T1, _T2>,
             enable_if_t<_Constraints::__implicit_default_constructible, int> = 0>
   _LIBCUDACXX_HIDE_FROM_ABI constexpr __pair_base() noexcept(
@@ -179,10 +184,13 @@ struct __pair_base<_T1, _T2, true>
       , second()
   {}
 
+  _CCCL_EXEC_CHECK_DISABLE
   _CCCL_HIDE_FROM_ABI constexpr __pair_base(const __pair_base&) = default;
-  _CCCL_HIDE_FROM_ABI constexpr __pair_base(__pair_base&&)      = default;
+  _CCCL_EXEC_CHECK_DISABLE
+  _CCCL_HIDE_FROM_ABI constexpr __pair_base(__pair_base&&) = default;
 
   // We need to ensure that a reference type, which would inhibit the implicit copy assignment still works
+  _CCCL_EXEC_CHECK_DISABLE
   _LIBCUDACXX_HIDE_FROM_ABI _CCCL_CONSTEXPR_CXX14 __pair_base& operator=(
     conditional_t<_CCCL_TRAIT(is_copy_assignable, _T1) && _CCCL_TRAIT(is_copy_assignable, _T2), __pair_base, __nat> const&
       __p) noexcept(_CCCL_TRAIT(is_nothrow_copy_assignable, _T1) && _CCCL_TRAIT(is_nothrow_copy_assignable, _T2))
@@ -193,6 +201,7 @@ struct __pair_base<_T1, _T2, true>
   }
 
   // We need to ensure that a reference type, which would inhibit the implicit move assignment still works
+  _CCCL_EXEC_CHECK_DISABLE
   _LIBCUDACXX_HIDE_FROM_ABI _CCCL_CONSTEXPR_CXX14 __pair_base& operator=(
     conditional_t<_CCCL_TRAIT(is_move_assignable, _T1) && _CCCL_TRAIT(is_move_assignable, _T2), __pair_base, __nat>&&
       __p) noexcept(_CCCL_TRAIT(is_nothrow_move_assignable, _T1) && _CCCL_TRAIT(is_nothrow_move_assignable, _T2))
@@ -202,6 +211,7 @@ struct __pair_base<_T1, _T2, true>
     return *this;
   }
 
+  _CCCL_EXEC_CHECK_DISABLE
   template <class _U1, class _U2>
   _LIBCUDACXX_HIDE_FROM_ABI constexpr __pair_base(_U1&& __t1, _U2&& __t2) noexcept(
     _CCCL_TRAIT(is_nothrow_constructible, _T1, _U1) && _CCCL_TRAIT(is_nothrow_constructible, _T2, _U2))
@@ -532,6 +542,7 @@ _CCCL_HOST_DEVICE pair(_T1, _T2) -> pair<_T1, _T2>;
 
 // [pairs.spec], specialized algorithms
 
+_CCCL_EXEC_CHECK_DISABLE
 template <class _T1, class _T2>
 _LIBCUDACXX_HIDE_FROM_ABI _CCCL_CONSTEXPR_CXX14 bool operator==(const pair<_T1, _T2>& __x, const pair<_T1, _T2>& __y)
 {
@@ -540,6 +551,7 @@ _LIBCUDACXX_HIDE_FROM_ABI _CCCL_CONSTEXPR_CXX14 bool operator==(const pair<_T1,
 
 #ifndef _LIBCUDACXX_HAS_NO_SPACESHIP_OPERATOR
 
+_CCCL_EXEC_CHECK_DISABLE
 template <class _T1, class _T2>
 _LIBCUDACXX_HIDE_FROM_ABI constexpr common_comparison_category_t<__synth_three_way_result<_T1>,
                                                                  __synth_three_way_result<_T2>>
@@ -554,30 +566,35 @@ operator<=>(const pair<_T1, _T2>& __x, const pair<_T1, _T2>& __y)
 
 #else // _LIBCUDACXX_HAS_NO_SPACESHIP_OPERATOR
 
+_CCCL_EXEC_CHECK_DISABLE
 template <class _T1, class _T2>
 _LIBCUDACXX_HIDE_FROM_ABI _CCCL_CONSTEXPR_CXX14 bool operator!=(const pair<_T1, _T2>& __x, const pair<_T1, _T2>& __y)
 {
   return !(__x == __y);
 }
 
+_CCCL_EXEC_CHECK_DISABLE
 template <class _T1, class _T2>
 _LIBCUDACXX_HIDE_FROM_ABI _CCCL_CONSTEXPR_CXX14 bool operator<(const pair<_T1, _T2>& __x, const pair<_T1, _T2>& __y)
 {
   return __x.first < __y.first || (!(__y.first < __x.first) && __x.second < __y.second);
 }
 
+_CCCL_EXEC_CHECK_DISABLE
 template <class _T1, class _T2>
 _LIBCUDACXX_HIDE_FROM_ABI _CCCL_CONSTEXPR_CXX14 bool operator>(const pair<_T1, _T2>& __x, const pair<_T1, _T2>& __y)
 {
   return __y < __x;
 }
 
+_CCCL_EXEC_CHECK_DISABLE
 template <class _T1, class _T2>
 _LIBCUDACXX_HIDE_FROM_ABI _CCCL_CONSTEXPR_CXX14 bool operator>=(const pair<_T1, _T2>& __x, const pair<_T1, _T2>& __y)
 {
   return !(__x < __y);
 }
 
+_CCCL_EXEC_CHECK_DISABLE
 template <class _T1, class _T2>
 _LIBCUDACXX_HIDE_FROM_ABI _CCCL_CONSTEXPR_CXX14 bool operator<=(const pair<_T1, _T2>& __x, const pair<_T1, _T2>& __y)
 {
diff --git a/libcudacxx/include/cuda/std/detail/libcxx/include/optional b/libcudacxx/include/cuda/std/detail/libcxx/include/optional
index 04f056c91d3..d61ce254f4d 100644
--- a/libcudacxx/include/cuda/std/detail/libcxx/include/optional
+++ b/libcudacxx/include/cuda/std/detail/libcxx/include/optional
@@ -296,12 +296,14 @@ struct __optional_destruct_base<_Tp, false>
       , __engaged_(false)
   {}
 
+  _CCCL_EXEC_CHECK_DISABLE
   template <class... _Args>
   _LIBCUDACXX_HIDE_FROM_ABI constexpr explicit __optional_destruct_base(in_place_t, _Args&&... __args)
       : __val_(_CUDA_VSTD::forward<_Args>(__args)...)
       , __engaged_(true)
   {}
 
+  _CCCL_EXEC_CHECK_DISABLE
   template <class _Fp, class... _Args>
   _LIBCUDACXX_HIDE_FROM_ABI constexpr __optional_destruct_base(
     __optional_construct_from_invoke_tag, _Fp&& __f, _Args&&... __args)
@@ -338,12 +340,14 @@ struct __optional_destruct_base<_Tp, true>
       , __engaged_(false)
   {}
 
+  _CCCL_EXEC_CHECK_DISABLE
   template <class... _Args>
   _LIBCUDACXX_HIDE_FROM_ABI constexpr explicit __optional_destruct_base(in_place_t, _Args&&... __args)
       : __val_(_CUDA_VSTD::forward<_Args>(__args)...)
       , __engaged_(true)
   {}
 
+  _CCCL_EXEC_CHECK_DISABLE
   template <class _Fp, class... _Args>
   _LIBCUDACXX_HIDE_FROM_ABI constexpr __optional_destruct_base(
     __optional_construct_from_invoke_tag, _Fp&& __f, _Args&&... __args)
@@ -389,6 +393,7 @@ struct __optional_storage_base : __optional_destruct_base<_Tp>
     return _CUDA_VSTD::move(this->__val_);
   }
 
+  _CCCL_EXEC_CHECK_DISABLE
   template <class... _Args>
   _LIBCUDACXX_HIDE_FROM_ABI _CCCL_CONSTEXPR_CXX20 void __construct(_Args&&... __args)
   {
@@ -410,6 +415,7 @@ struct __optional_storage_base : __optional_destruct_base<_Tp>
     }
   }
 
+  _CCCL_EXEC_CHECK_DISABLE
   template <class _That>
   _LIBCUDACXX_HIDE_FROM_ABI constexpr void __assign_from(_That&& __opt)
   {
@@ -811,6 +817,7 @@ public:
     return this->__get();
   }
 
+  _CCCL_EXEC_CHECK_DISABLE
   _LIBCUDACXX_HIDE_FROM_ABI constexpr void swap(optional& __opt) noexcept(
     _CCCL_TRAIT(is_nothrow_move_constructible, value_type) && _CCCL_TRAIT(is_nothrow_swappable, value_type))
   {
@@ -1088,6 +1095,7 @@ _CCCL_HOST_DEVICE optional(_Tp) -> optional<_Tp>;
 #  endif // _CCCL_NO_DEDUCTION_GUIDES
 
 // Comparisons between optionals
+_CCCL_EXEC_CHECK_DISABLE
 template <class _Tp, class _Up>
 _LIBCUDACXX_HIDE_FROM_ABI constexpr enable_if_t<
   _CCCL_TRAIT(is_convertible, decltype(declval<const _Tp&>() == declval<const _Up&>()), bool),
@@ -1105,6 +1113,7 @@ operator==(const optional<_Tp>& __x, const optional<_Up>& __y)
   return *__x == *__y;
 }
 
+_CCCL_EXEC_CHECK_DISABLE
 template <class _Tp, class _Up>
 _LIBCUDACXX_HIDE_FROM_ABI constexpr enable_if_t<
   _CCCL_TRAIT(is_convertible, decltype(declval<const _Tp&>() != declval<const _Up&>()), bool),
@@ -1122,6 +1131,7 @@ operator!=(const optional<_Tp>& __x, const optional<_Up>& __y)
   return *__x != *__y;
 }
 
+_CCCL_EXEC_CHECK_DISABLE
 template <class _Tp, class _Up>
 _LIBCUDACXX_HIDE_FROM_ABI constexpr enable_if_t<
   _CCCL_TRAIT(is_convertible, decltype(declval<const _Tp&>() < declval<const _Up&>()), bool),
@@ -1139,6 +1149,7 @@ operator<(const optional<_Tp>& __x, const optional<_Up>& __y)
   return *__x < *__y;
 }
 
+_CCCL_EXEC_CHECK_DISABLE
 template <class _Tp, class _Up>
 _LIBCUDACXX_HIDE_FROM_ABI constexpr enable_if_t<
   _CCCL_TRAIT(is_convertible, decltype(declval<const _Tp&>() > declval<const _Up&>()), bool),
@@ -1156,6 +1167,7 @@ operator>(const optional<_Tp>& __x, const optional<_Up>& __y)
   return *__x > *__y;
 }
 
+_CCCL_EXEC_CHECK_DISABLE
 template <class _Tp, class _Up>
 _LIBCUDACXX_HIDE_FROM_ABI constexpr enable_if_t<
   _CCCL_TRAIT(is_convertible, decltype(declval<const _Tp&>() <= declval<const _Up&>()), bool),
@@ -1173,6 +1185,7 @@ operator<=(const optional<_Tp>& __x, const optional<_Up>& __y)
   return *__x <= *__y;
 }
 
+_CCCL_EXEC_CHECK_DISABLE
 template <class _Tp, class _Up>
 _LIBCUDACXX_HIDE_FROM_ABI constexpr enable_if_t<
   _CCCL_TRAIT(is_convertible, decltype(declval<const _Tp&>() >= declval<const _Up&>()), bool),
@@ -1264,6 +1277,7 @@ _LIBCUDACXX_HIDE_FROM_ABI constexpr bool operator>=(nullopt_t, const optional<_T
 }
 
 // Comparisons with T
+_CCCL_EXEC_CHECK_DISABLE
 template <class _Tp, class _Up>
 _LIBCUDACXX_HIDE_FROM_ABI constexpr enable_if_t<
   _CCCL_TRAIT(is_convertible, decltype(declval<const _Tp&>() == declval<const _Up&>()), bool),
@@ -1273,6 +1287,7 @@ operator==(const optional<_Tp>& __x, const _Up& __v)
   return static_cast<bool>(__x) ? *__x == __v : false;
 }
 
+_CCCL_EXEC_CHECK_DISABLE
 template <class _Tp, class _Up>
 _LIBCUDACXX_HIDE_FROM_ABI constexpr enable_if_t<
   _CCCL_TRAIT(is_convertible, decltype(declval<const _Tp&>() == declval<const _Up&>()), bool),
@@ -1282,6 +1297,7 @@ operator==(const _Tp& __v, const optional<_Up>& __x)
   return static_cast<bool>(__x) ? __v == *__x : false;
 }
 
+_CCCL_EXEC_CHECK_DISABLE
 template <class _Tp, class _Up>
 _LIBCUDACXX_HIDE_FROM_ABI constexpr enable_if_t<
   _CCCL_TRAIT(is_convertible, decltype(declval<const _Tp&>() != declval<const _Up&>()), bool),
@@ -1291,6 +1307,7 @@ operator!=(const optional<_Tp>& __x, const _Up& __v)
   return static_cast<bool>(__x) ? *__x != __v : true;
 }
 
+_CCCL_EXEC_CHECK_DISABLE
 template <class _Tp, class _Up>
 _LIBCUDACXX_HIDE_FROM_ABI constexpr enable_if_t<
   _CCCL_TRAIT(is_convertible, decltype(declval<const _Tp&>() != declval<const _Up&>()), bool),
@@ -1300,6 +1317,7 @@ operator!=(const _Tp& __v, const optional<_Up>& __x)
   return static_cast<bool>(__x) ? __v != *__x : true;
 }
 
+_CCCL_EXEC_CHECK_DISABLE
 template <class _Tp, class _Up>
 _LIBCUDACXX_HIDE_FROM_ABI constexpr enable_if_t<
   _CCCL_TRAIT(is_convertible, decltype(declval<const _Tp&>() < declval<const _Up&>()), bool),
@@ -1309,6 +1327,7 @@ operator<(const optional<_Tp>& __x, const _Up& __v)
   return static_cast<bool>(__x) ? *__x < __v : true;
 }
 
+_CCCL_EXEC_CHECK_DISABLE
 template <class _Tp, class _Up>
 _LIBCUDACXX_HIDE_FROM_ABI constexpr enable_if_t<
   _CCCL_TRAIT(is_convertible, decltype(declval<const _Tp&>() < declval<const _Up&>()), bool),
@@ -1318,6 +1337,7 @@ operator<(const _Tp& __v, const optional<_Up>& __x)
   return static_cast<bool>(__x) ? __v < *__x : false;
 }
 
+_CCCL_EXEC_CHECK_DISABLE
 template <class _Tp, class _Up>
 _LIBCUDACXX_HIDE_FROM_ABI constexpr enable_if_t<
   _CCCL_TRAIT(is_convertible, decltype(declval<const _Tp&>() <= declval<const _Up&>()), bool),
@@ -1327,6 +1347,7 @@ operator<=(const optional<_Tp>& __x, const _Up& __v)
   return static_cast<bool>(__x) ? *__x <= __v : true;
 }
 
+_CCCL_EXEC_CHECK_DISABLE
 template <class _Tp, class _Up>
 _LIBCUDACXX_HIDE_FROM_ABI constexpr enable_if_t<
   _CCCL_TRAIT(is_convertible, decltype(declval<const _Tp&>() <= declval<const _Up&>()), bool),
@@ -1336,6 +1357,7 @@ operator<=(const _Tp& __v, const optional<_Up>& __x)
   return static_cast<bool>(__x) ? __v <= *__x : false;
 }
 
+_CCCL_EXEC_CHECK_DISABLE
 template <class _Tp, class _Up>
 _LIBCUDACXX_HIDE_FROM_ABI constexpr enable_if_t<
   _CCCL_TRAIT(is_convertible, decltype(declval<const _Tp&>() > declval<const _Up&>()), bool),
@@ -1345,6 +1367,7 @@ operator>(const optional<_Tp>& __x, const _Up& __v)
   return static_cast<bool>(__x) ? *__x > __v : false;
 }
 
+_CCCL_EXEC_CHECK_DISABLE
 template <class _Tp, class _Up>
 _LIBCUDACXX_HIDE_FROM_ABI constexpr enable_if_t<
   _CCCL_TRAIT(is_convertible, decltype(declval<const _Tp&>() > declval<const _Up&>()), bool),
@@ -1354,6 +1377,7 @@ operator>(const _Tp& __v, const optional<_Up>& __x)
   return static_cast<bool>(__x) ? __v > *__x : true;
 }
 
+_CCCL_EXEC_CHECK_DISABLE
 template <class _Tp, class _Up>
 _LIBCUDACXX_HIDE_FROM_ABI constexpr enable_if_t<
   _CCCL_TRAIT(is_convertible, decltype(declval<const _Tp&>() >= declval<const _Up&>()), bool),
@@ -1363,6 +1387,7 @@ operator>=(const optional<_Tp>& __x, const _Up& __v)
   return static_cast<bool>(__x) ? *__x >= __v : false;
 }
 
+_CCCL_EXEC_CHECK_DISABLE
 template <class _Tp, class _Up>
 _LIBCUDACXX_HIDE_FROM_ABI constexpr enable_if_t<
   _CCCL_TRAIT(is_convertible, decltype(declval<const _Tp&>() >= declval<const _Up&>()), bool),
diff --git a/libcudacxx/include/cuda/std/detail/libcxx/include/tuple b/libcudacxx/include/cuda/std/detail/libcxx/include/tuple
index aa2fdeaa368..6ff1039e61b 100644
--- a/libcudacxx/include/cuda/std/detail/libcxx/include/tuple
+++ b/libcudacxx/include/cuda/std/detail/libcxx/include/tuple
@@ -1124,6 +1124,7 @@ _LIBCUDACXX_HIDE_FROM_ABI _CCCL_CONSTEXPR_CXX14 tuple<_Tp&&...> forward_as_tuple
 template <size_t _Ip>
 struct __tuple_equal
 {
+  _CCCL_EXEC_CHECK_DISABLE
   template <class _Tp, class _Up>
   _LIBCUDACXX_HIDE_FROM_ABI _CCCL_CONSTEXPR_CXX14 bool operator()(const _Tp& __x, const _Up& __y)
   {
@@ -1157,6 +1158,7 @@ _LIBCUDACXX_HIDE_FROM_ABI _CCCL_CONSTEXPR_CXX14 bool operator!=(const tuple<_Tp.
 template <size_t _Ip>
 struct __tuple_less
 {
+  _CCCL_EXEC_CHECK_DISABLE
   template <class _Tp, class _Up>
   _LIBCUDACXX_HIDE_FROM_ABI _CCCL_CONSTEXPR_CXX14 bool operator()(const _Tp& __x, const _Up& __y)
   {
diff --git a/libcudacxx/include/cuda/std/detail/libcxx/include/variant b/libcudacxx/include/cuda/std/detail/libcxx/include/variant
index 0f6ec9d29fc..af1f7ba85ad 100644
--- a/libcudacxx/include/cuda/std/detail/libcxx/include/variant
+++ b/libcudacxx/include/cuda/std/detail/libcxx/include/variant
@@ -255,6 +255,7 @@ C++20
 #include <cuda/std/__utility/monostate.h>
 #include <cuda/std/__utility/move.h>
 #include <cuda/std/__utility/swap.h>
+#include <cuda/std/__utility/unreachable.h>
 #include <cuda/std/cstddef>
 #include <cuda/std/initializer_list>
 #include <cuda/std/tuple>
@@ -744,10 +745,22 @@ struct _CCCL_TYPE_VISIBILITY_DEFAULT __alt
 {
   using __value_type = _Tp;
 
+  _CCCL_EXEC_CHECK_DISABLE
   template <class... _Args>
   _LIBCUDACXX_HIDE_FROM_ABI explicit constexpr __alt(in_place_t, _Args&&... __args)
       : __value(_CUDA_VSTD::forward<_Args>(__args)...)
   {}
+  _CCCL_EXEC_CHECK_DISABLE
+  constexpr __alt(const __alt&) = default;
+  _CCCL_EXEC_CHECK_DISABLE
+  constexpr __alt(__alt&&) = default;
+  _CCCL_EXEC_CHECK_DISABLE
+  constexpr __alt& operator=(const __alt&) = default;
+  _CCCL_EXEC_CHECK_DISABLE
+  constexpr __alt& operator=(__alt&&) = default;
+
+  _CCCL_EXEC_CHECK_DISABLE
+  ~__alt() = default;
 
   __value_type __value;
 };
@@ -906,6 +919,7 @@ class _CCCL_TYPE_VISIBILITY_DEFAULT __dtor<__traits<_Types...>, _Trait::_Availab
 {
   struct __visitor
   {
+    _CCCL_EXEC_CHECK_DISABLE
     template <class _Alt>
     _LIBCUDACXX_HIDE_FROM_ABI void operator()(_Alt& __alt) const noexcept
     {
@@ -1148,6 +1162,7 @@ public:
   }
 
 protected:
+  _CCCL_EXEC_CHECK_DISABLE
   template <
     size_t _Ip,
     class _Tp,
@@ -1166,6 +1181,7 @@ protected:
     }
   }
 
+  _CCCL_EXEC_CHECK_DISABLE
   template <
     size_t _Ip,
     class _Tp,
@@ -1896,7 +1912,11 @@ private:
       return __op(_CUDA_VSTD::get<0>(__lhs), _CUDA_VSTD::get<0>(__rhs));
     }
     // We already checked that every variant has a value, so we should never reach this line
+#  if _CCCL_COMPILER(MSVC) // MSVC needs this to be wrapped in a function or it will error
+    _CUDA_VSTD::unreachable();
+#  else // ^^^ _CCCL_COMPILER(MSVC) ^^^ / vvv !_CCCL_COMPILER(MSVC) vvv
     _CCCL_UNREACHABLE();
+#  endif // !_CCCL_COMPILER(MSVC)
   }
 };
 
diff --git a/libcudacxx/test/libcudacxx/cuda/utilities/expected/device_only_types.pass.cpp b/libcudacxx/test/libcudacxx/cuda/utilities/expected/device_only_types.pass.cpp
new file mode 100644
index 00000000000..ba972e02d3a
--- /dev/null
+++ b/libcudacxx/test/libcudacxx/cuda/utilities/expected/device_only_types.pass.cpp
@@ -0,0 +1,201 @@
+//===----------------------------------------------------------------------===//
+//
+// Part of the libcu++ Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+// SPDX-FileCopyrightText: Copyright (c) 2025 NVIDIA CORPORATION & AFFILIATES.
+//
+//===----------------------------------------------------------------------===//
+
+// We cannot suppress execution checks in cuda::std::construct_at
+// XFAIL: c++20 && !nvrtc && nvcc && !msvc
+// UNSUPPORTED: clang-14
+
+#include <cuda/std/cassert>
+#include <cuda/std/expected>
+#include <cuda/std/initializer_list>
+
+#include "host_device_types.h"
+#include "test_macros.h"
+
+__device__ void test()
+{
+  using expected = cuda::std::expected<device_only_type, device_only_type>;
+  { // default construction
+    expected default_constructed{};
+    assert(default_constructed.has_value());
+    assert(*default_constructed == 0);
+  }
+
+  { // in_place zero initialization
+    expected in_place_zero_initialization{cuda::std::in_place};
+    assert(in_place_zero_initialization.has_value());
+    assert(*in_place_zero_initialization == 0);
+  }
+
+  { // in_place initialization
+    expected in_place_initialization{cuda::std::in_place, 42};
+    assert(in_place_initialization.has_value());
+    assert(*in_place_initialization == 42);
+  }
+
+  { // initializer_list initialization
+    expected init_list_initialization{cuda::std::in_place, cuda::std::initializer_list<int>{}, 42};
+    assert(init_list_initialization.has_value());
+    assert(*init_list_initialization == 42);
+  }
+
+  { // unexpect zero initialization
+    expected in_place_zero_initialization{cuda::std::unexpect};
+    assert(!in_place_zero_initialization.has_value());
+    assert(in_place_zero_initialization.error() == 0);
+  }
+
+  { // unexpect initialization
+    expected in_place_initialization{cuda::std::unexpect, 42};
+    assert(!in_place_initialization.has_value());
+    assert(in_place_initialization.error() == 42);
+  }
+
+  { // initializer_list initialization
+    expected init_list_initialization{cuda::std::unexpect, cuda::std::initializer_list<int>{}, 42};
+    assert(!init_list_initialization.has_value());
+    assert(init_list_initialization.error() == 42);
+  }
+
+  { // value initialization
+    expected value_initialization{42};
+    assert(value_initialization.has_value());
+    assert(*value_initialization == 42);
+  }
+
+  { // copy construction
+    expected input{42};
+    expected dest{input};
+    assert(dest.has_value());
+    assert(*dest == 42);
+  }
+
+  { // move construction
+    expected input{42};
+    expected dest{cuda::std::move(input)};
+    assert(dest.has_value());
+    assert(*dest == 42);
+  }
+
+  { // assignment, value to value
+    expected input{42};
+    expected dest{1337};
+    dest = input;
+    assert(dest.has_value());
+    assert(*dest == 42);
+  }
+
+  { // assignment, value to empty
+    expected input{42};
+    expected dest{};
+    dest = input;
+    assert(dest.has_value());
+    assert(*dest == 42);
+  }
+
+  { // assignment, empty to value
+    expected input{};
+    expected dest{1337};
+    dest = input;
+    assert(dest.has_value());
+    assert(*dest == 0);
+  }
+
+  { // assignment, empty to empty
+    expected input{};
+    expected dest{};
+    dest = input;
+    assert(dest.has_value());
+    assert(*dest == 0);
+  }
+
+  { // assignment, error to value
+    expected input{cuda::std::unexpect, 42};
+    expected dest{1337};
+    dest = input;
+    assert(!dest.has_value());
+    assert(dest.error() == 42);
+  }
+
+  { // assignment, value to error
+    expected input{42};
+    expected dest{cuda::std::unexpect, 1337};
+    dest = input;
+    assert(dest.has_value());
+    assert(*dest == 42);
+  }
+
+  { // assignment, error to error
+    expected input{cuda::std::unexpect, 42};
+    expected dest{cuda::std::unexpect, 1337};
+    dest = input;
+    assert(!dest.has_value());
+    assert(dest.error() == 42);
+  }
+
+  { // comparison with expected with value
+    expected lhs{42};
+    expected rhs{1337};
+    assert(!(lhs == rhs));
+    assert(lhs != rhs);
+  }
+
+  { // comparison with expected with error
+    expected lhs{cuda::std::unexpect, 42};
+    expected rhs{cuda::std::unexpect, 1337};
+    assert(!(lhs == rhs));
+    assert(lhs != rhs);
+  }
+
+  { // comparison with type and value
+    expected expect{42};
+    assert(expect == device_only_type{42});
+    assert(device_only_type{42} == expect);
+    assert(expect != device_only_type{1337});
+    assert(device_only_type{1337} != expect);
+  }
+
+  { // comparison with type and error
+    expected expect{cuda::std::unexpect, 42};
+    assert(expect == cuda::std::unexpected<device_only_type>{42});
+    assert(cuda::std::unexpected<device_only_type>{42} == expect);
+    assert(expect != cuda::std::unexpected<device_only_type>{1337});
+    assert(cuda::std::unexpected<device_only_type>{1337} != expect);
+  }
+
+  { // swap
+    expected lhs{42};
+    expected rhs{1337};
+    lhs.swap(rhs);
+    assert(*lhs == 1337);
+    assert(*rhs == 42);
+
+    swap(lhs, rhs);
+    assert(*lhs == 42);
+    assert(*rhs == 1337);
+  }
+
+  { // swap cross error
+    expected lhs{42};
+    expected rhs{cuda::std::unexpect, 1337};
+    lhs.swap(rhs);
+    assert(lhs.error() == 1337);
+    assert(*rhs == 42);
+
+    swap(lhs, rhs);
+    assert(*lhs == 42);
+    assert(rhs.error() == 1337);
+  }
+}
+
+int main(int arg, char** argv)
+{
+  NV_IF_TARGET(NV_IS_DEVICE, (test();))
+  return 0;
+}
diff --git a/libcudacxx/test/libcudacxx/cuda/utilities/expected/host_only_types.pass.cpp b/libcudacxx/test/libcudacxx/cuda/utilities/expected/host_only_types.pass.cpp
new file mode 100644
index 00000000000..282288b7be8
--- /dev/null
+++ b/libcudacxx/test/libcudacxx/cuda/utilities/expected/host_only_types.pass.cpp
@@ -0,0 +1,199 @@
+//===----------------------------------------------------------------------===//
+//
+// Part of the libcu++ Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+// SPDX-FileCopyrightText: Copyright (c) 2025 NVIDIA CORPORATION & AFFILIATES.
+//
+//===----------------------------------------------------------------------===//
+
+// UNSUPPORTED: nvrtc
+
+#include <cuda/std/cassert>
+#include <cuda/std/expected>
+#include <cuda/std/initializer_list>
+
+#include "host_device_types.h"
+#include "test_macros.h"
+
+void test()
+{
+  using expected = cuda::std::expected<host_only_type, host_only_type>;
+  { // default construction
+    expected default_constructed{};
+    assert(default_constructed.has_value());
+    assert(*default_constructed == 0);
+  }
+
+  { // in_place zero initialization
+    expected in_place_zero_initialization{cuda::std::in_place};
+    assert(in_place_zero_initialization.has_value());
+    assert(*in_place_zero_initialization == 0);
+  }
+
+  { // in_place initialization
+    expected in_place_initialization{cuda::std::in_place, 42};
+    assert(in_place_initialization.has_value());
+    assert(*in_place_initialization == 42);
+  }
+
+  { // initializer_list initialization
+    expected init_list_initialization{cuda::std::in_place, cuda::std::initializer_list<int>{}, 42};
+    assert(init_list_initialization.has_value());
+    assert(*init_list_initialization == 42);
+  }
+
+  { // unexpect zero initialization
+    expected in_place_zero_initialization{cuda::std::unexpect};
+    assert(!in_place_zero_initialization.has_value());
+    assert(in_place_zero_initialization.error() == 0);
+  }
+
+  { // unexpect initialization
+    expected in_place_initialization{cuda::std::unexpect, 42};
+    assert(!in_place_initialization.has_value());
+    assert(in_place_initialization.error() == 42);
+  }
+
+  { // initializer_list initialization
+    expected init_list_initialization{cuda::std::unexpect, cuda::std::initializer_list<int>{}, 42};
+    assert(!init_list_initialization.has_value());
+    assert(init_list_initialization.error() == 42);
+  }
+
+  { // value initialization
+    expected value_initialization{42};
+    assert(value_initialization.has_value());
+    assert(*value_initialization == 42);
+  }
+
+  { // copy construction
+    expected input{42};
+    expected dest{input};
+    assert(dest.has_value());
+    assert(*dest == 42);
+  }
+
+  { // move construction
+    expected input{42};
+    expected dest{cuda::std::move(input)};
+    assert(dest.has_value());
+    assert(*dest == 42);
+  }
+
+  { // assignment, value to value
+    expected input{42};
+    expected dest{1337};
+    dest = input;
+    assert(dest.has_value());
+    assert(*dest == 42);
+  }
+
+  { // assignment, value to empty
+    expected input{42};
+    expected dest{};
+    dest = input;
+    assert(dest.has_value());
+    assert(*dest == 42);
+  }
+
+  { // assignment, empty to value
+    expected input{};
+    expected dest{1337};
+    dest = input;
+    assert(dest.has_value());
+    assert(*dest == 0);
+  }
+
+  { // assignment, empty to empty
+    expected input{};
+    expected dest{};
+    dest = input;
+    assert(dest.has_value());
+    assert(*dest == 0);
+  }
+
+  { // assignment, error to value
+    expected input{cuda::std::unexpect, 42};
+    expected dest{1337};
+    dest = input;
+    assert(!dest.has_value());
+    assert(dest.error() == 42);
+  }
+
+  { // assignment, value to error
+    expected input{42};
+    expected dest{cuda::std::unexpect, 1337};
+    dest = input;
+    assert(dest.has_value());
+    assert(*dest == 42);
+  }
+
+  { // assignment, error to error
+    expected input{cuda::std::unexpect, 42};
+    expected dest{cuda::std::unexpect, 1337};
+    dest = input;
+    assert(!dest.has_value());
+    assert(dest.error() == 42);
+  }
+
+  { // comparison with expected with value
+    expected lhs{42};
+    expected rhs{1337};
+    assert(!(lhs == rhs));
+    assert(lhs != rhs);
+  }
+
+  { // comparison with expected with error
+    expected lhs{cuda::std::unexpect, 42};
+    expected rhs{cuda::std::unexpect, 1337};
+    assert(!(lhs == rhs));
+    assert(lhs != rhs);
+  }
+
+  { // comparison with type and value
+    expected expect{42};
+    assert(expect == host_only_type{42});
+    assert(host_only_type{42} == expect);
+    assert(expect != host_only_type{1337});
+    assert(host_only_type{1337} != expect);
+  }
+
+  { // comparison with type and error
+    expected expect{cuda::std::unexpect, 42};
+    assert(expect == cuda::std::unexpected<host_only_type>{42});
+    assert(cuda::std::unexpected<host_only_type>{42} == expect);
+    assert(expect != cuda::std::unexpected<host_only_type>{1337});
+    assert(cuda::std::unexpected<host_only_type>{1337} != expect);
+  }
+
+  { // swap
+    expected lhs{42};
+    expected rhs{1337};
+    lhs.swap(rhs);
+    assert(*lhs == 1337);
+    assert(*rhs == 42);
+
+    swap(lhs, rhs);
+    assert(*lhs == 42);
+    assert(*rhs == 1337);
+  }
+
+  { // swap cross error
+    expected lhs{42};
+    expected rhs{cuda::std::unexpect, 1337};
+    lhs.swap(rhs);
+    assert(lhs.error() == 1337);
+    assert(*rhs == 42);
+
+    swap(lhs, rhs);
+    assert(*lhs == 42);
+    assert(rhs.error() == 1337);
+  }
+}
+
+int main(int arg, char** argv)
+{
+  NV_IF_TARGET(NV_IS_HOST, (test();))
+  return 0;
+}
diff --git a/libcudacxx/test/libcudacxx/cuda/utilities/optional/device_only_types.pass.cpp b/libcudacxx/test/libcudacxx/cuda/utilities/optional/device_only_types.pass.cpp
new file mode 100644
index 00000000000..766b6ae821c
--- /dev/null
+++ b/libcudacxx/test/libcudacxx/cuda/utilities/optional/device_only_types.pass.cpp
@@ -0,0 +1,136 @@
+//===----------------------------------------------------------------------===//
+//
+// Part of the libcu++ Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+// SPDX-FileCopyrightText: Copyright (c) 2025 NVIDIA CORPORATION & AFFILIATES.
+//
+//===----------------------------------------------------------------------===//
+
+// We cannot suppress execution checks in cuda::std::construct_at
+// XFAIL: c++20 && !nvrtc && nvcc && !msvc
+// UNSUPPORTED: clang-14
+
+#include <cuda/std/cassert>
+#include <cuda/std/optional>
+
+#include "host_device_types.h"
+#include "test_macros.h"
+
+__device__ void test()
+{
+  using optional = cuda::std::optional<device_only_type>;
+  { // default construction
+    optional default_constructed{};
+    assert(!default_constructed.has_value());
+  }
+
+  { // in_place zero initialization
+    optional in_place_zero_initialization{cuda::std::in_place};
+    assert(in_place_zero_initialization.has_value());
+    assert(*in_place_zero_initialization == 0);
+  }
+
+  { // in_place initialization
+    optional in_place_initialization{cuda::std::in_place, 42};
+    assert(in_place_initialization.has_value());
+    assert(*in_place_initialization == 42);
+  }
+
+  { // value initialization
+    optional value_initialization{42};
+    assert(value_initialization.has_value());
+    assert(*value_initialization == 42);
+  }
+
+  { // copy construction
+    optional input{42};
+    optional dest{input};
+    assert(dest.has_value());
+    assert(*dest == 42);
+  }
+
+  { // move construction
+    optional input{42};
+    optional dest{cuda::std::move(input)};
+    assert(dest.has_value());
+    assert(*dest == 42);
+  }
+
+  { // assignment, value to value
+    optional input{42};
+    optional dest{1337};
+    dest = input;
+    assert(dest.has_value());
+    assert(*dest == 42);
+  }
+
+  { // assignment, value to empty
+    optional input{42};
+    optional dest{};
+    dest = input;
+    assert(dest.has_value());
+    assert(*dest == 42);
+  }
+
+  { // assignment, empty to value
+    optional input{};
+    optional dest{1337};
+    dest = input;
+    assert(!dest.has_value());
+  }
+
+  { // assignment, empty to empty
+    optional input{};
+    optional dest{};
+    dest = input;
+    assert(!dest.has_value());
+  }
+
+  { // comparison with optional
+    optional lhs{42};
+    optional rhs{1337};
+    assert(!(lhs == rhs));
+    assert(lhs != rhs);
+    assert(lhs < rhs);
+    assert(lhs <= rhs);
+    assert(!(lhs > rhs));
+    assert(!(lhs >= rhs));
+  }
+
+  { // comparison with type
+    optional opt{42};
+    assert(opt == device_only_type{42});
+    assert(device_only_type{42} == opt);
+    assert(opt != device_only_type{1337});
+    assert(device_only_type{1337} != opt);
+
+    assert(opt < device_only_type{1337});
+    assert(device_only_type{7} < opt);
+    assert(opt <= device_only_type{1337});
+    assert(device_only_type{7} <= opt);
+
+    assert(opt > device_only_type{7});
+    assert(device_only_type{1337} > opt);
+    assert(opt >= device_only_type{7});
+    assert(device_only_type{1337} >= opt);
+  }
+
+  { // swap
+    optional lhs{42};
+    optional rhs{1337};
+    lhs.swap(rhs);
+    assert(*lhs == 1337);
+    assert(*rhs == 42);
+
+    swap(lhs, rhs);
+    assert(*lhs == 42);
+    assert(*rhs == 1337);
+  }
+}
+
+int main(int arg, char** argv)
+{
+  NV_IF_TARGET(NV_IS_DEVICE, (test();))
+  return 0;
+}
diff --git a/libcudacxx/test/libcudacxx/cuda/utilities/optional/host_only_types.pass.cpp b/libcudacxx/test/libcudacxx/cuda/utilities/optional/host_only_types.pass.cpp
new file mode 100644
index 00000000000..3bf26d0fb2e
--- /dev/null
+++ b/libcudacxx/test/libcudacxx/cuda/utilities/optional/host_only_types.pass.cpp
@@ -0,0 +1,134 @@
+//===----------------------------------------------------------------------===//
+//
+// Part of the libcu++ Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+// SPDX-FileCopyrightText: Copyright (c) 2025 NVIDIA CORPORATION & AFFILIATES.
+//
+//===----------------------------------------------------------------------===//
+
+// UNSUPPORTED: nvrtc
+
+#include <cuda/std/cassert>
+#include <cuda/std/optional>
+
+#include "host_device_types.h"
+#include "test_macros.h"
+
+void test()
+{
+  using optional = cuda::std::optional<host_only_type>;
+  { // default construction
+    optional default_constructed{};
+    assert(!default_constructed.has_value());
+  }
+
+  { // in_place zero initialization
+    optional in_place_zero_initialization{cuda::std::in_place};
+    assert(in_place_zero_initialization.has_value());
+    assert(*in_place_zero_initialization == 0);
+  }
+
+  { // in_place initialization
+    optional in_place_initialization{cuda::std::in_place, 42};
+    assert(in_place_initialization.has_value());
+    assert(*in_place_initialization == 42);
+  }
+
+  { // value initialization
+    optional value_initialization{42};
+    assert(value_initialization.has_value());
+    assert(*value_initialization == 42);
+  }
+
+  { // copy construction
+    optional input{42};
+    optional dest{input};
+    assert(dest.has_value());
+    assert(*dest == 42);
+  }
+
+  { // move construction
+    optional input{42};
+    optional dest{cuda::std::move(input)};
+    assert(dest.has_value());
+    assert(*dest == 42);
+  }
+
+  { // assignment, value to value
+    optional input{42};
+    optional dest{1337};
+    dest = input;
+    assert(dest.has_value());
+    assert(*dest == 42);
+  }
+
+  { // assignment, value to empty
+    optional input{42};
+    optional dest{};
+    dest = input;
+    assert(dest.has_value());
+    assert(*dest == 42);
+  }
+
+  { // assignment, empty to value
+    optional input{};
+    optional dest{1337};
+    dest = input;
+    assert(!dest.has_value());
+  }
+
+  { // assignment, empty to empty
+    optional input{};
+    optional dest{};
+    dest = input;
+    assert(!dest.has_value());
+  }
+
+  { // comparison with optional
+    optional lhs{42};
+    optional rhs{1337};
+    assert(!(lhs == rhs));
+    assert(lhs != rhs);
+    assert(lhs < rhs);
+    assert(lhs <= rhs);
+    assert(!(lhs > rhs));
+    assert(!(lhs >= rhs));
+  }
+
+  { // comparison with type
+    optional opt{42};
+    assert(opt == host_only_type{42});
+    assert(host_only_type{42} == opt);
+    assert(opt != host_only_type{1337});
+    assert(host_only_type{1337} != opt);
+
+    assert(opt < host_only_type{1337});
+    assert(host_only_type{7} < opt);
+    assert(opt <= host_only_type{1337});
+    assert(host_only_type{7} <= opt);
+
+    assert(opt > host_only_type{7});
+    assert(host_only_type{1337} > opt);
+    assert(opt >= host_only_type{7});
+    assert(host_only_type{1337} >= opt);
+  }
+
+  { // swap
+    optional lhs{42};
+    optional rhs{1337};
+    lhs.swap(rhs);
+    assert(*lhs == 1337);
+    assert(*rhs == 42);
+
+    swap(lhs, rhs);
+    assert(*lhs == 42);
+    assert(*rhs == 1337);
+  }
+}
+
+int main(int arg, char** argv)
+{
+  NV_IF_TARGET(NV_IS_HOST, (test();))
+  return 0;
+}
diff --git a/libcudacxx/test/libcudacxx/cuda/utilities/tuple/device_only_types.pass.cpp b/libcudacxx/test/libcudacxx/cuda/utilities/tuple/device_only_types.pass.cpp
new file mode 100644
index 00000000000..d8820409d10
--- /dev/null
+++ b/libcudacxx/test/libcudacxx/cuda/utilities/tuple/device_only_types.pass.cpp
@@ -0,0 +1,81 @@
+//===----------------------------------------------------------------------===//
+//
+// Part of the libcu++ Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+// SPDX-FileCopyrightText: Copyright (c) 2025 NVIDIA CORPORATION & AFFILIATES.
+//
+//===----------------------------------------------------------------------===//
+
+#include <cuda/std/cassert>
+#include <cuda/std/tuple>
+
+#include "host_device_types.h"
+#include "test_macros.h"
+
+__device__ void test()
+{
+  using tuple = cuda::std::tuple<device_only_type>;
+  { // default construction
+    tuple default_constructed{};
+    assert(cuda::std::get<0>(default_constructed) == 0);
+  }
+
+  { // value initialization
+    tuple value_initialization{device_only_type{42}};
+    assert(cuda::std::get<0>(value_initialization) == 42);
+  }
+
+  { // value initialization
+    tuple value_initialization{42};
+    assert(cuda::std::get<0>(value_initialization) == 42);
+  }
+
+  { // copy construction
+    tuple input{42};
+    tuple dest{input};
+    assert(cuda::std::get<0>(dest) == 42);
+  }
+
+  { // move construction
+    tuple input{42};
+    tuple dest{cuda::std::move(input)};
+    assert(cuda::std::get<0>(dest) == 42);
+  }
+
+  { // assignment, value to value
+    tuple input{42};
+    tuple dest{1337};
+    dest = input;
+    assert(cuda::std::get<0>(dest) == 42);
+  }
+
+  { // comparison with tuple
+    tuple lhs{42};
+    tuple rhs{1337};
+    assert(!(lhs == rhs));
+    assert(lhs != rhs);
+    assert(lhs < rhs);
+    assert(lhs <= rhs);
+    assert(!(lhs > rhs));
+    assert(!(lhs >= rhs));
+  }
+
+  { // swap
+    tuple lhs{42};
+    tuple rhs{1337};
+    lhs.swap(rhs);
+    assert(cuda::std::get<0>(lhs) == 1337);
+    assert(cuda::std::get<0>(rhs) == 42);
+
+    swap(lhs, rhs);
+    assert(cuda::std::get<0>(lhs) == 42);
+    assert(cuda::std::get<0>(rhs) == 1337);
+  }
+}
+
+int main(int arg, char** argv)
+{
+  NV_IF_TARGET(NV_IS_DEVICE, (test();))
+  return 0;
+}
diff --git a/libcudacxx/test/libcudacxx/cuda/tuple/forward_as_tuple_interop.pass.cpp b/libcudacxx/test/libcudacxx/cuda/utilities/tuple/forward_as_tuple_interop.pass.cpp
similarity index 100%
rename from libcudacxx/test/libcudacxx/cuda/tuple/forward_as_tuple_interop.pass.cpp
rename to libcudacxx/test/libcudacxx/cuda/utilities/tuple/forward_as_tuple_interop.pass.cpp
diff --git a/libcudacxx/test/libcudacxx/cuda/utilities/tuple/host_only_types.pass.cpp b/libcudacxx/test/libcudacxx/cuda/utilities/tuple/host_only_types.pass.cpp
new file mode 100644
index 00000000000..4942d051b1c
--- /dev/null
+++ b/libcudacxx/test/libcudacxx/cuda/utilities/tuple/host_only_types.pass.cpp
@@ -0,0 +1,90 @@
+//===----------------------------------------------------------------------===//
+//
+// Part of the libcu++ Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+// SPDX-FileCopyrightText: Copyright (c) 2025 NVIDIA CORPORATION & AFFILIATES.
+//
+//===----------------------------------------------------------------------===//
+
+// UNSUPPORTED: nvrtc
+
+#include <cuda/std/cassert>
+#include <cuda/std/tuple>
+
+#include "host_device_types.h"
+#include "test_macros.h"
+
+void test()
+{
+  using tuple = cuda::std::tuple<host_only_type>;
+  { // default construction
+    tuple default_constructed{};
+    assert(cuda::std::get<0>(default_constructed) == 0);
+  }
+
+  { // value initialization
+    tuple value_initialization{host_only_type{42}};
+    assert(cuda::std::get<0>(value_initialization) == 42);
+  }
+
+  { // value initialization
+    tuple value_initialization{42};
+    assert(cuda::std::get<0>(value_initialization) == 42);
+  }
+
+  { // copy construction
+    tuple input{42};
+    tuple dest{input};
+    assert(cuda::std::get<0>(dest) == 42);
+  }
+
+  { // move construction
+    tuple input{42};
+    tuple dest{cuda::std::move(input)};
+    assert(cuda::std::get<0>(dest) == 42);
+  }
+
+  { // assignment, value to value
+    tuple input{42};
+    tuple dest{1337};
+    dest = input;
+    assert(cuda::std::get<0>(dest) == 42);
+  }
+
+  { // assignment, value to empty
+    tuple input{42};
+    tuple dest{};
+    dest = input;
+    assert(cuda::std::get<0>(dest) == 42);
+  }
+
+  { // comparison with tuple
+    tuple lhs{42};
+    tuple rhs{1337};
+    assert(!(lhs == rhs));
+    assert(lhs != rhs);
+    assert(lhs < rhs);
+    assert(lhs <= rhs);
+    assert(!(lhs > rhs));
+    assert(!(lhs >= rhs));
+  }
+
+  { // swap
+    tuple lhs{42};
+    tuple rhs{1337};
+    lhs.swap(rhs);
+    assert(cuda::std::get<0>(lhs) == 1337);
+    assert(cuda::std::get<0>(rhs) == 42);
+
+    swap(lhs, rhs);
+    assert(cuda::std::get<0>(lhs) == 42);
+    assert(cuda::std::get<0>(rhs) == 1337);
+  }
+}
+
+int main(int arg, char** argv)
+{
+  NV_IF_TARGET(NV_IS_HOST, (test();))
+  return 0;
+}
diff --git a/libcudacxx/test/libcudacxx/cuda/tuple/vector_types_get.pass.cpp b/libcudacxx/test/libcudacxx/cuda/utilities/tuple/vector_types_get.pass.cpp
similarity index 100%
rename from libcudacxx/test/libcudacxx/cuda/tuple/vector_types_get.pass.cpp
rename to libcudacxx/test/libcudacxx/cuda/utilities/tuple/vector_types_get.pass.cpp
diff --git a/libcudacxx/test/libcudacxx/cuda/tuple/vector_types_structured_bindings.pass.cpp b/libcudacxx/test/libcudacxx/cuda/utilities/tuple/vector_types_structured_bindings.pass.cpp
similarity index 100%
rename from libcudacxx/test/libcudacxx/cuda/tuple/vector_types_structured_bindings.pass.cpp
rename to libcudacxx/test/libcudacxx/cuda/utilities/tuple/vector_types_structured_bindings.pass.cpp
diff --git a/libcudacxx/test/libcudacxx/cuda/tuple/vector_types_tuple_element.pass.cpp b/libcudacxx/test/libcudacxx/cuda/utilities/tuple/vector_types_tuple_element.pass.cpp
similarity index 100%
rename from libcudacxx/test/libcudacxx/cuda/tuple/vector_types_tuple_element.pass.cpp
rename to libcudacxx/test/libcudacxx/cuda/utilities/tuple/vector_types_tuple_element.pass.cpp
diff --git a/libcudacxx/test/libcudacxx/cuda/tuple/vector_types_tuple_size.pass.cpp b/libcudacxx/test/libcudacxx/cuda/utilities/tuple/vector_types_tuple_size.pass.cpp
similarity index 100%
rename from libcudacxx/test/libcudacxx/cuda/tuple/vector_types_tuple_size.pass.cpp
rename to libcudacxx/test/libcudacxx/cuda/utilities/tuple/vector_types_tuple_size.pass.cpp
diff --git a/libcudacxx/test/libcudacxx/cuda/utilities/unexpected/device_only_types.pass.cpp b/libcudacxx/test/libcudacxx/cuda/utilities/unexpected/device_only_types.pass.cpp
new file mode 100644
index 00000000000..f36e86c2c3f
--- /dev/null
+++ b/libcudacxx/test/libcudacxx/cuda/utilities/unexpected/device_only_types.pass.cpp
@@ -0,0 +1,82 @@
+//===----------------------------------------------------------------------===//
+//
+// Part of the libcu++ Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+// SPDX-FileCopyrightText: Copyright (c) 2025 NVIDIA CORPORATION & AFFILIATES.
+//
+//===----------------------------------------------------------------------===//
+
+#include <cuda/std/cassert>
+#include <cuda/std/expected>
+
+#include "host_device_types.h"
+#include "test_macros.h"
+
+__device__ void test()
+{
+  using unexpected = cuda::std::unexpected<device_only_type>;
+  { // in_place zero initialization
+    unexpected in_place_zero_initialization{cuda::std::in_place};
+    assert(in_place_zero_initialization.error() == 0);
+  }
+
+  { // in_place initialization
+    unexpected in_place_initialization{cuda::std::in_place, 42};
+    assert(in_place_initialization.error() == 42);
+  }
+
+  { // value initialization
+    unexpected value_initialization{42};
+    assert(value_initialization.error() == 42);
+  }
+
+  { // initializer_list initialization
+    unexpected init_list_initialization{cuda::std::in_place, cuda::std::initializer_list<int>{}, 42};
+    assert(init_list_initialization.error() == 42);
+  }
+
+  { // copy construction
+    unexpected input{42};
+    unexpected dest{input};
+    assert(dest.error() == 42);
+  }
+
+  { // move construction
+    unexpected input{42};
+    unexpected dest{cuda::std::move(input)};
+    assert(dest.error() == 42);
+  }
+
+  { // assignment
+    unexpected input{42};
+    unexpected dest{1337};
+    dest = input;
+    assert(dest.error() == 42);
+  }
+
+  { // comparison with unexpected
+    unexpected lhs{42};
+    unexpected rhs{1337};
+    assert(!(lhs == rhs));
+    assert(lhs != rhs);
+  }
+
+  { // swap
+    unexpected lhs{42};
+    unexpected rhs{1337};
+    lhs.swap(rhs);
+    assert(lhs.error() == 1337);
+    assert(rhs.error() == 42);
+
+    swap(lhs, rhs);
+    assert(lhs.error() == 42);
+    assert(rhs.error() == 1337);
+  }
+}
+
+int main(int arg, char** argv)
+{
+  NV_IF_TARGET(NV_IS_DEVICE, (test();))
+  return 0;
+}
diff --git a/libcudacxx/test/libcudacxx/cuda/utilities/unexpected/host_only_types.pass.cpp b/libcudacxx/test/libcudacxx/cuda/utilities/unexpected/host_only_types.pass.cpp
new file mode 100644
index 00000000000..ca12494418c
--- /dev/null
+++ b/libcudacxx/test/libcudacxx/cuda/utilities/unexpected/host_only_types.pass.cpp
@@ -0,0 +1,85 @@
+//===----------------------------------------------------------------------===//
+//
+// Part of the libcu++ Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+// SPDX-FileCopyrightText: Copyright (c) 2025 NVIDIA CORPORATION & AFFILIATES.
+//
+//===----------------------------------------------------------------------===//
+
+// UNSUPPORTED: nvrtc
+
+#include <cuda/std/cassert>
+#include <cuda/std/expected>
+#include <cuda/std/initializer_list>
+
+#include "host_device_types.h"
+#include "test_macros.h"
+
+void test()
+{
+  using unexpected = cuda::std::unexpected<host_only_type>;
+  { // in_place zero initialization
+    unexpected in_place_zero_initialization{cuda::std::in_place};
+    assert(in_place_zero_initialization.error() == 0);
+  }
+
+  { // in_place initialization
+    unexpected in_place_initialization{cuda::std::in_place, 42};
+    assert(in_place_initialization.error() == 42);
+  }
+
+  { // value initialization
+    unexpected value_initialization{42};
+    assert(value_initialization.error() == 42);
+  }
+
+  { // initializer_list initialization
+    unexpected init_list_initialization{cuda::std::in_place, cuda::std::initializer_list<int>{}, 42};
+    assert(init_list_initialization.error() == 42);
+  }
+
+  { // copy construction
+    unexpected input{42};
+    unexpected dest{input};
+    assert(dest.error() == 42);
+  }
+
+  { // move construction
+    unexpected input{42};
+    unexpected dest{cuda::std::move(input)};
+    assert(dest.error() == 42);
+  }
+
+  { // assignment
+    unexpected input{42};
+    unexpected dest{1337};
+    dest = input;
+    assert(dest.error() == 42);
+  }
+
+  { // comparison with unexpected
+    unexpected lhs{42};
+    unexpected rhs{1337};
+    assert(!(lhs == rhs));
+    assert(lhs != rhs);
+  }
+
+  { // swap
+    unexpected lhs{42};
+    unexpected rhs{1337};
+    lhs.swap(rhs);
+    assert(lhs.error() == 1337);
+    assert(rhs.error() == 42);
+
+    swap(lhs, rhs);
+    assert(lhs.error() == 42);
+    assert(rhs.error() == 1337);
+  }
+}
+
+int main(int arg, char** argv)
+{
+  NV_IF_TARGET(NV_IS_HOST, (test();))
+  return 0;
+}
diff --git a/libcudacxx/test/libcudacxx/cuda/utilities/utility/pair/device_only_types.pass.cpp b/libcudacxx/test/libcudacxx/cuda/utilities/utility/pair/device_only_types.pass.cpp
new file mode 100644
index 00000000000..aebdd6e12ea
--- /dev/null
+++ b/libcudacxx/test/libcudacxx/cuda/utilities/utility/pair/device_only_types.pass.cpp
@@ -0,0 +1,93 @@
+//===----------------------------------------------------------------------===//
+//
+// Part of the libcu++ Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+// SPDX-FileCopyrightText: Copyright (c) 2025 NVIDIA CORPORATION & AFFILIATES.
+//
+//===----------------------------------------------------------------------===//
+
+// UNSUPPORTED: nvrtc
+
+#include <cuda/std/cassert>
+#include <cuda/std/utility>
+
+#include "host_device_types.h"
+#include "test_macros.h"
+
+__device__ void test()
+{
+  using pair = cuda::std::pair<device_only_type, device_only_type>;
+  { // default construction
+    pair default_constructed{};
+    assert(default_constructed.first == 0);
+    assert(default_constructed.second == 0);
+  }
+
+  { // value initialization
+    pair value_initialization{device_only_type{42}, device_only_type{1337}};
+    assert(value_initialization.first == 42);
+    assert(value_initialization.second == 1337);
+  }
+
+  { // value initialization
+    pair value_initialization{42, 1337};
+    assert(value_initialization.first == 42);
+    assert(value_initialization.second == 1337);
+  }
+
+  { // copy construction
+    pair input{42, 1337};
+    pair dest{input};
+    assert(dest.first == 42);
+    assert(dest.second == 1337);
+  }
+
+  { // move construction
+    pair input{42, 1337};
+    pair dest{cuda::std::move(input)};
+    assert(dest.first == 42);
+    assert(dest.second == 1337);
+  }
+
+  { // assignment, value to value
+    pair input{42, 1337};
+    pair dest{1337, 42};
+    dest = input;
+    assert(dest.first == 42);
+    assert(dest.second == 1337);
+  }
+
+  { // comparison with pair
+    pair lhs{42, 1337};
+    pair rhs{1337, 42};
+    assert(!(lhs == rhs));
+    assert(lhs != rhs);
+    assert(lhs < rhs);
+    assert(lhs <= rhs);
+    assert(!(lhs > rhs));
+    assert(!(lhs >= rhs));
+  }
+
+  { // swap
+    pair lhs{42, 1337};
+    pair rhs{1337, 42};
+    lhs.swap(rhs);
+    assert(lhs.first == 1337);
+    assert(lhs.second == 42);
+    assert(rhs.first == 42);
+    assert(rhs.second == 1337);
+
+    swap(lhs, rhs);
+    assert(lhs.first == 42);
+    assert(lhs.second == 1337);
+    assert(rhs.first == 1337);
+    assert(rhs.second == 42);
+  }
+}
+
+int main(int arg, char** argv)
+{
+  NV_IF_TARGET(NV_IS_DEVICE, (test();))
+  return 0;
+}
diff --git a/libcudacxx/test/libcudacxx/cuda/utilities/utility/pair/host_only_types.pass.cpp b/libcudacxx/test/libcudacxx/cuda/utilities/utility/pair/host_only_types.pass.cpp
new file mode 100644
index 00000000000..cf1195f204d
--- /dev/null
+++ b/libcudacxx/test/libcudacxx/cuda/utilities/utility/pair/host_only_types.pass.cpp
@@ -0,0 +1,93 @@
+//===----------------------------------------------------------------------===//
+//
+// Part of the libcu++ Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+// SPDX-FileCopyrightText: Copyright (c) 2025 NVIDIA CORPORATION & AFFILIATES.
+//
+//===----------------------------------------------------------------------===//
+
+// UNSUPPORTED: nvrtc
+
+#include <cuda/std/cassert>
+#include <cuda/std/utility>
+
+#include "host_device_types.h"
+#include "test_macros.h"
+
+void test()
+{
+  using pair = cuda::std::pair<host_only_type, host_only_type>;
+  { // default construction
+    pair default_constructed{};
+    assert(default_constructed.first == 0);
+    assert(default_constructed.second == 0);
+  }
+
+  { // value initialization
+    pair value_initialization{host_only_type{42}, host_only_type{1337}};
+    assert(value_initialization.first == 42);
+    assert(value_initialization.second == 1337);
+  }
+
+  { // value initialization
+    pair value_initialization{42, 1337};
+    assert(value_initialization.first == 42);
+    assert(value_initialization.second == 1337);
+  }
+
+  { // copy construction
+    pair input{42, 1337};
+    pair dest{input};
+    assert(dest.first == 42);
+    assert(dest.second == 1337);
+  }
+
+  { // move construction
+    pair input{42, 1337};
+    pair dest{cuda::std::move(input)};
+    assert(dest.first == 42);
+    assert(dest.second == 1337);
+  }
+
+  { // assignment, value to value
+    pair input{42, 1337};
+    pair dest{1337, 42};
+    dest = input;
+    assert(dest.first == 42);
+    assert(dest.second == 1337);
+  }
+
+  { // comparison with pair
+    pair lhs{42, 1337};
+    pair rhs{1337, 42};
+    assert(!(lhs == rhs));
+    assert(lhs != rhs);
+    assert(lhs < rhs);
+    assert(lhs <= rhs);
+    assert(!(lhs > rhs));
+    assert(!(lhs >= rhs));
+  }
+
+  { // swap
+    pair lhs{42, 1337};
+    pair rhs{1337, 42};
+    lhs.swap(rhs);
+    assert(lhs.first == 1337);
+    assert(lhs.second == 42);
+    assert(rhs.first == 42);
+    assert(rhs.second == 1337);
+
+    swap(lhs, rhs);
+    assert(lhs.first == 42);
+    assert(lhs.second == 1337);
+    assert(rhs.first == 1337);
+    assert(rhs.second == 42);
+  }
+}
+
+int main(int arg, char** argv)
+{
+  NV_IF_TARGET(NV_IS_HOST, (test();))
+  return 0;
+}
diff --git a/libcudacxx/test/libcudacxx/cuda/pair_interop/pair.assign.pass.cpp b/libcudacxx/test/libcudacxx/cuda/utilities/utility/pair/interop/pair.assign.pass.cpp
similarity index 100%
rename from libcudacxx/test/libcudacxx/cuda/pair_interop/pair.assign.pass.cpp
rename to libcudacxx/test/libcudacxx/cuda/utilities/utility/pair/interop/pair.assign.pass.cpp
diff --git a/libcudacxx/test/libcudacxx/cuda/pair_interop/pair.cons.pass.cpp b/libcudacxx/test/libcudacxx/cuda/utilities/utility/pair/interop/pair.cons.pass.cpp
similarity index 100%
rename from libcudacxx/test/libcudacxx/cuda/pair_interop/pair.cons.pass.cpp
rename to libcudacxx/test/libcudacxx/cuda/utilities/utility/pair/interop/pair.cons.pass.cpp
diff --git a/libcudacxx/test/libcudacxx/cuda/pair_interop/pair.conv.pass.cpp b/libcudacxx/test/libcudacxx/cuda/utilities/utility/pair/interop/pair.conv.pass.cpp
similarity index 100%
rename from libcudacxx/test/libcudacxx/cuda/pair_interop/pair.conv.pass.cpp
rename to libcudacxx/test/libcudacxx/cuda/utilities/utility/pair/interop/pair.conv.pass.cpp
diff --git a/libcudacxx/test/libcudacxx/cuda/utilities/variant/device_only_types.pass.cpp b/libcudacxx/test/libcudacxx/cuda/utilities/variant/device_only_types.pass.cpp
new file mode 100644
index 00000000000..38ee416a8fc
--- /dev/null
+++ b/libcudacxx/test/libcudacxx/cuda/utilities/variant/device_only_types.pass.cpp
@@ -0,0 +1,120 @@
+//===----------------------------------------------------------------------===//
+//
+// Part of the libcu++ Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+// SPDX-FileCopyrightText: Copyright (c) 2025 NVIDIA CORPORATION & AFFILIATES.
+//
+//===----------------------------------------------------------------------===//
+
+#include <cuda/std/cassert>
+#include <cuda/std/variant>
+
+#include "host_device_types.h"
+#include "test_macros.h"
+
+__device__ void test()
+{
+  using variant = cuda::std::variant<device_only_type>;
+  { // default construction
+    variant default_constructed{};
+    assert(cuda::std::get<0>(default_constructed) == 0);
+  }
+
+  { // value initialization
+    variant value_initialization{device_only_type{42}};
+    assert(cuda::std::get<0>(value_initialization) == 42);
+  }
+
+  { // value initialization
+    variant value_initialization{42};
+    assert(cuda::std::get<0>(value_initialization) == 42);
+  }
+
+  { // in_place_type_t initialization
+    variant in_place_initialization{cuda::std::in_place_type_t<device_only_type>{}, 42};
+    assert(cuda::std::get<0>(in_place_initialization) == 42);
+  }
+
+  { // in_place_index_t initialization
+    variant in_place_initialization{cuda::std::in_place_index_t<0>{}, 42};
+    assert(cuda::std::get<0>(in_place_initialization) == 42);
+  }
+
+  { // in_place_type_t initializer_list initialization
+    variant init_list_initialization{
+      cuda::std::in_place_type_t<device_only_type>{}, cuda::std::initializer_list<int>{}, 42};
+    assert(cuda::std::get<0>(init_list_initialization) == 42);
+  }
+
+  { // in_place_type_t initializer_list initialization
+    variant init_list_initialization{cuda::std::in_place_index_t<0>{}, cuda::std::initializer_list<int>{}, 42};
+    assert(cuda::std::get<0>(init_list_initialization) == 42);
+  }
+
+  { // copy construction
+    variant input{42};
+    variant dest{input};
+    assert(cuda::std::get<0>(dest) == 42);
+  }
+
+  { // move construction
+    variant input{42};
+    variant dest{cuda::std::move(input)};
+    assert(cuda::std::get<0>(dest) == 42);
+  }
+
+  { // assignment, value to value
+    variant input{42};
+    variant dest{1337};
+    dest = input;
+    assert(cuda::std::get<0>(dest) == 42);
+  }
+
+  { // emplace
+    variant var{42};
+    var.emplace<device_only_type>(42);
+    assert(cuda::std::get<0>(var) == 42);
+  }
+
+  { // emplace
+    variant var{42};
+    var.emplace<0>(42);
+    assert(cuda::std::get<0>(var) == 42);
+  }
+
+  { // emplace init list
+    variant var{42};
+    var.emplace<device_only_type>(cuda::std::initializer_list<int>{}, 42);
+    assert(cuda::std::get<0>(var) == 42);
+  }
+
+  { // comparison with variant
+    variant lhs{42};
+    variant rhs{1337};
+    assert(!(lhs == rhs));
+    assert(lhs != rhs);
+    assert(lhs < rhs);
+    assert(lhs <= rhs);
+    assert(!(lhs > rhs));
+    assert(!(lhs >= rhs));
+  }
+
+  { // swap
+    variant lhs{42};
+    variant rhs{1337};
+    lhs.swap(rhs);
+    assert(cuda::std::get<0>(lhs) == 1337);
+    assert(cuda::std::get<0>(rhs) == 42);
+
+    swap(lhs, rhs);
+    assert(cuda::std::get<0>(lhs) == 42);
+    assert(cuda::std::get<0>(rhs) == 1337);
+  }
+}
+
+int main(int arg, char** argv)
+{
+  NV_IF_TARGET(NV_IS_DEVICE, (test();))
+  return 0;
+}
diff --git a/libcudacxx/test/libcudacxx/cuda/utilities/variant/host_only_types.pass.cpp b/libcudacxx/test/libcudacxx/cuda/utilities/variant/host_only_types.pass.cpp
new file mode 100644
index 00000000000..5f12da6074b
--- /dev/null
+++ b/libcudacxx/test/libcudacxx/cuda/utilities/variant/host_only_types.pass.cpp
@@ -0,0 +1,129 @@
+//===----------------------------------------------------------------------===//
+//
+// Part of the libcu++ Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+// SPDX-FileCopyrightText: Copyright (c) 2025 NVIDIA CORPORATION & AFFILIATES.
+//
+//===----------------------------------------------------------------------===//
+
+// UNSUPPORTED: nvrtc
+
+#include <cuda/std/cassert>
+#include <cuda/std/variant>
+
+#include "host_device_types.h"
+#include "test_macros.h"
+
+void test()
+{
+  using variant = cuda::std::variant<host_only_type>;
+  { // default construction
+    variant default_constructed{};
+    assert(cuda::std::get<0>(default_constructed) == 0);
+  }
+
+  { // value initialization
+    variant value_initialization{host_only_type{42}};
+    assert(cuda::std::get<0>(value_initialization) == 42);
+  }
+
+  { // value initialization
+    variant value_initialization{42};
+    assert(cuda::std::get<0>(value_initialization) == 42);
+  }
+
+  { // in_place_type_t initialization
+    variant in_place_initialization{cuda::std::in_place_type_t<host_only_type>{}, 42};
+    assert(cuda::std::get<0>(in_place_initialization) == 42);
+  }
+
+  { // in_place_index_t initialization
+    variant in_place_initialization{cuda::std::in_place_index_t<0>{}, 42};
+    assert(cuda::std::get<0>(in_place_initialization) == 42);
+  }
+
+  { // in_place_type_t initializer_list initialization
+    variant init_list_initialization{
+      cuda::std::in_place_type_t<host_only_type>{}, cuda::std::initializer_list<int>{}, 42};
+    assert(cuda::std::get<0>(init_list_initialization) == 42);
+  }
+
+  { // in_place_type_t initializer_list initialization
+    variant init_list_initialization{cuda::std::in_place_index_t<0>{}, cuda::std::initializer_list<int>{}, 42};
+    assert(cuda::std::get<0>(init_list_initialization) == 42);
+  }
+
+  { // copy construction
+    variant input{42};
+    variant dest{input};
+    assert(cuda::std::get<0>(dest) == 42);
+  }
+
+  { // move construction
+    variant input{42};
+    variant dest{cuda::std::move(input)};
+    assert(cuda::std::get<0>(dest) == 42);
+  }
+
+  { // assignment, value to value
+    variant input{42};
+    variant dest{1337};
+    dest = input;
+    assert(cuda::std::get<0>(dest) == 42);
+  }
+
+  { // assignment, value to empty
+    variant input{42};
+    variant dest{};
+    dest = input;
+    assert(cuda::std::get<0>(dest) == 42);
+  }
+
+  { // emplace
+    variant var{42};
+    var.emplace<host_only_type>(42);
+    assert(cuda::std::get<0>(var) == 42);
+  }
+
+  { // emplace
+    variant var{42};
+    var.emplace<0>(42);
+    assert(cuda::std::get<0>(var) == 42);
+  }
+
+  { // emplace init list
+    variant var{42};
+    var.emplace<host_only_type>(cuda::std::initializer_list<int>{}, 42);
+    assert(cuda::std::get<0>(var) == 42);
+  }
+
+  { // comparison with variant
+    variant lhs{42};
+    variant rhs{1337};
+    assert(!(lhs == rhs));
+    assert(lhs != rhs);
+    assert(lhs < rhs);
+    assert(lhs <= rhs);
+    assert(!(lhs > rhs));
+    assert(!(lhs >= rhs));
+  }
+
+  { // swap
+    variant lhs{42};
+    variant rhs{1337};
+    lhs.swap(rhs);
+    assert(cuda::std::get<0>(lhs) == 1337);
+    assert(cuda::std::get<0>(rhs) == 42);
+
+    swap(lhs, rhs);
+    assert(cuda::std::get<0>(lhs) == 42);
+    assert(cuda::std::get<0>(rhs) == 1337);
+  }
+}
+
+int main(int arg, char** argv)
+{
+  NV_IF_TARGET(NV_IS_HOST, (test();))
+  return 0;
+}
diff --git a/libcudacxx/test/support/host_device_types.h b/libcudacxx/test/support/host_device_types.h
new file mode 100644
index 00000000000..e8fa21b85b9
--- /dev/null
+++ b/libcudacxx/test/support/host_device_types.h
@@ -0,0 +1,148 @@
+//===----------------------------------------------------------------------===//
+//
+// Part of the libcu++ Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+// SPDX-FileCopyrightText: Copyright (c) 2025 NVIDIA CORPORATION & AFFILIATES.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef TEST_SUPPORT_HOST_DEVICE_TYPES
+#define TEST_SUPPORT_HOST_DEVICE_TYPES
+
+#include <cuda/std/initializer_list>
+#include <cuda/std/utility>
+
+#if !_CCCL_COMPILER(NVRTC)
+struct host_only_type
+{
+  int val_;
+
+  host_only_type(const int val = 0) noexcept
+      : val_(val)
+  {}
+  host_only_type(cuda::std::initializer_list<int>, const int val) noexcept
+      : val_(val)
+  {}
+
+  host_only_type(const host_only_type& other) noexcept
+      : val_(other.val_)
+  {}
+  host_only_type(host_only_type&& other) noexcept
+      : val_(cuda::std::exchange(other.val_, -1))
+  {}
+
+  host_only_type& operator=(const host_only_type& other) noexcept
+  {
+    val_ = other.val_;
+    return *this;
+  }
+
+  host_only_type& operator=(host_only_type&& other) noexcept
+
+  {
+    val_ = cuda::std::exchange(other.val_, -1);
+    return *this;
+  }
+
+  ~host_only_type() noexcept {}
+
+  _CCCL_NODISCARD_FRIEND bool operator==(const host_only_type& lhs, const host_only_type& rhs) noexcept
+  {
+    return lhs.val_ == rhs.val_;
+  }
+  _CCCL_NODISCARD_FRIEND bool operator!=(const host_only_type& lhs, const host_only_type& rhs) noexcept
+  {
+    return lhs.val_ != rhs.val_;
+  }
+  _CCCL_NODISCARD_FRIEND bool operator<(const host_only_type& lhs, const host_only_type& rhs) noexcept
+  {
+    return lhs.val_ < rhs.val_;
+  }
+  _CCCL_NODISCARD_FRIEND bool operator<=(const host_only_type& lhs, const host_only_type& rhs) noexcept
+  {
+    return lhs.val_ <= rhs.val_;
+  }
+  _CCCL_NODISCARD_FRIEND bool operator>(const host_only_type& lhs, const host_only_type& rhs) noexcept
+  {
+    return lhs.val_ > rhs.val_;
+  }
+  _CCCL_NODISCARD_FRIEND bool operator>=(const host_only_type& lhs, const host_only_type& rhs) noexcept
+  {
+    return lhs.val_ >= rhs.val_;
+  }
+
+  void swap(host_only_type& other) noexcept
+  {
+    cuda::std::swap(val_, other.val_);
+  }
+};
+#endif // !_CCCL_COMPILER(NVRTC)
+
+#if _CCCL_HAS_CUDA_COMPILER
+struct device_only_type
+{
+  int val_;
+
+  __device__ device_only_type(const int val = 0) noexcept
+      : val_(val)
+  {}
+  __device__ device_only_type(cuda::std::initializer_list<int>, const int val) noexcept
+      : val_(val)
+  {}
+
+  __device__ device_only_type(const device_only_type& other) noexcept
+      : val_(other.val_)
+  {}
+  __device__ device_only_type(device_only_type&& other) noexcept
+      : val_(cuda::std::exchange(other.val_, -1))
+  {}
+
+  __device__ device_only_type& operator=(const device_only_type& other) noexcept
+  {
+    val_ = other.val_;
+    return *this;
+  }
+
+  __device__ device_only_type& operator=(device_only_type&& other) noexcept
+
+  {
+    val_ = cuda::std::exchange(other.val_, -1);
+    return *this;
+  }
+
+  __device__ ~device_only_type() noexcept {}
+
+  __device__ _CCCL_NODISCARD_FRIEND bool operator==(const device_only_type& lhs, const device_only_type& rhs) noexcept
+  {
+    return lhs.val_ == rhs.val_;
+  }
+  __device__ _CCCL_NODISCARD_FRIEND bool operator!=(const device_only_type& lhs, const device_only_type& rhs) noexcept
+  {
+    return lhs.val_ != rhs.val_;
+  }
+  __device__ _CCCL_NODISCARD_FRIEND bool operator<(const device_only_type& lhs, const device_only_type& rhs) noexcept
+  {
+    return lhs.val_ < rhs.val_;
+  }
+  __device__ _CCCL_NODISCARD_FRIEND bool operator<=(const device_only_type& lhs, const device_only_type& rhs) noexcept
+  {
+    return lhs.val_ <= rhs.val_;
+  }
+  __device__ _CCCL_NODISCARD_FRIEND bool operator>(const device_only_type& lhs, const device_only_type& rhs) noexcept
+  {
+    return lhs.val_ > rhs.val_;
+  }
+  __device__ _CCCL_NODISCARD_FRIEND bool operator>=(const device_only_type& lhs, const device_only_type& rhs) noexcept
+  {
+    return lhs.val_ >= rhs.val_;
+  }
+
+  __device__ void swap(device_only_type& other) noexcept
+  {
+    cuda::std::swap(val_, other.val_);
+  }
+};
+#endif // _CCCL_HAS_CUDA_COMPILER
+
+#endif // TEST_SUPPORT_HOST_DEVICE_TYPES

From 8615f321e6305a1dbbd72b8050c47e4e6b27790f Mon Sep 17 00:00:00 2001
From: Wesley Maxey <71408887+wmaxey@users.noreply.github.com>
Date: Thu, 30 Jan 2025 00:09:17 -0800
Subject: [PATCH 15/33] [nv/target] Add sm_120 macros. (#3550)

Co-authored-by: Bernhard Manfred Gruber <bernhardmgruber@gmail.com>
---
 libcudacxx/include/nv/detail/__target_macros | 21 ++++++++++++++++++++
 libcudacxx/include/nv/target                 |  9 +++++++--
 2 files changed, 28 insertions(+), 2 deletions(-)

diff --git a/libcudacxx/include/nv/detail/__target_macros b/libcudacxx/include/nv/detail/__target_macros
index 85df652c7d4..2de10fc8ec4 100644
--- a/libcudacxx/include/nv/detail/__target_macros
+++ b/libcudacxx/include/nv/detail/__target_macros
@@ -35,6 +35,7 @@
 #define _NV_TARGET_ARCH_TO_SELECTOR_900  nv::target::sm_90
 #define _NV_TARGET_ARCH_TO_SELECTOR_1000 nv::target::sm_100
 #define _NV_TARGET_ARCH_TO_SELECTOR_1010 nv::target::sm_101
+#define _NV_TARGET_ARCH_TO_SELECTOR_1200 nv::target::sm_120
 
 #define _NV_TARGET_ARCH_TO_SM_350  35
 #define _NV_TARGET_ARCH_TO_SM_370  37
@@ -54,6 +55,7 @@
 #define _NV_TARGET_ARCH_TO_SM_900  90
 #define _NV_TARGET_ARCH_TO_SM_1000 100
 #define _NV_TARGET_ARCH_TO_SM_1010 101
+#define _NV_TARGET_ARCH_TO_SM_1200 120
 
 // Only enable when compiling for CUDA/stdpar
 #if defined(_NV_COMPILER_NVCXX) && defined(_NVHPC_CUDA)
@@ -76,6 +78,7 @@
 #  define _NV_TARGET_VAL_SM_90  nv::target::sm_90
 #  define _NV_TARGET_VAL_SM_100 nv::target::sm_100
 #  define _NV_TARGET_VAL_SM_101 nv::target::sm_101
+#  define _NV_TARGET_VAL_SM_120 nv::target::sm_120
 
 #  define _NV_TARGET___NV_IS_HOST   nv::target::is_host
 #  define _NV_TARGET___NV_IS_DEVICE nv::target::is_device
@@ -112,6 +115,7 @@
 #  define _NV_TARGET_VAL_SM_90  900
 #  define _NV_TARGET_VAL_SM_100 1000
 #  define _NV_TARGET_VAL_SM_101 1010
+#  define _NV_TARGET_VAL_SM_120 1200
 
 #  if defined(__CUDA_ARCH__)
 #    define _NV_TARGET_VAL                __CUDA_ARCH__
@@ -160,6 +164,7 @@
 #  define _NV_TARGET_VAL_SM_90  900
 #  define _NV_TARGET_VAL_SM_100 1000
 #  define _NV_TARGET_VAL_SM_101 1010
+#  define _NV_TARGET_VAL_SM_120 1200
 
 #  define _NV_TARGET_VAL 0
 
@@ -191,6 +196,7 @@
 #define _NV_TARGET___NV_PROVIDES_SM_90  (_NV_TARGET_PROVIDES(_NV_TARGET_VAL_SM_90))
 #define _NV_TARGET___NV_PROVIDES_SM_100 (_NV_TARGET_PROVIDES(_NV_TARGET_VAL_SM_100))
 #define _NV_TARGET___NV_PROVIDES_SM_101 (_NV_TARGET_PROVIDES(_NV_TARGET_VAL_SM_101))
+#define _NV_TARGET___NV_PROVIDES_SM_120 (_NV_TARGET_PROVIDES(_NV_TARGET_VAL_SM_120))
 
 #define _NV_TARGET___NV_IS_EXACTLY_SM_35  (_NV_TARGET_IS_EXACTLY(_NV_TARGET_VAL_SM_35))
 #define _NV_TARGET___NV_IS_EXACTLY_SM_37  (_NV_TARGET_IS_EXACTLY(_NV_TARGET_VAL_SM_37))
@@ -210,6 +216,7 @@
 #define _NV_TARGET___NV_IS_EXACTLY_SM_90  (_NV_TARGET_IS_EXACTLY(_NV_TARGET_VAL_SM_90))
 #define _NV_TARGET___NV_IS_EXACTLY_SM_100 (_NV_TARGET_IS_EXACTLY(_NV_TARGET_VAL_SM_100))
 #define _NV_TARGET___NV_IS_EXACTLY_SM_101 (_NV_TARGET_IS_EXACTLY(_NV_TARGET_VAL_SM_101))
+#define _NV_TARGET___NV_IS_EXACTLY_SM_120 (_NV_TARGET_IS_EXACTLY(_NV_TARGET_VAL_SM_120))
 
 #define NV_PROVIDES_SM_35  __NV_PROVIDES_SM_35
 #define NV_PROVIDES_SM_37  __NV_PROVIDES_SM_37
@@ -229,6 +236,7 @@
 #define NV_PROVIDES_SM_90  __NV_PROVIDES_SM_90
 #define NV_PROVIDES_SM_100 __NV_PROVIDES_SM_100
 #define NV_PROVIDES_SM_101 __NV_PROVIDES_SM_101
+#define NV_PROVIDES_SM_120 __NV_PROVIDES_SM_120
 
 #define NV_IS_EXACTLY_SM_35  __NV_IS_EXACTLY_SM_35
 #define NV_IS_EXACTLY_SM_37  __NV_IS_EXACTLY_SM_37
@@ -248,6 +256,7 @@
 #define NV_IS_EXACTLY_SM_90  __NV_IS_EXACTLY_SM_90
 #define NV_IS_EXACTLY_SM_100 __NV_IS_EXACTLY_SM_100
 #define NV_IS_EXACTLY_SM_101 __NV_IS_EXACTLY_SM_101
+#define NV_IS_EXACTLY_SM_120 __NV_IS_EXACTLY_SM_120
 
 // Disable SM_90a support on non-supporting compilers.
 // Will re-enable for nvcc below.
@@ -381,6 +390,12 @@
 #    define _NV_TARGET_BOOL___NV_IS_EXACTLY_SM_101 0
 #  endif
 
+#  if (_NV_TARGET___NV_IS_EXACTLY_SM_120)
+#    define _NV_TARGET_BOOL___NV_IS_EXACTLY_SM_120 1
+#  else
+#    define _NV_TARGET_BOOL___NV_IS_EXACTLY_SM_120 0
+#  endif
+
 // Re-enable sm_90a support in nvcc.
 #  undef NV_HAS_FEATURE_SM_90a
 #  define NV_HAS_FEATURE_SM_90a __NV_HAS_FEATURE_SM_90a
@@ -529,6 +544,12 @@
 #    define _NV_TARGET_BOOL___NV_PROVIDES_SM_101 0
 #  endif
 
+#  if (_NV_TARGET___NV_PROVIDES_SM_120)
+#    define _NV_TARGET_BOOL___NV_PROVIDES_SM_120 1
+#  else
+#    define _NV_TARGET_BOOL___NV_PROVIDES_SM_120 0
+#  endif
+
 #  define _NV_ARCH_COND_CAT1(cond) _NV_TARGET_BOOL_##cond
 #  define _NV_ARCH_COND_CAT(cond)  _NV_EVAL(_NV_ARCH_COND_CAT1(cond))
 
diff --git a/libcudacxx/include/nv/target b/libcudacxx/include/nv/target
index d8617220c84..4b77011243f 100644
--- a/libcudacxx/include/nv/target
+++ b/libcudacxx/include/nv/target
@@ -68,9 +68,10 @@ constexpr base_int_t sm_89_bit  = 1 << 15;
 constexpr base_int_t sm_90_bit  = 1 << 16;
 constexpr base_int_t sm_100_bit = 1 << 17;
 constexpr base_int_t sm_101_bit = 1 << 18;
+constexpr base_int_t sm_120_bit = 1 << 19;
 constexpr base_int_t all_devices =
   sm_35_bit | sm_37_bit | sm_50_bit | sm_52_bit | sm_53_bit | sm_60_bit | sm_61_bit | sm_62_bit | sm_70_bit | sm_72_bit
-  | sm_75_bit | sm_80_bit | sm_86_bit | sm_87_bit | sm_89_bit | sm_90_bit | sm_100_bit | sm_101_bit;
+  | sm_75_bit | sm_80_bit | sm_86_bit | sm_87_bit | sm_89_bit | sm_90_bit | sm_100_bit | sm_101_bit | sm_120_bit;
 
 // Store a set of targets as a set of bits
 struct _NV_BITSET_ATTRIBUTE target_description
@@ -103,6 +104,7 @@ enum class sm_selector : base_int_t
   sm_90  = 90,
   sm_100 = 100,
   sm_101 = 101,
+  sm_120 = 120,
 };
 
 constexpr base_int_t toint(sm_selector a)
@@ -130,12 +132,14 @@ constexpr base_int_t bitexact(sm_selector a)
        : toint(a) == 90  ? sm_90_bit
        : toint(a) == 100 ? sm_100_bit
        : toint(a) == 101 ? sm_101_bit
+       : toint(a) == 120 ? sm_120_bit
                          : 0;
 }
 
 constexpr base_int_t bitrounddown(sm_selector a)
 {
-  return toint(a) >= 101 ? sm_101_bit
+  return toint(a) >= 120 ? sm_120_bit
+       : toint(a) >= 101 ? sm_101_bit
        : toint(a) >= 100 ? sm_100_bit
        : toint(a) >= 90  ? sm_90_bit
        : toint(a) >= 89  ? sm_89_bit
@@ -214,6 +218,7 @@ constexpr sm_selector sm_89  = sm_selector::sm_89;
 constexpr sm_selector sm_90  = sm_selector::sm_90;
 constexpr sm_selector sm_100 = sm_selector::sm_100;
 constexpr sm_selector sm_101 = sm_selector::sm_101;
+constexpr sm_selector sm_120 = sm_selector::sm_120;
 
 using detail::is_exactly;
 using detail::provides;

From 3e888d8fd7953d595af016eacd89af610fb624e6 Mon Sep 17 00:00:00 2001
From: Bernhard Manfred Gruber <bernhardmgruber@gmail.com>
Date: Thu, 30 Jan 2025 09:10:00 +0100
Subject: [PATCH 16/33] PTX: Remove internal instructions (#3583)

* barrier.cluster.aligned: Remove
This is not supposed to be exposed in CCCL.

* elect.sync: Remove
Not ready for inclusion yet. This needs to handle the optional extra
output mask as well.

* mapa: Remove
This has compiler bugs. We should use intrinsics instead.

Co-authored-by: Allard Hendriksen <ahendriksen@nvidia.com>
---
 .../generated/barrier_cluster_aligned.rst     |  63 ---------
 .../ptx/instructions/generated/elect_sync.rst |  11 --
 .../ptx/instructions/generated/mapa.rst       |  14 --
 .../generated/barrier_cluster_aligned.h       | 130 ------------------
 .../__ptx/instructions/generated/elect_sync.h |  36 -----
 .../cuda/__ptx/instructions/generated/mapa.h  |  33 -----
 .../ptx/generated/barrier_cluster_aligned.h   |  61 --------
 .../cuda/ptx/generated/elect_sync.h           |  26 ----
 .../test/libcudacxx/cuda/ptx/generated/mapa.h |  27 ----
 9 files changed, 401 deletions(-)
 delete mode 100644 docs/libcudacxx/ptx/instructions/generated/barrier_cluster_aligned.rst
 delete mode 100644 docs/libcudacxx/ptx/instructions/generated/elect_sync.rst
 delete mode 100644 docs/libcudacxx/ptx/instructions/generated/mapa.rst
 delete mode 100644 libcudacxx/include/cuda/__ptx/instructions/generated/barrier_cluster_aligned.h
 delete mode 100644 libcudacxx/include/cuda/__ptx/instructions/generated/elect_sync.h
 delete mode 100644 libcudacxx/include/cuda/__ptx/instructions/generated/mapa.h
 delete mode 100644 libcudacxx/test/libcudacxx/cuda/ptx/generated/barrier_cluster_aligned.h
 delete mode 100644 libcudacxx/test/libcudacxx/cuda/ptx/generated/elect_sync.h
 delete mode 100644 libcudacxx/test/libcudacxx/cuda/ptx/generated/mapa.h

diff --git a/docs/libcudacxx/ptx/instructions/generated/barrier_cluster_aligned.rst b/docs/libcudacxx/ptx/instructions/generated/barrier_cluster_aligned.rst
deleted file mode 100644
index a24093ac7b6..00000000000
--- a/docs/libcudacxx/ptx/instructions/generated/barrier_cluster_aligned.rst
+++ /dev/null
@@ -1,63 +0,0 @@
-..
-   This file was automatically generated. Do not edit.
-
-barrier.cluster.arrive.aligned
-^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-.. code:: cuda
-
-   // barrier.cluster.arrive.aligned; // PTX ISA 78, SM_90
-   // .aligned   = { .aligned }
-   // Marked volatile and as clobbering memory
-   template <typename = void>
-   __device__ static inline void barrier_cluster_arrive(
-     cuda::ptx::dot_aligned_t);
-
-barrier.cluster.wait.aligned
-^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-.. code:: cuda
-
-   // barrier.cluster.wait.aligned; // PTX ISA 78, SM_90
-   // .aligned   = { .aligned }
-   // Marked volatile and as clobbering memory
-   template <typename = void>
-   __device__ static inline void barrier_cluster_wait(
-     cuda::ptx::dot_aligned_t);
-
-barrier.cluster.arrive.release.aligned
-^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-.. code:: cuda
-
-   // barrier.cluster.arrive.sem.aligned; // PTX ISA 80, SM_90
-   // .sem       = { .release }
-   // .aligned   = { .aligned }
-   // Marked volatile and as clobbering memory
-   template <typename = void>
-   __device__ static inline void barrier_cluster_arrive(
-     cuda::ptx::sem_release_t,
-     cuda::ptx::dot_aligned_t);
-
-barrier.cluster.arrive.relaxed.aligned
-^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-.. code:: cuda
-
-   // barrier.cluster.arrive.sem.aligned; // PTX ISA 80, SM_90
-   // .sem       = { .relaxed }
-   // .aligned   = { .aligned }
-   // Marked volatile
-   template <typename = void>
-   __device__ static inline void barrier_cluster_arrive(
-     cuda::ptx::sem_relaxed_t,
-     cuda::ptx::dot_aligned_t);
-
-barrier.cluster.wait.acquire.aligned
-^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-.. code:: cuda
-
-   // barrier.cluster.wait.sem.aligned; // PTX ISA 80, SM_90
-   // .sem       = { .acquire }
-   // .aligned   = { .aligned }
-   // Marked volatile and as clobbering memory
-   template <typename = void>
-   __device__ static inline void barrier_cluster_wait(
-     cuda::ptx::sem_acquire_t,
-     cuda::ptx::dot_aligned_t);
diff --git a/docs/libcudacxx/ptx/instructions/generated/elect_sync.rst b/docs/libcudacxx/ptx/instructions/generated/elect_sync.rst
deleted file mode 100644
index bc909c54319..00000000000
--- a/docs/libcudacxx/ptx/instructions/generated/elect_sync.rst
+++ /dev/null
@@ -1,11 +0,0 @@
-..
-   This file was automatically generated. Do not edit.
-
-elect.sync
-^^^^^^^^^^
-.. code:: cuda
-
-   // elect.sync _|is_elected, membermask; // PTX ISA 80, SM_90
-   template <typename = void>
-   __device__ static inline bool elect_sync(
-     const uint32_t& membermask);
diff --git a/docs/libcudacxx/ptx/instructions/generated/mapa.rst b/docs/libcudacxx/ptx/instructions/generated/mapa.rst
deleted file mode 100644
index 4ffc70d85d9..00000000000
--- a/docs/libcudacxx/ptx/instructions/generated/mapa.rst
+++ /dev/null
@@ -1,14 +0,0 @@
-..
-   This file was automatically generated. Do not edit.
-
-mapa.shared::cluster.u32
-^^^^^^^^^^^^^^^^^^^^^^^^
-.. code:: cuda
-
-   // mapa.space.u32  dest, addr, target_cta; // PTX ISA 78, SM_90
-   // .space     = { .shared::cluster }
-   template <typename Tp>
-   __device__ static inline Tp* mapa(
-     cuda::ptx::space_cluster_t,
-     const Tp* addr,
-     uint32_t target_cta);
diff --git a/libcudacxx/include/cuda/__ptx/instructions/generated/barrier_cluster_aligned.h b/libcudacxx/include/cuda/__ptx/instructions/generated/barrier_cluster_aligned.h
deleted file mode 100644
index 80fe3796e69..00000000000
--- a/libcudacxx/include/cuda/__ptx/instructions/generated/barrier_cluster_aligned.h
+++ /dev/null
@@ -1,130 +0,0 @@
-// This file was automatically generated. Do not edit.
-
-#ifndef _CUDA_PTX_GENERATED_BARRIER_CLUSTER_ALIGNED_H_
-#define _CUDA_PTX_GENERATED_BARRIER_CLUSTER_ALIGNED_H_
-
-/*
-// barrier.cluster.arrive.aligned; // PTX ISA 78, SM_90
-// .aligned   = { .aligned }
-// Marked volatile and as clobbering memory
-template <typename = void>
-__device__ static inline void barrier_cluster_arrive(
-  cuda::ptx::dot_aligned_t);
-*/
-#if __cccl_ptx_isa >= 780
-extern "C" _CCCL_DEVICE void __cuda_ptx_barrier_cluster_arrive_is_not_supported_before_SM_90__();
-template <typename = void>
-_CCCL_DEVICE static inline void barrier_cluster_arrive(dot_aligned_t)
-{
-// __aligned == aligned (due to parameter type constraint)
-#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
-  asm volatile("barrier.cluster.arrive.aligned;" : : : "memory");
-#  else
-  // Unsupported architectures will have a linker error with a semi-decent error message
-  __cuda_ptx_barrier_cluster_arrive_is_not_supported_before_SM_90__();
-#  endif
-}
-#endif // __cccl_ptx_isa >= 780
-
-/*
-// barrier.cluster.wait.aligned; // PTX ISA 78, SM_90
-// .aligned   = { .aligned }
-// Marked volatile and as clobbering memory
-template <typename = void>
-__device__ static inline void barrier_cluster_wait(
-  cuda::ptx::dot_aligned_t);
-*/
-#if __cccl_ptx_isa >= 780
-extern "C" _CCCL_DEVICE void __cuda_ptx_barrier_cluster_wait_is_not_supported_before_SM_90__();
-template <typename = void>
-_CCCL_DEVICE static inline void barrier_cluster_wait(dot_aligned_t)
-{
-// __aligned == aligned (due to parameter type constraint)
-#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
-  asm volatile("barrier.cluster.wait.aligned;" : : : "memory");
-#  else
-  // Unsupported architectures will have a linker error with a semi-decent error message
-  __cuda_ptx_barrier_cluster_wait_is_not_supported_before_SM_90__();
-#  endif
-}
-#endif // __cccl_ptx_isa >= 780
-
-/*
-// barrier.cluster.arrive.sem.aligned; // PTX ISA 80, SM_90
-// .sem       = { .release }
-// .aligned   = { .aligned }
-// Marked volatile and as clobbering memory
-template <typename = void>
-__device__ static inline void barrier_cluster_arrive(
-  cuda::ptx::sem_release_t,
-  cuda::ptx::dot_aligned_t);
-*/
-#if __cccl_ptx_isa >= 800
-extern "C" _CCCL_DEVICE void __cuda_ptx_barrier_cluster_arrive_is_not_supported_before_SM_90__();
-template <typename = void>
-_CCCL_DEVICE static inline void barrier_cluster_arrive(sem_release_t, dot_aligned_t)
-{
-// __sem == sem_release (due to parameter type constraint)
-// __aligned == aligned (due to parameter type constraint)
-#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
-  asm volatile("barrier.cluster.arrive.release.aligned;" : : : "memory");
-#  else
-  // Unsupported architectures will have a linker error with a semi-decent error message
-  __cuda_ptx_barrier_cluster_arrive_is_not_supported_before_SM_90__();
-#  endif
-}
-#endif // __cccl_ptx_isa >= 800
-
-/*
-// barrier.cluster.arrive.sem.aligned; // PTX ISA 80, SM_90
-// .sem       = { .relaxed }
-// .aligned   = { .aligned }
-// Marked volatile
-template <typename = void>
-__device__ static inline void barrier_cluster_arrive(
-  cuda::ptx::sem_relaxed_t,
-  cuda::ptx::dot_aligned_t);
-*/
-#if __cccl_ptx_isa >= 800
-extern "C" _CCCL_DEVICE void __cuda_ptx_barrier_cluster_arrive_is_not_supported_before_SM_90__();
-template <typename = void>
-_CCCL_DEVICE static inline void barrier_cluster_arrive(sem_relaxed_t, dot_aligned_t)
-{
-// __sem == sem_relaxed (due to parameter type constraint)
-// __aligned == aligned (due to parameter type constraint)
-#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
-  asm volatile("barrier.cluster.arrive.relaxed.aligned;" : : :);
-#  else
-  // Unsupported architectures will have a linker error with a semi-decent error message
-  __cuda_ptx_barrier_cluster_arrive_is_not_supported_before_SM_90__();
-#  endif
-}
-#endif // __cccl_ptx_isa >= 800
-
-/*
-// barrier.cluster.wait.sem.aligned; // PTX ISA 80, SM_90
-// .sem       = { .acquire }
-// .aligned   = { .aligned }
-// Marked volatile and as clobbering memory
-template <typename = void>
-__device__ static inline void barrier_cluster_wait(
-  cuda::ptx::sem_acquire_t,
-  cuda::ptx::dot_aligned_t);
-*/
-#if __cccl_ptx_isa >= 800
-extern "C" _CCCL_DEVICE void __cuda_ptx_barrier_cluster_wait_is_not_supported_before_SM_90__();
-template <typename = void>
-_CCCL_DEVICE static inline void barrier_cluster_wait(sem_acquire_t, dot_aligned_t)
-{
-// __sem == sem_acquire (due to parameter type constraint)
-// __aligned == aligned (due to parameter type constraint)
-#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
-  asm volatile("barrier.cluster.wait.acquire.aligned;" : : : "memory");
-#  else
-  // Unsupported architectures will have a linker error with a semi-decent error message
-  __cuda_ptx_barrier_cluster_wait_is_not_supported_before_SM_90__();
-#  endif
-}
-#endif // __cccl_ptx_isa >= 800
-
-#endif // _CUDA_PTX_GENERATED_BARRIER_CLUSTER_ALIGNED_H_
diff --git a/libcudacxx/include/cuda/__ptx/instructions/generated/elect_sync.h b/libcudacxx/include/cuda/__ptx/instructions/generated/elect_sync.h
deleted file mode 100644
index e8691178f14..00000000000
--- a/libcudacxx/include/cuda/__ptx/instructions/generated/elect_sync.h
+++ /dev/null
@@ -1,36 +0,0 @@
-// This file was automatically generated. Do not edit.
-
-#ifndef _CUDA_PTX_GENERATED_ELECT_SYNC_H_
-#define _CUDA_PTX_GENERATED_ELECT_SYNC_H_
-
-/*
-// elect.sync _|is_elected, membermask; // PTX ISA 80, SM_90
-template <typename = void>
-__device__ static inline bool elect_sync(
-  const uint32_t& membermask);
-*/
-#if __cccl_ptx_isa >= 800
-extern "C" _CCCL_DEVICE void __cuda_ptx_elect_sync_is_not_supported_before_SM_90__();
-template <typename = void>
-_CCCL_DEVICE static inline bool elect_sync(const _CUDA_VSTD::uint32_t& __membermask)
-{
-#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
-  _CUDA_VSTD::uint32_t __is_elected;
-  asm volatile(
-    "{\n\t .reg .pred P_OUT; \n\t"
-    "elect.sync _|P_OUT, %1;\n\t"
-    "selp.b32 %0, 1, 0, P_OUT; \n"
-    "}"
-    : "=r"(__is_elected)
-    : "r"(__membermask)
-    :);
-  return static_cast<bool>(__is_elected);
-#  else
-  // Unsupported architectures will have a linker error with a semi-decent error message
-  __cuda_ptx_elect_sync_is_not_supported_before_SM_90__();
-  return false;
-#  endif
-}
-#endif // __cccl_ptx_isa >= 800
-
-#endif // _CUDA_PTX_GENERATED_ELECT_SYNC_H_
diff --git a/libcudacxx/include/cuda/__ptx/instructions/generated/mapa.h b/libcudacxx/include/cuda/__ptx/instructions/generated/mapa.h
deleted file mode 100644
index f93c8a62157..00000000000
--- a/libcudacxx/include/cuda/__ptx/instructions/generated/mapa.h
+++ /dev/null
@@ -1,33 +0,0 @@
-// This file was automatically generated. Do not edit.
-
-#ifndef _CUDA_PTX_GENERATED_MAPA_H_
-#define _CUDA_PTX_GENERATED_MAPA_H_
-
-/*
-// mapa.space.u32  dest, addr, target_cta; // PTX ISA 78, SM_90
-// .space     = { .shared::cluster }
-template <typename Tp>
-__device__ static inline Tp* mapa(
-  cuda::ptx::space_cluster_t,
-  const Tp* addr,
-  uint32_t target_cta);
-*/
-#if __cccl_ptx_isa >= 780
-extern "C" _CCCL_DEVICE void __cuda_ptx_mapa_is_not_supported_before_SM_90__();
-template <typename _Tp>
-_CCCL_DEVICE static inline _Tp* mapa(space_cluster_t, const _Tp* __addr, _CUDA_VSTD::uint32_t __target_cta)
-{
-// __space == space_cluster (due to parameter type constraint)
-#  if _CCCL_CUDA_COMPILER(NVHPC) || __CUDA_ARCH__ >= 900
-  _CUDA_VSTD::uint32_t __dest;
-  asm("mapa.shared::cluster.u32  %0, %1, %2;" : "=r"(__dest) : "r"(__as_ptr_smem(__addr)), "r"(__target_cta) :);
-  return __from_ptr_dsmem<_Tp>(__dest);
-#  else
-  // Unsupported architectures will have a linker error with a semi-decent error message
-  __cuda_ptx_mapa_is_not_supported_before_SM_90__();
-  return __from_ptr_dsmem<_Tp>(0);
-#  endif
-}
-#endif // __cccl_ptx_isa >= 780
-
-#endif // _CUDA_PTX_GENERATED_MAPA_H_
diff --git a/libcudacxx/test/libcudacxx/cuda/ptx/generated/barrier_cluster_aligned.h b/libcudacxx/test/libcudacxx/cuda/ptx/generated/barrier_cluster_aligned.h
deleted file mode 100644
index 6f5a022dbc8..00000000000
--- a/libcudacxx/test/libcudacxx/cuda/ptx/generated/barrier_cluster_aligned.h
+++ /dev/null
@@ -1,61 +0,0 @@
-// This file was automatically generated. Do not edit.
-
-// We use a special strategy to force the generation of the PTX. This is mainly
-// a fight against dead-code-elimination in the NVVM layer.
-//
-// The reason we need this strategy is because certain older versions of ptxas
-// segfault when a non-sensical sequence of PTX is generated. So instead, we try
-// to force the instantiation and compilation to PTX of all the overloads of the
-// PTX wrapping functions.
-//
-// We do this by writing a function pointer of each overload to the kernel
-// parameter `fn_ptr`.
-//
-// Because `fn_ptr` is possibly visible outside this translation unit, the
-// compiler must compile all the functions which are stored.
-
-__global__ void test_barrier_cluster_aligned(void** fn_ptr)
-{
-#if __cccl_ptx_isa >= 780
-  NV_IF_TARGET(NV_PROVIDES_SM_90,
-               (
-                   // barrier.cluster.arrive.aligned;
-                   * fn_ptr++ = reinterpret_cast<void*>(
-                     static_cast<void (*)(cuda::ptx::dot_aligned_t)>(cuda::ptx::barrier_cluster_arrive));));
-#endif // __cccl_ptx_isa >= 780
-
-#if __cccl_ptx_isa >= 780
-  NV_IF_TARGET(NV_PROVIDES_SM_90,
-               (
-                   // barrier.cluster.wait.aligned;
-                   * fn_ptr++ = reinterpret_cast<void*>(
-                     static_cast<void (*)(cuda::ptx::dot_aligned_t)>(cuda::ptx::barrier_cluster_wait));));
-#endif // __cccl_ptx_isa >= 780
-
-#if __cccl_ptx_isa >= 800
-  NV_IF_TARGET(
-    NV_PROVIDES_SM_90,
-    (
-        // barrier.cluster.arrive.release.aligned;
-        * fn_ptr++ = reinterpret_cast<void*>(static_cast<void (*)(cuda::ptx::sem_release_t, cuda::ptx::dot_aligned_t)>(
-          cuda::ptx::barrier_cluster_arrive));));
-#endif // __cccl_ptx_isa >= 800
-
-#if __cccl_ptx_isa >= 800
-  NV_IF_TARGET(
-    NV_PROVIDES_SM_90,
-    (
-        // barrier.cluster.arrive.relaxed.aligned;
-        * fn_ptr++ = reinterpret_cast<void*>(static_cast<void (*)(cuda::ptx::sem_relaxed_t, cuda::ptx::dot_aligned_t)>(
-          cuda::ptx::barrier_cluster_arrive));));
-#endif // __cccl_ptx_isa >= 800
-
-#if __cccl_ptx_isa >= 800
-  NV_IF_TARGET(
-    NV_PROVIDES_SM_90,
-    (
-        // barrier.cluster.wait.acquire.aligned;
-        * fn_ptr++ = reinterpret_cast<void*>(static_cast<void (*)(cuda::ptx::sem_acquire_t, cuda::ptx::dot_aligned_t)>(
-          cuda::ptx::barrier_cluster_wait));));
-#endif // __cccl_ptx_isa >= 800
-}
diff --git a/libcudacxx/test/libcudacxx/cuda/ptx/generated/elect_sync.h b/libcudacxx/test/libcudacxx/cuda/ptx/generated/elect_sync.h
deleted file mode 100644
index 298225881d1..00000000000
--- a/libcudacxx/test/libcudacxx/cuda/ptx/generated/elect_sync.h
+++ /dev/null
@@ -1,26 +0,0 @@
-// This file was automatically generated. Do not edit.
-
-// We use a special strategy to force the generation of the PTX. This is mainly
-// a fight against dead-code-elimination in the NVVM layer.
-//
-// The reason we need this strategy is because certain older versions of ptxas
-// segfault when a non-sensical sequence of PTX is generated. So instead, we try
-// to force the instantiation and compilation to PTX of all the overloads of the
-// PTX wrapping functions.
-//
-// We do this by writing a function pointer of each overload to the kernel
-// parameter `fn_ptr`.
-//
-// Because `fn_ptr` is possibly visible outside this translation unit, the
-// compiler must compile all the functions which are stored.
-
-__global__ void test_elect_sync(void** fn_ptr)
-{
-#if __cccl_ptx_isa >= 800
-  NV_IF_TARGET(
-    NV_PROVIDES_SM_90,
-    (
-        // elect.sync _|is_elected, membermask;
-        * fn_ptr++ = reinterpret_cast<void*>(static_cast<bool (*)(const uint32_t&)>(cuda::ptx::elect_sync));));
-#endif // __cccl_ptx_isa >= 800
-}
diff --git a/libcudacxx/test/libcudacxx/cuda/ptx/generated/mapa.h b/libcudacxx/test/libcudacxx/cuda/ptx/generated/mapa.h
deleted file mode 100644
index 9160be1fe2d..00000000000
--- a/libcudacxx/test/libcudacxx/cuda/ptx/generated/mapa.h
+++ /dev/null
@@ -1,27 +0,0 @@
-// This file was automatically generated. Do not edit.
-
-// We use a special strategy to force the generation of the PTX. This is mainly
-// a fight against dead-code-elimination in the NVVM layer.
-//
-// The reason we need this strategy is because certain older versions of ptxas
-// segfault when a non-sensical sequence of PTX is generated. So instead, we try
-// to force the instantiation and compilation to PTX of all the overloads of the
-// PTX wrapping functions.
-//
-// We do this by writing a function pointer of each overload to the kernel
-// parameter `fn_ptr`.
-//
-// Because `fn_ptr` is possibly visible outside this translation unit, the
-// compiler must compile all the functions which are stored.
-
-__global__ void test_mapa(void** fn_ptr)
-{
-#if __cccl_ptx_isa >= 780
-  NV_IF_TARGET(
-    NV_PROVIDES_SM_90,
-    (
-        // mapa.shared::cluster.u32  dest, addr, target_cta;
-        * fn_ptr++ = reinterpret_cast<void*>(
-          static_cast<uint64_t* (*) (cuda::ptx::space_cluster_t, const uint64_t*, uint32_t)>(cuda::ptx::mapa));));
-#endif // __cccl_ptx_isa >= 780
-}

From 15a011658172b1b63bfac8a96fb49fec6d6af92a Mon Sep 17 00:00:00 2001
From: Nader Al Awar <naderalawar@gmail.com>
Date: Thu, 30 Jan 2025 03:03:11 -0600
Subject: [PATCH 17/33] Add dynamic CUB dispatch for merge_sort (#3525)

* Add `dependent_launch` parameter to `TripleChevronFactory`
* Add `ItemsPerTile()` method to `PolicyWrapper`
* Add `MergeSortPolicyWrapper`
* Add `KernelSource` and use `launcher_factory` to launch `merge_sort` kernels
* Move the vsmem_helper to kernel source and read `BlockThreads` from there instead of the policy directly
* Make `BlockThreads` templated on the policy type
* Obtain `ItemsPerTile` from the kernel source through vsmem helper
* Change vsmem indirection so that it is its own template parameter passed to `DispatchMergeSort`
* Use `_CCCL_HOST_DEVICE` for RTC
---
 cub/cub/detail/launcher/cuda_runtime.cuh      |   6 +-
 .../device/dispatch/dispatch_merge_sort.cuh   | 214 +++++++++++-------
 .../device/dispatch/kernels/merge_sort.cuh    |  22 ++
 .../dispatch/tuning/tuning_merge_sort.cuh     |  32 ++-
 cub/cub/util_device.cuh                       |   5 +
 5 files changed, 189 insertions(+), 90 deletions(-)

diff --git a/cub/cub/detail/launcher/cuda_runtime.cuh b/cub/cub/detail/launcher/cuda_runtime.cuh
index 81ef450f424..f59c26d7fbb 100644
--- a/cub/cub/detail/launcher/cuda_runtime.cuh
+++ b/cub/cub/detail/launcher/cuda_runtime.cuh
@@ -21,10 +21,10 @@ namespace detail
 
 struct TripleChevronFactory
 {
-  CUB_RUNTIME_FUNCTION THRUST_NS_QUALIFIER::cuda_cub::launcher::triple_chevron
-  operator()(dim3 grid, dim3 block, _CUDA_VSTD::size_t shared_mem, cudaStream_t stream) const
+  CUB_RUNTIME_FUNCTION THRUST_NS_QUALIFIER::cuda_cub::launcher::triple_chevron operator()(
+    dim3 grid, dim3 block, _CUDA_VSTD::size_t shared_mem, cudaStream_t stream, bool dependent_launch = false) const
   {
-    return THRUST_NS_QUALIFIER::cuda_cub::launcher::triple_chevron(grid, block, shared_mem, stream);
+    return THRUST_NS_QUALIFIER::cuda_cub::launcher::triple_chevron(grid, block, shared_mem, stream, dependent_launch);
   }
 
   CUB_RUNTIME_FUNCTION cudaError_t PtxVersion(int& version)
diff --git a/cub/cub/device/dispatch/dispatch_merge_sort.cuh b/cub/cub/device/dispatch/dispatch_merge_sort.cuh
index 056522e162d..98a4b40e8f8 100644
--- a/cub/cub/device/dispatch/dispatch_merge_sort.cuh
+++ b/cub/cub/device/dispatch/dispatch_merge_sort.cuh
@@ -46,7 +46,6 @@
 #include <cub/util_vsmem.cuh>
 
 #include <thrust/detail/integer_math.h>
-#include <thrust/system/cuda/detail/core/triple_chevron_launch.h>
 
 #include <cuda/std/__algorithm/max.h>
 #include <cuda/std/__algorithm/min.h>
@@ -54,24 +53,89 @@
 
 CUB_NAMESPACE_BEGIN
 
-/*******************************************************************************
- * Policy
- ******************************************************************************/
-
-template <typename KeyInputIteratorT,
+namespace detail::merge_sort
+{
+template <typename MaxPolicyT,
+          typename KeyInputIteratorT,
           typename ValueInputIteratorT,
           typename KeyIteratorT,
           typename ValueIteratorT,
           typename OffsetT,
-          typename CompareOpT,
-          typename PolicyHub = detail::merge_sort::policy_hub<KeyIteratorT>>
+          typename CompareOpT>
+struct DeviceMergeSortKernelSource
+{
+  using KeyT   = cub::detail::value_t<KeyIteratorT>;
+  using ValueT = cub::detail::value_t<ValueIteratorT>;
+
+  CUB_DEFINE_KERNEL_GETTER(
+    MergeSortBlockSortKernel,
+    DeviceMergeSortBlockSortKernel<
+      MaxPolicyT,
+      KeyInputIteratorT,
+      ValueInputIteratorT,
+      KeyIteratorT,
+      ValueIteratorT,
+      OffsetT,
+      CompareOpT,
+      KeyT,
+      ValueT>);
+
+  CUB_DEFINE_KERNEL_GETTER(MergeSortPartitionKernel,
+                           DeviceMergeSortPartitionKernel<KeyIteratorT, OffsetT, CompareOpT, KeyT>);
+
+  CUB_DEFINE_KERNEL_GETTER(
+    MergeSortMergeKernel,
+    DeviceMergeSortMergeKernel<MaxPolicyT,
+                               KeyInputIteratorT,
+                               ValueInputIteratorT,
+                               KeyIteratorT,
+                               ValueIteratorT,
+                               OffsetT,
+                               CompareOpT,
+                               KeyT,
+                               ValueT>);
+};
+
+} // namespace detail::merge_sort
+
+/*******************************************************************************
+ * Policy
+ ******************************************************************************/
+
+template <
+  typename KeyInputIteratorT,
+  typename ValueInputIteratorT,
+  typename KeyIteratorT,
+  typename ValueIteratorT,
+  typename OffsetT,
+  typename CompareOpT,
+  typename PolicyHub    = detail::merge_sort::policy_hub<KeyIteratorT>,
+  typename KernelSource = detail::merge_sort::DeviceMergeSortKernelSource<
+    typename PolicyHub::MaxPolicy,
+    KeyInputIteratorT,
+    ValueInputIteratorT,
+    KeyIteratorT,
+    ValueIteratorT,
+    OffsetT,
+    CompareOpT>,
+  typename KernelLauncherFactory = detail::TripleChevronFactory,
+  typename VSMemHelperPolicyT    = detail::merge_sort::merge_sort_vsmem_helper_t<
+       typename PolicyHub::MaxPolicy::MergeSortPolicy,
+       KeyInputIteratorT,
+       ValueInputIteratorT,
+       KeyIteratorT,
+       ValueIteratorT,
+       OffsetT,
+       CompareOpT,
+       cub::detail::value_t<KeyIteratorT>,
+       cub::detail::value_t<ValueIteratorT>>>
 struct DispatchMergeSort
 {
   using KeyT   = cub::detail::value_t<KeyIteratorT>;
   using ValueT = cub::detail::value_t<ValueIteratorT>;
 
   /// Whether or not there are values to be trucked along with keys
-  static constexpr bool KEYS_ONLY = std::is_same<ValueT, NullType>::value;
+  static constexpr bool KEYS_ONLY = ::cuda::std::is_same_v<ValueT, NullType>;
 
   // Problem state
 
@@ -106,6 +170,12 @@ struct DispatchMergeSort
 
   int ptx_version;
 
+  KernelSource kernel_source;
+
+  KernelLauncherFactory launcher_factory;
+
+  VSMemHelperPolicyT vsmem_helper;
+
   // Constructor
   CUB_RUNTIME_FUNCTION _CCCL_FORCEINLINE DispatchMergeSort(
     void* d_temp_storage,
@@ -117,7 +187,10 @@ struct DispatchMergeSort
     OffsetT num_items,
     CompareOpT compare_op,
     cudaStream_t stream,
-    int ptx_version)
+    int ptx_version,
+    KernelSource kernel_source             = {},
+    KernelLauncherFactory launcher_factory = {},
+    VSMemHelperPolicyT vsmem_helper        = {})
       : d_temp_storage(d_temp_storage)
       , temp_storage_bytes(temp_storage_bytes)
       , d_input_keys(d_input_keys)
@@ -128,28 +201,15 @@ struct DispatchMergeSort
       , compare_op(compare_op)
       , stream(stream)
       , ptx_version(ptx_version)
+      , kernel_source(kernel_source)
+      , launcher_factory(launcher_factory)
+      , vsmem_helper(vsmem_helper)
   {}
 
   // Invocation
   template <typename ActivePolicyT>
-  CUB_RUNTIME_FUNCTION _CCCL_FORCEINLINE cudaError_t Invoke()
+  CUB_RUNTIME_FUNCTION _CCCL_FORCEINLINE cudaError_t Invoke(ActivePolicyT policy = {})
   {
-    using MergePolicyT = typename ActivePolicyT::MergeSortPolicy;
-
-    using merge_sort_helper_t = detail::merge_sort::merge_sort_vsmem_helper_t<
-      MergePolicyT,
-      KeyInputIteratorT,
-      ValueInputIteratorT,
-      KeyIteratorT,
-      ValueIteratorT,
-      OffsetT,
-      CompareOpT,
-      KeyT,
-      ValueT>;
-
-    using BlockSortVSmemHelperT  = detail::vsmem_helper_impl<typename merge_sort_helper_t::block_sort_agent_t>;
-    using MergeAgentVSmemHelperT = detail::vsmem_helper_impl<typename merge_sort_helper_t::merge_agent_t>;
-
     cudaError error = cudaSuccess;
 
     if (num_items == 0)
@@ -163,8 +223,9 @@ struct DispatchMergeSort
 
     do
     {
-      constexpr auto tile_size = merge_sort_helper_t::policy_t::ITEMS_PER_TILE;
-      const auto num_tiles     = ::cuda::ceil_div(num_items, tile_size);
+      auto wrapped_policy  = detail::merge_sort::MakeMergeSortPolicyWrapper(policy);
+      const auto tile_size = vsmem_helper.ItemsPerTile(wrapped_policy.MergeSort());
+      const auto num_tiles = ::cuda::ceil_div(num_items, tile_size);
 
       const auto merge_partitions_size         = static_cast<std::size_t>(1 + num_tiles) * sizeof(OffsetT);
       const auto temporary_keys_storage_size   = static_cast<std::size_t>(num_items * sizeof(KeyT));
@@ -174,8 +235,8 @@ struct DispatchMergeSort
        * Merge sort supports large types, which can lead to excessive shared memory size requirements. In these cases,
        * merge sort allocates virtual shared memory that resides in global memory.
        */
-      const std::size_t block_sort_smem_size       = num_tiles * BlockSortVSmemHelperT::vsmem_per_block;
-      const std::size_t merge_smem_size            = num_tiles * MergeAgentVSmemHelperT::vsmem_per_block;
+      const std::size_t block_sort_smem_size       = num_tiles * vsmem_helper.block_sort_vsmem_per_block();
+      const std::size_t merge_smem_size            = num_tiles * vsmem_helper.merge_vsmem_per_block();
       const std::size_t virtual_shared_memory_size = (::cuda::std::max)(block_sort_smem_size, merge_smem_size);
 
       void* allocations[4]            = {nullptr, nullptr, nullptr, nullptr};
@@ -214,29 +275,19 @@ struct DispatchMergeSort
       auto items_buffer     = static_cast<ValueT*>(allocations[2]);
 
       // Invoke DeviceMergeSortBlockSortKernel
-      THRUST_NS_QUALIFIER::cuda_cub::launcher::triple_chevron(
-        static_cast<int>(num_tiles), merge_sort_helper_t::policy_t::BLOCK_THREADS, 0, stream, true)
-        .doit(
-          detail::merge_sort::DeviceMergeSortBlockSortKernel<
-            typename PolicyHub::MaxPolicy,
-            KeyInputIteratorT,
-            ValueInputIteratorT,
-            KeyIteratorT,
-            ValueIteratorT,
-            OffsetT,
-            CompareOpT,
-            KeyT,
-            ValueT>,
-          ping,
-          d_input_keys,
-          d_input_items,
-          d_output_keys,
-          d_output_items,
-          num_items,
-          keys_buffer,
-          items_buffer,
-          compare_op,
-          cub::detail::vsmem_t{allocations[3]});
+      launcher_factory(
+        static_cast<int>(num_tiles), vsmem_helper.BlockThreads(wrapped_policy.MergeSort()), 0, stream, true)
+        .doit(kernel_source.MergeSortBlockSortKernel(),
+              ping,
+              d_input_keys,
+              d_input_items,
+              d_output_keys,
+              d_output_items,
+              num_items,
+              keys_buffer,
+              items_buffer,
+              compare_op,
+              cub::detail::vsmem_t{allocations[3]});
 
       error = CubDebug(detail::DebugSyncStream(stream));
       if (cudaSuccess != error)
@@ -273,9 +324,8 @@ struct DispatchMergeSort
         const OffsetT target_merged_tiles_number = OffsetT(2) << pass;
 
         // Partition
-        THRUST_NS_QUALIFIER::cuda_cub::launcher::triple_chevron(
-          partition_grid_size, threads_per_partition_block, 0, stream, true)
-          .doit(detail::merge_sort::DeviceMergeSortPartitionKernel<KeyIteratorT, OffsetT, CompareOpT, KeyT>,
+        launcher_factory(partition_grid_size, threads_per_partition_block, 0, stream, true)
+          .doit(kernel_source.MergeSortPartitionKernel(),
                 ping,
                 d_output_keys,
                 keys_buffer,
@@ -300,29 +350,19 @@ struct DispatchMergeSort
         }
 
         // Merge
-        THRUST_NS_QUALIFIER::cuda_cub::launcher::triple_chevron(
-          static_cast<int>(num_tiles), static_cast<int>(merge_sort_helper_t::policy_t::BLOCK_THREADS), 0, stream, true)
-          .doit(
-            detail::merge_sort::DeviceMergeSortMergeKernel<
-              typename PolicyHub::MaxPolicy,
-              KeyInputIteratorT,
-              ValueInputIteratorT,
-              KeyIteratorT,
-              ValueIteratorT,
-              OffsetT,
-              CompareOpT,
-              KeyT,
-              ValueT>,
-            ping,
-            d_output_keys,
-            d_output_items,
-            num_items,
-            keys_buffer,
-            items_buffer,
-            compare_op,
-            merge_partitions,
-            target_merged_tiles_number,
-            cub::detail::vsmem_t{allocations[3]});
+        launcher_factory(
+          static_cast<int>(num_tiles), vsmem_helper.BlockThreads(wrapped_policy.MergeSort()), 0, stream, true)
+          .doit(kernel_source.MergeSortMergeKernel(),
+                ping,
+                d_output_keys,
+                d_output_items,
+                num_items,
+                keys_buffer,
+                items_buffer,
+                compare_op,
+                merge_partitions,
+                target_merged_tiles_number,
+                cub::detail::vsmem_t{allocations[3]});
 
         error = CubDebug(detail::DebugSyncStream(stream));
         if (cudaSuccess != error)
@@ -342,6 +382,7 @@ struct DispatchMergeSort
     return error;
   }
 
+  template <typename MaxPolicyT = typename PolicyHub::MaxPolicy>
   CUB_RUNTIME_FUNCTION _CCCL_FORCEINLINE static cudaError_t Dispatch(
     void* d_temp_storage,
     std::size_t& temp_storage_bytes,
@@ -351,7 +392,11 @@ struct DispatchMergeSort
     ValueIteratorT d_output_items,
     OffsetT num_items,
     CompareOpT compare_op,
-    cudaStream_t stream)
+    cudaStream_t stream,
+    KernelSource kernel_source             = {},
+    KernelLauncherFactory launcher_factory = {},
+    MaxPolicyT max_policy                  = {},
+    VSMemHelperPolicyT vsmem_helper        = {})
   {
     cudaError error = cudaSuccess;
     do
@@ -375,10 +420,13 @@ struct DispatchMergeSort
         num_items,
         compare_op,
         stream,
-        ptx_version);
+        ptx_version,
+        kernel_source,
+        launcher_factory,
+        vsmem_helper);
 
       // Dispatch to chained policy
-      error = CubDebug(PolicyHub::MaxPolicy::Invoke(ptx_version, dispatch));
+      error = CubDebug(max_policy.Invoke(ptx_version, dispatch));
       if (cudaSuccess != error)
       {
         break;
diff --git a/cub/cub/device/dispatch/kernels/merge_sort.cuh b/cub/cub/device/dispatch/kernels/merge_sort.cuh
index 1065313c20d..c9a8a61395a 100644
--- a/cub/cub/device/dispatch/kernels/merge_sort.cuh
+++ b/cub/cub/device/dispatch/kernels/merge_sort.cuh
@@ -116,6 +116,28 @@ public:
   using block_sort_agent_t =
     ::cuda::std::_If<uses_fallback_policy, fallback_block_sort_agent_t, default_block_sort_agent_t>;
   using merge_agent_t = ::cuda::std::_If<uses_fallback_policy, fallback_merge_agent_t, default_merge_agent_t>;
+
+  _CCCL_HOST_DEVICE static constexpr ::cuda::std::size_t block_sort_vsmem_per_block()
+  {
+    return detail::vsmem_helper_impl<block_sort_agent_t>::vsmem_per_block;
+  }
+
+  _CCCL_HOST_DEVICE static constexpr ::cuda::std::size_t merge_vsmem_per_block()
+  {
+    return detail::vsmem_helper_impl<merge_agent_t>::vsmem_per_block;
+  }
+
+  template <typename PolicyT>
+  _CCCL_HOST_DEVICE static constexpr int BlockThreads(PolicyT /*policy*/)
+  {
+    return policy_t::BLOCK_THREADS;
+  }
+
+  template <typename PolicyT>
+  _CCCL_HOST_DEVICE static constexpr int ItemsPerTile(PolicyT /*policy*/)
+  {
+    return policy_t::ITEMS_PER_TILE;
+  }
 };
 template <typename ChainedPolicyT,
           typename KeyInputIteratorT,
diff --git a/cub/cub/device/dispatch/tuning/tuning_merge_sort.cuh b/cub/cub/device/dispatch/tuning/tuning_merge_sort.cuh
index 29e98a3898a..2c93b1b1147 100644
--- a/cub/cub/device/dispatch/tuning/tuning_merge_sort.cuh
+++ b/cub/cub/device/dispatch/tuning/tuning_merge_sort.cuh
@@ -42,10 +42,34 @@
 
 CUB_NAMESPACE_BEGIN
 
-namespace detail
+namespace detail::merge_sort
 {
-namespace merge_sort
+
+template <typename PolicyT, typename = void>
+struct MergeSortPolicyWrapper : PolicyT
+{
+  CUB_RUNTIME_FUNCTION MergeSortPolicyWrapper(PolicyT base)
+      : PolicyT(base)
+  {}
+};
+
+template <typename StaticPolicyT>
+struct MergeSortPolicyWrapper<StaticPolicyT, ::cuda::std::void_t<typename StaticPolicyT::MergeSortPolicy>>
+    : StaticPolicyT
+{
+  CUB_RUNTIME_FUNCTION MergeSortPolicyWrapper(StaticPolicyT base)
+      : StaticPolicyT(base)
+  {}
+
+  CUB_DEFINE_SUB_POLICY_GETTER(MergeSort);
+};
+
+template <typename PolicyT>
+CUB_RUNTIME_FUNCTION MergeSortPolicyWrapper<PolicyT> MakeMergeSortPolicyWrapper(PolicyT policy)
 {
+  return MergeSortPolicyWrapper<PolicyT>{policy};
+}
+
 template <typename KeyIteratorT>
 struct policy_hub
 {
@@ -88,8 +112,8 @@ struct policy_hub
 
   using MaxPolicy = Policy600;
 };
-} // namespace merge_sort
-} // namespace detail
+
+} // namespace detail::merge_sort
 
 template <typename KeyIteratorT>
 using DeviceMergeSortPolicy CCCL_DEPRECATED_BECAUSE("This class is considered an implementation detail and it will be "
diff --git a/cub/cub/util_device.cuh b/cub/cub/util_device.cuh
index fd356b8f9e5..ca365b531fc 100644
--- a/cub/cub/util_device.cuh
+++ b/cub/cub/util_device.cuh
@@ -553,6 +553,11 @@ struct PolicyWrapper<
   {
     return StaticPolicyT::ITEMS_PER_THREAD;
   }
+
+  CUB_RUNTIME_FUNCTION static constexpr int ItemsPerTile()
+  {
+    return StaticPolicyT::ITEMS_PER_TILE;
+  }
 };
 
 template <typename PolicyT>

From 5ce5d28f0572d34126e00f0765977d8c54391e8e Mon Sep 17 00:00:00 2001
From: Bernhard Manfred Gruber <bernhardmgruber@gmail.com>
Date: Thu, 30 Jan 2025 10:52:13 +0100
Subject: [PATCH 18/33] PTX: Update existing instructions (#3584)

* mbarrier.expect_tx: Add missing source and test
It was already documented(!)

* cp.async.bulk.tensor: Add .{gather,scatter}4
* fence: Add .sync_restrict, .proxy.async.sync_restrict

Co-authored-by: Allard Hendriksen <ahendriksen@nvidia.com>
---
 .../ptx/instructions/cp_async_bulk_tensor.rst |  5 +++
 docs/libcudacxx/ptx/instructions/fence.rst    | 10 +++++
 .../__ptx/instructions/cp_async_bulk_tensor.h |  1 +
 .../include/cuda/__ptx/instructions/fence.h   |  2 +
 .../__ptx/instructions/mbarrier_expect_tx.h   | 37 +++++++++++++++++++
 libcudacxx/include/cuda/ptx                   |  1 +
 .../ptx.cp.async.bulk.tensor.compile.pass.cpp |  1 +
 .../cuda/ptx/ptx.fence.compile.pass.cpp       |  2 +
 .../ptx.mbarrier.expect_tx.compile.pass.cpp   | 22 +++++++++++
 9 files changed, 81 insertions(+)
 create mode 100644 libcudacxx/include/cuda/__ptx/instructions/mbarrier_expect_tx.h
 create mode 100644 libcudacxx/test/libcudacxx/cuda/ptx/ptx.mbarrier.expect_tx.compile.pass.cpp

diff --git a/docs/libcudacxx/ptx/instructions/cp_async_bulk_tensor.rst b/docs/libcudacxx/ptx/instructions/cp_async_bulk_tensor.rst
index bde3488bac9..8dc9def989b 100644
--- a/docs/libcudacxx/ptx/instructions/cp_async_bulk_tensor.rst
+++ b/docs/libcudacxx/ptx/instructions/cp_async_bulk_tensor.rst
@@ -21,3 +21,8 @@ Multicast
 ---------
 
 .. include:: generated/cp_async_bulk_tensor_multicast.rst
+
+Scatter / Gather
+----------------
+
+.. include:: generated/cp_async_bulk_tensor_gather_scatter.rst
diff --git a/docs/libcudacxx/ptx/instructions/fence.rst b/docs/libcudacxx/ptx/instructions/fence.rst
index 82de170f63b..4d9126be62f 100644
--- a/docs/libcudacxx/ptx/instructions/fence.rst
+++ b/docs/libcudacxx/ptx/instructions/fence.rst
@@ -13,6 +13,11 @@ fence
 
 .. include:: generated/fence.rst
 
+fence.sync_restrict
+-------------------
+
+.. include:: generated/fence_sync_restrict.rst
+
 fence.mbarrier_init
 -------------------
 
@@ -29,6 +34,11 @@ fence.proxy.async
 
 .. include:: generated/fence_proxy_async.rst
 
+fence.proxy.async.sync_restrict
+-------------------------------
+
+.. include:: generated/fence_proxy_async_generic_sync_restrict.rst
+
 fence.proxy.tensormap
 ---------------------
 
diff --git a/libcudacxx/include/cuda/__ptx/instructions/cp_async_bulk_tensor.h b/libcudacxx/include/cuda/__ptx/instructions/cp_async_bulk_tensor.h
index 7de5b41b744..f99c0c6f73b 100644
--- a/libcudacxx/include/cuda/__ptx/instructions/cp_async_bulk_tensor.h
+++ b/libcudacxx/include/cuda/__ptx/instructions/cp_async_bulk_tensor.h
@@ -33,6 +33,7 @@ _LIBCUDACXX_BEGIN_NAMESPACE_CUDA_PTX
 // 9.7.8.24.9. Data Movement and Conversion Instructions: cp.async.bulk.tensor
 // https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#data-movement-and-conversion-instructions-cp-async-bulk-tensor
 #include <cuda/__ptx/instructions/generated/cp_async_bulk_tensor.h>
+#include <cuda/__ptx/instructions/generated/cp_async_bulk_tensor_gather_scatter.h>
 #include <cuda/__ptx/instructions/generated/cp_async_bulk_tensor_multicast.h>
 
 _LIBCUDACXX_END_NAMESPACE_CUDA_PTX
diff --git a/libcudacxx/include/cuda/__ptx/instructions/fence.h b/libcudacxx/include/cuda/__ptx/instructions/fence.h
index a8dccf979c2..3c123840797 100644
--- a/libcudacxx/include/cuda/__ptx/instructions/fence.h
+++ b/libcudacxx/include/cuda/__ptx/instructions/fence.h
@@ -36,7 +36,9 @@ _LIBCUDACXX_BEGIN_NAMESPACE_CUDA_PTX
 #include <cuda/__ptx/instructions/generated/fence_mbarrier_init.h>
 #include <cuda/__ptx/instructions/generated/fence_proxy_alias.h>
 #include <cuda/__ptx/instructions/generated/fence_proxy_async.h>
+#include <cuda/__ptx/instructions/generated/fence_proxy_async_generic_sync_restrict.h>
 #include <cuda/__ptx/instructions/generated/fence_proxy_tensormap_generic.h>
+#include <cuda/__ptx/instructions/generated/fence_sync_restrict.h>
 
 _LIBCUDACXX_END_NAMESPACE_CUDA_PTX
 
diff --git a/libcudacxx/include/cuda/__ptx/instructions/mbarrier_expect_tx.h b/libcudacxx/include/cuda/__ptx/instructions/mbarrier_expect_tx.h
new file mode 100644
index 00000000000..886bfe64d75
--- /dev/null
+++ b/libcudacxx/include/cuda/__ptx/instructions/mbarrier_expect_tx.h
@@ -0,0 +1,37 @@
+// -*- C++ -*-
+//===----------------------------------------------------------------------===//
+//
+// Part of libcu++, the C++ Standard Library for your entire system,
+// under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+// SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef _CUDA_PTX_MBARRIER_EXPECT_TX_H_
+#define _CUDA_PTX_MBARRIER_EXPECT_TX_H_
+
+#include <cuda/std/detail/__config>
+
+#if defined(_CCCL_IMPLICIT_SYSTEM_HEADER_GCC)
+#  pragma GCC system_header
+#elif defined(_CCCL_IMPLICIT_SYSTEM_HEADER_CLANG)
+#  pragma clang system_header
+#elif defined(_CCCL_IMPLICIT_SYSTEM_HEADER_MSVC)
+#  pragma system_header
+#endif // no system header
+
+#include <cuda/__ptx/ptx_dot_variants.h>
+#include <cuda/__ptx/ptx_helper_functions.h>
+#include <cuda/std/cstdint>
+
+#include <nv/target> // __CUDA_MINIMUM_ARCH__ and friends
+
+_LIBCUDACXX_BEGIN_NAMESPACE_CUDA_PTX
+
+#include <cuda/__ptx/instructions/generated/mbarrier_expect_tx.h>
+
+_LIBCUDACXX_END_NAMESPACE_CUDA_PTX
+
+#endif // _CUDA_PTX_MBARRIER_EXPECT_TX_H_
diff --git a/libcudacxx/include/cuda/ptx b/libcudacxx/include/cuda/ptx
index 44edb20c98e..4798973df77 100644
--- a/libcudacxx/include/cuda/ptx
+++ b/libcudacxx/include/cuda/ptx
@@ -80,6 +80,7 @@
 #include <cuda/__ptx/instructions/get_sreg.h>
 #include <cuda/__ptx/instructions/getctarank.h>
 #include <cuda/__ptx/instructions/mbarrier_arrive.h>
+#include <cuda/__ptx/instructions/mbarrier_expect_tx.h>
 #include <cuda/__ptx/instructions/mbarrier_init.h>
 #include <cuda/__ptx/instructions/mbarrier_wait.h>
 #include <cuda/__ptx/instructions/red_async.h>
diff --git a/libcudacxx/test/libcudacxx/cuda/ptx/ptx.cp.async.bulk.tensor.compile.pass.cpp b/libcudacxx/test/libcudacxx/cuda/ptx/ptx.cp.async.bulk.tensor.compile.pass.cpp
index 42bc5b8e355..efd66a8fa4e 100644
--- a/libcudacxx/test/libcudacxx/cuda/ptx/ptx.cp.async.bulk.tensor.compile.pass.cpp
+++ b/libcudacxx/test/libcudacxx/cuda/ptx/ptx.cp.async.bulk.tensor.compile.pass.cpp
@@ -17,6 +17,7 @@
 #include "nvrtc_workaround.h"
 // above header needs to be included before the generated test header
 #include "generated/cp_async_bulk_tensor.h"
+#include "generated/cp_async_bulk_tensor_gather_scatter.h"
 
 int main(int, char**)
 {
diff --git a/libcudacxx/test/libcudacxx/cuda/ptx/ptx.fence.compile.pass.cpp b/libcudacxx/test/libcudacxx/cuda/ptx/ptx.fence.compile.pass.cpp
index c439720b8f8..aa2c9ec6152 100644
--- a/libcudacxx/test/libcudacxx/cuda/ptx/ptx.fence.compile.pass.cpp
+++ b/libcudacxx/test/libcudacxx/cuda/ptx/ptx.fence.compile.pass.cpp
@@ -20,7 +20,9 @@
 #include "generated/fence_mbarrier_init.h"
 #include "generated/fence_proxy_alias.h"
 #include "generated/fence_proxy_async.h"
+#include "generated/fence_proxy_async_generic_sync_restrict.h"
 #include "generated/fence_proxy_tensormap_generic.h"
+#include "generated/fence_sync_restrict.h"
 
 int main(int, char**)
 {
diff --git a/libcudacxx/test/libcudacxx/cuda/ptx/ptx.mbarrier.expect_tx.compile.pass.cpp b/libcudacxx/test/libcudacxx/cuda/ptx/ptx.mbarrier.expect_tx.compile.pass.cpp
new file mode 100644
index 00000000000..f4d06bdb8ba
--- /dev/null
+++ b/libcudacxx/test/libcudacxx/cuda/ptx/ptx.mbarrier.expect_tx.compile.pass.cpp
@@ -0,0 +1,22 @@
+//===----------------------------------------------------------------------===//
+//
+// Part of libcu++, the C++ Standard Library for your entire system,
+// under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+// SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES.
+//
+//===----------------------------------------------------------------------===//
+// UNSUPPORTED: libcpp-has-no-threads
+
+// <cuda/ptx>
+
+#include <cuda/ptx>
+#include <cuda/std/utility>
+
+#include "generated/mbarrier_expect_tx.h"
+
+int main(int, char**)
+{
+  return 0;
+}

From a1a73a8708eac531498762c22999d0a5aea076d0 Mon Sep 17 00:00:00 2001
From: Bernhard Manfred Gruber <bernhardmgruber@gmail.com>
Date: Thu, 30 Jan 2025 11:26:03 +0100
Subject: [PATCH 19/33] Internalize cuda/detail/core/util.h (#3505)

---
 cub/cub/agent/agent_adjacent_difference.cuh   |  4 +-
 cub/cub/agent/agent_merge.cuh                 |  8 +-
 cub/cub/agent/agent_merge_sort.cuh            | 15 ++--
 cub/cub/agent/agent_sub_warp_merge_sort.cuh   |  4 +-
 cub/cub/device/dispatch/dispatch_merge.cuh    |  2 +-
 .../device/dispatch/kernels/merge_sort.cuh    | 19 ++---
 .../system/cuda/detail/core/agent_launcher.h  | 46 +++---------
 .../system/cuda/detail/core/load_iterator.h   |  4 +-
 .../cuda/detail/core/make_load_iterator.h     |  4 +-
 thrust/thrust/system/cuda/detail/core/util.h  | 51 +------------
 thrust/thrust/system/cuda/detail/extrema.h    | 18 ++---
 thrust/thrust/system/cuda/detail/reduce.h     | 40 +++++-----
 .../thrust/system/cuda/detail/reduce_by_key.h | 48 ++++++------
 .../system/cuda/detail/set_operations.h       | 73 +++++++++----------
 thrust/thrust/system/cuda/detail/sort.h       |  6 +-
 thrust/thrust/system/cuda/detail/unique.h     | 43 +++++------
 16 files changed, 156 insertions(+), 229 deletions(-)

diff --git a/cub/cub/agent/agent_adjacent_difference.cuh b/cub/cub/agent/agent_adjacent_difference.cuh
index c19cb90079a..8617c78193b 100644
--- a/cub/cub/agent/agent_adjacent_difference.cuh
+++ b/cub/cub/agent/agent_adjacent_difference.cuh
@@ -79,7 +79,7 @@ template <typename Policy,
           bool ReadLeft>
 struct AgentDifference
 {
-  using LoadIt = typename THRUST_NS_QUALIFIER::cuda_cub::core::LoadIterator<Policy, InputIteratorT>::type;
+  using LoadIt = typename THRUST_NS_QUALIFIER::cuda_cub::core::detail::LoadIterator<Policy, InputIteratorT>::type;
 
   using BlockLoad  = typename cub::BlockLoadType<Policy, LoadIt>::type;
   using BlockStore = typename cub::BlockStoreType<Policy, OutputIteratorT, OutputT>::type;
@@ -119,7 +119,7 @@ struct AgentDifference
     OffsetT num_items)
       : temp_storage(temp_storage.Alias())
       , input_it(input_it)
-      , load_it(THRUST_NS_QUALIFIER::cuda_cub::core::make_load_iterator(Policy(), input_it))
+      , load_it(THRUST_NS_QUALIFIER::cuda_cub::core::detail::make_load_iterator(Policy(), input_it))
       , first_tile_previous(first_tile_previous)
       , result(result)
       , difference_op(difference_op)
diff --git a/cub/cub/agent/agent_merge.cuh b/cub/cub/agent/agent_merge.cuh
index 9ae14c3e42e..5c7d5322456 100644
--- a/cub/cub/agent/agent_merge.cuh
+++ b/cub/cub/agent/agent_merge.cuh
@@ -64,10 +64,10 @@ struct agent_t
   using key_type  = typename ::cuda::std::iterator_traits<KeysIt1>::value_type;
   using item_type = typename ::cuda::std::iterator_traits<ItemsIt1>::value_type;
 
-  using keys_load_it1  = typename THRUST_NS_QUALIFIER::cuda_cub::core::LoadIterator<Policy, KeysIt1>::type;
-  using keys_load_it2  = typename THRUST_NS_QUALIFIER::cuda_cub::core::LoadIterator<Policy, KeysIt2>::type;
-  using items_load_it1 = typename THRUST_NS_QUALIFIER::cuda_cub::core::LoadIterator<Policy, ItemsIt1>::type;
-  using items_load_it2 = typename THRUST_NS_QUALIFIER::cuda_cub::core::LoadIterator<Policy, ItemsIt2>::type;
+  using keys_load_it1  = typename THRUST_NS_QUALIFIER::cuda_cub::core::detail::LoadIterator<Policy, KeysIt1>::type;
+  using keys_load_it2  = typename THRUST_NS_QUALIFIER::cuda_cub::core::detail::LoadIterator<Policy, KeysIt2>::type;
+  using items_load_it1 = typename THRUST_NS_QUALIFIER::cuda_cub::core::detail::LoadIterator<Policy, ItemsIt1>::type;
+  using items_load_it2 = typename THRUST_NS_QUALIFIER::cuda_cub::core::detail::LoadIterator<Policy, ItemsIt2>::type;
 
   using block_load_keys1  = typename BlockLoadType<Policy, keys_load_it1>::type;
   using block_load_keys2  = typename BlockLoadType<Policy, keys_load_it2>::type;
diff --git a/cub/cub/agent/agent_merge_sort.cuh b/cub/cub/agent/agent_merge_sort.cuh
index bf4984f7256..1ec952187a7 100644
--- a/cub/cub/agent/agent_merge_sort.cuh
+++ b/cub/cub/agent/agent_merge_sort.cuh
@@ -91,8 +91,10 @@ struct AgentBlockSort
 
   using BlockMergeSortT = BlockMergeSort<KeyT, Policy::BLOCK_THREADS, Policy::ITEMS_PER_THREAD, ValueT>;
 
-  using KeysLoadIt  = typename THRUST_NS_QUALIFIER::cuda_cub::core::LoadIterator<Policy, KeyInputIteratorT>::type;
-  using ItemsLoadIt = typename THRUST_NS_QUALIFIER::cuda_cub::core::LoadIterator<Policy, ValueInputIteratorT>::type;
+  using KeysLoadIt =
+    typename THRUST_NS_QUALIFIER::cuda_cub::core::detail::LoadIterator<Policy, KeyInputIteratorT>::type;
+  using ItemsLoadIt =
+    typename THRUST_NS_QUALIFIER::cuda_cub::core::detail::LoadIterator<Policy, ValueInputIteratorT>::type;
 
   using BlockLoadKeys  = typename cub::BlockLoadType<Policy, KeysLoadIt>::type;
   using BlockLoadItems = typename cub::BlockLoadType<Policy, ItemsLoadIt>::type;
@@ -438,10 +440,11 @@ struct AgentMerge
   //---------------------------------------------------------------------
   // Types and constants
   //---------------------------------------------------------------------
-  using KeysLoadPingIt  = typename THRUST_NS_QUALIFIER::cuda_cub::core::LoadIterator<Policy, KeyIteratorT>::type;
-  using ItemsLoadPingIt = typename THRUST_NS_QUALIFIER::cuda_cub::core::LoadIterator<Policy, ValueIteratorT>::type;
-  using KeysLoadPongIt  = typename THRUST_NS_QUALIFIER::cuda_cub::core::LoadIterator<Policy, KeyT*>::type;
-  using ItemsLoadPongIt = typename THRUST_NS_QUALIFIER::cuda_cub::core::LoadIterator<Policy, ValueT*>::type;
+  using KeysLoadPingIt = typename THRUST_NS_QUALIFIER::cuda_cub::core::detail::LoadIterator<Policy, KeyIteratorT>::type;
+  using ItemsLoadPingIt =
+    typename THRUST_NS_QUALIFIER::cuda_cub::core::detail::LoadIterator<Policy, ValueIteratorT>::type;
+  using KeysLoadPongIt  = typename THRUST_NS_QUALIFIER::cuda_cub::core::detail::LoadIterator<Policy, KeyT*>::type;
+  using ItemsLoadPongIt = typename THRUST_NS_QUALIFIER::cuda_cub::core::detail::LoadIterator<Policy, ValueT*>::type;
 
   using KeysOutputPongIt  = KeyIteratorT;
   using ItemsOutputPongIt = ValueIteratorT;
diff --git a/cub/cub/agent/agent_sub_warp_merge_sort.cuh b/cub/cub/agent/agent_sub_warp_merge_sort.cuh
index b10f1cda3ea..9f98ac42e3b 100644
--- a/cub/cub/agent/agent_sub_warp_merge_sort.cuh
+++ b/cub/cub/agent/agent_sub_warp_merge_sort.cuh
@@ -183,8 +183,8 @@ public:
 
   using WarpMergeSortT = WarpMergeSort<KeyT, PolicyT::ITEMS_PER_THREAD, PolicyT::WARP_THREADS, ValueT>;
 
-  using KeysLoadItT  = typename THRUST_NS_QUALIFIER::cuda_cub::core::LoadIterator<PolicyT, const KeyT*>::type;
-  using ItemsLoadItT = typename THRUST_NS_QUALIFIER::cuda_cub::core::LoadIterator<PolicyT, const ValueT*>::type;
+  using KeysLoadItT  = typename THRUST_NS_QUALIFIER::cuda_cub::core::detail::LoadIterator<PolicyT, const KeyT*>::type;
+  using ItemsLoadItT = typename THRUST_NS_QUALIFIER::cuda_cub::core::detail::LoadIterator<PolicyT, const ValueT*>::type;
 
   using WarpLoadKeysT = cub::WarpLoad<KeyT, PolicyT::ITEMS_PER_THREAD, PolicyT::LOAD_ALGORITHM, PolicyT::WARP_THREADS>;
   using WarpLoadItemsT =
diff --git a/cub/cub/device/dispatch/dispatch_merge.cuh b/cub/cub/device/dispatch/dispatch_merge.cuh
index b3d0c8ab2ca..c4df61fd29a 100644
--- a/cub/cub/device/dispatch/dispatch_merge.cuh
+++ b/cub/cub/device/dispatch/dispatch_merge.cuh
@@ -138,7 +138,7 @@ __launch_bounds__(
     CompareOp>::type;
   using MergePolicy = typename MergeAgent::policy;
 
-  using THRUST_NS_QUALIFIER::cuda_cub::core::make_load_iterator;
+  using THRUST_NS_QUALIFIER::cuda_cub::core::detail::make_load_iterator;
   using vsmem_helper_t = vsmem_helper_impl<MergeAgent>;
   __shared__ typename vsmem_helper_t::static_temp_storage_t shared_temp_storage;
   auto& temp_storage = vsmem_helper_t::get_temp_storage(shared_temp_storage, global_temp_storage);
diff --git a/cub/cub/device/dispatch/kernels/merge_sort.cuh b/cub/cub/device/dispatch/kernels/merge_sort.cuh
index c9a8a61395a..79f7c6bbe40 100644
--- a/cub/cub/device/dispatch/kernels/merge_sort.cuh
+++ b/cub/cub/device/dispatch/kernels/merge_sort.cuh
@@ -19,12 +19,13 @@
 
 THRUST_NAMESPACE_BEGIN
 
-namespace cuda_cub::core
+namespace cuda_cub::core::detail
 {
 // We must forward declare here because make_load_iterator.h pulls in non NVRTC compilable code
 template <class PtxPlan, class It>
-typename LoadIterator<PtxPlan, It>::type _CCCL_DEVICE _CCCL_FORCEINLINE make_load_iterator(PtxPlan const&, It it);
-} // namespace cuda_cub::core
+typename detail::LoadIterator<PtxPlan, It>::type _CCCL_DEVICE _CCCL_FORCEINLINE
+make_load_iterator(PtxPlan const&, It it);
+} // namespace cuda_cub::core::detail
 
 THRUST_NAMESPACE_END
 
@@ -196,8 +197,8 @@ __launch_bounds__(
   AgentBlockSortT agent(
     ping,
     temp_storage,
-    THRUST_NS_QUALIFIER::cuda_cub::core::make_load_iterator(ActivePolicyT(), keys_in),
-    THRUST_NS_QUALIFIER::cuda_cub::core::make_load_iterator(ActivePolicyT(), items_in),
+    THRUST_NS_QUALIFIER::cuda_cub::core::detail::make_load_iterator(ActivePolicyT(), keys_in),
+    THRUST_NS_QUALIFIER::cuda_cub::core::detail::make_load_iterator(ActivePolicyT(), items_in),
     keys_count,
     keys_out,
     items_out,
@@ -302,10 +303,10 @@ __launch_bounds__(
   AgentMergeT agent(
     ping,
     temp_storage,
-    THRUST_NS_QUALIFIER::cuda_cub::core::make_load_iterator(ActivePolicyT(), keys_ping),
-    THRUST_NS_QUALIFIER::cuda_cub::core::make_load_iterator(ActivePolicyT(), items_ping),
-    THRUST_NS_QUALIFIER::cuda_cub::core::make_load_iterator(ActivePolicyT(), keys_pong),
-    THRUST_NS_QUALIFIER::cuda_cub::core::make_load_iterator(ActivePolicyT(), items_pong),
+    THRUST_NS_QUALIFIER::cuda_cub::core::detail::make_load_iterator(ActivePolicyT(), keys_ping),
+    THRUST_NS_QUALIFIER::cuda_cub::core::detail::make_load_iterator(ActivePolicyT(), items_ping),
+    THRUST_NS_QUALIFIER::cuda_cub::core::detail::make_load_iterator(ActivePolicyT(), keys_pong),
+    THRUST_NS_QUALIFIER::cuda_cub::core::detail::make_load_iterator(ActivePolicyT(), items_pong),
     keys_count,
     keys_pong,
     items_pong,
diff --git a/thrust/thrust/system/cuda/detail/core/agent_launcher.h b/thrust/thrust/system/cuda/detail/core/agent_launcher.h
index fb7c1ef22d6..d9baeb47593 100644
--- a/thrust/thrust/system/cuda/detail/core/agent_launcher.h
+++ b/thrust/thrust/system/cuda/detail/core/agent_launcher.h
@@ -62,7 +62,8 @@ namespace cuda_cub
 {
 namespace core
 {
-
+namespace detail
+{
 #  ifndef THRUST_DETAIL_KERNEL_ATTRIBUTES
 #    define THRUST_DETAIL_KERNEL_ATTRIBUTES CCCL_DETAIL_KERNEL_ATTRIBUTES
 #  endif
@@ -97,7 +98,7 @@ THRUST_DETAIL_KERNEL_ATTRIBUTES void _kernel_agent_vshmem(char*, Args... args)
 template <class Agent>
 struct AgentLauncher : Agent
 {
-  core::AgentPlan plan;
+  AgentPlan plan;
   size_t count;
   cudaStream_t stream;
   char const* name;
@@ -121,7 +122,7 @@ struct AgentLauncher : Agent
       , name(name_)
       , grid(static_cast<unsigned int>((count + plan.items_per_tile - 1) / plan.items_per_tile))
       , vshmem(nullptr)
-      , has_shmem((size_t) core::get_max_shared_memory_per_block() >= (size_t) plan.shared_memory_size)
+      , has_shmem((size_t) get_max_shared_memory_per_block() >= (size_t) plan.shared_memory_size)
       , shmem_size(has_shmem ? plan.shared_memory_size : 0)
   {
     assert(count > 0);
@@ -136,7 +137,7 @@ struct AgentLauncher : Agent
       , name(name_)
       , grid(static_cast<unsigned int>((count + plan.items_per_tile - 1) / plan.items_per_tile))
       , vshmem(vshmem)
-      , has_shmem((size_t) core::get_max_shared_memory_per_block() >= (size_t) plan.shared_memory_size)
+      , has_shmem((size_t) get_max_shared_memory_per_block() >= (size_t) plan.shared_memory_size)
       , shmem_size(has_shmem ? plan.shared_memory_size : 0)
   {
     assert(count > 0);
@@ -149,7 +150,7 @@ struct AgentLauncher : Agent
       , name(name_)
       , grid(plan.grid_size)
       , vshmem(nullptr)
-      , has_shmem((size_t) core::get_max_shared_memory_per_block() >= (size_t) plan.shared_memory_size)
+      , has_shmem((size_t) get_max_shared_memory_per_block() >= (size_t) plan.shared_memory_size)
       , shmem_size(has_shmem ? plan.shared_memory_size : 0)
   {
     assert(plan.grid_size > 0);
@@ -162,43 +163,19 @@ struct AgentLauncher : Agent
       , name(name_)
       , grid(plan.grid_size)
       , vshmem(vshmem)
-      , has_shmem((size_t) core::get_max_shared_memory_per_block() >= (size_t) plan.shared_memory_size)
+      , has_shmem((size_t) get_max_shared_memory_per_block() >= (size_t) plan.shared_memory_size)
       , shmem_size(has_shmem ? plan.shared_memory_size : 0)
   {
     assert(plan.grid_size > 0);
   }
 
-#  if 0
-    THRUST_RUNTIME_FUNCTION
-    AgentPlan static get_plan(cudaStream_t s, void* d_ptr = 0)
-    {
-      // in separable compilation mode, we have no choice
-      // but to call kernel to get agent_plan
-      // otherwise the risk is something may fail
-      // if user mix & match ptx versions in a separably compiled function
-      // http://nvbugs/1772071
-      // XXX may be it is too string of a requirements, consider relaxing it in
-      // the future
-#    ifdef __CUDACC_RDC__
-      return core::get_agent_plan<Agent>(s, d_ptr);
-#    else
-      return get_agent_plan<Agent>(core::get_ptx_version());
-#    endif
-    }
-    THRUST_RUNTIME_FUNCTION
-    AgentPlan static get_plan_default()
-    {
-      return get_agent_plan<Agent>(sm_arch<0>::type::ver);
-    }
-#  endif
-
-  THRUST_RUNTIME_FUNCTION typename core::get_plan<Agent>::type static get_plan(cudaStream_t, void* d_ptr = 0)
+  THRUST_RUNTIME_FUNCTION typename get_plan<Agent>::type static get_plan(cudaStream_t, void* d_ptr = 0)
   {
     THRUST_UNUSED_VAR(d_ptr);
-    return get_agent_plan<Agent>(core::get_ptx_version());
+    return get_agent_plan<Agent>(get_ptx_version());
   }
 
-  THRUST_RUNTIME_FUNCTION typename core::get_plan<Agent>::type static get_plan()
+  THRUST_RUNTIME_FUNCTION typename detail::get_plan<Agent>::type static get_plan()
   {
     return get_agent_plan<Agent>(lowest_supported_sm_arch::ver);
   }
@@ -227,7 +204,7 @@ struct AgentLauncher : Agent
   {
 #  if THRUST_DEBUG_SYNC_FLAG
     cuda_optional<int> occ = max_sm_occupancy(k);
-    const int ptx_version  = core::get_ptx_version();
+    const int ptx_version  = get_ptx_version();
     if (count > 0)
     {
       _CubLog(
@@ -305,6 +282,7 @@ struct AgentLauncher : Agent
   }
 };
 
+} // namespace detail
 } // namespace core
 } // namespace cuda_cub
 
diff --git a/thrust/thrust/system/cuda/detail/core/load_iterator.h b/thrust/thrust/system/cuda/detail/core/load_iterator.h
index 07c5eba0eaa..6f2c118b151 100644
--- a/thrust/thrust/system/cuda/detail/core/load_iterator.h
+++ b/thrust/thrust/system/cuda/detail/core/load_iterator.h
@@ -34,7 +34,7 @@
 
 THRUST_NAMESPACE_BEGIN
 
-namespace cuda_cub::core
+namespace cuda_cub::core::detail
 {
 
 // LoadIterator
@@ -52,6 +52,6 @@ struct LoadIterator
                                cub::CacheModifiedInputIterator<PtxPlan::LOAD_MODIFIER, value_type, size_type>,
                                It>;
 }; // struct Iterator
-} // namespace cuda_cub::core
+} // namespace cuda_cub::core::detail
 
 THRUST_NAMESPACE_END
diff --git a/thrust/thrust/system/cuda/detail/core/make_load_iterator.h b/thrust/thrust/system/cuda/detail/core/make_load_iterator.h
index 28c65c813ea..9497ccacca9 100644
--- a/thrust/thrust/system/cuda/detail/core/make_load_iterator.h
+++ b/thrust/thrust/system/cuda/detail/core/make_load_iterator.h
@@ -33,7 +33,7 @@
 
 THRUST_NAMESPACE_BEGIN
 
-namespace cuda_cub::core
+namespace cuda_cub::core::detail
 {
 template <class PtxPlan, class It>
 typename LoadIterator<PtxPlan, It>::type _CCCL_DEVICE _CCCL_FORCEINLINE
@@ -55,6 +55,6 @@ typename LoadIterator<PtxPlan, It>::type _CCCL_DEVICE _CCCL_FORCEINLINE make_loa
   return make_load_iterator_impl<PtxPlan>(it, typename is_contiguous_iterator<It>::type());
 }
 
-} // namespace cuda_cub::core
+} // namespace cuda_cub::core::detail
 
 THRUST_NAMESPACE_END
diff --git a/thrust/thrust/system/cuda/detail/core/util.h b/thrust/thrust/system/cuda/detail/core/util.h
index 94a7e750aeb..b3bdcf1f086 100644
--- a/thrust/thrust/system/cuda/detail/core/util.h
+++ b/thrust/thrust/system/cuda/detail/core/util.h
@@ -78,6 +78,8 @@ namespace core
 #  endif
 #endif
 
+namespace detail
+{
 /// Typelist - a container of types
 template <typename...>
 struct typelist;
@@ -458,22 +460,9 @@ THRUST_RUNTIME_FUNCTION inline size_t get_max_shared_memory_per_block()
   return static_cast<size_t>(i32value);
 }
 
-THRUST_RUNTIME_FUNCTION inline size_t virtual_shmem_size(size_t shmem_per_block)
-{
-  size_t max_shmem_per_block = core::get_max_shared_memory_per_block();
-  if (shmem_per_block > max_shmem_per_block)
-  {
-    return shmem_per_block;
-  }
-  else
-  {
-    return 0;
-  }
-}
-
 THRUST_RUNTIME_FUNCTION inline size_t vshmem_size(size_t shmem_per_block, size_t num_blocks)
 {
-  size_t max_shmem_per_block = core::get_max_shared_memory_per_block();
+  size_t max_shmem_per_block = get_max_shared_memory_per_block();
   if (shmem_per_block > max_shmem_per_block)
   {
     return shmem_per_block * num_blocks;
@@ -509,22 +498,6 @@ struct BlockLoad
                    get_arch<PtxPlan>::type::ver>;
 };
 
-// BlockStore
-// -----------
-// a helper metaprogram that returns type of a block loader
-template <class PtxPlan, class It, class T = typename iterator_traits<It>::value_type>
-struct BlockStore
-{
-  using type =
-    cub::BlockStore<T,
-                    PtxPlan::BLOCK_THREADS,
-                    PtxPlan::ITEMS_PER_THREAD,
-                    PtxPlan::STORE_ALGORITHM,
-                    1,
-                    1,
-                    get_arch<PtxPlan>::type::ver>;
-};
-
 // cuda_optional
 // --------------
 // used for function that return cudaError_t along with the result
@@ -619,16 +592,6 @@ THRUST_RUNTIME_FUNCTION inline int get_ptx_version()
   return ptx_version;
 }
 
-THRUST_RUNTIME_FUNCTION inline cudaError_t sync_stream(cudaStream_t stream)
-{
-  return cub::SyncStream(stream);
-}
-
-inline void _CCCL_DEVICE sync_threadblock()
-{
-  __syncthreads();
-}
-
 // Deprecated [Since 2.8]
 #define CUDA_CUB_RET_IF_FAIL(e)                \
   {                                            \
@@ -719,11 +682,6 @@ struct uninitialized_array
   }
 };
 
-_CCCL_HOST_DEVICE _CCCL_FORCEINLINE size_t align_to(size_t n, size_t align)
-{
-  return ((n + align - 1) / align) * align;
-}
-
 namespace host
 {
 inline cuda_optional<size_t> get_max_shared_memory_per_block()
@@ -753,9 +711,8 @@ THRUST_RUNTIME_FUNCTION cudaError_t alias_storage(
   return cub::AliasTemporaries(storage_ptr, storage_size, allocations, allocation_sizes);
 }
 
+} // namespace detail
 } // namespace core
-using core::sm52;
-using core::sm60;
 } // namespace cuda_cub
 
 THRUST_NAMESPACE_END
diff --git a/thrust/thrust/system/cuda/detail/extrema.h b/thrust/thrust/system/cuda/detail/extrema.h
index 617eb8bbc79..b2124323424 100644
--- a/thrust/thrust/system/cuda/detail/extrema.h
+++ b/thrust/thrust/system/cuda/detail/extrema.h
@@ -184,10 +184,10 @@ cudaError_t THRUST_RUNTIME_FUNCTION doit_step(
   OutputIt output_it,
   cudaStream_t stream)
 {
-  using core::AgentLauncher;
-  using core::AgentPlan;
-  using core::cuda_optional;
-  using core::get_agent_plan;
+  using core::detail::AgentLauncher;
+  using core::detail::AgentPlan;
+  using core::detail::cuda_optional;
+  using core::detail::get_agent_plan;
 
   using UnsignedSize = typename detail::make_unsigned_special<Size>::type;
 
@@ -204,7 +204,7 @@ cudaError_t THRUST_RUNTIME_FUNCTION doit_step(
 
   if (num_items <= reduce_plan.items_per_tile)
   {
-    size_t vshmem_size = core::vshmem_size(reduce_plan.shared_memory_size, 1);
+    size_t vshmem_size = core::detail::vshmem_size(reduce_plan.shared_memory_size, 1);
 
     // small, single tile size
     if (d_temp_storage == nullptr)
@@ -221,7 +221,7 @@ cudaError_t THRUST_RUNTIME_FUNCTION doit_step(
   else
   {
     // regular size
-    cuda_optional<int> sm_count = core::get_sm_count();
+    cuda_optional<int> sm_count = core::detail::get_sm_count();
     CUDA_CUB_RET_IF_FAIL(sm_count.status());
 
     // reduction will not use more cta counts than requested
@@ -245,7 +245,7 @@ cudaError_t THRUST_RUNTIME_FUNCTION doit_step(
     // we will launch at most "max_blocks" blocks in a grid
     // so preallocate virtual shared memory storage for this if required
     //
-    size_t vshmem_size = core::vshmem_size(reduce_plan.shared_memory_size, max_blocks);
+    size_t vshmem_size = core::detail::vshmem_size(reduce_plan.shared_memory_size, max_blocks);
 
     // Temporary storage allocation requirements
     void* allocations[3]       = {nullptr, nullptr, nullptr};
@@ -331,14 +331,14 @@ extrema(execution_policy<Derived>& policy, InputIt first, Size num_items, Binary
   void* allocations[2]       = {nullptr, nullptr};
 
   size_t storage_size = 0;
-  status              = core::alias_storage(nullptr, storage_size, allocations, allocation_sizes);
+  status              = core::detail::alias_storage(nullptr, storage_size, allocations, allocation_sizes);
   cuda_cub::throw_on_error(status, "extrema failed on 1st alias storage");
 
   // Allocate temporary storage.
   thrust::detail::temporary_array<std::uint8_t, Derived> tmp(policy, storage_size);
   void* ptr = static_cast<void*>(tmp.data().get());
 
-  status = core::alias_storage(ptr, storage_size, allocations, allocation_sizes);
+  status = core::detail::alias_storage(ptr, storage_size, allocations, allocation_sizes);
   cuda_cub::throw_on_error(status, "extrema failed on 2nd alias storage");
 
   T* d_result = thrust::detail::aligned_reinterpret_cast<T*>(allocations[0]);
diff --git a/thrust/thrust/system/cuda/detail/reduce.h b/thrust/thrust/system/cuda/detail/reduce.h
index 3787ab62367..61ec2086adf 100644
--- a/thrust/thrust/system/cuda/detail/reduce.h
+++ b/thrust/thrust/system/cuda/detail/reduce.h
@@ -109,7 +109,7 @@ template <class, class>
 struct Tuning;
 
 template <class T>
-struct Tuning<sm52, T>
+struct Tuning<core::detail::sm52, T>
 {
   enum
   {
@@ -155,7 +155,7 @@ struct ReduceAgent
     using tuning = Tuning<Arch, T>;
 
     using Vector      = typename cub::CubVector<T, PtxPlan::VECTOR_LOAD_LENGTH>;
-    using LoadIt      = typename core::LoadIterator<PtxPlan, InputIt>::type;
+    using LoadIt      = typename core::detail::LoadIterator<PtxPlan, InputIt>::type;
     using BlockReduce = cub::BlockReduce<T, PtxPlan::BLOCK_THREADS, PtxPlan::BLOCK_ALGORITHM, 1, 1, Arch::ver>;
 
     using VectorLoadIt = cub::CacheModifiedInputIterator<PtxPlan::LOAD_MODIFIER, Vector, Size>;
@@ -175,7 +175,7 @@ struct ReduceAgent
   // Other algorithms, e.g. merge, may not need additional information,
   // and may use AgentPlan directly, instead of defining their own Plan type.
   //
-  struct Plan : core::AgentPlan
+  struct Plan : core::detail::AgentPlan
   {
     cub::GridMappingStrategy grid_mapping;
 
@@ -183,7 +183,7 @@ struct ReduceAgent
 
     template <class P>
     THRUST_RUNTIME_FUNCTION Plan(P)
-        : core::AgentPlan(P())
+        : core::detail::AgentPlan(P())
         , grid_mapping(P::GRID_MAPPING)
     {}
   };
@@ -192,7 +192,7 @@ struct ReduceAgent
   // ptx_plan type *must* only be used from device code
   // Its use from host code will result in *undefined behaviour*
   //
-  using ptx_plan = typename core::specialize_plan_msvc10_war<PtxPlan>::type::type;
+  using ptx_plan = typename core::detail::specialize_plan_msvc10_war<PtxPlan>::type::type;
 
   using TempStorage  = typename ptx_plan::TempStorage;
   using Vector       = typename ptx_plan::Vector;
@@ -230,7 +230,7 @@ struct ReduceAgent
     THRUST_DEVICE_FUNCTION impl(TempStorage& storage_, InputIt input_it_, ReductionOp reduction_op_)
         : storage(storage_)
         , input_it(input_it_)
-        , load_it(core::make_load_iterator(ptx_plan(), input_it))
+        , load_it(core::detail::make_load_iterator(ptx_plan(), input_it))
         , reduction_op(reduction_op_)
     {}
 
@@ -428,8 +428,6 @@ struct ReduceAgent
     THRUST_DEVICE_FUNCTION T
     consume_tiles_impl(Size num_items, cub::GridQueue<UnsignedSize> queue, CAN_VECTORIZE can_vectorize)
     {
-      using core::sync_threadblock;
-
       // We give each thread block at least one tile of input.
       T thread_aggregate;
       Size block_offset    = blockIdx.x * ITEMS_PER_TILE;
@@ -454,7 +452,7 @@ struct ReduceAgent
           storage.dequeue_offset = queue.Drain(ITEMS_PER_TILE) + even_share_base;
         }
 
-        sync_threadblock();
+        __syncthreads();
 
         // Grab tile offset and check if we're done with full tiles
         block_offset = storage.dequeue_offset;
@@ -465,7 +463,7 @@ struct ReduceAgent
           consume_tile<false>(
             thread_aggregate, block_offset, ITEMS_PER_TILE, thrust::detail::true_type(), can_vectorize);
 
-          sync_threadblock();
+          __syncthreads();
 
           // Dequeue a tile of items
           if (threadIdx.x == 0)
@@ -473,7 +471,7 @@ struct ReduceAgent
             storage.dequeue_offset = queue.Drain(ITEMS_PER_TILE) + even_share_base;
           }
 
-          sync_threadblock();
+          __syncthreads();
 
           // Grab tile offset and check if we're done with full tiles
           block_offset = storage.dequeue_offset;
@@ -586,7 +584,7 @@ struct DrainAgent
   template <class Arch>
   struct PtxPlan : PtxPolicy<1>
   {};
-  using ptx_plan = core::specialize_plan<PtxPlan>;
+  using ptx_plan = core::detail::specialize_plan<PtxPlan>;
 
   //---------------------------------------------------------------------
   // Agent entry point
@@ -609,10 +607,10 @@ cudaError_t THRUST_RUNTIME_FUNCTION doit_step(
   OutputIt output_it,
   cudaStream_t stream)
 {
-  using core::AgentLauncher;
-  using core::AgentPlan;
-  using core::cuda_optional;
-  using core::get_agent_plan;
+  using core::detail::AgentLauncher;
+  using core::detail::AgentPlan;
+  using core::detail::cuda_optional;
+  using core::detail::get_agent_plan;
 
   using UnsignedSize = typename detail::make_unsigned_special<Size>::type;
 
@@ -629,7 +627,7 @@ cudaError_t THRUST_RUNTIME_FUNCTION doit_step(
 
   if (num_items <= reduce_plan.items_per_tile)
   {
-    size_t vshmem_size = core::vshmem_size(reduce_plan.shared_memory_size, 1);
+    size_t vshmem_size = core::detail::vshmem_size(reduce_plan.shared_memory_size, 1);
 
     // small, single tile size
     if (d_temp_storage == nullptr)
@@ -646,7 +644,7 @@ cudaError_t THRUST_RUNTIME_FUNCTION doit_step(
   else
   {
     // regular size
-    cuda_optional<int> sm_count = core::get_sm_count();
+    cuda_optional<int> sm_count = core::detail::get_sm_count();
     CUDA_CUB_RET_IF_FAIL(sm_count.status());
 
     // reduction will not use more cta counts than requested
@@ -670,7 +668,7 @@ cudaError_t THRUST_RUNTIME_FUNCTION doit_step(
     // we will launch at most "max_blocks" blocks in a grid
     // so preallocate virtual shared memory storage for this if required
     //
-    size_t vshmem_size = core::vshmem_size(reduce_plan.shared_memory_size, max_blocks);
+    size_t vshmem_size = core::detail::vshmem_size(reduce_plan.shared_memory_size, max_blocks);
 
     // Temporary storage allocation requirements
     void* allocations[3]       = {nullptr, nullptr, nullptr};
@@ -755,14 +753,14 @@ reduce(execution_policy<Derived>& policy, InputIt first, Size num_items, T init,
   void* allocations[2]       = {nullptr, nullptr};
 
   size_t storage_size = 0;
-  status              = core::alias_storage(nullptr, storage_size, allocations, allocation_sizes);
+  status              = core::detail::alias_storage(nullptr, storage_size, allocations, allocation_sizes);
   cuda_cub::throw_on_error(status, "reduce failed on 1st alias_storage");
 
   // Allocate temporary storage.
   thrust::detail::temporary_array<std::uint8_t, Derived> tmp(policy, storage_size);
   void* ptr = static_cast<void*>(tmp.data().get());
 
-  status = core::alias_storage(ptr, storage_size, allocations, allocation_sizes);
+  status = core::detail::alias_storage(ptr, storage_size, allocations, allocation_sizes);
   cuda_cub::throw_on_error(status, "reduce failed on 2nd alias_storage");
 
   T* d_result = thrust::detail::aligned_reinterpret_cast<T*>(allocations[0]);
diff --git a/thrust/thrust/system/cuda/detail/reduce_by_key.h b/thrust/thrust/system/cuda/detail/reduce_by_key.h
index ae1f0ffab96..8c1db436085 100644
--- a/thrust/thrust/system/cuda/detail/reduce_by_key.h
+++ b/thrust/thrust/system/cuda/detail/reduce_by_key.h
@@ -115,7 +115,7 @@ template <class Arch, class Key, class Value>
 struct Tuning;
 
 template <class Key, class Value>
-struct Tuning<sm52, Key, Value>
+struct Tuning<core::detail::sm52, Key, Value>
 {
   enum
   {
@@ -163,11 +163,11 @@ struct ReduceByKeyAgent
   {
     using tuning = Tuning<Arch, key_type, value_type>;
 
-    using KeysLoadIt   = typename core::LoadIterator<PtxPlan, KeysInputIt>::type;
-    using ValuesLoadIt = typename core::LoadIterator<PtxPlan, ValuesInputIt>::type;
+    using KeysLoadIt   = typename core::detail::LoadIterator<PtxPlan, KeysInputIt>::type;
+    using ValuesLoadIt = typename core::detail::LoadIterator<PtxPlan, ValuesInputIt>::type;
 
-    using BlockLoadKeys   = typename core::BlockLoad<PtxPlan, KeysLoadIt>::type;
-    using BlockLoadValues = typename core::BlockLoad<PtxPlan, ValuesLoadIt>::type;
+    using BlockLoadKeys   = typename core::detail::BlockLoad<PtxPlan, KeysLoadIt>::type;
+    using BlockLoadValues = typename core::detail::BlockLoad<PtxPlan, ValuesLoadIt>::type;
 
     using BlockDiscontinuityKeys = cub::BlockDiscontinuity<key_type, PtxPlan::BLOCK_THREADS, 1, 1, Arch::ver>;
 
@@ -188,11 +188,11 @@ struct ReduceByKeyAgent
       typename BlockLoadKeys::TempStorage load_keys;
       typename BlockLoadValues::TempStorage load_values;
 
-      core::uninitialized_array<key_value_pair_t, PtxPlan::ITEMS_PER_TILE + 1> raw_exchange;
+      core::detail::uninitialized_array<key_value_pair_t, PtxPlan::ITEMS_PER_TILE + 1> raw_exchange;
     }; // union TempStorage
   }; // struct PtxPlan
 
-  using ptx_plan = typename core::specialize_plan_msvc10_war<PtxPlan>::type::type;
+  using ptx_plan = typename core::detail::specialize_plan_msvc10_war<PtxPlan>::type::type;
 
   using KeysLoadIt             = typename ptx_plan::KeysLoadIt;
   using ValuesLoadIt           = typename ptx_plan::ValuesLoadIt;
@@ -360,9 +360,7 @@ struct ReduceByKeyAgent
       size_type num_tile_segments,
       size_type num_tile_segments_prefix)
     {
-      using core::sync_threadblock;
-
-      sync_threadblock();
+      __syncthreads();
 
       // Compact and scatter keys
 #  pragma unroll
@@ -375,7 +373,7 @@ struct ReduceByKeyAgent
         }
       }
 
-      sync_threadblock();
+      __syncthreads();
 
       for (int item = threadIdx.x; item < num_tile_segments; item += BLOCK_THREADS)
       {
@@ -445,8 +443,6 @@ struct ReduceByKeyAgent
     template <bool IS_LAST_TILE>
     THRUST_DEVICE_FUNCTION void consume_first_tile(Size num_remaining, Size tile_offset, ScanTileState& tile_state)
     {
-      using core::sync_threadblock;
-
       key_type keys[ITEMS_PER_THREAD]; // Tile keys
       key_type pred_keys[ITEMS_PER_THREAD]; // Tile keys shifted up (predecessor)
       value_type values[ITEMS_PER_THREAD]; // Tile values
@@ -468,7 +464,7 @@ struct ReduceByKeyAgent
         BlockLoadKeys(storage.load_keys).Load(keys_load_it + tile_offset, keys);
       }
 
-      sync_threadblock();
+      __syncthreads();
 
       // Load values (last tile repeats final element)
       if (IS_LAST_TILE)
@@ -481,7 +477,7 @@ struct ReduceByKeyAgent
         BlockLoadValues(storage.load_values).Load(values_load_it + tile_offset, values);
       }
 
-      sync_threadblock();
+      __syncthreads();
 
       // Set head segment_flags.
       // First tile sets the first flag for the first item
@@ -540,8 +536,6 @@ struct ReduceByKeyAgent
     THRUST_DEVICE_FUNCTION void
     consume_subsequent_tile(Size num_remaining, int tile_idx, Size tile_offset, ScanTileState& tile_state)
     {
-      using core::sync_threadblock;
-
       key_type keys[ITEMS_PER_THREAD]; // Tile keys
       key_type pred_keys[ITEMS_PER_THREAD]; // Tile keys shifted up (predecessor)
       value_type values[ITEMS_PER_THREAD]; // Tile values
@@ -563,7 +557,7 @@ struct ReduceByKeyAgent
 
       key_type tile_pred_key = (threadIdx.x == 0) ? key_type(keys_load_it[tile_offset - 1]) : key_type();
 
-      sync_threadblock();
+      __syncthreads();
 
       // Load values (last tile repeats final element)
       if (IS_LAST_TILE)
@@ -576,7 +570,7 @@ struct ReduceByKeyAgent
         BlockLoadValues(storage.load_values).Load(values_load_it + tile_offset, values);
       }
 
-      sync_threadblock();
+      __syncthreads();
 
       // Set head segment_flags
       BlockDiscontinuityKeys(storage.scan_storage.discontinuity)
@@ -635,8 +629,8 @@ struct ReduceByKeyAgent
       int /*num_tiles*/,
       ScanTileState& tile_state)
         : storage(storage_)
-        , keys_load_it(core::make_load_iterator(ptx_plan(), keys_input_it_))
-        , values_load_it(core::make_load_iterator(ptx_plan(), values_input_it_))
+        , keys_load_it(core::detail::make_load_iterator(ptx_plan(), keys_input_it_))
+        , values_load_it(core::detail::make_load_iterator(ptx_plan(), values_input_it_))
         , keys_output_it(keys_output_it_)
         , values_output_it(values_output_it_)
         , num_runs_output_it(num_runs_output_it_)
@@ -703,7 +697,7 @@ struct InitAgent
   template <class Arch>
   struct PtxPlan : PtxPolicy<128>
   {};
-  using ptx_plan = core::specialize_plan<PtxPlan>;
+  using ptx_plan = core::detail::specialize_plan<PtxPlan>;
 
   //---------------------------------------------------------------------
   // Agent entry point
@@ -740,8 +734,8 @@ THRUST_RUNTIME_FUNCTION cudaError_t doit_step(
   Size num_items,
   cudaStream_t stream)
 {
-  using core::AgentLauncher;
-  using core::AgentPlan;
+  using core::detail::AgentLauncher;
+  using core::detail::AgentPlan;
 
   cudaError_t status = cudaSuccess;
   if (num_items == 0)
@@ -762,7 +756,7 @@ THRUST_RUNTIME_FUNCTION cudaError_t doit_step(
   int tile_size  = reduce_by_key_plan.items_per_tile;
   Size num_tiles = ::cuda::ceil_div(num_items, tile_size);
 
-  size_t vshmem_size = core::vshmem_size(reduce_by_key_plan.shared_memory_size, num_tiles);
+  size_t vshmem_size = core::detail::vshmem_size(reduce_by_key_plan.shared_memory_size, num_tiles);
 
   size_t allocation_sizes[2] = {9, vshmem_size};
   status                     = ScanTileState::AllocationSize(static_cast<int>(num_tiles), allocation_sizes[0]);
@@ -848,14 +842,14 @@ THRUST_RUNTIME_FUNCTION pair<KeysOutputIt, ValuesOutputIt> reduce_by_key_dispatc
   void* allocations[2]       = {nullptr, nullptr};
 
   size_t storage_size = 0;
-  status              = core::alias_storage(nullptr, storage_size, allocations, allocation_sizes);
+  status              = core::detail::alias_storage(nullptr, storage_size, allocations, allocation_sizes);
   cuda_cub::throw_on_error(status, "reduce failed on 1st alias_storage");
 
   // Allocate temporary storage.
   thrust::detail::temporary_array<std::uint8_t, Derived> tmp(policy, storage_size);
   void* ptr = static_cast<void*>(tmp.data().get());
 
-  status = core::alias_storage(ptr, storage_size, allocations, allocation_sizes);
+  status = core::detail::alias_storage(ptr, storage_size, allocations, allocation_sizes);
   cuda_cub::throw_on_error(status, "reduce failed on 2nd alias_storage");
 
   Size* d_num_runs_out = thrust::detail::aligned_reinterpret_cast<Size*>(allocations[0]);
diff --git a/thrust/thrust/system/cuda/detail/set_operations.h b/thrust/thrust/system/cuda/detail/set_operations.h
index 7a267080bf8..b336f8e55fa 100644
--- a/thrust/thrust/system/cuda/detail/set_operations.h
+++ b/thrust/thrust/system/cuda/detail/set_operations.h
@@ -222,7 +222,7 @@ struct Tuning;
 namespace mpl = thrust::detail::mpl::math;
 
 template <class T, class U>
-struct Tuning<sm52, T, U>
+struct Tuning<core::detail::sm52, T, U>
 {
   enum
   {
@@ -243,7 +243,7 @@ struct Tuning<sm52, T, U>
 }; // tuning sm52
 
 template <class T, class U>
-struct Tuning<sm60, T, U>
+struct Tuning<core::detail::sm60, T, U>
 {
   enum
   {
@@ -290,15 +290,15 @@ struct SetOpAgent
   {
     using tuning = Tuning<Arch, key_type, value_type>;
 
-    using KeysLoadIt1   = typename core::LoadIterator<PtxPlan, KeysIt1>::type;
-    using KeysLoadIt2   = typename core::LoadIterator<PtxPlan, KeysIt2>::type;
-    using ValuesLoadIt1 = typename core::LoadIterator<PtxPlan, ValuesIt1>::type;
-    using ValuesLoadIt2 = typename core::LoadIterator<PtxPlan, ValuesIt2>::type;
+    using KeysLoadIt1   = typename core::detail::LoadIterator<PtxPlan, KeysIt1>::type;
+    using KeysLoadIt2   = typename core::detail::LoadIterator<PtxPlan, KeysIt2>::type;
+    using ValuesLoadIt1 = typename core::detail::LoadIterator<PtxPlan, ValuesIt1>::type;
+    using ValuesLoadIt2 = typename core::detail::LoadIterator<PtxPlan, ValuesIt2>::type;
 
-    using BlockLoadKeys1   = typename core::BlockLoad<PtxPlan, KeysLoadIt1>::type;
-    using BlockLoadKeys2   = typename core::BlockLoad<PtxPlan, KeysLoadIt2>::type;
-    using BlockLoadValues1 = typename core::BlockLoad<PtxPlan, ValuesLoadIt1>::type;
-    using BlockLoadValues2 = typename core::BlockLoad<PtxPlan, ValuesLoadIt2>::type;
+    using BlockLoadKeys1   = typename core::detail::BlockLoad<PtxPlan, KeysLoadIt1>::type;
+    using BlockLoadKeys2   = typename core::detail::BlockLoad<PtxPlan, KeysLoadIt2>::type;
+    using BlockLoadValues1 = typename core::detail::BlockLoad<PtxPlan, ValuesLoadIt1>::type;
+    using BlockLoadValues2 = typename core::detail::BlockLoad<PtxPlan, ValuesLoadIt2>::type;
 
     using TilePrefixCallback = cub::TilePrefixCallbackOp<Size, ::cuda::std::plus<>, ScanTileState, Arch::ver>;
 
@@ -316,7 +316,7 @@ struct SetOpAgent
 
       struct LoadStorage
       {
-        core::uninitialized_array<int, PtxPlan::BLOCK_THREADS> offset;
+        core::detail::uninitialized_array<int, PtxPlan::BLOCK_THREADS> offset;
         union
         {
           // FIXME These don't appear to be used anywhere?
@@ -328,15 +328,15 @@ struct SetOpAgent
           // Allocate extra shmem than truly necessary
           // This will permit to avoid range checks in
           // serial set operations, e.g. serial_set_difference
-          core::uninitialized_array<key_type, PtxPlan::ITEMS_PER_TILE + PtxPlan::BLOCK_THREADS> keys_shared;
+          core::detail::uninitialized_array<key_type, PtxPlan::ITEMS_PER_TILE + PtxPlan::BLOCK_THREADS> keys_shared;
 
-          core::uninitialized_array<value_type, PtxPlan::ITEMS_PER_TILE + PtxPlan::BLOCK_THREADS> values_shared;
+          core::detail::uninitialized_array<value_type, PtxPlan::ITEMS_PER_TILE + PtxPlan::BLOCK_THREADS> values_shared;
         }; // anon union
       } load_storage; // struct LoadStorage
     }; // union TempStorage
   }; // struct PtxPlan
 
-  using ptx_plan = typename core::specialize_plan_msvc10_war<PtxPlan>::type::type;
+  using ptx_plan = typename core::detail::specialize_plan_msvc10_war<PtxPlan>::type::type;
 
   using KeysLoadIt1   = typename ptx_plan::KeysLoadIt1;
   using KeysLoadIt2   = typename ptx_plan::KeysLoadIt2;
@@ -441,8 +441,6 @@ struct SetOpAgent
       Size tile_output_prefix,
       int tile_output_count)
     {
-      using core::sync_threadblock;
-
       int local_scatter_idx = thread_output_prefix - tile_output_prefix;
 #  pragma unroll
       for (int ITEM = 0; ITEM < ITEMS_PER_THREAD; ++ITEM)
@@ -452,7 +450,7 @@ struct SetOpAgent
           shared[local_scatter_idx++] = input[ITEM];
         }
       }
-      sync_threadblock();
+      __syncthreads();
 
       for (int item = threadIdx.x; item < tile_output_count; item += BLOCK_THREADS)
       {
@@ -483,8 +481,7 @@ struct SetOpAgent
     template <bool IS_LAST_TILE>
     void THRUST_DEVICE_FUNCTION consume_tile(Size tile_idx)
     {
-      using core::sync_threadblock;
-      using core::uninitialized_array;
+      using core::detail::uninitialized_array;
 
       pair<Size, Size> partition_beg = partitions[tile_idx + 0];
       pair<Size, Size> partition_end = partitions[tile_idx + 1];
@@ -506,7 +503,7 @@ struct SetOpAgent
 
       reg_to_shared(&storage.load_storage.keys_shared[0], keys_loc);
 
-      sync_threadblock();
+      __syncthreads();
 
       int diag_loc = min<int>(ITEMS_PER_THREAD * threadIdx.x, num_keys1 + num_keys2);
 
@@ -529,7 +526,7 @@ struct SetOpAgent
       int dst                          = threadIdx.x == 0 ? BLOCK_THREADS - 1 : threadIdx.x - 1;
       storage.load_storage.offset[dst] = value;
 
-      core::sync_threadblock();
+      __syncthreads();
 
       pair<int, int> partition1_loc = thrust::make_pair(
         storage.load_storage.offset[threadIdx.x] >> 16, storage.load_storage.offset[threadIdx.x] & 0xFFFF);
@@ -554,7 +551,7 @@ struct SetOpAgent
         indices,
         compare_op,
         set_op);
-      sync_threadblock();
+      __syncthreads();
 #  if 0
         if (ITEMS_PER_THREAD*threadIdx.x >= num_keys1 + num_keys2)
           active_mask = 0;
@@ -588,7 +585,7 @@ struct SetOpAgent
         tile_output_prefix = prefix_cb.GetExclusivePrefix();
       }
 
-      sync_threadblock();
+      __syncthreads();
 
       // scatter results
       //
@@ -605,11 +602,11 @@ struct SetOpAgent
         value_type values_loc[ITEMS_PER_THREAD];
         gmem_to_reg<!IS_LAST_TILE>(values_loc, values1_in + keys1_beg, values2_in + keys2_beg, num_keys1, num_keys2);
 
-        sync_threadblock();
+        __syncthreads();
 
         reg_to_shared(&storage.load_storage.values_shared[0], values_loc);
 
-        sync_threadblock();
+        __syncthreads();
 
         // gather items from shared mem
         //
@@ -622,7 +619,7 @@ struct SetOpAgent
           }
         }
 
-        sync_threadblock();
+        __syncthreads();
 
         scatter(values_out,
                 values_loc,
@@ -660,10 +657,10 @@ struct SetOpAgent
          std::size_t* output_count_)
         : storage(storage_)
         , tile_state(tile_state_)
-        , keys1_in(core::make_load_iterator(ptx_plan(), keys1_))
-        , keys2_in(core::make_load_iterator(ptx_plan(), keys2_))
-        , values1_in(core::make_load_iterator(ptx_plan(), values1_))
-        , values2_in(core::make_load_iterator(ptx_plan(), values2_))
+        , keys1_in(core::detail::make_load_iterator(ptx_plan(), keys1_))
+        , keys2_in(core::detail::make_load_iterator(ptx_plan(), keys2_))
+        , values1_in(core::detail::make_load_iterator(ptx_plan(), values1_))
+        , values2_in(core::detail::make_load_iterator(ptx_plan(), values2_))
         , keys1_count(keys1_count_)
         , keys2_count(keys2_count_)
         , keys_out(keys_out_)
@@ -733,7 +730,7 @@ struct PartitionAgent
   struct PtxPlan : PtxPolicy<256>
   {};
 
-  using ptx_plan = core::specialize_plan<PtxPlan>;
+  using ptx_plan = core::detail::specialize_plan<PtxPlan>;
 
   //---------------------------------------------------------------------
   // Agent entry point
@@ -767,7 +764,7 @@ struct InitAgent
   struct PtxPlan : PtxPolicy<128>
   {};
 
-  using ptx_plan = core::specialize_plan<PtxPlan>;
+  using ptx_plan = core::detail::specialize_plan<PtxPlan>;
 
   //---------------------------------------------------------------------
   // Agent entry point
@@ -1058,8 +1055,8 @@ cudaError_t THRUST_RUNTIME_FUNCTION doit_step(
 
   cudaError_t status = cudaSuccess;
 
-  using core::AgentLauncher;
-  using core::AgentPlan;
+  using core::detail::AgentLauncher;
+  using core::detail::AgentPlan;
 
   using set_op_agent = AgentLauncher<
     SetOpAgent<KeysIt1, KeysIt2, ValuesIt1, ValuesIt2, KeysOutputIt, ValuesOutputIt, Size, CompareOp, SetOp, HAS_VALUES>>;
@@ -1080,13 +1077,13 @@ cudaError_t THRUST_RUNTIME_FUNCTION doit_step(
   status = ScanTileState::AllocationSize(static_cast<int>(num_tiles), tile_agent_storage);
   CUDA_CUB_RET_IF_FAIL(status);
 
-  size_t vshmem_storage          = core::vshmem_size(set_op_plan.shared_memory_size, num_tiles);
+  size_t vshmem_storage          = core::detail::vshmem_size(set_op_plan.shared_memory_size, num_tiles);
   size_t partition_agent_storage = (num_tiles + 1) * sizeof(Size) * 2;
 
   void* allocations[3]       = {nullptr, nullptr, nullptr};
   size_t allocation_sizes[3] = {tile_agent_storage, partition_agent_storage, vshmem_storage};
 
-  status = core::alias_storage(d_temp_storage, temp_storage_size, allocations, allocation_sizes);
+  status = core::detail::alias_storage(d_temp_storage, temp_storage_size, allocations, allocation_sizes);
   CUDA_CUB_RET_IF_FAIL(status);
 
   if (d_temp_storage == nullptr)
@@ -1192,14 +1189,14 @@ THRUST_RUNTIME_FUNCTION pair<KeysOutputIt, ValuesOutputIt> set_operations(
 
   size_t storage_size = 0;
 
-  status = core::alias_storage(nullptr, storage_size, allocations, allocation_sizes);
+  status = core::detail::alias_storage(nullptr, storage_size, allocations, allocation_sizes);
   cuda_cub::throw_on_error(status, "set_operations failed on 1st alias_storage");
 
   // Allocate temporary storage.
   thrust::detail::temporary_array<std::uint8_t, Derived> tmp(policy, storage_size);
   void* ptr = static_cast<void*>(tmp.data().get());
 
-  status = core::alias_storage(ptr, storage_size, allocations, allocation_sizes);
+  status = core::detail::alias_storage(ptr, storage_size, allocations, allocation_sizes);
   cuda_cub::throw_on_error(status, "set_operations failed on 2nd alias_storage");
 
   std::size_t* d_output_count = thrust::detail::aligned_reinterpret_cast<std::size_t*>(allocations[0]);
diff --git a/thrust/thrust/system/cuda/detail/sort.h b/thrust/thrust/system/cuda/detail/sort.h
index 2c3ef85202d..7ad67fd4e0c 100644
--- a/thrust/thrust/system/cuda/detail/sort.h
+++ b/thrust/thrust/system/cuda/detail/sort.h
@@ -58,6 +58,8 @@
 #  include <thrust/system/cuda/detail/util.h>
 #  include <thrust/type_traits/is_contiguous_iterator.h>
 
+#  include <cuda/cmath>
+
 #  include <cstdint>
 
 #  if defined(_CCCL_HAS_NVFP16)
@@ -277,8 +279,8 @@ THRUST_RUNTIME_FUNCTION void radix_sort(execution_policy<Derived>& policy, Key*
     dispatch<SORT_ITEMS, CompareOp>::doit(nullptr, temp_storage_bytes, keys_buffer, items_buffer, keys_count, stream);
   cuda_cub::throw_on_error(status, "radix_sort: failed on 1st step");
 
-  size_t keys_temp_storage  = core::align_to(sizeof(Key) * keys_count, 128);
-  size_t items_temp_storage = core::align_to(sizeof(Item) * items_count, 128);
+  size_t keys_temp_storage  = ::cuda::round_up(sizeof(Key) * keys_count, 128);
+  size_t items_temp_storage = ::cuda::round_up(sizeof(Item) * items_count, 128);
 
   size_t storage_size = keys_temp_storage + items_temp_storage + temp_storage_bytes;
 
diff --git a/thrust/thrust/system/cuda/detail/unique.h b/thrust/thrust/system/cuda/detail/unique.h
index ac94017758b..1d39b161866 100644
--- a/thrust/thrust/system/cuda/detail/unique.h
+++ b/thrust/thrust/system/cuda/detail/unique.h
@@ -123,7 +123,7 @@ struct items_per_thread
 };
 
 template <class T>
-struct Tuning<sm52, T>
+struct Tuning<core::detail::sm52, T>
 {
   const static int INPUT_SIZE = sizeof(T);
   enum
@@ -149,16 +149,16 @@ struct UniqueAgent
   {
     using tuning = Tuning<Arch, item_type>;
 
-    using ItemsLoadIt = typename core::LoadIterator<PtxPlan, ItemsIt>::type;
+    using ItemsLoadIt = typename core::detail::LoadIterator<PtxPlan, ItemsIt>::type;
 
-    using BlockLoadItems = typename core::BlockLoad<PtxPlan, ItemsLoadIt>::type;
+    using BlockLoadItems = typename core::detail::BlockLoad<PtxPlan, ItemsLoadIt>::type;
 
     using BlockDiscontinuityItems = cub::BlockDiscontinuity<item_type, PtxPlan::BLOCK_THREADS, 1, 1, Arch::ver>;
 
     using TilePrefixCallback = cub::TilePrefixCallbackOp<Size, ::cuda::std::plus<>, ScanTileState, Arch::ver>;
     using BlockScan          = cub::BlockScan<Size, PtxPlan::BLOCK_THREADS, PtxPlan::SCAN_ALGORITHM, 1, 1, Arch::ver>;
 
-    using shared_items_t = core::uninitialized_array<item_type, PtxPlan::ITEMS_PER_TILE>;
+    using shared_items_t = core::detail::uninitialized_array<item_type, PtxPlan::ITEMS_PER_TILE>;
 
     union TempStorage
     {
@@ -175,7 +175,7 @@ struct UniqueAgent
     }; // union TempStorage
   }; // struct PtxPlan
 
-  using ptx_plan = typename core::specialize_plan_msvc10_war<PtxPlan>::type::type;
+  using ptx_plan = typename core::detail::specialize_plan_msvc10_war<PtxPlan>::type::type;
 
   using ItemsLoadIt             = typename ptx_plan::ItemsLoadIt;
   using BlockLoadItems          = typename ptx_plan::BlockLoadItems;
@@ -224,8 +224,6 @@ struct UniqueAgent
       Size num_selections_prefix,
       Size /*num_selections*/)
     {
-      using core::sync_threadblock;
-
 #  pragma unroll
       for (int ITEM = 0; ITEM < ITEMS_PER_THREAD; ++ITEM)
       {
@@ -236,14 +234,14 @@ struct UniqueAgent
         }
       }
 
-      sync_threadblock();
+      __syncthreads();
 
       for (int item = threadIdx.x; item < num_tile_selections; item += BLOCK_THREADS)
       {
         items_out[num_selections_prefix + item] = get_shared()[item];
       }
 
-      sync_threadblock();
+      __syncthreads();
     }
 
     //---------------------------------------------------------------------
@@ -253,8 +251,7 @@ struct UniqueAgent
     template <bool IS_LAST_TILE, bool IS_FIRST_TILE>
     Size THRUST_DEVICE_FUNCTION consume_tile_impl(int num_tile_items, int tile_idx, Size tile_base)
     {
-      using core::sync_threadblock;
-      using core::uninitialized_array;
+      using core::detail::uninitialized_array;
 
       item_type items_loc[ITEMS_PER_THREAD];
       Size selection_flags[ITEMS_PER_THREAD];
@@ -270,7 +267,7 @@ struct UniqueAgent
         BlockLoadItems(temp_storage.load_items).Load(items_in + tile_base, items_loc);
       }
 
-      sync_threadblock();
+      __syncthreads();
 
       if (IS_FIRST_TILE)
       {
@@ -294,7 +291,7 @@ struct UniqueAgent
         }
       }
 
-      sync_threadblock();
+      __syncthreads();
 
       Size num_tile_selections   = 0;
       Size num_selections        = 0;
@@ -337,7 +334,7 @@ struct UniqueAgent
         }
       }
 
-      sync_threadblock();
+      __syncthreads();
 
       scatter(items_loc,
               selection_flags,
@@ -420,7 +417,7 @@ struct UniqueAgent
 
     impl(storage,
          tile_state,
-         core::make_load_iterator(ptx_plan(), items_in),
+         core::detail::make_load_iterator(ptx_plan(), items_in),
          items_out,
          binary_pred,
          num_items,
@@ -435,7 +432,7 @@ struct InitAgent
   template <class Arch>
   struct PtxPlan : PtxPolicy<128>
   {};
-  using ptx_plan = core::specialize_plan<PtxPlan>;
+  using ptx_plan = core::detail::specialize_plan<PtxPlan>;
 
   //---------------------------------------------------------------------
   // Agent entry point
@@ -463,9 +460,9 @@ static cudaError_t THRUST_RUNTIME_FUNCTION doit_step(
   Size num_items,
   cudaStream_t stream)
 {
-  using core::AgentLauncher;
-  using core::AgentPlan;
-  using core::get_agent_plan;
+  using core::detail::AgentLauncher;
+  using core::detail::AgentPlan;
+  using core::detail::get_agent_plan;
 
   using unique_agent = AgentLauncher<UniqueAgent<ItemsInputIt, ItemsOutputIt, BinaryPred, Size, NumSelectedOutIt>>;
 
@@ -473,14 +470,14 @@ static cudaError_t THRUST_RUNTIME_FUNCTION doit_step(
 
   using init_agent = AgentLauncher<InitAgent<ScanTileState, NumSelectedOutIt, Size>>;
 
-  using core::get_plan;
+  using core::detail::get_plan;
   typename get_plan<init_agent>::type init_plan     = init_agent::get_plan();
   typename get_plan<unique_agent>::type unique_plan = unique_agent::get_plan(stream);
 
   int tile_size    = unique_plan.items_per_tile;
   size_t num_tiles = ::cuda::ceil_div(num_items, tile_size);
 
-  size_t vshmem_size = core::vshmem_size(unique_plan.shared_memory_size, num_tiles);
+  size_t vshmem_size = core::detail::vshmem_size(unique_plan.shared_memory_size, num_tiles);
 
   cudaError_t status         = cudaSuccess;
   size_t allocation_sizes[2] = {0, vshmem_size};
@@ -550,14 +547,14 @@ THRUST_RUNTIME_FUNCTION ItemsOutputIt unique(
   void* allocations[2]       = {nullptr, nullptr};
 
   size_t storage_size = 0;
-  status              = core::alias_storage(nullptr, storage_size, allocations, allocation_sizes);
+  status              = core::detail::alias_storage(nullptr, storage_size, allocations, allocation_sizes);
   cuda_cub::throw_on_error(status, "unique: failed on 1st step");
 
   // Allocate temporary storage.
   thrust::detail::temporary_array<std::uint8_t, Derived> tmp(policy, storage_size);
   void* ptr = static_cast<void*>(tmp.data().get());
 
-  status = core::alias_storage(ptr, storage_size, allocations, allocation_sizes);
+  status = core::detail::alias_storage(ptr, storage_size, allocations, allocation_sizes);
   cuda_cub::throw_on_error(status, "unique: failed on 2nd step");
 
   size_type* d_num_selected_out = thrust::detail::aligned_reinterpret_cast<size_type*>(allocations[0]);

From 9a27ba3ba2da14dd9b8bd22c04ea057d9a7f493b Mon Sep 17 00:00:00 2001
From: Bernhard Manfred Gruber <bernhardmgruber@gmail.com>
Date: Thu, 30 Jan 2025 13:07:45 +0100
Subject: [PATCH 20/33] PTX: Add clusterlaunchcontrol (#3589)

Co-authored-by: Allard Hendriksen <ahendriksen@nvidia.com>
---
 docs/libcudacxx/ptx/instructions.rst          |  1 +
 .../ptx/instructions/clusterlaunchcontrol.rst | 11 ++++++
 .../__ptx/instructions/clusterlaunchcontrol.h | 37 +++++++++++++++++++
 libcudacxx/include/cuda/ptx                   |  1 +
 .../ptx.clusterlaunchcontrol.compile.pass.cpp | 22 +++++++++++
 5 files changed, 72 insertions(+)
 create mode 100644 docs/libcudacxx/ptx/instructions/clusterlaunchcontrol.rst
 create mode 100644 libcudacxx/include/cuda/__ptx/instructions/clusterlaunchcontrol.h
 create mode 100644 libcudacxx/test/libcudacxx/cuda/ptx/ptx.clusterlaunchcontrol.compile.pass.cpp

diff --git a/docs/libcudacxx/ptx/instructions.rst b/docs/libcudacxx/ptx/instructions.rst
index f0776974eec..32db843c28d 100644
--- a/docs/libcudacxx/ptx/instructions.rst
+++ b/docs/libcudacxx/ptx/instructions.rst
@@ -7,6 +7,7 @@ PTX Instructions
    :maxdepth: 1
 
    instructions/barrier_cluster
+   instructions/clusterlaunchcontrol
    instructions/cp_async_bulk
    instructions/cp_async_bulk_commit_group
    instructions/cp_async_bulk_wait_group
diff --git a/docs/libcudacxx/ptx/instructions/clusterlaunchcontrol.rst b/docs/libcudacxx/ptx/instructions/clusterlaunchcontrol.rst
new file mode 100644
index 00000000000..75fe44f6f22
--- /dev/null
+++ b/docs/libcudacxx/ptx/instructions/clusterlaunchcontrol.rst
@@ -0,0 +1,11 @@
+.. _libcudacxx-ptx-instructions-clusterlaunchcontrol:
+
+clusterlaunchcontrol
+====================
+
+-  PTX ISA:
+   `clusterlaunchcontrol.try_cancel <https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#parallel-synchronization-and-communication-instructions-clusterlaunchcontrol-try-cancel>`__
+-  PTX ISA:
+   `clusterlaunchcontrol.query_cancel <https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#parallel-synchronization-and-communication-instructions-clusterlaunchcontrol-query-cancel>`__
+
+.. include:: generated/clusterlaunchcontrol.rst
diff --git a/libcudacxx/include/cuda/__ptx/instructions/clusterlaunchcontrol.h b/libcudacxx/include/cuda/__ptx/instructions/clusterlaunchcontrol.h
new file mode 100644
index 00000000000..b15cfddf4a0
--- /dev/null
+++ b/libcudacxx/include/cuda/__ptx/instructions/clusterlaunchcontrol.h
@@ -0,0 +1,37 @@
+// -*- C++ -*-
+//===----------------------------------------------------------------------===//
+//
+// Part of libcu++, the C++ Standard Library for your entire system,
+// under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+// SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef _CUDA_PTX_CLUSTERLAUNCHCONTROL_H_
+#define _CUDA_PTX_CLUSTERLAUNCHCONTROL_H_
+
+#include <cuda/std/detail/__config>
+
+#if defined(_CCCL_IMPLICIT_SYSTEM_HEADER_GCC)
+#  pragma GCC system_header
+#elif defined(_CCCL_IMPLICIT_SYSTEM_HEADER_CLANG)
+#  pragma clang system_header
+#elif defined(_CCCL_IMPLICIT_SYSTEM_HEADER_MSVC)
+#  pragma system_header
+#endif // no system header
+
+#include <cuda/__ptx/ptx_dot_variants.h>
+#include <cuda/__ptx/ptx_helper_functions.h>
+#include <cuda/std/cstdint>
+
+#include <nv/target> // __CUDA_MINIMUM_ARCH__ and friends
+
+_LIBCUDACXX_BEGIN_NAMESPACE_CUDA_PTX
+
+#include <cuda/__ptx/instructions/generated/clusterlaunchcontrol.h>
+
+_LIBCUDACXX_END_NAMESPACE_CUDA_PTX
+
+#endif // _CUDA_PTX_CLUSTERLAUNCHCONTROL_H_
diff --git a/libcudacxx/include/cuda/ptx b/libcudacxx/include/cuda/ptx
index 4798973df77..7087dd97d2a 100644
--- a/libcudacxx/include/cuda/ptx
+++ b/libcudacxx/include/cuda/ptx
@@ -70,6 +70,7 @@
  */
 
 #include <cuda/__ptx/instructions/barrier_cluster.h>
+#include <cuda/__ptx/instructions/clusterlaunchcontrol.h>
 #include <cuda/__ptx/instructions/cp_async_bulk.h>
 #include <cuda/__ptx/instructions/cp_async_bulk_commit_group.h>
 #include <cuda/__ptx/instructions/cp_async_bulk_tensor.h>
diff --git a/libcudacxx/test/libcudacxx/cuda/ptx/ptx.clusterlaunchcontrol.compile.pass.cpp b/libcudacxx/test/libcudacxx/cuda/ptx/ptx.clusterlaunchcontrol.compile.pass.cpp
new file mode 100644
index 00000000000..212414c4535
--- /dev/null
+++ b/libcudacxx/test/libcudacxx/cuda/ptx/ptx.clusterlaunchcontrol.compile.pass.cpp
@@ -0,0 +1,22 @@
+//===----------------------------------------------------------------------===//
+//
+// Part of libcu++, the C++ Standard Library for your entire system,
+// under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+// SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES.
+//
+//===----------------------------------------------------------------------===//
+// UNSUPPORTED: libcpp-has-no-threads
+
+// <cuda/ptx>
+
+#include <cuda/ptx>
+#include <cuda/std/utility>
+
+#include "generated/clusterlaunchcontrol.h"
+
+int main(int, char**)
+{
+  return 0;
+}

From b1f2e63dafcb8d1379819e80375b1cd33393f449 Mon Sep 17 00:00:00 2001
From: Bernhard Manfred Gruber <bernhardmgruber@gmail.com>
Date: Thu, 30 Jan 2025 13:10:21 +0100
Subject: [PATCH 21/33] PTX: Add st.bulk (#3604)

Co-authored-by: Allard Hendriksen <ahendriksen@nvidia.com>
---
 docs/libcudacxx/ptx/instructions.rst          |  1 +
 docs/libcudacxx/ptx/instructions/st_bulk.rst  |  9 +++++
 .../include/cuda/__ptx/instructions/st_bulk.h | 37 +++++++++++++++++++
 libcudacxx/include/cuda/ptx                   |  1 +
 .../cuda/ptx/ptx.st.bulk.compile.pass.cpp     | 22 +++++++++++
 5 files changed, 70 insertions(+)
 create mode 100644 docs/libcudacxx/ptx/instructions/st_bulk.rst
 create mode 100644 libcudacxx/include/cuda/__ptx/instructions/st_bulk.h
 create mode 100644 libcudacxx/test/libcudacxx/cuda/ptx/ptx.st.bulk.compile.pass.cpp

diff --git a/docs/libcudacxx/ptx/instructions.rst b/docs/libcudacxx/ptx/instructions.rst
index 32db843c28d..ebf6e31f716 100644
--- a/docs/libcudacxx/ptx/instructions.rst
+++ b/docs/libcudacxx/ptx/instructions.rst
@@ -24,6 +24,7 @@ PTX Instructions
    instructions/mbarrier_try_wait
    instructions/red_async
    instructions/st_async
+   instructions/st_bulk
    instructions/tensormap_replace
    instructions/tensormap_cp_fenceproxy
    instructions/special_registers
diff --git a/docs/libcudacxx/ptx/instructions/st_bulk.rst b/docs/libcudacxx/ptx/instructions/st_bulk.rst
new file mode 100644
index 00000000000..64886598909
--- /dev/null
+++ b/docs/libcudacxx/ptx/instructions/st_bulk.rst
@@ -0,0 +1,9 @@
+.. _libcudacxx-ptx-instructions-st-bulk:
+
+st.bulk
+=======
+
+-  PTX ISA:
+   `st.bulk <https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#data-movement-and-conversion-instructions-st-bulk>`__
+
+.. include:: generated/st_bulk.rst
diff --git a/libcudacxx/include/cuda/__ptx/instructions/st_bulk.h b/libcudacxx/include/cuda/__ptx/instructions/st_bulk.h
new file mode 100644
index 00000000000..686e0ecf166
--- /dev/null
+++ b/libcudacxx/include/cuda/__ptx/instructions/st_bulk.h
@@ -0,0 +1,37 @@
+// -*- C++ -*-
+//===----------------------------------------------------------------------===//
+//
+// Part of libcu++, the C++ Standard Library for your entire system,
+// under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+// SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef _CUDA_PTX_ST_BULK_H_
+#define _CUDA_PTX_ST_BULK_H_
+
+#include <cuda/std/detail/__config>
+
+#if defined(_CCCL_IMPLICIT_SYSTEM_HEADER_GCC)
+#  pragma GCC system_header
+#elif defined(_CCCL_IMPLICIT_SYSTEM_HEADER_CLANG)
+#  pragma clang system_header
+#elif defined(_CCCL_IMPLICIT_SYSTEM_HEADER_MSVC)
+#  pragma system_header
+#endif // no system header
+
+#include <cuda/__ptx/ptx_dot_variants.h>
+#include <cuda/__ptx/ptx_helper_functions.h>
+#include <cuda/std/cstdint>
+
+#include <nv/target> // __CUDA_MINIMUM_ARCH__ and friends
+
+_LIBCUDACXX_BEGIN_NAMESPACE_CUDA_PTX
+
+#include <cuda/__ptx/instructions/generated/st_bulk.h>
+
+_LIBCUDACXX_END_NAMESPACE_CUDA_PTX
+
+#endif // _CUDA_PTX_ST_BULK_H_
diff --git a/libcudacxx/include/cuda/ptx b/libcudacxx/include/cuda/ptx
index 7087dd97d2a..db9e70ab7e6 100644
--- a/libcudacxx/include/cuda/ptx
+++ b/libcudacxx/include/cuda/ptx
@@ -86,6 +86,7 @@
 #include <cuda/__ptx/instructions/mbarrier_wait.h>
 #include <cuda/__ptx/instructions/red_async.h>
 #include <cuda/__ptx/instructions/st_async.h>
+#include <cuda/__ptx/instructions/st_bulk.h>
 #include <cuda/__ptx/instructions/tensormap_cp_fenceproxy.h>
 #include <cuda/__ptx/instructions/tensormap_replace.h>
 
diff --git a/libcudacxx/test/libcudacxx/cuda/ptx/ptx.st.bulk.compile.pass.cpp b/libcudacxx/test/libcudacxx/cuda/ptx/ptx.st.bulk.compile.pass.cpp
new file mode 100644
index 00000000000..951e1a9f513
--- /dev/null
+++ b/libcudacxx/test/libcudacxx/cuda/ptx/ptx.st.bulk.compile.pass.cpp
@@ -0,0 +1,22 @@
+//===----------------------------------------------------------------------===//
+//
+// Part of libcu++, the C++ Standard Library for your entire system,
+// under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+// SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES.
+//
+//===----------------------------------------------------------------------===//
+// UNSUPPORTED: libcpp-has-no-threads
+
+// <cuda/ptx>
+
+#include <cuda/ptx>
+#include <cuda/std/utility>
+
+#include "generated/st_bulk.h"
+
+int main(int, char**)
+{
+  return 0;
+}

From afa2ca25d00fc9bd8037b3b2ca064f2c18708bfc Mon Sep 17 00:00:00 2001
From: Bernhard Manfred Gruber <bernhardmgruber@gmail.com>
Date: Thu, 30 Jan 2025 13:10:35 +0100
Subject: [PATCH 22/33] PTX: Add multimem instructions (#3603)

* Add multimem.ld_reduce
* Add multimem.red
* Add multimem.st

Co-authored-by: Allard Hendriksen <ahendriksen@nvidia.com>
---
 docs/libcudacxx/ptx/instructions.rst          |  3 ++
 .../ptx/instructions/multimem_ld_reduce.rst   |  9 +++++
 .../ptx/instructions/multimem_red.rst         |  9 +++++
 .../ptx/instructions/multimem_st.rst          |  9 +++++
 .../__ptx/instructions/multimem_ld_reduce.h   | 37 +++++++++++++++++++
 .../cuda/__ptx/instructions/multimem_red.h    | 37 +++++++++++++++++++
 .../cuda/__ptx/instructions/multimem_st.h     | 37 +++++++++++++++++++
 libcudacxx/include/cuda/ptx                   |  3 ++
 .../ptx.multimem.ld_reduce.compile.pass.cpp   | 22 +++++++++++
 .../ptx/ptx.multimem.red.compile.pass.cpp     | 22 +++++++++++
 .../cuda/ptx/ptx.multimem.st.compile.pass.cpp | 22 +++++++++++
 11 files changed, 210 insertions(+)
 create mode 100644 docs/libcudacxx/ptx/instructions/multimem_ld_reduce.rst
 create mode 100644 docs/libcudacxx/ptx/instructions/multimem_red.rst
 create mode 100644 docs/libcudacxx/ptx/instructions/multimem_st.rst
 create mode 100644 libcudacxx/include/cuda/__ptx/instructions/multimem_ld_reduce.h
 create mode 100644 libcudacxx/include/cuda/__ptx/instructions/multimem_red.h
 create mode 100644 libcudacxx/include/cuda/__ptx/instructions/multimem_st.h
 create mode 100644 libcudacxx/test/libcudacxx/cuda/ptx/ptx.multimem.ld_reduce.compile.pass.cpp
 create mode 100644 libcudacxx/test/libcudacxx/cuda/ptx/ptx.multimem.red.compile.pass.cpp
 create mode 100644 libcudacxx/test/libcudacxx/cuda/ptx/ptx.multimem.st.compile.pass.cpp

diff --git a/docs/libcudacxx/ptx/instructions.rst b/docs/libcudacxx/ptx/instructions.rst
index ebf6e31f716..797e26d9911 100644
--- a/docs/libcudacxx/ptx/instructions.rst
+++ b/docs/libcudacxx/ptx/instructions.rst
@@ -22,6 +22,9 @@ PTX Instructions
    instructions/mbarrier_expect_tx
    instructions/mbarrier_test_wait
    instructions/mbarrier_try_wait
+   instructions/multimem_ld_reduce
+   instructions/multimem_red
+   instructions/multimem_st
    instructions/red_async
    instructions/st_async
    instructions/st_bulk
diff --git a/docs/libcudacxx/ptx/instructions/multimem_ld_reduce.rst b/docs/libcudacxx/ptx/instructions/multimem_ld_reduce.rst
new file mode 100644
index 00000000000..e9f5212131b
--- /dev/null
+++ b/docs/libcudacxx/ptx/instructions/multimem_ld_reduce.rst
@@ -0,0 +1,9 @@
+.. _libcudacxx-ptx-instructions-multimem-ld_reduce:
+
+multimem.ld_reduce
+==================
+
+-  PTX ISA:
+   `multimem.ld_reduce <https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#data-movement-and-conversion-instructions-multimem-ld-reduce-multimem-st-multimem-red>`__
+
+.. include:: generated/multimem_ld_reduce.rst
diff --git a/docs/libcudacxx/ptx/instructions/multimem_red.rst b/docs/libcudacxx/ptx/instructions/multimem_red.rst
new file mode 100644
index 00000000000..0a6511b78d1
--- /dev/null
+++ b/docs/libcudacxx/ptx/instructions/multimem_red.rst
@@ -0,0 +1,9 @@
+.. _libcudacxx-ptx-instructions-multimem-red:
+
+multimem.red
+============
+
+-  PTX ISA:
+   `multimem.red <https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#data-movement-and-conversion-instructions-multimem-ld-reduce-multimem-st-multimem-red>`__
+
+.. include:: generated/multimem_red.rst
diff --git a/docs/libcudacxx/ptx/instructions/multimem_st.rst b/docs/libcudacxx/ptx/instructions/multimem_st.rst
new file mode 100644
index 00000000000..75197f440c6
--- /dev/null
+++ b/docs/libcudacxx/ptx/instructions/multimem_st.rst
@@ -0,0 +1,9 @@
+.. _libcudacxx-ptx-instructions-multimem-st:
+
+multimem.st
+===========
+
+-  PTX ISA:
+   `multimem.st <https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#data-movement-and-conversion-instructions-multimem-ld-reduce-multimem-st-multimem-red>`__
+
+.. include:: generated/multimem_st.rst
diff --git a/libcudacxx/include/cuda/__ptx/instructions/multimem_ld_reduce.h b/libcudacxx/include/cuda/__ptx/instructions/multimem_ld_reduce.h
new file mode 100644
index 00000000000..29081e6107e
--- /dev/null
+++ b/libcudacxx/include/cuda/__ptx/instructions/multimem_ld_reduce.h
@@ -0,0 +1,37 @@
+// -*- C++ -*-
+//===----------------------------------------------------------------------===//
+//
+// Part of libcu++, the C++ Standard Library for your entire system,
+// under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+// SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef _CUDA_PTX_MULTIMEM_LD_REDUCE_H_
+#define _CUDA_PTX_MULTIMEM_LD_REDUCE_H_
+
+#include <cuda/std/detail/__config>
+
+#if defined(_CCCL_IMPLICIT_SYSTEM_HEADER_GCC)
+#  pragma GCC system_header
+#elif defined(_CCCL_IMPLICIT_SYSTEM_HEADER_CLANG)
+#  pragma clang system_header
+#elif defined(_CCCL_IMPLICIT_SYSTEM_HEADER_MSVC)
+#  pragma system_header
+#endif // no system header
+
+#include <cuda/__ptx/ptx_dot_variants.h>
+#include <cuda/__ptx/ptx_helper_functions.h>
+#include <cuda/std/cstdint>
+
+#include <nv/target> // __CUDA_MINIMUM_ARCH__ and friends
+
+_LIBCUDACXX_BEGIN_NAMESPACE_CUDA_PTX
+
+#include <cuda/__ptx/instructions/generated/multimem_ld_reduce.h>
+
+_LIBCUDACXX_END_NAMESPACE_CUDA_PTX
+
+#endif // _CUDA_PTX_MULTIMEM_LD_REDUCE_H_
diff --git a/libcudacxx/include/cuda/__ptx/instructions/multimem_red.h b/libcudacxx/include/cuda/__ptx/instructions/multimem_red.h
new file mode 100644
index 00000000000..f0fc4e4d0e5
--- /dev/null
+++ b/libcudacxx/include/cuda/__ptx/instructions/multimem_red.h
@@ -0,0 +1,37 @@
+// -*- C++ -*-
+//===----------------------------------------------------------------------===//
+//
+// Part of libcu++, the C++ Standard Library for your entire system,
+// under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+// SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef _CUDA_PTX_MULTIMEM_RED_H_
+#define _CUDA_PTX_MULTIMEM_RED_H_
+
+#include <cuda/std/detail/__config>
+
+#if defined(_CCCL_IMPLICIT_SYSTEM_HEADER_GCC)
+#  pragma GCC system_header
+#elif defined(_CCCL_IMPLICIT_SYSTEM_HEADER_CLANG)
+#  pragma clang system_header
+#elif defined(_CCCL_IMPLICIT_SYSTEM_HEADER_MSVC)
+#  pragma system_header
+#endif // no system header
+
+#include <cuda/__ptx/ptx_dot_variants.h>
+#include <cuda/__ptx/ptx_helper_functions.h>
+#include <cuda/std/cstdint>
+
+#include <nv/target> // __CUDA_MINIMUM_ARCH__ and friends
+
+_LIBCUDACXX_BEGIN_NAMESPACE_CUDA_PTX
+
+#include <cuda/__ptx/instructions/generated/multimem_red.h>
+
+_LIBCUDACXX_END_NAMESPACE_CUDA_PTX
+
+#endif // _CUDA_PTX_MULTIMEM_RED_H_
diff --git a/libcudacxx/include/cuda/__ptx/instructions/multimem_st.h b/libcudacxx/include/cuda/__ptx/instructions/multimem_st.h
new file mode 100644
index 00000000000..608402f0131
--- /dev/null
+++ b/libcudacxx/include/cuda/__ptx/instructions/multimem_st.h
@@ -0,0 +1,37 @@
+// -*- C++ -*-
+//===----------------------------------------------------------------------===//
+//
+// Part of libcu++, the C++ Standard Library for your entire system,
+// under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+// SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef _CUDA_PTX_MULTIMEM_ST_H_
+#define _CUDA_PTX_MULTIMEM_ST_H_
+
+#include <cuda/std/detail/__config>
+
+#if defined(_CCCL_IMPLICIT_SYSTEM_HEADER_GCC)
+#  pragma GCC system_header
+#elif defined(_CCCL_IMPLICIT_SYSTEM_HEADER_CLANG)
+#  pragma clang system_header
+#elif defined(_CCCL_IMPLICIT_SYSTEM_HEADER_MSVC)
+#  pragma system_header
+#endif // no system header
+
+#include <cuda/__ptx/ptx_dot_variants.h>
+#include <cuda/__ptx/ptx_helper_functions.h>
+#include <cuda/std/cstdint>
+
+#include <nv/target> // __CUDA_MINIMUM_ARCH__ and friends
+
+_LIBCUDACXX_BEGIN_NAMESPACE_CUDA_PTX
+
+#include <cuda/__ptx/instructions/generated/multimem_st.h>
+
+_LIBCUDACXX_END_NAMESPACE_CUDA_PTX
+
+#endif // _CUDA_PTX_MULTIMEM_ST_H_
diff --git a/libcudacxx/include/cuda/ptx b/libcudacxx/include/cuda/ptx
index db9e70ab7e6..d11659ac6fb 100644
--- a/libcudacxx/include/cuda/ptx
+++ b/libcudacxx/include/cuda/ptx
@@ -84,6 +84,9 @@
 #include <cuda/__ptx/instructions/mbarrier_expect_tx.h>
 #include <cuda/__ptx/instructions/mbarrier_init.h>
 #include <cuda/__ptx/instructions/mbarrier_wait.h>
+#include <cuda/__ptx/instructions/multimem_ld_reduce.h>
+#include <cuda/__ptx/instructions/multimem_red.h>
+#include <cuda/__ptx/instructions/multimem_st.h>
 #include <cuda/__ptx/instructions/red_async.h>
 #include <cuda/__ptx/instructions/st_async.h>
 #include <cuda/__ptx/instructions/st_bulk.h>
diff --git a/libcudacxx/test/libcudacxx/cuda/ptx/ptx.multimem.ld_reduce.compile.pass.cpp b/libcudacxx/test/libcudacxx/cuda/ptx/ptx.multimem.ld_reduce.compile.pass.cpp
new file mode 100644
index 00000000000..cbe0ba81971
--- /dev/null
+++ b/libcudacxx/test/libcudacxx/cuda/ptx/ptx.multimem.ld_reduce.compile.pass.cpp
@@ -0,0 +1,22 @@
+//===----------------------------------------------------------------------===//
+//
+// Part of libcu++, the C++ Standard Library for your entire system,
+// under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+// SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES.
+//
+//===----------------------------------------------------------------------===//
+// UNSUPPORTED: libcpp-has-no-threads
+
+// <cuda/ptx>
+
+#include <cuda/ptx>
+#include <cuda/std/utility>
+
+#include "generated/multimem_ld_reduce.h"
+
+int main(int, char**)
+{
+  return 0;
+}
diff --git a/libcudacxx/test/libcudacxx/cuda/ptx/ptx.multimem.red.compile.pass.cpp b/libcudacxx/test/libcudacxx/cuda/ptx/ptx.multimem.red.compile.pass.cpp
new file mode 100644
index 00000000000..b4aefa3b338
--- /dev/null
+++ b/libcudacxx/test/libcudacxx/cuda/ptx/ptx.multimem.red.compile.pass.cpp
@@ -0,0 +1,22 @@
+//===----------------------------------------------------------------------===//
+//
+// Part of libcu++, the C++ Standard Library for your entire system,
+// under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+// SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES.
+//
+//===----------------------------------------------------------------------===//
+// UNSUPPORTED: libcpp-has-no-threads
+
+// <cuda/ptx>
+
+#include <cuda/ptx>
+#include <cuda/std/utility>
+
+#include "generated/multimem_red.h"
+
+int main(int, char**)
+{
+  return 0;
+}
diff --git a/libcudacxx/test/libcudacxx/cuda/ptx/ptx.multimem.st.compile.pass.cpp b/libcudacxx/test/libcudacxx/cuda/ptx/ptx.multimem.st.compile.pass.cpp
new file mode 100644
index 00000000000..4998c854382
--- /dev/null
+++ b/libcudacxx/test/libcudacxx/cuda/ptx/ptx.multimem.st.compile.pass.cpp
@@ -0,0 +1,22 @@
+//===----------------------------------------------------------------------===//
+//
+// Part of libcu++, the C++ Standard Library for your entire system,
+// under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+// SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES.
+//
+//===----------------------------------------------------------------------===//
+// UNSUPPORTED: libcpp-has-no-threads
+
+// <cuda/ptx>
+
+#include <cuda/ptx>
+#include <cuda/std/utility>
+
+#include "generated/multimem_st.h"
+
+int main(int, char**)
+{
+  return 0;
+}

From 0f52dd50c8a049372dfba62950f490813c2217ea Mon Sep 17 00:00:00 2001
From: Bernhard Manfred Gruber <bernhardmgruber@gmail.com>
Date: Thu, 30 Jan 2025 13:38:22 +0100
Subject: [PATCH 23/33] PTX: Add cp.async.mbarrier.arrive{.noinc} (#3602)

Co-authored-by: Allard Hendriksen <ahendriksen@nvidia.com>
---
 docs/libcudacxx/ptx/instructions.rst          |  1 +
 .../instructions/cp_async_mbarrier_arrive.rst | 10 +++++
 .../instructions/cp_async_mbarrier_arrive.h   | 38 +++++++++++++++++++
 libcudacxx/include/cuda/ptx                   |  1 +
 ....cp.async.mbarrier.arrive.compile.pass.cpp | 23 +++++++++++
 5 files changed, 73 insertions(+)
 create mode 100644 docs/libcudacxx/ptx/instructions/cp_async_mbarrier_arrive.rst
 create mode 100644 libcudacxx/include/cuda/__ptx/instructions/cp_async_mbarrier_arrive.h
 create mode 100644 libcudacxx/test/libcudacxx/cuda/ptx/ptx.cp.async.mbarrier.arrive.compile.pass.cpp

diff --git a/docs/libcudacxx/ptx/instructions.rst b/docs/libcudacxx/ptx/instructions.rst
index 797e26d9911..87ccc82b5b1 100644
--- a/docs/libcudacxx/ptx/instructions.rst
+++ b/docs/libcudacxx/ptx/instructions.rst
@@ -12,6 +12,7 @@ PTX Instructions
    instructions/cp_async_bulk_commit_group
    instructions/cp_async_bulk_wait_group
    instructions/cp_async_bulk_tensor
+   instructions/cp_async_mbarrier_arrive
    instructions/cp_reduce_async_bulk
    instructions/cp_reduce_async_bulk_tensor
    instructions/fence
diff --git a/docs/libcudacxx/ptx/instructions/cp_async_mbarrier_arrive.rst b/docs/libcudacxx/ptx/instructions/cp_async_mbarrier_arrive.rst
new file mode 100644
index 00000000000..f2ff2ff5ee7
--- /dev/null
+++ b/docs/libcudacxx/ptx/instructions/cp_async_mbarrier_arrive.rst
@@ -0,0 +1,10 @@
+.. _libcudacxx-ptx-instructions-cp-async-mbarrier-arrive:
+
+cp.async.mbarrier.arrive
+========================
+
+-  PTX ISA:
+   `cp.async.mbarrier.arrive <https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#parallel-synchronization-and-communication-instructions-cp-async-mbarrier-arrive>`__
+
+.. include:: generated/cp_async_mbarrier_arrive.rst
+.. include:: generated/cp_async_mbarrier_arrive_noinc.rst
diff --git a/libcudacxx/include/cuda/__ptx/instructions/cp_async_mbarrier_arrive.h b/libcudacxx/include/cuda/__ptx/instructions/cp_async_mbarrier_arrive.h
new file mode 100644
index 00000000000..c19a09e2922
--- /dev/null
+++ b/libcudacxx/include/cuda/__ptx/instructions/cp_async_mbarrier_arrive.h
@@ -0,0 +1,38 @@
+// -*- C++ -*-
+//===----------------------------------------------------------------------===//
+//
+// Part of libcu++, the C++ Standard Library for your entire system,
+// under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+// SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef _CUDA_PTX_CP_ASYNC_MBARRIER_ARRIVE_H_
+#define _CUDA_PTX_CP_ASYNC_MBARRIER_ARRIVE_H_
+
+#include <cuda/std/detail/__config>
+
+#if defined(_CCCL_IMPLICIT_SYSTEM_HEADER_GCC)
+#  pragma GCC system_header
+#elif defined(_CCCL_IMPLICIT_SYSTEM_HEADER_CLANG)
+#  pragma clang system_header
+#elif defined(_CCCL_IMPLICIT_SYSTEM_HEADER_MSVC)
+#  pragma system_header
+#endif // no system header
+
+#include <cuda/__ptx/ptx_dot_variants.h>
+#include <cuda/__ptx/ptx_helper_functions.h>
+#include <cuda/std/cstdint>
+
+#include <nv/target> // __CUDA_MINIMUM_ARCH__ and friends
+
+_LIBCUDACXX_BEGIN_NAMESPACE_CUDA_PTX
+
+#include <cuda/__ptx/instructions/generated/cp_async_mbarrier_arrive.h>
+#include <cuda/__ptx/instructions/generated/cp_async_mbarrier_arrive_noinc.h>
+
+_LIBCUDACXX_END_NAMESPACE_CUDA_PTX
+
+#endif // _CUDA_PTX_CP_ASYNC_MBARRIER_ARRIVE_H_
diff --git a/libcudacxx/include/cuda/ptx b/libcudacxx/include/cuda/ptx
index d11659ac6fb..0d699b2e2ca 100644
--- a/libcudacxx/include/cuda/ptx
+++ b/libcudacxx/include/cuda/ptx
@@ -75,6 +75,7 @@
 #include <cuda/__ptx/instructions/cp_async_bulk_commit_group.h>
 #include <cuda/__ptx/instructions/cp_async_bulk_tensor.h>
 #include <cuda/__ptx/instructions/cp_async_bulk_wait_group.h>
+#include <cuda/__ptx/instructions/cp_async_mbarrier_arrive.h>
 #include <cuda/__ptx/instructions/cp_reduce_async_bulk.h>
 #include <cuda/__ptx/instructions/cp_reduce_async_bulk_tensor.h>
 #include <cuda/__ptx/instructions/fence.h>
diff --git a/libcudacxx/test/libcudacxx/cuda/ptx/ptx.cp.async.mbarrier.arrive.compile.pass.cpp b/libcudacxx/test/libcudacxx/cuda/ptx/ptx.cp.async.mbarrier.arrive.compile.pass.cpp
new file mode 100644
index 00000000000..97623078198
--- /dev/null
+++ b/libcudacxx/test/libcudacxx/cuda/ptx/ptx.cp.async.mbarrier.arrive.compile.pass.cpp
@@ -0,0 +1,23 @@
+//===----------------------------------------------------------------------===//
+//
+// Part of libcu++, the C++ Standard Library for your entire system,
+// under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+// SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES.
+//
+//===----------------------------------------------------------------------===//
+// UNSUPPORTED: libcpp-has-no-threads
+
+// <cuda/ptx>
+
+#include <cuda/ptx>
+#include <cuda/std/utility>
+
+#include "generated/cp_async_mbarrier_arrive.h"
+#include "generated/cp_async_mbarrier_arrive_noinc.h"
+
+int main(int, char**)
+{
+  return 0;
+}

From 38983ebc42de5683e212562c931aa0789c6eefe7 Mon Sep 17 00:00:00 2001
From: Bernhard Manfred Gruber <bernhardmgruber@gmail.com>
Date: Thu, 30 Jan 2025 16:40:27 +0100
Subject: [PATCH 24/33] PTX: Add tcgen05 instructions (#3607)

* ptx: Add tcgen05.alloc

* ptx: Add tcgen05.commit

* ptx: Add tcgen05.cp

* ptx: Add tcgen05.fence

* ptx: Add tcgen05.ld

* ptx: Add tcgen05.mma

* ptx: Add tcgen05.mma.ws

* ptx: Add tcgen05.shift

* ptx: Add tcgen05.st

* ptx: Add tcgen05.wait

* fix docs

---------

Co-authored-by: Allard Hendriksen <ahendriksen@nvidia.com>
---
 docs/libcudacxx/ptx/instructions.rst          | 10 +++++
 .../ptx/instructions/tcgen05_alloc.rst        |  9 +++++
 .../ptx/instructions/tcgen05_commit.rst       |  9 +++++
 .../ptx/instructions/tcgen05_cp.rst           |  9 +++++
 .../ptx/instructions/tcgen05_fence.rst        |  9 +++++
 .../ptx/instructions/tcgen05_ld.rst           |  9 +++++
 .../ptx/instructions/tcgen05_mma.rst          |  9 +++++
 .../ptx/instructions/tcgen05_mma_ws.rst       |  9 +++++
 .../ptx/instructions/tcgen05_shift.rst        |  9 +++++
 .../ptx/instructions/tcgen05_st.rst           |  9 +++++
 .../ptx/instructions/tcgen05_wait.rst         |  9 +++++
 .../cuda/__ptx/instructions/tcgen05_alloc.h   | 37 +++++++++++++++++++
 .../cuda/__ptx/instructions/tcgen05_commit.h  | 37 +++++++++++++++++++
 .../cuda/__ptx/instructions/tcgen05_cp.h      | 37 +++++++++++++++++++
 .../cuda/__ptx/instructions/tcgen05_fence.h   | 37 +++++++++++++++++++
 .../cuda/__ptx/instructions/tcgen05_ld.h      | 37 +++++++++++++++++++
 .../cuda/__ptx/instructions/tcgen05_mma.h     | 37 +++++++++++++++++++
 .../cuda/__ptx/instructions/tcgen05_mma_ws.h  | 37 +++++++++++++++++++
 .../cuda/__ptx/instructions/tcgen05_shift.h   | 37 +++++++++++++++++++
 .../cuda/__ptx/instructions/tcgen05_st.h      | 37 +++++++++++++++++++
 .../cuda/__ptx/instructions/tcgen05_wait.h    | 37 +++++++++++++++++++
 libcudacxx/include/cuda/ptx                   | 10 +++++
 .../ptx/ptx.tcgen05.alloc.compile.pass.cpp    | 22 +++++++++++
 .../ptx/ptx.tcgen05.commit.compile.pass.cpp   | 22 +++++++++++
 .../cuda/ptx/ptx.tcgen05.cp.compile.pass.cpp  | 22 +++++++++++
 .../ptx/ptx.tcgen05.fence.compile.pass.cpp    | 22 +++++++++++
 .../cuda/ptx/ptx.tcgen05.ld.compile.pass.cpp  | 22 +++++++++++
 .../cuda/ptx/ptx.tcgen05.mma.compile.pass.cpp | 22 +++++++++++
 .../ptx/ptx.tcgen05.mma.ws.compile.pass.cpp   | 22 +++++++++++
 .../ptx/ptx.tcgen05.shift.compile.pass.cpp    | 22 +++++++++++
 .../cuda/ptx/ptx.tcgen05.st.compile.pass.cpp  | 22 +++++++++++
 .../ptx/ptx.tcgen05.wait.compile.pass.cpp     | 22 +++++++++++
 32 files changed, 700 insertions(+)
 create mode 100644 docs/libcudacxx/ptx/instructions/tcgen05_alloc.rst
 create mode 100644 docs/libcudacxx/ptx/instructions/tcgen05_commit.rst
 create mode 100644 docs/libcudacxx/ptx/instructions/tcgen05_cp.rst
 create mode 100644 docs/libcudacxx/ptx/instructions/tcgen05_fence.rst
 create mode 100644 docs/libcudacxx/ptx/instructions/tcgen05_ld.rst
 create mode 100644 docs/libcudacxx/ptx/instructions/tcgen05_mma.rst
 create mode 100644 docs/libcudacxx/ptx/instructions/tcgen05_mma_ws.rst
 create mode 100644 docs/libcudacxx/ptx/instructions/tcgen05_shift.rst
 create mode 100644 docs/libcudacxx/ptx/instructions/tcgen05_st.rst
 create mode 100644 docs/libcudacxx/ptx/instructions/tcgen05_wait.rst
 create mode 100644 libcudacxx/include/cuda/__ptx/instructions/tcgen05_alloc.h
 create mode 100644 libcudacxx/include/cuda/__ptx/instructions/tcgen05_commit.h
 create mode 100644 libcudacxx/include/cuda/__ptx/instructions/tcgen05_cp.h
 create mode 100644 libcudacxx/include/cuda/__ptx/instructions/tcgen05_fence.h
 create mode 100644 libcudacxx/include/cuda/__ptx/instructions/tcgen05_ld.h
 create mode 100644 libcudacxx/include/cuda/__ptx/instructions/tcgen05_mma.h
 create mode 100644 libcudacxx/include/cuda/__ptx/instructions/tcgen05_mma_ws.h
 create mode 100644 libcudacxx/include/cuda/__ptx/instructions/tcgen05_shift.h
 create mode 100644 libcudacxx/include/cuda/__ptx/instructions/tcgen05_st.h
 create mode 100644 libcudacxx/include/cuda/__ptx/instructions/tcgen05_wait.h
 create mode 100644 libcudacxx/test/libcudacxx/cuda/ptx/ptx.tcgen05.alloc.compile.pass.cpp
 create mode 100644 libcudacxx/test/libcudacxx/cuda/ptx/ptx.tcgen05.commit.compile.pass.cpp
 create mode 100644 libcudacxx/test/libcudacxx/cuda/ptx/ptx.tcgen05.cp.compile.pass.cpp
 create mode 100644 libcudacxx/test/libcudacxx/cuda/ptx/ptx.tcgen05.fence.compile.pass.cpp
 create mode 100644 libcudacxx/test/libcudacxx/cuda/ptx/ptx.tcgen05.ld.compile.pass.cpp
 create mode 100644 libcudacxx/test/libcudacxx/cuda/ptx/ptx.tcgen05.mma.compile.pass.cpp
 create mode 100644 libcudacxx/test/libcudacxx/cuda/ptx/ptx.tcgen05.mma.ws.compile.pass.cpp
 create mode 100644 libcudacxx/test/libcudacxx/cuda/ptx/ptx.tcgen05.shift.compile.pass.cpp
 create mode 100644 libcudacxx/test/libcudacxx/cuda/ptx/ptx.tcgen05.st.compile.pass.cpp
 create mode 100644 libcudacxx/test/libcudacxx/cuda/ptx/ptx.tcgen05.wait.compile.pass.cpp

diff --git a/docs/libcudacxx/ptx/instructions.rst b/docs/libcudacxx/ptx/instructions.rst
index 87ccc82b5b1..136dfb81fc3 100644
--- a/docs/libcudacxx/ptx/instructions.rst
+++ b/docs/libcudacxx/ptx/instructions.rst
@@ -29,6 +29,16 @@ PTX Instructions
    instructions/red_async
    instructions/st_async
    instructions/st_bulk
+   instructions/tcgen05_alloc
+   instructions/tcgen05_commit
+   instructions/tcgen05_cp
+   instructions/tcgen05_fence
+   instructions/tcgen05_ld
+   instructions/tcgen05_mma
+   instructions/tcgen05_mma_ws
+   instructions/tcgen05_shift
+   instructions/tcgen05_st
+   instructions/tcgen05_wait
    instructions/tensormap_replace
    instructions/tensormap_cp_fenceproxy
    instructions/special_registers
diff --git a/docs/libcudacxx/ptx/instructions/tcgen05_alloc.rst b/docs/libcudacxx/ptx/instructions/tcgen05_alloc.rst
new file mode 100644
index 00000000000..a30f2a2560c
--- /dev/null
+++ b/docs/libcudacxx/ptx/instructions/tcgen05_alloc.rst
@@ -0,0 +1,9 @@
+.. _libcudacxx-ptx-instructions-tcgen05-alloc:
+
+tcgen05.alloc
+=============
+
+-  PTX ISA:
+   `tcgen05.alloc <https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#tensorcore-5th-generation-instructions-tcgen05-alloc-tcgen05-dealloc-tcgen05-relinquish-alloc-permit>`__
+
+.. include:: generated/tcgen05_alloc.rst
diff --git a/docs/libcudacxx/ptx/instructions/tcgen05_commit.rst b/docs/libcudacxx/ptx/instructions/tcgen05_commit.rst
new file mode 100644
index 00000000000..a431350dea8
--- /dev/null
+++ b/docs/libcudacxx/ptx/instructions/tcgen05_commit.rst
@@ -0,0 +1,9 @@
+.. _libcudacxx-ptx-instructions-tcgen05-commit:
+
+tcgen05.commit
+==============
+
+-  PTX ISA:
+   `tcgen05.commit <https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#tensorcore-5th-generation-instructions-tcgen05-commit>`__
+
+.. include:: generated/tcgen05_commit.rst
diff --git a/docs/libcudacxx/ptx/instructions/tcgen05_cp.rst b/docs/libcudacxx/ptx/instructions/tcgen05_cp.rst
new file mode 100644
index 00000000000..5a220536d6e
--- /dev/null
+++ b/docs/libcudacxx/ptx/instructions/tcgen05_cp.rst
@@ -0,0 +1,9 @@
+.. _libcudacxx-ptx-instructions-tcgen05-cp:
+
+tcgen05.cp
+==========
+
+-  PTX ISA:
+   `tcgen05.cp <https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#tensorcore-5th-generation-instructions-tcgen05-cp>`__
+
+.. include:: generated/tcgen05_cp.rst
diff --git a/docs/libcudacxx/ptx/instructions/tcgen05_fence.rst b/docs/libcudacxx/ptx/instructions/tcgen05_fence.rst
new file mode 100644
index 00000000000..6635131f707
--- /dev/null
+++ b/docs/libcudacxx/ptx/instructions/tcgen05_fence.rst
@@ -0,0 +1,9 @@
+.. _libcudacxx-ptx-instructions-tcgen05-fence:
+
+tcgen05.fence
+=============
+
+-  PTX ISA:
+   `tcgen05.fence <https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#tensorcore-5th-generation-instructions-tcgen05-fence>`__
+
+.. include:: generated/tcgen05_fence.rst
diff --git a/docs/libcudacxx/ptx/instructions/tcgen05_ld.rst b/docs/libcudacxx/ptx/instructions/tcgen05_ld.rst
new file mode 100644
index 00000000000..165b8eb935a
--- /dev/null
+++ b/docs/libcudacxx/ptx/instructions/tcgen05_ld.rst
@@ -0,0 +1,9 @@
+.. _libcudacxx-ptx-instructions-tcgen05-ld:
+
+tcgen05.ld
+==========
+
+-  PTX ISA:
+   `tcgen05.ld <https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#tensorcore-5th-generation-instructions-tcgen05-ld>`__
+
+.. include:: generated/tcgen05_ld.rst
diff --git a/docs/libcudacxx/ptx/instructions/tcgen05_mma.rst b/docs/libcudacxx/ptx/instructions/tcgen05_mma.rst
new file mode 100644
index 00000000000..9672ae0d0a1
--- /dev/null
+++ b/docs/libcudacxx/ptx/instructions/tcgen05_mma.rst
@@ -0,0 +1,9 @@
+.. _libcudacxx-ptx-instructions-tcgen05-mma:
+
+tcgen05.mma
+===========
+
+-  PTX ISA:
+   `tcgen05.mma <https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#tensorcore-5th-generation-instructions-tcgen05-mma>`__
+
+.. include:: generated/tcgen05_mma.rst
diff --git a/docs/libcudacxx/ptx/instructions/tcgen05_mma_ws.rst b/docs/libcudacxx/ptx/instructions/tcgen05_mma_ws.rst
new file mode 100644
index 00000000000..e22066298ac
--- /dev/null
+++ b/docs/libcudacxx/ptx/instructions/tcgen05_mma_ws.rst
@@ -0,0 +1,9 @@
+.. _libcudacxx-ptx-instructions-tcgen05-mma-ws:
+
+tcgen05.mma.ws
+==============
+
+-  PTX ISA:
+   `tcgen05.mma.ws <https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#tensorcore-5th-generation-instructions-tcgen05-mma-ws>`__
+
+.. include:: generated/tcgen05_mma_ws.rst
diff --git a/docs/libcudacxx/ptx/instructions/tcgen05_shift.rst b/docs/libcudacxx/ptx/instructions/tcgen05_shift.rst
new file mode 100644
index 00000000000..eef04ae4d5e
--- /dev/null
+++ b/docs/libcudacxx/ptx/instructions/tcgen05_shift.rst
@@ -0,0 +1,9 @@
+.. _libcudacxx-ptx-instructions-tcgen05-shift:
+
+tcgen05.shift
+=============
+
+-  PTX ISA:
+   `tcgen05.shift <https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#tensorcore-5th-generation-instructions-tcgen05-shift>`__
+
+.. include:: generated/tcgen05_shift.rst
diff --git a/docs/libcudacxx/ptx/instructions/tcgen05_st.rst b/docs/libcudacxx/ptx/instructions/tcgen05_st.rst
new file mode 100644
index 00000000000..f101149481f
--- /dev/null
+++ b/docs/libcudacxx/ptx/instructions/tcgen05_st.rst
@@ -0,0 +1,9 @@
+.. _libcudacxx-ptx-instructions-tcgen05-st:
+
+tcgen05.st
+==========
+
+-  PTX ISA:
+   `tcgen05.st <https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#tensorcore-5th-generation-instructions-tcgen05-st>`__
+
+.. include:: generated/tcgen05_st.rst
diff --git a/docs/libcudacxx/ptx/instructions/tcgen05_wait.rst b/docs/libcudacxx/ptx/instructions/tcgen05_wait.rst
new file mode 100644
index 00000000000..cb149e5c9a1
--- /dev/null
+++ b/docs/libcudacxx/ptx/instructions/tcgen05_wait.rst
@@ -0,0 +1,9 @@
+.. _libcudacxx-ptx-instructions-tcgen05-wait:
+
+tcgen05.wait
+============
+
+-  PTX ISA:
+   `tcgen05.wait <https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#tensorcore-5th-generation-instructions-tcgen05-wait>`__
+
+.. include:: generated/tcgen05_wait.rst
diff --git a/libcudacxx/include/cuda/__ptx/instructions/tcgen05_alloc.h b/libcudacxx/include/cuda/__ptx/instructions/tcgen05_alloc.h
new file mode 100644
index 00000000000..743ee4306ee
--- /dev/null
+++ b/libcudacxx/include/cuda/__ptx/instructions/tcgen05_alloc.h
@@ -0,0 +1,37 @@
+// -*- C++ -*-
+//===----------------------------------------------------------------------===//
+//
+// Part of libcu++, the C++ Standard Library for your entire system,
+// under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+// SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef _CUDA_PTX_TCGEN05_ALLOC_H_
+#define _CUDA_PTX_TCGEN05_ALLOC_H_
+
+#include <cuda/std/detail/__config>
+
+#if defined(_CCCL_IMPLICIT_SYSTEM_HEADER_GCC)
+#  pragma GCC system_header
+#elif defined(_CCCL_IMPLICIT_SYSTEM_HEADER_CLANG)
+#  pragma clang system_header
+#elif defined(_CCCL_IMPLICIT_SYSTEM_HEADER_MSVC)
+#  pragma system_header
+#endif // no system header
+
+#include <cuda/__ptx/ptx_dot_variants.h>
+#include <cuda/__ptx/ptx_helper_functions.h>
+#include <cuda/std/cstdint>
+
+#include <nv/target> // __CUDA_MINIMUM_ARCH__ and friends
+
+_LIBCUDACXX_BEGIN_NAMESPACE_CUDA_PTX
+
+#include <cuda/__ptx/instructions/generated/tcgen05_alloc.h>
+
+_LIBCUDACXX_END_NAMESPACE_CUDA_PTX
+
+#endif // _CUDA_PTX_TCGEN05_ALLOC_H_
diff --git a/libcudacxx/include/cuda/__ptx/instructions/tcgen05_commit.h b/libcudacxx/include/cuda/__ptx/instructions/tcgen05_commit.h
new file mode 100644
index 00000000000..ca06ec6b97d
--- /dev/null
+++ b/libcudacxx/include/cuda/__ptx/instructions/tcgen05_commit.h
@@ -0,0 +1,37 @@
+// -*- C++ -*-
+//===----------------------------------------------------------------------===//
+//
+// Part of libcu++, the C++ Standard Library for your entire system,
+// under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+// SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef _CUDA_PTX_TCGEN05_COMMIT_H_
+#define _CUDA_PTX_TCGEN05_COMMIT_H_
+
+#include <cuda/std/detail/__config>
+
+#if defined(_CCCL_IMPLICIT_SYSTEM_HEADER_GCC)
+#  pragma GCC system_header
+#elif defined(_CCCL_IMPLICIT_SYSTEM_HEADER_CLANG)
+#  pragma clang system_header
+#elif defined(_CCCL_IMPLICIT_SYSTEM_HEADER_MSVC)
+#  pragma system_header
+#endif // no system header
+
+#include <cuda/__ptx/ptx_dot_variants.h>
+#include <cuda/__ptx/ptx_helper_functions.h>
+#include <cuda/std/cstdint>
+
+#include <nv/target> // __CUDA_MINIMUM_ARCH__ and friends
+
+_LIBCUDACXX_BEGIN_NAMESPACE_CUDA_PTX
+
+#include <cuda/__ptx/instructions/generated/tcgen05_commit.h>
+
+_LIBCUDACXX_END_NAMESPACE_CUDA_PTX
+
+#endif // _CUDA_PTX_TCGEN05_COMMIT_H_
diff --git a/libcudacxx/include/cuda/__ptx/instructions/tcgen05_cp.h b/libcudacxx/include/cuda/__ptx/instructions/tcgen05_cp.h
new file mode 100644
index 00000000000..e0c6ebf74ad
--- /dev/null
+++ b/libcudacxx/include/cuda/__ptx/instructions/tcgen05_cp.h
@@ -0,0 +1,37 @@
+// -*- C++ -*-
+//===----------------------------------------------------------------------===//
+//
+// Part of libcu++, the C++ Standard Library for your entire system,
+// under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+// SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef _CUDA_PTX_TCGEN05_CP_H_
+#define _CUDA_PTX_TCGEN05_CP_H_
+
+#include <cuda/std/detail/__config>
+
+#if defined(_CCCL_IMPLICIT_SYSTEM_HEADER_GCC)
+#  pragma GCC system_header
+#elif defined(_CCCL_IMPLICIT_SYSTEM_HEADER_CLANG)
+#  pragma clang system_header
+#elif defined(_CCCL_IMPLICIT_SYSTEM_HEADER_MSVC)
+#  pragma system_header
+#endif // no system header
+
+#include <cuda/__ptx/ptx_dot_variants.h>
+#include <cuda/__ptx/ptx_helper_functions.h>
+#include <cuda/std/cstdint>
+
+#include <nv/target> // __CUDA_MINIMUM_ARCH__ and friends
+
+_LIBCUDACXX_BEGIN_NAMESPACE_CUDA_PTX
+
+#include <cuda/__ptx/instructions/generated/tcgen05_cp.h>
+
+_LIBCUDACXX_END_NAMESPACE_CUDA_PTX
+
+#endif // _CUDA_PTX_TCGEN05_CP_H_
diff --git a/libcudacxx/include/cuda/__ptx/instructions/tcgen05_fence.h b/libcudacxx/include/cuda/__ptx/instructions/tcgen05_fence.h
new file mode 100644
index 00000000000..a36847cd0f3
--- /dev/null
+++ b/libcudacxx/include/cuda/__ptx/instructions/tcgen05_fence.h
@@ -0,0 +1,37 @@
+// -*- C++ -*-
+//===----------------------------------------------------------------------===//
+//
+// Part of libcu++, the C++ Standard Library for your entire system,
+// under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+// SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef _CUDA_PTX_TCGEN05_FENCE_H_
+#define _CUDA_PTX_TCGEN05_FENCE_H_
+
+#include <cuda/std/detail/__config>
+
+#if defined(_CCCL_IMPLICIT_SYSTEM_HEADER_GCC)
+#  pragma GCC system_header
+#elif defined(_CCCL_IMPLICIT_SYSTEM_HEADER_CLANG)
+#  pragma clang system_header
+#elif defined(_CCCL_IMPLICIT_SYSTEM_HEADER_MSVC)
+#  pragma system_header
+#endif // no system header
+
+#include <cuda/__ptx/ptx_dot_variants.h>
+#include <cuda/__ptx/ptx_helper_functions.h>
+#include <cuda/std/cstdint>
+
+#include <nv/target> // __CUDA_MINIMUM_ARCH__ and friends
+
+_LIBCUDACXX_BEGIN_NAMESPACE_CUDA_PTX
+
+#include <cuda/__ptx/instructions/generated/tcgen05_fence.h>
+
+_LIBCUDACXX_END_NAMESPACE_CUDA_PTX
+
+#endif // _CUDA_PTX_TCGEN05_FENCE_H_
diff --git a/libcudacxx/include/cuda/__ptx/instructions/tcgen05_ld.h b/libcudacxx/include/cuda/__ptx/instructions/tcgen05_ld.h
new file mode 100644
index 00000000000..782ba20e804
--- /dev/null
+++ b/libcudacxx/include/cuda/__ptx/instructions/tcgen05_ld.h
@@ -0,0 +1,37 @@
+// -*- C++ -*-
+//===----------------------------------------------------------------------===//
+//
+// Part of libcu++, the C++ Standard Library for your entire system,
+// under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+// SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef _CUDA_PTX_TCGEN05_LD_H_
+#define _CUDA_PTX_TCGEN05_LD_H_
+
+#include <cuda/std/detail/__config>
+
+#if defined(_CCCL_IMPLICIT_SYSTEM_HEADER_GCC)
+#  pragma GCC system_header
+#elif defined(_CCCL_IMPLICIT_SYSTEM_HEADER_CLANG)
+#  pragma clang system_header
+#elif defined(_CCCL_IMPLICIT_SYSTEM_HEADER_MSVC)
+#  pragma system_header
+#endif // no system header
+
+#include <cuda/__ptx/ptx_dot_variants.h>
+#include <cuda/__ptx/ptx_helper_functions.h>
+#include <cuda/std/cstdint>
+
+#include <nv/target> // __CUDA_MINIMUM_ARCH__ and friends
+
+_LIBCUDACXX_BEGIN_NAMESPACE_CUDA_PTX
+
+#include <cuda/__ptx/instructions/generated/tcgen05_ld.h>
+
+_LIBCUDACXX_END_NAMESPACE_CUDA_PTX
+
+#endif // _CUDA_PTX_TCGEN05_LD_H_
diff --git a/libcudacxx/include/cuda/__ptx/instructions/tcgen05_mma.h b/libcudacxx/include/cuda/__ptx/instructions/tcgen05_mma.h
new file mode 100644
index 00000000000..ff9d159930b
--- /dev/null
+++ b/libcudacxx/include/cuda/__ptx/instructions/tcgen05_mma.h
@@ -0,0 +1,37 @@
+// -*- C++ -*-
+//===----------------------------------------------------------------------===//
+//
+// Part of libcu++, the C++ Standard Library for your entire system,
+// under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+// SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef _CUDA_PTX_TCGEN05_MMA_H_
+#define _CUDA_PTX_TCGEN05_MMA_H_
+
+#include <cuda/std/detail/__config>
+
+#if defined(_CCCL_IMPLICIT_SYSTEM_HEADER_GCC)
+#  pragma GCC system_header
+#elif defined(_CCCL_IMPLICIT_SYSTEM_HEADER_CLANG)
+#  pragma clang system_header
+#elif defined(_CCCL_IMPLICIT_SYSTEM_HEADER_MSVC)
+#  pragma system_header
+#endif // no system header
+
+#include <cuda/__ptx/ptx_dot_variants.h>
+#include <cuda/__ptx/ptx_helper_functions.h>
+#include <cuda/std/cstdint>
+
+#include <nv/target> // __CUDA_MINIMUM_ARCH__ and friends
+
+_LIBCUDACXX_BEGIN_NAMESPACE_CUDA_PTX
+
+#include <cuda/__ptx/instructions/generated/tcgen05_mma.h>
+
+_LIBCUDACXX_END_NAMESPACE_CUDA_PTX
+
+#endif // _CUDA_PTX_TCGEN05_MMA_H_
diff --git a/libcudacxx/include/cuda/__ptx/instructions/tcgen05_mma_ws.h b/libcudacxx/include/cuda/__ptx/instructions/tcgen05_mma_ws.h
new file mode 100644
index 00000000000..5d0bd5b8b5a
--- /dev/null
+++ b/libcudacxx/include/cuda/__ptx/instructions/tcgen05_mma_ws.h
@@ -0,0 +1,37 @@
+// -*- C++ -*-
+//===----------------------------------------------------------------------===//
+//
+// Part of libcu++, the C++ Standard Library for your entire system,
+// under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+// SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef _CUDA_PTX_TCGEN05_MMA_WS_H_
+#define _CUDA_PTX_TCGEN05_MMA_WS_H_
+
+#include <cuda/std/detail/__config>
+
+#if defined(_CCCL_IMPLICIT_SYSTEM_HEADER_GCC)
+#  pragma GCC system_header
+#elif defined(_CCCL_IMPLICIT_SYSTEM_HEADER_CLANG)
+#  pragma clang system_header
+#elif defined(_CCCL_IMPLICIT_SYSTEM_HEADER_MSVC)
+#  pragma system_header
+#endif // no system header
+
+#include <cuda/__ptx/ptx_dot_variants.h>
+#include <cuda/__ptx/ptx_helper_functions.h>
+#include <cuda/std/cstdint>
+
+#include <nv/target> // __CUDA_MINIMUM_ARCH__ and friends
+
+_LIBCUDACXX_BEGIN_NAMESPACE_CUDA_PTX
+
+#include <cuda/__ptx/instructions/generated/tcgen05_mma_ws.h>
+
+_LIBCUDACXX_END_NAMESPACE_CUDA_PTX
+
+#endif // _CUDA_PTX_TCGEN05_MMA_WS_H_
diff --git a/libcudacxx/include/cuda/__ptx/instructions/tcgen05_shift.h b/libcudacxx/include/cuda/__ptx/instructions/tcgen05_shift.h
new file mode 100644
index 00000000000..aab5cbe27b8
--- /dev/null
+++ b/libcudacxx/include/cuda/__ptx/instructions/tcgen05_shift.h
@@ -0,0 +1,37 @@
+// -*- C++ -*-
+//===----------------------------------------------------------------------===//
+//
+// Part of libcu++, the C++ Standard Library for your entire system,
+// under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+// SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef _CUDA_PTX_TCGEN05_SHIFT_H_
+#define _CUDA_PTX_TCGEN05_SHIFT_H_
+
+#include <cuda/std/detail/__config>
+
+#if defined(_CCCL_IMPLICIT_SYSTEM_HEADER_GCC)
+#  pragma GCC system_header
+#elif defined(_CCCL_IMPLICIT_SYSTEM_HEADER_CLANG)
+#  pragma clang system_header
+#elif defined(_CCCL_IMPLICIT_SYSTEM_HEADER_MSVC)
+#  pragma system_header
+#endif // no system header
+
+#include <cuda/__ptx/ptx_dot_variants.h>
+#include <cuda/__ptx/ptx_helper_functions.h>
+#include <cuda/std/cstdint>
+
+#include <nv/target> // __CUDA_MINIMUM_ARCH__ and friends
+
+_LIBCUDACXX_BEGIN_NAMESPACE_CUDA_PTX
+
+#include <cuda/__ptx/instructions/generated/tcgen05_shift.h>
+
+_LIBCUDACXX_END_NAMESPACE_CUDA_PTX
+
+#endif // _CUDA_PTX_TCGEN05_SHIFT_H_
diff --git a/libcudacxx/include/cuda/__ptx/instructions/tcgen05_st.h b/libcudacxx/include/cuda/__ptx/instructions/tcgen05_st.h
new file mode 100644
index 00000000000..94c86614b1e
--- /dev/null
+++ b/libcudacxx/include/cuda/__ptx/instructions/tcgen05_st.h
@@ -0,0 +1,37 @@
+// -*- C++ -*-
+//===----------------------------------------------------------------------===//
+//
+// Part of libcu++, the C++ Standard Library for your entire system,
+// under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+// SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef _CUDA_PTX_TCGEN05_ST_H_
+#define _CUDA_PTX_TCGEN05_ST_H_
+
+#include <cuda/std/detail/__config>
+
+#if defined(_CCCL_IMPLICIT_SYSTEM_HEADER_GCC)
+#  pragma GCC system_header
+#elif defined(_CCCL_IMPLICIT_SYSTEM_HEADER_CLANG)
+#  pragma clang system_header
+#elif defined(_CCCL_IMPLICIT_SYSTEM_HEADER_MSVC)
+#  pragma system_header
+#endif // no system header
+
+#include <cuda/__ptx/ptx_dot_variants.h>
+#include <cuda/__ptx/ptx_helper_functions.h>
+#include <cuda/std/cstdint>
+
+#include <nv/target> // __CUDA_MINIMUM_ARCH__ and friends
+
+_LIBCUDACXX_BEGIN_NAMESPACE_CUDA_PTX
+
+#include <cuda/__ptx/instructions/generated/tcgen05_st.h>
+
+_LIBCUDACXX_END_NAMESPACE_CUDA_PTX
+
+#endif // _CUDA_PTX_TCGEN05_ST_H_
diff --git a/libcudacxx/include/cuda/__ptx/instructions/tcgen05_wait.h b/libcudacxx/include/cuda/__ptx/instructions/tcgen05_wait.h
new file mode 100644
index 00000000000..1684d9afd65
--- /dev/null
+++ b/libcudacxx/include/cuda/__ptx/instructions/tcgen05_wait.h
@@ -0,0 +1,37 @@
+// -*- C++ -*-
+//===----------------------------------------------------------------------===//
+//
+// Part of libcu++, the C++ Standard Library for your entire system,
+// under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+// SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef _CUDA_PTX_TCGEN05_WAIT_H_
+#define _CUDA_PTX_TCGEN05_WAIT_H_
+
+#include <cuda/std/detail/__config>
+
+#if defined(_CCCL_IMPLICIT_SYSTEM_HEADER_GCC)
+#  pragma GCC system_header
+#elif defined(_CCCL_IMPLICIT_SYSTEM_HEADER_CLANG)
+#  pragma clang system_header
+#elif defined(_CCCL_IMPLICIT_SYSTEM_HEADER_MSVC)
+#  pragma system_header
+#endif // no system header
+
+#include <cuda/__ptx/ptx_dot_variants.h>
+#include <cuda/__ptx/ptx_helper_functions.h>
+#include <cuda/std/cstdint>
+
+#include <nv/target> // __CUDA_MINIMUM_ARCH__ and friends
+
+_LIBCUDACXX_BEGIN_NAMESPACE_CUDA_PTX
+
+#include <cuda/__ptx/instructions/generated/tcgen05_wait.h>
+
+_LIBCUDACXX_END_NAMESPACE_CUDA_PTX
+
+#endif // _CUDA_PTX_TCGEN05_WAIT_H_
diff --git a/libcudacxx/include/cuda/ptx b/libcudacxx/include/cuda/ptx
index 0d699b2e2ca..971288b456c 100644
--- a/libcudacxx/include/cuda/ptx
+++ b/libcudacxx/include/cuda/ptx
@@ -91,6 +91,16 @@
 #include <cuda/__ptx/instructions/red_async.h>
 #include <cuda/__ptx/instructions/st_async.h>
 #include <cuda/__ptx/instructions/st_bulk.h>
+#include <cuda/__ptx/instructions/tcgen05_alloc.h>
+#include <cuda/__ptx/instructions/tcgen05_commit.h>
+#include <cuda/__ptx/instructions/tcgen05_cp.h>
+#include <cuda/__ptx/instructions/tcgen05_fence.h>
+#include <cuda/__ptx/instructions/tcgen05_ld.h>
+#include <cuda/__ptx/instructions/tcgen05_mma.h>
+#include <cuda/__ptx/instructions/tcgen05_mma_ws.h>
+#include <cuda/__ptx/instructions/tcgen05_shift.h>
+#include <cuda/__ptx/instructions/tcgen05_st.h>
+#include <cuda/__ptx/instructions/tcgen05_wait.h>
 #include <cuda/__ptx/instructions/tensormap_cp_fenceproxy.h>
 #include <cuda/__ptx/instructions/tensormap_replace.h>
 
diff --git a/libcudacxx/test/libcudacxx/cuda/ptx/ptx.tcgen05.alloc.compile.pass.cpp b/libcudacxx/test/libcudacxx/cuda/ptx/ptx.tcgen05.alloc.compile.pass.cpp
new file mode 100644
index 00000000000..49f9df928e9
--- /dev/null
+++ b/libcudacxx/test/libcudacxx/cuda/ptx/ptx.tcgen05.alloc.compile.pass.cpp
@@ -0,0 +1,22 @@
+//===----------------------------------------------------------------------===//
+//
+// Part of libcu++, the C++ Standard Library for your entire system,
+// under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+// SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES.
+//
+//===----------------------------------------------------------------------===//
+// UNSUPPORTED: libcpp-has-no-threads
+
+// <cuda/ptx>
+
+#include <cuda/ptx>
+#include <cuda/std/utility>
+
+#include "generated/tcgen05_alloc.h"
+
+int main(int, char**)
+{
+  return 0;
+}
diff --git a/libcudacxx/test/libcudacxx/cuda/ptx/ptx.tcgen05.commit.compile.pass.cpp b/libcudacxx/test/libcudacxx/cuda/ptx/ptx.tcgen05.commit.compile.pass.cpp
new file mode 100644
index 00000000000..73ea1851bec
--- /dev/null
+++ b/libcudacxx/test/libcudacxx/cuda/ptx/ptx.tcgen05.commit.compile.pass.cpp
@@ -0,0 +1,22 @@
+//===----------------------------------------------------------------------===//
+//
+// Part of libcu++, the C++ Standard Library for your entire system,
+// under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+// SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES.
+//
+//===----------------------------------------------------------------------===//
+// UNSUPPORTED: libcpp-has-no-threads
+
+// <cuda/ptx>
+
+#include <cuda/ptx>
+#include <cuda/std/utility>
+
+#include "generated/tcgen05_commit.h"
+
+int main(int, char**)
+{
+  return 0;
+}
diff --git a/libcudacxx/test/libcudacxx/cuda/ptx/ptx.tcgen05.cp.compile.pass.cpp b/libcudacxx/test/libcudacxx/cuda/ptx/ptx.tcgen05.cp.compile.pass.cpp
new file mode 100644
index 00000000000..85ddc17efe4
--- /dev/null
+++ b/libcudacxx/test/libcudacxx/cuda/ptx/ptx.tcgen05.cp.compile.pass.cpp
@@ -0,0 +1,22 @@
+//===----------------------------------------------------------------------===//
+//
+// Part of libcu++, the C++ Standard Library for your entire system,
+// under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+// SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES.
+//
+//===----------------------------------------------------------------------===//
+// UNSUPPORTED: libcpp-has-no-threads
+
+// <cuda/ptx>
+
+#include <cuda/ptx>
+#include <cuda/std/utility>
+
+#include "generated/tcgen05_cp.h"
+
+int main(int, char**)
+{
+  return 0;
+}
diff --git a/libcudacxx/test/libcudacxx/cuda/ptx/ptx.tcgen05.fence.compile.pass.cpp b/libcudacxx/test/libcudacxx/cuda/ptx/ptx.tcgen05.fence.compile.pass.cpp
new file mode 100644
index 00000000000..fda57b348de
--- /dev/null
+++ b/libcudacxx/test/libcudacxx/cuda/ptx/ptx.tcgen05.fence.compile.pass.cpp
@@ -0,0 +1,22 @@
+//===----------------------------------------------------------------------===//
+//
+// Part of libcu++, the C++ Standard Library for your entire system,
+// under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+// SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES.
+//
+//===----------------------------------------------------------------------===//
+// UNSUPPORTED: libcpp-has-no-threads
+
+// <cuda/ptx>
+
+#include <cuda/ptx>
+#include <cuda/std/utility>
+
+#include "generated/tcgen05_fence.h"
+
+int main(int, char**)
+{
+  return 0;
+}
diff --git a/libcudacxx/test/libcudacxx/cuda/ptx/ptx.tcgen05.ld.compile.pass.cpp b/libcudacxx/test/libcudacxx/cuda/ptx/ptx.tcgen05.ld.compile.pass.cpp
new file mode 100644
index 00000000000..8da8e54f18d
--- /dev/null
+++ b/libcudacxx/test/libcudacxx/cuda/ptx/ptx.tcgen05.ld.compile.pass.cpp
@@ -0,0 +1,22 @@
+//===----------------------------------------------------------------------===//
+//
+// Part of libcu++, the C++ Standard Library for your entire system,
+// under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+// SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES.
+//
+//===----------------------------------------------------------------------===//
+// UNSUPPORTED: libcpp-has-no-threads
+
+// <cuda/ptx>
+
+#include <cuda/ptx>
+#include <cuda/std/utility>
+
+#include "generated/tcgen05_ld.h"
+
+int main(int, char**)
+{
+  return 0;
+}
diff --git a/libcudacxx/test/libcudacxx/cuda/ptx/ptx.tcgen05.mma.compile.pass.cpp b/libcudacxx/test/libcudacxx/cuda/ptx/ptx.tcgen05.mma.compile.pass.cpp
new file mode 100644
index 00000000000..098cbbfa896
--- /dev/null
+++ b/libcudacxx/test/libcudacxx/cuda/ptx/ptx.tcgen05.mma.compile.pass.cpp
@@ -0,0 +1,22 @@
+//===----------------------------------------------------------------------===//
+//
+// Part of libcu++, the C++ Standard Library for your entire system,
+// under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+// SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES.
+//
+//===----------------------------------------------------------------------===//
+// UNSUPPORTED: libcpp-has-no-threads
+
+// <cuda/ptx>
+
+#include <cuda/ptx>
+#include <cuda/std/utility>
+
+#include "generated/tcgen05_mma.h"
+
+int main(int, char**)
+{
+  return 0;
+}
diff --git a/libcudacxx/test/libcudacxx/cuda/ptx/ptx.tcgen05.mma.ws.compile.pass.cpp b/libcudacxx/test/libcudacxx/cuda/ptx/ptx.tcgen05.mma.ws.compile.pass.cpp
new file mode 100644
index 00000000000..350c964d749
--- /dev/null
+++ b/libcudacxx/test/libcudacxx/cuda/ptx/ptx.tcgen05.mma.ws.compile.pass.cpp
@@ -0,0 +1,22 @@
+//===----------------------------------------------------------------------===//
+//
+// Part of libcu++, the C++ Standard Library for your entire system,
+// under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+// SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES.
+//
+//===----------------------------------------------------------------------===//
+// UNSUPPORTED: libcpp-has-no-threads
+
+// <cuda/ptx>
+
+#include <cuda/ptx>
+#include <cuda/std/utility>
+
+#include "generated/tcgen05_mma_ws.h"
+
+int main(int, char**)
+{
+  return 0;
+}
diff --git a/libcudacxx/test/libcudacxx/cuda/ptx/ptx.tcgen05.shift.compile.pass.cpp b/libcudacxx/test/libcudacxx/cuda/ptx/ptx.tcgen05.shift.compile.pass.cpp
new file mode 100644
index 00000000000..5ecfff7ff3b
--- /dev/null
+++ b/libcudacxx/test/libcudacxx/cuda/ptx/ptx.tcgen05.shift.compile.pass.cpp
@@ -0,0 +1,22 @@
+//===----------------------------------------------------------------------===//
+//
+// Part of libcu++, the C++ Standard Library for your entire system,
+// under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+// SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES.
+//
+//===----------------------------------------------------------------------===//
+// UNSUPPORTED: libcpp-has-no-threads
+
+// <cuda/ptx>
+
+#include <cuda/ptx>
+#include <cuda/std/utility>
+
+#include "generated/tcgen05_shift.h"
+
+int main(int, char**)
+{
+  return 0;
+}
diff --git a/libcudacxx/test/libcudacxx/cuda/ptx/ptx.tcgen05.st.compile.pass.cpp b/libcudacxx/test/libcudacxx/cuda/ptx/ptx.tcgen05.st.compile.pass.cpp
new file mode 100644
index 00000000000..92a49224f0e
--- /dev/null
+++ b/libcudacxx/test/libcudacxx/cuda/ptx/ptx.tcgen05.st.compile.pass.cpp
@@ -0,0 +1,22 @@
+//===----------------------------------------------------------------------===//
+//
+// Part of libcu++, the C++ Standard Library for your entire system,
+// under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+// SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES.
+//
+//===----------------------------------------------------------------------===//
+// UNSUPPORTED: libcpp-has-no-threads
+
+// <cuda/ptx>
+
+#include <cuda/ptx>
+#include <cuda/std/utility>
+
+#include "generated/tcgen05_st.h"
+
+int main(int, char**)
+{
+  return 0;
+}
diff --git a/libcudacxx/test/libcudacxx/cuda/ptx/ptx.tcgen05.wait.compile.pass.cpp b/libcudacxx/test/libcudacxx/cuda/ptx/ptx.tcgen05.wait.compile.pass.cpp
new file mode 100644
index 00000000000..4bb3156ed12
--- /dev/null
+++ b/libcudacxx/test/libcudacxx/cuda/ptx/ptx.tcgen05.wait.compile.pass.cpp
@@ -0,0 +1,22 @@
+//===----------------------------------------------------------------------===//
+//
+// Part of libcu++, the C++ Standard Library for your entire system,
+// under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+// SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES.
+//
+//===----------------------------------------------------------------------===//
+// UNSUPPORTED: libcpp-has-no-threads
+
+// <cuda/ptx>
+
+#include <cuda/ptx>
+#include <cuda/std/utility>
+
+#include "generated/tcgen05_wait.h"
+
+int main(int, char**)
+{
+  return 0;
+}

From cea61a3410fdea796154dcd9157e010659aab837 Mon Sep 17 00:00:00 2001
From: Michael Schellenberger Costa <miscco@nvidia.com>
Date: Thu, 30 Jan 2025 16:48:09 +0100
Subject: [PATCH 25/33] Use a differrent implementation for
 `tuple_of_iterator_references` to tuple conversion (#3609)

---
 .../include/cuda/std/detail/libcxx/include/tuple    | 13 +++++++++++--
 1 file changed, 11 insertions(+), 2 deletions(-)

diff --git a/libcudacxx/include/cuda/std/detail/libcxx/include/tuple b/libcudacxx/include/cuda/std/detail/libcxx/include/tuple
index 6ff1039e61b..47f8b16222b 100644
--- a/libcudacxx/include/cuda/std/detail/libcxx/include/tuple
+++ b/libcudacxx/include/cuda/std/detail/libcxx/include/tuple
@@ -891,10 +891,19 @@ public:
             enable_if_t<__is_tuple_of_iterator_references<_TupleOfIteratorReferences>::value, int> = 0,
             enable_if_t<(tuple_size<_TupleOfIteratorReferences>::value == sizeof...(_Tp)), int>    = 0>
   _LIBCUDACXX_HIDE_FROM_ABI _CCCL_CONSTEXPR_CXX14 tuple(_TupleOfIteratorReferences&& __t)
-      : tuple(_CUDA_VSTD::forward<_TupleOfIteratorReferences>(__t).template __to_tuple<_Tp...>(
-          __make_tuple_indices_t<sizeof...(_Tp)>()))
+      : tuple(_CUDA_VSTD::forward<_TupleOfIteratorReferences>(__t),
+              typename __make_tuple_indices<sizeof...(_Tp)>::type{})
   {}
 
+private:
+  template <class _TupleOfIteratorReferences,
+            size_t... _Indices,
+            enable_if_t<__is_tuple_of_iterator_references<_TupleOfIteratorReferences>::value, int> = 0>
+  _LIBCUDACXX_HIDE_FROM_ABI _CCCL_CONSTEXPR_CXX14 tuple(_TupleOfIteratorReferences&& __t, __tuple_indices<_Indices...>)
+      : tuple(_CUDA_VSTD::get<_Indices>(_CUDA_VSTD::forward<_TupleOfIteratorReferences>(__t))...)
+  {}
+
+public:
   template <class _Tuple,
             class _Constraints                                          = __tuple_like_constraints<_Tuple>,
             enable_if_t<!_PackExpandsToThisTuple<_Tuple>::value, int>   = 0,

From a00de21b5e79aa5c398efeac50b37d99d580c859 Mon Sep 17 00:00:00 2001
From: Federico Busato <50413820+fbusato@users.noreply.github.com>
Date: Thu, 30 Jan 2025 10:46:01 -0800
Subject: [PATCH 26/33] Remove CUB `DeviceSpMV` (#3549)

---
 cub/cub/agent/agent_spmv_orig.cuh             | 764 ---------------
 cub/cub/cub.cuh                               |   1 -
 cub/cub/device/device_spmv.cuh                | 216 ----
 .../device/dispatch/dispatch_spmv_orig.cuh    | 924 ------------------
 cub/test/test_device_spmv.cu                  | 611 ------------
 5 files changed, 2516 deletions(-)
 delete mode 100644 cub/cub/agent/agent_spmv_orig.cuh
 delete mode 100644 cub/cub/device/device_spmv.cuh
 delete mode 100644 cub/cub/device/dispatch/dispatch_spmv_orig.cuh
 delete mode 100644 cub/test/test_device_spmv.cu

diff --git a/cub/cub/agent/agent_spmv_orig.cuh b/cub/cub/agent/agent_spmv_orig.cuh
deleted file mode 100644
index 90a5e3aa6c9..00000000000
--- a/cub/cub/agent/agent_spmv_orig.cuh
+++ /dev/null
@@ -1,764 +0,0 @@
-/******************************************************************************
- * Copyright (c) 2011, Duane Merrill.  All rights reserved.
- * Copyright (c) 2011-2018, NVIDIA CORPORATION.  All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of the NVIDIA CORPORATION nor the
- *       names of its contributors may be used to endorse or promote products
- *       derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL NVIDIA CORPORATION BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************/
-
-/**
- * \file
- * cub::AgentSpmv implements a stateful abstraction of CUDA thread blocks for participating in device-wide SpMV.
- */
-
-#pragma once
-
-#include <cub/config.cuh>
-
-#if defined(_CCCL_IMPLICIT_SYSTEM_HEADER_GCC)
-#  pragma GCC system_header
-#elif defined(_CCCL_IMPLICIT_SYSTEM_HEADER_CLANG)
-#  pragma clang system_header
-#elif defined(_CCCL_IMPLICIT_SYSTEM_HEADER_MSVC)
-#  pragma system_header
-#endif // no system header
-
-#include <cub/block/block_exchange.cuh>
-#include <cub/block/block_reduce.cuh>
-#include <cub/block/block_scan.cuh>
-#include <cub/iterator/cache_modified_input_iterator.cuh>
-#include <cub/iterator/counting_input_iterator.cuh>
-#include <cub/thread/thread_operators.cuh>
-#include <cub/thread/thread_search.cuh>
-#include <cub/util_type.cuh>
-
-#include <cuda/std/__algorithm/max.h>
-#include <cuda/std/__algorithm/min.h>
-#include <cuda/std/type_traits>
-
-#include <iterator>
-
-CUB_NAMESPACE_BEGIN
-
-/******************************************************************************
- * Tuning policy
- ******************************************************************************/
-
-/**
- * @param Parameterizable tuning policy type for AgentSpmv
- *
- * @tparam _BLOCK_THREADS
- *   Threads per thread block
- *
- * @tparam _ITEMS_PER_THREAD
- *   Items per thread (per tile of input)
- *
- * @tparam _ROW_OFFSETS_SEARCH_LOAD_MODIFIER
- *   Cache load modifier for reading CSR row-offsets during search
- *
- * @tparam _ROW_OFFSETS_LOAD_MODIFIER
- *   Cache load modifier for reading CSR row-offsets
- *
- * @tparam _COLUMN_INDICES_LOAD_MODIFIER
- *   Cache load modifier for reading CSR column-indices
- *
- * @tparam _VALUES_LOAD_MODIFIER
- *   Cache load modifier for reading CSR values
- *
- * @tparam _VECTOR_VALUES_LOAD_MODIFIER
- *   Cache load modifier for reading vector values
- *
- * @tparam _DIRECT_LOAD_NONZEROS
- *   Whether to load nonzeros directly from global during sequential merging (vs. pre-staged through
- * shared memory)
- *
- * @tparam _SCAN_ALGORITHM
- *   The BlockScan algorithm to use
- */
-template <int _BLOCK_THREADS,
-          int _ITEMS_PER_THREAD,
-          CacheLoadModifier _ROW_OFFSETS_SEARCH_LOAD_MODIFIER,
-          CacheLoadModifier _ROW_OFFSETS_LOAD_MODIFIER,
-          CacheLoadModifier _COLUMN_INDICES_LOAD_MODIFIER,
-          CacheLoadModifier _VALUES_LOAD_MODIFIER,
-          CacheLoadModifier _VECTOR_VALUES_LOAD_MODIFIER,
-          bool _DIRECT_LOAD_NONZEROS,
-          BlockScanAlgorithm _SCAN_ALGORITHM>
-struct CCCL_DEPRECATED_BECAUSE("Use the cuSPARSE library instead") AgentSpmvPolicy
-{
-  enum
-  {
-    /// Threads per thread block
-    BLOCK_THREADS = _BLOCK_THREADS,
-
-    /// Items per thread (per tile of input)
-    ITEMS_PER_THREAD = _ITEMS_PER_THREAD,
-
-    /// Whether to load nonzeros directly from global during sequential merging (pre-staged through
-    /// shared memory)
-    DIRECT_LOAD_NONZEROS = _DIRECT_LOAD_NONZEROS,
-  };
-
-  /// Cache load modifier for reading CSR row-offsets
-  static constexpr CacheLoadModifier ROW_OFFSETS_SEARCH_LOAD_MODIFIER = _ROW_OFFSETS_SEARCH_LOAD_MODIFIER;
-
-  /// Cache load modifier for reading CSR row-offsets
-  static constexpr CacheLoadModifier ROW_OFFSETS_LOAD_MODIFIER = _ROW_OFFSETS_LOAD_MODIFIER;
-
-  /// Cache load modifier for reading CSR column-indices
-  static constexpr CacheLoadModifier COLUMN_INDICES_LOAD_MODIFIER = _COLUMN_INDICES_LOAD_MODIFIER;
-
-  /// Cache load modifier for reading CSR values
-  static constexpr CacheLoadModifier VALUES_LOAD_MODIFIER = _VALUES_LOAD_MODIFIER;
-
-  /// Cache load modifier for reading vector values
-  static constexpr CacheLoadModifier VECTOR_VALUES_LOAD_MODIFIER = _VECTOR_VALUES_LOAD_MODIFIER;
-
-  /// The BlockScan algorithm to use
-  static constexpr BlockScanAlgorithm SCAN_ALGORITHM = _SCAN_ALGORITHM;
-};
-
-/******************************************************************************
- * Thread block abstractions
- ******************************************************************************/
-
-/**
- * @tparam ValueT
- *   Matrix and vector value type
- *
- * @tparam OffsetT
- *   Signed integer type for sequence offsets
- */
-template <typename ValueT, typename OffsetT>
-struct
-// with NVHPC, we get a deprecation warning in the implementation of cudaLaunchKernelEx, which we cannot suppress :/
-#if !_CCCL_COMPILER(NVHPC)
-  CCCL_DEPRECATED_BECAUSE("Use the cuSPARSE library instead")
-#endif
-    SpmvParams
-{
-  /// Pointer to the array of \p num_nonzeros values of the corresponding nonzero elements of matrix
-  /// <b>A</b>.
-  const ValueT* d_values;
-
-  /// Pointer to the array of \p m offsets demarcating the end of every row in \p d_column_indices
-  /// and \p d_values
-  const OffsetT* d_row_end_offsets;
-
-  /// Pointer to the array of \p num_nonzeros column-indices of the corresponding nonzero elements
-  /// of matrix <b>A</b>.  (Indices are zero-valued.)
-  const OffsetT* d_column_indices;
-
-  /// Pointer to the array of \p num_cols values corresponding to the dense input vector <em>x</em>
-  const ValueT* d_vector_x;
-
-  /// Pointer to the array of \p num_rows values corresponding to the dense output vector <em>y</em>
-  ValueT* d_vector_y;
-
-  /// Number of rows of matrix <b>A</b>.
-  int num_rows;
-
-  /// Number of columns of matrix <b>A</b>.
-  int num_cols;
-
-  /// Number of nonzero elements of matrix <b>A</b>.
-  int num_nonzeros;
-
-  /// Alpha multiplicand
-  ValueT alpha;
-
-  /// Beta addend-multiplicand
-  ValueT beta;
-};
-
-/**
- * @brief AgentSpmv implements a stateful abstraction of CUDA thread blocks for participating in device-wide SpMV.
- *
- * @tparam AgentSpmvPolicyT
- *   Parameterized AgentSpmvPolicy tuning policy type
- *
- * @tparam ValueT
- *   Matrix and vector value type
- *
- * @tparam OffsetT
- *   Signed integer type for sequence offsets
- *
- * @tparam HAS_ALPHA
- *   Whether the input parameter \p alpha is 1
- *
- * @tparam HAS_BETA
- *   Whether the input parameter \p beta is 0
- *
- * @tparam LEGACY_PTX_ARCH
- *   PTX compute capability (unused)
- */
-template <typename AgentSpmvPolicyT,
-          typename ValueT,
-          typename OffsetT,
-          bool HAS_ALPHA,
-          bool HAS_BETA,
-          int LEGACY_PTX_ARCH = 0>
-struct CCCL_DEPRECATED_BECAUSE("Use the cuSPARSE library instead") AgentSpmv
-{
-  //---------------------------------------------------------------------
-  // Types and constants
-  //---------------------------------------------------------------------
-
-  /// Constants
-  enum
-  {
-    BLOCK_THREADS    = AgentSpmvPolicyT::BLOCK_THREADS,
-    ITEMS_PER_THREAD = AgentSpmvPolicyT::ITEMS_PER_THREAD,
-    TILE_ITEMS       = BLOCK_THREADS * ITEMS_PER_THREAD,
-  };
-
-  /// 2D merge path coordinate type
-  using CoordinateT = typename CubVector<OffsetT, 2>::Type;
-
-  /// Input iterator wrapper types (for applying cache modifiers)
-
-  using RowOffsetsSearchIteratorT =
-    CacheModifiedInputIterator<AgentSpmvPolicyT::ROW_OFFSETS_SEARCH_LOAD_MODIFIER, OffsetT, OffsetT>;
-
-  using RowOffsetsIteratorT = CacheModifiedInputIterator<AgentSpmvPolicyT::ROW_OFFSETS_LOAD_MODIFIER, OffsetT, OffsetT>;
-
-  using ColumnIndicesIteratorT =
-    CacheModifiedInputIterator<AgentSpmvPolicyT::COLUMN_INDICES_LOAD_MODIFIER, OffsetT, OffsetT>;
-
-  using ValueIteratorT = CacheModifiedInputIterator<AgentSpmvPolicyT::VALUES_LOAD_MODIFIER, ValueT, OffsetT>;
-
-  using VectorValueIteratorT =
-    CacheModifiedInputIterator<AgentSpmvPolicyT::VECTOR_VALUES_LOAD_MODIFIER, ValueT, OffsetT>;
-
-  // Tuple type for scanning (pairs accumulated segment-value with segment-index)
-  using KeyValuePairT = KeyValuePair<OffsetT, ValueT>;
-
-  // Reduce-value-by-segment scan operator
-  using ReduceBySegmentOpT = ReduceByKeyOp<::cuda::std::plus<>>;
-
-  // BlockReduce specialization
-  using BlockReduceT = BlockReduce<ValueT, BLOCK_THREADS, BLOCK_REDUCE_WARP_REDUCTIONS>;
-
-  // BlockScan specialization
-  using BlockScanT = BlockScan<KeyValuePairT, BLOCK_THREADS, AgentSpmvPolicyT::SCAN_ALGORITHM>;
-
-  // BlockScan specialization
-  using BlockPrefixSumT = BlockScan<ValueT, BLOCK_THREADS, AgentSpmvPolicyT::SCAN_ALGORITHM>;
-
-  // BlockExchange specialization
-  using BlockExchangeT = BlockExchange<ValueT, BLOCK_THREADS, ITEMS_PER_THREAD>;
-
-  /// Merge item type (either a non-zero value or a row-end offset)
-  union MergeItem
-  {
-    // Value type to pair with index type OffsetT
-    // (NullType if loading values directly during merge)
-    using MergeValueT = ::cuda::std::_If<AgentSpmvPolicyT::DIRECT_LOAD_NONZEROS, NullType, ValueT>;
-
-    OffsetT row_end_offset;
-    MergeValueT nonzero;
-  };
-
-  /// Shared memory type required by this thread block
-  struct _TempStorage
-  {
-    CoordinateT tile_coords[2];
-
-    union Aliasable
-    {
-      // Smem needed for tile of merge items
-      MergeItem merge_items[ITEMS_PER_THREAD + TILE_ITEMS + 1];
-
-      // Smem needed for block exchange
-      typename BlockExchangeT::TempStorage exchange;
-
-      // Smem needed for block-wide reduction
-      typename BlockReduceT::TempStorage reduce;
-
-      // Smem needed for tile scanning
-      typename BlockScanT::TempStorage scan;
-
-      // Smem needed for tile prefix sum
-      typename BlockPrefixSumT::TempStorage prefix_sum;
-
-    } aliasable;
-  };
-
-  /// Temporary storage type (unionable)
-  struct TempStorage : Uninitialized<_TempStorage>
-  {};
-
-  //---------------------------------------------------------------------
-  // Per-thread fields
-  //---------------------------------------------------------------------
-
-  /// Reference to temp_storage
-  _TempStorage& temp_storage;
-
-  _CCCL_SUPPRESS_DEPRECATED_PUSH
-  SpmvParams<ValueT, OffsetT>& spmv_params;
-  _CCCL_SUPPRESS_DEPRECATED_POP
-
-  /// Wrapped pointer to the array of \p num_nonzeros values of the corresponding nonzero elements
-  /// of matrix <b>A</b>.
-  ValueIteratorT wd_values;
-
-  /// Wrapped Pointer to the array of \p m offsets demarcating the end of every row in \p
-  /// d_column_indices and \p d_values
-  RowOffsetsIteratorT wd_row_end_offsets;
-
-  /// Wrapped Pointer to the array of \p num_nonzeros column-indices of the corresponding nonzero
-  /// elements of matrix <b>A</b>.  (Indices are zero-valued.)
-  ColumnIndicesIteratorT wd_column_indices;
-
-  /// Wrapped Pointer to the array of \p num_cols values corresponding to the dense input vector
-  /// <em>x</em>
-  VectorValueIteratorT wd_vector_x;
-
-  /// Wrapped Pointer to the array of \p num_cols values corresponding to the dense input vector
-  /// <em>x</em>
-  VectorValueIteratorT wd_vector_y;
-
-  //---------------------------------------------------------------------
-  // Interface
-  //---------------------------------------------------------------------
-
-  /**
-   * @param temp_storage
-   *   Reference to temp_storage
-   *
-   * @param spmv_params
-   *   SpMV input parameter bundle
-   */
-  _CCCL_SUPPRESS_DEPRECATED_PUSH
-  _CCCL_DEVICE _CCCL_FORCEINLINE AgentSpmv(TempStorage& temp_storage, SpmvParams<ValueT, OffsetT>& spmv_params)
-      : temp_storage(temp_storage.Alias())
-      , spmv_params(spmv_params)
-      , wd_values(spmv_params.d_values)
-      , wd_row_end_offsets(spmv_params.d_row_end_offsets)
-      , wd_column_indices(spmv_params.d_column_indices)
-      , wd_vector_x(spmv_params.d_vector_x)
-      , wd_vector_y(spmv_params.d_vector_y)
-  {}
-  _CCCL_SUPPRESS_DEPRECATED_POP
-
-  /**
-   * @brief Consume a merge tile, specialized for direct-load of nonzeros
-   *
-   * @param is_direct_load
-   *   Marker type indicating whether to load nonzeros directly during path-discovery or beforehand in batch
-   */
-  _CCCL_DEVICE _CCCL_FORCEINLINE KeyValuePairT
-  ConsumeTile(int tile_idx, CoordinateT tile_start_coord, CoordinateT tile_end_coord, Int2Type<true> is_direct_load)
-  {
-    int tile_num_rows               = tile_end_coord.x - tile_start_coord.x;
-    int tile_num_nonzeros           = tile_end_coord.y - tile_start_coord.y;
-    OffsetT* s_tile_row_end_offsets = &temp_storage.aliasable.merge_items[0].row_end_offset;
-
-    // Gather the row end-offsets for the merge tile into shared memory
-    for (int item = threadIdx.x; item < tile_num_rows + ITEMS_PER_THREAD; item += BLOCK_THREADS)
-    {
-      const OffsetT offset = (::cuda::std::min)(
-        static_cast<OffsetT>(tile_start_coord.x + item), static_cast<OffsetT>(spmv_params.num_rows - 1));
-      s_tile_row_end_offsets[item] = wd_row_end_offsets[offset];
-    }
-
-    __syncthreads();
-
-    // Search for the thread's starting coordinate within the merge tile
-    _CCCL_SUPPRESS_DEPRECATED_PUSH
-    CountingInputIterator<OffsetT> tile_nonzero_indices(tile_start_coord.y);
-    _CCCL_SUPPRESS_DEPRECATED_POP
-    CoordinateT thread_start_coord;
-
-    MergePathSearch(
-      OffsetT(threadIdx.x * ITEMS_PER_THREAD), // Diagonal
-      s_tile_row_end_offsets, // List A
-      tile_nonzero_indices, // List B
-      tile_num_rows,
-      tile_num_nonzeros,
-      thread_start_coord);
-
-    __syncthreads(); // Perf-sync
-
-    // Compute the thread's merge path segment
-    CoordinateT thread_current_coord = thread_start_coord;
-    KeyValuePairT scan_segment[ITEMS_PER_THREAD];
-
-    ValueT running_total = 0.0;
-
-#pragma unroll
-    for (int ITEM = 0; ITEM < ITEMS_PER_THREAD; ++ITEM)
-    {
-      OffsetT nonzero_idx = CUB_MIN(tile_nonzero_indices[thread_current_coord.y], spmv_params.num_nonzeros - 1);
-      OffsetT column_idx  = wd_column_indices[nonzero_idx];
-      ValueT value        = wd_values[nonzero_idx];
-
-      ValueT vector_value = wd_vector_x[column_idx];
-
-      ValueT nonzero = value * vector_value;
-
-      OffsetT row_end_offset = s_tile_row_end_offsets[thread_current_coord.x];
-
-      if (tile_nonzero_indices[thread_current_coord.y] < row_end_offset)
-      {
-        // Move down (accumulate)
-        running_total += nonzero;
-        scan_segment[ITEM].value = running_total;
-        scan_segment[ITEM].key   = tile_num_rows;
-        ++thread_current_coord.y;
-      }
-      else
-      {
-        // Move right (reset)
-        scan_segment[ITEM].value = running_total;
-        scan_segment[ITEM].key   = thread_current_coord.x;
-        running_total            = 0.0;
-        ++thread_current_coord.x;
-      }
-    }
-
-    __syncthreads();
-
-    // Block-wide reduce-value-by-segment
-    KeyValuePairT tile_carry;
-    ReduceBySegmentOpT scan_op;
-    KeyValuePairT scan_item;
-
-    scan_item.value = running_total;
-    scan_item.key   = thread_current_coord.x;
-
-    BlockScanT(temp_storage.aliasable.scan).ExclusiveScan(scan_item, scan_item, scan_op, tile_carry);
-
-    if (tile_num_rows > 0)
-    {
-      if (threadIdx.x == 0)
-      {
-        scan_item.key = -1;
-      }
-
-// Direct scatter
-#pragma unroll
-      for (int ITEM = 0; ITEM < ITEMS_PER_THREAD; ++ITEM)
-      {
-        if (scan_segment[ITEM].key < tile_num_rows)
-        {
-          if (scan_item.key == scan_segment[ITEM].key)
-          {
-            scan_segment[ITEM].value = scan_item.value + scan_segment[ITEM].value;
-          }
-
-          if (HAS_ALPHA)
-          {
-            scan_segment[ITEM].value *= spmv_params.alpha;
-          }
-
-          if (HAS_BETA)
-          {
-            // Update the output vector element
-            ValueT addend = spmv_params.beta * wd_vector_y[tile_start_coord.x + scan_segment[ITEM].key];
-            scan_segment[ITEM].value += addend;
-          }
-
-          // Set the output vector element
-          spmv_params.d_vector_y[tile_start_coord.x + scan_segment[ITEM].key] = scan_segment[ITEM].value;
-        }
-      }
-    }
-
-    // Return the tile's running carry-out
-    return tile_carry;
-  }
-
-  /**
-   * @brief Consume a merge tile, specialized for indirect load of nonzeros
-   *
-   * @param is_direct_load
-   *   Marker type indicating whether to load nonzeros directly during path-discovery or beforehand in batch
-   */
-  _CCCL_DEVICE _CCCL_FORCEINLINE KeyValuePairT
-  ConsumeTile(int tile_idx, CoordinateT tile_start_coord, CoordinateT tile_end_coord, Int2Type<false> is_direct_load)
-  {
-    int tile_num_rows     = tile_end_coord.x - tile_start_coord.x;
-    int tile_num_nonzeros = tile_end_coord.y - tile_start_coord.y;
-
-#if (CUB_PTX_ARCH >= 520)
-
-    OffsetT* s_tile_row_end_offsets = &temp_storage.aliasable.merge_items[0].row_end_offset;
-    ValueT* s_tile_nonzeros         = &temp_storage.aliasable.merge_items[tile_num_rows + ITEMS_PER_THREAD].nonzero;
-
-// Gather the nonzeros for the merge tile into shared memory
-#  pragma unroll
-    for (int ITEM = 0; ITEM < ITEMS_PER_THREAD; ++ITEM)
-    {
-      int nonzero_idx = threadIdx.x + (ITEM * BLOCK_THREADS);
-
-      ValueIteratorT a          = wd_values + tile_start_coord.y + nonzero_idx;
-      ColumnIndicesIteratorT ci = wd_column_indices + tile_start_coord.y + nonzero_idx;
-      ValueT* s                 = s_tile_nonzeros + nonzero_idx;
-
-      if (nonzero_idx < tile_num_nonzeros)
-      {
-        OffsetT column_idx = *ci;
-        ValueT value       = *a;
-
-        ValueT vector_value = wd_vector_x[column_idx];
-
-        ValueT nonzero = value * vector_value;
-
-        *s = nonzero;
-      }
-    }
-
-#else
-
-    OffsetT* s_tile_row_end_offsets = &temp_storage.aliasable.merge_items[0].row_end_offset;
-    ValueT* s_tile_nonzeros         = &temp_storage.aliasable.merge_items[tile_num_rows + ITEMS_PER_THREAD].nonzero;
-
-    // Gather the nonzeros for the merge tile into shared memory
-    if (tile_num_nonzeros > 0)
-    {
-#  pragma unroll
-      for (int ITEM = 0; ITEM < ITEMS_PER_THREAD; ++ITEM)
-      {
-        int nonzero_idx = threadIdx.x + (ITEM * BLOCK_THREADS);
-        nonzero_idx     = CUB_MIN(nonzero_idx, tile_num_nonzeros - 1);
-
-        OffsetT column_idx = wd_column_indices[tile_start_coord.y + nonzero_idx];
-        ValueT value       = wd_values[tile_start_coord.y + nonzero_idx];
-
-        ValueT vector_value = wd_vector_x[column_idx];
-
-        ValueT nonzero = value * vector_value;
-
-        s_tile_nonzeros[nonzero_idx] = nonzero;
-      }
-    }
-
-#endif
-
-// Gather the row end-offsets for the merge tile into shared memory
-#pragma unroll 1
-    for (int item = threadIdx.x; item < tile_num_rows + ITEMS_PER_THREAD; item += BLOCK_THREADS)
-    {
-      const OffsetT offset = (::cuda::std::min)(
-        static_cast<OffsetT>(tile_start_coord.x + item), static_cast<OffsetT>(spmv_params.num_rows - 1));
-      s_tile_row_end_offsets[item] = wd_row_end_offsets[offset];
-    }
-
-    __syncthreads();
-
-    // Search for the thread's starting coordinate within the merge tile
-    _CCCL_SUPPRESS_DEPRECATED_PUSH
-    CountingInputIterator<OffsetT> tile_nonzero_indices(tile_start_coord.y);
-    _CCCL_SUPPRESS_DEPRECATED_POP
-    CoordinateT thread_start_coord;
-
-    MergePathSearch(
-      OffsetT(threadIdx.x * ITEMS_PER_THREAD), // Diagonal
-      s_tile_row_end_offsets, // List A
-      tile_nonzero_indices, // List B
-      tile_num_rows,
-      tile_num_nonzeros,
-      thread_start_coord);
-
-    __syncthreads(); // Perf-sync
-
-    // Compute the thread's merge path segment
-    CoordinateT thread_current_coord = thread_start_coord;
-    KeyValuePairT scan_segment[ITEMS_PER_THREAD];
-    ValueT running_total = 0.0;
-
-    OffsetT row_end_offset = s_tile_row_end_offsets[thread_current_coord.x];
-    ValueT nonzero         = s_tile_nonzeros[thread_current_coord.y];
-
-#pragma unroll
-    for (int ITEM = 0; ITEM < ITEMS_PER_THREAD; ++ITEM)
-    {
-      if (tile_nonzero_indices[thread_current_coord.y] < row_end_offset)
-      {
-        // Move down (accumulate)
-        scan_segment[ITEM].value = nonzero;
-        running_total += nonzero;
-        ++thread_current_coord.y;
-        nonzero = s_tile_nonzeros[thread_current_coord.y];
-      }
-      else
-      {
-        // Move right (reset)
-        scan_segment[ITEM].value = 0.0;
-        running_total            = 0.0;
-        ++thread_current_coord.x;
-        row_end_offset = s_tile_row_end_offsets[thread_current_coord.x];
-      }
-
-      scan_segment[ITEM].key = thread_current_coord.x;
-    }
-
-    __syncthreads();
-
-    // Block-wide reduce-value-by-segment
-    KeyValuePairT tile_carry;
-    ReduceBySegmentOpT scan_op;
-    KeyValuePairT scan_item;
-
-    scan_item.value = running_total;
-    scan_item.key   = thread_current_coord.x;
-
-    BlockScanT(temp_storage.aliasable.scan).ExclusiveScan(scan_item, scan_item, scan_op, tile_carry);
-
-    if (threadIdx.x == 0)
-    {
-      scan_item.key   = thread_start_coord.x;
-      scan_item.value = 0.0;
-    }
-
-    if (tile_num_rows > 0)
-    {
-      __syncthreads();
-
-      // Scan downsweep and scatter
-      ValueT* s_partials = &temp_storage.aliasable.merge_items[0].nonzero;
-
-      if (scan_item.key != scan_segment[0].key)
-      {
-        s_partials[scan_item.key] = scan_item.value;
-      }
-      else
-      {
-        scan_segment[0].value += scan_item.value;
-      }
-
-#pragma unroll
-      for (int ITEM = 1; ITEM < ITEMS_PER_THREAD; ++ITEM)
-      {
-        if (scan_segment[ITEM - 1].key != scan_segment[ITEM].key)
-        {
-          s_partials[scan_segment[ITEM - 1].key] = scan_segment[ITEM - 1].value;
-        }
-        else
-        {
-          scan_segment[ITEM].value += scan_segment[ITEM - 1].value;
-        }
-      }
-
-      __syncthreads();
-
-#pragma unroll 1
-      for (int item = threadIdx.x; item < tile_num_rows; item += BLOCK_THREADS)
-      {
-        spmv_params.d_vector_y[tile_start_coord.x + item] = s_partials[item];
-      }
-    }
-
-    // Return the tile's running carry-out
-    return tile_carry;
-  }
-
-  /**
-   * @brief Consume input tile
-   *
-   * @param[in] d_tile_coordinates
-   *   Pointer to the temporary array of tile starting coordinates
-   *
-   * @param[out] d_tile_carry_pairs
-   *   Pointer to the temporary array carry-out dot product row-ids, one per block
-   *
-   * @param[in] num_merge_tiles
-   *   Number of merge tiles
-   */
-  _CCCL_DEVICE _CCCL_FORCEINLINE void
-  ConsumeTile(CoordinateT* d_tile_coordinates, KeyValuePairT* d_tile_carry_pairs, int num_merge_tiles)
-  {
-    int tile_idx = (blockIdx.x * gridDim.y) + blockIdx.y; // Current tile index
-
-    if (tile_idx >= num_merge_tiles)
-    {
-      return;
-    }
-
-    // Read our starting coordinates
-    if (threadIdx.x < 2)
-    {
-      if (d_tile_coordinates == nullptr)
-      {
-        // Search our starting coordinates
-        OffsetT diagonal = (tile_idx + threadIdx.x) * TILE_ITEMS;
-        CoordinateT tile_coord;
-        _CCCL_SUPPRESS_DEPRECATED_PUSH
-        CountingInputIterator<OffsetT> nonzero_indices(0);
-        _CCCL_SUPPRESS_DEPRECATED_POP
-
-        // Search the merge path
-        MergePathSearch(
-          diagonal,
-          RowOffsetsSearchIteratorT(spmv_params.d_row_end_offsets),
-          nonzero_indices,
-          spmv_params.num_rows,
-          spmv_params.num_nonzeros,
-          tile_coord);
-
-        temp_storage.tile_coords[threadIdx.x] = tile_coord;
-      }
-      else
-      {
-        temp_storage.tile_coords[threadIdx.x] = d_tile_coordinates[tile_idx + threadIdx.x];
-      }
-    }
-
-    __syncthreads();
-
-    CoordinateT tile_start_coord = temp_storage.tile_coords[0];
-    CoordinateT tile_end_coord   = temp_storage.tile_coords[1];
-
-    // Consume multi-segment tile
-    KeyValuePairT tile_carry =
-      ConsumeTile(tile_idx, tile_start_coord, tile_end_coord, Int2Type<AgentSpmvPolicyT::DIRECT_LOAD_NONZEROS>());
-
-    // Output the tile's carry-out
-    if (threadIdx.x == 0)
-    {
-      if (HAS_ALPHA)
-      {
-        tile_carry.value *= spmv_params.alpha;
-      }
-
-      tile_carry.key += tile_start_coord.x;
-      if (tile_carry.key >= spmv_params.num_rows)
-      {
-        // FIXME: This works around an invalid memory access in the
-        // fixup kernel. The underlying issue needs to be debugged and
-        // properly fixed, but this hack prevents writes to
-        // out-of-bounds addresses. It doesn't appear to have an effect
-        // on the validity of the results, since this only affects the
-        // carry-over from last tile in the input.
-        tile_carry.key   = spmv_params.num_rows - 1;
-        tile_carry.value = ValueT{};
-      };
-
-      d_tile_carry_pairs[tile_idx] = tile_carry;
-    }
-  }
-};
-
-CUB_NAMESPACE_END
diff --git a/cub/cub/cub.cuh b/cub/cub/cub.cuh
index 2c4d6dd5f4e..ce55c879e0c 100644
--- a/cub/cub/cub.cuh
+++ b/cub/cub/cub.cuh
@@ -75,7 +75,6 @@
 #include <cub/device/device_segmented_reduce.cuh>
 #include <cub/device/device_segmented_sort.cuh>
 #include <cub/device/device_select.cuh>
-#include <cub/device/device_spmv.cuh>
 #include <cub/device/device_transform.cuh>
 
 // Grid
diff --git a/cub/cub/device/device_spmv.cuh b/cub/cub/device/device_spmv.cuh
deleted file mode 100644
index 241af8cd1d1..00000000000
--- a/cub/cub/device/device_spmv.cuh
+++ /dev/null
@@ -1,216 +0,0 @@
-
-/******************************************************************************
- * Copyright (c) 2011, Duane Merrill.  All rights reserved.
- * Copyright (c) 2011-2022, NVIDIA CORPORATION.  All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of the NVIDIA CORPORATION nor the
- *       names of its contributors may be used to endorse or promote products
- *       derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL NVIDIA CORPORATION BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************/
-
-//! @file
-//! cub::DeviceSpmv provides device-wide parallel operations for performing sparse-matrix * vector multiplication
-//! (SpMV).
-
-#pragma once
-
-#include <cub/config.cuh>
-
-#if defined(_CCCL_IMPLICIT_SYSTEM_HEADER_GCC)
-#  pragma GCC system_header
-#elif defined(_CCCL_IMPLICIT_SYSTEM_HEADER_CLANG)
-#  pragma clang system_header
-#elif defined(_CCCL_IMPLICIT_SYSTEM_HEADER_MSVC)
-#  pragma system_header
-#endif // no system header
-
-#include <cub/config.cuh>
-
-#include <cub/detail/nvtx.cuh>
-#include <cub/device/dispatch/dispatch_spmv_orig.cuh>
-
-#include <iterator>
-#include <limits>
-
-#include <stdio.h>
-
-CUB_NAMESPACE_BEGIN
-
-//! @rst
-//! DeviceSpmv provides device-wide parallel operations for performing
-//! sparse-matrix * dense-vector multiplication (SpMV).
-//!
-//! Overview
-//! +++++++++++++++++++++++++++++++++++++++++++++
-//!
-//! The `SpMV computation <http://en.wikipedia.org/wiki/Sparse_matrix-vector_multiplication>`_
-//! performs the matrix-vector operation ``y = A * x + y``, where:
-//!
-//!  - ``A`` is an ``m * n`` sparse matrix whose non-zero structure is specified in
-//!    `compressed-storage-row (CSR) format
-//!    <https://en.wikipedia.org/wiki/Sparse_matrix#Compressed_sparse_row_(CSR,_CRS_or_Yale_format)>`_ (i.e., three
-//!    arrays:
-//!    ``values``, ``row_offsets``, and ``column_indices``)
-//!  - ``x`` and ``y`` are dense vectors
-//!
-//! Usage Considerations
-//! +++++++++++++++++++++++++++++++++++++++++++++
-//!
-//! @cdp_class{DeviceSpmv}
-//!
-//! @endrst
-struct CCCL_DEPRECATED_BECAUSE("Use the cuSPARSE library instead") DeviceSpmv
-{
-  //! @name CSR matrix operations
-  //! @{
-
-  //! @rst
-  //! This function performs the matrix-vector operation ``y = A*x``.
-  //!
-  //! Snippet
-  //! +++++++++++++++++++++++++++++++++++++++++++++
-  //!
-  //! The code snippet below illustrates SpMV upon a 9x9 CSR matrix ``A`` representing a 3x3 lattice (24 non-zeros).
-  //!
-  //! .. code-block:: c++
-  //!
-  //!    #include <cub/cub.cuh>   // or equivalently <cub/device/device_spmv.cuh>
-  //!
-  //!    // Declare, allocate, and initialize device-accessible pointers for input matrix A, input
-  //!    vector x,
-  //!    // and output vector y
-  //!    int    num_rows = 9;
-  //!    int    num_cols = 9;
-  //!    int    num_nonzeros = 24;
-  //!
-  //!    float* d_values;  // e.g., [1, 1, 1, 1, 1, 1, 1, 1,
-  //!                      //        1, 1, 1, 1, 1, 1, 1, 1,
-  //!                      //        1, 1, 1, 1, 1, 1, 1, 1]
-  //!
-  //!    int*   d_column_indices; // e.g., [1, 3, 0, 2, 4, 1, 5, 0,
-  //!                             //        4, 6, 1, 3, 5, 7, 2, 4,
-  //!                             //        8, 3, 7, 4, 6, 8, 5, 7]
-  //!
-  //!    int*   d_row_offsets;    // e.g., [0, 2, 5, 7, 10, 14, 17, 19, 22, 24]
-  //!
-  //!    float* d_vector_x;       // e.g., [1, 1, 1, 1, 1, 1, 1, 1, 1]
-  //!    float* d_vector_y;       // e.g., [ ,  ,  ,  ,  ,  ,  ,  ,  ]
-  //!    ...
-  //!
-  //!    // Determine temporary device storage requirements
-  //!    void*    d_temp_storage = nullptr;
-  //!    size_t   temp_storage_bytes = 0;
-  //!    cub::DeviceSpmv::CsrMV(d_temp_storage, temp_storage_bytes, d_values,
-  //!        d_row_offsets, d_column_indices, d_vector_x, d_vector_y,
-  //!        num_rows, num_cols, num_nonzeros);
-  //!
-  //!    // Allocate temporary storage
-  //!    cudaMalloc(&d_temp_storage, temp_storage_bytes);
-  //!
-  //!    // Run SpMV
-  //!    cub::DeviceSpmv::CsrMV(d_temp_storage, temp_storage_bytes, d_values,
-  //!        d_row_offsets, d_column_indices, d_vector_x, d_vector_y,
-  //!        num_rows, num_cols, num_nonzeros);
-  //!
-  //!    // d_vector_y <-- [2, 3, 2, 3, 4, 3, 2, 3, 2]
-  //!
-  //! @endrst
-  //!
-  //! @tparam ValueT
-  //!   **[inferred]** Matrix and vector value type (e.g., `float`, `double`, etc.)
-  //!
-  //! @param[in] d_temp_storage
-  //!   Device-accessible allocation of temporary storage.
-  //!   When nullptr, the required allocation size is written to `temp_storage_bytes` and no work is done.
-  //!
-  //! @param[in,out] temp_storage_bytes
-  //!   Reference to size in bytes of `d_temp_storage` allocation
-  //!
-  //! @param[in] d_values
-  //!   Pointer to the array of `num_nonzeros` values of the corresponding nonzero elements
-  //!   of matrix `A`.
-  //!
-  //! @param[in] d_row_offsets
-  //!   Pointer to the array of `m + 1` offsets demarcating the start of every row in
-  //!   `d_column_indices` and `d_values` (with the final entry being equal to `num_nonzeros`)
-  //!
-  //! @param[in] d_column_indices
-  //!   Pointer to the array of `num_nonzeros` column-indices of the corresponding nonzero
-  //!   elements of matrix `A`. (Indices are zero-valued.)
-  //!
-  //! @param[in] d_vector_x
-  //!   Pointer to the array of `num_cols` values corresponding to the dense input vector `x`
-  //!
-  //! @param[out] d_vector_y
-  //!   Pointer to the array of `num_rows` values corresponding to the dense output vector `y`
-  //!
-  //! @param[in] num_rows
-  //!   number of rows of matrix `A`.
-  //!
-  //! @param[in] num_cols
-  //!   number of columns of matrix `A`.
-  //!
-  //! @param[in] num_nonzeros
-  //!   number of nonzero elements of matrix `A`.
-  //!
-  //! @param[in] stream
-  //!   @rst
-  //!   **[optional]** CUDA stream to launch kernels within. Default is stream\ :sub:`0`.
-  //!   @endrst
-  template <typename ValueT>
-  CCCL_DEPRECATED_BECAUSE("Use the cuSPARSE library instead")
-  CUB_RUNTIME_FUNCTION static cudaError_t
-    CsrMV(void* d_temp_storage,
-          size_t& temp_storage_bytes,
-          const ValueT* d_values,
-          const int* d_row_offsets,
-          const int* d_column_indices,
-          const ValueT* d_vector_x,
-          ValueT* d_vector_y,
-          int num_rows,
-          int num_cols,
-          int num_nonzeros,
-          cudaStream_t stream = 0)
-  {
-    CUB_DETAIL_NVTX_RANGE_SCOPE_IF(d_temp_storage, "cub::DeviceSpmv::CsrMV");
-
-    SpmvParams<ValueT, int> spmv_params;
-    spmv_params.d_values          = d_values;
-    spmv_params.d_row_end_offsets = d_row_offsets + 1;
-    spmv_params.d_column_indices  = d_column_indices;
-    spmv_params.d_vector_x        = d_vector_x;
-    spmv_params.d_vector_y        = d_vector_y;
-    spmv_params.num_rows          = num_rows;
-    spmv_params.num_cols          = num_cols;
-    spmv_params.num_nonzeros      = num_nonzeros;
-    spmv_params.alpha             = ValueT{1};
-    spmv_params.beta              = ValueT{0};
-
-    _CCCL_SUPPRESS_DEPRECATED_PUSH
-    return DispatchSpmv<ValueT, int>::Dispatch(d_temp_storage, temp_storage_bytes, spmv_params, stream);
-    _CCCL_SUPPRESS_DEPRECATED_POP
-  }
-
-  //! @}  end member group
-};
-
-CUB_NAMESPACE_END
diff --git a/cub/cub/device/dispatch/dispatch_spmv_orig.cuh b/cub/cub/device/dispatch/dispatch_spmv_orig.cuh
deleted file mode 100644
index 16353f392dc..00000000000
--- a/cub/cub/device/dispatch/dispatch_spmv_orig.cuh
+++ /dev/null
@@ -1,924 +0,0 @@
-
-/******************************************************************************
- * Copyright (c) 2011, Duane Merrill.  All rights reserved.
- * Copyright (c) 2011-2018, NVIDIA CORPORATION.  All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of the NVIDIA CORPORATION nor the
- *       names of its contributors may be used to endorse or promote products
- *       derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL NVIDIA CORPORATION BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************/
-
-/**
- * @file
- * cub::DeviceSpmv provides device-wide parallel operations for performing sparse-matrix * vector
- * multiplication (SpMV).
- */
-
-#pragma once
-
-#include <cub/config.cuh>
-
-#if defined(_CCCL_IMPLICIT_SYSTEM_HEADER_GCC)
-#  pragma GCC system_header
-#elif defined(_CCCL_IMPLICIT_SYSTEM_HEADER_CLANG)
-#  pragma clang system_header
-#elif defined(_CCCL_IMPLICIT_SYSTEM_HEADER_MSVC)
-#  pragma system_header
-#endif // no system header
-
-#include <cub/agent/agent_segment_fixup.cuh>
-#include <cub/agent/agent_spmv_orig.cuh>
-#include <cub/agent/single_pass_scan_operators.cuh>
-#include <cub/grid/grid_queue.cuh>
-#include <cub/thread/thread_search.cuh>
-#include <cub/util_debug.cuh>
-#include <cub/util_device.cuh>
-#include <cub/util_math.cuh>
-#include <cub/util_type.cuh>
-
-#include <thrust/system/cuda/detail/core/triple_chevron_launch.h>
-
-#include <cstdio>
-#include <iterator>
-
-#include <nv/target>
-
-CUB_NAMESPACE_BEGIN
-
-/******************************************************************************
- * SpMV kernel entry points
- *****************************************************************************/
-
-/**
- * @brief Spmv search kernel. Identifies merge path starting coordinates for each tile.
- *
- * @tparam AgentSpmvPolicyT
- *   Parameterized SpmvPolicy tuning policy type
- *
- * @tparam ValueT
- *   Matrix and vector value type
- *
- * @tparam OffsetT
- *   Signed integer type for sequence offsets
- *
- * @param[in] spmv_params
- *   SpMV input parameter bundle
- */
-_CCCL_SUPPRESS_DEPRECATED_PUSH
-template <typename AgentSpmvPolicyT, typename ValueT, typename OffsetT>
-CCCL_DEPRECATED_BECAUSE("Use the cuSPARSE library instead")
-CUB_DETAIL_KERNEL_ATTRIBUTES void DeviceSpmv1ColKernel(SpmvParams<ValueT, OffsetT> spmv_params) //
-  _CCCL_SUPPRESS_DEPRECATED_POP
-{
-  using VectorValueIteratorT =
-    CacheModifiedInputIterator<AgentSpmvPolicyT::VECTOR_VALUES_LOAD_MODIFIER, ValueT, OffsetT>;
-
-  VectorValueIteratorT wrapped_vector_x(spmv_params.d_vector_x);
-
-  int row_idx = (blockIdx.x * blockDim.x) + threadIdx.x;
-  if (row_idx < spmv_params.num_rows)
-  {
-    OffsetT end_nonzero_idx = spmv_params.d_row_end_offsets[row_idx];
-    OffsetT nonzero_idx     = spmv_params.d_row_end_offsets[row_idx - 1];
-
-    ValueT value = 0.0;
-    if (end_nonzero_idx != nonzero_idx)
-    {
-      value = spmv_params.d_values[nonzero_idx] * wrapped_vector_x[spmv_params.d_column_indices[nonzero_idx]];
-    }
-
-    spmv_params.d_vector_y[row_idx] = value;
-  }
-}
-
-/**
- * @brief Spmv search kernel. Identifies merge path starting coordinates for each tile.
- *
- * @tparam SpmvPolicyT
- *   Parameterized SpmvPolicy tuning policy type
- *
- * @tparam OffsetT
- *   Signed integer type for sequence offsets
- *
- * @tparam CoordinateT
- *   Merge path coordinate type
- *
- * @tparam SpmvParamsT
- *   SpmvParams type
- *
- * @param[in] num_merge_tiles
- *   Number of SpMV merge tiles (spmv grid size)
- *
- * @param[out] d_tile_coordinates
- *   Pointer to the temporary array of tile starting coordinates
- *
- * @param[in] spmv_params
- *   SpMV input parameter bundle
- */
-template <typename SpmvPolicyT, typename OffsetT, typename CoordinateT, typename SpmvParamsT>
-CCCL_DEPRECATED_BECAUSE("Use the cuSPARSE library instead")
-CUB_DETAIL_KERNEL_ATTRIBUTES void DeviceSpmvSearchKernel(
-  int num_merge_tiles, CoordinateT* d_tile_coordinates, SpmvParamsT spmv_params)
-{
-  /// Constants
-  enum
-  {
-    BLOCK_THREADS    = SpmvPolicyT::BLOCK_THREADS,
-    ITEMS_PER_THREAD = SpmvPolicyT::ITEMS_PER_THREAD,
-    TILE_ITEMS       = BLOCK_THREADS * ITEMS_PER_THREAD,
-  };
-
-  using RowOffsetsSearchIteratorT =
-    CacheModifiedInputIterator<SpmvPolicyT::ROW_OFFSETS_SEARCH_LOAD_MODIFIER, OffsetT, OffsetT>;
-
-  // Find the starting coordinate for all tiles (plus the end coordinate of the last one)
-  int tile_idx = (blockIdx.x * blockDim.x) + threadIdx.x;
-  if (tile_idx < num_merge_tiles + 1)
-  {
-    OffsetT diagonal = (tile_idx * TILE_ITEMS);
-    CoordinateT tile_coordinate;
-    _CCCL_SUPPRESS_DEPRECATED_PUSH
-    CountingInputIterator<OffsetT> nonzero_indices(0);
-    _CCCL_SUPPRESS_DEPRECATED_POP
-
-    // Search the merge path
-    MergePathSearch(
-      diagonal,
-      RowOffsetsSearchIteratorT(spmv_params.d_row_end_offsets),
-      nonzero_indices,
-      spmv_params.num_rows,
-      spmv_params.num_nonzeros,
-      tile_coordinate);
-
-    // Output starting offset
-    d_tile_coordinates[tile_idx] = tile_coordinate;
-  }
-}
-
-/**
- * @brief Spmv agent entry point
- *
- * @tparam SpmvPolicyT
- *   Parameterized SpmvPolicy tuning policy type
- *
- * @tparam ScanTileStateT
- *   Tile status interface type
- *
- * @tparam ValueT
- *   Matrix and vector value type
- *
- * @tparam OffsetT
- *   Signed integer type for sequence offsets
- *
- * @tparam CoordinateT
- *   Merge path coordinate type
- *
- * @tparam HAS_ALPHA
- *   Whether the input parameter Alpha is 1
- *
- * @tparam HAS_BETA
- *   Whether the input parameter Beta is 0
- *
- * @param[in] spmv_params
- *   SpMV input parameter bundle
- *
- * @param[in] d_tile_coordinates
- *   Pointer to the temporary array of tile starting coordinates
- *
- * @param[out] d_tile_carry_pairs
- *   Pointer to the temporary array carry-out dot product row-ids, one per block
- *
- * @param[in] num_tiles
- *   Number of merge tiles
- *
- * @param[in] tile_state
- *   Tile status interface for fixup reduce-by-key kernel
- *
- * @param[in] num_segment_fixup_tiles
- *   Number of reduce-by-key tiles (fixup grid size)
- */
-template <typename SpmvPolicyT,
-          typename ScanTileStateT,
-          typename ValueT,
-          typename OffsetT,
-          typename CoordinateT,
-          bool HAS_ALPHA,
-          bool HAS_BETA>
-CCCL_DEPRECATED_BECAUSE("Use the cuSPARSE library instead")
-__launch_bounds__(int(SpmvPolicyT::BLOCK_THREADS)) CUB_DETAIL_KERNEL_ATTRIBUTES void DeviceSpmvKernel(
-  SpmvParams<ValueT, OffsetT> spmv_params,
-  CoordinateT* d_tile_coordinates,
-  KeyValuePair<OffsetT, ValueT>* d_tile_carry_pairs,
-  int num_tiles,
-  ScanTileStateT tile_state,
-  int num_segment_fixup_tiles)
-{
-  // Spmv agent type specialization
-  _CCCL_SUPPRESS_DEPRECATED_PUSH
-  using AgentSpmvT = AgentSpmv<SpmvPolicyT, ValueT, OffsetT, HAS_ALPHA, HAS_BETA>;
-  _CCCL_SUPPRESS_DEPRECATED_POP
-
-  // Shared memory for AgentSpmv
-  __shared__ typename AgentSpmvT::TempStorage temp_storage;
-
-  AgentSpmvT(temp_storage, spmv_params).ConsumeTile(d_tile_coordinates, d_tile_carry_pairs, num_tiles);
-
-  // Initialize fixup tile status
-  tile_state.InitializeStatus(num_segment_fixup_tiles);
-}
-
-/**
- * @tparam ValueT
- *   Matrix and vector value type
- *
- * @tparam OffsetT
- *   Signed integer type for sequence offsets
- *
- * @tparam HAS_BETA
- *   Whether the input parameter Beta is 0
- */
-template <typename ValueT, typename OffsetT, bool HAS_BETA>
-CCCL_DEPRECATED_BECAUSE("Use the cuSPARSE library instead")
-CUB_DETAIL_KERNEL_ATTRIBUTES void DeviceSpmvEmptyMatrixKernel(SpmvParams<ValueT, OffsetT> spmv_params)
-{
-  const int row = static_cast<int>(threadIdx.x + blockIdx.x * blockDim.x);
-
-  if (row < spmv_params.num_rows)
-  {
-    ValueT result = 0.0;
-
-    _CCCL_IF_CONSTEXPR (HAS_BETA)
-    {
-      result += spmv_params.beta * spmv_params.d_vector_y[row];
-    }
-
-    spmv_params.d_vector_y[row] = result;
-  }
-}
-
-/**
- * @brief Multi-block reduce-by-key sweep kernel entry point
- *
- * @tparam AgentSegmentFixupPolicyT
- *   Parameterized AgentSegmentFixupPolicy tuning policy type
- *
- * @tparam PairsInputIteratorT
- *   Random-access input iterator type for keys
- *
- * @tparam AggregatesOutputIteratorT
- *   Random-access output iterator type for values
- *
- * @tparam OffsetT
- *   Signed integer type for global offsets
- *
- * @tparam ScanTileStateT
- *   Tile status interface type
- *
- * @param[in] d_pairs_in
- *   Pointer to the array carry-out dot product row-ids, one per spmv block
- *
- * @param[in,out] d_aggregates_out
- *   Output value aggregates
- *
- * @param[in] num_items
- *   Total number of items to select from
- *
- * @param[in] num_tiles
- *   Total number of tiles for the entire problem
- *
- * @param[in] tile_state
- *   Tile status interface
- */
-_CCCL_SUPPRESS_DEPRECATED_PUSH
-template <typename AgentSegmentFixupPolicyT,
-          typename PairsInputIteratorT,
-          typename AggregatesOutputIteratorT,
-          typename OffsetT,
-          typename ScanTileStateT>
-CCCL_DEPRECATED_BECAUSE("Use the cuSPARSE library instead")
-__launch_bounds__(int(AgentSegmentFixupPolicyT::BLOCK_THREADS))
-  CUB_DETAIL_KERNEL_ATTRIBUTES void DeviceSegmentFixupKernel(
-    PairsInputIteratorT d_pairs_in,
-    AggregatesOutputIteratorT d_aggregates_out,
-    OffsetT num_items,
-    int num_tiles,
-    ScanTileStateT tile_state) //
-  _CCCL_SUPPRESS_DEPRECATED_POP
-{
-  // Thread block type for reducing tiles of value segments
-  using AgentSegmentFixupT =
-    AgentSegmentFixup<AgentSegmentFixupPolicyT,
-                      PairsInputIteratorT,
-                      AggregatesOutputIteratorT,
-                      ::cuda::std::equal_to<>,
-                      ::cuda::std::plus<>,
-                      OffsetT>;
-
-  // Shared memory for AgentSegmentFixup
-  __shared__ typename AgentSegmentFixupT::TempStorage temp_storage;
-
-  // Process tiles
-  AgentSegmentFixupT(temp_storage, d_pairs_in, d_aggregates_out, ::cuda::std::equal_to<>{}, ::cuda::std::plus<>{})
-    .ConsumeRange(num_items, num_tiles, tile_state);
-}
-
-/******************************************************************************
- * Dispatch
- ******************************************************************************/
-
-/**
- * @brief Utility class for dispatching the appropriately-tuned kernels for DeviceSpmv
- *
- * @tparam ValueT
- *   Matrix and vector value type
- *
- * @tparam OffsetT
- *   Signed integer type for global offsets
- */
-template <typename ValueT, typename OffsetT>
-struct CCCL_DEPRECATED_BECAUSE("Use the cuSPARSE library instead") DispatchSpmv
-{
-  //---------------------------------------------------------------------
-  // Constants and Types
-  //---------------------------------------------------------------------
-
-  enum
-  {
-    INIT_KERNEL_THREADS         = 128,
-    EMPTY_MATRIX_KERNEL_THREADS = 128
-  };
-
-  // SpmvParams bundle type
-  using SpmvParamsT = SpmvParams<ValueT, OffsetT>;
-
-  // 2D merge path coordinate type
-  using CoordinateT = typename CubVector<OffsetT, 2>::Type;
-
-  // Tile status descriptor interface type
-  using ScanTileStateT = ReduceByKeyScanTileState<ValueT, OffsetT>;
-
-  // Tuple type for scanning (pairs accumulated segment-value with segment-index)
-  using KeyValuePairT = KeyValuePair<OffsetT, ValueT>;
-
-  //---------------------------------------------------------------------
-  // Tuning policies
-  //---------------------------------------------------------------------
-
-  /// SM50
-  struct Policy500
-  {
-    using SpmvPolicyT =
-      AgentSpmvPolicy<(sizeof(ValueT) > 4) ? 64 : 128,
-                      (sizeof(ValueT) > 4) ? 6 : 7,
-                      LOAD_LDG,
-                      LOAD_DEFAULT,
-                      (sizeof(ValueT) > 4) ? LOAD_LDG : LOAD_DEFAULT,
-                      (sizeof(ValueT) > 4) ? LOAD_LDG : LOAD_DEFAULT,
-                      LOAD_LDG,
-                      (sizeof(ValueT) > 4) ? true : false,
-                      (sizeof(ValueT) > 4) ? BLOCK_SCAN_WARP_SCANS : BLOCK_SCAN_RAKING_MEMOIZE>;
-
-    using SegmentFixupPolicyT =
-      AgentSegmentFixupPolicy<128, 3, BLOCK_LOAD_VECTORIZE, LOAD_LDG, BLOCK_SCAN_RAKING_MEMOIZE>;
-  };
-
-  /// SM60
-  struct Policy600
-  {
-    using SpmvPolicyT =
-      AgentSpmvPolicy<(sizeof(ValueT) > 4) ? 64 : 128,
-                      (sizeof(ValueT) > 4) ? 5 : 7,
-                      LOAD_DEFAULT,
-                      LOAD_DEFAULT,
-                      LOAD_DEFAULT,
-                      LOAD_DEFAULT,
-                      LOAD_DEFAULT,
-                      false,
-                      BLOCK_SCAN_WARP_SCANS>;
-
-    using SegmentFixupPolicyT = AgentSegmentFixupPolicy<128, 3, BLOCK_LOAD_DIRECT, LOAD_LDG, BLOCK_SCAN_WARP_SCANS>;
-  };
-
-  //---------------------------------------------------------------------
-  // Tuning policies of current PTX compiler pass
-  //---------------------------------------------------------------------
-
-#if (CUB_PTX_ARCH >= 600)
-  using PtxPolicy = Policy600;
-
-#else
-  using PtxPolicy = Policy500;
-#endif
-
-  // "Opaque" policies (whose parameterizations aren't reflected in the type signature)
-  struct PtxSpmvPolicyT : PtxPolicy::SpmvPolicyT
-  {};
-  struct PtxSegmentFixupPolicy : PtxPolicy::SegmentFixupPolicyT
-  {};
-
-  //---------------------------------------------------------------------
-  // Utilities
-  //---------------------------------------------------------------------
-
-  /**
-   * Initialize kernel dispatch configurations with the policies corresponding to the PTX assembly we will use
-   */
-  template <typename KernelConfig>
-  CUB_RUNTIME_FUNCTION _CCCL_FORCEINLINE static void
-  InitConfigs(int ptx_version, KernelConfig& spmv_config, KernelConfig& segment_fixup_config)
-  {
-    NV_IF_TARGET(
-      NV_IS_DEVICE,
-      ( // We're on the device, so initialize the kernel dispatch
-        // configurations with the current PTX policy
-        spmv_config.template Init<PtxSpmvPolicyT>(); segment_fixup_config.template Init<PtxSegmentFixupPolicy>();),
-      (
-        // We're on the host, so lookup and initialize the kernel dispatch
-        // configurations with the policies that match the device's PTX
-        // version
-        if (ptx_version >= 600) {
-          spmv_config.template Init<typename Policy600::SpmvPolicyT>();
-          segment_fixup_config.template Init<typename Policy600::SegmentFixupPolicyT>();
-        } else if (ptx_version >= 500) {
-          spmv_config.template Init<typename Policy500::SpmvPolicyT>();
-          segment_fixup_config.template Init<typename Policy500::SegmentFixupPolicyT>();
-        } else {
-          spmv_config.template Init<typename Policy500::SpmvPolicyT>();
-          segment_fixup_config.template Init<typename Policy500::SegmentFixupPolicyT>();
-        }));
-  }
-
-  /**
-   * Kernel kernel dispatch configuration.
-   */
-  struct KernelConfig
-  {
-    int block_threads;
-    int items_per_thread;
-    int tile_items;
-
-    template <typename PolicyT>
-    CUB_RUNTIME_FUNCTION _CCCL_FORCEINLINE void Init()
-    {
-      block_threads    = PolicyT::BLOCK_THREADS;
-      items_per_thread = PolicyT::ITEMS_PER_THREAD;
-      tile_items       = block_threads * items_per_thread;
-    }
-  };
-
-  //---------------------------------------------------------------------
-  // Dispatch entrypoints
-  //---------------------------------------------------------------------
-
-  /**
-   * Internal dispatch routine for computing a device-wide reduction using the
-   * specified kernel functions.
-   *
-   * If the input is larger than a single tile, this method uses two-passes of
-   * kernel invocations.
-   *
-   * @tparam Spmv1ColKernelT
-   *   Function type of cub::DeviceSpmv1ColKernel
-   *
-   * @tparam SpmvSearchKernelT
-   *   Function type of cub::AgentSpmvSearchKernel
-   *
-   * @tparam SpmvKernelT
-   *   Function type of cub::AgentSpmvKernel
-   *
-   * @tparam SegmentFixupKernelT
-   *   Function type of cub::DeviceSegmentFixupKernelT
-   *
-   * @tparam SpmvEmptyMatrixKernelT
-   *   Function type of cub::DeviceSpmvEmptyMatrixKernel
-   *
-   * @param[in] d_temp_storage
-   *   Device-accessible allocation of temporary storage.
-   *   When nullptr, the required allocation size is written to
-   *   `temp_storage_bytes` and no work is done.
-   *
-   * @param[in,out] temp_storage_bytes
-   *   Reference to size in bytes of \p d_temp_storage allocation
-   *
-   * @paramSpMV spmv_params
-   *   input parameter bundle
-   *
-   * @param[in] stream
-   *   CUDA stream to launch kernels within. Default is stream<sub>0</sub>.
-   *
-   * @param[in] spmv_1col_kernel
-   *   Kernel function pointer to parameterization of DeviceSpmv1ColKernel
-   *
-   * @param[in] spmv_search_kernel
-   *   Kernel function pointer to parameterization of AgentSpmvSearchKernel
-   *
-   * @param[in] spmv_kernel
-   *   Kernel function pointer to parameterization of AgentSpmvKernel
-   *
-   * @param[in] segment_fixup_kernel
-   *   Kernel function pointer to parameterization of cub::DeviceSegmentFixupKernel
-   *
-   * @param[in] spmv_empty_matrix_kernel
-   *   Kernel function pointer to parameterization of cub::DeviceSpmvEmptyMatrixKernel
-   *
-   * @param[in] spmv_config
-   *   Dispatch parameters that match the policy that @p spmv_kernel was compiled for
-   *
-   * @param[in] segment_fixup_config
-   *   Dispatch parameters that match the policy that @p segment_fixup_kernel was compiled for
-   */
-  template <typename Spmv1ColKernelT,
-            typename SpmvSearchKernelT,
-            typename SpmvKernelT,
-            typename SegmentFixupKernelT,
-            typename SpmvEmptyMatrixKernelT>
-  CUB_RUNTIME_FUNCTION _CCCL_VISIBILITY_HIDDEN _CCCL_FORCEINLINE static cudaError_t Dispatch(
-    void* d_temp_storage,
-    size_t& temp_storage_bytes,
-    SpmvParamsT& spmv_params,
-    cudaStream_t stream,
-    Spmv1ColKernelT spmv_1col_kernel,
-    SpmvSearchKernelT spmv_search_kernel,
-    SpmvKernelT spmv_kernel,
-    SegmentFixupKernelT segment_fixup_kernel,
-    SpmvEmptyMatrixKernelT spmv_empty_matrix_kernel,
-    KernelConfig spmv_config,
-    KernelConfig segment_fixup_config)
-  {
-    cudaError error = cudaSuccess;
-    do
-    {
-      if (spmv_params.num_rows < 0 || spmv_params.num_cols < 0)
-      {
-        return cudaErrorInvalidValue;
-      }
-
-      if (spmv_params.num_rows == 0 || spmv_params.num_cols == 0)
-      { // Empty problem, no-op.
-        if (d_temp_storage == nullptr)
-        {
-          temp_storage_bytes = 1;
-        }
-
-        break;
-      }
-
-      if (spmv_params.num_nonzeros == 0)
-      {
-        if (d_temp_storage == nullptr)
-        {
-          // Return if the caller is simply requesting the size of the storage allocation
-          temp_storage_bytes = 1;
-          break;
-        }
-
-        constexpr int threads_in_block = EMPTY_MATRIX_KERNEL_THREADS;
-        const int blocks_in_grid       = ::cuda::ceil_div(spmv_params.num_rows, threads_in_block);
-
-#ifdef CUB_DEBUG_LOG
-        _CubLog("Invoking spmv_empty_matrix_kernel<<<%d, %d, 0, %lld>>>()\n",
-                blocks_in_grid,
-                threads_in_block,
-                (long long) stream);
-#endif // CUB_DEBUG_LOG
-        error = THRUST_NS_QUALIFIER::cuda_cub::launcher::triple_chevron(blocks_in_grid, threads_in_block, 0, stream)
-                  .doit(spmv_empty_matrix_kernel, spmv_params);
-
-        if (CubDebug(error))
-        {
-          break;
-        }
-
-        // Sync the stream if specified to flush runtime errors
-        error = detail::DebugSyncStream(stream);
-        if (CubDebug(error))
-        {
-          break;
-        }
-
-        break;
-      }
-
-      if (spmv_params.num_cols == 1)
-      {
-        if (d_temp_storage == nullptr)
-        {
-          // Return if the caller is simply requesting the size of the storage allocation
-          temp_storage_bytes = 1;
-          break;
-        }
-
-        // Get search/init grid dims
-        int degen_col_kernel_block_size = INIT_KERNEL_THREADS;
-        int degen_col_kernel_grid_size  = ::cuda::ceil_div(spmv_params.num_rows, degen_col_kernel_block_size);
-
-#ifdef CUB_DEBUG_LOG
-        _CubLog("Invoking spmv_1col_kernel<<<%d, %d, 0, %lld>>>()\n",
-                degen_col_kernel_grid_size,
-                degen_col_kernel_block_size,
-                (long long) stream);
-#endif // CUB_DEBUG_LOG
-
-        // Invoke spmv_search_kernel
-        THRUST_NS_QUALIFIER::cuda_cub::launcher::triple_chevron(
-          degen_col_kernel_grid_size, degen_col_kernel_block_size, 0, stream)
-          .doit(spmv_1col_kernel, spmv_params);
-
-        // Check for failure to launch
-        if (CubDebug(error = cudaPeekAtLastError()))
-        {
-          break;
-        }
-
-        // Sync the stream if specified to flush runtime errors
-        error = detail::DebugSyncStream(stream);
-        if (CubDebug(error))
-        {
-          break;
-        }
-
-        break;
-      }
-
-      // Get device ordinal
-      int device_ordinal;
-      if (CubDebug(error = cudaGetDevice(&device_ordinal)))
-      {
-        break;
-      }
-
-      // Get SM count
-      int sm_count;
-      if (CubDebug(error = cudaDeviceGetAttribute(&sm_count, cudaDevAttrMultiProcessorCount, device_ordinal)))
-      {
-        break;
-      }
-
-      // Get max x-dimension of grid
-      int max_dim_x;
-      if (CubDebug(error = cudaDeviceGetAttribute(&max_dim_x, cudaDevAttrMaxGridDimX, device_ordinal)))
-      {
-        break;
-      }
-
-      // Total number of spmv work items
-      int num_merge_items = spmv_params.num_rows + spmv_params.num_nonzeros;
-
-      // Tile sizes of kernels
-      int merge_tile_size         = spmv_config.block_threads * spmv_config.items_per_thread;
-      int segment_fixup_tile_size = segment_fixup_config.block_threads * segment_fixup_config.items_per_thread;
-
-      // Number of tiles for kernels
-      int num_merge_tiles         = ::cuda::ceil_div(num_merge_items, merge_tile_size);
-      int num_segment_fixup_tiles = ::cuda::ceil_div(num_merge_tiles, segment_fixup_tile_size);
-
-      // Get SM occupancy for kernels
-      int spmv_sm_occupancy;
-      if (CubDebug(error = MaxSmOccupancy(spmv_sm_occupancy, spmv_kernel, spmv_config.block_threads)))
-      {
-        break;
-      }
-
-      int segment_fixup_sm_occupancy;
-      if (CubDebug(error = MaxSmOccupancy(
-                     segment_fixup_sm_occupancy, segment_fixup_kernel, segment_fixup_config.block_threads)))
-      {
-        break;
-      }
-
-      // Get grid dimensions
-      dim3 spmv_grid_size(CUB_MIN(num_merge_tiles, max_dim_x), ::cuda::ceil_div(num_merge_tiles, max_dim_x), 1);
-
-      dim3 segment_fixup_grid_size(
-        CUB_MIN(num_segment_fixup_tiles, max_dim_x), ::cuda::ceil_div(num_segment_fixup_tiles, max_dim_x), 1);
-
-      // Get the temporary storage allocation requirements
-      size_t allocation_sizes[3];
-      if (CubDebug(error = ScanTileStateT::AllocationSize(num_segment_fixup_tiles, allocation_sizes[0])))
-      {
-        break; // bytes needed for reduce-by-key tile status descriptors
-      }
-      allocation_sizes[1] = num_merge_tiles * sizeof(KeyValuePairT); // bytes needed for block carry-out pairs
-      allocation_sizes[2] = (num_merge_tiles + 1) * sizeof(CoordinateT); // bytes needed for tile starting coordinates
-
-      // Alias the temporary allocations from the single storage blob (or compute the necessary size of the blob)
-      void* allocations[3] = {};
-      if (CubDebug(error = AliasTemporaries(d_temp_storage, temp_storage_bytes, allocations, allocation_sizes)))
-      {
-        break;
-      }
-      if (d_temp_storage == nullptr)
-      {
-        // Return if the caller is simply requesting the size of the storage allocation
-        break;
-      }
-
-      // Construct the tile status interface
-      ScanTileStateT tile_state;
-      if (CubDebug(error = tile_state.Init(num_segment_fixup_tiles, allocations[0], allocation_sizes[0])))
-      {
-        break;
-      }
-
-      // Alias the other allocations
-      KeyValuePairT* d_tile_carry_pairs = (KeyValuePairT*) allocations[1]; // Agent carry-out pairs
-      CoordinateT* d_tile_coordinates   = (CoordinateT*) allocations[2]; // Agent starting coordinates
-
-      // Get search/init grid dims
-      int search_block_size = INIT_KERNEL_THREADS;
-      int search_grid_size  = ::cuda::ceil_div(num_merge_tiles + 1, search_block_size);
-
-      if (search_grid_size < sm_count)
-      //            if (num_merge_tiles < spmv_sm_occupancy * sm_count)
-      {
-        // Not enough spmv tiles to saturate the device: have spmv blocks search their own staring coords
-        d_tile_coordinates = nullptr;
-      }
-      else
-      {
-// Use separate search kernel if we have enough spmv tiles to saturate the device
-
-// Log spmv_search_kernel configuration
-#ifdef CUB_DEBUG_LOG
-        _CubLog("Invoking spmv_search_kernel<<<%d, %d, 0, %lld>>>()\n",
-                search_grid_size,
-                search_block_size,
-                (long long) stream);
-#endif // CUB_DEBUG_LOG
-
-        // Invoke spmv_search_kernel
-        THRUST_NS_QUALIFIER::cuda_cub::launcher::triple_chevron(search_grid_size, search_block_size, 0, stream)
-          .doit(spmv_search_kernel, num_merge_tiles, d_tile_coordinates, spmv_params);
-
-        // Check for failure to launch
-        if (CubDebug(error = cudaPeekAtLastError()))
-        {
-          break;
-        }
-
-        // Sync the stream if specified to flush runtime errors
-        error = detail::DebugSyncStream(stream);
-        if (CubDebug(error))
-        {
-          break;
-        }
-      }
-
-// Log spmv_kernel configuration
-#ifdef CUB_DEBUG_LOG
-      _CubLog("Invoking spmv_kernel<<<{%d,%d,%d}, %d, 0, %lld>>>(), %d items per thread, %d SM occupancy\n",
-              spmv_grid_size.x,
-              spmv_grid_size.y,
-              spmv_grid_size.z,
-              spmv_config.block_threads,
-              (long long) stream,
-              spmv_config.items_per_thread,
-              spmv_sm_occupancy);
-#endif // CUB_DEBUG_LOG
-
-      // Invoke spmv_kernel
-      THRUST_NS_QUALIFIER::cuda_cub::launcher::triple_chevron(spmv_grid_size, spmv_config.block_threads, 0, stream)
-        .doit(spmv_kernel,
-              spmv_params,
-              d_tile_coordinates,
-              d_tile_carry_pairs,
-              num_merge_tiles,
-              tile_state,
-              num_segment_fixup_tiles);
-
-      // Check for failure to launch
-      if (CubDebug(error = cudaPeekAtLastError()))
-      {
-        break;
-      }
-
-      // Sync the stream if specified to flush runtime errors
-      error = detail::DebugSyncStream(stream);
-      if (CubDebug(error))
-      {
-        break;
-      }
-
-      // Run reduce-by-key fixup if necessary
-      if (num_merge_tiles > 1)
-      {
-// Log segment_fixup_kernel configuration
-#ifdef CUB_DEBUG_LOG
-        _CubLog("Invoking segment_fixup_kernel<<<{%d,%d,%d}, %d, 0, %lld>>>(), %d items per thread, %d SM occupancy\n",
-                segment_fixup_grid_size.x,
-                segment_fixup_grid_size.y,
-                segment_fixup_grid_size.z,
-                segment_fixup_config.block_threads,
-                (long long) stream,
-                segment_fixup_config.items_per_thread,
-                segment_fixup_sm_occupancy);
-#endif // CUB_DEBUG_LOG
-
-        // Invoke segment_fixup_kernel
-        THRUST_NS_QUALIFIER::cuda_cub::launcher::triple_chevron(
-          segment_fixup_grid_size, segment_fixup_config.block_threads, 0, stream)
-          .doit(segment_fixup_kernel,
-                d_tile_carry_pairs,
-                spmv_params.d_vector_y,
-                num_merge_tiles,
-                num_segment_fixup_tiles,
-                tile_state);
-
-        // Check for failure to launch
-        if (CubDebug(error = cudaPeekAtLastError()))
-        {
-          break;
-        }
-
-        // Sync the stream if specified to flush runtime errors
-        error = detail::DebugSyncStream(stream);
-        if (CubDebug(error))
-        {
-          break;
-        }
-      }
-    } while (0);
-
-    return error;
-  }
-
-  /**
-   * @brief Internal dispatch routine for computing a device-wide reduction
-   *
-   * @param[in] d_temp_storage
-   *   Device-accessible allocation of temporary storage.
-   *   When nullptr, the required allocation size is written to
-   *   `temp_storage_bytes` and no work is done.
-   *
-   * @param[in,out] temp_storage_bytes
-   *   Reference to size in bytes of `d_temp_storage` allocation
-   *
-   * @param SpMV spmv_params
-   *   input parameter bundle
-   *
-   * @param[in] stream
-   *   **[optional]** CUDA stream to launch kernels within. Default is stream<sub>0</sub>.
-   */
-  CUB_RUNTIME_FUNCTION _CCCL_FORCEINLINE static cudaError_t
-  Dispatch(void* d_temp_storage, size_t& temp_storage_bytes, SpmvParamsT& spmv_params, cudaStream_t stream = 0)
-  {
-    cudaError error = cudaSuccess;
-    do
-    {
-      // Get PTX version
-      int ptx_version = 0;
-      if (CubDebug(error = PtxVersion(ptx_version)))
-      {
-        break;
-      }
-
-      // Get kernel kernel dispatch configurations
-      KernelConfig spmv_config, segment_fixup_config;
-      InitConfigs(ptx_version, spmv_config, segment_fixup_config);
-
-      constexpr bool has_alpha = false;
-      constexpr bool has_beta  = false;
-
-      if (CubDebug(
-            error = Dispatch(
-              d_temp_storage,
-              temp_storage_bytes,
-              spmv_params,
-              stream,
-              DeviceSpmv1ColKernel<PtxSpmvPolicyT, ValueT, OffsetT>,
-              DeviceSpmvSearchKernel<PtxSpmvPolicyT, OffsetT, CoordinateT, SpmvParamsT>,
-              DeviceSpmvKernel<PtxSpmvPolicyT, ScanTileStateT, ValueT, OffsetT, CoordinateT, has_alpha, has_beta>,
-              DeviceSegmentFixupKernel<PtxSegmentFixupPolicy, KeyValuePairT*, ValueT*, OffsetT, ScanTileStateT>,
-              DeviceSpmvEmptyMatrixKernel<ValueT, OffsetT, has_beta>,
-              spmv_config,
-              segment_fixup_config)))
-      {
-        break;
-      }
-
-    } while (0);
-
-    return error;
-  }
-};
-
-CUB_NAMESPACE_END
diff --git a/cub/test/test_device_spmv.cu b/cub/test/test_device_spmv.cu
deleted file mode 100644
index 13dba77a594..00000000000
--- a/cub/test/test_device_spmv.cu
+++ /dev/null
@@ -1,611 +0,0 @@
-/******************************************************************************
- * Copyright (c) 2021, NVIDIA CORPORATION.  All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of the NVIDIA CORPORATION nor the
- *       names of its contributors may be used to endorse or promote products
- *       derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL NVIDIA CORPORATION BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************/
-
-// Ensure printing of CUDA runtime errors to console
-#define CUB_STDERR
-
-#include <cub/device/device_spmv.cuh>
-#include <cub/util_debug.cuh>
-
-#include <thrust/distance.h>
-#include <thrust/execution_policy.h>
-#include <thrust/host_vector.h>
-#include <thrust/mismatch.h>
-#include <thrust/scan.h>
-
-#include <cuda/std/type_traits>
-
-#include <iostream>
-#include <type_traits>
-#include <typeinfo>
-
-#include "test_util.h"
-#include <c2h/device_policy.h>
-#include <c2h/vector.h>
-
-_CCCL_SUPPRESS_DEPRECATED_PUSH
-
-bool g_verbose = false;
-
-//==============================================================================
-// Casts char types to int for numeric printing
-template <typename T>
-T print_cast(T val)
-{
-  return val;
-}
-
-int print_cast(char val)
-{
-  return static_cast<int>(val);
-}
-
-int print_cast(signed char val)
-{
-  return static_cast<int>(val);
-}
-
-int print_cast(unsigned char val)
-{
-  return static_cast<int>(val);
-}
-
-//==============================================================================
-// Print a vector to out
-template <typename VectorT>
-void print_vector(std::ostream& out, const VectorT& vec)
-{
-  bool first = true;
-  for (const auto& val : vec)
-  {
-    if (!first)
-    {
-      out << ", ";
-    }
-    first = false;
-    out << print_cast(val);
-  }
-}
-
-//==============================================================================
-// Simple CSR matrix implementation.
-// HostStorage controls whether data is stored on the host or device.
-// Use the host_csr_matrix and device_csr_matrix aliases for code clarity.
-template <typename ValueT, bool HostStorage>
-struct csr_matrix
-{
-  csr_matrix(int num_rows, int num_cols)
-      : m_row_offsets(static_cast<size_t>(num_rows + 1), 0)
-      , m_num_rows(num_rows)
-      , m_num_columns(num_cols)
-  {}
-
-  // host/device conversion constructor
-  explicit csr_matrix(const csr_matrix<ValueT, !HostStorage>& other)
-      : m_values(other.m_values)
-      , m_row_offsets(other.m_row_offsets)
-      , m_column_indices(other.m_column_indices)
-      , m_num_rows(other.m_num_rows)
-      , m_num_columns(other.m_num_columns)
-      , m_num_nonzeros(other.m_num_nonzeros)
-  {}
-
-  // Note that this must append to the values array. Finish filling each row
-  // before adding to the next, and each row's columns must be added in order.
-  // Must call `finalize` once all items are added.
-  void append_value(int row, int col, ValueT value)
-  {
-    ++m_num_nonzeros;
-    ++m_row_offsets[row];
-    m_column_indices.push_back(col);
-    m_values.push_back(std::move(value));
-  }
-
-  void finalize()
-  {
-    _CCCL_IF_CONSTEXPR (HostStorage)
-    {
-      thrust::exclusive_scan(thrust::host, m_row_offsets.cbegin(), m_row_offsets.cend(), m_row_offsets.begin());
-    }
-    else
-    {
-      thrust::exclusive_scan(c2h::device_policy, m_row_offsets.cbegin(), m_row_offsets.cend(), m_row_offsets.begin());
-    }
-    AssertEquals(m_row_offsets.back(), m_num_nonzeros);
-  }
-
-  const ValueT* get_values() const
-  {
-    return thrust::raw_pointer_cast(m_values.data());
-  }
-
-  const int* get_row_offsets() const
-  {
-    return thrust::raw_pointer_cast(m_row_offsets.data());
-  }
-
-  int get_row_offset(int row) const
-  {
-    return m_row_offsets[row];
-  }
-
-  int get_row_num_nonzero(int row) const
-  {
-    return m_row_offsets[row + 1] - m_row_offsets[row];
-  }
-
-  const int* get_column_indices() const
-  {
-    return thrust::raw_pointer_cast(m_column_indices.data());
-  }
-
-  int get_num_rows() const
-  {
-    return m_num_rows;
-  }
-
-  int get_num_columns() const
-  {
-    return m_num_columns;
-  }
-
-  int get_num_nonzeros() const
-  {
-    return m_num_nonzeros;
-  }
-
-  void print_internals(std::ostream& out) const
-  {
-    out << (HostStorage ? "host" : "device") << "_csr_matrix"
-        << "(" << m_num_rows << ", " << m_num_columns << ")\n"
-        << " - num_elems:   " << (m_num_rows * m_num_columns) << "\n"
-        << " - num_nonzero: " << m_num_nonzeros << "\n"
-        << " - row_offsets:\n     [";
-    print_vector(out, m_row_offsets);
-    out << "]\n"
-        << " - column_indices:\n     [";
-    print_vector(out, m_column_indices);
-    out << "]\n"
-        << " - values:\n     [";
-    print_vector(out, m_values);
-    out << "]\n";
-  }
-
-  void print_summary(std::ostream& out) const
-  {
-    const int num_elems = m_num_rows * m_num_columns;
-    const float fill_ratio =
-      num_elems == 0 ? 0.f : (static_cast<float>(m_num_nonzeros) / static_cast<float>(num_elems));
-
-    out << m_num_rows << "x" << m_num_columns << ", " << m_num_nonzeros << "/" << num_elems << " (" << fill_ratio
-        << ")\n";
-  }
-
-  friend class csr_matrix<ValueT, !HostStorage>;
-
-private:
-  template <typename VecValueT>
-  using vector_t = ::cuda::std::_If<HostStorage, c2h::host_vector<VecValueT>, c2h::device_vector<VecValueT>>;
-
-  vector_t<ValueT> m_values;
-  vector_t<int> m_row_offsets;
-  vector_t<int> m_column_indices;
-
-  int m_num_rows{0};
-  int m_num_columns{0};
-  int m_num_nonzeros{0};
-};
-
-//==============================================================================
-// Convenience aliases for host/device csr_matrix types.
-template <typename ValueT>
-using host_csr_matrix = csr_matrix<ValueT, true>;
-
-template <typename ValueT>
-using device_csr_matrix = csr_matrix<ValueT, false>;
-
-//==============================================================================
-// Compare two floats within a tolerance.
-// This mimics the approach used by Thrust's ASSERT_ALMOST_EQUAL checks.
-template <typename ValueT>
-struct fp_almost_equal_functor
-{
-  __host__ __device__ bool operator()(ValueT v1, ValueT v2) const
-  {
-    constexpr double r_tol = 1e-3;
-    constexpr double a_tol = 1e-2;
-    const double limit     = r_tol * (std::fabs(v1) + std::fabs(v2)) + a_tol;
-    return std::fabs(v1 - v2) <= limit;
-  }
-};
-
-//==============================================================================
-// Compare the reference and cub output vectors.
-// Use fuzzy check for floating point values.
-template <typename ValueT>
-bool compare_results(
-  std::true_type /* is_fp */, const c2h::host_vector<ValueT>& h_vec1, const c2h::device_vector<ValueT>& d_vec2)
-{
-  c2h::device_vector<ValueT> d_vec1(h_vec1);
-  auto err = thrust::mismatch(
-    c2h::device_policy, d_vec1.cbegin(), d_vec1.cend(), d_vec2.cbegin(), fp_almost_equal_functor<ValueT>{});
-  if (err.first == d_vec1.cend() || err.second == d_vec2.cend())
-  {
-    return true;
-  }
-  else
-  {
-    c2h::host_vector<ValueT> h_vec2(d_vec2);
-    const auto idx = thrust::distance(d_vec1.cbegin(), err.first);
-    std::cerr << "Mismatch at position " << idx << ": " << print_cast(ValueT{h_vec1[idx]}) << " vs "
-              << print_cast(ValueT{h_vec2[idx]}) << std::endl;
-    return false;
-  }
-};
-
-template <typename ValueT>
-bool compare_results(
-  std::false_type /* is_fp */, const c2h::host_vector<ValueT>& h_vec1, const c2h::device_vector<ValueT>& d_vec2)
-{
-  c2h::device_vector<ValueT> d_vec1(h_vec1);
-  auto err = thrust::mismatch(c2h::device_policy, d_vec1.cbegin(), d_vec1.cend(), d_vec2.cbegin());
-  if (err.first == d_vec1.cend() || err.second == d_vec2.cend())
-  {
-    return true;
-  }
-  else
-  {
-    c2h::host_vector<ValueT> h_vec2(d_vec2);
-    const auto idx = thrust::distance(d_vec1.cbegin(), err.first);
-    std::cerr << "Mismatch at position " << idx << ": " << print_cast(ValueT{h_vec1[idx]}) << " vs "
-              << print_cast(ValueT{h_vec2[idx]}) << std::endl;
-    return false;
-  }
-}
-
-//==============================================================================
-// Generate a random host_csr_matrix<ValueT> with the specified dimensions.
-// target_fill_ratio is the target fraction of non-zero elements (may be more
-// or less in the output).
-template <typename ValueT>
-host_csr_matrix<ValueT> make_random_csr_matrix(int num_rows, int num_cols, float target_fill_ratio)
-{
-  host_csr_matrix<ValueT> mat{num_rows, num_cols};
-
-  for (int row = 0; row < num_rows; ++row)
-  {
-    for (int col = 0; col < num_cols; ++col)
-    {
-      const bool is_non_zero = RandomValue<float>(1.f) < target_fill_ratio;
-      if (!is_non_zero)
-      {
-        continue;
-      }
-
-      if (std::is_floating_point<ValueT>::value)
-      {
-        // Keep fp numbers somewhat small, from -50 -> 50; otherwise we run
-        // into issues with nans/infs
-        ValueT value = (RandomValue(static_cast<ValueT>(100)) - static_cast<ValueT>(50));
-        mat.append_value(row, col, value);
-      }
-      else
-      {
-        ValueT value{};
-        InitValue(RANDOM, value);
-        mat.append_value(row, col, value);
-      }
-    }
-  }
-
-  mat.finalize();
-
-  const int num_elements        = num_rows * num_cols;
-  const float actual_fill_ratio = static_cast<float>(mat.get_num_nonzeros()) / static_cast<float>(num_elements);
-
-  if (g_verbose)
-  {
-    printf(
-      "Created host_csr_matrix<%s>(%d, %d)\n"
-      " - NumElements: %d\n"
-      " - NumNonZero:  %d\n"
-      " - Target fill: %0.2f%%\n"
-      " - Actual fill: %0.2f%%\n",
-      typeid(ValueT).name(),
-      num_rows,
-      num_cols,
-      num_elements,
-      mat.get_num_nonzeros(),
-      target_fill_ratio,
-      actual_fill_ratio);
-  }
-
-  return mat;
-}
-
-//==============================================================================
-// Fill a vector with random values.
-template <typename ValueT>
-c2h::host_vector<ValueT> make_random_vector(int len)
-{
-  c2h::host_vector<ValueT> vec(len);
-  for (auto& val : vec)
-  {
-    if (std::is_floating_point<ValueT>::value)
-    { // Keep fp numbers somewhat small; otherwise we run into issues with
-      // nans/infs
-      val = RandomValue(static_cast<ValueT>(100)) - static_cast<ValueT>(50);
-    }
-    else
-    {
-      InitValue(RANDOM, val);
-    }
-  }
-  return vec;
-}
-
-//==============================================================================
-// Serial y = Ax computation
-template <typename ValueT>
-void compute_reference_solution(
-  const host_csr_matrix<ValueT>& a, const c2h::host_vector<ValueT>& x, c2h::host_vector<ValueT>& y)
-{
-  if (a.get_num_rows() == 0 || a.get_num_columns() == 0)
-  {
-    return;
-  }
-
-  for (int row = 0; row < a.get_num_rows(); ++row)
-  {
-    const int row_offset = a.get_row_offset(row);
-    const int row_length = a.get_row_num_nonzero(row);
-    const int* cols      = a.get_column_indices() + row_offset;
-    const int* cols_end  = cols + row_length;
-    const ValueT* values = a.get_values() + row_offset;
-
-    ValueT accum{};
-    while (cols < cols_end)
-    {
-      accum += (*values++) * x[*cols++];
-    }
-    y[row] = accum;
-  }
-}
-
-//==============================================================================
-// cub::DeviceSpmv::CsrMV y = Ax computation
-template <typename ValueT>
-void compute_cub_solution(
-  const device_csr_matrix<ValueT>& a, const c2h::device_vector<ValueT>& x, c2h::device_vector<ValueT>& y)
-{
-  c2h::device_vector<char> temp_storage;
-  std::size_t temp_storage_bytes{};
-  auto err = cub::DeviceSpmv::CsrMV(
-    nullptr,
-    temp_storage_bytes,
-    a.get_values(),
-    a.get_row_offsets(),
-    a.get_column_indices(),
-    thrust::raw_pointer_cast(x.data()),
-    thrust::raw_pointer_cast(y.data()),
-    a.get_num_rows(),
-    a.get_num_columns(),
-    a.get_num_nonzeros());
-  CubDebugExit(err);
-
-  temp_storage.resize(temp_storage_bytes);
-
-  err = cub::DeviceSpmv::CsrMV(
-    thrust::raw_pointer_cast(temp_storage.data()),
-    temp_storage_bytes,
-    a.get_values(),
-    a.get_row_offsets(),
-    a.get_column_indices(),
-    thrust::raw_pointer_cast(x.data()),
-    thrust::raw_pointer_cast(y.data()),
-    a.get_num_rows(),
-    a.get_num_columns(),
-    a.get_num_nonzeros());
-  CubDebugExit(err);
-}
-
-//==============================================================================
-// Compute y = Ax twice, one reference and one cub::DeviceSpmv, and compare the
-// results.
-template <typename ValueT>
-void test_spmv(const host_csr_matrix<ValueT>& h_a, const c2h::host_vector<ValueT>& h_x)
-{
-  if (g_verbose)
-  {
-    std::cout << "Testing cub::DeviceSpmv on inputs:\n";
-    h_a.print_internals(std::cout);
-    std::cout << "x vector:\n  [";
-    print_vector(std::cout, h_x);
-    std::cout << "]" << std::endl;
-  }
-  else
-  {
-    h_a.print_summary(std::cout);
-  }
-
-  const device_csr_matrix<ValueT> d_a(h_a);
-  const c2h::device_vector<ValueT> d_x(h_x);
-
-  c2h::host_vector<ValueT> h_y(h_a.get_num_rows());
-  c2h::device_vector<ValueT> d_y(d_a.get_num_rows());
-
-  compute_reference_solution(h_a, h_x, h_y);
-  compute_cub_solution(d_a, d_x, d_y);
-
-  if (g_verbose)
-  {
-    std::cout << "reference output:\n  [";
-    print_vector(std::cout, h_y);
-    std::cout << "]\n";
-    c2h::host_vector<ValueT> tmp_y(d_y);
-    std::cout << "cub::DeviceSpmv output:\n  [";
-    print_vector(std::cout, tmp_y);
-    std::cout << "]" << std::endl;
-  }
-
-  constexpr auto is_fp = std::is_floating_point<ValueT>{};
-  AssertTrue(compare_results(is_fp, h_y, d_y));
-}
-
-//==============================================================================
-// Test example from cub::DeviceSpmv documentation
-template <typename ValueT>
-void test_doc_example()
-{
-  std::cout << "\n\ntest_doc_example<" << typeid(ValueT).name() << ">()" << std::endl;
-
-  host_csr_matrix<ValueT> h_a(9, 9);
-  h_a.append_value(0, 1, ValueT{1});
-  h_a.append_value(0, 3, ValueT{1});
-  h_a.append_value(1, 0, ValueT{1});
-  h_a.append_value(1, 2, ValueT{1});
-  h_a.append_value(1, 4, ValueT{1});
-  h_a.append_value(2, 1, ValueT{1});
-  h_a.append_value(2, 5, ValueT{1});
-  h_a.append_value(3, 0, ValueT{1});
-  h_a.append_value(3, 4, ValueT{1});
-  h_a.append_value(3, 6, ValueT{1});
-  h_a.append_value(4, 1, ValueT{1});
-  h_a.append_value(4, 3, ValueT{1});
-  h_a.append_value(4, 5, ValueT{1});
-  h_a.append_value(4, 7, ValueT{1});
-  h_a.append_value(5, 2, ValueT{1});
-  h_a.append_value(5, 4, ValueT{1});
-  h_a.append_value(5, 8, ValueT{1});
-  h_a.append_value(6, 3, ValueT{1});
-  h_a.append_value(6, 7, ValueT{1});
-  h_a.append_value(7, 4, ValueT{1});
-  h_a.append_value(7, 6, ValueT{1});
-  h_a.append_value(7, 8, ValueT{1});
-  h_a.append_value(8, 5, ValueT{1});
-  h_a.append_value(8, 7, ValueT{1});
-  h_a.finalize();
-
-  c2h::host_vector<ValueT> h_x(9, ValueT{1});
-
-  test_spmv(h_a, h_x);
-}
-
-//==============================================================================
-// Generate and test a random SpMV operation with the given parameters.
-template <typename ValueT>
-void test_random(int rows, int cols, float target_fill_ratio)
-{
-  std::cout << "\n\ntest_random<" << typeid(ValueT).name() << ">(" << rows << ", " << cols << ", " << target_fill_ratio
-            << ")" << std::endl;
-
-  host_csr_matrix<ValueT> h_a  = make_random_csr_matrix<ValueT>(rows, cols, target_fill_ratio);
-  c2h::host_vector<ValueT> h_x = make_random_vector<ValueT>(cols);
-
-  test_spmv(h_a, h_x);
-}
-
-//==============================================================================
-// Dispatch many random SpMV tests over a variety of parameters.
-template <typename ValueT>
-void test_random()
-{
-  test_random<ValueT>(0, 0, 1.f);
-  test_random<ValueT>(0, 1, 1.f);
-  test_random<ValueT>(1, 0, 1.f);
-
-  constexpr int dim_min = 1;
-  constexpr int dim_max = 10000;
-
-  constexpr int max_num_elems = 100000;
-
-  constexpr float ratio_min  = 0.f;
-  constexpr float ratio_max  = 1.1f; // a lil over to account for fp errors
-  constexpr float ratio_step = 0.3334f;
-
-  for (int rows = dim_min; rows < dim_max; rows <<= 1)
-  {
-    for (int cols = dim_min; cols < dim_max; cols <<= 1)
-    {
-      if (rows * cols >= max_num_elems)
-      {
-        continue;
-      }
-
-      for (float ratio = ratio_min; ratio < ratio_max; ratio += ratio_step)
-      {
-        test_random<ValueT>(rows, cols, ratio);
-        // Test nearby non-power-of-two dims:
-        test_random<ValueT>(rows + 97, cols + 83, ratio);
-      }
-    }
-  }
-}
-
-//==============================================================================
-// Dispatch many SpMV tests for a given ValueT.
-template <typename ValueT>
-void test_type()
-{
-  test_doc_example<ValueT>();
-  test_random<ValueT>();
-}
-
-//==============================================================================
-// Dispatch many SpMV tests over a variety of types.
-void test_types()
-{
-  test_type<float>();
-  test_type<double>();
-  test_type<signed char>();
-  test_type<int>();
-  test_type<long long>();
-}
-
-int main(int argc, char** argv)
-{
-  // Initialize command line
-  CommandLineArgs args(argc, argv);
-  g_verbose = args.CheckCmdLineFlag("v");
-
-  // Print usage
-  if (args.CheckCmdLineFlag("help"))
-  {
-    printf("%s "
-           "[--device=<device-id>] "
-           "[--v] verbose"
-           "\n",
-           argv[0]);
-    exit(0);
-  }
-
-  CubDebugExit(args.DeviceInit());
-
-  test_types();
-}
-
-_CCCL_SUPPRESS_DEPRECATED_POP

From b6dd111f7ab213d14c41c3cd96c7e819683541bf Mon Sep 17 00:00:00 2001
From: Eric Niebler <eniebler@nvidia.com>
Date: Thu, 30 Jan 2025 11:01:23 -0800
Subject: [PATCH 27/33] work around erroneous "undefined in device code" error
 in `basic_any` (#3614)

---
 .../__utility/basic_any/virtcall.cuh          | 29 ++++++++++---------
 .../__utility/basic_any/virtual_functions.cuh |  4 +--
 2 files changed, 18 insertions(+), 15 deletions(-)

diff --git a/cudax/include/cuda/experimental/__utility/basic_any/virtcall.cuh b/cudax/include/cuda/experimental/__utility/basic_any/virtcall.cuh
index a51b36d29c9..e090e4b023c 100644
--- a/cudax/include/cuda/experimental/__utility/basic_any/virtcall.cuh
+++ b/cudax/include/cuda/experimental/__utility/basic_any/virtcall.cuh
@@ -22,6 +22,7 @@
 #endif // no system header
 
 #include <cuda/std/__concepts/concept_macros.h>
+#include <cuda/std/__type_traits/is_callable.h>
 
 #include <cuda/experimental/__utility/basic_any/access.cuh>
 #include <cuda/experimental/__utility/basic_any/basic_any_from.cuh>
@@ -60,19 +61,13 @@ namespace cuda::experimental
 //! except for the virtuals map, which substitutes the correct member function
 //! pointer for the user so they don't have to think about it.
 template <auto _Mbr, auto _BoundMbr>
-struct __virtuals_map_pair
+struct __virtuals_map_element
 {
   // map ifoo<>::meow to itself
-  _CCCL_NODISCARD _CUDAX_TRIVIAL_HOST_API constexpr auto operator()(__ctag<_Mbr>) const noexcept
-  {
-    return _Mbr;
-  }
+  auto operator()(__ctag<_Mbr>) const -> __virtual_fn<_Mbr>;
 
   // map ifoo<_Super>::meow to ifoo<>::meow
-  _CCCL_NODISCARD _CUDAX_TRIVIAL_HOST_API constexpr auto operator()(__ctag<_BoundMbr>) const noexcept
-  {
-    return _Mbr;
-  }
+  auto operator()(__ctag<_BoundMbr>) const -> __virtual_fn<_Mbr>;
 };
 
 template <class, class>
@@ -80,15 +75,23 @@ struct __virtuals_map;
 
 template <class _Interface, auto... _Mbrs, class _BoundInterface, auto... _BoundMbrs>
 struct __virtuals_map<overrides_for<_Interface, _Mbrs...>, overrides_for<_BoundInterface, _BoundMbrs...>>
-    : __virtuals_map_pair<_Mbrs, _BoundMbrs>...
+    : __virtuals_map_element<_Mbrs, _BoundMbrs>...
 {
-  using __virtuals_map_pair<_Mbrs, _BoundMbrs>::operator()...;
+  using __virtuals_map_element<_Mbrs, _BoundMbrs>::operator()...;
 };
 
 template <class _Interface, class _Super>
 using __virtuals_map_for _CCCL_NODEBUG_ALIAS =
   __virtuals_map<__overrides_for<_Interface>, __overrides_for<__rebind_interface<_Interface, _Super>>>;
 
+template <auto _Mbr, class _Interface, class _Super>
+extern _CUDA_VSTD::__call_result_t<__virtuals_map_for<_Interface, _Super>, __ctag<_Mbr>> __virtual_fn_for_v;
+
+// This alias indirects through the above variable template to cache the result
+// of the virtuals map lookup.
+template <auto _Mbr, class _Interface, class _Super>
+using __virtual_fn_for _CCCL_NODEBUG_ALIAS = decltype(__virtual_fn_for_v<_Mbr, _Interface, _Super>);
+
 //!
 //! virtcall
 //!
@@ -109,8 +112,8 @@ _CUDAX_HOST_API auto __virtcall(_Self* __self, _Args&&... __args) //
   auto* __vptr = __basic_any_access::__get_vptr(*__self)->__query_interface(_Interface());
   auto* __obj  = __basic_any_access::__get_optr(*__self);
   // map the member function pointer to the correct one if necessary
-  constexpr auto _Mbr2 = __virtuals_map_for<_Interface, _Super>{}(__ctag<_Mbr>());
-  return __vptr->__virtual_fn<_Mbr2>::__fn_(__obj, static_cast<_Args&&>(__args)...);
+  using __virtual_fn_t = __virtual_fn_for<_Mbr, _Interface, _Super>;
+  return __vptr->__virtual_fn_t::__fn_(__obj, static_cast<_Args&&>(__args)...);
 }
 
 _CCCL_TEMPLATE(auto _Mbr, template <class...> class _Interface, class _Super, class... _Args)
diff --git a/cudax/include/cuda/experimental/__utility/basic_any/virtual_functions.cuh b/cudax/include/cuda/experimental/__utility/basic_any/virtual_functions.cuh
index 32d7a77ebba..f31d396b608 100644
--- a/cudax/include/cuda/experimental/__utility/basic_any/virtual_functions.cuh
+++ b/cudax/include/cuda/experimental/__utility/basic_any/virtual_functions.cuh
@@ -64,8 +64,8 @@ _CUDAX_TRIVIAL_API auto __c_style_cast(_Src* __ptr) noexcept -> _DstPtr
 }
 
 template <class _Tp, auto _Fn, class _Ret, bool _IsConst, bool _IsNothrow, class... _Args>
-_CCCL_NODISCARD _CUDAX_API auto __override_fn_([[maybe_unused]] _CUDA_VSTD::__maybe_const<_IsConst, void>* __pv,
-                                               [[maybe_unused]] _Args... __args) noexcept(_IsNothrow) -> _Ret
+_CCCL_NODISCARD _CUDAX_HOST_API auto __override_fn_([[maybe_unused]] _CUDA_VSTD::__maybe_const<_IsConst, void>* __pv,
+                                                    [[maybe_unused]] _Args... __args) noexcept(_IsNothrow) -> _Ret
 {
   using __value_type _CCCL_NODEBUG_ALIAS = _CUDA_VSTD::__maybe_const<_IsConst, _Tp>;
 

From 73db01e1bb352a12ee46930644783bede3d6e3ed Mon Sep 17 00:00:00 2001
From: Federico Busato <50413820+fbusato@users.noreply.github.com>
Date: Thu, 30 Jan 2025 11:04:09 -0800
Subject: [PATCH 28/33] Deprecate `AgentSegmentFixupPolicy` (#3593)

---
 cub/cub/agent/agent_segment_fixup.cuh | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/cub/cub/agent/agent_segment_fixup.cuh b/cub/cub/agent/agent_segment_fixup.cuh
index 717b9b115e9..515b34d7c72 100644
--- a/cub/cub/agent/agent_segment_fixup.cuh
+++ b/cub/cub/agent/agent_segment_fixup.cuh
@@ -84,7 +84,8 @@ template <int _BLOCK_THREADS,
           BlockLoadAlgorithm _LOAD_ALGORITHM,
           CacheLoadModifier _LOAD_MODIFIER,
           BlockScanAlgorithm _SCAN_ALGORITHM>
-struct AgentSegmentFixupPolicy
+struct CCCL_DEPRECATED_BECAUSE("This class is considered an implementation detail and the public "
+                               "interface will be removed.") AgentSegmentFixupPolicy
 {
   enum
   {

From 0ecae0387712c0d7fb615b3e42b5c3811965d2f3 Mon Sep 17 00:00:00 2001
From: Wesley Maxey <71408887+wmaxey@users.noreply.github.com>
Date: Thu, 30 Jan 2025 11:46:28 -0800
Subject: [PATCH 29/33] Fix deadlocks by enabling eager module loading in
 libcudacxx tests. (#3585)

* Try using eager loading in lit to fix barrier deadlock

* Use override to limit testing

* Revert "Use override to limit testing"

This reverts commit 86edec483cbc74050db1d9364c494934d960a8eb.
---
 libcudacxx/test/utils/libcudacxx/test/config.py | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/libcudacxx/test/utils/libcudacxx/test/config.py b/libcudacxx/test/utils/libcudacxx/test/config.py
index af90b9fcbec..dbf7a84b73d 100644
--- a/libcudacxx/test/utils/libcudacxx/test/config.py
+++ b/libcudacxx/test/utils/libcudacxx/test/config.py
@@ -78,6 +78,7 @@ def __init__(self, lit_config, config):
         self.link_shared = self.get_lit_bool("enable_shared", default=True)
         self.debug_build = self.get_lit_bool("debug_build", default=False)
         self.exec_env = dict(os.environ)
+        self.exec_env["CUDA_MODULE_LOADING"] = "EAGER"
         self.use_target = False
         self.use_system_cxx_lib = False
         self.use_clang_verify = False
@@ -201,7 +202,8 @@ def get_modules_enabled(self):
     def make_static_lib_name(self, name):
         """Return the full filename for the specified library name"""
         if self.is_windows:
-            assert name == "c++"  # Only allow libc++ to use this function for now.
+            # Only allow libc++ to use this function for now.
+            assert name == "c++"
             return "lib" + name + ".lib"
         else:
             return "lib" + name + ".a"
@@ -308,7 +310,7 @@ def configure_cxx(self):
             cxx is not None and os.path.basename(cxx) == "clang-cl.exe"
         )
 
-        ## Build CXXCompiler manually for NVRTCC
+        # Build CXXCompiler manually for NVRTCC
         if nvrtc is True:
             cxx_type = "nvrtcc"
             self.cxx = CXXCompiler(
@@ -751,7 +753,7 @@ def configure_compile_flags(self):
             if compute_archs == "native":
                 compute_archs = self.get_compute_capabilities()
 
-            compute_archs = set(sorted(re.split("\s|;|,", compute_archs)))
+            compute_archs = set(sorted(re.split("\\s|;|,", compute_archs)))
             for s in compute_archs:
                 # Split arch and mode i.e. 80-virtual -> 80, virtual
                 arch, *mode = re.split("-", s)

From 51a890a86fdae2549c9e99f0b062ae954581aa0d Mon Sep 17 00:00:00 2001
From: Bernhard Manfred Gruber <bernhardmgruber@gmail.com>
Date: Thu, 30 Jan 2025 21:26:22 +0100
Subject: [PATCH 30/33] Add b200 tunings for histogram (#3616)

Co-authored-by: Giannis Gonidelis <ggonidelis@nvidia.com>
---
 .../device/dispatch/dispatch_histogram.cuh    |  42 +++-
 .../dispatch/tuning/tuning_histogram.cuh      | 186 +++++++++++++++++-
 2 files changed, 216 insertions(+), 12 deletions(-)

diff --git a/cub/cub/device/dispatch/dispatch_histogram.cuh b/cub/cub/device/dispatch/dispatch_histogram.cuh
index 2c2d0a2a9ca..43944dfc0b5 100644
--- a/cub/cub/device/dispatch/dispatch_histogram.cuh
+++ b/cub/cub/device/dispatch/dispatch_histogram.cuh
@@ -36,6 +36,8 @@
 
 #include <cub/config.cuh>
 
+#include <cuda/std/__type_traits/is_void.h>
+
 #if defined(_CCCL_IMPLICIT_SYSTEM_HEADER_GCC)
 #  pragma GCC system_header
 #elif defined(_CCCL_IMPLICIT_SYSTEM_HEADER_CLANG)
@@ -554,8 +556,7 @@ template <int NUM_CHANNELS,
           typename CounterT,
           typename LevelT,
           typename OffsetT,
-          typename PolicyHub =
-            detail::histogram::policy_hub<detail::value_t<SampleIteratorT>, CounterT, NUM_CHANNELS, NUM_ACTIVE_CHANNELS>>
+          typename PolicyHub = void> // if user passes a custom Policy this should not be void
 struct DispatchHistogram
 {
   static_assert(NUM_CHANNELS <= 4, "Histograms only support up to 4 channels");
@@ -920,8 +921,14 @@ public:
     cudaStream_t stream,
     Int2Type<false> /*is_byte_sample*/)
   {
-    using MaxPolicyT = typename PolicyHub::MaxPolicy;
-    cudaError error  = cudaSuccess;
+    // Should we call DispatchHistogram<....., PolicyHub=void> in DeviceHistogram?
+    static constexpr bool isEven = 0;
+    using fallback_policy_hub    = detail::histogram::
+      policy_hub<detail::value_t<SampleIteratorT>, CounterT, NUM_CHANNELS, NUM_ACTIVE_CHANNELS, isEven>;
+
+    using MaxPolicyT =
+      typename cuda::std::_If<cuda::std::is_void<PolicyHub>::value, fallback_policy_hub, PolicyHub>::MaxPolicy;
+    cudaError error = cudaSuccess;
 
     do
     {
@@ -1091,8 +1098,13 @@ public:
     cudaStream_t stream,
     Int2Type<true> /*is_byte_sample*/)
   {
-    using MaxPolicyT = typename PolicyHub::MaxPolicy;
-    cudaError error  = cudaSuccess;
+    static constexpr bool isEven = 0;
+    using fallback_policy_hub    = detail::histogram::
+      policy_hub<detail::value_t<SampleIteratorT>, CounterT, NUM_CHANNELS, NUM_ACTIVE_CHANNELS, isEven>;
+
+    using MaxPolicyT =
+      typename cuda::std::_If<cuda::std::is_void<PolicyHub>::value, fallback_policy_hub, PolicyHub>::MaxPolicy;
+    cudaError error = cudaSuccess;
 
     do
     {
@@ -1226,8 +1238,13 @@ public:
     cudaStream_t stream,
     Int2Type<false> /*is_byte_sample*/)
   {
-    using MaxPolicyT = typename PolicyHub::MaxPolicy;
-    cudaError error  = cudaSuccess;
+    static constexpr bool isEven = 1;
+    using fallback_policy_hub    = detail::histogram::
+      policy_hub<detail::value_t<SampleIteratorT>, CounterT, NUM_CHANNELS, NUM_ACTIVE_CHANNELS, isEven>;
+
+    using MaxPolicyT =
+      typename cuda::std::_If<cuda::std::is_void<PolicyHub>::value, fallback_policy_hub, PolicyHub>::MaxPolicy;
+    cudaError error = cudaSuccess;
 
     do
     {
@@ -1412,8 +1429,13 @@ public:
     cudaStream_t stream,
     Int2Type<true> /*is_byte_sample*/)
   {
-    using MaxPolicyT = typename PolicyHub::MaxPolicy;
-    cudaError error  = cudaSuccess;
+    static constexpr bool isEven = 1;
+    using fallback_policy_hub    = detail::histogram::
+      policy_hub<detail::value_t<SampleIteratorT>, CounterT, NUM_CHANNELS, NUM_ACTIVE_CHANNELS, isEven>;
+
+    using MaxPolicyT =
+      typename cuda::std::_If<cuda::std::is_void<PolicyHub>::value, fallback_policy_hub, PolicyHub>::MaxPolicy;
+    cudaError error = cudaSuccess;
 
     do
     {
diff --git a/cub/cub/device/dispatch/tuning/tuning_histogram.cuh b/cub/cub/device/dispatch/tuning/tuning_histogram.cuh
index bd19489971e..3ae3f7fc58a 100644
--- a/cub/cub/device/dispatch/tuning/tuning_histogram.cuh
+++ b/cub/cub/device/dispatch/tuning/tuning_histogram.cuh
@@ -60,6 +60,8 @@ enum class sample_size
 {
   _1,
   _2,
+  _4,
+  _8,
   unknown
 };
 
@@ -125,7 +127,164 @@ struct sm90_tuning<SampleT, 1, 1, counter_size::_4, primitive_sample::yes, sampl
   static constexpr bool work_stealing = false;
 };
 
-template <class SampleT, class CounterT, int NumChannels, int NumActiveChannels>
+template <bool IsEven,
+          class SampleT,
+          int NumChannels,
+          int NumActiveChannels,
+          counter_size CounterSize,
+          primitive_sample PrimitiveSample = is_primitive_sample<SampleT>(),
+          sample_size SampleSize           = classify_sample_size<SampleT>()>
+struct sm100_tuning;
+
+// even
+template <class SampleT>
+struct sm100_tuning<1, SampleT, 1, 1, counter_size::_4, primitive_sample::yes, sample_size::_1>
+{
+  // ipt_12.tpb_928.rle_0.ws_0.mem_1.ld_2.laid_0.vec_2 1.033332  0.940517  1.031835  1.195876
+  static constexpr int items                                     = 12;
+  static constexpr int threads                                   = 928;
+  static constexpr bool rle_compress                             = false;
+  static constexpr bool work_stealing                            = false;
+  static constexpr BlockHistogramMemoryPreference mem_preference = SMEM;
+  static constexpr CacheLoadModifier load_modifier               = LOAD_CA;
+  static constexpr BlockLoadAlgorithm load_algorithm             = BLOCK_LOAD_DIRECT;
+  static constexpr int tune_vec_size                             = 1 << 2;
+};
+
+// same as base
+template <class SampleT>
+struct sm100_tuning<1, SampleT, 1, 1, counter_size::_4, primitive_sample::yes, sample_size::_2>
+    : sm90_tuning<SampleT, 1, 1, counter_size::_4, primitive_sample::yes, sample_size::_2>
+{};
+
+// same as base
+template <class SampleT>
+struct sm100_tuning<1, SampleT, 1, 1, counter_size::_4, primitive_sample::yes, sample_size::_4>
+    : sm90_tuning<SampleT, 1, 1, counter_size::_4, primitive_sample::yes, sample_size::_4>
+{};
+
+// same as base
+template <class SampleT>
+struct sm100_tuning<1, SampleT, 1, 1, counter_size::_4, primitive_sample::yes, sample_size::_8>
+    : sm90_tuning<SampleT, 1, 1, counter_size::_4, primitive_sample::yes, sample_size::_8>
+{};
+
+// range
+template <class SampleT>
+struct sm100_tuning<0, SampleT, 1, 1, counter_size::_4, primitive_sample::yes, sample_size::_1>
+{
+  // ipt_12.tpb_448.rle_0.ws_0.mem_1.ld_1.laid_0.vec_2 1.078987  0.985542  1.085118  1.175637
+  static constexpr int items                                     = 12;
+  static constexpr int threads                                   = 448;
+  static constexpr bool rle_compress                             = false;
+  static constexpr bool work_stealing                            = false;
+  static constexpr BlockHistogramMemoryPreference mem_preference = SMEM;
+  static constexpr CacheLoadModifier load_modifier               = LOAD_LDG;
+  static constexpr BlockLoadAlgorithm load_algorithm             = BLOCK_LOAD_DIRECT;
+  static constexpr int tune_vec_size                             = 1 << 2;
+};
+
+// same as base
+template <class SampleT>
+struct sm100_tuning<0, SampleT, 1, 1, counter_size::_4, primitive_sample::yes, sample_size::_2>
+    : sm90_tuning<SampleT, 1, 1, counter_size::_4, primitive_sample::yes, sample_size::_2>
+{};
+
+template <class SampleT>
+struct sm100_tuning<0, SampleT, 1, 1, counter_size::_4, primitive_sample::yes, sample_size::_4>
+{
+  // ipt_9.tpb_1024.rle_1.ws_0.mem_1.ld_0.laid_1.vec_0 1.358537  1.001009  1.373329  2.614104
+  static constexpr int items                                     = 9;
+  static constexpr int threads                                   = 1024;
+  static constexpr bool rle_compress                             = true;
+  static constexpr bool work_stealing                            = false;
+  static constexpr BlockHistogramMemoryPreference mem_preference = SMEM;
+  static constexpr CacheLoadModifier load_modifier               = LOAD_DEFAULT;
+  static constexpr BlockLoadAlgorithm load_algorithm             = BLOCK_LOAD_WARP_TRANSPOSE;
+  static constexpr int tune_vec_size                             = 1 << 0;
+};
+
+template <class SampleT>
+struct sm100_tuning<0, SampleT, 1, 1, counter_size::_4, primitive_sample::yes, sample_size::_8>
+{
+  // ipt_7.tpb_544.rle_1.ws_0.mem_1.ld_1.laid_0.vec_0 1.105331  0.934888  1.108557  1.391657
+  static constexpr int items                                     = 7;
+  static constexpr int threads                                   = 544;
+  static constexpr bool rle_compress                             = true;
+  static constexpr bool work_stealing                            = false;
+  static constexpr BlockHistogramMemoryPreference mem_preference = SMEM;
+  static constexpr CacheLoadModifier load_modifier               = LOAD_LDG;
+  static constexpr BlockLoadAlgorithm load_algorithm             = BLOCK_LOAD_DIRECT;
+  static constexpr int tune_vec_size                             = 1 << 0;
+};
+
+// multi.even
+template <class SampleT>
+struct sm100_tuning<1, SampleT, 4, 3, counter_size::_4, primitive_sample::yes, sample_size::_1>
+{
+  // ipt_9.tpb_1024.rle_0.ws_0.mem_1.ld_1.laid_1.vec_0 1.629591  0.997416  1.570900  2.772504
+  static constexpr int items                                     = 9;
+  static constexpr int threads                                   = 1024;
+  static constexpr bool rle_compress                             = false;
+  static constexpr bool work_stealing                            = false;
+  static constexpr BlockHistogramMemoryPreference mem_preference = SMEM;
+  static constexpr CacheLoadModifier load_modifier               = LOAD_LDG;
+  static constexpr BlockLoadAlgorithm load_algorithm             = BLOCK_LOAD_WARP_TRANSPOSE;
+  static constexpr int tune_vec_size                             = 1 << 0;
+};
+
+// same as base
+template <class SampleT>
+struct sm100_tuning<1, SampleT, 4, 3, counter_size::_4, primitive_sample::yes, sample_size::_2>
+    : sm90_tuning<SampleT, 1, 1, counter_size::_4, primitive_sample::yes, sample_size::_2>
+{};
+
+// same as base
+template <class SampleT>
+struct sm100_tuning<1, SampleT, 4, 3, counter_size::_4, primitive_sample::yes, sample_size::_4>
+    : sm90_tuning<SampleT, 1, 1, counter_size::_4, primitive_sample::yes, sample_size::_4>
+{};
+
+// same as base
+template <class SampleT>
+struct sm100_tuning<1, SampleT, 4, 3, counter_size::_4, primitive_sample::yes, sample_size::_8>
+    : sm90_tuning<SampleT, 1, 1, counter_size::_4, primitive_sample::yes, sample_size::_8>
+{};
+
+// multi.range
+template <class SampleT>
+struct sm100_tuning<0, SampleT, 4, 3, counter_size::_4, primitive_sample::yes, sample_size::_1>
+{
+  // ipt_7.tpb_160.rle_0.ws_0.mem_1.ld_1.laid_1.vec_1 1.210837  0.99556  1.189049  1.939584
+  static constexpr int items                                     = 7;
+  static constexpr int threads                                   = 160;
+  static constexpr bool rle_compress                             = false;
+  static constexpr bool work_stealing                            = false;
+  static constexpr BlockHistogramMemoryPreference mem_preference = SMEM;
+  static constexpr CacheLoadModifier load_modifier               = LOAD_LDG;
+  static constexpr BlockLoadAlgorithm load_algorithm             = BLOCK_LOAD_WARP_TRANSPOSE;
+  static constexpr int tune_vec_size                             = 1 << 1;
+};
+
+// same as base
+template <class SampleT>
+struct sm100_tuning<0, SampleT, 4, 3, counter_size::_4, primitive_sample::yes, sample_size::_2>
+    : sm90_tuning<SampleT, 1, 1, counter_size::_4, primitive_sample::yes, sample_size::_2>
+{};
+
+// same as base
+template <class SampleT>
+struct sm100_tuning<0, SampleT, 4, 3, counter_size::_4, primitive_sample::yes, sample_size::_4>
+    : sm90_tuning<SampleT, 1, 1, counter_size::_4, primitive_sample::yes, sample_size::_4>
+{};
+
+// same as base
+template <class SampleT>
+struct sm100_tuning<0, SampleT, 4, 3, counter_size::_4, primitive_sample::yes, sample_size::_8>
+    : sm90_tuning<SampleT, 1, 1, counter_size::_4, primitive_sample::yes, sample_size::_8>
+{};
+
+template <class SampleT, class CounterT, int NumChannels, int NumActiveChannels, bool IsEven>
 struct policy_hub
 {
   // TODO(bgruber): move inside t_scale in C++14
@@ -166,7 +325,30 @@ struct policy_hub
                sm90_tuning<SampleT, NumChannels, NumActiveChannels, histogram::classify_counter_size<CounterT>()>>(0));
   };
 
-  using MaxPolicy = Policy900;
+  struct Policy1000 : ChainedPolicy<1000, Policy1000, Policy900>
+  {
+    // Use values from tuning if a specialization exists, otherwise pick Policy900
+    template <typename Tuning>
+    static auto select_agent_policy(int)
+      -> AgentHistogramPolicy<Tuning::threads,
+                              Tuning::items,
+                              Tuning::load_algorithm,
+                              Tuning::load_modifier,
+                              Tuning::rle_compress,
+                              Tuning::mem_preference,
+                              Tuning::work_stealing,
+                              Tuning::vec_size>;
+
+    template <typename Tuning>
+    static auto select_agent_policy(long) -> typename Policy900::AgentHistogramPolicyT;
+
+    using AgentHistogramPolicyT =
+      decltype(select_agent_policy<
+               sm100_tuning<IsEven, SampleT, NumChannels, NumActiveChannels, histogram::classify_counter_size<CounterT>()>>(
+        0));
+  };
+
+  using MaxPolicy = Policy1000;
 };
 } // namespace histogram
 } // namespace detail

From 0ce59c7f3eb8b6d92fee4c88065dacebe2864b87 Mon Sep 17 00:00:00 2001
From: Eric Niebler <eniebler@nvidia.com>
Date: Thu, 30 Jan 2025 12:34:04 -0800
Subject: [PATCH 31/33] make `uninitialized[_async]_buffer`'s range accessors
 const-correct (#3615)

---
 .../uninitialized_async_buffer.cuh            | 36 ++++++++++++++-----
 .../__container/uninitialized_buffer.cuh      | 36 ++++++++++++++-----
 .../containers/uninitialized_async_buffer.cu  |  6 ++++
 cudax/test/containers/uninitialized_buffer.cu |  6 ++++
 4 files changed, 68 insertions(+), 16 deletions(-)

diff --git a/cudax/include/cuda/experimental/__container/uninitialized_async_buffer.cuh b/cudax/include/cuda/experimental/__container/uninitialized_async_buffer.cuh
index 3f55084dc63..e66b7bf2ac3 100644
--- a/cudax/include/cuda/experimental/__container/uninitialized_async_buffer.cuh
+++ b/cudax/include/cuda/experimental/__container/uninitialized_async_buffer.cuh
@@ -108,7 +108,7 @@ private:
     size_t __space               = __get_allocation_size(__count_);
     void* __ptr                  = __buf_;
     return _CUDA_VSTD::launder(
-      reinterpret_cast<_Tp*>(_CUDA_VSTD::align(__alignment, __count_ * sizeof(_Tp), __ptr, __space)));
+      static_cast<_Tp*>(_CUDA_VSTD::align(__alignment, __count_ * sizeof(_Tp), __ptr, __space)));
   }
 
   //! @brief Causes the buffer to be treated as a span when passed to cudax::launch.
@@ -136,10 +136,12 @@ private:
   }
 
 public:
-  using value_type = _Tp;
-  using reference  = _Tp&;
-  using pointer    = _Tp*;
-  using size_type  = size_t;
+  using value_type      = _Tp;
+  using reference       = _Tp&;
+  using const_reference = const _Tp&;
+  using pointer         = _Tp*;
+  using const_pointer   = const _Tp*;
+  using size_type       = size_t;
 
   //! @brief Constructs an \c uninitialized_async_buffer, allocating sufficient storage for \p __count elements through
   //! \p __mr
@@ -215,20 +217,38 @@ public:
   }
 
   //! @brief Returns an aligned pointer to the first element in the buffer
-  _CCCL_NODISCARD _CCCL_HIDE_FROM_ABI constexpr pointer begin() const noexcept
+  _CCCL_NODISCARD _CCCL_HIDE_FROM_ABI constexpr pointer begin() noexcept
+  {
+    return __get_data();
+  }
+
+  //! @overload
+  _CCCL_NODISCARD _CCCL_HIDE_FROM_ABI constexpr const_pointer begin() const noexcept
   {
     return __get_data();
   }
 
   //! @brief Returns an aligned pointer to the element following the last element of the buffer.
   //! This element acts as a placeholder; attempting to access it results in undefined behavior.
-  _CCCL_NODISCARD _CCCL_HIDE_FROM_ABI constexpr pointer end() const noexcept
+  _CCCL_NODISCARD _CCCL_HIDE_FROM_ABI constexpr pointer end() noexcept
+  {
+    return __get_data() + __count_;
+  }
+
+  //! @overload
+  _CCCL_NODISCARD _CCCL_HIDE_FROM_ABI constexpr const_pointer end() const noexcept
   {
     return __get_data() + __count_;
   }
 
   //! @brief Returns an aligned pointer to the first element in the buffer
-  _CCCL_NODISCARD _CCCL_HIDE_FROM_ABI constexpr pointer data() const noexcept
+  _CCCL_NODISCARD _CCCL_HIDE_FROM_ABI constexpr pointer data() noexcept
+  {
+    return __get_data();
+  }
+
+  //! @overload
+  _CCCL_NODISCARD _CCCL_HIDE_FROM_ABI constexpr const_pointer data() const noexcept
   {
     return __get_data();
   }
diff --git a/cudax/include/cuda/experimental/__container/uninitialized_buffer.cuh b/cudax/include/cuda/experimental/__container/uninitialized_buffer.cuh
index 55168b38805..edf17e70865 100644
--- a/cudax/include/cuda/experimental/__container/uninitialized_buffer.cuh
+++ b/cudax/include/cuda/experimental/__container/uninitialized_buffer.cuh
@@ -98,7 +98,7 @@ private:
     size_t __space               = __get_allocation_size(__count_);
     void* __ptr                  = __buf_;
     return _CUDA_VSTD::launder(
-      reinterpret_cast<_Tp*>(_CUDA_VSTD::align(__alignment, __count_ * sizeof(_Tp), __ptr, __space)));
+      static_cast<_Tp*>(_CUDA_VSTD::align(__alignment, __count_ * sizeof(_Tp), __ptr, __space)));
   }
 
   //! @brief Causes the buffer to be treated as a span when passed to cudax::launch.
@@ -124,10 +124,12 @@ private:
   }
 
 public:
-  using value_type = _Tp;
-  using reference  = _Tp&;
-  using pointer    = _Tp*;
-  using size_type  = size_t;
+  using value_type      = _Tp;
+  using reference       = _Tp&;
+  using const_reference = const _Tp&;
+  using pointer         = _Tp*;
+  using const_pointer   = const _Tp*;
+  using size_type       = size_t;
 
   //! @brief Constructs an \c uninitialized_buffer and allocates sufficient storage for \p __count elements through
   //! \p __mr
@@ -198,20 +200,38 @@ public:
   }
 
   //! @brief Returns an aligned pointer to the first element in the buffer
-  _CCCL_NODISCARD _CCCL_HIDE_FROM_ABI pointer begin() const noexcept
+  _CCCL_NODISCARD _CCCL_HIDE_FROM_ABI pointer begin() noexcept
+  {
+    return __get_data();
+  }
+
+  //! @overload
+  _CCCL_NODISCARD _CCCL_HIDE_FROM_ABI const_pointer begin() const noexcept
   {
     return __get_data();
   }
 
   //! @brief Returns an aligned pointer to the element following the last element of the buffer.
   //! This element acts as a placeholder; attempting to access it results in undefined behavior.
-  _CCCL_NODISCARD _CCCL_HIDE_FROM_ABI pointer end() const noexcept
+  _CCCL_NODISCARD _CCCL_HIDE_FROM_ABI pointer end() noexcept
+  {
+    return __get_data() + __count_;
+  }
+
+  //! @overload
+  _CCCL_NODISCARD _CCCL_HIDE_FROM_ABI const_pointer end() const noexcept
   {
     return __get_data() + __count_;
   }
 
   //! @brief Returns an aligned pointer to the first element in the buffer
-  _CCCL_NODISCARD _CCCL_HIDE_FROM_ABI pointer data() const noexcept
+  _CCCL_NODISCARD _CCCL_HIDE_FROM_ABI pointer data() noexcept
+  {
+    return __get_data();
+  }
+
+  //! @overload
+  _CCCL_NODISCARD _CCCL_HIDE_FROM_ABI const_pointer data() const noexcept
   {
     return __get_data();
   }
diff --git a/cudax/test/containers/uninitialized_async_buffer.cu b/cudax/test/containers/uninitialized_async_buffer.cu
index 392f5fb2944..4e57bf7c1c7 100644
--- a/cudax/test/containers/uninitialized_async_buffer.cu
+++ b/cudax/test/containers/uninitialized_async_buffer.cu
@@ -137,6 +137,9 @@ TEMPLATE_TEST_CASE(
   SECTION("access")
   {
     uninitialized_async_buffer buf{resource, stream, 42};
+    static_assert(cuda::std::is_same<decltype(buf.begin()), TestType*>::value, "");
+    static_assert(cuda::std::is_same<decltype(buf.end()), TestType*>::value, "");
+    static_assert(cuda::std::is_same<decltype(buf.data()), TestType*>::value, "");
     CUDAX_CHECK(buf.data() != nullptr);
     CUDAX_CHECK(buf.size() == 42);
     CUDAX_CHECK(buf.size_bytes() == 42 * sizeof(TestType));
@@ -145,6 +148,9 @@ TEMPLATE_TEST_CASE(
     CUDAX_CHECK(buf.get_stream() == stream);
     CUDAX_CHECK(buf.get_memory_resource() == resource);
 
+    static_assert(cuda::std::is_same<decltype(cuda::std::as_const(buf).begin()), TestType const*>::value, "");
+    static_assert(cuda::std::is_same<decltype(cuda::std::as_const(buf).end()), TestType const*>::value, "");
+    static_assert(cuda::std::is_same<decltype(cuda::std::as_const(buf).data()), TestType const*>::value, "");
     CUDAX_CHECK(cuda::std::as_const(buf).data() != nullptr);
     CUDAX_CHECK(cuda::std::as_const(buf).size() == 42);
     CUDAX_CHECK(cuda::std::as_const(buf).size_bytes() == 42 * sizeof(TestType));
diff --git a/cudax/test/containers/uninitialized_buffer.cu b/cudax/test/containers/uninitialized_buffer.cu
index 3e5c48c0eff..1aa8f467d8a 100644
--- a/cudax/test/containers/uninitialized_buffer.cu
+++ b/cudax/test/containers/uninitialized_buffer.cu
@@ -155,6 +155,9 @@ TEMPLATE_TEST_CASE(
   SECTION("access")
   {
     uninitialized_buffer buf{resource, 42};
+    static_assert(cuda::std::is_same<decltype(buf.begin()), TestType*>::value, "");
+    static_assert(cuda::std::is_same<decltype(buf.end()), TestType*>::value, "");
+    static_assert(cuda::std::is_same<decltype(buf.data()), TestType*>::value, "");
     CUDAX_CHECK(buf.data() != nullptr);
     CUDAX_CHECK(buf.size() == 42);
     CUDAX_CHECK(buf.size_bytes() == 42 * sizeof(TestType));
@@ -162,6 +165,9 @@ TEMPLATE_TEST_CASE(
     CUDAX_CHECK(buf.end() == buf.begin() + buf.size());
     CUDAX_CHECK(buf.get_memory_resource() == resource);
 
+    static_assert(cuda::std::is_same<decltype(cuda::std::as_const(buf).begin()), TestType const*>::value, "");
+    static_assert(cuda::std::is_same<decltype(cuda::std::as_const(buf).end()), TestType const*>::value, "");
+    static_assert(cuda::std::is_same<decltype(cuda::std::as_const(buf).data()), TestType const*>::value, "");
     CUDAX_CHECK(cuda::std::as_const(buf).data() != nullptr);
     CUDAX_CHECK(cuda::std::as_const(buf).size() == 42);
     CUDAX_CHECK(cuda::std::as_const(buf).begin() == buf.data());

From 77a6a45c7ea6e46bf127cfe466ce973c5a675a87 Mon Sep 17 00:00:00 2001
From: Federico Busato <50413820+fbusato@users.noreply.github.com>
Date: Thu, 30 Jan 2025 12:51:37 -0800
Subject: [PATCH 32/33] Remove `LEGACY_PTX_ARCH` (#3551)

---
 cub/cub/agent/agent_batch_memcpy.cuh          |  2 --
 cub/cub/agent/agent_histogram.cuh             | 12 +++-------
 cub/cub/agent/agent_reduce_by_key.cuh         |  2 +-
 cub/cub/agent/agent_rle.cuh                   |  2 +-
 cub/cub/agent/agent_scan.cuh                  |  2 +-
 cub/cub/agent/agent_scan_by_key.cuh           |  2 +-
 cub/cub/agent/agent_select_if.cuh             |  2 +-
 cub/cub/agent/agent_three_way_partition.cuh   |  2 +-
 cub/cub/agent/agent_unique_by_key.cuh         |  5 ++---
 cub/cub/agent/single_pass_scan_operators.cuh  |  1 -
 cub/cub/block/block_adjacent_difference.cuh   |  2 +-
 cub/cub/block/block_discontinuity.cuh         |  4 +---
 cub/cub/block/block_exchange.cuh              |  5 +----
 cub/cub/block/block_histogram.cuh             |  5 +----
 cub/cub/block/block_load.cuh                  |  5 +----
 cub/cub/block/block_radix_rank.cuh            |  8 ++-----
 cub/cub/block/block_radix_sort.cuh            |  5 +----
 cub/cub/block/block_raking_layout.cuh         |  4 +---
 cub/cub/block/block_reduce.cuh                |  5 +----
 cub/cub/block/block_scan.cuh                  |  5 +----
 cub/cub/block/block_shuffle.cuh               |  4 +---
 cub/cub/block/block_store.cuh                 |  5 +----
 .../specializations/block_histogram_sort.cuh  | 22 +++----------------
 .../specializations/block_reduce_raking.cuh   |  9 +++-----
 .../block_reduce_raking_commutative_only.cuh  |  9 +++-----
 .../block_reduce_warp_reductions.cuh          |  9 +++-----
 .../specializations/block_scan_raking.cuh     |  9 +++-----
 .../specializations/block_scan_warp_scans.cuh |  9 +++-----
 cub/cub/util_ptx.cuh                          |  2 +-
 .../warp/specializations/warp_reduce_shfl.cuh |  9 +++-----
 .../warp/specializations/warp_reduce_smem.cuh |  9 +++-----
 .../warp/specializations/warp_scan_shfl.cuh   |  9 +++-----
 .../warp/specializations/warp_scan_smem.cuh   |  9 +++-----
 cub/cub/warp/warp_exchange.cuh                |  4 ----
 cub/cub/warp/warp_load.cuh                    |  5 +----
 cub/cub/warp/warp_merge_sort.cuh              |  9 +-------
 cub/cub/warp/warp_reduce.cuh                  |  8 +++----
 cub/cub/warp/warp_scan.cuh                    |  4 +---
 cub/cub/warp/warp_store.cuh                   |  5 +----
 cub/test/catch2_test_warp_exchange.cuh        | 12 +++++-----
 docs/cub/developer_overview.rst               | 18 ++++++---------
 thrust/thrust/system/cuda/detail/core/util.h  |  9 +-------
 thrust/thrust/system/cuda/detail/reduce.h     |  2 +-
 .../thrust/system/cuda/detail/reduce_by_key.h |  8 +++----
 .../system/cuda/detail/set_operations.h       |  4 ++--
 thrust/thrust/system/cuda/detail/unique.h     |  6 ++---
 46 files changed, 85 insertions(+), 203 deletions(-)

diff --git a/cub/cub/agent/agent_batch_memcpy.cuh b/cub/cub/agent/agent_batch_memcpy.cuh
index 2b926f582fe..c2cf936bd87 100644
--- a/cub/cub/agent/agent_batch_memcpy.cuh
+++ b/cub/cub/agent/agent_batch_memcpy.cuh
@@ -642,14 +642,12 @@ private:
     TilePrefixCallbackOp<BufferOffsetT,
                          ::cuda::std::plus<>,
                          BLevBufferOffsetTileState,
-                         0,
                          typename AgentMemcpySmallBuffersPolicyT::buff_delay_constructor>;
 
   using BLevBlockScanPrefixCallbackOpT =
     TilePrefixCallbackOp<BlockOffsetT,
                          ::cuda::std::plus<>,
                          BLevBlockOffsetTileState,
-                         0,
                          typename AgentMemcpySmallBuffersPolicyT::block_delay_constructor>;
 
   //-----------------------------------------------------------------------------
diff --git a/cub/cub/agent/agent_histogram.cuh b/cub/cub/agent/agent_histogram.cuh
index 2e98bf76771..400d1778b11 100644
--- a/cub/cub/agent/agent_histogram.cuh
+++ b/cub/cub/agent/agent_histogram.cuh
@@ -172,9 +172,6 @@ namespace histogram
  *
  * @tparam OffsetT
  *   Signed integer type for global offsets
- *
- * @tparam LEGACY_PTX_ARCH
- *   PTX compute capability (unused)
  */
 template <typename AgentHistogramPolicyT,
           int PRIVATIZED_SMEM_BINS,
@@ -184,8 +181,7 @@ template <typename AgentHistogramPolicyT,
           typename CounterT,
           typename PrivatizedDecodeOpT,
           typename OutputDecodeOpT,
-          typename OffsetT,
-          int LEGACY_PTX_ARCH = 0>
+          typename OffsetT>
 struct AgentHistogram
 {
   //---------------------------------------------------------------------
@@ -930,8 +926,7 @@ template <typename AgentHistogramPolicyT,
           typename CounterT,
           typename PrivatizedDecodeOpT,
           typename OutputDecodeOpT,
-          typename OffsetT,
-          int LEGACY_PTX_ARCH = 0>
+          typename OffsetT>
 using AgentHistogram CCCL_DEPRECATED_BECAUSE("This class is considered an implementation detail and the public "
                                              "interface will be removed.") =
   detail::histogram::AgentHistogram<
@@ -943,7 +938,6 @@ using AgentHistogram CCCL_DEPRECATED_BECAUSE("This class is considered an implem
     CounterT,
     PrivatizedDecodeOpT,
     OutputDecodeOpT,
-    OffsetT,
-    LEGACY_PTX_ARCH>;
+    OffsetT>;
 
 CUB_NAMESPACE_END
diff --git a/cub/cub/agent/agent_reduce_by_key.cuh b/cub/cub/agent/agent_reduce_by_key.cuh
index a90399f4325..fffa5a88e57 100644
--- a/cub/cub/agent/agent_reduce_by_key.cuh
+++ b/cub/cub/agent/agent_reduce_by_key.cuh
@@ -276,7 +276,7 @@ struct AgentReduceByKey
   // Callback type for obtaining tile prefix during block scan
   using DelayConstructorT = typename AgentReduceByKeyPolicyT::detail::delay_constructor_t;
   using TilePrefixCallbackOpT =
-    TilePrefixCallbackOp<OffsetValuePairT, ReduceBySegmentOpT, ScanTileStateT, 0, DelayConstructorT>;
+    TilePrefixCallbackOp<OffsetValuePairT, ReduceBySegmentOpT, ScanTileStateT, DelayConstructorT>;
 
   // Key and value exchange types
   using KeyExchangeT   = KeyOutputT[TILE_ITEMS + 1];
diff --git a/cub/cub/agent/agent_rle.cuh b/cub/cub/agent/agent_rle.cuh
index 2ea0729db92..fabc0b721ae 100644
--- a/cub/cub/agent/agent_rle.cuh
+++ b/cub/cub/agent/agent_rle.cuh
@@ -258,7 +258,7 @@ struct AgentRle
   // Callback type for obtaining tile prefix during block scan
   using DelayConstructorT = typename AgentRlePolicyT::detail::delay_constructor_t;
   using TilePrefixCallbackOpT =
-    TilePrefixCallbackOp<LengthOffsetPair, ReduceBySegmentOpT, ScanTileStateT, 0, DelayConstructorT>;
+    TilePrefixCallbackOp<LengthOffsetPair, ReduceBySegmentOpT, ScanTileStateT, DelayConstructorT>;
 
   // Warp exchange types
   using WarpExchangePairs = WarpExchange<LengthOffsetPair, ITEMS_PER_THREAD>;
diff --git a/cub/cub/agent/agent_scan.cuh b/cub/cub/agent/agent_scan.cuh
index c3cc02b69a1..9f29615a5cd 100644
--- a/cub/cub/agent/agent_scan.cuh
+++ b/cub/cub/agent/agent_scan.cuh
@@ -201,7 +201,7 @@ struct AgentScan
 
   // Callback type for obtaining tile prefix during block scan
   using DelayConstructorT     = typename AgentScanPolicyT::detail::delay_constructor_t;
-  using TilePrefixCallbackOpT = TilePrefixCallbackOp<AccumT, ScanOpT, ScanTileStateT, 0 /* PTX */, DelayConstructorT>;
+  using TilePrefixCallbackOpT = TilePrefixCallbackOp<AccumT, ScanOpT, ScanTileStateT, DelayConstructorT>;
 
   // Stateful BlockScan prefix callback type for managing a running total while
   // scanning consecutive tiles
diff --git a/cub/cub/agent/agent_scan_by_key.cuh b/cub/cub/agent/agent_scan_by_key.cuh
index 722a44ac074..161a8a5c237 100644
--- a/cub/cub/agent/agent_scan_by_key.cuh
+++ b/cub/cub/agent/agent_scan_by_key.cuh
@@ -179,7 +179,7 @@ struct AgentScanByKey
 
   using DelayConstructorT = typename AgentScanByKeyPolicyT::detail::delay_constructor_t;
   using TilePrefixCallbackT =
-    TilePrefixCallbackOp<FlagValuePairT, ReduceBySegmentOpT, ScanTileStateT, 0, DelayConstructorT>;
+    TilePrefixCallbackOp<FlagValuePairT, ReduceBySegmentOpT, ScanTileStateT, DelayConstructorT>;
 
   using BlockScanT = BlockScan<FlagValuePairT, BLOCK_THREADS, AgentScanByKeyPolicyT::SCAN_ALGORITHM, 1, 1>;
 
diff --git a/cub/cub/agent/agent_select_if.cuh b/cub/cub/agent/agent_select_if.cuh
index 37e7b838adf..b1785651f12 100644
--- a/cub/cub/agent/agent_select_if.cuh
+++ b/cub/cub/agent/agent_select_if.cuh
@@ -274,7 +274,7 @@ struct AgentSelectIf
   // Callback type for obtaining tile prefix during block scan
   using DelayConstructorT = typename AgentSelectIfPolicyT::detail::delay_constructor_t;
   using TilePrefixCallbackOpT =
-    TilePrefixCallbackOp<OffsetT, ::cuda::std::plus<>, MemoryOrderedTileStateT, 0, DelayConstructorT>;
+    TilePrefixCallbackOp<OffsetT, ::cuda::std::plus<>, MemoryOrderedTileStateT, DelayConstructorT>;
 
   // Item exchange type
   using ItemExchangeT = InputT[TILE_ITEMS];
diff --git a/cub/cub/agent/agent_three_way_partition.cuh b/cub/cub/agent/agent_three_way_partition.cuh
index 047861254ac..f36151f916f 100644
--- a/cub/cub/agent/agent_three_way_partition.cuh
+++ b/cub/cub/agent/agent_three_way_partition.cuh
@@ -207,7 +207,7 @@ struct AgentThreeWayPartition
   // Callback type for obtaining tile prefix during block scan
   using DelayConstructorT = typename PolicyT::detail::delay_constructor_t;
   using TilePrefixCallbackOpT =
-    cub::TilePrefixCallbackOp<AccumPackT, ::cuda::std::plus<>, ScanTileStateT, 0, DelayConstructorT>;
+    cub::TilePrefixCallbackOp<AccumPackT, ::cuda::std::plus<>, ScanTileStateT, DelayConstructorT>;
 
   // Item exchange type
   using ItemExchangeT = InputT[TILE_ITEMS];
diff --git a/cub/cub/agent/agent_unique_by_key.cuh b/cub/cub/agent/agent_unique_by_key.cuh
index a1a731f150f..52ca1d9b3a2 100644
--- a/cub/cub/agent/agent_unique_by_key.cuh
+++ b/cub/cub/agent/agent_unique_by_key.cuh
@@ -179,9 +179,8 @@ struct AgentUniqueByKey
   using BlockScanT = cub::BlockScan<OffsetT, BLOCK_THREADS, AgentUniqueByKeyPolicyT::SCAN_ALGORITHM>;
 
   // Parameterized BlockDiscontinuity type for items
-  using DelayConstructorT = typename AgentUniqueByKeyPolicyT::detail::delay_constructor_t;
-  using TilePrefixCallback =
-    cub::TilePrefixCallbackOp<OffsetT, ::cuda::std::plus<>, ScanTileStateT, 0, DelayConstructorT>;
+  using DelayConstructorT  = typename AgentUniqueByKeyPolicyT::detail::delay_constructor_t;
+  using TilePrefixCallback = cub::TilePrefixCallbackOp<OffsetT, ::cuda::std::plus<>, ScanTileStateT, DelayConstructorT>;
 
   // Key exchange type
   using KeyExchangeT = KeyT[ITEMS_PER_TILE];
diff --git a/cub/cub/agent/single_pass_scan_operators.cuh b/cub/cub/agent/single_pass_scan_operators.cuh
index bd6551b8f8d..98769aa7791 100644
--- a/cub/cub/agent/single_pass_scan_operators.cuh
+++ b/cub/cub/agent/single_pass_scan_operators.cuh
@@ -1170,7 +1170,6 @@ struct ReduceByKeyScanTileState<ValueT, KeyT, true>
 template <typename T,
           typename ScanOpT,
           typename ScanTileStateT,
-          int LEGACY_PTX_ARCH        = 0,
           typename DelayConstructorT = detail::default_delay_constructor_t<T>>
 struct TilePrefixCallbackOp
 {
diff --git a/cub/cub/block/block_adjacent_difference.cuh b/cub/cub/block/block_adjacent_difference.cuh
index 38636571e80..119ca4f328e 100644
--- a/cub/cub/block/block_adjacent_difference.cuh
+++ b/cub/cub/block/block_adjacent_difference.cuh
@@ -122,7 +122,7 @@ CUB_NAMESPACE_BEGIN
 //! ``{ [4,-2,-1,0], [0,0,0,0], [1,1,0,0], [0,1,-3,3], ... }``.
 //!
 //! @endrst
-template <typename T, int BLOCK_DIM_X, int BLOCK_DIM_Y = 1, int BLOCK_DIM_Z = 1, int LEGACY_PTX_ARCH = 0>
+template <typename T, int BLOCK_DIM_X, int BLOCK_DIM_Y = 1, int BLOCK_DIM_Z = 1>
 class BlockAdjacentDifference
 {
 private:
diff --git a/cub/cub/block/block_discontinuity.cuh b/cub/cub/block/block_discontinuity.cuh
index e4998f32510..c175ac96458 100644
--- a/cub/cub/block/block_discontinuity.cuh
+++ b/cub/cub/block/block_discontinuity.cuh
@@ -122,9 +122,7 @@ CUB_NAMESPACE_BEGIN
 //! @tparam BLOCK_DIM_Z
 //!   **[optional]** The thread block length in threads along the Z dimension (default: 1)
 //!
-//! @tparam LEGACY_PTX_ARCH
-//!   **[optional]** Unused
-template <typename T, int BLOCK_DIM_X, int BLOCK_DIM_Y = 1, int BLOCK_DIM_Z = 1, int LEGACY_PTX_ARCH = 0>
+template <typename T, int BLOCK_DIM_X, int BLOCK_DIM_Y = 1, int BLOCK_DIM_Z = 1>
 class BlockDiscontinuity
 {
 private:
diff --git a/cub/cub/block/block_exchange.cuh b/cub/cub/block/block_exchange.cuh
index d1ae91c223d..402c60fe5a4 100644
--- a/cub/cub/block/block_exchange.cuh
+++ b/cub/cub/block/block_exchange.cuh
@@ -137,15 +137,12 @@ CUB_NAMESPACE_BEGIN
 //! @tparam BLOCK_DIM_Z
 //!    **[optional]** The thread block length in threads along the Z dimension (default: 1)
 //!
-//! @tparam LEGACY_PTX_ARCH
-//!    <b>[optional]</b> Unused.
 template <typename T,
           int BLOCK_DIM_X,
           int ITEMS_PER_THREAD,
           bool WARP_TIME_SLICING = false,
           int BLOCK_DIM_Y        = 1,
-          int BLOCK_DIM_Z        = 1,
-          int LEGACY_PTX_ARCH    = 0>
+          int BLOCK_DIM_Z        = 1>
 class BlockExchange
 {
   static constexpr int BLOCK_THREADS = BLOCK_DIM_X * BLOCK_DIM_Y * BLOCK_DIM_Z; ///< The thread block size in threads
diff --git a/cub/cub/block/block_histogram.cuh b/cub/cub/block/block_histogram.cuh
index 41abbd588b3..5ebd5c9371d 100644
--- a/cub/cub/block/block_histogram.cuh
+++ b/cub/cub/block/block_histogram.cuh
@@ -179,16 +179,13 @@ enum BlockHistogramAlgorithm
 //! @tparam BLOCK_DIM_Z
 //!   **[optional]** The thread block length in threads along the Z dimension (default: 1)
 //!
-//! @tparam LEGACY_PTX_ARCH
-//!   **[optional]** Unused.
 template <typename T,
           int BLOCK_DIM_X,
           int ITEMS_PER_THREAD,
           int BINS,
           BlockHistogramAlgorithm ALGORITHM = BLOCK_HISTO_SORT,
           int BLOCK_DIM_Y                   = 1,
-          int BLOCK_DIM_Z                   = 1,
-          int LEGACY_PTX_ARCH               = 0>
+          int BLOCK_DIM_Z                   = 1>
 class BlockHistogram
 {
 private:
diff --git a/cub/cub/block/block_load.cuh b/cub/cub/block/block_load.cuh
index c1e9b95ac56..f4a693f4750 100644
--- a/cub/cub/block/block_load.cuh
+++ b/cub/cub/block/block_load.cuh
@@ -790,15 +790,12 @@ enum BlockLoadAlgorithm
 //! @tparam BLOCK_DIM_Z
 //!   **[optional]** The thread block length in threads along the Z dimension (default: 1)
 //!
-//! @tparam LEGACY_PTX_ARCH
-//!   **[optional]** Unused.
 template <typename T,
           int BLOCK_DIM_X,
           int ITEMS_PER_THREAD,
           BlockLoadAlgorithm ALGORITHM = BLOCK_LOAD_DIRECT,
           int BLOCK_DIM_Y              = 1,
-          int BLOCK_DIM_Z              = 1,
-          int LEGACY_PTX_ARCH          = 0>
+          int BLOCK_DIM_Z              = 1>
 class BlockLoad
 {
   static constexpr int BLOCK_THREADS = BLOCK_DIM_X * BLOCK_DIM_Y * BLOCK_DIM_Z; // total threads in the block
diff --git a/cub/cub/block/block_radix_rank.cuh b/cub/cub/block/block_radix_rank.cuh
index ad495e1db31..6a899b1440a 100644
--- a/cub/cub/block/block_radix_rank.cuh
+++ b/cub/cub/block/block_radix_rank.cuh
@@ -204,8 +204,6 @@ struct warp_in_block_matcher_t<Bits, 0, PartialWarpId>
 //! @tparam BLOCK_DIM_Z
 //!   **[optional]** The thread block length in threads along the Z dimension (default: 1)
 //!
-//! @tparam LEGACY_PTX_ARCH
-//!   **[optional]** Unused.
 template <int BLOCK_DIM_X,
           int RADIX_BITS,
           bool IS_DESCENDING,
@@ -213,8 +211,7 @@ template <int BLOCK_DIM_X,
           BlockScanAlgorithm INNER_SCAN_ALGORITHM = BLOCK_SCAN_WARP_SCANS,
           cudaSharedMemConfig SMEM_CONFIG         = cudaSharedMemBankSizeFourByte,
           int BLOCK_DIM_Y                         = 1,
-          int BLOCK_DIM_Z                         = 1,
-          int LEGACY_PTX_ARCH                     = 0>
+          int BLOCK_DIM_Z                         = 1>
 class BlockRadixRank
 {
 private:
@@ -560,8 +557,7 @@ template <int BLOCK_DIM_X,
           bool IS_DESCENDING,
           BlockScanAlgorithm INNER_SCAN_ALGORITHM = BLOCK_SCAN_WARP_SCANS,
           int BLOCK_DIM_Y                         = 1,
-          int BLOCK_DIM_Z                         = 1,
-          int LEGACY_PTX_ARCH                     = 0>
+          int BLOCK_DIM_Z                         = 1>
 class BlockRadixRankMatch
 {
 private:
diff --git a/cub/cub/block/block_radix_sort.cuh b/cub/cub/block/block_radix_sort.cuh
index 080053348d7..55dd8747ee4 100644
--- a/cub/cub/block/block_radix_sort.cuh
+++ b/cub/cub/block/block_radix_sort.cuh
@@ -238,8 +238,6 @@ CUB_NAMESPACE_BEGIN
 //! @tparam BLOCK_DIM_Z
 //!   **[optional]** The thread block length in threads along the Z dimension (default: 1)
 //!
-//! @tparam LEGACY_PTX_ARCH
-//!   **[optional]** Unused
 template <typename KeyT,
           int BLOCK_DIM_X,
           int ITEMS_PER_THREAD,
@@ -249,8 +247,7 @@ template <typename KeyT,
           BlockScanAlgorithm INNER_SCAN_ALGORITHM = BLOCK_SCAN_WARP_SCANS,
           cudaSharedMemConfig SMEM_CONFIG         = cudaSharedMemBankSizeFourByte,
           int BLOCK_DIM_Y                         = 1,
-          int BLOCK_DIM_Z                         = 1,
-          int LEGACY_PTX_ARCH                     = 0>
+          int BLOCK_DIM_Z                         = 1>
 class BlockRadixSort
 {
 private:
diff --git a/cub/cub/block/block_raking_layout.cuh b/cub/cub/block/block_raking_layout.cuh
index 4d675b626b8..8f7f8b138c0 100644
--- a/cub/cub/block/block_raking_layout.cuh
+++ b/cub/cub/block/block_raking_layout.cuh
@@ -68,9 +68,7 @@ CUB_NAMESPACE_BEGIN
 //! @tparam BLOCK_THREADS
 //!   The thread block size in threads.
 //!
-//! @tparam LEGACY_PTX_ARCH
-//!   **[optional]** Unused.
-template <typename T, int BLOCK_THREADS, int LEGACY_PTX_ARCH = 0>
+template <typename T, int BLOCK_THREADS>
 struct BlockRakingLayout
 {
   //---------------------------------------------------------------------
diff --git a/cub/cub/block/block_reduce.cuh b/cub/cub/block/block_reduce.cuh
index 6cf578963fc..356134d3b40 100644
--- a/cub/cub/block/block_reduce.cuh
+++ b/cub/cub/block/block_reduce.cuh
@@ -232,14 +232,11 @@ enum BlockReduceAlgorithm
 //! @tparam BLOCK_DIM_Z
 //!   **[optional]** The thread block length in threads along the Z dimension (default: 1)
 //!
-//! @tparam LEGACY_PTX_ARCH
-//!   **[optional]** Unused.
 template <typename T,
           int BLOCK_DIM_X,
           BlockReduceAlgorithm ALGORITHM = BLOCK_REDUCE_WARP_REDUCTIONS,
           int BLOCK_DIM_Y                = 1,
-          int BLOCK_DIM_Z                = 1,
-          int LEGACY_PTX_ARCH            = 0>
+          int BLOCK_DIM_Z                = 1>
 class BlockReduce
 {
 private:
diff --git a/cub/cub/block/block_scan.cuh b/cub/cub/block/block_scan.cuh
index c25bd2d258d..de019116956 100644
--- a/cub/cub/block/block_scan.cuh
+++ b/cub/cub/block/block_scan.cuh
@@ -221,14 +221,11 @@ enum BlockScanAlgorithm
 //! @tparam BLOCK_DIM_Z
 //!   **[optional]** The thread block length in threads along the Z dimension (default: 1)
 //!
-//! @tparam LEGACY_PTX_ARCH
-//!   **[optional]** Unused.
 template <typename T,
           int BLOCK_DIM_X,
           BlockScanAlgorithm ALGORITHM = BLOCK_SCAN_RAKING,
           int BLOCK_DIM_Y              = 1,
-          int BLOCK_DIM_Z              = 1,
-          int LEGACY_PTX_ARCH          = 0>
+          int BLOCK_DIM_Z              = 1>
 class BlockScan
 {
 private:
diff --git a/cub/cub/block/block_shuffle.cuh b/cub/cub/block/block_shuffle.cuh
index 93d8715c63b..0cb42eba3a0 100644
--- a/cub/cub/block/block_shuffle.cuh
+++ b/cub/cub/block/block_shuffle.cuh
@@ -73,9 +73,7 @@ CUB_NAMESPACE_BEGIN
 //! @tparam BLOCK_DIM_Z
 //!   **[optional]** The thread block length in threads along the Z dimension (default: 1)
 //!
-//! @tparam LEGACY_PTX_ARCH
-//!   **[optional]** Unused
-template <typename T, int BLOCK_DIM_X, int BLOCK_DIM_Y = 1, int BLOCK_DIM_Z = 1, int LEGACY_PTX_ARCH = 0>
+template <typename T, int BLOCK_DIM_X, int BLOCK_DIM_Y = 1, int BLOCK_DIM_Z = 1>
 class BlockShuffle
 {
 private:
diff --git a/cub/cub/block/block_store.cuh b/cub/cub/block/block_store.cuh
index e207a1d76c1..a2cd74fcd90 100644
--- a/cub/cub/block/block_store.cuh
+++ b/cub/cub/block/block_store.cuh
@@ -639,15 +639,12 @@ enum BlockStoreAlgorithm
 //! @tparam BLOCK_DIM_Z
 //!   **[optional]** The thread block length in threads along the Z dimension (default: 1)
 //!
-//! @tparam LEGACY_PTX_ARCH
-//!   **[optional]** Unused.
 template <typename T,
           int BLOCK_DIM_X,
           int ITEMS_PER_THREAD,
           BlockStoreAlgorithm ALGORITHM = BLOCK_STORE_DIRECT,
           int BLOCK_DIM_Y               = 1,
-          int BLOCK_DIM_Z               = 1,
-          int LEGACY_PTX_ARCH           = 0>
+          int BLOCK_DIM_Z               = 1>
 class BlockStore
 {
 private:
diff --git a/cub/cub/block/specializations/block_histogram_sort.cuh b/cub/cub/block/specializations/block_histogram_sort.cuh
index 127f30953b2..b5e0f7beae2 100644
--- a/cub/cub/block/specializations/block_histogram_sort.cuh
+++ b/cub/cub/block/specializations/block_histogram_sort.cuh
@@ -72,17 +72,8 @@ namespace detail
  *
  * @tparam BLOCK_DIM_Z
  *   The thread block length in threads along the Z dimension
- *
- * @tparam LEGACY_PTX_ARCH
- *   The PTX compute capability for which to to specialize this collective (unused)
  */
-template <typename T,
-          int BLOCK_DIM_X,
-          int ITEMS_PER_THREAD,
-          int BINS,
-          int BLOCK_DIM_Y,
-          int BLOCK_DIM_Z,
-          int LEGACY_PTX_ARCH = 0>
+template <typename T, int BLOCK_DIM_X, int ITEMS_PER_THREAD, int BINS, int BLOCK_DIM_Y, int BLOCK_DIM_Z>
 struct BlockHistogramSort
 {
   /// Constants
@@ -246,16 +237,9 @@ struct BlockHistogramSort
 };
 } // namespace detail
 
-template <typename T,
-          int BLOCK_DIM_X,
-          int ITEMS_PER_THREAD,
-          int BINS,
-          int BLOCK_DIM_Y,
-          int BLOCK_DIM_Z,
-          int LEGACY_PTX_ARCH = 0>
+template <typename T, int BLOCK_DIM_X, int ITEMS_PER_THREAD, int BINS, int BLOCK_DIM_Y, int BLOCK_DIM_Z>
 using BlockHistogramSort CCCL_DEPRECATED_BECAUSE(
   "This class is considered an implementation detail and the public interface will be "
-  "removed.") =
-  detail::BlockHistogramSort<T, BLOCK_DIM_X, ITEMS_PER_THREAD, BINS, BLOCK_DIM_Y, BLOCK_DIM_Z, LEGACY_PTX_ARCH>;
+  "removed.") = detail::BlockHistogramSort<T, BLOCK_DIM_X, ITEMS_PER_THREAD, BINS, BLOCK_DIM_Y, BLOCK_DIM_Z>;
 
 CUB_NAMESPACE_END
diff --git a/cub/cub/block/specializations/block_reduce_raking.cuh b/cub/cub/block/specializations/block_reduce_raking.cuh
index 90f8f12236f..a45a16f6e0d 100644
--- a/cub/cub/block/specializations/block_reduce_raking.cuh
+++ b/cub/cub/block/specializations/block_reduce_raking.cuh
@@ -77,11 +77,8 @@ namespace detail
  *
  * @tparam BLOCK_DIM_Z
  *   The thread block length in threads along the Z dimension
- *
- * @tparam LEGACY_PTX_ARCH
- *   The PTX compute capability for which to to specialize this collective
  */
-template <typename T, int BLOCK_DIM_X, int BLOCK_DIM_Y, int BLOCK_DIM_Z, int LEGACY_PTX_ARCH = 0>
+template <typename T, int BLOCK_DIM_X, int BLOCK_DIM_Y, int BLOCK_DIM_Z>
 struct BlockReduceRaking
 {
   /// Constants
@@ -260,9 +257,9 @@ struct BlockReduceRaking
 };
 } // namespace detail
 
-template <typename T, int BLOCK_DIM_X, int BLOCK_DIM_Y, int BLOCK_DIM_Z, int LEGACY_PTX_ARCH = 0>
+template <typename T, int BLOCK_DIM_X, int BLOCK_DIM_Y, int BLOCK_DIM_Z>
 using BlockReduceRaking CCCL_DEPRECATED_BECAUSE(
   "This class is considered an implementation detail and the public interface will be "
-  "removed.") = detail::BlockReduceRaking<T, BLOCK_DIM_X, BLOCK_DIM_Y, BLOCK_DIM_Z, LEGACY_PTX_ARCH>;
+  "removed.") = detail::BlockReduceRaking<T, BLOCK_DIM_X, BLOCK_DIM_Y, BLOCK_DIM_Z>;
 
 CUB_NAMESPACE_END
diff --git a/cub/cub/block/specializations/block_reduce_raking_commutative_only.cuh b/cub/cub/block/specializations/block_reduce_raking_commutative_only.cuh
index 7841db5f18a..28ff55b5fe0 100644
--- a/cub/cub/block/specializations/block_reduce_raking_commutative_only.cuh
+++ b/cub/cub/block/specializations/block_reduce_raking_commutative_only.cuh
@@ -68,11 +68,8 @@ namespace detail
  *
  * @tparam BLOCK_DIM_Z
  *   The thread block length in threads along the Z dimension
- *
- * @tparam LEGACY_PTX_ARCH
- *   The PTX compute capability for which to to specialize this collective
  */
-template <typename T, int BLOCK_DIM_X, int BLOCK_DIM_Y, int BLOCK_DIM_Z, int LEGACY_PTX_ARCH = 0>
+template <typename T, int BLOCK_DIM_X, int BLOCK_DIM_Y, int BLOCK_DIM_Z>
 struct BlockReduceRakingCommutativeOnly
 {
   /// Constants
@@ -234,9 +231,9 @@ struct BlockReduceRakingCommutativeOnly
 };
 } // namespace detail
 
-template <typename T, int BLOCK_DIM_X, int BLOCK_DIM_Y, int BLOCK_DIM_Z, int LEGACY_PTX_ARCH = 0>
+template <typename T, int BLOCK_DIM_X, int BLOCK_DIM_Y, int BLOCK_DIM_Z>
 using BlockReduceRakingCommutativeOnly CCCL_DEPRECATED_BECAUSE(
   "This class is considered an implementation detail and the public interface will be "
-  "removed.") = detail::BlockReduceRakingCommutativeOnly<T, BLOCK_DIM_X, BLOCK_DIM_Y, BLOCK_DIM_Z, LEGACY_PTX_ARCH>;
+  "removed.") = detail::BlockReduceRakingCommutativeOnly<T, BLOCK_DIM_X, BLOCK_DIM_Y, BLOCK_DIM_Z>;
 
 CUB_NAMESPACE_END
diff --git a/cub/cub/block/specializations/block_reduce_warp_reductions.cuh b/cub/cub/block/specializations/block_reduce_warp_reductions.cuh
index 2dfa526771f..b6e70248b1e 100644
--- a/cub/cub/block/specializations/block_reduce_warp_reductions.cuh
+++ b/cub/cub/block/specializations/block_reduce_warp_reductions.cuh
@@ -67,11 +67,8 @@ namespace detail
  *
  * @tparam BLOCK_DIM_Z
  *   The thread block length in threads along the Z dimension
- *
- * @tparam LEGACY_PTX_ARCH
- *   The PTX compute capability for which to to specialize this collective
  */
-template <typename T, int BLOCK_DIM_X, int BLOCK_DIM_Y, int BLOCK_DIM_Z, int LEGACY_PTX_ARCH = 0>
+template <typename T, int BLOCK_DIM_X, int BLOCK_DIM_Y, int BLOCK_DIM_Z>
 struct BlockReduceWarpReductions
 {
   /// Constants
@@ -259,9 +256,9 @@ struct BlockReduceWarpReductions
 };
 } // namespace detail
 
-template <typename T, int BLOCK_DIM_X, int BLOCK_DIM_Y, int BLOCK_DIM_Z, int LEGACY_PTX_ARCH = 0>
+template <typename T, int BLOCK_DIM_X, int BLOCK_DIM_Y, int BLOCK_DIM_Z>
 using BlockReduceWarpReductions CCCL_DEPRECATED_BECAUSE(
   "This class is considered an implementation detail and the public interface will be "
-  "removed.") = detail::BlockReduceWarpReductions<T, BLOCK_DIM_X, BLOCK_DIM_Y, BLOCK_DIM_Z, LEGACY_PTX_ARCH>;
+  "removed.") = detail::BlockReduceWarpReductions<T, BLOCK_DIM_X, BLOCK_DIM_Y, BLOCK_DIM_Z>;
 
 CUB_NAMESPACE_END
diff --git a/cub/cub/block/specializations/block_scan_raking.cuh b/cub/cub/block/specializations/block_scan_raking.cuh
index 2af4b8693fc..26d9d949226 100644
--- a/cub/cub/block/specializations/block_scan_raking.cuh
+++ b/cub/cub/block/specializations/block_scan_raking.cuh
@@ -73,11 +73,8 @@ namespace detail
  * @tparam MEMOIZE
  *   Whether or not to buffer outer raking scan partials to incur fewer shared memory reads at the
  * expense of higher register pressure
- *
- * @tparam LEGACY_PTX_ARCH
- *   The PTX compute capability for which to to specialize this collective
  */
-template <typename T, int BLOCK_DIM_X, int BLOCK_DIM_Y, int BLOCK_DIM_Z, bool MEMOIZE, int LEGACY_PTX_ARCH = 0>
+template <typename T, int BLOCK_DIM_X, int BLOCK_DIM_Y, int BLOCK_DIM_Z, bool MEMOIZE>
 struct BlockScanRaking
 {
   //---------------------------------------------------------------------
@@ -797,9 +794,9 @@ struct BlockScanRaking
 };
 } // namespace detail
 
-template <typename T, int BLOCK_DIM_X, int BLOCK_DIM_Y, int BLOCK_DIM_Z, bool MEMOIZE, int LEGACY_PTX_ARCH = 0>
+template <typename T, int BLOCK_DIM_X, int BLOCK_DIM_Y, int BLOCK_DIM_Z, bool MEMOIZE>
 using BlockScanRaking CCCL_DEPRECATED_BECAUSE(
   "This class is considered an implementation detail and the public interface will be "
-  "removed.") = detail::BlockScanRaking<T, BLOCK_DIM_X, BLOCK_DIM_Y, BLOCK_DIM_Z, MEMOIZE, LEGACY_PTX_ARCH>;
+  "removed.") = detail::BlockScanRaking<T, BLOCK_DIM_X, BLOCK_DIM_Y, BLOCK_DIM_Z, MEMOIZE>;
 
 CUB_NAMESPACE_END
diff --git a/cub/cub/block/specializations/block_scan_warp_scans.cuh b/cub/cub/block/specializations/block_scan_warp_scans.cuh
index d034d2838ea..4fc74b423ce 100644
--- a/cub/cub/block/specializations/block_scan_warp_scans.cuh
+++ b/cub/cub/block/specializations/block_scan_warp_scans.cuh
@@ -64,11 +64,8 @@ namespace detail
  *
  * @tparam BLOCK_DIM_Z
  *   The thread block length in threads along the Z dimension
- *
- * @tparam LEGACY_PTX_ARCH
- *   The PTX compute capability for which to to specialize this collective
  */
-template <typename T, int BLOCK_DIM_X, int BLOCK_DIM_Y, int BLOCK_DIM_Z, int LEGACY_PTX_ARCH = 0>
+template <typename T, int BLOCK_DIM_X, int BLOCK_DIM_Y, int BLOCK_DIM_Z>
 struct BlockScanWarpScans
 {
   //---------------------------------------------------------------------
@@ -539,9 +536,9 @@ struct BlockScanWarpScans
   }
 };
 } // namespace detail
-template <typename T, int BLOCK_DIM_X, int BLOCK_DIM_Y, int BLOCK_DIM_Z, int LEGACY_PTX_ARCH = 0>
+template <typename T, int BLOCK_DIM_X, int BLOCK_DIM_Y, int BLOCK_DIM_Z>
 using BlockScanWarpScans CCCL_DEPRECATED_BECAUSE(
   "This class is considered an implementation detail and the public interface will be "
-  "removed.") = detail::BlockScanWarpScans<T, BLOCK_DIM_X, BLOCK_DIM_Y, BLOCK_DIM_Z, LEGACY_PTX_ARCH>;
+  "removed.") = detail::BlockScanWarpScans<T, BLOCK_DIM_X, BLOCK_DIM_Y, BLOCK_DIM_Z>;
 
 CUB_NAMESPACE_END
diff --git a/cub/cub/util_ptx.cuh b/cub/cub/util_ptx.cuh
index e6bb45c4a31..8e37c287109 100644
--- a/cub/cub/util_ptx.cuh
+++ b/cub/cub/util_ptx.cuh
@@ -384,7 +384,7 @@ _CCCL_DEVICE _CCCL_FORCEINLINE unsigned int WarpId()
  *                              hardware warp threads).
  * @param warp_id Id of virtual warp within architectural warp
  */
-template <int LOGICAL_WARP_THREADS, int LEGACY_PTX_ARCH = 0>
+template <int LOGICAL_WARP_THREADS>
 _CCCL_HOST_DEVICE _CCCL_FORCEINLINE unsigned int WarpMask(unsigned int warp_id)
 {
   constexpr bool is_pow_of_two = PowerOfTwo<LOGICAL_WARP_THREADS>::VALUE;
diff --git a/cub/cub/warp/specializations/warp_reduce_shfl.cuh b/cub/cub/warp/specializations/warp_reduce_shfl.cuh
index 8c4ad78d1ad..3592e7c920a 100644
--- a/cub/cub/warp/specializations/warp_reduce_shfl.cuh
+++ b/cub/cub/warp/specializations/warp_reduce_shfl.cuh
@@ -92,11 +92,8 @@ struct reduce_max_exists<T, decltype(__reduce_max_sync(0xFFFFFFFF, T{}))> : ::cu
  *
  * @tparam LOGICAL_WARP_THREADS
  *   Number of threads per logical warp (must be a power-of-two)
- *
- * @tparam LEGACY_PTX_ARCH
- *   The PTX compute capability for which to to specialize this collective
  */
-template <typename T, int LOGICAL_WARP_THREADS, int LEGACY_PTX_ARCH = 0>
+template <typename T, int LOGICAL_WARP_THREADS>
 struct WarpReduceShfl
 {
   static_assert(PowerOfTwo<LOGICAL_WARP_THREADS>::VALUE, "LOGICAL_WARP_THREADS must be a power of two");
@@ -739,9 +736,9 @@ struct WarpReduceShfl
 };
 } // namespace detail
 
-template <typename T, int LOGICAL_WARP_THREADS, int LEGACY_PTX_ARCH = 0>
+template <typename T, int LOGICAL_WARP_THREADS>
 using WarpReduceShfl CCCL_DEPRECATED_BECAUSE(
   "This class is considered an implementation detail and the public interface will be "
-  "removed.") = detail::WarpReduceShfl<T, LOGICAL_WARP_THREADS, LEGACY_PTX_ARCH>;
+  "removed.") = detail::WarpReduceShfl<T, LOGICAL_WARP_THREADS>;
 
 CUB_NAMESPACE_END
diff --git a/cub/cub/warp/specializations/warp_reduce_smem.cuh b/cub/cub/warp/specializations/warp_reduce_smem.cuh
index ade195ee6cb..b4e509d6766 100644
--- a/cub/cub/warp/specializations/warp_reduce_smem.cuh
+++ b/cub/cub/warp/specializations/warp_reduce_smem.cuh
@@ -63,11 +63,8 @@ namespace detail
  *
  * @tparam LOGICAL_WARP_THREADS
  *   Number of threads per logical warp
- *
- * @tparam LEGACY_PTX_ARCH
- *   The PTX compute capability for which to to specialize this collective
  */
-template <typename T, int LOGICAL_WARP_THREADS, int LEGACY_PTX_ARCH = 0>
+template <typename T, int LOGICAL_WARP_THREADS>
 struct WarpReduceSmem
 {
   /******************************************************************************
@@ -414,8 +411,8 @@ struct WarpReduceSmem
 };
 } // namespace detail
 
-template <typename T, int LOGICAL_WARP_THREADS, int LEGACY_PTX_ARCH = 0>
+template <typename T, int LOGICAL_WARP_THREADS>
 using WarpReduceSmem CCCL_DEPRECATED_BECAUSE(
   "This class is considered an implementation detail and the public interface will be "
-  "removed.") = detail::WarpReduceSmem<T, LOGICAL_WARP_THREADS, LEGACY_PTX_ARCH>;
+  "removed.") = detail::WarpReduceSmem<T, LOGICAL_WARP_THREADS>;
 CUB_NAMESPACE_END
diff --git a/cub/cub/warp/specializations/warp_scan_shfl.cuh b/cub/cub/warp/specializations/warp_scan_shfl.cuh
index 402b476c4e4..4b3b115b266 100644
--- a/cub/cub/warp/specializations/warp_scan_shfl.cuh
+++ b/cub/cub/warp/specializations/warp_scan_shfl.cuh
@@ -62,11 +62,8 @@ namespace detail
  *
  * @tparam LOGICAL_WARP_THREADS
  *   Number of threads per logical warp (must be a power-of-two)
- *
- * @tparam LEGACY_PTX_ARCH
- *   The PTX compute capability for which to to specialize this collective
  */
-template <typename T, int LOGICAL_WARP_THREADS, int LEGACY_PTX_ARCH = 0>
+template <typename T, int LOGICAL_WARP_THREADS>
 struct WarpScanShfl
 {
   //---------------------------------------------------------------------
@@ -677,9 +674,9 @@ struct WarpScanShfl
 };
 } // namespace detail
 
-template <typename T, int LOGICAL_WARP_THREADS, int LEGACY_PTX_ARCH = 0>
+template <typename T, int LOGICAL_WARP_THREADS>
 using WarpScanShfl CCCL_DEPRECATED_BECAUSE(
   "This class is considered an implementation detail and the public interface will be "
-  "removed.") = detail::WarpScanShfl<T, LOGICAL_WARP_THREADS, LEGACY_PTX_ARCH>;
+  "removed.") = detail::WarpScanShfl<T, LOGICAL_WARP_THREADS>;
 
 CUB_NAMESPACE_END
diff --git a/cub/cub/warp/specializations/warp_scan_smem.cuh b/cub/cub/warp/specializations/warp_scan_smem.cuh
index 090f0f96cb5..e6d18fb561f 100644
--- a/cub/cub/warp/specializations/warp_scan_smem.cuh
+++ b/cub/cub/warp/specializations/warp_scan_smem.cuh
@@ -63,11 +63,8 @@ namespace detail
  *
  * @tparam LOGICAL_WARP_THREADS
  *   Number of threads per logical warp
- *
- * @tparam LEGACY_PTX_ARCH
- *   The PTX compute capability for which to to specialize this collective
  */
-template <typename T, int LOGICAL_WARP_THREADS, int LEGACY_PTX_ARCH = 0>
+template <typename T, int LOGICAL_WARP_THREADS>
 struct WarpScanSmem
 {
   /******************************************************************************
@@ -435,9 +432,9 @@ struct WarpScanSmem
 };
 } // namespace detail
 
-template <typename T, int LOGICAL_WARP_THREADS, int LEGACY_PTX_ARCH = 0>
+template <typename T, int LOGICAL_WARP_THREADS>
 using WarpScanSmem CCCL_DEPRECATED_BECAUSE(
   "This class is considered an implementation detail and the public interface will be "
-  "removed.") = detail::WarpScanSmem<T, LOGICAL_WARP_THREADS, LEGACY_PTX_ARCH>;
+  "removed.") = detail::WarpScanSmem<T, LOGICAL_WARP_THREADS>;
 
 CUB_NAMESPACE_END
diff --git a/cub/cub/warp/warp_exchange.cuh b/cub/cub/warp/warp_exchange.cuh
index 79f422f5abe..7ce5997a446 100644
--- a/cub/cub/warp/warp_exchange.cuh
+++ b/cub/cub/warp/warp_exchange.cuh
@@ -83,9 +83,6 @@ using InternalWarpExchangeImpl =
  *   targeted CUDA compute-capability (e.g., 32 threads for SM86). Must be a
  *   power of two.
  *
- * @tparam LEGACY_PTX_ARCH
- *   Unused.
- *
  * @par Overview
  * - It is commonplace for a warp of threads to rearrange data items between
  *   threads. For example, the global memory accesses prefer patterns where
@@ -139,7 +136,6 @@ using InternalWarpExchangeImpl =
 template <typename InputT,
           int ITEMS_PER_THREAD,
           int LOGICAL_WARP_THREADS                      = CUB_PTX_WARP_THREADS,
-          int LEGACY_PTX_ARCH                           = 0,
           WarpExchangeAlgorithm WARP_EXCHANGE_ALGORITHM = WARP_EXCHANGE_SMEM>
 class WarpExchange
     : private detail::InternalWarpExchangeImpl<InputT, ITEMS_PER_THREAD, LOGICAL_WARP_THREADS, WARP_EXCHANGE_ALGORITHM>
diff --git a/cub/cub/warp/warp_load.cuh b/cub/cub/warp/warp_load.cuh
index 3f11129c35a..b945a5355b2 100644
--- a/cub/cub/warp/warp_load.cuh
+++ b/cub/cub/warp/warp_load.cuh
@@ -216,13 +216,10 @@ enum WarpLoadAlgorithm
 //!   targeted CUDA compute-capability (e.g., 32 threads for SM86). Must be a
 //!   power of two.
 //!
-//! @tparam LEGACY_PTX_ARCH
-//!   Unused.
 template <typename InputT,
           int ITEMS_PER_THREAD,
           WarpLoadAlgorithm ALGORITHM = WARP_LOAD_DIRECT,
-          int LOGICAL_WARP_THREADS    = CUB_PTX_WARP_THREADS,
-          int LEGACY_PTX_ARCH         = 0>
+          int LOGICAL_WARP_THREADS    = CUB_PTX_WARP_THREADS>
 class WarpLoad
 {
   static constexpr bool IS_ARCH_WARP = LOGICAL_WARP_THREADS == CUB_WARP_THREADS(0);
diff --git a/cub/cub/warp/warp_merge_sort.cuh b/cub/cub/warp/warp_merge_sort.cuh
index de3d311ae59..447dc4d00c2 100644
--- a/cub/cub/warp/warp_merge_sort.cuh
+++ b/cub/cub/warp/warp_merge_sort.cuh
@@ -122,14 +122,7 @@ CUB_NAMESPACE_BEGIN
 //!   <b>[optional]</b> Value type (default: cub::NullType, which indicates a
 //!   keys-only sort)
 //!
-//! @tparam LEGACY_PTX_ARCH
-//!   Unused.
-//!
-template <typename KeyT,
-          int ITEMS_PER_THREAD,
-          int LOGICAL_WARP_THREADS = CUB_WARP_THREADS(0),
-          typename ValueT          = NullType,
-          int LEGACY_PTX_ARCH      = 0>
+template <typename KeyT, int ITEMS_PER_THREAD, int LOGICAL_WARP_THREADS = CUB_WARP_THREADS(0), typename ValueT = NullType>
 class WarpMergeSort
     : public BlockMergeSortStrategy<KeyT,
                                     ValueT,
diff --git a/cub/cub/warp/warp_reduce.cuh b/cub/cub/warp/warp_reduce.cuh
index 4b2c61e343a..7992432a1c3 100644
--- a/cub/cub/warp/warp_reduce.cuh
+++ b/cub/cub/warp/warp_reduce.cuh
@@ -150,9 +150,7 @@ CUB_NAMESPACE_BEGIN
 //!   hardware warp threads).  Default is the warp size of the targeted CUDA compute-capability
 //!   (e.g., 32 threads for SM20).
 //!
-//! @tparam LEGACY_PTX_ARCH
-//!   <b>[optional]</b> Unused.
-template <typename T, int LOGICAL_WARP_THREADS = CUB_PTX_WARP_THREADS, int LEGACY_PTX_ARCH = 0>
+template <typename T, int LOGICAL_WARP_THREADS = CUB_PTX_WARP_THREADS>
 class WarpReduce
 {
 private:
@@ -663,8 +661,8 @@ public:
 };
 
 #ifndef _CCCL_DOXYGEN_INVOKED // Do not document
-template <typename T, int LEGACY_PTX_ARCH>
-class WarpReduce<T, 1, LEGACY_PTX_ARCH>
+template <typename T>
+class WarpReduce<T, 1>
 {
 private:
   using _TempStorage = cub::NullType;
diff --git a/cub/cub/warp/warp_scan.cuh b/cub/cub/warp/warp_scan.cuh
index 6eb6a35562b..e1c07c82691 100644
--- a/cub/cub/warp/warp_scan.cuh
+++ b/cub/cub/warp/warp_scan.cuh
@@ -156,9 +156,7 @@ CUB_NAMESPACE_BEGIN
 //!   hardware warp threads). Default is the warp size associated with the CUDA Compute Capability
 //!   targeted by the compiler (e.g., 32 threads for SM20).
 //!
-//! @tparam LEGACY_PTX_ARCH
-//!   **[optional]** Unused.
-template <typename T, int LOGICAL_WARP_THREADS = CUB_PTX_WARP_THREADS, int LEGACY_PTX_ARCH = 0>
+template <typename T, int LOGICAL_WARP_THREADS = CUB_PTX_WARP_THREADS>
 class WarpScan
 {
 private:
diff --git a/cub/cub/warp/warp_store.cuh b/cub/cub/warp/warp_store.cuh
index f0a9929e24f..a7ccb899607 100644
--- a/cub/cub/warp/warp_store.cuh
+++ b/cub/cub/warp/warp_store.cuh
@@ -223,13 +223,10 @@ enum WarpStoreAlgorithm
 //!   targeted CUDA compute-capability (e.g., 32 threads for SM86). Must be a
 //!   power of two.
 //!
-//! @tparam LEGACY_PTX_ARCH
-//!   Unused.
 template <typename T,
           int ITEMS_PER_THREAD,
           WarpStoreAlgorithm ALGORITHM = WARP_STORE_DIRECT,
-          int LOGICAL_WARP_THREADS     = CUB_PTX_WARP_THREADS,
-          int LEGACY_PTX_ARCH          = 0>
+          int LOGICAL_WARP_THREADS     = CUB_PTX_WARP_THREADS>
 class WarpStore
 {
   static_assert(PowerOfTwo<LOGICAL_WARP_THREADS>::VALUE, "LOGICAL_WARP_THREADS must be a power of two");
diff --git a/cub/test/catch2_test_warp_exchange.cuh b/cub/test/catch2_test_warp_exchange.cuh
index 4b3b13563c0..e240abc7f48 100644
--- a/cub/test/catch2_test_warp_exchange.cuh
+++ b/cub/test/catch2_test_warp_exchange.cuh
@@ -53,7 +53,7 @@ struct exchange_data_t<InputT,
 
   template <int LogicalWarpThreads>
   inline __device__ void
-  scatter(cub::WarpExchange<InputT, ItemsPerThread, LogicalWarpThreads, 0, Alg>& exchange, int (&ranks)[ItemsPerThread])
+  scatter(cub::WarpExchange<InputT, ItemsPerThread, LogicalWarpThreads, Alg>& exchange, int (&ranks)[ItemsPerThread])
   {
     exchange.ScatterToStriped(input, ranks);
   }
@@ -71,7 +71,7 @@ struct exchange_data_t<InputT,
 
   template <int LogicalWarpThreads>
   inline __device__ void
-  scatter(cub::WarpExchange<InputT, ItemsPerThread, LogicalWarpThreads, 0, Alg>& exchange, int (&ranks)[ItemsPerThread])
+  scatter(cub::WarpExchange<InputT, ItemsPerThread, LogicalWarpThreads, Alg>& exchange, int (&ranks)[ItemsPerThread])
   {
     exchange.ScatterToStriped(input, output, ranks);
   }
@@ -85,7 +85,7 @@ template <int LOGICAL_WARP_THREADS,
           typename OutputT>
 __global__ void scatter_kernel(const InputT* input_data, OutputT* output_data)
 {
-  using warp_exchange_t = cub::WarpExchange<InputT, ITEMS_PER_THREAD, LOGICAL_WARP_THREADS, 0, Alg>;
+  using warp_exchange_t = cub::WarpExchange<InputT, ITEMS_PER_THREAD, LOGICAL_WARP_THREADS, Alg>;
   using storage_t       = typename warp_exchange_t::TempStorage;
 
   constexpr int tile_size = ITEMS_PER_THREAD * LOGICAL_WARP_THREADS;
@@ -147,7 +147,7 @@ template <int LOGICAL_WARP_THREADS,
           typename ActionT>
 __global__ void kernel(const InputT* input_data, OutputT* output_data, ActionT action)
 {
-  using warp_exchange_t = cub::WarpExchange<InputT, ITEMS_PER_THREAD, LOGICAL_WARP_THREADS, 0, Alg>;
+  using warp_exchange_t = cub::WarpExchange<InputT, ITEMS_PER_THREAD, LOGICAL_WARP_THREADS, Alg>;
   using storage_t       = typename warp_exchange_t::TempStorage;
 
   constexpr int tile_size = ITEMS_PER_THREAD * LOGICAL_WARP_THREADS;
@@ -205,7 +205,7 @@ struct blocked_to_striped
             cub::WarpExchangeAlgorithm Alg>
   __device__ void operator()(InputT (&input)[ITEMS_PER_THREAD],
                              OutputT (&output)[ITEMS_PER_THREAD],
-                             cub::WarpExchange<InputT, ItemsPerThread, LogicalWarpThreads, 0, Alg>& exchange)
+                             cub::WarpExchange<InputT, ItemsPerThread, LogicalWarpThreads, Alg>& exchange)
   {
     exchange.BlockedToStriped(input, output);
   }
@@ -221,7 +221,7 @@ struct striped_to_blocked
             cub::WarpExchangeAlgorithm Alg>
   __device__ void operator()(InputT (&input)[ITEMS_PER_THREAD],
                              OutputT (&output)[ITEMS_PER_THREAD],
-                             cub::WarpExchange<InputT, ItemsPerThread, LogicalWarpThreads, 0, Alg>& exchange)
+                             cub::WarpExchange<InputT, ItemsPerThread, LogicalWarpThreads, Alg>& exchange)
   {
     exchange.StripedToBlocked(input, output);
   }
diff --git a/docs/cub/developer_overview.rst b/docs/cub/developer_overview.rst
index 8b31dab6283..29f02995ac4 100644
--- a/docs/cub/developer_overview.rst
+++ b/docs/cub/developer_overview.rst
@@ -157,8 +157,7 @@ For example, :cpp:struct:`cub::WarpReduce` is a class template:
 .. code-block:: c++
 
     template <typename T,
-              int LOGICAL_WARP_THREADS = 32,
-              int LEGACY_PTX_ARCH = 0>
+              int      LOGICAL_WARP_THREADS = 32>
     class WarpReduce {
       // ...
       // (1)   define `_TempStorage` type
@@ -193,10 +192,6 @@ There is a vital difference in the behavior of warp-level algorithms that depend
 
 .. TODO: Add diagram showing non-power of two logical warps.
 
-It's important to note that ``LEGACY_PTX_ARCH`` has been recently deprecated.
-This parameter used to affect specialization selection (see below).
-It was conflicting with the PTX dispatch refactoring and limited NVHPC support.
-
 Temporary storage usage
 ====================================
 
@@ -258,13 +253,15 @@ and algorithm implementation look like:
           .Reduce(input, valid_items, ::cuda::std::plus<>{});
     }
 
-Due to ``LEGACY_PTX_ARCH`` issues described above,
-we can't specialize on the PTX version.
+
+
+``__CUDA_ARCH__`` cannot be used because it is conflicting with the PTX dispatch refactoring and limited NVHPC support.
+Due to  this limitation, we can't specialize on the PTX version.
 ``NV_IF_TARGET`` shall be used by specializations instead:
 
 .. code-block:: c++
 
-    template <typename T, int LOGICAL_WARP_THREADS, int LEGACY_PTX_ARCH = 0>
+    template <typename T, int LOGICAL_WARP_THREADS>
     struct WarpReduceShfl
     {
 
@@ -314,8 +311,7 @@ Block-scope algorithms are provided by structures as well:
               int BLOCK_DIM_X,
               BlockReduceAlgorithm ALGORITHM = BLOCK_REDUCE_WARP_REDUCTIONS,
               int BLOCK_DIM_Y = 1,
-              int BLOCK_DIM_Z = 1,
-              int LEGACY_PTX_ARCH = 0>
+              int BLOCK_DIM_Z = 1>
     class BlockReduce {
     public:
       struct TempStorage : Uninitialized<_TempStorage> {};
diff --git a/thrust/thrust/system/cuda/detail/core/util.h b/thrust/thrust/system/cuda/detail/core/util.h
index b3bdcf1f086..1b11f459c71 100644
--- a/thrust/thrust/system/cuda/detail/core/util.h
+++ b/thrust/thrust/system/cuda/detail/core/util.h
@@ -488,14 +488,7 @@ struct get_arch<Plan<Arch>>
 template <class PtxPlan, class It, class T = typename iterator_traits<It>::value_type>
 struct BlockLoad
 {
-  using type =
-    cub::BlockLoad<T,
-                   PtxPlan::BLOCK_THREADS,
-                   PtxPlan::ITEMS_PER_THREAD,
-                   PtxPlan::LOAD_ALGORITHM,
-                   1,
-                   1,
-                   get_arch<PtxPlan>::type::ver>;
+  using type = cub::BlockLoad<T, PtxPlan::BLOCK_THREADS, PtxPlan::ITEMS_PER_THREAD, PtxPlan::LOAD_ALGORITHM, 1, 1>;
 };
 
 // cuda_optional
diff --git a/thrust/thrust/system/cuda/detail/reduce.h b/thrust/thrust/system/cuda/detail/reduce.h
index 61ec2086adf..8ef245dc082 100644
--- a/thrust/thrust/system/cuda/detail/reduce.h
+++ b/thrust/thrust/system/cuda/detail/reduce.h
@@ -156,7 +156,7 @@ struct ReduceAgent
 
     using Vector      = typename cub::CubVector<T, PtxPlan::VECTOR_LOAD_LENGTH>;
     using LoadIt      = typename core::detail::LoadIterator<PtxPlan, InputIt>::type;
-    using BlockReduce = cub::BlockReduce<T, PtxPlan::BLOCK_THREADS, PtxPlan::BLOCK_ALGORITHM, 1, 1, Arch::ver>;
+    using BlockReduce = cub::BlockReduce<T, PtxPlan::BLOCK_THREADS, PtxPlan::BLOCK_ALGORITHM, 1, 1>;
 
     using VectorLoadIt = cub::CacheModifiedInputIterator<PtxPlan::LOAD_MODIFIER, Vector, Size>;
 
diff --git a/thrust/thrust/system/cuda/detail/reduce_by_key.h b/thrust/thrust/system/cuda/detail/reduce_by_key.h
index 8c1db436085..fc6ceefa21b 100644
--- a/thrust/thrust/system/cuda/detail/reduce_by_key.h
+++ b/thrust/thrust/system/cuda/detail/reduce_by_key.h
@@ -169,12 +169,10 @@ struct ReduceByKeyAgent
     using BlockLoadKeys   = typename core::detail::BlockLoad<PtxPlan, KeysLoadIt>::type;
     using BlockLoadValues = typename core::detail::BlockLoad<PtxPlan, ValuesLoadIt>::type;
 
-    using BlockDiscontinuityKeys = cub::BlockDiscontinuity<key_type, PtxPlan::BLOCK_THREADS, 1, 1, Arch::ver>;
+    using BlockDiscontinuityKeys = cub::BlockDiscontinuity<key_type, PtxPlan::BLOCK_THREADS, 1, 1>;
 
-    using TilePrefixCallback =
-      cub::TilePrefixCallbackOp<size_value_pair_t, ReduceBySegmentOp, ScanTileState, Arch::ver>;
-    using BlockScan =
-      cub::BlockScan<size_value_pair_t, PtxPlan::BLOCK_THREADS, PtxPlan::SCAN_ALGORITHM, 1, 1, Arch::ver>;
+    using TilePrefixCallback = cub::TilePrefixCallbackOp<size_value_pair_t, ReduceBySegmentOp, ScanTileState>;
+    using BlockScan          = cub::BlockScan<size_value_pair_t, PtxPlan::BLOCK_THREADS, PtxPlan::SCAN_ALGORITHM, 1, 1>;
 
     union TempStorage
     {
diff --git a/thrust/thrust/system/cuda/detail/set_operations.h b/thrust/thrust/system/cuda/detail/set_operations.h
index b336f8e55fa..85d03ae51cb 100644
--- a/thrust/thrust/system/cuda/detail/set_operations.h
+++ b/thrust/thrust/system/cuda/detail/set_operations.h
@@ -300,9 +300,9 @@ struct SetOpAgent
     using BlockLoadValues1 = typename core::detail::BlockLoad<PtxPlan, ValuesLoadIt1>::type;
     using BlockLoadValues2 = typename core::detail::BlockLoad<PtxPlan, ValuesLoadIt2>::type;
 
-    using TilePrefixCallback = cub::TilePrefixCallbackOp<Size, ::cuda::std::plus<>, ScanTileState, Arch::ver>;
+    using TilePrefixCallback = cub::TilePrefixCallbackOp<Size, ::cuda::std::plus<>, ScanTileState>;
 
-    using BlockScan = cub::BlockScan<Size, PtxPlan::BLOCK_THREADS, PtxPlan::SCAN_ALGORITHM, 1, 1, Arch::ver>;
+    using BlockScan = cub::BlockScan<Size, PtxPlan::BLOCK_THREADS, PtxPlan::SCAN_ALGORITHM, 1, 1>;
 
     // gather required temporary storage in a union
     //
diff --git a/thrust/thrust/system/cuda/detail/unique.h b/thrust/thrust/system/cuda/detail/unique.h
index 1d39b161866..bb5092ba9ef 100644
--- a/thrust/thrust/system/cuda/detail/unique.h
+++ b/thrust/thrust/system/cuda/detail/unique.h
@@ -153,10 +153,10 @@ struct UniqueAgent
 
     using BlockLoadItems = typename core::detail::BlockLoad<PtxPlan, ItemsLoadIt>::type;
 
-    using BlockDiscontinuityItems = cub::BlockDiscontinuity<item_type, PtxPlan::BLOCK_THREADS, 1, 1, Arch::ver>;
+    using BlockDiscontinuityItems = cub::BlockDiscontinuity<item_type, PtxPlan::BLOCK_THREADS, 1, 1>;
 
-    using TilePrefixCallback = cub::TilePrefixCallbackOp<Size, ::cuda::std::plus<>, ScanTileState, Arch::ver>;
-    using BlockScan          = cub::BlockScan<Size, PtxPlan::BLOCK_THREADS, PtxPlan::SCAN_ALGORITHM, 1, 1, Arch::ver>;
+    using TilePrefixCallback = cub::TilePrefixCallbackOp<Size, ::cuda::std::plus<>, ScanTileState>;
+    using BlockScan          = cub::BlockScan<Size, PtxPlan::BLOCK_THREADS, PtxPlan::SCAN_ALGORITHM, 1, 1>;
 
     using shared_items_t = core::detail::uninitialized_array<item_type, PtxPlan::ITEMS_PER_TILE>;
 

From ca007c9ea13fbd43de5df6e0d94ebe7b7e1618f3 Mon Sep 17 00:00:00 2001
From: Cliff Burdick <30670611+cliffburdick@users.noreply.github.com>
Date: Thu, 30 Jan 2025 14:02:46 -0800
Subject: [PATCH 33/33] Fix typo in index.rst (#3620)

---
 docs/libcudacxx/index.rst | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/docs/libcudacxx/index.rst b/docs/libcudacxx/index.rst
index 0ae9c84339c..4ada47e7d85 100644
--- a/docs/libcudacxx/index.rst
+++ b/docs/libcudacxx/index.rst
@@ -65,7 +65,7 @@ learning curve of learning CUDA. However, there are many aspects of writing high
 be expressed through purely Standard conforming APIs. For these cases, libcu++ also provides *extensions* of Standard
 Library utilities.
 
-For example, libcu++ extends ``atomic<T>`` and other synchornization primitives with the notion of a “thread scope”
+For example, libcu++ extends ``atomic<T>`` and other synchronization primitives with the notion of a “thread scope”
 that controls the strength of the memory fence.
 
 To use utilities that are extensions to Standard Library features, drop the ``std``: