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NaghasanNaghasan
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Add grammar entries for SPV_INTEL_task_sequence
fixes KhronosGroup#492
1 parent 54a521d commit 17646a3

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10 files changed

+152
-0
lines changed

10 files changed

+152
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lines changed

‎include/spirv/unified1/spirv.bf

+6
Original file line numberDiff line numberDiff line change
@@ -1291,6 +1291,7 @@ namespace Spv
12911291
ArithmeticFenceEXT = 6144,
12921292
FPGAClusterAttributesV2INTEL = 6150,
12931293
FPGAKernelAttributesv2INTEL = 6161,
1294+
TaskSequenceINTEL = 6162,
12941295
FPMaxErrorINTEL = 6169,
12951296
FPGALatencyControlINTEL = 6171,
12961297
FPGAArgumentInterfacesINTEL = 6174,
@@ -2412,6 +2413,11 @@ namespace Spv
24122413
OpControlBarrierArriveINTEL = 6142,
24132414
OpControlBarrierWaitINTEL = 6143,
24142415
OpArithmeticFenceEXT = 6145,
2416+
OpTaskSequenceCreateINTEL = 6163,
2417+
OpTaskSequenceAsyncINTEL = 6164,
2418+
OpTaskSequenceGetINTEL = 6165,
2419+
OpTaskSequenceReleaseINTEL = 6166,
2420+
OpTypeTaskSequenceINTEL = 6199,
24152421
OpSubgroupBlockPrefetchINTEL = 6221,
24162422
OpSubgroup2DBlockLoadINTEL = 6231,
24172423
OpSubgroup2DBlockLoadTransformINTEL = 6232,

‎include/spirv/unified1/spirv.core.grammar.json

+65
Original file line numberDiff line numberDiff line change
@@ -10468,6 +10468,65 @@
1046810468
"capabilities" : [ "ArithmeticFenceEXT" ],
1046910469
"version" : "None"
1047010470
},
10471+
{
10472+
"opname" : "OpTaskSequenceCreateINTEL",
10473+
"class" : "Reserved",
10474+
"opcode" : 6163,
10475+
"operands" : [
10476+
{ "kind" : "IdResultType" },
10477+
{ "kind" : "IdResult" },
10478+
{ "kind" : "IdRef", "name" : "'Function'" },
10479+
{ "kind" : "LiteralInteger", "name" : "'Pipelined'" },
10480+
{ "kind" : "LiteralInteger", "name" : "'UseStallEnableClusters'" },
10481+
{ "kind" : "LiteralInteger", "name" : "'GetCapacity'" },
10482+
{ "kind" : "LiteralInteger", "name" : "'AsyncCapacity'" }
10483+
],
10484+
"capabilities" : [ "TaskSequenceINTEL" ],
10485+
"version" : "None"
10486+
},
10487+
{
10488+
"opname" : "OpTaskSequenceAsyncINTEL",
10489+
"class" : "Reserved",
10490+
"opcode" : 6164,
10491+
"operands" : [
10492+
{ "kind" : "IdRef", "name" : "'Sequence'" },
10493+
{ "kind" : "IdRef", "quantifier" : "*", "name" : "'Arguments'" }
10494+
],
10495+
"capabilities" : [ "TaskSequenceINTEL" ],
10496+
"version" : "None"
10497+
},
10498+
{
10499+
"opname" : "OpTaskSequenceGetINTEL",
10500+
"class" : "Reserved",
10501+
"opcode" : 6165,
10502+
"operands" : [
10503+
{ "kind" : "IdResultType" },
10504+
{ "kind" : "IdResult" },
10505+
{ "kind" : "IdRef", "name" : "'Sequence'" }
10506+
],
10507+
"capabilities" : [ "TaskSequenceINTEL" ],
10508+
"version" : "None"
10509+
},
10510+
{
10511+
"opname" : "OpTaskSequenceReleaseINTEL",
10512+
"class" : "Reserved",
10513+
"opcode" : 6166,
10514+
"operands" : [
10515+
{ "kind" : "IdRef", "name" : "'Sequence'" }
10516+
],
10517+
"capabilities" : [ "TaskSequenceINTEL" ],
10518+
"version" : "None"
10519+
},
10520+
{
10521+
"opname" : "OpTypeTaskSequenceINTEL",
10522+
"class" : "Type-Declaration",
10523+
"opcode" : 6199,
10524+
"operands" : [
10525+
{ "kind" : "IdResult" }
10526+
],
10527+
"capabilities" : [ "TaskSequenceINTEL" ],
10528+
"version": "None"
10529+
},
1047110530
{
1047210531
"opname" : "OpSubgroupBlockPrefetchINTEL",
1047310532
"class" : "Group",
@@ -17097,6 +17156,12 @@
1709717156
"extensions" : [ "SPV_INTEL_kernel_attributes" ],
1709817157
"version" : "None"
1709917158
},
17159+
{
17160+
"enumerant" : "TaskSequenceINTEL",
17161+
"value" : 6162,
17162+
"extensions" : [ "SPV_INTEL_task_sequence" ],
17163+
"version" : "None"
17164+
},
1710017165
{
1710117166
"enumerant" : "FPMaxErrorINTEL",
1710217167
"value" : 6169,

‎include/spirv/unified1/spirv.cs

+6
Original file line numberDiff line numberDiff line change
@@ -1290,6 +1290,7 @@ public enum Capability
12901290
ArithmeticFenceEXT = 6144,
12911291
FPGAClusterAttributesV2INTEL = 6150,
12921292
FPGAKernelAttributesv2INTEL = 6161,
1293+
TaskSequenceINTEL = 6162,
12931294
FPMaxErrorINTEL = 6169,
12941295
FPGALatencyControlINTEL = 6171,
12951296
FPGAArgumentInterfacesINTEL = 6174,
@@ -2411,6 +2412,11 @@ public enum Op
24112412
OpControlBarrierArriveINTEL = 6142,
24122413
OpControlBarrierWaitINTEL = 6143,
24132414
OpArithmeticFenceEXT = 6145,
2415+
OpTaskSequenceCreateINTEL = 6163,
2416+
OpTaskSequenceAsyncINTEL = 6164,
2417+
OpTaskSequenceGetINTEL = 6165,
2418+
OpTaskSequenceReleaseINTEL = 6166,
2419+
OpTypeTaskSequenceINTEL = 6199,
24142420
OpSubgroupBlockPrefetchINTEL = 6221,
24152421
OpSubgroup2DBlockLoadINTEL = 6231,
24162422
OpSubgroup2DBlockLoadTransformINTEL = 6232,

‎include/spirv/unified1/spirv.h

+17
Original file line numberDiff line numberDiff line change
@@ -1261,6 +1261,7 @@ typedef enum SpvCapability_ {
12611261
SpvCapabilityArithmeticFenceEXT = 6144,
12621262
SpvCapabilityFPGAClusterAttributesV2INTEL = 6150,
12631263
SpvCapabilityFPGAKernelAttributesv2INTEL = 6161,
1264+
SpvCapabilityTaskSequenceINTEL = 6162,
12641265
SpvCapabilityFPMaxErrorINTEL = 6169,
12651266
SpvCapabilityFPGALatencyControlINTEL = 6171,
12661267
SpvCapabilityFPGAArgumentInterfacesINTEL = 6174,
@@ -2348,6 +2349,11 @@ typedef enum SpvOp_ {
23482349
SpvOpControlBarrierArriveINTEL = 6142,
23492350
SpvOpControlBarrierWaitINTEL = 6143,
23502351
SpvOpArithmeticFenceEXT = 6145,
2352+
SpvOpTaskSequenceCreateINTEL = 6163,
2353+
SpvOpTaskSequenceAsyncINTEL = 6164,
2354+
SpvOpTaskSequenceGetINTEL = 6165,
2355+
SpvOpTaskSequenceReleaseINTEL = 6166,
2356+
SpvOpTypeTaskSequenceINTEL = 6199,
23512357
SpvOpSubgroupBlockPrefetchINTEL = 6221,
23522358
SpvOpSubgroup2DBlockLoadINTEL = 6231,
23532359
SpvOpSubgroup2DBlockLoadTransformINTEL = 6232,
@@ -3146,6 +3152,11 @@ inline void SpvHasResultAndType(SpvOp opcode, bool *hasResult, bool *hasResultTy
31463152
case SpvOpControlBarrierArriveINTEL: *hasResult = false; *hasResultType = false; break;
31473153
case SpvOpControlBarrierWaitINTEL: *hasResult = false; *hasResultType = false; break;
31483154
case SpvOpArithmeticFenceEXT: *hasResult = true; *hasResultType = true; break;
3155+
case SpvOpTaskSequenceCreateINTEL: *hasResult = true; *hasResultType = true; break;
3156+
case SpvOpTaskSequenceAsyncINTEL: *hasResult = false; *hasResultType = false; break;
3157+
case SpvOpTaskSequenceGetINTEL: *hasResult = true; *hasResultType = true; break;
3158+
case SpvOpTaskSequenceReleaseINTEL: *hasResult = false; *hasResultType = false; break;
3159+
case SpvOpTypeTaskSequenceINTEL: *hasResult = true; *hasResultType = false; break;
31493160
case SpvOpSubgroupBlockPrefetchINTEL: *hasResult = false; *hasResultType = false; break;
31503161
case SpvOpSubgroup2DBlockLoadINTEL: *hasResult = false; *hasResultType = false; break;
31513162
case SpvOpSubgroup2DBlockLoadTransformINTEL: *hasResult = false; *hasResultType = false; break;
@@ -4091,6 +4102,7 @@ inline const char* SpvCapabilityToString(SpvCapability value) {
40914102
case SpvCapabilityArithmeticFenceEXT: return "ArithmeticFenceEXT";
40924103
case SpvCapabilityFPGAClusterAttributesV2INTEL: return "FPGAClusterAttributesV2INTEL";
40934104
case SpvCapabilityFPGAKernelAttributesv2INTEL: return "FPGAKernelAttributesv2INTEL";
4105+
case SpvCapabilityTaskSequenceINTEL: return "TaskSequenceINTEL";
40944106
case SpvCapabilityFPMaxErrorINTEL: return "FPMaxErrorINTEL";
40954107
case SpvCapabilityFPGALatencyControlINTEL: return "FPGALatencyControlINTEL";
40964108
case SpvCapabilityFPGAArgumentInterfacesINTEL: return "FPGAArgumentInterfacesINTEL";
@@ -5066,6 +5078,11 @@ inline const char* SpvOpToString(SpvOp value) {
50665078
case SpvOpControlBarrierArriveINTEL: return "OpControlBarrierArriveINTEL";
50675079
case SpvOpControlBarrierWaitINTEL: return "OpControlBarrierWaitINTEL";
50685080
case SpvOpArithmeticFenceEXT: return "OpArithmeticFenceEXT";
5081+
case SpvOpTaskSequenceCreateINTEL: return "OpTaskSequenceCreateINTEL";
5082+
case SpvOpTaskSequenceAsyncINTEL: return "OpTaskSequenceAsyncINTEL";
5083+
case SpvOpTaskSequenceGetINTEL: return "OpTaskSequenceGetINTEL";
5084+
case SpvOpTaskSequenceReleaseINTEL: return "OpTaskSequenceReleaseINTEL";
5085+
case SpvOpTypeTaskSequenceINTEL: return "OpTypeTaskSequenceINTEL";
50695086
case SpvOpSubgroupBlockPrefetchINTEL: return "OpSubgroupBlockPrefetchINTEL";
50705087
case SpvOpSubgroup2DBlockLoadINTEL: return "OpSubgroup2DBlockLoadINTEL";
50715088
case SpvOpSubgroup2DBlockLoadTransformINTEL: return "OpSubgroup2DBlockLoadTransformINTEL";

‎include/spirv/unified1/spirv.hpp

+17
Original file line numberDiff line numberDiff line change
@@ -1257,6 +1257,7 @@ enum Capability {
12571257
CapabilityArithmeticFenceEXT = 6144,
12581258
CapabilityFPGAClusterAttributesV2INTEL = 6150,
12591259
CapabilityFPGAKernelAttributesv2INTEL = 6161,
1260+
CapabilityTaskSequenceINTEL = 6162,
12601261
CapabilityFPMaxErrorINTEL = 6169,
12611262
CapabilityFPGALatencyControlINTEL = 6171,
12621263
CapabilityFPGAArgumentInterfacesINTEL = 6174,
@@ -2344,6 +2345,11 @@ enum Op {
23442345
OpControlBarrierArriveINTEL = 6142,
23452346
OpControlBarrierWaitINTEL = 6143,
23462347
OpArithmeticFenceEXT = 6145,
2348+
OpTaskSequenceCreateINTEL = 6163,
2349+
OpTaskSequenceAsyncINTEL = 6164,
2350+
OpTaskSequenceGetINTEL = 6165,
2351+
OpTaskSequenceReleaseINTEL = 6166,
2352+
OpTypeTaskSequenceINTEL = 6199,
23472353
OpSubgroupBlockPrefetchINTEL = 6221,
23482354
OpSubgroup2DBlockLoadINTEL = 6231,
23492355
OpSubgroup2DBlockLoadTransformINTEL = 6232,
@@ -3142,6 +3148,11 @@ inline void HasResultAndType(Op opcode, bool *hasResult, bool *hasResultType) {
31423148
case OpControlBarrierArriveINTEL: *hasResult = false; *hasResultType = false; break;
31433149
case OpControlBarrierWaitINTEL: *hasResult = false; *hasResultType = false; break;
31443150
case OpArithmeticFenceEXT: *hasResult = true; *hasResultType = true; break;
3151+
case OpTaskSequenceCreateINTEL: *hasResult = true; *hasResultType = true; break;
3152+
case OpTaskSequenceAsyncINTEL: *hasResult = false; *hasResultType = false; break;
3153+
case OpTaskSequenceGetINTEL: *hasResult = true; *hasResultType = true; break;
3154+
case OpTaskSequenceReleaseINTEL: *hasResult = false; *hasResultType = false; break;
3155+
case OpTypeTaskSequenceINTEL: *hasResult = true; *hasResultType = false; break;
31453156
case OpSubgroupBlockPrefetchINTEL: *hasResult = false; *hasResultType = false; break;
31463157
case OpSubgroup2DBlockLoadINTEL: *hasResult = false; *hasResultType = false; break;
31473158
case OpSubgroup2DBlockLoadTransformINTEL: *hasResult = false; *hasResultType = false; break;
@@ -4087,6 +4098,7 @@ inline const char* CapabilityToString(Capability value) {
40874098
case CapabilityArithmeticFenceEXT: return "ArithmeticFenceEXT";
40884099
case CapabilityFPGAClusterAttributesV2INTEL: return "FPGAClusterAttributesV2INTEL";
40894100
case CapabilityFPGAKernelAttributesv2INTEL: return "FPGAKernelAttributesv2INTEL";
4101+
case CapabilityTaskSequenceINTEL: return "TaskSequenceINTEL";
40904102
case CapabilityFPMaxErrorINTEL: return "FPMaxErrorINTEL";
40914103
case CapabilityFPGALatencyControlINTEL: return "FPGALatencyControlINTEL";
40924104
case CapabilityFPGAArgumentInterfacesINTEL: return "FPGAArgumentInterfacesINTEL";
@@ -5062,6 +5074,11 @@ inline const char* OpToString(Op value) {
50625074
case OpControlBarrierArriveINTEL: return "OpControlBarrierArriveINTEL";
50635075
case OpControlBarrierWaitINTEL: return "OpControlBarrierWaitINTEL";
50645076
case OpArithmeticFenceEXT: return "OpArithmeticFenceEXT";
5077+
case OpTaskSequenceCreateINTEL: return "OpTaskSequenceCreateINTEL";
5078+
case OpTaskSequenceAsyncINTEL: return "OpTaskSequenceAsyncINTEL";
5079+
case OpTaskSequenceGetINTEL: return "OpTaskSequenceGetINTEL";
5080+
case OpTaskSequenceReleaseINTEL: return "OpTaskSequenceReleaseINTEL";
5081+
case OpTypeTaskSequenceINTEL: return "OpTypeTaskSequenceINTEL";
50655082
case OpSubgroupBlockPrefetchINTEL: return "OpSubgroupBlockPrefetchINTEL";
50665083
case OpSubgroup2DBlockLoadINTEL: return "OpSubgroup2DBlockLoadINTEL";
50675084
case OpSubgroup2DBlockLoadTransformINTEL: return "OpSubgroup2DBlockLoadTransformINTEL";

‎include/spirv/unified1/spirv.hpp11

+17
Original file line numberDiff line numberDiff line change
@@ -1257,6 +1257,7 @@ enum class Capability : unsigned {
12571257
ArithmeticFenceEXT = 6144,
12581258
FPGAClusterAttributesV2INTEL = 6150,
12591259
FPGAKernelAttributesv2INTEL = 6161,
1260+
TaskSequenceINTEL = 6162,
12601261
FPMaxErrorINTEL = 6169,
12611262
FPGALatencyControlINTEL = 6171,
12621263
FPGAArgumentInterfacesINTEL = 6174,
@@ -2344,6 +2345,11 @@ enum class Op : unsigned {
23442345
OpControlBarrierArriveINTEL = 6142,
23452346
OpControlBarrierWaitINTEL = 6143,
23462347
OpArithmeticFenceEXT = 6145,
2348+
OpTaskSequenceCreateINTEL = 6163,
2349+
OpTaskSequenceAsyncINTEL = 6164,
2350+
OpTaskSequenceGetINTEL = 6165,
2351+
OpTaskSequenceReleaseINTEL = 6166,
2352+
OpTypeTaskSequenceINTEL = 6199,
23472353
OpSubgroupBlockPrefetchINTEL = 6221,
23482354
OpSubgroup2DBlockLoadINTEL = 6231,
23492355
OpSubgroup2DBlockLoadTransformINTEL = 6232,
@@ -3142,6 +3148,11 @@ inline void HasResultAndType(Op opcode, bool *hasResult, bool *hasResultType) {
31423148
case Op::OpControlBarrierArriveINTEL: *hasResult = false; *hasResultType = false; break;
31433149
case Op::OpControlBarrierWaitINTEL: *hasResult = false; *hasResultType = false; break;
31443150
case Op::OpArithmeticFenceEXT: *hasResult = true; *hasResultType = true; break;
3151+
case Op::OpTaskSequenceCreateINTEL: *hasResult = true; *hasResultType = true; break;
3152+
case Op::OpTaskSequenceAsyncINTEL: *hasResult = false; *hasResultType = false; break;
3153+
case Op::OpTaskSequenceGetINTEL: *hasResult = true; *hasResultType = true; break;
3154+
case Op::OpTaskSequenceReleaseINTEL: *hasResult = false; *hasResultType = false; break;
3155+
case Op::OpTypeTaskSequenceINTEL: *hasResult = true; *hasResultType = false; break;
31453156
case Op::OpSubgroupBlockPrefetchINTEL: *hasResult = false; *hasResultType = false; break;
31463157
case Op::OpSubgroup2DBlockLoadINTEL: *hasResult = false; *hasResultType = false; break;
31473158
case Op::OpSubgroup2DBlockLoadTransformINTEL: *hasResult = false; *hasResultType = false; break;
@@ -4087,6 +4098,7 @@ inline const char* CapabilityToString(Capability value) {
40874098
case Capability::ArithmeticFenceEXT: return "ArithmeticFenceEXT";
40884099
case Capability::FPGAClusterAttributesV2INTEL: return "FPGAClusterAttributesV2INTEL";
40894100
case Capability::FPGAKernelAttributesv2INTEL: return "FPGAKernelAttributesv2INTEL";
4101+
case Capability::TaskSequenceINTEL: return "TaskSequenceINTEL";
40904102
case Capability::FPMaxErrorINTEL: return "FPMaxErrorINTEL";
40914103
case Capability::FPGALatencyControlINTEL: return "FPGALatencyControlINTEL";
40924104
case Capability::FPGAArgumentInterfacesINTEL: return "FPGAArgumentInterfacesINTEL";
@@ -5062,6 +5074,11 @@ inline const char* OpToString(Op value) {
50625074
case Op::OpControlBarrierArriveINTEL: return "OpControlBarrierArriveINTEL";
50635075
case Op::OpControlBarrierWaitINTEL: return "OpControlBarrierWaitINTEL";
50645076
case Op::OpArithmeticFenceEXT: return "OpArithmeticFenceEXT";
5077+
case Op::OpTaskSequenceCreateINTEL: return "OpTaskSequenceCreateINTEL";
5078+
case Op::OpTaskSequenceAsyncINTEL: return "OpTaskSequenceAsyncINTEL";
5079+
case Op::OpTaskSequenceGetINTEL: return "OpTaskSequenceGetINTEL";
5080+
case Op::OpTaskSequenceReleaseINTEL: return "OpTaskSequenceReleaseINTEL";
5081+
case Op::OpTypeTaskSequenceINTEL: return "OpTypeTaskSequenceINTEL";
50655082
case Op::OpSubgroupBlockPrefetchINTEL: return "OpSubgroupBlockPrefetchINTEL";
50665083
case Op::OpSubgroup2DBlockLoadINTEL: return "OpSubgroup2DBlockLoadINTEL";
50675084
case Op::OpSubgroup2DBlockLoadTransformINTEL: return "OpSubgroup2DBlockLoadTransformINTEL";

‎include/spirv/unified1/spirv.json

+6
Original file line numberDiff line numberDiff line change
@@ -1233,6 +1233,7 @@
12331233
"ArithmeticFenceEXT": 6144,
12341234
"FPGAClusterAttributesV2INTEL": 6150,
12351235
"FPGAKernelAttributesv2INTEL": 6161,
1236+
"TaskSequenceINTEL": 6162,
12361237
"FPMaxErrorINTEL": 6169,
12371238
"FPGALatencyControlINTEL": 6171,
12381239
"FPGAArgumentInterfacesINTEL": 6174,
@@ -2331,6 +2332,11 @@
23312332
"OpControlBarrierArriveINTEL": 6142,
23322333
"OpControlBarrierWaitINTEL": 6143,
23332334
"OpArithmeticFenceEXT": 6145,
2335+
"OpTaskSequenceCreateINTEL": 6163,
2336+
"OpTaskSequenceAsyncINTEL": 6164,
2337+
"OpTaskSequenceGetINTEL": 6165,
2338+
"OpTaskSequenceReleaseINTEL": 6166,
2339+
"OpTypeTaskSequenceINTEL": 6199,
23342340
"OpSubgroupBlockPrefetchINTEL": 6221,
23352341
"OpSubgroup2DBlockLoadINTEL": 6231,
23362342
"OpSubgroup2DBlockLoadTransformINTEL": 6232,

‎include/spirv/unified1/spirv.lua

+6
Original file line numberDiff line numberDiff line change
@@ -1248,6 +1248,7 @@ spv = {
12481248
ArithmeticFenceEXT = 6144,
12491249
FPGAClusterAttributesV2INTEL = 6150,
12501250
FPGAKernelAttributesv2INTEL = 6161,
1251+
TaskSequenceINTEL = 6162,
12511252
FPMaxErrorINTEL = 6169,
12521253
FPGALatencyControlINTEL = 6171,
12531254
FPGAArgumentInterfacesINTEL = 6174,
@@ -2335,6 +2336,11 @@ spv = {
23352336
OpControlBarrierArriveINTEL = 6142,
23362337
OpControlBarrierWaitINTEL = 6143,
23372338
OpArithmeticFenceEXT = 6145,
2339+
OpTaskSequenceCreateINTEL = 6163,
2340+
OpTaskSequenceAsyncINTEL = 6164,
2341+
OpTaskSequenceGetINTEL = 6165,
2342+
OpTaskSequenceReleaseINTEL = 6166,
2343+
OpTypeTaskSequenceINTEL = 6199,
23382344
OpSubgroupBlockPrefetchINTEL = 6221,
23392345
OpSubgroup2DBlockLoadINTEL = 6231,
23402346
OpSubgroup2DBlockLoadTransformINTEL = 6232,

‎include/spirv/unified1/spirv.py

+6
Original file line numberDiff line numberDiff line change
@@ -1219,6 +1219,7 @@
12191219
'ArithmeticFenceEXT' : 6144,
12201220
'FPGAClusterAttributesV2INTEL' : 6150,
12211221
'FPGAKernelAttributesv2INTEL' : 6161,
1222+
'TaskSequenceINTEL' : 6162,
12221223
'FPMaxErrorINTEL' : 6169,
12231224
'FPGALatencyControlINTEL' : 6171,
12241225
'FPGAArgumentInterfacesINTEL' : 6174,
@@ -2279,6 +2280,11 @@
22792280
'OpControlBarrierArriveINTEL' : 6142,
22802281
'OpControlBarrierWaitINTEL' : 6143,
22812282
'OpArithmeticFenceEXT' : 6145,
2283+
'OpTaskSequenceCreateINTEL' : 6163,
2284+
'OpTaskSequenceAsyncINTEL' : 6164,
2285+
'OpTaskSequenceGetINTEL' : 6165,
2286+
'OpTaskSequenceReleaseINTEL' : 6166,
2287+
'OpTypeTaskSequenceINTEL' : 6199,
22822288
'OpSubgroupBlockPrefetchINTEL' : 6221,
22832289
'OpSubgroup2DBlockLoadINTEL' : 6231,
22842290
'OpSubgroup2DBlockLoadTransformINTEL' : 6232,

‎include/spirv/unified1/spv.d

+6
Original file line numberDiff line numberDiff line change
@@ -1293,6 +1293,7 @@ enum Capability : uint
12931293
ArithmeticFenceEXT = 6144,
12941294
FPGAClusterAttributesV2INTEL = 6150,
12951295
FPGAKernelAttributesv2INTEL = 6161,
1296+
TaskSequenceINTEL = 6162,
12961297
FPMaxErrorINTEL = 6169,
12971298
FPGALatencyControlINTEL = 6171,
12981299
FPGAArgumentInterfacesINTEL = 6174,
@@ -2414,6 +2415,11 @@ enum Op : uint
24142415
OpControlBarrierArriveINTEL = 6142,
24152416
OpControlBarrierWaitINTEL = 6143,
24162417
OpArithmeticFenceEXT = 6145,
2418+
OpTaskSequenceCreateINTEL = 6163,
2419+
OpTaskSequenceAsyncINTEL = 6164,
2420+
OpTaskSequenceGetINTEL = 6165,
2421+
OpTaskSequenceReleaseINTEL = 6166,
2422+
OpTypeTaskSequenceINTEL = 6199,
24172423
OpSubgroupBlockPrefetchINTEL = 6221,
24182424
OpSubgroup2DBlockLoadINTEL = 6231,
24192425
OpSubgroup2DBlockLoadTransformINTEL = 6232,

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