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Name of 'module' needs to change when filename name is changed #31

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chrisnappi opened this issue Mar 15, 2019 · 1 comment

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chrisnappi commented Mar 15, 2019

@coreyeng
Fairly certain that when we specify --verilog_top_output_name the name of the module in the file needs to be changed to match.

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ginty commented Sep 13, 2019

I think this may be fixed by #43

ginty added a commit that referenced this issue


          Fix for #31

c8798ac

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