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8.0.2
Added examples/stm32cube
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103 files changed

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‎arm-cm/blinky_ek-tm4c123gxl/blinky.c

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -95,7 +95,8 @@ QState Blinky_initial(Blinky * const me, void const * const par) {
9595
// QS software tracing instrumentation (active only when Q_SPY is defined)
9696
QS_OBJ_DICTIONARY(AO_Blinky);
9797
QS_OBJ_DICTIONARY(&Blinky_inst.timeEvt);
98-
QS_SIG_DICTIONARY(TIMEOUT_SIG, (void*)0);
98+
QS_SIG_DICTIONARY(TIMEOUT_SIG, me);
99+
99100
QS_FUN_DICTIONARY(&Blinky_initial);
100101
QS_FUN_DICTIONARY(&Blinky_off);
101102
QS_FUN_DICTIONARY(&Blinky_on);

‎arm-cm/blinky_nucleo-c031c6/blinky.c

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -95,7 +95,8 @@ QState Blinky_initial(Blinky * const me, void const * const par) {
9595
// QS software tracing instrumentation (active only when Q_SPY is defined)
9696
QS_OBJ_DICTIONARY(AO_Blinky);
9797
QS_OBJ_DICTIONARY(&Blinky_inst.timeEvt);
98-
QS_SIG_DICTIONARY(TIMEOUT_SIG, (void*)0);
98+
QS_SIG_DICTIONARY(TIMEOUT_SIG, me);
99+
99100
QS_FUN_DICTIONARY(&Blinky_initial);
100101
QS_FUN_DICTIONARY(&Blinky_off);
101102
QS_FUN_DICTIONARY(&Blinky_on);

‎arm-cm/blinky_nucleo-c031c6/qk/bsp.c

Lines changed: 7 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -78,7 +78,7 @@ void assert_failed(char const * const module, int_t const id) {
7878
Q_onError(module, id);
7979
}
8080

81-
// ISRs used in the application ============================================
81+
// ISRs used in the application ==============================================
8282

8383
void SysTick_Handler(void); // prototype
8484
void SysTick_Handler(void) {
@@ -194,8 +194,6 @@ void QF_onStartup(void) {
194194
// ...
195195

196196
// enable IRQs...
197-
NVIC_EnableIRQ(EXTI0_1_IRQn);
198-
199197
#ifdef Q_SPY
200198
NVIC_EnableIRQ(USART2_IRQn); // UART2 interrupt used for QS-RX
201199
#endif
@@ -207,16 +205,15 @@ void QF_onCleanup(void) {
207205
void QK_onIdle(void) {
208206
// toggle an LED on and then off (not enough LEDs, see NOTE02)
209207
//QF_INT_DISABLE();
210-
//QF_MEM_SYS();
211208
//GPIOA->BSRR = (1U << LD4_PIN); // turn LED[n] on
212209
//GPIOA->BSRR = (1U << (LD4_PIN + 16U)); // turn LED[n] off
213-
//QF_MEM_APP();
214210
//QF_INT_ENABLE();
215211

216212
#ifdef Q_SPY
217213
QS_rxParse(); // parse all the received bytes
218214

219-
if ((USART2->ISR & (1U << 7U)) != 0U) { // TXE empty?
215+
// while Transmit Data Register Empty or TX-FIFO Not Full
216+
if ((USART2->ISR & USART_ISR_TXE_TXFNF_Msk) != 0U) { // TXE empty?
220217
QF_INT_DISABLE();
221218
uint16_t b = QS_getByte();
222219
QF_INT_ENABLE();
@@ -229,7 +226,6 @@ void QK_onIdle(void) {
229226
// Put the CPU and peripherals to the low-power mode.
230227
// you might need to customize the clock management for your application,
231228
// see the datasheet for your particular Cortex-M MCU.
232-
//
233229
__WFI(); // Wait-For-Interrupt
234230
#endif
235231
}
@@ -296,7 +292,7 @@ void QS_onCleanup(void) {
296292
}
297293
//............................................................................
298294
QSTimeCtr QS_onGetTime(void) { // NOTE: invoked with interrupts DISABLED
299-
if ((SysTick->CTRL & 0x00010000U) == 0U) { // not set?
295+
if ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == 0U) { // not set?
300296
return QS_tickTime_ - (QSTimeCtr)SysTick->VAL;
301297
}
302298
else { // the rollover occurred, but the SysTick_ISR did not run yet
@@ -311,7 +307,7 @@ void QS_onFlush(void) {
311307
for (;;) {
312308
uint16_t b = QS_getByte();
313309
if (b != QS_EOD) {
314-
while ((USART2->ISR & (1U << 7U)) == 0U) { // while TXE not empty
310+
while ((USART2->ISR & USART_ISR_TXE_TXFNF_Msk) == 0U) { // while TXE not empty
315311
}
316312
USART2->TDR = b;
317313
}
@@ -341,9 +337,9 @@ void QS_onCommand(uint8_t cmdId,
341337
// QK_ISR_ENTRY/QK_ISR_EXIT and they cannot post or publish events.
342338

343339
void USART2_IRQHandler(void); // prototype
344-
void USART2_IRQHandler(void) { // used in QS-RX (kernel UNAWARE interrutp)
340+
void USART2_IRQHandler(void) { // used in QS-RX (kernel UNAWARE interrupt)
345341
// is RX register NOT empty?
346-
if ((USART2->ISR & (1U << 5U)) != 0U) {
342+
if ((USART2->ISR & USART_ISR_RXNE_RXFNE_Msk) != 0U) {
347343
uint32_t b = USART2->RDR;
348344
QS_RX_PUT(b);
349345
}
@@ -352,7 +348,6 @@ void USART2_IRQHandler(void) { // used in QS-RX (kernel UNAWARE interrutp)
352348
}
353349

354350
#endif // Q_SPY
355-
//----------------------------------------------------------------------------
356351

357352
//============================================================================
358353
// NOTE1:

‎arm-cm/blinky_nucleo-c031c6/qv/bsp.c

Lines changed: 7 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -78,7 +78,7 @@ void assert_failed(char const * const module, int_t const id) {
7878
Q_onError(module, id);
7979
}
8080

81-
// ISRs used in the application ============================================
81+
// ISRs used in the application ==============================================
8282

8383
void SysTick_Handler(void); // prototype
8484
void SysTick_Handler(void) {
@@ -192,8 +192,6 @@ void QF_onStartup(void) {
192192
// ...
193193

194194
// enable IRQs...
195-
NVIC_EnableIRQ(EXTI0_1_IRQn);
196-
197195
#ifdef Q_SPY
198196
NVIC_EnableIRQ(USART2_IRQn); // UART2 interrupt used for QS-RX
199197
#endif
@@ -212,7 +210,8 @@ void QV_onIdle(void) { // called with interrupts DISABLED, see NOTE01
212210
QF_INT_ENABLE(); // enable interrupts
213211
QS_rxParse(); // parse all the received bytes
214212

215-
if ((USART2->ISR & (1U << 7U)) != 0U) { // TXE empty?
213+
// while Transmit Data Register Empty or TX-FIFO Not Full
214+
if ((USART2->ISR & USART_ISR_TXE_TXFNF_Msk) != 0U) { // TXE empty?
216215
QF_INT_DISABLE();
217216
uint16_t b = QS_getByte();
218217
QF_INT_ENABLE();
@@ -225,7 +224,6 @@ void QV_onIdle(void) { // called with interrupts DISABLED, see NOTE01
225224
// Put the CPU and peripherals to the low-power mode.
226225
// you might need to customize the clock management for your application,
227226
// see the datasheet for your particular Cortex-M MCU.
228-
//
229227
QV_CPU_SLEEP(); // atomically go to sleep and enable interrupts
230228
#else
231229
QF_INT_ENABLE(); // just enable interrupts
@@ -294,7 +292,7 @@ void QS_onCleanup(void) {
294292
}
295293
//............................................................................
296294
QSTimeCtr QS_onGetTime(void) { // NOTE: invoked with interrupts DISABLED
297-
if ((SysTick->CTRL & 0x00010000U) == 0U) { // not set?
295+
if ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == 0U) { // not set?
298296
return QS_tickTime_ - (QSTimeCtr)SysTick->VAL;
299297
}
300298
else { // the rollover occurred, but the SysTick_ISR did not run yet
@@ -309,7 +307,7 @@ void QS_onFlush(void) {
309307
for (;;) {
310308
uint16_t b = QS_getByte();
311309
if (b != QS_EOD) {
312-
while ((USART2->ISR & (1U << 7U)) == 0U) { // while TXE not empty
310+
while ((USART2->ISR & USART_ISR_TXE_TXFNF_Msk) == 0U) { // while TXE not empty
313311
}
314312
USART2->TDR = b;
315313
}
@@ -339,9 +337,9 @@ void QS_onCommand(uint8_t cmdId,
339337
// QK_ISR_ENTRY/QK_ISR_EXIT and they cannot post or publish events.
340338

341339
void USART2_IRQHandler(void); // prototype
342-
void USART2_IRQHandler(void) { // used in QS-RX (kernel UNAWARE interrutp)
340+
void USART2_IRQHandler(void) { // used in QS-RX (kernel UNAWARE interrupt)
343341
// is RX register NOT empty?
344-
if ((USART2->ISR & (1U << 5U)) != 0U) {
342+
if ((USART2->ISR & USART_ISR_RXNE_RXFNE_Msk) != 0U) {
345343
uint32_t b = USART2->RDR;
346344
QS_RX_PUT(b);
347345
}
@@ -350,7 +348,6 @@ void USART2_IRQHandler(void) { // used in QS-RX (kernel UNAWARE interrutp)
350348
}
351349

352350
#endif // Q_SPY
353-
//----------------------------------------------------------------------------
354351

355352
//============================================================================
356353
// NOTE1:

‎arm-cm/blinky_nucleo-c031c6/qxk/bsp.c

Lines changed: 8 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -78,7 +78,7 @@ void assert_failed(char const * const module, int_t const id) {
7878
Q_onError(module, id);
7979
}
8080

81-
// ISRs used in the application ============================================
81+
// ISRs used in the application ==============================================
8282

8383
void SysTick_Handler(void); // prototype
8484
void SysTick_Handler(void) {
@@ -203,8 +203,6 @@ void QF_onStartup(void) {
203203
// ...
204204

205205
// enable IRQs...
206-
NVIC_EnableIRQ(EXTI0_1_IRQn);
207-
208206
#ifdef Q_SPY
209207
NVIC_EnableIRQ(USART2_IRQn); // UART2 interrupt used for QS-RX
210208
#endif
@@ -216,16 +214,15 @@ void QF_onCleanup(void) {
216214
void QXK_onIdle(void) {
217215
// toggle an LED on and then off (not enough LEDs, see NOTE02)
218216
//QF_INT_DISABLE();
219-
//QF_MEM_SYS();
220217
//GPIOA->BSRR = (1U << LD4_PIN); // turn LED[n] on
221218
//GPIOA->BSRR = (1U << (LD4_PIN + 16U)); // turn LED[n] off
222-
//QF_MEM_APP();
223219
//QF_INT_ENABLE();
224220

225221
#ifdef Q_SPY
226222
QS_rxParse(); // parse all the received bytes
227223

228-
if ((USART2->ISR & (1U << 7U)) != 0U) { // TXE empty?
224+
// while Transmit Data Register Empty or TX-FIFO Not Full
225+
if ((USART2->ISR & USART_ISR_TXE_TXFNF_Msk) != 0U) { // TXE empty?
229226
QF_INT_DISABLE();
230227
uint16_t b = QS_getByte();
231228
QF_INT_ENABLE();
@@ -238,7 +235,6 @@ void QXK_onIdle(void) {
238235
// Put the CPU and peripherals to the low-power mode.
239236
// you might need to customize the clock management for your application,
240237
// see the datasheet for your particular Cortex-M MCU.
241-
//
242238
__WFI(); // Wait-For-Interrupt
243239
#endif
244240
}
@@ -305,7 +301,7 @@ void QS_onCleanup(void) {
305301
}
306302
//............................................................................
307303
QSTimeCtr QS_onGetTime(void) { // NOTE: invoked with interrupts DISABLED
308-
if ((SysTick->CTRL & 0x00010000U) == 0U) { // not set?
304+
if ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == 0U) { // not set?
309305
return QS_tickTime_ - (QSTimeCtr)SysTick->VAL;
310306
}
311307
else { // the rollover occurred, but the SysTick_ISR did not run yet
@@ -320,7 +316,7 @@ void QS_onFlush(void) {
320316
for (;;) {
321317
uint16_t b = QS_getByte();
322318
if (b != QS_EOD) {
323-
while ((USART2->ISR & (1U << 7U)) == 0U) { // while TXE not empty
319+
while ((USART2->ISR & USART_ISR_TXE_TXFNF_Msk) == 0U) { // while TXE not empty
324320
}
325321
USART2->TDR = b;
326322
}
@@ -346,13 +342,13 @@ void QS_onCommand(uint8_t cmdId,
346342
//............................................................................
347343
// ISR for receiving bytes from the QSPY Back-End
348344
// NOTE: This ISR is "QF-unaware" meaning that it does not interact with
349-
// the QF/QXK and is not disabled. Such ISRs don't need to call
350-
// QXK_ISR_ENTRY/QXK_ISR_EXIT and they cannot post or publish events.
345+
// the QF/QK and is not disabled. Such ISRs don't need to call
346+
// QK_ISR_ENTRY/QK_ISR_EXIT and they cannot post or publish events.
351347

352348
void USART2_IRQHandler(void); // prototype
353349
void USART2_IRQHandler(void) { // used in QS-RX (kernel UNAWARE interrupt)
354350
// is RX register NOT empty?
355-
if ((USART2->ISR & (1U << 5U)) != 0U) {
351+
if ((USART2->ISR & USART_ISR_RXNE_RXFNE_Msk) != 0U) {
356352
uint32_t b = USART2->RDR;
357353
QS_RX_PUT(b);
358354
}
@@ -361,7 +357,6 @@ void USART2_IRQHandler(void) { // used in QS-RX (kernel UNAWARE interrupt)
361357
}
362358

363359
#endif // Q_SPY
364-
//----------------------------------------------------------------------------
365360

366361
//============================================================================
367362
// NOTE1:

‎arm-cm/blinky_nucleo-u545re/blinky.c

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -95,7 +95,8 @@ QState Blinky_initial(Blinky * const me, void const * const par) {
9595
// QS software tracing instrumentation (active only when Q_SPY is defined)
9696
QS_OBJ_DICTIONARY(AO_Blinky);
9797
QS_OBJ_DICTIONARY(&Blinky_inst.timeEvt);
98-
QS_SIG_DICTIONARY(TIMEOUT_SIG, (void*)0);
98+
QS_SIG_DICTIONARY(TIMEOUT_SIG, me);
99+
99100
QS_FUN_DICTIONARY(&Blinky_initial);
100101
QS_FUN_DICTIONARY(&Blinky_off);
101102
QS_FUN_DICTIONARY(&Blinky_on);

‎arm-cm/blinky_nucleo-u545re/qk/bsp.c

Lines changed: 18 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -68,7 +68,7 @@ Q_NORETURN Q_onError(char const * const module, int_t const id) {
6868
// (assuming that you ship your production code with assertions enabled).
6969
Q_UNUSED_PAR(module);
7070
Q_UNUSED_PAR(id);
71-
QS_ASSERTION(module, id, 10000U);
71+
QS_ASSERTION(module, id, 10000U); // report assertion to QS
7272

7373
#ifndef NDEBUG
7474
// light up the user LED
@@ -88,7 +88,7 @@ void assert_failed(char const * const module, int_t const id) {
8888
Q_onError(module, id);
8989
}
9090

91-
// ISRs used in the application ============================================
91+
// ISRs used in the application ==============================================
9292

9393
void SysTick_Handler(void); // prototype
9494
void SysTick_Handler(void) {
@@ -114,39 +114,40 @@ static void STM32U545RE_MPU_setup(void) {
114114

115115
MPU->RNR = 0U; // region 0 (for ROM: read-only, can-execute)
116116
MPU->RBAR = ARM_MPU_RBAR(0x08000000U,
117-
ARM_MPU_SH_NON,
118-
ARM_MPU_AP_RO,
119-
ARM_MPU_AP_PO,
120-
ARM_MPU_EX);
117+
ARM_MPU_SH_NON, // SH: Normal memory (not-shareable)
118+
1U, // RO: Normal memory, read-only
119+
0U, // NP: Normal memory, privileged access only
120+
0U); // XN: eXecute never (disabled)
121121
MPU->RLAR = ARM_MPU_RLAR(0x0807FFFFU, 0U);
122122

123123
MPU->RNR = 1U; // region 0 (for RAM1: read-write, execute-never)
124124
MPU->RBAR = ARM_MPU_RBAR(0x20000000U,
125-
ARM_MPU_SH_OUTER,
126-
ARM_MPU_AP_RW,
127-
ARM_MPU_AP_PO,
128-
ARM_MPU_XN);
125+
ARM_MPU_SH_OUTER, // SH: Normal memory (outer shareable)
126+
0U, // RO: Normal memory, read/write
127+
0U, // NP: Normal memory, privileged access only
128+
1U); // XN: eXecute never
129129
MPU->RLAR = ARM_MPU_RLAR(0x2003FFFFU, 0U);
130130

131131
MPU->RNR = 2U; // region 0 (for RAM2: read-write, execute-never)
132132
MPU->RBAR = ARM_MPU_RBAR(0x28000000U,
133-
ARM_MPU_SH_OUTER,
134-
ARM_MPU_AP_RW,
135-
ARM_MPU_AP_PO,
136-
ARM_MPU_XN);
133+
ARM_MPU_SH_OUTER, // SH: Normal memory (outer shareable)
134+
0U, // RO: Normal memory, read/write
135+
0U, // NP: Normal memory, privileged access only
136+
1U); // XN: eXecute never
137137
MPU->RLAR = ARM_MPU_RLAR(0x28003FFFU, 0U);
138138

139139
// Enable MPU with all region definitions
140140
__DMB();
141-
MPU->CTRL = MPU_CTRL_PRIVDEFENA_Msk | MPU_CTRL_ENABLE_Msk;
141+
MPU->CTRL = MPU_CTRL_PRIVDEFENA_Msk
142+
| MPU_CTRL_HFNMIENA_Msk
143+
| MPU_CTRL_ENABLE_Msk;
142144

143145
// Enable MemManage Faults
144146
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
145147
__DSB();
146148
__ISB();
147149
}
148-
149-
// BSP functions ===========================================================
150+
//..........................................................................
150151
void BSP_init(void) {
151152
// setup the MPU...
152153
STM32U545RE_MPU_setup();

‎arm-cm/blinky_nucleo-u545re/qp_config.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -199,7 +199,7 @@
199199
// <c2>Kernel uses critical section based on BASEPRI (QF_USE_BASEPRI)
200200
// <i>If not selected, critical section will be based on PRIMASK
201201
// <i>NOTE: The BASEPRI threshold can be adjusted in the "Text Editor" mode.
202-
//#define QF_USE_BASEPRI 0x3F
202+
#define QF_USE_BASEPRI 0x3F
203203
// </c>
204204
#endif // (__ARM_ARCH > 6)
205205

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