From 37bf2295c960a37bf57ee78975f63f4dca92b13d Mon Sep 17 00:00:00 2001 From: Maxime Meignan Date: Fri, 24 Jan 2025 16:38:36 +0100 Subject: [PATCH] aarch64: implements lifting (intrinsics) for LDXP/STXP --- arch/arm64/arch_arm64.cpp | 4 ++++ arch/arm64/il.cpp | 6 ++++++ arch/arm64/il.h | 2 ++ 3 files changed, 12 insertions(+) diff --git a/arch/arm64/arch_arm64.cpp b/arch/arm64/arch_arm64.cpp index 4931ca6d2..71bf21b9b 100644 --- a/arch/arm64/arch_arm64.cpp +++ b/arch/arm64/arch_arm64.cpp @@ -1004,6 +1004,8 @@ class Arm64Architecture : public Architecture return "__ldxrb"; case ARM64_INTRIN_LDXRH: return "__ldxrh"; + case ARM64_INTRIN_LDXP: + return "__ldxp"; case ARM64_INTRIN_LDAXR: return "__ldaxr"; case ARM64_INTRIN_LDAXRB: @@ -1016,6 +1018,8 @@ class Arm64Architecture : public Architecture return "__stxrb"; case ARM64_INTRIN_STXRH: return "__stxrh"; + case ARM64_INTRIN_STXP: + return "__stxp"; case ARM64_INTRIN_STLXR: return "__stlxr"; case ARM64_INTRIN_STLXRB: diff --git a/arch/arm64/il.cpp b/arch/arm64/il.cpp index 8ab06a061..0d367beb7 100644 --- a/arch/arm64/il.cpp +++ b/arch/arm64/il.cpp @@ -2016,6 +2016,9 @@ bool GetLowLevelILForInstruction( case ARM64_LDXRH: il.AddInstruction(il.Intrinsic({ RegisterOrFlag::Register(REG_O(operand1)) }, ARM64_INTRIN_LDXRH, { ILREG_O(operand2) })); // We don't have a way to specify intrinsic register size, so we explicitly embed the size in the intrinsic name. + case ARM64_LDXP: + il.AddInstruction(il.Intrinsic({ RegisterOrFlag::Register(REG_O(operand1)), RegisterOrFlag::Register(REG_O(operand2)) }, ARM64_INTRIN_LDXP, { ILREG_O(operand3) })); + break; case ARM64_LDAXR: il.AddInstruction(il.Intrinsic({ RegisterOrFlag::Register(REG_O(operand1)) }, ARM64_INTRIN_LDAXR, { ILREG_O(operand2) })); break; @@ -2034,6 +2037,9 @@ bool GetLowLevelILForInstruction( case ARM64_STXRH: il.AddInstruction(il.Intrinsic({ RegisterOrFlag::Register(REG_O(operand1)) }, ARM64_INTRIN_STXRH, { ILREG_O(operand2), ILREG_O(operand3) })); break; + case ARM64_STXP: + il.AddInstruction(il.Intrinsic({ RegisterOrFlag::Register(REG_O(operand1)) }, ARM64_INTRIN_STXP, { ILREG_O(operand2), ILREG_O(operand3), ILREG_O(operand4) })); + break; case ARM64_STLXR: il.AddInstruction(il.Intrinsic({ RegisterOrFlag::Register(REG_O(operand1)) }, ARM64_INTRIN_STLXR, { ILREG_O(operand2), ILREG_O(operand3) })); break; diff --git a/arch/arm64/il.h b/arch/arm64/il.h index e345e3955..ba1a52da1 100644 --- a/arch/arm64/il.h +++ b/arch/arm64/il.h @@ -80,12 +80,14 @@ enum Arm64Intrinsic : uint32_t ARM64_INTRIN_LDXR, ARM64_INTRIN_LDXRB, ARM64_INTRIN_LDXRH, + ARM64_INTRIN_LDXP, ARM64_INTRIN_LDAXR, ARM64_INTRIN_LDAXRB, ARM64_INTRIN_LDAXRH, ARM64_INTRIN_STXR, ARM64_INTRIN_STXRB, ARM64_INTRIN_STXRH, + ARM64_INTRIN_STXP, ARM64_INTRIN_STLXR, ARM64_INTRIN_STLXRB, ARM64_INTRIN_STLXRH,