LLVM Scheduling Model!

[lenary]

I think I threatened to make one of these a while ago on twitter… finally sat down and started one this weekend: https://reviews.llvm.org/D78910

I'm not sure I have the model entirely correct, and tbh improving instruction selection in the LLVM RISC-V backend will make a bigger difference than improving instruction scheduling, but I am interested to see if it helps at all.

I also know I don't have forwarding entirely correct yet, and probably some of the other latencies are incorrect too. I though I'd at least show you before it was finished and merged so you could have some input.

[Wren6991]

Wow! This is far out of my wheelhouse, but at a first glance the parameters in that .td file look correct to me.

I'm not sure about this

  // RISCBoy has some funky instruction fetch fun
  let LoopMicroOpBufferSize = 2;

I do have a prefetch queue, mostly for timing reasons oddly enough, but it gets flushed on any branch, predicted or no. You just flush twice on a mispredict :)

I will do a pass over the processor documentation and make sure it is all strictly accurate, to save your from wasting time. In particular I think I am dropping the plugin idea.

[Wren6991]

Load-use is indeed two cycles, but there is a load-to-store forward, so for that particular case (back-to-back load store) you don't pay the penalty cycle. This is mostly a waste of gates except perhaps for memcpy.

[lenary]

Yeah, I'm not sure about the LoopMicroOpBufferSize which may just be for OoO cores.

There is a way to tell the scheduling model you have forwarding, I just haven't worked out exactly how to write it correctly.

[lenary]

I haven't got around to updating this, but I see you've spun off a new repo for Hazard5 - should I rename the model to give the core that name instead?

[Wren6991]

Yep, no rush -- I'm going to move the documentation over there too, and will do an update pass over it when I do that. I'll also add some friendlier test environment like a Verilator model so that people can run code against the core and get accurate cycle counts

[Wren6991]

Yeah Hazard5 is the CPU, RISCBoy is the games console!