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RISC-V: Rounding mode on widening instructions
This commit adds support for rounding modes on widening instructions to the assembler/disassembler. On the disassembler, non-default rounding mode is displayed when "no-aliases" option is given or the rounding mode itself is invalid. On the assembler, specifying such rounding modes is prohibited unless we have supported in the past. gas/ChangeLog: * config/tc-riscv.c (validate_riscv_insn): Add rounding mode support to widening instructions. (riscv_ip): Likewise. * testsuite/gas/riscv/rounding-dis-widening.d: New disasm test. * testsuite/gas/riscv/rounding-dis-widening.s: Likewise. * testsuite/gas/riscv/rounding-dis-widening-na.d: Likewise. * testsuite/gas/riscv/rounding-fail.d: Add testcases for widening instructions. * testsuite/gas/riscv/rounding-fail.l: Likewise. * testsuite/gas/riscv/rounding-fail.s: Likewise. * testsuite/gas/riscv/rounding-fcvt.q.l.d: New test. * testsuite/gas/riscv/rounding-fcvt.q.l.l: Likewise. * testsuite/gas/riscv/rounding-fcvt.q.l.s: Likewise. * testsuite/gas/riscv/rounding-fcvt.q.l-na.d: Likewise. opcodes/ChangeLog: * riscv-dis.c (print_insn_args): Add rounding mode support to widening instructions. * riscv-opc.c (riscv_opcodes): Use new operand types. Idea-by: Tsukasa OI <[email protected]> Idea-by: S Pawan Kumar <[email protected]>
1 parent 974f49d commit 7b801ac

13 files changed

+155
-15
lines changed

‎gas/config/tc-riscv.c

Lines changed: 29 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1430,6 +1430,8 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length)
14301430
case 'f':
14311431
switch (*++oparg)
14321432
{
1433+
case 'M': /* Fall through. */
1434+
case 'm': USE_BITS (OP_MASK_RM, OP_SH_RM); break;
14331435
case 'v': USE_BITS (OP_MASK_RS1, OP_SH_RS1); break;
14341436
default:
14351437
goto unknown_validate_operand;
@@ -3526,6 +3528,33 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
35263528
case 'f':
35273529
switch (*++oparg)
35283530
{
3531+
case 'M':
3532+
case 'm':
3533+
/* Optional rounding mode (widening conversion)
3534+
'M': operand either disallowed or not recommended
3535+
(considered to be non-useful to normal software).
3536+
'm': operand allowed for compatibility reasons
3537+
(display a warning instead). */
3538+
if (*asarg == '\0')
3539+
{
3540+
INSERT_OPERAND (RM, *ip, 0);
3541+
continue;
3542+
}
3543+
else if (*asarg == ',' && asarg++
3544+
&& arg_lookup (&asarg, riscv_rm,
3545+
ARRAY_SIZE (riscv_rm), &regno))
3546+
{
3547+
INSERT_OPERAND (RM, *ip, regno);
3548+
if (*oparg == 'M')
3549+
as_bad (_ ("rounding mode cannot be specified "
3550+
"on widening conversion"));
3551+
else
3552+
as_warn (
3553+
_ ("specifying a rounding mode is strongly "
3554+
"discourged on widening conversion"));
3555+
continue;
3556+
}
3557+
break;
35293558
case 'v':
35303559
/* FLI.[HSDQ] value field for 'Zfa' extension. */
35313560
if (!arg_lookup (&asarg, riscv_fli_symval,

‎gas/testsuite/gas/riscv/rounding-dis-widening-na.d

Lines changed: 13 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,13 @@
1+
#as: -march=rv32ifd
2+
#source: rounding-dis-widening.s
3+
#objdump: -d -M no-aliases
4+
5+
.*:[ ]+file format .*
6+
7+
8+
Disassembly of section .text:
9+
10+
0+000 <target>:
11+
[ ]+[0-9a-f]+:[ ]+420100d3[ ]+fcvt\.d\.s[ ]+ft1,ft2
12+
[ ]+[0-9a-f]+:[ ]+420100d3[ ]+fcvt\.d\.s[ ]+ft1,ft2
13+
[ ]+[0-9a-f]+:[ ]+420170d3[ ]+fcvt\.d\.s[ ]+ft1,ft2,dyn

‎gas/testsuite/gas/riscv/rounding-dis-widening.d

Lines changed: 13 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,13 @@
1+
#as: -march=rv32ifd
2+
#source: rounding-dis-widening.s
3+
#objdump: -d
4+
5+
.*:[ ]+file format .*
6+
7+
8+
Disassembly of section .text:
9+
10+
0+000 <target>:
11+
[ ]+[0-9a-f]+:[ ]+420100d3[ ]+fcvt\.d\.s[ ]+ft1,ft2
12+
[ ]+[0-9a-f]+:[ ]+420100d3[ ]+fcvt\.d\.s[ ]+ft1,ft2
13+
[ ]+[0-9a-f]+:[ ]+420170d3[ ]+fcvt\.d\.s[ ]+ft1,ft2

‎gas/testsuite/gas/riscv/rounding-dis-widening.s

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,8 @@
1+
target:
2+
fcvt.d.s ft1, ft2
3+
# Standard encoding:
4+
# - 2nd operand is the rounding mode (RNE [0b000] is preferred).
5+
# - 6th operand (additional function) is zero for FCVT.D.S.
6+
.insn r OP_FP, 0x0, 0x21, ft1, ft2, f0
7+
# Non-standard encoding
8+
.insn r OP_FP, 0x7, 0x21, ft1, ft2, f0

‎gas/testsuite/gas/riscv/rounding-fail.d

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,3 +1,3 @@
1-
#as: -march=rv32ifd
1+
#as: -march=rv32ifdq_zfh
22
#source: rounding-fail.s
33
#error_output: rounding-fail.l

‎gas/testsuite/gas/riscv/rounding-fail.l

Lines changed: 11 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -3,3 +3,14 @@
33
.*: Error: illegal operands `fadd.d fa1,fa1,fa1,'
44
.*: Error: illegal operands `fadd.s fa1,fa1,fa1,unknown'
55
.*: Error: illegal operands `fadd.d fa1,fa1,fa1,unknown'
6+
.*: Error: rounding mode cannot be specified on widening conversion
7+
.*: Error: rounding mode cannot be specified on widening conversion
8+
.*: Error: rounding mode cannot be specified on widening conversion
9+
.*: Error: rounding mode cannot be specified on widening conversion
10+
.*: Error: rounding mode cannot be specified on widening conversion
11+
.*: Error: rounding mode cannot be specified on widening conversion
12+
.*: Error: rounding mode cannot be specified on widening conversion
13+
.*: Error: rounding mode cannot be specified on widening conversion
14+
.*: Error: rounding mode cannot be specified on widening conversion
15+
.*: Error: rounding mode cannot be specified on widening conversion
16+
.*: Error: illegal operands `fcvt\.q\.wu ft1,t0,unknown'

‎gas/testsuite/gas/riscv/rounding-fail.s

Lines changed: 16 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -5,3 +5,19 @@ target:
55
# Invalid rounding mode
66
fadd.s fa1,fa1,fa1,unknown
77
fadd.d fa1,fa1,fa1,unknown
8+
9+
# Rounding mode cannot be specified on widening conversion
10+
# unless we have supported in the past.
11+
fcvt.s.h ft1,ft2,dyn
12+
fcvt.d.h ft1,ft2,dyn
13+
fcvt.q.h ft1,ft2,dyn
14+
fcvt.d.s ft1,ft2,dyn
15+
fcvt.q.s ft1,ft2,dyn
16+
fcvt.q.d ft1,ft2,dyn
17+
fcvt.d.w ft1,t0,dyn
18+
fcvt.d.wu ft1,t0,dyn
19+
fcvt.q.w ft1,t0,dyn
20+
fcvt.q.wu ft1,t0,dyn
21+
22+
# Different error message because of an invalid rounding mode
23+
fcvt.q.wu ft1,t0,unknown

‎gas/testsuite/gas/riscv/rounding-fcvt.q.l-na.d

Lines changed: 15 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,15 @@
1+
#as: -march=rv64ifdq
2+
#source: rounding-fcvt.q.l.s
3+
#warning_output: rounding-fcvt.q.l.l
4+
#objdump: -d -M no-aliases
5+
6+
.*:[ ]+file format .*
7+
8+
9+
Disassembly of section .text:
10+
11+
0+000 <target>:
12+
[ ]+[0-9a-f]+:[ ]+d62280d3[ ]+fcvt\.q\.l[ ]+ft1,t0
13+
[ ]+[0-9a-f]+:[ ]+d622f0d3[ ]+fcvt\.q\.l[ ]+ft1,t0,dyn
14+
[ ]+[0-9a-f]+:[ ]+d63280d3[ ]+fcvt\.q\.lu[ ]+ft1,t0
15+
[ ]+[0-9a-f]+:[ ]+d632f0d3[ ]+fcvt\.q\.lu[ ]+ft1,t0,dyn

‎gas/testsuite/gas/riscv/rounding-fcvt.q.l.d

Lines changed: 15 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,15 @@
1+
#as: -march=rv64ifdq
2+
#source: rounding-fcvt.q.l.s
3+
#warning_output: rounding-fcvt.q.l.l
4+
#objdump: -d
5+
6+
.*:[ ]+file format .*
7+
8+
9+
Disassembly of section .text:
10+
11+
0+000 <target>:
12+
[ ]+[0-9a-f]+:[ ]+d62280d3[ ]+fcvt\.q\.l[ ]+ft1,t0
13+
[ ]+[0-9a-f]+:[ ]+d622f0d3[ ]+fcvt\.q\.l[ ]+ft1,t0
14+
[ ]+[0-9a-f]+:[ ]+d63280d3[ ]+fcvt\.q\.lu[ ]+ft1,t0
15+
[ ]+[0-9a-f]+:[ ]+d632f0d3[ ]+fcvt\.q\.lu[ ]+ft1,t0

‎gas/testsuite/gas/riscv/rounding-fcvt.q.l.l

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,3 @@
1+
.*: Assembler messages:
2+
.*: Warning: specifying a rounding mode is strongly discourged on widening conversion
3+
.*: Warning: specifying a rounding mode is strongly discourged on widening conversion

‎gas/testsuite/gas/riscv/rounding-fcvt.q.l.s

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,5 @@
1+
target:
2+
fcvt.q.l ft1,t0
3+
fcvt.q.l ft1,t0,dyn
4+
fcvt.q.lu ft1,t0
5+
fcvt.q.lu ft1,t0,dyn

‎opcodes/riscv-dis.c

Lines changed: 14 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -601,6 +601,20 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info
601601
case 'f':
602602
switch (*++oparg)
603603
{
604+
case 'M': /* Fall through. */
605+
case 'm':
606+
/* Optional rounding mode (widening conversion)
607+
which defaults to RNE (0b000).
608+
Display non-default rounding mode if:
609+
1. rounding mode is invalid or
610+
2. 'no-aliases' option is specified. */
611+
if (EXTRACT_OPERAND (RM, l) == 0
612+
|| (!no_aliases && riscv_rm[EXTRACT_OPERAND (RM, l)]))
613+
break;
614+
print (info->stream, dis_style_text, ",");
615+
arg_print (info, EXTRACT_OPERAND (RM, l), riscv_rm,
616+
ARRAY_SIZE (riscv_rm));
617+
break;
604618
case 'v':
605619
if (riscv_fli_symval[rs1])
606620
print (info->stream, dis_style_text, "%s",

‎opcodes/riscv-opc.c

Lines changed: 12 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -702,9 +702,9 @@ const struct riscv_opcode riscv_opcodes[] =
702702
{"fcvt.h.w", 0, INSN_CLASS_ZFH_INX, "D,s,m", MATCH_FCVT_H_W, MASK_FCVT_H_W, match_opcode, 0 },
703703
{"fcvt.h.wu", 0, INSN_CLASS_ZFH_INX, "D,s", MATCH_FCVT_H_WU|MASK_RM, MASK_FCVT_H_WU|MASK_RM, match_opcode, 0 },
704704
{"fcvt.h.wu", 0, INSN_CLASS_ZFH_INX, "D,s,m", MATCH_FCVT_H_WU, MASK_FCVT_H_WU, match_opcode, 0 },
705-
{"fcvt.s.h", 0, INSN_CLASS_ZFHMIN_INX, "D,S", MATCH_FCVT_S_H, MASK_FCVT_S_H|MASK_RM, match_opcode, 0 },
706-
{"fcvt.d.h", 0, INSN_CLASS_ZFHMIN_AND_D_INX, "D,S", MATCH_FCVT_D_H, MASK_FCVT_D_H|MASK_RM, match_opcode, 0 },
707-
{"fcvt.q.h", 0, INSN_CLASS_ZFHMIN_AND_Q_INX, "D,S", MATCH_FCVT_Q_H, MASK_FCVT_Q_H|MASK_RM, match_opcode, 0 },
705+
{"fcvt.s.h", 0, INSN_CLASS_ZFHMIN_INX, "D,SWfM", MATCH_FCVT_S_H, MASK_FCVT_S_H, match_opcode, 0 },
706+
{"fcvt.d.h", 0, INSN_CLASS_ZFHMIN_AND_D_INX, "D,SWfM", MATCH_FCVT_D_H, MASK_FCVT_D_H, match_opcode, 0 },
707+
{"fcvt.q.h", 0, INSN_CLASS_ZFHMIN_AND_Q_INX, "D,SWfM", MATCH_FCVT_Q_H, MASK_FCVT_Q_H, match_opcode, 0 },
708708
{"fcvt.h.s", 0, INSN_CLASS_ZFHMIN_INX, "D,S", MATCH_FCVT_H_S|MASK_RM, MASK_FCVT_H_S|MASK_RM, match_opcode, 0 },
709709
{"fcvt.h.s", 0, INSN_CLASS_ZFHMIN_INX, "D,S,m", MATCH_FCVT_H_S, MASK_FCVT_H_S, match_opcode, 0 },
710710
{"fcvt.h.d", 0, INSN_CLASS_ZFHMIN_AND_D_INX, "D,S", MATCH_FCVT_H_D|MASK_RM, MASK_FCVT_H_D|MASK_RM, match_opcode, 0 },
@@ -843,9 +843,9 @@ const struct riscv_opcode riscv_opcodes[] =
843843
{"fcvt.w.d", 0, INSN_CLASS_D_INX, "d,S,m", MATCH_FCVT_W_D, MASK_FCVT_W_D, match_opcode, 0 },
844844
{"fcvt.wu.d", 0, INSN_CLASS_D_INX, "d,S", MATCH_FCVT_WU_D|MASK_RM, MASK_FCVT_WU_D|MASK_RM, match_opcode, 0 },
845845
{"fcvt.wu.d", 0, INSN_CLASS_D_INX, "d,S,m", MATCH_FCVT_WU_D, MASK_FCVT_WU_D, match_opcode, 0 },
846-
{"fcvt.d.w", 0, INSN_CLASS_D_INX, "D,s", MATCH_FCVT_D_W, MASK_FCVT_D_W|MASK_RM, match_opcode, 0 },
847-
{"fcvt.d.wu", 0, INSN_CLASS_D_INX, "D,s", MATCH_FCVT_D_WU, MASK_FCVT_D_WU|MASK_RM, match_opcode, 0 },
848-
{"fcvt.d.s", 0, INSN_CLASS_D_INX, "D,S", MATCH_FCVT_D_S, MASK_FCVT_D_S|MASK_RM, match_opcode, 0 },
846+
{"fcvt.d.w", 0, INSN_CLASS_D_INX, "D,sWfM", MATCH_FCVT_D_W, MASK_FCVT_D_W, match_opcode, 0 },
847+
{"fcvt.d.wu", 0, INSN_CLASS_D_INX, "D,sWfM", MATCH_FCVT_D_WU, MASK_FCVT_D_WU, match_opcode, 0 },
848+
{"fcvt.d.s", 0, INSN_CLASS_D_INX, "D,SWfM", MATCH_FCVT_D_S, MASK_FCVT_D_S, match_opcode, 0 },
849849
{"fcvt.s.d", 0, INSN_CLASS_D_INX, "D,S", MATCH_FCVT_S_D|MASK_RM, MASK_FCVT_S_D|MASK_RM, match_opcode, 0 },
850850
{"fcvt.s.d", 0, INSN_CLASS_D_INX, "D,S,m", MATCH_FCVT_S_D, MASK_FCVT_S_D, match_opcode, 0 },
851851
{"fclass.d", 0, INSN_CLASS_D_INX, "d,S", MATCH_FCLASS_D, MASK_FCLASS_D, match_opcode, 0 },
@@ -900,10 +900,10 @@ const struct riscv_opcode riscv_opcodes[] =
900900
{"fcvt.w.q", 0, INSN_CLASS_Q_INX, "d,S,m", MATCH_FCVT_W_Q, MASK_FCVT_W_Q, match_opcode, 0 },
901901
{"fcvt.wu.q", 0, INSN_CLASS_Q_INX, "d,S", MATCH_FCVT_WU_Q|MASK_RM, MASK_FCVT_WU_Q|MASK_RM, match_opcode, 0 },
902902
{"fcvt.wu.q", 0, INSN_CLASS_Q_INX, "d,S,m", MATCH_FCVT_WU_Q, MASK_FCVT_WU_Q, match_opcode, 0 },
903-
{"fcvt.q.w", 0, INSN_CLASS_Q_INX, "D,s", MATCH_FCVT_Q_W, MASK_FCVT_Q_W|MASK_RM, match_opcode, 0 },
904-
{"fcvt.q.wu", 0, INSN_CLASS_Q_INX, "D,s", MATCH_FCVT_Q_WU, MASK_FCVT_Q_WU|MASK_RM, match_opcode, 0 },
905-
{"fcvt.q.s", 0, INSN_CLASS_Q_INX, "D,S", MATCH_FCVT_Q_S, MASK_FCVT_Q_S|MASK_RM, match_opcode, 0 },
906-
{"fcvt.q.d", 0, INSN_CLASS_Q_INX, "D,S", MATCH_FCVT_Q_D, MASK_FCVT_Q_D|MASK_RM, match_opcode, 0 },
903+
{"fcvt.q.w", 0, INSN_CLASS_Q_INX, "D,sWfM", MATCH_FCVT_Q_W, MASK_FCVT_Q_W, match_opcode, 0 },
904+
{"fcvt.q.wu", 0, INSN_CLASS_Q_INX, "D,sWfM", MATCH_FCVT_Q_WU, MASK_FCVT_Q_WU, match_opcode, 0 },
905+
{"fcvt.q.s", 0, INSN_CLASS_Q_INX, "D,SWfM", MATCH_FCVT_Q_S, MASK_FCVT_Q_S, match_opcode, 0 },
906+
{"fcvt.q.d", 0, INSN_CLASS_Q_INX, "D,SWfM", MATCH_FCVT_Q_D, MASK_FCVT_Q_D, match_opcode, 0 },
907907
{"fcvt.s.q", 0, INSN_CLASS_Q_INX, "D,S", MATCH_FCVT_S_Q|MASK_RM, MASK_FCVT_S_Q|MASK_RM, match_opcode, 0 },
908908
{"fcvt.s.q", 0, INSN_CLASS_Q_INX, "D,S,m", MATCH_FCVT_S_Q, MASK_FCVT_S_Q, match_opcode, 0 },
909909
{"fcvt.d.q", 0, INSN_CLASS_Q_INX, "D,S", MATCH_FCVT_D_Q|MASK_RM, MASK_FCVT_D_Q|MASK_RM, match_opcode, 0 },
@@ -918,10 +918,8 @@ const struct riscv_opcode riscv_opcodes[] =
918918
{"fcvt.l.q", 64, INSN_CLASS_Q_INX, "d,S,m", MATCH_FCVT_L_Q, MASK_FCVT_L_Q, match_opcode, 0 },
919919
{"fcvt.lu.q", 64, INSN_CLASS_Q_INX, "d,S", MATCH_FCVT_LU_Q|MASK_RM, MASK_FCVT_LU_Q|MASK_RM, match_opcode, 0 },
920920
{"fcvt.lu.q", 64, INSN_CLASS_Q_INX, "d,S,m", MATCH_FCVT_LU_Q, MASK_FCVT_LU_Q, match_opcode, 0 },
921-
{"fcvt.q.l", 64, INSN_CLASS_Q_INX, "D,s", MATCH_FCVT_Q_L, MASK_FCVT_Q_L|MASK_RM, match_opcode, 0 },
922-
{"fcvt.q.l", 64, INSN_CLASS_Q_INX, "D,s,m", MATCH_FCVT_Q_L, MASK_FCVT_Q_L, match_opcode, 0 },
923-
{"fcvt.q.lu", 64, INSN_CLASS_Q_INX, "D,s", MATCH_FCVT_Q_LU, MASK_FCVT_Q_LU|MASK_RM, match_opcode, 0 },
924-
{"fcvt.q.lu", 64, INSN_CLASS_Q_INX, "D,s,m", MATCH_FCVT_Q_LU, MASK_FCVT_Q_LU, match_opcode, 0 },
921+
{"fcvt.q.l", 64, INSN_CLASS_Q_INX, "D,sWfm", MATCH_FCVT_Q_L, MASK_FCVT_Q_L, match_opcode, 0 },
922+
{"fcvt.q.lu", 64, INSN_CLASS_Q_INX, "D,sWfm", MATCH_FCVT_Q_LU, MASK_FCVT_Q_LU, match_opcode, 0 },
925923

926924
/* Compressed instructions. */
927925
{"c.unimp", 0, INSN_CLASS_C, "", 0, 0xffffU, match_opcode, 0 },

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