Write a SystemVerilog code to implement a 6x6 Wallace Tree Multiplier Based on the 5x5 Design

[cuber2116]

You are required to implement a 6x6 Wallace Tree Multiplier by expanding upon the design of the provided 5x5 Wallace Tree Multiplier. Use the 5x5 Wallace Tree multiplier diagram as a reference for the implementation.
Implementing adder+Working Test bench = 800 points

[Ishanvee]

Can i be assigned?

[cuber2116]

!assign @Ishanvee 150

[Ishanvee]

Sorry not able to work on this

[cuber2116]

!deassign

[Satvik-max33]

Can i be assigned?

[codebuddyjr]

assign me

[velukutty2194]

can i be assigned?

[cuber2116]

!assign @Satvik-max33 120

[cuber2116]

!assign @codebuddyjr 120

[cuber2116]

!assign @velukutty2194 120

[Satvik-max33]

Sorry not able to work on this

[cuber2116]

!deassign

[Rojas-Binny]

Can I be assigned?

[cuber2116]

!assign @Rojas-Binny 120

[Rojas-Binny]

I am having a lil trouble with my iverilog, can I just try putting up a PR still?

[cuber2116]

@Rojas-Binny Try using EDA playground