Adding firdata feature to OCC

Adding the fir data collection code to capture
FIR information to PNOR upon a runtime checkstop.

Change-Id: Ia7d6f9a234ca2c86783f7ac8f51407c15895358e
RTC: 115282
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/15970
Reviewed-by: Stephan Broyles <[email protected]>
Tested-by: Stephan Broyles <[email protected]>

Author: sbroylesibm

.gitignore

@@ -14,4 +14,5 @@ occStringFile
 customrc
 env.bash
 src/build/
+*.sw*
 

src/occ/Makefile

@@ -5,15 +5,15 @@
 #
 # OpenPOWER OnChipController Project
 #
-# Contributors Listed Below - COPYRIGHT 2011,2014
-# [+] Google Inc.
+# Contributors Listed Below - COPYRIGHT 2011,2015
 # [+] International Business Machines Corp.
 #
+#
 # Licensed under the Apache License, Version 2.0 (the "License");
 # you may not use this file except in compliance with the License.
 # You may obtain a copy of the License at
 #
-# http://www.apache.org/licenses/LICENSE-2.0
+#     http://www.apache.org/licenses/LICENSE-2.0
 #
 # Unless required by applicable law or agreed to in writing, software
 # distributed under the License is distributed on an "AS IS" BASIS,
@@ -49,6 +49,7 @@ APP_INCLUDES += -I.
 APP_INCLUDES += -I../occ 
 APP_INCLUDES += -I../../occ 
 APP_INCLUDES += -I./timer
+APP_INCLUDES += -I./firdata
 
 export APP_INCLUDES
 

src/occ/app.mk

@@ -5,15 +5,15 @@
 #
 # OpenPOWER OnChipController Project
 #
-# Contributors Listed Below - COPYRIGHT 2011,2014
-# [+] Google Inc.
+# Contributors Listed Below - COPYRIGHT 2011,2015
 # [+] International Business Machines Corp.
 #
+#
 # Licensed under the Apache License, Version 2.0 (the "License");
 # you may not use this file except in compliance with the License.
 # You may obtain a copy of the License at
 #
-# http://www.apache.org/licenses/LICENSE-2.0
+#     http://www.apache.org/licenses/LICENSE-2.0
 #
 # Unless required by applicable law or agreed to in writing, software
 # distributed under the License is distributed on an "AS IS" BASIS,
@@ -107,6 +107,7 @@ LDFLAGS = \
 		  -L $(OCC)/thread \
 		  -L $(OCC)/timer \
 		  -L $(OCC)/trac \
+		  -L $(OCC)/firdata \
 		  -lssx -lppc32 --oformat=elf32-powerpc -melf32ppc
 
 # Added for linking files compiled using gnu assembler

src/occ/cfiles.mk

@@ -91,8 +91,21 @@ occ_CFILES = \
                 occbuildname.c \
                 common.c \
 
+occ_CFILES += firdata/ecc.c
+occ_CFILES += firdata/fir_data_collect.c
+occ_CFILES += firdata/firData.c
+occ_CFILES += firdata/fsi.c
+occ_CFILES += firdata/lpc.c
+occ_CFILES += firdata/native.c
+occ_CFILES += firdata/nor_micron.c
+occ_CFILES += firdata/pnor_util.c
+occ_CFILES += firdata/scom_trgt.c
+occ_CFILES += firdata/scom_util.c
+occ_CFILES += firdata/sfc_ast2400.c
+
 occ_SFILES = cmdh/ll_ffdc.S
 
+
 occ_cfiles = ${occ_CFILES:.c=.o}
 occ_Sfiles = ${occ_SFILES:.S=.o}
 

src/occ/cmdh/cmdh_fsp_cmds.c

@@ -216,9 +216,10 @@ ERRL_RC cmdh_poll_v10(cmdh_fsp_rsp_t * o_rsp_ptr)
     cmdh_poll_resp_v10_fixed_t * l_poll_rsp = (cmdh_poll_resp_v10_fixed_t *) o_rsp_ptr;
 
     // Byte 1
-    l_poll_rsp->status.word     = SMGR_validate_get_valid_states(); //TODO: Do we need to set FIR master?
+    l_poll_rsp->status.word = SMGR_validate_get_valid_states();
     // Byte 2
-    l_poll_rsp->ext_status.word = 0;                                //TODO: What values should we set for memthrotOT and n power?
+    //TODO: What values should we set for memthrotOT and n power?
+    l_poll_rsp->ext_status.word = 0;
 
     for ( k = 0; k < MAX_NUM_CORES; k++ )
     {

src/occ/cmdh/cmdh_fsp_cmds_datacnfg.c

@@ -1073,7 +1073,10 @@ errlHndl_t data_store_pstate_super(const cmdh_fsp_cmd_t * i_cmd_ptr,
 //
 // Name:   data_store_role
 //
-// Description: TODO Add description
+// Description: Tell the OCC if it should run as a master or slave.  HTMGT knows
+//              which OCC is the master from the MRW.  To be the master OCC
+//              requires a connection to the APSS.  Until an OCC is told a role
+//              it should default to running as a slave
 //
 // End Function Specification
 errlHndl_t data_store_role(const cmdh_fsp_cmd_t * i_cmd_ptr,
@@ -1082,17 +1085,13 @@ errlHndl_t data_store_role(const cmdh_fsp_cmd_t * i_cmd_ptr,
     errlHndl_t l_errlHndl = NULL;
     uint8_t    l_old_role = G_occ_role;
     uint8_t    l_new_role = OCC_SLAVE;
-    uint8_t    l_fir_master = 0x00;
     ERRL_RC    l_rc       = ERRL_RC_SUCCESS;
 
     // Cast the command to the struct for this format
     cmdh_set_role_t * l_cmd_ptr = (cmdh_set_role_t *)i_cmd_ptr;
 
-    // With BMC-based systems, there is a FIR Master bit
-    l_fir_master = l_cmd_ptr->role >> 7;
-
-    // Mask off the FIR Master bit
-    l_new_role = l_cmd_ptr->role & 0x7F;
+    // Mask off the OCC role
+    l_new_role = l_cmd_ptr->role & OCC_ROLE_MASTER_MASK;
 
 
     // Must be in standby state before we can change roles

src/occ/cmdh/cmdh_fsp_cmds_datacnfg.h

@@ -84,6 +84,10 @@ typedef enum
     DATA_FRU_MAX,
 } eConfigDataFruType;
 
+// Set OCC Role Masks
+#define OCC_ROLE_MASTER_MASK        0x01
+#define OCC_ROLE_FIR_MASTER_MASK    0x40
+
 // Used by TMGT to send OCC the PstateSuperStruct
 typedef struct __attribute__ ((packed))
 {

src/occ/errl/errl.c

@@ -59,6 +59,7 @@ errlHndl_t  G_occErrSlots[ERRL_MAX_SLOTS] = {
                 };
 
 extern uint8_t G_occ_interrupt_type;
+extern bool G_fir_collection_required;
 
 void hexDumpLog( errlHndl_t i_log );
 
@@ -354,18 +355,30 @@ void addTraceToErrl(
     void * l_traceAddr = io_err;
     uint16_t l_actualSizeOfUsrDtls = 0;
     pore_status_t l_gpe0_status;
+    ocb_oisr0_t l_oisr0_status;
     static bool L_gpe_halt_traced = FALSE;
+    static bool L_sys_checkstop_traced = FALSE;
 
 
     // check if GPE was frozen due to a checkstop
     l_gpe0_status.value = in64(PORE_GPE0_STATUS);
     if(l_gpe0_status.fields.freeze_action && !L_gpe_halt_traced)
     {
         L_gpe_halt_traced = TRUE;
-        TRAC_ERR("addTraceToErrl: OCC GPE halted due to checkstop. GPE0 status[0x%08x%08x]",
-                  l_gpe0_status.words.high_order, l_gpe0_status.words.low_order);
+        TRAC_IMP("addTraceToErrl: Frozen GPE0 detected. GPE0 status[0x%08x%08x]",
+                 l_gpe0_status.words.high_order,
+                 l_gpe0_status.words.low_order);
     }
 
+    // Check if there is a system checkstop
+    l_oisr0_status.value = in32(OCB_OISR0);
+    if (l_oisr0_status.fields.check_stop && !L_sys_checkstop_traced)
+    {
+        L_sys_checkstop_traced = TRUE;
+        TRAC_IMP("addTraceToErrl: System checkstop detected");
+    }
+
+
     // 1. Check if error log is not null
     // 2. error log is not invalid
     // 3. error log has not been commited
@@ -520,16 +533,20 @@ void reportErrorLog( errlHndl_t i_err, uint16_t i_entrySize )
            i_err->iv_userDetails.iv_modId, i_err->iv_reasonCode,
            i_err->iv_userDetails.iv_userData1, i_err->iv_userDetails.iv_userData2);
 
-    // If this system is using PSIHB complex, send an interrupt to Host so that
-    // Host can inform HTMGT to collect the error log
-    if (G_occ_interrupt_type == PSIHB_INTERRUPT)
+    // Defer the interrupt if FIR collection is required
+    if (!G_fir_collection_required)
     {
-        // From OCC OpenPower Interface v1.1, OCC needs to set bits 0 and 1 of
-        // the OCB_OCCMISC register
-        l_reg.fields.core_ext_intr = 1;
-        l_reg.fields.reason_intr = 1;
+        // If this system is using PSIHB complex, send an interrupt to Host so that
+        // Host can inform HTMGT to collect the error log
+        if (G_occ_interrupt_type == PSIHB_INTERRUPT)
+        {
+            // From OCC OpenPower Interface v1.1, OCC needs to set bits 0 and 1 of
+            // the OCB_OCCMISC register
+            l_reg.fields.core_ext_intr = 1;
+            l_reg.fields.reason_intr = 1;
 
-        out32(OCB_OCCMISC_OR, l_reg.value);
+            out32(OCB_OCCMISC_OR, l_reg.value);
+        }
     }
 }
 
@@ -544,16 +561,33 @@ void reportErrorLog( errlHndl_t i_err, uint16_t i_entrySize )
 void commitErrl( errlHndl_t *io_err )
 {
     pore_status_t l_gpe0_status;
+    ocb_oisr0_t l_oisr0_status;
+    static bool L_log_commits_suspended_by_safe_mode = FALSE;
 
-    if ( io_err != NULL )
+    if (!L_log_commits_suspended_by_safe_mode && io_err != NULL)
     {
         // check if handle is valid and is NOT empty
         if ((*io_err != NULL ) && ( *io_err != INVALID_ERR_HNDL ))
         {
-            // check if GPE was frozen due to a checkstop
+            // Check if the GPE is frozen or if a system
+            // checkstop has occurred
             l_gpe0_status.value = in64(PORE_GPE0_STATUS);
-            if(l_gpe0_status.fields.freeze_action)
+            l_oisr0_status.value = in32(OCB_OISR0);
+
+            if (l_gpe0_status.fields.freeze_action
+                ||
+                l_oisr0_status.fields.check_stop)
             {
+                if (l_gpe0_status.fields.freeze_action)
+                {
+                    TRAC_IMP("Frozen GPE0 detected by commitErrl");
+                }
+
+                if (l_oisr0_status.fields.check_stop)
+                {
+                    TRAC_IMP("System checkstop detected by commitErrl");
+                }
+
                 //Go to the reset state to minimize errors
                 reset_state_request(RESET_REQUESTED_DUE_TO_ERROR);
 
@@ -565,6 +599,14 @@ void commitErrl( errlHndl_t *io_err )
 
                 //set callouts to 0
                 (*io_err)->iv_numCallouts = 0;
+
+                TRAC_IMP("SAFE mode required, suspending error log commits. FIR capture required.");
+
+                // Suspend all error log commits
+                L_log_commits_suspended_by_safe_mode = TRUE;
+
+                // Motivate FIR data collection
+                G_fir_collection_required = TRUE;
             }
 
             // if reset action bit is set force severity to unrecoverable and