alexforencich
diff --git a/‎README.md
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diff --git a/‎example/HXT100G/fpga/Makefile renamed to ‎example/HTG640/fpga/Makefile b/‎example/HXT100G/fpga/Makefile renamed to ‎example/HTG640/fpga/Makefile
diff --git a/‎example/HXT100G/fpga/README.md renamed to ‎example/HTG640/fpga/README.md
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diff --git a/‎example/HXT100G/fpga/common/xilinx.mk renamed to ‎example/HTG640/fpga/common/xilinx.mk b/‎example/HXT100G/fpga/common/xilinx.mk renamed to ‎example/HTG640/fpga/common/xilinx.mk
diff --git a/‎example/HXT100G/fpga/coregen/Makefile renamed to ‎example/HTG640/fpga/coregen/Makefile b/‎example/HXT100G/fpga/coregen/Makefile renamed to ‎example/HTG640/fpga/coregen/Makefile
diff --git a/‎example/HXT100G/fpga/coregen/coregen.cgp renamed to ‎example/HTG640/fpga/coregen/coregen.cgp b/‎example/HXT100G/fpga/coregen/coregen.cgp renamed to ‎example/HTG640/fpga/coregen/coregen.cgp
diff --git a/‎example/HXT100G/fpga/coregen/ten_gig_eth_pcs_pma_v2_6.xco renamed to ‎example/HTG640/fpga/coregen/ten_gig_eth_pcs_pma_v2_6.xco b/‎example/HXT100G/fpga/coregen/ten_gig_eth_pcs_pma_v2_6.xco renamed to ‎example/HTG640/fpga/coregen/ten_gig_eth_pcs_pma_v2_6.xco
diff --git a/‎example/HXT100G/fpga/coregen/ten_gig_eth_pcs_pma_v2_6_v6gth_wrapper.xco renamed to ‎example/HTG640/fpga/coregen/ten_gig_eth_pcs_pma_v2_6_v6gth_wrapper.xco b/‎example/HXT100G/fpga/coregen/ten_gig_eth_pcs_pma_v2_6_v6gth_wrapper.xco renamed to ‎example/HTG640/fpga/coregen/ten_gig_eth_pcs_pma_v2_6_v6gth_wrapper.xco
diff --git a/‎example/HXT100G/fpga/fpga.ucf renamed to ‎example/HTG640/fpga/fpga.ucf b/‎example/HXT100G/fpga/fpga.ucf renamed to ‎example/HTG640/fpga/fpga.ucf
diff --git a/‎example/HXT100G/fpga/fpga/Makefile renamed to ‎example/HTG640/fpga/fpga/Makefile b/‎example/HXT100G/fpga/fpga/Makefile renamed to ‎example/HTG640/fpga/fpga/Makefile
@@ -46,7 +46,7 @@ following boards:
 *  Exablaze ExaNIC X10 (Xilinx Kintex UltraScale XCKU035)
 *  Exablaze ExaNIC X25 (Xilinx Kintex UltraScale+ XCKU3P)
 *  HiTech Global HTG-9200 (Xilinx UltraScale+ XCVU9P)
-*  HiTech Global HTG-V6HXT-100GIG-565 (Xilinx Virtex 6 XC6VHX565T)
+*  HiTech Global HTG-640 (HTG-V6HXT-100GIG-565) (Xilinx Virtex 6 XC6VHX565T)
 *  Silicom fb2CG@KU15P (Xilinx Kintex UltraScale+ XCKU15P)
 *  Xilinx KC705 (Xilinx Kintex 7 XC7K325T)
 *  Xilinx ML605 (Xilinx Virtex 6 XC6VLX240T)
 
@@ -1,8 +1,8 @@
-# Verilog Ethernet HXT100G Example Design
+# Verilog Ethernet HTG-640 Example Design
 
 ## Introduction
 
-This example design targets the HiTech Global HXT100G FPGA board.
+This example design targets the HiTech Global HTG-640 (HTG-V6HXT-100GIG-565) FPGA board.
 
 The design by default listens to UDP port 1234 at IP address 192.168.1.128 and
 will echo back any packets received.  The design will also respond correctly
@@ -18,7 +18,7 @@ in PATH.
 
 ## How to test
 
-Run make program to program the HXT100G board with the Xilinx Impact software.
+Run make program to program the HTG-640 board with the Xilinx Impact software.
 Then run
 
     netcat -u 192.168.1.128 1234