clock/v2: Fix formatting

atsamd-rs · Oct 11, 2021 · bddd31f · bddd31f
1 parent d7b047a
commit bddd31f
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Showing 5 changed files with 17 additions and 16 deletions.
diff --git a/hal/src/thumbv7em/clock/v2/dfll.rs b/hal/src/thumbv7em/clock/v2/dfll.rs
@@ -20,7 +20,7 @@ use crate::clock::v2::{
 use crate::time::{Hertz, U32Ext};
 use crate::typelevel::Sealed;
 
-use super::gclk::{Gclk0, GclkSource, GclkSourceEnum, GclkSourceMarker, GclkNum};
+use super::gclk::{Gclk0, GclkNum, GclkSource, GclkSourceEnum, GclkSourceMarker};
 use super::gclkio::NotGclkInput;
 use super::pclk::{Dfll48, Pclk, PclkSourceMarker};
 
@@ -170,7 +170,7 @@ pub trait LoopMode: Sealed {
 /// implementations blocks for [`Enabled`]`<`[`Dfll`]`<`[`OpenLoop`]`>>` and
 /// [`Dfll`]`<`[`OpenLoop`]`>` structs
 pub struct OpenLoop {
-    __: ()
+    __: (),
 }
 
 impl LoopMode for OpenLoop {
@@ -257,9 +257,7 @@ impl Dfll<OpenLoop> {
         Self {
             token,
             freq: 48.mhz().into(),
-            mode: OpenLoop {
-                __: ()
-            },
+            mode: OpenLoop { __: () },
             multiplication_factor: 1_u16,
             run_standby: false,
             on_demand_mode: true,

diff --git a/hal/src/thumbv7em/clock/v2/gclk.rs b/hal/src/thumbv7em/clock/v2/gclk.rs
@@ -502,7 +502,8 @@ where
 /// This struct represents a disabled [`Gclk`] - generic clock generator
 ///
 /// It is generic over:
-/// - a numeric variant (available variants: [`GclkNum`] implementors - eg. [`marker::Gclk3`])
+/// - a numeric variant (available variants: [`GclkNum`] implementors - eg.
+///   [`marker::Gclk3`])
 /// - a current signal source (expressed via source's marker type)
 pub struct Gclk<G, T>
 where

diff --git a/hal/src/thumbv7em/clock/v2/osculp32k.rs b/hal/src/thumbv7em/clock/v2/osculp32k.rs
@@ -22,14 +22,14 @@ use crate::pac::osc32kctrl::rtcctrl::RTCSEL_A;
 use crate::pac::osc32kctrl::OSCULP32K;
 
 use crate::clock::v2::{
+    rtc::RtcSourceMarker,
     types::{Counter, Enabled},
     Source, SourceMarker,
-    rtc::{RtcSourceMarker}
 };
 use crate::time::{Hertz, U32Ext};
 use crate::typelevel::Sealed;
 
-use super::gclk::{GclkSource, GclkSourceMarker, GclkNum};
+use super::gclk::{GclkNum, GclkSource, GclkSourceMarker};
 use super::gclkio::NotGclkInput;
 use super::rtc::*;
 

diff --git a/hal/src/thumbv7em/clock/v2/presets.rs b/hal/src/thumbv7em/clock/v2/presets.rs
@@ -5,8 +5,8 @@
 /// - [`Dfll<OpenLoop>`][`super::dfll::Dfll`] (`48 MHz`)
 /// - [`Gclk5<marker::Dfll>`][`super::gclk::Gclk5`] (`48 MHz / 24 -> 2 MHz`)
 /// - [`Pclk<marker::Dpll0, marker::Gclk5>`][`super::pclk::Pclk`]
-/// - [`Dpll0<PclkDriven<marker::Dpll0, marker::Gclk5>>`][`super::dpll::Dpll0`] (`2 MHz * 60 ->
-///   120 MHz`)
+/// - [`Dpll0<PclkDriven<marker::Dpll0, marker::Gclk5>>`][`super::dpll::Dpll0`]
+///   (`2 MHz * 60 -> 120 MHz`)
 /// - [`Gclk0<marker::Dpll0>`][`super::gclk::Gclk0`] (`120 MHz`)
 ///
 /// Input arguments for this macro can be retrieved by calling
@@ -52,8 +52,8 @@ macro_rules! clocking_preset_gclk0_120mhz_gclk5_2mhz {
 /// - [`Dfll<OpenLoop>`][`super::dfll::Dfll`] (`48 MHz`)
 /// - [`Gclk5<marker::Dfll>`][`super::gclk::Gclk5`] (`48 MHz / 24 -> 2 MHz`)
 /// - [`Pclk<marker::Dpll0, marker::Gclk5>`][`super::pclk::Pclk`]
-/// - [`Dpll0<PclkDriven<marker::Dpll0, marker::Gclk5>>`][`super::dpll::Dpll0`] (`2 MHz * 60 ->
-///   120 MHz`)
+/// - [`Dpll0<PclkDriven<marker::Dpll0, marker::Gclk5>>`][`super::dpll::Dpll0`]
+///   (`2 MHz * 60 -> 120 MHz`)
 /// - [`Gclk0<marker::Dpll0>`][`super::gclk::Gclk0`] (`120 MHz`)
 ///
 /// with configured external 32k crystal oscillator:
@@ -109,8 +109,8 @@ macro_rules! clocking_preset_gclk0_120mhz_gclk5_2mhz_gclk1_external_32khz {
 /// - [`Dfll<OpenLoop>`][`super::dfll::Dfll`] (`48 MHz`)
 /// - [`Gclk5<marker::Dfll>`][`super::gclk::Gclk5`] (`48 MHz / 24 -> 2 MHz`)
 /// - [`Pclk<marker::Dpll0, marker::Gclk5>`][`super::pclk::Pclk`]
-/// - [`Dpll0<PclkDriven<marker::Dpll0, marker::Gclk5>>`][`super::dpll::Dpll0`] (`2 MHz * 60 ->
-///   120 MHz`)
+/// - [`Dpll0<PclkDriven<marker::Dpll0, marker::Gclk5>>`][`super::dpll::Dpll0`]
+///   (`2 MHz * 60 -> 120 MHz`)
 /// - [`Gclk0<marker::Dpll0>`][`super::gclk::Gclk0`] (`120 MHz`)
 ///
 /// with internal, ultra low power 32k oscillator:

diff --git a/hal/src/thumbv7em/clock/v2/xosc32k.rs b/hal/src/thumbv7em/clock/v2/xosc32k.rs
@@ -10,7 +10,8 @@
 //! - [`Enabled`]`<`[`Xosc32k`]`<`[`ClockMode`]`, _, _>>`: Xosc32k is being
 //!   powered by an external signal (1 pin)
 //!
-//! Signal outputs are independently controllable and also expressed as typestates
+//! Signal outputs are independently controllable and also expressed as
+//! typestates
 //! - [`Enabled`]`<`[`Xosc32k`]`<_, `[`Active32k`]`, _>>`: Xosc32k 32 kHz signal
 //!   output is active
 //! - [`Enabled`]`<`[`Xosc32k`]`<_, `[`Inactive32k`]`, _>>`: Xosc32k 32 kHz
@@ -24,7 +25,8 @@
 //! - [`Enabled<Xosc32k>::activate_32k`]
 //! - [`Enabled<Xosc32k>::activate_1k`]
 //!
-//! To construct a Xosc32k in a proper mode use an appropriate construction function:
+//! To construct a Xosc32k in a proper mode use an appropriate construction
+//! function:
 //! - [`Xosc32k::from_clock`]
 //! - [`Xosc32k::from_crystal`]
 //! Then, enable it with a [`Xosc32k::enable`] function call