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ocs_hal.c
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/*
* BSD LICENSE
*
* Copyright (c) 2011-2018 Broadcom. All Rights Reserved.
* The term "Broadcom" refers to Broadcom Inc. and/or its subsidiaries.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* * Neither the name of Intel Corporation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/**
* @file
* Defines and implements the Hardware Abstraction Layer (HAL).
* All interaction with the hardware is performed through the HAL, which abstracts
* the details of the underlying SLI-4 implementation.
*/
/**
* @defgroup devInitShutdown Device Initialization and Shutdown
* @defgroup domain Domain Functions
* @defgroup port Port Functions
* @defgroup node Remote Node Functions
* @defgroup io IO Functions
* @defgroup interrupt Interrupt handling
* @defgroup os OS Required Functions
*/
#include "ocs_os.h"
#include "ocs.h"
#include "ocs_hal.h"
#include "ocs_hal_queues.h"
#include "spdk_nvmf_xport.h"
#define OCS_HAL_MQ_DEPTH 128
#define OCS_HAL_READ_FCF_SIZE 4096
#define OCS_HAL_DEFAULT_AUTO_XFER_RDY_IOS 256
#define OCS_HAL_WQ_TIMER_PERIOD_MS 500
/* values used for setting the auto xfer rdy parameters */
#define OCS_HAL_AUTO_XFER_RDY_BLK_SIZE_DEFAULT 0 /* 512 bytes */
#define OCS_HAL_AUTO_XFER_RDY_REF_TAG_IS_LBA_DEFAULT TRUE
#define OCS_HAL_AUTO_XFER_RDY_APP_TAG_VALID_DEFAULT FALSE
#define OCS_HAL_AUTO_XFER_RDY_APP_TAG_VALUE_DEFAULT 0
#define OCS_HAL_REQUE_XRI_REGTAG 65534
/* max command and response buffer lengths -- arbitrary at the moment */
#define OCS_HAL_DMTF_CLP_CMD_MAX 256
#define OCS_HAL_DMTF_CLP_RSP_MAX 256
/* HAL global data */
ocs_hal_global_t hal_global;
static void ocs_hal_queue_hash_add(ocs_queue_hash_t *, uint16_t, uint16_t);
static void ocs_hal_adjust_wqs(ocs_hal_t *hal);
static uint32_t ocs_hal_get_num_chutes(ocs_hal_t *hal);
static int32_t ocs_hal_cb_link(void *, void *);
static int32_t ocs_hal_cb_fip(void *, void *);
static int32_t ocs_hal_command_process(ocs_hal_t *, int32_t, uint8_t *, size_t);
static int32_t ocs_hal_mq_process(ocs_hal_t *, int32_t, sli4_queue_t *);
static int32_t ocs_hal_cb_read_fcf(ocs_hal_t *, int32_t, uint8_t *, void *);
static int32_t ocs_hal_cb_node_attach(ocs_hal_t *, int32_t, uint8_t *, void *);
static int32_t ocs_hal_cb_node_free(ocs_hal_t *, int32_t, uint8_t *, void *);
static int32_t ocs_hal_cb_node_free_all(ocs_hal_t *, int32_t, uint8_t *, void *);
static ocs_hal_rtn_e ocs_hal_setup_io(ocs_hal_t *);
static ocs_hal_rtn_e ocs_hal_init_io(ocs_hal_t *);
static int32_t ocs_hal_flush(ocs_hal_t *);
static int32_t ocs_hal_command_cancel(ocs_hal_t *);
static int32_t ocs_hal_io_cancel(ocs_hal_t *);
static void ocs_hal_io_quarantine(ocs_hal_t *hal, hal_wq_t *wq, ocs_hal_io_t *io);
static void ocs_hal_io_restore_sgl(ocs_hal_t *, ocs_hal_io_t *);
static int32_t ocs_hal_io_ini_sge(ocs_hal_t *, ocs_hal_io_t *, ocs_dma_t *, uint32_t, ocs_dma_t *);
static ocs_hal_rtn_e ocs_hal_firmware_write_lancer(ocs_hal_t *hal, ocs_dma_t *dma, uint32_t size, uint32_t offset, int last, ocs_hal_fw_cb_t cb, void *arg);
static int32_t ocs_hal_cb_fw_write(ocs_hal_t *, int32_t, uint8_t *, void *);
static int32_t ocs_hal_cb_sfp(ocs_hal_t *, int32_t, uint8_t *, void *);
static int32_t ocs_hal_cb_temp(ocs_hal_t *, int32_t, uint8_t *, void *);
static int32_t ocs_hal_cb_link_stat(ocs_hal_t *, int32_t, uint8_t *, void *);
static int32_t ocs_hal_cb_host_stat(ocs_hal_t *hal, int32_t status, uint8_t *mqe, void *arg);
static void ocs_hal_dmtf_clp_cb(ocs_hal_t *hal, int32_t status, uint8_t *mqe, void *arg);
static int32_t ocs_hal_clp_resp_get_value(ocs_hal_t *hal, const char *keyword, char *value, uint32_t value_len, const char *resp, uint32_t resp_len);
typedef void (*ocs_hal_dmtf_clp_cb_t)(ocs_hal_t *hal, int32_t status, uint32_t result_len, void *arg);
static ocs_hal_rtn_e ocs_hal_exec_dmtf_clp_cmd(ocs_hal_t *hal, ocs_dma_t *dma_cmd, ocs_dma_t *dma_resp, uint32_t opts, ocs_hal_dmtf_clp_cb_t cb, void *arg);
static void ocs_hal_linkcfg_dmtf_clp_cb(ocs_hal_t *hal, int32_t status, uint32_t result_len, void *arg);
static int32_t __ocs_read_topology_cb(ocs_hal_t *, int32_t, uint8_t *, void *);
static ocs_hal_rtn_e ocs_hal_get_linkcfg(ocs_hal_t *, uint32_t, ocs_hal_port_control_cb_t, void *);
static ocs_hal_rtn_e ocs_hal_get_linkcfg_lancer(ocs_hal_t *, uint32_t, ocs_hal_port_control_cb_t, void *);
static ocs_hal_rtn_e ocs_hal_get_linkcfg_skyhawk(ocs_hal_t *, uint32_t, ocs_hal_port_control_cb_t, void *);
static ocs_hal_rtn_e ocs_hal_set_linkcfg(ocs_hal_t *, ocs_hal_linkcfg_e, uint32_t, ocs_hal_port_control_cb_t, void *);
static ocs_hal_rtn_e ocs_hal_set_linkcfg_lancer(ocs_hal_t *, ocs_hal_linkcfg_e, uint32_t, ocs_hal_port_control_cb_t, void *);
static ocs_hal_rtn_e ocs_hal_set_linkcfg_skyhawk(ocs_hal_t *, ocs_hal_linkcfg_e, uint32_t, ocs_hal_port_control_cb_t, void *);
static void ocs_hal_init_linkcfg_cb(int32_t status, uintptr_t value, void *arg);
static ocs_hal_rtn_e ocs_hal_set_eth_license(ocs_hal_t *hal, uint32_t license);
static ocs_hal_rtn_e ocs_hal_set_dif_seed(ocs_hal_t *hal);
static ocs_hal_rtn_e ocs_hal_set_dif_mode(ocs_hal_t *hal);
static void ocs_hal_io_free_internal(void *arg);
static void ocs_hal_io_free_port_owned(void *arg);
static ocs_hal_rtn_e ocs_hal_config_auto_xfer_rdy_t10pi(ocs_hal_t *hal, uint8_t *buf);
static ocs_hal_rtn_e ocs_hal_config_set_fdt_xfer_hint(ocs_hal_t *hal, uint32_t fdt_xfer_hint);
static void ocs_hal_wq_process_abort(void *arg, uint8_t *cqe, int32_t status);
static int32_t ocs_hal_config_mrq(ocs_hal_t *hal, uint8_t, uint16_t, uint16_t);
static ocs_hal_rtn_e ocs_hal_config_watchdog_timer(ocs_hal_t *hal);
static ocs_hal_rtn_e ocs_hal_config_sli_port_health_check(ocs_hal_t *hal, uint8_t query, uint8_t enable);
/* HAL domain database operations */
static int32_t ocs_hal_domain_add(ocs_hal_t *, ocs_domain_t *);
static int32_t ocs_hal_domain_del(ocs_hal_t *, ocs_domain_t *);
/* Port state machine */
static void *__ocs_hal_port_alloc_init(ocs_sm_ctx_t *, ocs_sm_event_t, void *);
static void *__ocs_hal_port_alloc_read_sparm64(ocs_sm_ctx_t *, ocs_sm_event_t, void *);
static void *__ocs_hal_port_alloc_init_vpi(ocs_sm_ctx_t *, ocs_sm_event_t, void *);
static void *__ocs_hal_port_done(ocs_sm_ctx_t *, ocs_sm_event_t, void *);
static void *__ocs_hal_port_free_unreg_vpi(ocs_sm_ctx_t *, ocs_sm_event_t, void *);
/* Domain state machine */
static void *__ocs_hal_domain_init(ocs_sm_ctx_t *, ocs_sm_event_t, void *);
static void *__ocs_hal_domain_alloc_reg_fcfi(ocs_sm_ctx_t *, ocs_sm_event_t, void *);
static void * __ocs_hal_domain_alloc_init_vfi(ocs_sm_ctx_t *, ocs_sm_event_t, void *);
static void *__ocs_hal_domain_free_unreg_vfi(ocs_sm_ctx_t *, ocs_sm_event_t, void *);
static void *__ocs_hal_domain_free_unreg_fcfi(ocs_sm_ctx_t *ctx, ocs_sm_event_t evt, void *data);
static int32_t __ocs_hal_domain_cb(ocs_hal_t *, int32_t, uint8_t *, void *);
static int32_t __ocs_hal_port_cb(ocs_hal_t *, int32_t, uint8_t *, void *);
static int32_t __ocs_hal_port_realloc_cb(ocs_hal_t *hal, int32_t status, uint8_t *mqe, void *arg);
/* BZ 161832 */
static void ocs_hal_check_sec_hio_list(ocs_hal_t *hal);
/* WQE timeouts */
static void target_wqe_timer_cb(void *arg);
static void shutdown_target_wqe_timer(ocs_hal_t *hal);
static inline void
ocs_hal_add_io_timed_wqe(ocs_hal_t *hal, ocs_hal_io_t *io)
{
if (hal->config.emulate_tgt_wqe_timeout && io->tgt_wqe_timeout) {
/*
* Active WQE list currently only used for
* target WQE timeouts.
*/
ocs_lock(&hal->io_lock);
ocs_list_add_tail(&hal->io_timed_wqe, io);
io->submit_ticks = ocs_get_os_ticks();
ocs_unlock(&hal->io_lock);
}
}
static inline void
ocs_hal_remove_io_timed_wqe(ocs_hal_t *hal, ocs_hal_io_t *io)
{
if (hal->config.emulate_tgt_wqe_timeout) {
/*
* If target wqe timeouts are enabled,
* remove from active wqe list.
*/
ocs_lock(&hal->io_lock);
if (ocs_list_on_list(&io->wqe_link)) {
ocs_list_remove(&hal->io_timed_wqe, io);
}
ocs_unlock(&hal->io_lock);
}
}
static uint8_t ocs_hal_iotype_is_originator(uint16_t io_type)
{
switch (io_type) {
case OCS_HAL_IO_INITIATOR_READ:
case OCS_HAL_IO_INITIATOR_WRITE:
case OCS_HAL_IO_INITIATOR_NODATA:
case OCS_HAL_FC_CT:
case OCS_HAL_ELS_REQ:
return 1;
default:
return 0;
}
}
static uint8_t ocs_hal_wcqe_abort_needed(uint16_t status, uint8_t ext, uint8_t xb)
{
/* if exchange not active, nothing to abort */
if (!xb) {
return FALSE;
}
if (status == SLI4_FC_WCQE_STATUS_LOCAL_REJECT) {
switch (ext) {
/* exceptions where abort is not needed */
case SLI4_FC_LOCAL_REJECT_INVALID_RPI: /* lancer returns this after unreg_rpi */
case SLI4_FC_LOCAL_REJECT_ABORT_REQUESTED: /* abort already in progress */
return FALSE;
default:
break;
}
}
return TRUE;
}
/**
* @brief Determine the number of chutes on the device.
*
* @par Description
* Some devices require queue resources allocated per protocol processor
* (chute). This function returns the number of chutes on this device.
*
* @param hal Hardware context allocated by the caller.
*
* @return Returns the number of chutes on the device for protocol.
*/
static uint32_t
ocs_hal_get_num_chutes(ocs_hal_t *hal)
{
uint32_t num_chutes = 1;
if (sli_get_is_dual_ulp_capable(&hal->sli) &&
sli_get_is_ulp_enabled(&hal->sli, 0) &&
sli_get_is_ulp_enabled(&hal->sli, 1)) {
num_chutes = 2;
}
return num_chutes;
}
static ocs_hal_rtn_e
ocs_hal_link_event_init(ocs_hal_t *hal)
{
if (hal == NULL) {
ocs_log_err(hal->os, "%s: bad parameter hal=%p\n", __func__, hal);
return OCS_HAL_RTN_ERROR;
}
hal->link.status = SLI_LINK_STATUS_MAX;
hal->link.topology = SLI_LINK_TOPO_NONE;
hal->link.medium = SLI_LINK_MEDIUM_MAX;
hal->link.speed = 0;
hal->link.loop_map = NULL;
hal->link.fc_id = UINT32_MAX;
return OCS_HAL_RTN_SUCCESS;
}
/**
* @ingroup devInitShutdown
* @brief If this is physical port 0, then read the max dump size.
*
* @par Description
* Queries the FW for the maximum dump size
*
* @param hal Hardware context allocated by the caller.
*
* @return Returns 0 on success, or a non-zero value on failure.
*/
static ocs_hal_rtn_e
ocs_hal_read_max_dump_size(ocs_hal_t *hal)
{
uint8_t buf[SLI4_BMBX_SIZE];
uint8_t bus, dev, func;
int rc;
/* lancer only */
if (SLI4_IF_TYPE_LANCER_FC_ETH != sli_get_if_type(&hal->sli)) {
ocs_log_debug(hal->os, "%s: Function only supported for I/F type 2\n", __func__);
return OCS_HAL_RTN_ERROR;
}
/*
* Make sure the FW is new enough to support this command. If the FW
* is too old, the FW will UE.
*/
if (hal->workaround.disable_dump_loc) {
ocs_log_test(hal->os, "%s: FW version is too old for this feature\n", __func__);
return OCS_HAL_RTN_ERROR;
}
/* attempt to detemine the dump size for function 0 only. */
ocs_get_bus_dev_func(hal->os, &bus, &dev, &func);
if (func == 0) {
if (sli_cmd_common_set_dump_location(&hal->sli, buf,
SLI4_BMBX_SIZE, 1, 0, NULL)) {
sli4_res_common_set_dump_location_t *rsp =
(sli4_res_common_set_dump_location_t *)
(buf + offsetof(sli4_cmd_sli_config_t,
payload.embed));
rc = ocs_hal_command(hal, buf, OCS_CMD_POLL, NULL, NULL);
if (rc != OCS_HAL_RTN_SUCCESS) {
ocs_log_test(hal->os, "%s: set dump location command failed\n", __func__);
return rc;
} else {
hal->dump_size = rsp->buffer_length;
ocs_log_debug(hal->os, "Dump size %x\n", rsp->buffer_length);
}
}
}
return OCS_HAL_RTN_SUCCESS;
}
/**
* @ingroup devInitShutdown
* @brief Set up the Hardware Abstraction Layer module.
*
* @par Description
* Calls set up to configure the hardware.
*
* @param hal Hardware context allocated by the caller.
* @param os Device abstraction.
* @param port_type Protocol type of port, such as FC and NIC.
*
* @todo Why is port_type a parameter?
*
* @return Returns 0 on success, or a non-zero value on failure.
*/
ocs_hal_rtn_e
ocs_hal_setup(ocs_hal_t *hal, ocs_os_handle_t os, sli4_port_type_e port_type)
{
uint32_t i;
char prop_buf[32];
ocs_t *ocs = os;
if (hal == NULL) {
ocs_log_err(os, "%s: bad parameter(s) hal=%p\n", __func__, hal);
return OCS_HAL_RTN_ERROR;
}
if (hal->hal_setup_called) {
/* Setup run-time workarounds.
* Call for each setup, to allow for hal_war_version
*/
ocs_hal_workaround_setup(hal);
return OCS_HAL_RTN_SUCCESS;
}
/*
* ocs_hal_init() relies on NULL pointers indicating that a structure
* needs allocation. If a structure is non-NULL, ocs_hal_init() won't
* free/realloc that memory
*/
ocs_memset(hal, 0, sizeof(ocs_hal_t));
hal->hal_setup_called = TRUE;
hal->os = os;
ocs_lock_init(hal->os, &hal->cmd_lock, "HAL_cmd_lock[%d]", ocs_instance(hal->os));
ocs_list_init(&hal->cmd_head, ocs_command_ctx_t, link);
ocs_list_init(&hal->cmd_pending, ocs_command_ctx_t, link);
hal->cmd_head_count = 0;
ocs_lock_init(hal->os, &hal->io_lock, "HAL_io_lock[%d]", ocs_instance(hal->os));
ocs_lock_init(hal->os, &hal->io_abort_lock, "HAL_io_abort_lock[%d]", ocs_instance(hal->os));
ocs_atomic_init(&hal->io_alloc_failed_count, 0);
hal->config.speed = FC_LINK_SPEED_AUTO_16_8_4;
hal->config.dif_seed = 0;
hal->config.auto_xfer_rdy_blk_size_chip = OCS_HAL_AUTO_XFER_RDY_BLK_SIZE_DEFAULT;
hal->config.auto_xfer_rdy_ref_tag_is_lba = OCS_HAL_AUTO_XFER_RDY_REF_TAG_IS_LBA_DEFAULT;
hal->config.auto_xfer_rdy_app_tag_valid = OCS_HAL_AUTO_XFER_RDY_APP_TAG_VALID_DEFAULT;
hal->config.auto_xfer_rdy_app_tag_value = OCS_HAL_AUTO_XFER_RDY_APP_TAG_VALUE_DEFAULT;
if (sli_setup(&hal->sli, hal->os, port_type)) {
ocs_log_err(hal->os, "%s: SLI setup failed\n", __func__);
return OCS_HAL_RTN_ERROR;
}
ocs_memset(hal->domains, 0, sizeof(hal->domains));
ocs_memset(hal->fcf_index_fcfi, 0, sizeof(hal->fcf_index_fcfi));
ocs_hal_link_event_init(hal);
sli_callback(&hal->sli, SLI4_CB_LINK, ocs_hal_cb_link, hal);
sli_callback(&hal->sli, SLI4_CB_FIP, ocs_hal_cb_fip, hal);
/*
* Set all the queue sizes to the maximum allowed. These values may
* be changes later by the adjust and workaround functions.
*/
for (i = 0; i < ARRAY_SIZE(hal->num_qentries); i++) {
hal->num_qentries[i] = sli_get_max_qentries(&hal->sli, i);
}
/*
* The RQ assignment for RQ pair mode.
*/
hal->config.rq_default_buffer_size = OCS_HAL_RQ_SIZE_PAYLOAD;
hal->config.n_io = sli_get_max_rsrc(&hal->sli, SLI_RSRC_FCOE_XRI);
if (ocs_get_property("auto_xfer_rdy_xri_cnt", prop_buf, sizeof(prop_buf)) == 0) {
hal->config.auto_xfer_rdy_xri_cnt = ocs_strtoul(prop_buf, 0, 0);
}
/* by default, enable initiator-only auto-ABTS emulation */
hal->config.i_only_aab = TRUE;
/* Setup run-time workarounds */
ocs_hal_workaround_setup(hal);
/* HAL_WORKAROUND_OVERRIDE_FCFI_IN_SRB */
if (hal->workaround.override_fcfi) {
hal->first_domain_idx = -1;
}
/* Must be done after the workaround setup */
if (SLI4_IF_TYPE_LANCER_FC_ETH == sli_get_if_type(&hal->sli)) {
(void)ocs_hal_read_max_dump_size(hal);
}
/* calculate the number of WQs required. */
ocs_hal_adjust_wqs(hal);
/* Set the default dif mode */
if (! sli_is_dif_inline_capable(&hal->sli)) {
ocs_log_test(hal->os, "%s: not inline capable, setting mode to seperate\n", __func__);
hal->config.dif_mode = OCS_HAL_DIF_MODE_SEPARATE;
}
/* Workaround: BZ 161832 */
if (hal->workaround.use_dif_sec_xri) {
ocs_list_init(&hal->sec_hio_wait_list, ocs_hal_io_t, link);
}
/*
* Figure out the starting and max ULP to spread the WQs across the
* ULPs.
*/
if (sli_get_is_dual_ulp_capable(&hal->sli)) {
if (sli_get_is_ulp_enabled(&hal->sli, 0) &&
sli_get_is_ulp_enabled(&hal->sli, 1)) {
hal->ulp_start = 0;
hal->ulp_max = 1;
} else if (sli_get_is_ulp_enabled(&hal->sli, 0)) {
hal->ulp_start = 0;
hal->ulp_max = 0;
} else {
hal->ulp_start = 1;
hal->ulp_max = 1;
}
} else {
if (sli_get_is_ulp_enabled(&hal->sli, 0)) {
hal->ulp_start = 0;
hal->ulp_max = 0;
} else {
hal->ulp_start = 1;
hal->ulp_max = 1;
}
}
ocs_log_debug(hal->os, "ulp_start %d, ulp_max %d\n",
hal->ulp_start, hal->ulp_max);
hal->config.queue_topology = ocs->queue_topology;
hal->qtop = ocs_hal_qtop_parse(hal, hal->config.queue_topology);
hal->config.n_eq = hal->qtop->entry_counts[QTOP_EQ];
hal->config.n_cq = hal->qtop->entry_counts[QTOP_CQ];
hal->config.n_rq = hal->qtop->entry_counts[QTOP_RQ];
hal->config.n_wq = hal->qtop->entry_counts[QTOP_WQ];
hal->config.n_mq = hal->qtop->entry_counts[QTOP_MQ];
return OCS_HAL_RTN_SUCCESS;
}
/**
* @ingroup devInitShutdown
* @brief Allocate memory structures to prepare for the device operation.
*
* @par Description
* Allocates memory structures needed by the device and prepares the device
* for operation.
* @n @n @b Note: This function may be called more than once (for example, at
* initialization and then after a reset), but the size of the internal resources
* may not be changed without tearing down the HAL (ocs_hal_teardown()).
*
* @param hal Hardware context allocated by the caller.
*
* @return Returns 0 on success, or a non-zero value on failure.
*/
ocs_hal_rtn_e
ocs_hal_init(ocs_hal_t *hal)
{
ocs_hal_rtn_e rc;
uint32_t i = 0;
uint8_t buf[SLI4_BMBX_SIZE];
uint32_t max_rpi;
int rem_count;
int written_size = 0;
uint32_t count;
char prop_buf[32];
uint32_t ramdisc_blocksize = 512;
uint32_t q_count = 0;
/*
* Make sure the command lists are empty. If this is start-of-day,
* they'll be empty since they were just initialized in ocs_hal_setup.
* If we've just gone through a reset, the command and command pending
* lists should have been cleaned up as part of the reset (ocs_hal_reset()).
*/
ocs_lock(&hal->cmd_lock);
if (!ocs_list_empty(&hal->cmd_head)) {
ocs_log_test(hal->os, "%s: command found on cmd list\n", __func__);
ocs_unlock(&hal->cmd_lock);
return OCS_HAL_RTN_ERROR;
}
if (!ocs_list_empty(&hal->cmd_pending)) {
ocs_log_test(hal->os, "%s: command found on pending list\n", __func__);
ocs_unlock(&hal->cmd_lock);
return OCS_HAL_RTN_ERROR;
}
ocs_unlock(&hal->cmd_lock);
/* Free RQ buffers if prevously allocated */
ocs_hal_rx_free(hal);
/*
* The IO queues must be initialized here for the reset case. The
* ocs_hal_init_io() function will re-add the IOs to the free list.
* The cmd_head list should be OK since we free all entries in
* ocs_hal_command_cancel() that is called in the ocs_hal_reset().
*/
/* If we are in this function due to a reset, there may be stale items
* on lists that need to be removed. Clean them up.
*/
rem_count=0;
if (ocs_list_valid(&hal->io_wait_free)) {
while ((!ocs_list_empty(&hal->io_wait_free))) {
rem_count++;
ocs_list_remove_head(&hal->io_wait_free);
}
if (rem_count > 0) {
ocs_log_debug(hal->os, "%s: removed %d items from io_wait_free list\n", __func__, rem_count);
}
}
rem_count=0;
if (ocs_list_valid(&hal->io_inuse)) {
while ((!ocs_list_empty(&hal->io_inuse))) {
rem_count++;
ocs_list_remove_head(&hal->io_inuse);
}
if (rem_count > 0) {
ocs_log_debug(hal->os, "%s: removed %d items from io_inuse list\n", __func__, rem_count);
}
}
rem_count=0;
if (ocs_list_valid(&hal->io_free)) {
while ((!ocs_list_empty(&hal->io_free))) {
rem_count++;
ocs_list_remove_head(&hal->io_free);
}
if (rem_count > 0) {
ocs_log_debug(hal->os, "%s: removed %d items from io_free list\n", __func__, rem_count);
}
}
if (ocs_list_valid(&hal->io_port_owned)) {
while ((!ocs_list_empty(&hal->io_port_owned))) {
ocs_list_remove_head(&hal->io_port_owned);
}
}
ocs_list_init(&hal->io_inuse, ocs_hal_io_t, link);
ocs_list_init(&hal->io_free, ocs_hal_io_t, link);
ocs_list_init(&hal->io_port_owned, ocs_hal_io_t, link);
ocs_list_init(&hal->io_wait_free, ocs_hal_io_t, link);
ocs_list_init(&hal->io_timed_wqe, ocs_hal_io_t, wqe_link);
ocs_list_init(&hal->io_port_dnrx, ocs_hal_io_t, dnrx_link);
if (ocs_get_property("ramdisc_blocksize", prop_buf, sizeof(prop_buf)) == 0) {
ramdisc_blocksize = ocs_strtoul(prop_buf, 0, 0);
}
/* If MRQ not required, Make sure we dont request feature. */
if (hal->config.n_rq == 1) {
hal->sli.config.features.flag.mrqp = FALSE;
}
if (sli_init(&hal->sli)) {
ocs_log_err(hal->os, "SLI failed to initialize\n");
return OCS_HAL_RTN_ERROR;
}
/*
* Enable the auto xfer rdy feature if requested.
*/
hal->auto_xfer_rdy_enabled = FALSE;
if (sli_get_auto_xfer_rdy_capable(&hal->sli) &&
hal->config.auto_xfer_rdy_size > 0) {
if (hal->config.esoc){
written_size = sli_cmd_config_auto_xfer_rdy_hp(&hal->sli, buf, SLI4_BMBX_SIZE, hal->config.auto_xfer_rdy_size, 1, ramdisc_blocksize);
} else {
written_size = sli_cmd_config_auto_xfer_rdy(&hal->sli, buf, SLI4_BMBX_SIZE, hal->config.auto_xfer_rdy_size);
}
if (written_size) {
rc = ocs_hal_command(hal, buf, OCS_CMD_POLL, NULL, NULL);
if (rc != OCS_HAL_RTN_SUCCESS) {
ocs_log_err(hal->os, "%s: config auto xfer rdy failed\n", __func__);
return rc;
}
}
hal->auto_xfer_rdy_enabled = TRUE;
if (hal->config.auto_xfer_rdy_t10_enable) {
rc = ocs_hal_config_auto_xfer_rdy_t10pi(hal, buf);
if (rc != OCS_HAL_RTN_SUCCESS) {
ocs_log_err(hal->os, "%s: set parameters auto xfer rdy T10 PI failed\n", __func__);
return rc;
}
}
}
if(hal->sliport_healthcheck) {
rc = ocs_hal_config_sli_port_health_check(hal, 0, 1);
if (rc != OCS_HAL_RTN_SUCCESS) {
ocs_log_err(hal->os, "%s: Enabling Sliport Health check failed \n", __func__);
return rc;
}
}
/*
* Set FDT transfer hint, only works on Lancer
*/
if ((hal->sli.if_type == SLI4_IF_TYPE_LANCER_FC_ETH) && (OCS_HAL_FDT_XFER_HINT != 0)) {
/*
* Non-fatal error. In particular, we can disregard failure to set OCS_HAL_FDT_XFER_HINT on
* devices with legacy firmware that do not support OCS_HAL_FDT_XFER_HINT feature.
*/
ocs_hal_config_set_fdt_xfer_hint(hal, OCS_HAL_FDT_XFER_HINT);
}
/*
* Verify that we have not exceeded any queue sizes
*/
q_count = MIN(sli_get_max_queue(&hal->sli, SLI_QTYPE_EQ), OCS_HAL_MAX_NUM_EQ);
if (hal->config.n_eq > q_count) {
ocs_log_err(hal->os, "requested %d EQ but %d allowed\n",
hal->config.n_eq, q_count);
return OCS_HAL_RTN_ERROR;
}
q_count = MIN(sli_get_max_queue(&hal->sli, SLI_QTYPE_CQ), OCS_HAL_MAX_NUM_CQ);
if (hal->config.n_cq > sli_get_max_queue(&hal->sli, SLI_QTYPE_CQ)) {
ocs_log_err(hal->os, "requested %d CQ but %d allowed\n",
hal->config.n_cq, q_count);
return OCS_HAL_RTN_ERROR;
}
q_count = MIN(sli_get_max_queue(&hal->sli, SLI_QTYPE_MQ), OCS_HAL_MAX_NUM_MQ);
if (hal->config.n_mq > sli_get_max_queue(&hal->sli, SLI_QTYPE_MQ)) {
ocs_log_err(hal->os, "requested %d MQ but %d allowed\n",
hal->config.n_mq, q_count);
return OCS_HAL_RTN_ERROR;
}
q_count = MIN(sli_get_max_queue(&hal->sli, SLI_QTYPE_RQ), OCS_HAL_MAX_NUM_RQ);
if (hal->config.n_rq > sli_get_max_queue(&hal->sli, SLI_QTYPE_RQ)) {
ocs_log_err(hal->os, "requested %d RQ but %d allowed\n",
hal->config.n_rq, q_count);
return OCS_HAL_RTN_ERROR;
}
q_count = MIN(sli_get_max_queue(&hal->sli, SLI_QTYPE_WQ), OCS_HAL_MAX_NUM_WQ);
if (hal->config.n_wq > sli_get_max_queue(&hal->sli, SLI_QTYPE_WQ)) {
ocs_log_err(hal->os, "requested %d WQ but %d allowed\n",
hal->config.n_wq, q_count);
return OCS_HAL_RTN_ERROR;
}
/* zero the hashes */
ocs_memset(hal->cq_hash, 0, sizeof(hal->cq_hash));
ocs_log_debug(hal->os, "%s Max CQs %d, hash size = %d\n",
__func__, OCS_HAL_MAX_NUM_CQ, OCS_HAL_Q_HASH_SIZE);
ocs_memset(hal->rq_hash, 0, sizeof(hal->rq_hash));
ocs_log_debug(hal->os, "%s Max RQs %d, hash size = %d\n",
__func__, OCS_HAL_MAX_NUM_RQ, OCS_HAL_Q_HASH_SIZE);
ocs_memset(hal->wq_hash, 0, sizeof(hal->wq_hash));
ocs_log_debug(hal->os, "%s Max WQs %d, hash size = %d\n",
__func__, OCS_HAL_MAX_NUM_WQ, OCS_HAL_Q_HASH_SIZE);
rc = ocs_hal_init_queues(hal, hal->qtop);
if (rc != OCS_HAL_RTN_SUCCESS) {
return rc;
}
max_rpi = sli_get_max_rsrc(&hal->sli, SLI_RSRC_FCOE_RPI);
i = sli_fc_get_rpi_requirements(&hal->sli, max_rpi);
if (i) {
ocs_dma_t payload_memory;
rc = OCS_HAL_RTN_ERROR;
if (hal->rnode_mem.size) {
ocs_dma_free(hal->os, &hal->rnode_mem);
}
if (ocs_dma_alloc(hal->os, &hal->rnode_mem, i, 4096)) {
ocs_log_err(hal->os, "%s: remote node memory allocation fail\n", __func__);
return OCS_HAL_RTN_NO_MEMORY;
}
payload_memory.size = 0;
if (sli_cmd_fcoe_post_hdr_templates(&hal->sli, buf, SLI4_BMBX_SIZE,
&hal->rnode_mem, UINT16_MAX, &payload_memory)) {
rc = ocs_hal_command(hal, buf, OCS_CMD_POLL, NULL, NULL);
if (payload_memory.size != 0) {
/* The command was non-embedded - need to free the dma buffer */
ocs_dma_free(hal->os, &payload_memory);
}
}
if (rc != OCS_HAL_RTN_SUCCESS) {
ocs_log_err(hal->os, "%s: header template registration failed\n", __func__);
return rc;
}
}
/* Allocate and post RQ buffers */
rc = ocs_hal_rx_allocate(hal);
if (rc) {
ocs_log_err(hal->os, "rx_allocate failed\n");
return rc;
}
/* Populate hal->seq_free_list */
if (hal->seq_pool == NULL) {
uint32_t count = 0;
uint32_t i;
/* Sum up the total number of RQ entries, to use to allocate the sequence object pool */
for (i = 0; i < hal->hal_rq_count; i++) {
count += hal->hal_rq[i]->entry_count;
}
hal->seq_pool = ocs_array_alloc(hal->os, sizeof(ocs_hal_sequence_t), count);
if (hal->seq_pool == NULL) {
ocs_log_err(hal->os, "%s: malloc seq_pool failed\n", __func__);
return OCS_HAL_RTN_NO_MEMORY;
}
}
if(ocs_hal_rx_post(hal)) {
ocs_log_err(hal->os, "%s: WARNING - error posting RQ buffers\n", __func__);
}
/* Allocate rpi_ref if not previously allocated */
if (hal->rpi_ref == NULL) {
hal->rpi_ref = ocs_malloc(hal->os, max_rpi * sizeof(*hal->rpi_ref),
OCS_M_ZERO | OCS_M_NOWAIT);
if (hal->rpi_ref == NULL) {
ocs_log_err(hal->os, "rpi_ref allocation failure (%d)\n", i);
return OCS_HAL_RTN_NO_MEMORY;
}
}
for (i = 0; i < max_rpi; i ++) {
ocs_atomic_init(&hal->rpi_ref[i].rpi_count, 0);
ocs_atomic_init(&hal->rpi_ref[i].rpi_attached, 0);
}
ocs_memset(hal->domains, 0, sizeof(hal->domains));
/* HAL_WORKAROUND_OVERRIDE_FCFI_IN_SRB */
if (hal->workaround.override_fcfi) {
hal->first_domain_idx = -1;
}
ocs_memset(hal->fcf_index_fcfi, 0, sizeof(hal->fcf_index_fcfi));
/* Register a FCFI to allow unsolicited frames to be routed to the driver */
if (sli_get_medium(&hal->sli) == SLI_LINK_MEDIUM_FC) {
if (hal->hal_mrq_used) {
ocs_log_info(hal->os, "%s: using REG_FCFI MRQ\n", __func__);
rc = ocs_hal_config_mrq(hal, SLI4_CMD_REG_FCFI_SET_FCFI_MODE, 0, 0);
if (rc != OCS_HAL_RTN_SUCCESS) {
ocs_log_err(hal->os, "%s: REG_FCFI_MRQ FCFI registration failed\n", __func__);
return rc;
}
rc = ocs_hal_config_mrq(hal, SLI4_CMD_REG_FCFI_SET_MRQ_MODE, 0, 0);
if (rc != OCS_HAL_RTN_SUCCESS) {
ocs_log_err(hal->os, "%s: REG_FCFI_MRQ MRQ registration failed\n", __func__);
return rc;
}
} else {
sli4_cmd_rq_cfg_t rq_cfg[SLI4_CMD_REG_FCFI_NUM_RQ_CFG];
ocs_log_info(hal->os, "%s: using REG_FCFI standard\n", __func__);
/* Set the filter match/mask values from hal's filter_def values */
for (i = 0; i < SLI4_CMD_REG_FCFI_NUM_RQ_CFG; i++) {
rq_cfg[i].rq_id = 0xffff;
rq_cfg[i].r_ctl_mask = (uint8_t) hal->config.filter_def[i];
rq_cfg[i].r_ctl_match = (uint8_t) (hal->config.filter_def[i] >> 8);
rq_cfg[i].type_mask = (uint8_t) (hal->config.filter_def[i] >> 16);
rq_cfg[i].type_match = (uint8_t) (hal->config.filter_def[i] >> 24);
}
/*
* Update the rq_id's of the FCF configuration (don't update more than the number
* of rq_cfg elements)
*/
for (i = 0; i < OCS_MIN(hal->hal_rq_count, SLI4_CMD_REG_FCFI_NUM_RQ_CFG); i++) {
hal_rq_t *rq = hal->hal_rq[i];
uint32_t j;
for (j = 0; j < SLI4_CMD_REG_FCFI_NUM_RQ_CFG; j++) {
uint32_t mask = (rq->filter_mask != 0) ? rq->filter_mask : 1;
if (mask & (1U << j)) {
rq_cfg[j].rq_id = rq->hdr->id;
ocs_log_info(hal->os, "REG_FCFI: filter[%d] %08X -> RQ[%d] id=%d\n",
j, hal->config.filter_def[j], i, rq->hdr->id);
}
}
}
rc = OCS_HAL_RTN_ERROR;
if (sli_cmd_reg_fcfi(&hal->sli, buf, SLI4_BMBX_SIZE, 0, rq_cfg, 0)) {
rc = ocs_hal_command(hal, buf, OCS_CMD_POLL, NULL, NULL);
}
if (rc != OCS_HAL_RTN_SUCCESS) {
ocs_log_err(hal->os, "%s: FCFI registration failed\n", __func__);
return rc;
}
hal->fcf_indicator = ((sli4_cmd_reg_fcfi_t *)buf)->fcfi;
}
}
/*
* Allocate the WQ request tag pool, if not previously allocated (the request tag value is 16 bits,
* thus the pool allocation size of 64k)
*/
rc = ocs_hal_reqtag_init(hal);
if (rc) {
ocs_log_err(hal->os, "%s: ocs_pool_alloc hal_wq_callback_t failed: %d\n", __func__, rc);
return rc;
}
rc = ocs_hal_setup_io(hal);
if (rc) {
ocs_log_err(hal->os, "%s: IO allocation failure\n", __func__);
return rc;
}
rc = ocs_hal_init_io(hal);
if (rc) {
ocs_log_err(hal->os, "%s: IO initialization failure\n", __func__);
return rc;
}
ocs_queue_history_init(hal->os, &hal->q_hist);
/* get hw link config; polling, so callback will be called immediately */
hal->linkcfg = OCS_HAL_LINKCFG_NA;
ocs_hal_get_linkcfg(hal, OCS_CMD_POLL, ocs_hal_init_linkcfg_cb, hal);
/* if lancer ethernet, ethernet ports need to be enabled */
if ((hal->sli.if_type == SLI4_IF_TYPE_LANCER_FC_ETH) &&
(sli_get_medium(&hal->sli) == SLI_LINK_MEDIUM_ETHERNET)) {
if (ocs_hal_set_eth_license(hal, hal->eth_license)) {
/* log warning but continue */
ocs_log_err(hal->os, "%s: Failed to set ethernet license\n", __func__);
}
}
/* Set the DIF seed - only for lancer right now */
if (SLI4_IF_TYPE_LANCER_FC_ETH == sli_get_if_type(&hal->sli) &&
ocs_hal_set_dif_seed(hal) != OCS_HAL_RTN_SUCCESS) {
ocs_log_err(hal->os, "%s: Failed to set DIF seed value\n", __func__);
return rc;
}
/* Set the DIF mode - skyhawk only */
if (SLI4_IF_TYPE_BE3_SKH_PF == sli_get_if_type(&hal->sli) &&
sli_get_dif_capable(&hal->sli)) {
rc = ocs_hal_set_dif_mode(hal);
if (rc != OCS_HAL_RTN_SUCCESS) {
ocs_log_err(hal->os, "%s: Failed to set DIF mode value\n", __func__);
return rc;
}
}
/*
* Arming the EQ allows (e.g.) interrupts when CQ completions write EQ entries
*/
for (i = 0; i < hal->eq_count; i++) {
sli_queue_arm(&hal->sli, &hal->eq[i], TRUE);
}
/*
* Initialize RQ hash
*/
for (i = 0; i < hal->rq_count; i++) {
ocs_hal_queue_hash_add(hal->rq_hash, hal->rq[i].id, i);
}
/*
* Initialize WQ hash
*/
for (i = 0; i < hal->wq_count; i++) {
ocs_hal_queue_hash_add(hal->wq_hash, hal->wq[i].id, i);
}
/*
* Arming the CQ allows (e.g.) MQ completions to write CQ entries
*/
for (i = 0; i < hal->cq_count; i++) {
ocs_hal_queue_hash_add(hal->cq_hash, hal->cq[i].id, i);
sli_queue_arm(&hal->sli, &hal->cq[i], TRUE);
}
/* record the fact that the queues are functional */
hal->state = OCS_HAL_STATE_ACTIVE;
/* Note: Must be after the IOs are setup and the state is active*/
if (ocs_hal_rqpair_init(hal)) {
ocs_log_err(hal->os, "%s: WARNING - error initializing RQ pair\n", __func__);
}
/* finally kick off periodic timer to check for timed out target WQEs */
if (hal->config.emulate_tgt_wqe_timeout) {
ocs_setup_timer(hal->os, &hal->wqe_timer, target_wqe_timer_cb, hal,
OCS_HAL_WQ_TIMER_PERIOD_MS);
}
/*
* Allocate a HAL IOs for send frame. Allocate one for each Class 1 WQ, or if there
* are none of those, allocate one for WQ[0]
*/
if ((count = ocs_varray_get_count(hal->wq_class_array[1])) > 0) {
for (i = 0; i < count; i++) {
hal_wq_t *wq = ocs_varray_iter_next(hal->wq_class_array[1]);
wq->send_frame_io = ocs_hal_io_alloc(hal);
if (wq->send_frame_io == NULL) {
ocs_log_err(hal->os, "%s: ocs_hal_io_alloc for send_frame_io failed\n", __func__);
}
}
} else {
hal->hal_wq[0]->send_frame_io = ocs_hal_io_alloc(hal);
if (hal->hal_wq[0]->send_frame_io == NULL) {
ocs_log_err(hal->os, "%s: ocs_hal_io_alloc for send_frame_io failed\n", __func__);
}
}
/* Initialize send frame frame sequence id */
ocs_atomic_init(&hal->send_frame_seq_id, 0);
/* Initialize watchdog timer if enabled by user */
if(hal->watchdog_timeout) {
if((hal->watchdog_timeout < 1) || (hal->watchdog_timeout > 65534)) {
ocs_log_err(hal->os, "%s: watchdog_timeout out of range: Valid range is 1 - 65534\n", __func__);
}else if(!ocs_hal_config_watchdog_timer(hal)) {
ocs_log_info(hal->os, "watchdog timer configured with timeout = %d seconds \n", hal->watchdog_timeout);
}
}
return OCS_HAL_RTN_SUCCESS;
}
/**
* @brief Configure Multi-RQ
*
* @param hal Hardware context allocated by the caller.
* @param mode 1 to set MRQ filters and 0 to set FCFI index
* @param vlanid valid in mode 0
* @param fcf_index valid in mode 0
*
* @return Returns 0 on success, or a non-zero value on failure.
*/
static int32_t
ocs_hal_config_mrq(ocs_hal_t *hal, uint8_t mode, uint16_t vlanid, uint16_t fcf_index)
{
uint8_t buf[SLI4_BMBX_SIZE];
hal_rq_t *rq;
sli4_cmd_reg_fcfi_mrq_t *rsp = NULL;
uint32_t i, j;
sli4_cmd_rq_cfg_t rq_filter[SLI4_CMD_REG_FCFI_NUM_RQ_CFG];
int32_t rc;