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vivado.log
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#-----------------------------------------------------------
# Vivado v2017.4 (64-bit)
# SW Build 2086221 on Fri Dec 15 20:55:39 MST 2017
# IP Build 2085800 on Fri Dec 15 22:25:07 MST 2017
# Start of session at: Mon Dec 2 19:22:19 2019
# Process ID: 15012
# Current directory: H:/363/project_5
# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent13896 H:\363\project_5\project_5.xpr
# Log file: H:/363/project_5/vivado.log
# Journal file: H:/363/project_5\vivado.jou
#-----------------------------------------------------------
start_gui
open_project H:/363/project_5/project_5.xpr
Scanning sources...
Finished scanning sources
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2017.4/data/ip'.
open_project: Time (s): cpu = 00:00:09 ; elapsed = 00:00:07 . Memory (MB): peak = 713.984 ; gain = 19.328
update_compile_order -fileset sources_1
launch_simulation
INFO: [Vivado 12-5682] Launching behavioral simulation in 'H:/363/project_5/project_5.sim/sim_1/behav/xsim'
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [SIM-utils-54] Inspecting design source files for 'testbench' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'H:/363/project_5/project_5.sim/sim_1/behav/xsim'
"xvlog --incr --relax -prj testbench_vlog.prj"
INFO: [VRFC 10-2263] Analyzing Verilog file "H:/363/project_5/project_5.srcs/sources_1/new/ALU.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ALU
INFO: [VRFC 10-2263] Analyzing Verilog file "H:/363/project_5/project_5.srcs/sources_1/new/Controller.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Controller
INFO: [VRFC 10-2263] Analyzing Verilog file "H:/363/project_5/project_5.srcs/sources_1/new/Datapath.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Datapath
INFO: [VRFC 10-2263] Analyzing Verilog file "H:/363/project_5/project_5.srcs/sources_1/new/Processor.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Processor
INFO: [VRFC 10-2263] Analyzing Verilog file "H:/363/project_5/project_5.srcs/sources_1/new/Register.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Register
INFO: [VRFC 10-2263] Analyzing Verilog file "H:/363/project_5/project_5.srcs/sim_1/new/testbench.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module testbench
INFO: [USF-XSim-69] 'compile' step finished in '2' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'H:/363/project_5/project_5.sim/sim_1/behav/xsim'
Vivado Simulator 2017.4
Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved.
Running: C:/Xilinx/Vivado/2017.4/bin/unwrapped/win64.o/xelab.exe -wto b6bb88ed20fa4300ab5d89fe1afc2363 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot testbench_behav xil_defaultlib.testbench xil_defaultlib.glbl -log elaborate.log
Using 2 slave threads.
Starting static elaboration
ERROR: [VRFC 10-529] concurrent assignment to a non-net readReg1 is not permitted [H:/363/project_5/project_5.srcs/sources_1/new/Processor.v:124]
ERROR: [XSIM 43-3322] Static elaboration of top level Verilog design unit(s) in library work failed.
INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds
INFO: [USF-XSim-99] Step results log file:'H:/363/project_5/project_5.sim/sim_1/behav/xsim/elaborate.log'
ERROR: [USF-XSim-62] 'elaborate' step failed with error(s). Please check the Tcl console output or 'H:/363/project_5/project_5.sim/sim_1/behav/xsim/elaborate.log' file for more information.
ERROR: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation.
launch_simulation: Time (s): cpu = 00:00:02 ; elapsed = 00:00:05 . Memory (MB): peak = 772.590 ; gain = 0.000
ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors.
launch_simulation
INFO: [Vivado 12-5682] Launching behavioral simulation in 'H:/363/project_5/project_5.sim/sim_1/behav/xsim'
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [SIM-utils-54] Inspecting design source files for 'testbench' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'H:/363/project_5/project_5.sim/sim_1/behav/xsim'
"xvlog --incr --relax -prj testbench_vlog.prj"
INFO: [VRFC 10-2263] Analyzing Verilog file "H:/363/project_5/project_5.srcs/sources_1/new/ALU.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ALU
INFO: [VRFC 10-2263] Analyzing Verilog file "H:/363/project_5/project_5.srcs/sources_1/new/Controller.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Controller
INFO: [VRFC 10-2263] Analyzing Verilog file "H:/363/project_5/project_5.srcs/sources_1/new/Datapath.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Datapath
INFO: [VRFC 10-2263] Analyzing Verilog file "H:/363/project_5/project_5.srcs/sources_1/new/Processor.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Processor
INFO: [VRFC 10-2263] Analyzing Verilog file "H:/363/project_5/project_5.srcs/sources_1/new/Register.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Register
INFO: [VRFC 10-2263] Analyzing Verilog file "H:/363/project_5/project_5.srcs/sim_1/new/testbench.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module testbench
INFO: [USF-XSim-69] 'compile' step finished in '2' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'H:/363/project_5/project_5.sim/sim_1/behav/xsim'
Vivado Simulator 2017.4
Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved.
Running: C:/Xilinx/Vivado/2017.4/bin/unwrapped/win64.o/xelab.exe -wto b6bb88ed20fa4300ab5d89fe1afc2363 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot testbench_behav xil_defaultlib.testbench xil_defaultlib.glbl -log elaborate.log
Using 2 slave threads.
Starting static elaboration
ERROR: [VRFC 10-529] concurrent assignment to a non-net readReg2 is not permitted [H:/363/project_5/project_5.srcs/sources_1/new/Processor.v:124]
ERROR: [XSIM 43-3322] Static elaboration of top level Verilog design unit(s) in library work failed.
INFO: [USF-XSim-69] 'elaborate' step finished in '1' seconds
INFO: [USF-XSim-99] Step results log file:'H:/363/project_5/project_5.sim/sim_1/behav/xsim/elaborate.log'
ERROR: [USF-XSim-62] 'elaborate' step failed with error(s). Please check the Tcl console output or 'H:/363/project_5/project_5.sim/sim_1/behav/xsim/elaborate.log' file for more information.
ERROR: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation.
launch_simulation: Time (s): cpu = 00:00:00 ; elapsed = 00:00:07 . Memory (MB): peak = 773.426 ; gain = 0.000
ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors.
launch_simulation
INFO: [Vivado 12-5682] Launching behavioral simulation in 'H:/363/project_5/project_5.sim/sim_1/behav/xsim'
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [SIM-utils-54] Inspecting design source files for 'testbench' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'H:/363/project_5/project_5.sim/sim_1/behav/xsim'
"xvlog --incr --relax -prj testbench_vlog.prj"
INFO: [VRFC 10-2263] Analyzing Verilog file "H:/363/project_5/project_5.srcs/sources_1/new/ALU.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ALU
INFO: [VRFC 10-2263] Analyzing Verilog file "H:/363/project_5/project_5.srcs/sources_1/new/Controller.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Controller
INFO: [VRFC 10-2263] Analyzing Verilog file "H:/363/project_5/project_5.srcs/sources_1/new/Datapath.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Datapath
INFO: [VRFC 10-2263] Analyzing Verilog file "H:/363/project_5/project_5.srcs/sources_1/new/Processor.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Processor
INFO: [VRFC 10-2263] Analyzing Verilog file "H:/363/project_5/project_5.srcs/sources_1/new/Register.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Register
INFO: [VRFC 10-2263] Analyzing Verilog file "H:/363/project_5/project_5.srcs/sim_1/new/testbench.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module testbench
INFO: [USF-XSim-69] 'compile' step finished in '1' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'H:/363/project_5/project_5.sim/sim_1/behav/xsim'
Vivado Simulator 2017.4
Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved.
Running: C:/Xilinx/Vivado/2017.4/bin/unwrapped/win64.o/xelab.exe -wto b6bb88ed20fa4300ab5d89fe1afc2363 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot testbench_behav xil_defaultlib.testbench xil_defaultlib.glbl -log elaborate.log
Using 2 slave threads.
Starting static elaboration
ERROR: [VRFC 10-529] concurrent assignment to a non-net PC is not permitted [H:/363/project_5/project_5.srcs/sources_1/new/Processor.v:124]
ERROR: [XSIM 43-3322] Static elaboration of top level Verilog design unit(s) in library work failed.
INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds
INFO: [USF-XSim-99] Step results log file:'H:/363/project_5/project_5.sim/sim_1/behav/xsim/elaborate.log'
ERROR: [USF-XSim-62] 'elaborate' step failed with error(s). Please check the Tcl console output or 'H:/363/project_5/project_5.sim/sim_1/behav/xsim/elaborate.log' file for more information.
ERROR: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation.
ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors.
launch_simulation
INFO: [Vivado 12-5682] Launching behavioral simulation in 'H:/363/project_5/project_5.sim/sim_1/behav/xsim'
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [SIM-utils-54] Inspecting design source files for 'testbench' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'H:/363/project_5/project_5.sim/sim_1/behav/xsim'
"xvlog --incr --relax -prj testbench_vlog.prj"
INFO: [VRFC 10-2263] Analyzing Verilog file "H:/363/project_5/project_5.srcs/sources_1/new/ALU.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ALU
INFO: [VRFC 10-2263] Analyzing Verilog file "H:/363/project_5/project_5.srcs/sources_1/new/Controller.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Controller
INFO: [VRFC 10-2263] Analyzing Verilog file "H:/363/project_5/project_5.srcs/sources_1/new/Datapath.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Datapath
INFO: [VRFC 10-2263] Analyzing Verilog file "H:/363/project_5/project_5.srcs/sources_1/new/Processor.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Processor
INFO: [VRFC 10-2263] Analyzing Verilog file "H:/363/project_5/project_5.srcs/sources_1/new/Register.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Register
INFO: [VRFC 10-2263] Analyzing Verilog file "H:/363/project_5/project_5.srcs/sim_1/new/testbench.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module testbench
INFO: [USF-XSim-69] 'compile' step finished in '2' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'H:/363/project_5/project_5.sim/sim_1/behav/xsim'
Vivado Simulator 2017.4
Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved.
Running: C:/Xilinx/Vivado/2017.4/bin/unwrapped/win64.o/xelab.exe -wto b6bb88ed20fa4300ab5d89fe1afc2363 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot testbench_behav xil_defaultlib.testbench xil_defaultlib.glbl -log elaborate.log
Using 2 slave threads.
Starting static elaboration
ERROR: [VRFC 10-529] concurrent assignment to a non-net PC is not permitted [H:/363/project_5/project_5.srcs/sources_1/new/Processor.v:124]
ERROR: [XSIM 43-3322] Static elaboration of top level Verilog design unit(s) in library work failed.
INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds
INFO: [USF-XSim-99] Step results log file:'H:/363/project_5/project_5.sim/sim_1/behav/xsim/elaborate.log'
ERROR: [USF-XSim-62] 'elaborate' step failed with error(s). Please check the Tcl console output or 'H:/363/project_5/project_5.sim/sim_1/behav/xsim/elaborate.log' file for more information.
ERROR: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation.
launch_simulation: Time (s): cpu = 00:00:00 ; elapsed = 00:00:05 . Memory (MB): peak = 773.426 ; gain = 0.000
ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors.
launch_simulation
INFO: [Vivado 12-5682] Launching behavioral simulation in 'H:/363/project_5/project_5.sim/sim_1/behav/xsim'
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [SIM-utils-54] Inspecting design source files for 'testbench' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'H:/363/project_5/project_5.sim/sim_1/behav/xsim'
"xvlog --incr --relax -prj testbench_vlog.prj"
INFO: [VRFC 10-2263] Analyzing Verilog file "H:/363/project_5/project_5.srcs/sources_1/new/ALU.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ALU
INFO: [VRFC 10-2263] Analyzing Verilog file "H:/363/project_5/project_5.srcs/sources_1/new/Controller.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Controller
INFO: [VRFC 10-2263] Analyzing Verilog file "H:/363/project_5/project_5.srcs/sources_1/new/Datapath.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Datapath
INFO: [VRFC 10-2263] Analyzing Verilog file "H:/363/project_5/project_5.srcs/sources_1/new/Processor.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Processor
INFO: [VRFC 10-2263] Analyzing Verilog file "H:/363/project_5/project_5.srcs/sources_1/new/Register.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Register
INFO: [VRFC 10-2263] Analyzing Verilog file "H:/363/project_5/project_5.srcs/sim_1/new/testbench.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module testbench
INFO: [USF-XSim-69] 'compile' step finished in '2' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'H:/363/project_5/project_5.sim/sim_1/behav/xsim'
Vivado Simulator 2017.4
Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved.
Running: C:/Xilinx/Vivado/2017.4/bin/unwrapped/win64.o/xelab.exe -wto b6bb88ed20fa4300ab5d89fe1afc2363 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot testbench_behav xil_defaultlib.testbench xil_defaultlib.glbl -log elaborate.log
Using 2 slave threads.
Starting static elaboration
ERROR: [VRFC 10-529] concurrent assignment to a non-net Result is not permitted [H:/363/project_5/project_5.srcs/sources_1/new/Processor.v:124]
ERROR: [XSIM 43-3322] Static elaboration of top level Verilog design unit(s) in library work failed.
INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds
INFO: [USF-XSim-99] Step results log file:'H:/363/project_5/project_5.sim/sim_1/behav/xsim/elaborate.log'
ERROR: [USF-XSim-62] 'elaborate' step failed with error(s). Please check the Tcl console output or 'H:/363/project_5/project_5.sim/sim_1/behav/xsim/elaborate.log' file for more information.
ERROR: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation.
launch_simulation: Time (s): cpu = 00:00:00 ; elapsed = 00:00:06 . Memory (MB): peak = 773.426 ; gain = 0.000
ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors.
launch_simulation
INFO: [Vivado 12-5682] Launching behavioral simulation in 'H:/363/project_5/project_5.sim/sim_1/behav/xsim'
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [SIM-utils-54] Inspecting design source files for 'testbench' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'H:/363/project_5/project_5.sim/sim_1/behav/xsim'
"xvlog --incr --relax -prj testbench_vlog.prj"
INFO: [VRFC 10-2263] Analyzing Verilog file "H:/363/project_5/project_5.srcs/sources_1/new/ALU.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ALU
INFO: [VRFC 10-2263] Analyzing Verilog file "H:/363/project_5/project_5.srcs/sources_1/new/Controller.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Controller
INFO: [VRFC 10-2263] Analyzing Verilog file "H:/363/project_5/project_5.srcs/sources_1/new/Datapath.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Datapath
INFO: [VRFC 10-2263] Analyzing Verilog file "H:/363/project_5/project_5.srcs/sources_1/new/Processor.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Processor
INFO: [VRFC 10-2263] Analyzing Verilog file "H:/363/project_5/project_5.srcs/sources_1/new/Register.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Register
INFO: [VRFC 10-2263] Analyzing Verilog file "H:/363/project_5/project_5.srcs/sim_1/new/testbench.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module testbench
INFO: [USF-XSim-69] 'compile' step finished in '2' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'H:/363/project_5/project_5.sim/sim_1/behav/xsim'
Vivado Simulator 2017.4
Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved.
Running: C:/Xilinx/Vivado/2017.4/bin/unwrapped/win64.o/xelab.exe -wto b6bb88ed20fa4300ab5d89fe1afc2363 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot testbench_behav xil_defaultlib.testbench xil_defaultlib.glbl -log elaborate.log
Using 2 slave threads.
Starting static elaboration
ERROR: [VRFC 10-529] concurrent assignment to a non-net result is not permitted [H:/363/project_5/project_5.srcs/sources_1/new/Datapath.v:14]
ERROR: [XSIM 43-3322] Static elaboration of top level Verilog design unit(s) in library work failed.
INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds
INFO: [USF-XSim-99] Step results log file:'H:/363/project_5/project_5.sim/sim_1/behav/xsim/elaborate.log'
ERROR: [USF-XSim-62] 'elaborate' step failed with error(s). Please check the Tcl console output or 'H:/363/project_5/project_5.sim/sim_1/behav/xsim/elaborate.log' file for more information.
ERROR: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation.
launch_simulation: Time (s): cpu = 00:00:01 ; elapsed = 00:00:05 . Memory (MB): peak = 773.426 ; gain = 0.000
ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors.
launch_simulation
INFO: [Vivado 12-5682] Launching behavioral simulation in 'H:/363/project_5/project_5.sim/sim_1/behav/xsim'
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [SIM-utils-54] Inspecting design source files for 'testbench' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'H:/363/project_5/project_5.sim/sim_1/behav/xsim'
"xvlog --incr --relax -prj testbench_vlog.prj"
INFO: [VRFC 10-2263] Analyzing Verilog file "H:/363/project_5/project_5.srcs/sources_1/new/ALU.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ALU
INFO: [VRFC 10-2263] Analyzing Verilog file "H:/363/project_5/project_5.srcs/sources_1/new/Controller.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Controller
INFO: [VRFC 10-2263] Analyzing Verilog file "H:/363/project_5/project_5.srcs/sources_1/new/Datapath.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Datapath
INFO: [VRFC 10-2263] Analyzing Verilog file "H:/363/project_5/project_5.srcs/sources_1/new/Processor.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Processor
INFO: [VRFC 10-2263] Analyzing Verilog file "H:/363/project_5/project_5.srcs/sources_1/new/Register.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Register
INFO: [VRFC 10-2263] Analyzing Verilog file "H:/363/project_5/project_5.srcs/sim_1/new/testbench.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module testbench
INFO: [USF-XSim-69] 'compile' step finished in '2' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'H:/363/project_5/project_5.sim/sim_1/behav/xsim'
Vivado Simulator 2017.4
Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved.
Running: C:/Xilinx/Vivado/2017.4/bin/unwrapped/win64.o/xelab.exe -wto b6bb88ed20fa4300ab5d89fe1afc2363 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot testbench_behav xil_defaultlib.testbench xil_defaultlib.glbl -log elaborate.log
Using 2 slave threads.
Starting static elaboration
ERROR: [VRFC 10-529] concurrent assignment to a non-net zFlag is not permitted [H:/363/project_5/project_5.srcs/sources_1/new/Datapath.v:14]
ERROR: [XSIM 43-3322] Static elaboration of top level Verilog design unit(s) in library work failed.
INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds
INFO: [USF-XSim-99] Step results log file:'H:/363/project_5/project_5.sim/sim_1/behav/xsim/elaborate.log'
ERROR: [USF-XSim-62] 'elaborate' step failed with error(s). Please check the Tcl console output or 'H:/363/project_5/project_5.sim/sim_1/behav/xsim/elaborate.log' file for more information.
ERROR: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation.
launch_simulation: Time (s): cpu = 00:00:01 ; elapsed = 00:00:05 . Memory (MB): peak = 781.664 ; gain = 4.230
ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors.
launch_simulation
INFO: [Vivado 12-5682] Launching behavioral simulation in 'H:/363/project_5/project_5.sim/sim_1/behav/xsim'
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [SIM-utils-54] Inspecting design source files for 'testbench' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'H:/363/project_5/project_5.sim/sim_1/behav/xsim'
"xvlog --incr --relax -prj testbench_vlog.prj"
INFO: [VRFC 10-2263] Analyzing Verilog file "H:/363/project_5/project_5.srcs/sources_1/new/ALU.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ALU
INFO: [VRFC 10-2263] Analyzing Verilog file "H:/363/project_5/project_5.srcs/sources_1/new/Controller.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Controller
INFO: [VRFC 10-2263] Analyzing Verilog file "H:/363/project_5/project_5.srcs/sources_1/new/Datapath.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Datapath
INFO: [VRFC 10-2263] Analyzing Verilog file "H:/363/project_5/project_5.srcs/sources_1/new/Processor.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Processor
INFO: [VRFC 10-2263] Analyzing Verilog file "H:/363/project_5/project_5.srcs/sources_1/new/Register.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Register
INFO: [VRFC 10-2263] Analyzing Verilog file "H:/363/project_5/project_5.srcs/sim_1/new/testbench.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module testbench
INFO: [USF-XSim-69] 'compile' step finished in '2' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'H:/363/project_5/project_5.sim/sim_1/behav/xsim'
Vivado Simulator 2017.4
Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved.
Running: C:/Xilinx/Vivado/2017.4/bin/unwrapped/win64.o/xelab.exe -wto b6bb88ed20fa4300ab5d89fe1afc2363 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot testbench_behav xil_defaultlib.testbench xil_defaultlib.glbl -log elaborate.log
Using 2 slave threads.
Starting static elaboration
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling module xil_defaultlib.ALU
Compiling module xil_defaultlib.Datapath
Compiling module xil_defaultlib.Register
Compiling module xil_defaultlib.Controller
Compiling module xil_defaultlib.Processor
Compiling module xil_defaultlib.testbench
Compiling module xil_defaultlib.glbl
Built simulation snapshot testbench_behav
****** Webtalk v2017.4 (64-bit)
**** SW Build 2086221 on Fri Dec 15 20:55:39 MST 2017
**** IP Build 2085800 on Fri Dec 15 22:25:07 MST 2017
** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
source H:/363/project_5/project_5.sim/sim_1/behav/xsim/xsim.dir/testbench_behav/webtalk/xsim_webtalk.tcl -notrace
INFO: [Common 17-186] 'H:/363/project_5/project_5.sim/sim_1/behav/xsim/xsim.dir/testbench_behav/webtalk/usage_statistics_ext_xsim.xml' has been successfully sent to Xilinx on Mon Dec 2 19:37:42 2019. For additional details about this file, please refer to the WebTalk help file at C:/Xilinx/Vivado/2017.4/doc/webtalk_introduction.html.
INFO: [Common 17-206] Exiting Webtalk at Mon Dec 2 19:37:42 2019...
run_program: Time (s): cpu = 00:00:00 ; elapsed = 00:00:09 . Memory (MB): peak = 781.664 ; gain = 0.000
INFO: [USF-XSim-69] 'elaborate' step finished in '9' seconds
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'H:/363/project_5/project_5.sim/sim_1/behav/xsim'
INFO: [USF-XSim-98] *** Running xsim
with args "testbench_behav -key {Behavioral:sim_1:Functional:testbench} -tclbatch {testbench.tcl} -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
Vivado Simulator 2017.4
Time resolution is 1 ps
source testbench.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
# if { [llength [get_objects]] > 0} {
# add_wave /
# set_property needs_save false [current_wave_config]
# } else {
# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
# }
# }
# run 1000ns
xsim: Time (s): cpu = 00:00:03 ; elapsed = 00:00:05 . Memory (MB): peak = 794.691 ; gain = 13.027
INFO: [USF-XSim-96] XSim completed. Design snapshot 'testbench_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
launch_simulation: Time (s): cpu = 00:00:04 ; elapsed = 00:00:18 . Memory (MB): peak = 794.691 ; gain = 13.027
close_sim
INFO: [Simtcl 6-16] Simulation closed
close_sim: Time (s): cpu = 00:00:01 ; elapsed = 00:00:08 . Memory (MB): peak = 800.770 ; gain = 0.000
launch_simulation
INFO: [Vivado 12-5682] Launching behavioral simulation in 'H:/363/project_5/project_5.sim/sim_1/behav/xsim'
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [SIM-utils-54] Inspecting design source files for 'testbench' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'H:/363/project_5/project_5.sim/sim_1/behav/xsim'
"xvlog --incr --relax -prj testbench_vlog.prj"
INFO: [VRFC 10-2263] Analyzing Verilog file "H:/363/project_5/project_5.srcs/sources_1/new/ALU.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ALU
INFO: [VRFC 10-2263] Analyzing Verilog file "H:/363/project_5/project_5.srcs/sources_1/new/Controller.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Controller
INFO: [VRFC 10-2263] Analyzing Verilog file "H:/363/project_5/project_5.srcs/sources_1/new/Datapath.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Datapath
INFO: [VRFC 10-2263] Analyzing Verilog file "H:/363/project_5/project_5.srcs/sources_1/new/Processor.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Processor
INFO: [VRFC 10-2263] Analyzing Verilog file "H:/363/project_5/project_5.srcs/sources_1/new/Register.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Register
INFO: [VRFC 10-2263] Analyzing Verilog file "H:/363/project_5/project_5.srcs/sim_1/new/testbench.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module testbench
INFO: [USF-XSim-69] 'compile' step finished in '2' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'H:/363/project_5/project_5.sim/sim_1/behav/xsim'
Vivado Simulator 2017.4
Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved.
Running: C:/Xilinx/Vivado/2017.4/bin/unwrapped/win64.o/xelab.exe -wto b6bb88ed20fa4300ab5d89fe1afc2363 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot testbench_behav xil_defaultlib.testbench xil_defaultlib.glbl -log elaborate.log
Using 2 slave threads.
Starting static elaboration
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling module xil_defaultlib.ALU
Compiling module xil_defaultlib.Datapath
Compiling module xil_defaultlib.Register
Compiling module xil_defaultlib.Controller
Compiling module xil_defaultlib.Processor
Compiling module xil_defaultlib.testbench
Compiling module xil_defaultlib.glbl
Built simulation snapshot testbench_behav
INFO: [USF-XSim-69] 'elaborate' step finished in '4' seconds
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'H:/363/project_5/project_5.sim/sim_1/behav/xsim'
INFO: [USF-XSim-98] *** Running xsim
with args "testbench_behav -key {Behavioral:sim_1:Functional:testbench} -tclbatch {testbench.tcl} -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
Vivado Simulator 2017.4
Time resolution is 1 ps
source testbench.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
# if { [llength [get_objects]] > 0} {
# add_wave /
# set_property needs_save false [current_wave_config]
# } else {
# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
# }
# }
# run 1000ns
xsim: Time (s): cpu = 00:00:03 ; elapsed = 00:00:05 . Memory (MB): peak = 804.332 ; gain = 3.563
INFO: [USF-XSim-96] XSim completed. Design snapshot 'testbench_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
launch_simulation: Time (s): cpu = 00:00:04 ; elapsed = 00:00:12 . Memory (MB): peak = 804.332 ; gain = 3.563
close_sim
INFO: [Simtcl 6-16] Simulation closed
launch_simulation
INFO: [Vivado 12-5682] Launching behavioral simulation in 'H:/363/project_5/project_5.sim/sim_1/behav/xsim'
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [SIM-utils-54] Inspecting design source files for 'testbench' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'H:/363/project_5/project_5.sim/sim_1/behav/xsim'
"xvlog --incr --relax -prj testbench_vlog.prj"
INFO: [VRFC 10-2263] Analyzing Verilog file "H:/363/project_5/project_5.srcs/sources_1/new/ALU.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ALU
INFO: [VRFC 10-2263] Analyzing Verilog file "H:/363/project_5/project_5.srcs/sources_1/new/Controller.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Controller
INFO: [VRFC 10-2263] Analyzing Verilog file "H:/363/project_5/project_5.srcs/sources_1/new/Datapath.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Datapath
INFO: [VRFC 10-2263] Analyzing Verilog file "H:/363/project_5/project_5.srcs/sources_1/new/Processor.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Processor
INFO: [VRFC 10-2263] Analyzing Verilog file "H:/363/project_5/project_5.srcs/sources_1/new/Register.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Register
INFO: [VRFC 10-2263] Analyzing Verilog file "H:/363/project_5/project_5.srcs/sim_1/new/testbench.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module testbench
INFO: [USF-XSim-69] 'compile' step finished in '2' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'H:/363/project_5/project_5.sim/sim_1/behav/xsim'
Vivado Simulator 2017.4
Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved.
Running: C:/Xilinx/Vivado/2017.4/bin/unwrapped/win64.o/xelab.exe -wto b6bb88ed20fa4300ab5d89fe1afc2363 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot testbench_behav xil_defaultlib.testbench xil_defaultlib.glbl -log elaborate.log
Using 2 slave threads.
Starting static elaboration
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling module xil_defaultlib.ALU
Compiling module xil_defaultlib.Datapath
Compiling module xil_defaultlib.Register
Compiling module xil_defaultlib.Controller
Compiling module xil_defaultlib.Processor
Compiling module xil_defaultlib.testbench
Compiling module xil_defaultlib.glbl
Built simulation snapshot testbench_behav
INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'H:/363/project_5/project_5.sim/sim_1/behav/xsim'
INFO: [USF-XSim-98] *** Running xsim
with args "testbench_behav -key {Behavioral:sim_1:Functional:testbench} -tclbatch {testbench.tcl} -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
Vivado Simulator 2017.4
Time resolution is 1 ps
source testbench.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
# if { [llength [get_objects]] > 0} {
# add_wave /
# set_property needs_save false [current_wave_config]
# } else {
# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
# }
# }
# run 1000ns
INFO: [USF-XSim-96] XSim completed. Design snapshot 'testbench_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
launch_simulation: Time (s): cpu = 00:00:04 ; elapsed = 00:00:11 . Memory (MB): peak = 810.223 ; gain = 0.000
close_sim
INFO: [Simtcl 6-16] Simulation closed
launch_simulation
INFO: [Vivado 12-5682] Launching behavioral simulation in 'H:/363/project_5/project_5.sim/sim_1/behav/xsim'
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [SIM-utils-54] Inspecting design source files for 'testbench' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'H:/363/project_5/project_5.sim/sim_1/behav/xsim'
"xvlog --incr --relax -prj testbench_vlog.prj"
INFO: [VRFC 10-2263] Analyzing Verilog file "H:/363/project_5/project_5.srcs/sources_1/new/ALU.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ALU
INFO: [VRFC 10-2263] Analyzing Verilog file "H:/363/project_5/project_5.srcs/sources_1/new/Controller.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Controller
INFO: [VRFC 10-2263] Analyzing Verilog file "H:/363/project_5/project_5.srcs/sources_1/new/Datapath.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Datapath
INFO: [VRFC 10-2263] Analyzing Verilog file "H:/363/project_5/project_5.srcs/sources_1/new/Processor.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Processor
INFO: [VRFC 10-2263] Analyzing Verilog file "H:/363/project_5/project_5.srcs/sources_1/new/Register.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Register
INFO: [VRFC 10-2263] Analyzing Verilog file "H:/363/project_5/project_5.srcs/sim_1/new/testbench.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module testbench
INFO: [USF-XSim-69] 'compile' step finished in '1' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'H:/363/project_5/project_5.sim/sim_1/behav/xsim'
Vivado Simulator 2017.4
Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved.
Running: C:/Xilinx/Vivado/2017.4/bin/unwrapped/win64.o/xelab.exe -wto b6bb88ed20fa4300ab5d89fe1afc2363 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot testbench_behav xil_defaultlib.testbench xil_defaultlib.glbl -log elaborate.log
Using 2 slave threads.
Starting static elaboration
WARNING: [VRFC 10-597] element index 1087 into One_D_Array_DM is out of bounds [H:/363/project_5/project_5.srcs/sources_1/new/Register.v:35]
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling module xil_defaultlib.ALU
Compiling module xil_defaultlib.Datapath
Compiling module xil_defaultlib.Register
Compiling module xil_defaultlib.Controller
Compiling module xil_defaultlib.Processor
Compiling module xil_defaultlib.testbench
Compiling module xil_defaultlib.glbl
Built simulation snapshot testbench_behav
INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'H:/363/project_5/project_5.sim/sim_1/behav/xsim'
INFO: [USF-XSim-98] *** Running xsim
with args "testbench_behav -key {Behavioral:sim_1:Functional:testbench} -tclbatch {testbench.tcl} -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
Vivado Simulator 2017.4
Time resolution is 1 ps
source testbench.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
# if { [llength [get_objects]] > 0} {
# add_wave /
# set_property needs_save false [current_wave_config]
# } else {
# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
# }
# }
# run 1000ns
INFO: [USF-XSim-96] XSim completed. Design snapshot 'testbench_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
launch_simulation: Time (s): cpu = 00:00:03 ; elapsed = 00:00:10 . Memory (MB): peak = 810.223 ; gain = 0.000
close_sim
INFO: [Simtcl 6-16] Simulation closed
launch_simulation
INFO: [Vivado 12-5682] Launching behavioral simulation in 'H:/363/project_5/project_5.sim/sim_1/behav/xsim'
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [SIM-utils-54] Inspecting design source files for 'testbench' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'H:/363/project_5/project_5.sim/sim_1/behav/xsim'
"xvlog --incr --relax -prj testbench_vlog.prj"
INFO: [VRFC 10-2263] Analyzing Verilog file "H:/363/project_5/project_5.srcs/sources_1/new/ALU.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ALU
INFO: [VRFC 10-2263] Analyzing Verilog file "H:/363/project_5/project_5.srcs/sources_1/new/Controller.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Controller
INFO: [VRFC 10-2263] Analyzing Verilog file "H:/363/project_5/project_5.srcs/sources_1/new/Datapath.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Datapath
INFO: [VRFC 10-2263] Analyzing Verilog file "H:/363/project_5/project_5.srcs/sources_1/new/Processor.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Processor
INFO: [VRFC 10-2263] Analyzing Verilog file "H:/363/project_5/project_5.srcs/sources_1/new/Register.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Register
INFO: [VRFC 10-2263] Analyzing Verilog file "H:/363/project_5/project_5.srcs/sim_1/new/testbench.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module testbench
INFO: [USF-XSim-69] 'compile' step finished in '1' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'H:/363/project_5/project_5.sim/sim_1/behav/xsim'
Vivado Simulator 2017.4
Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved.
Running: C:/Xilinx/Vivado/2017.4/bin/unwrapped/win64.o/xelab.exe -wto b6bb88ed20fa4300ab5d89fe1afc2363 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot testbench_behav xil_defaultlib.testbench xil_defaultlib.glbl -log elaborate.log
Using 2 slave threads.
Starting static elaboration
WARNING: [VRFC 10-597] element index 1087 into One_D_Array_DM is out of bounds [H:/363/project_5/project_5.srcs/sources_1/new/Register.v:35]
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling module xil_defaultlib.ALU
Compiling module xil_defaultlib.Datapath
Compiling module xil_defaultlib.Register
Compiling module xil_defaultlib.Controller
Compiling module xil_defaultlib.Processor
Compiling module xil_defaultlib.testbench
Compiling module xil_defaultlib.glbl
Built simulation snapshot testbench_behav
INFO: [USF-XSim-69] 'elaborate' step finished in '4' seconds
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'H:/363/project_5/project_5.sim/sim_1/behav/xsim'
INFO: [USF-XSim-98] *** Running xsim
with args "testbench_behav -key {Behavioral:sim_1:Functional:testbench} -tclbatch {testbench.tcl} -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
Vivado Simulator 2017.4
Time resolution is 1 ps
source testbench.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
# if { [llength [get_objects]] > 0} {
# add_wave /
# set_property needs_save false [current_wave_config]
# } else {
# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
# }
# }
# run 1000ns
INFO: [USF-XSim-96] XSim completed. Design snapshot 'testbench_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
launch_simulation: Time (s): cpu = 00:00:03 ; elapsed = 00:00:11 . Memory (MB): peak = 810.223 ; gain = 0.000
close_sim
INFO: [Simtcl 6-16] Simulation closed
launch_simulation
INFO: [Vivado 12-5682] Launching behavioral simulation in 'H:/363/project_5/project_5.sim/sim_1/behav/xsim'
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [SIM-utils-54] Inspecting design source files for 'testbench' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'H:/363/project_5/project_5.sim/sim_1/behav/xsim'
"xvlog --incr --relax -prj testbench_vlog.prj"
INFO: [VRFC 10-2263] Analyzing Verilog file "H:/363/project_5/project_5.srcs/sources_1/new/ALU.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ALU
INFO: [VRFC 10-2263] Analyzing Verilog file "H:/363/project_5/project_5.srcs/sources_1/new/Controller.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Controller
INFO: [VRFC 10-2263] Analyzing Verilog file "H:/363/project_5/project_5.srcs/sources_1/new/Datapath.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Datapath
INFO: [VRFC 10-2263] Analyzing Verilog file "H:/363/project_5/project_5.srcs/sources_1/new/Processor.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Processor
INFO: [VRFC 10-2263] Analyzing Verilog file "H:/363/project_5/project_5.srcs/sources_1/new/Register.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Register
INFO: [VRFC 10-2263] Analyzing Verilog file "H:/363/project_5/project_5.srcs/sim_1/new/testbench.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module testbench
INFO: [USF-XSim-69] 'compile' step finished in '2' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'H:/363/project_5/project_5.sim/sim_1/behav/xsim'
Vivado Simulator 2017.4
Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved.
Running: C:/Xilinx/Vivado/2017.4/bin/unwrapped/win64.o/xelab.exe -wto b6bb88ed20fa4300ab5d89fe1afc2363 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot testbench_behav xil_defaultlib.testbench xil_defaultlib.glbl -log elaborate.log
Using 2 slave threads.
Starting static elaboration
WARNING: [VRFC 10-597] element index 1087 into One_D_Array_DM is out of bounds [H:/363/project_5/project_5.srcs/sources_1/new/Register.v:35]
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling module xil_defaultlib.ALU
Compiling module xil_defaultlib.Datapath
Compiling module xil_defaultlib.Register
Compiling module xil_defaultlib.Controller
Compiling module xil_defaultlib.Processor
Compiling module xil_defaultlib.testbench
Compiling module xil_defaultlib.glbl
Built simulation snapshot testbench_behav
INFO: [USF-XSim-69] 'elaborate' step finished in '4' seconds
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'H:/363/project_5/project_5.sim/sim_1/behav/xsim'
INFO: [USF-XSim-98] *** Running xsim
with args "testbench_behav -key {Behavioral:sim_1:Functional:testbench} -tclbatch {testbench.tcl} -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
Vivado Simulator 2017.4
Time resolution is 1 ps
source testbench.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
# if { [llength [get_objects]] > 0} {
# add_wave /
# set_property needs_save false [current_wave_config]
# } else {
# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
# }
# }
# run 1000ns
INFO: [USF-XSim-96] XSim completed. Design snapshot 'testbench_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
launch_simulation: Time (s): cpu = 00:00:03 ; elapsed = 00:00:11 . Memory (MB): peak = 810.969 ; gain = 0.746