From f2870352032f217cc1ea9bcf426327d915c89cb8 Mon Sep 17 00:00:00 2001
From: Matteo Lupi <matteo.lupi@cern.ch>
Date: Tue, 6 Feb 2024 15:01:34 +0100
Subject: [PATCH 1/2] ML fixed #2076

---
 verilog/parser/verilog.y | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/verilog/parser/verilog.y b/verilog/parser/verilog.y
index a0ae63d82..5a0741d7a 100644
--- a/verilog/parser/verilog.y
+++ b/verilog/parser/verilog.y
@@ -773,6 +773,8 @@ KeywordIdentifier
     { $$ = std::move($1); }
   | TK_discrete
     { $$ = std::move($1); }
+  | TK_analog
+    { $$ = std::move($1); }
   /* TK_sample is in SystemVerilog coverage_event */
   | TK_sample
     { $$ = std::move($1); }

From 72ff5ce9127d41092b143a35f943acfc12d2626e Mon Sep 17 00:00:00 2001
From: Matteo Lupi <matteo.lupi@cern.ch>
Date: Tue, 6 Feb 2024 15:17:29 +0100
Subject: [PATCH 2/2] ML added testcase for #2076

---
 verilog/parser/verilog_parser_unittest.cc | 1 +
 1 file changed, 1 insertion(+)

diff --git a/verilog/parser/verilog_parser_unittest.cc b/verilog/parser/verilog_parser_unittest.cc
index 551e05b82..5e8023a8d 100644
--- a/verilog/parser/verilog_parser_unittest.cc
+++ b/verilog/parser/verilog_parser_unittest.cc
@@ -1773,6 +1773,7 @@ static constexpr ParserTestCaseArray kModuleTests = {
     // keyword tests
     "module keyword_identifiers;\n"
     "reg branch;  // branch is a Verilog-AMS keyword\n"
+    "reg analog;  // analog is a Verilog-AMS keyword\n"
     "input from;  // from is a Verilog-AMS keyword\n"
     "wire access;  // access is a Verilog-AMS keyword\n"
     "wire exclude;  // exclude is a Verilog-AMS keyword\n"