GA32.htm

<h1 align="center">GA32 32-computer Chip</h1><h3>

The GA32 needs describing since it is the first of GreenArray's computers to be fabricated. The version being tested in June has only 31 computers. Node 00 was replaced with test circuits that will improve the accuracy of future simulations.

<p>The chip measures 2.5 mm in a 180 nm process. That size was chosen because it minimizes the cost of prototypes. 88 pads border the chip and 32 computers fit inside.

<p>Low power results from our computer (one node of an array) being asynchronous (unclocked). Spec sheets will be forthcoming. Meanwhile this list of features should prove impressive. Bill composed a handy <a href="GA32.pdf">poster</a> with much info.

<p>GA32 has 88 pads. It's package has 88 pins. Pins are numbered counter-clockwise from upper left<ul>
<li>18 pins for RAM data: 1 2 3 8 9 10 11 12 13 16 21 22 23 24 25 30 31 32
<li>18 pins for RAM address: 37 38 39 42 43 44 45 46 53 54 55 56 57 58 65 66 67 68
<li>11 pins for Vdd (1.8 V): 4 17 19 28 40 47 49 62 64 74 82
<li>11 pins NC: 5 18 20 29 41 48 50 61 63 75 83
<br>These were Vss (0 V) but will be reassigned on future chips. Vss is now the ground/heat-sink on the bottom of the package.
<li>Reset: 88
<li>23 digital I/O: 6 7 14 15 26 27 33 34 35 36 51 52 59 60 71 78 79 80 81 84 85 86 87
<li>3 D/A outputs: 70 72 77
<li>3 A/D inputs: 69 73 76</ul>

<p>The 12 interior computers have the same ROM. They are used as wires to pass messages and as compute engines. The 20 edge computers are assigned nominal functions based upon their ROM and I/O pads. But they may be used differently:<ul>
<li>Node 00, missing in GA31
<li>01: digital 26 27; SerDes
<li>02
<li>03: RAM data, pins reassigned in GA31
<li>04: RAM control 33 34 35 36
<li>05: RAM address
<li>06
<li>07
<li>10: digital 14 15; Sync boot
<li>17: digital 51 52; Sync boot
<li>20: digital 6 7
<li>27: digital 59 60
<li>30
<li>31: digital 86 87; SerDes
<li>32: digital 80 81 84 85; SPI boot
<li>33: digital 78 79; Async (RS232) boot
<li>34: analog 76 77
<li>35: analog 73 72
<li>36: digital 71; analog trigger
<li>37: analog 69 70
</ul>

<h2>Features</h2><ul>
<li>3 pF I/O pad capacitance (inclusive of ESD) 
<li>1.8V Vdd +- 10%
<li>3 mA per node that's running; 100 nA if sleeping (leakage)
<li>Powers-up in reset<ul>
   <li>Draws no power
   <li>High on pin 88 takes chip out of reset</ul>
<li>Implements the <a href="inst.htm">colorForth instruction set</a>

<p><li>Serial communication<ul>
<li>Asynchronous (RS232)
<li>Synchronous
<li>Serializer/Deserializer
</ul>

<p><li>D/A out<ul>
<li>9-bits of scaled current into a 75Ohm load
<li>Range from 0 to 1.5 V
<li>Moderate non-linearity correctable with software or op-amp
<li>Drivers designed to minimize glitches
<li>About 30mA max current (TBD)
</ul>

<p><li>A/D in<ul>
<li>VCO with 18-bit counter
<li>Averages value over sample interval (low-pass filter)
<li>6-bit resolution at 10 MHz, 17-bit at 10 KHz
<li>Range from .5 to 1.3 V
<li>Moderate non-linearity correctable with software
<li>Triggerable from neighboring node
<li>Internal calibration at Vdd and Vss
<li>Reset to Vdd input allows no-connect of pin</ul>

<p><li>Digital I/O<ul>
<li>4 modes for each pad:<ul>
   <li>Output high (1.8 V)
   <li>Output low
   <li>Input
   <li>Input with weak (50KOhm) pull-down (default at reset)</ul>
<li>50Ohm output drivers; that's 18 mA max
<li>Pad connected to bit 17 of IOCS convenient for input (can be tested as sign bit)
<li>Bit 17 high or low can wake up node
<li>Pull-down allows no-connect of pin</ul> 

<p><li>Wake-up<ul>
<li>A node can sleep (using no power) by reading the wake-up port. It can wake up when input goes high or low (level detect)
<li>Such wake-up synchronizes the node to the input edge, with a  phase jitter of picoseconds. The input node can synchronize other nodes via the internal communication ports
</ul>

</ul>