-
Notifications
You must be signed in to change notification settings - Fork 8
/
Copy pathi8086.cxx
1976 lines (1819 loc) · 66.1 KB
/
i8086.cxx
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
// 8086 emulator
// Written by David Lee in late 2022.
// Useful: http://bitsavers.org/components/intel/8086/9800722-03_The_8086_Family_Users_Manual_Oct79.pdf
// https://www.eeeguide.com/8086-instruction-format/
// https://www.felixcloutier.com/x86
// https://onlinedisassembler.com/odaweb/
// https://www2.math.uni-wuppertal.de/~fpf/Uebungen/GdR-SS02/opcode_i.html
// https://www.pcjs.org/documents/manuals/intel/8086/
// https://www.righto.com/2023/02/8086-modrm-addressing.html
// https://www.righto.com/2023/07/undocumented-8086-instructions.html
// Cycle counts are approximate -- within 25% of actual values. It doesn't account for misalignment,
// ignores some immediate vs. reg cases where the difference is 1 cycle, gets div/mult approximately,
// and doesn't handle many other cases. Also, various 8086 tech documents don't have consistent counts.
// I tested cycle counts against physical 80186 and 8088 machines. This is somewhere in between.
// Not implemented: "For the 8086, add four clocks for each 16-bit word transfer with an odd address. For the 8088, add four clocks for each 16-bit word transfer."
// String operations don't allow for interrupts until completion, unlike real hardware.
#include <djl_os.hxx>
#include <stdio.h>
#include <memory.h>
#include <assert.h>
#include <djltrace.hxx>
#include <djl8086d.hxx>
using namespace std;
#include "i8086.hxx"
uint8_t memory[ 0x10fff0 ]; // though only 0..fffff is addressable on the 8086
i8086 cpu;
static CDisassemble8086 g_Disassembler;
static uint32_t g_State = 0;
const uint32_t stateTraceInstructions = 1;
const uint32_t stateEndEmulation = 2;
const uint32_t stateExitEmulateEarly = 4;
const uint32_t stateTrapSet = 8;
void i8086::trace_instructions( bool t ) { if ( t ) g_State |= stateTraceInstructions; else g_State &= ~stateTraceInstructions; }
void i8086::end_emulation() { g_State |= stateEndEmulation; }
void i8086::exit_emulate_early() { g_State |= stateExitEmulateEarly; }
static void trap_set() { g_State |= stateTrapSet; }
bool i8086::external_interrupt( uint8_t interrupt_num )
{
if ( fInterrupt && !fTrap )
{
op_interrupt( interrupt_num, 0 ); // 0 since it's not in the instruction stream
return true;
}
return false;
} //external_interrupt
void i8086::unhandled_instruction()
{
reset_disassembler();
trace_state();
char ac[ 100 ];
snprintf( ac, sizeof( ac ), "unhandled 8086 instruction %02x %02x %02x, _mod %02x, _reg %02x, _rm %02x, isword %d, toreg %d, seg %02x\n",
_b0, _b1, _pcode[ 2 ], _mod, _reg, _rm, isword(), toreg(), prefix_segment_override );
i8086_hard_exit( ac );
} //unhandled_instruction
void i8086::reset_disassembler()
{
g_Disassembler.ClearLastIP();
} //reset_disassembler.ClearLasetIP();
void i8086::trace_state()
{
const uint8_t * pcode = flat_address8( cs, ip );
const char * pdisassemble = g_Disassembler.Disassemble( pcode );
tracer.TraceQuiet( "ip %4x, opc %02x %02x %02x %02x %02x, ax %04x, bx %04x, cx %04x, dx %04x, di %04x, "
"si %04x, ds %04x, es %04x, cs %04x, ss %04x, bp %04x, sp %04x, %s, %s ; %u\n",
ip, pcode[0], pcode[1], pcode[2], pcode[3], pcode[4],
ax, bx, cx, dx, di, si, ds, es, cs, ss, bp, sp,
render_flags(), pdisassemble, g_Disassembler.BytesConsumed() );
} //trace_state
// base cycle count per opcode; will be higher for multi-byte instructions, memory references,
// ea calculations, jumps taken, loops taken, rotate cl-times, and reps
static const uint8_t i8086_cycles[ 256 ] =
{
/*00*/ 3, 3, 3, 3, 4, 4, 14, 12, 3, 3, 3, 3, 4, 4, 14, 14,
/*10*/ 3, 3, 3, 3, 4, 4, 14, 12, 3, 3, 3, 3, 4, 4, 14, 12,
/*20*/ 3, 3, 3, 3, 4, 4, 2, 4, 3, 3, 3, 3, 4, 4, 2, 4,
/*30*/ 3, 3, 3, 3, 4, 4, 2, 4, 3, 3, 3, 3, 4, 4, 2, 4,
/*40*/ 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
/*50*/ 15, 15, 15, 15, 15, 15, 15, 15, 12, 12, 12, 12, 12, 12, 12, 12,
/*60*/ 4, 4, 4, 4, 4, 4, 4, 4, 4, 1, 4, 4, 4, 4, 4, 4,
/*70*/ 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4,
/*80*/ 4, 4, 4, 4, 5, 5, 4, 4, 2, 2, 2, 2, 2, 4, 2, 12, // lea as 4, not 2; docs can't be right
/*90*/ 4, 4, 4, 4, 4, 4, 4, 4, 2, 5, 36, 4, 14, 12, 4, 4,
/*a0*/ 14, 14, 14, 14, 18, 26, 30, 30, 5, 5, 11, 15, 16, 16, 19, 19,
/*b0*/ 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4,
/*c0*/ 24, 20, 24, 20, 24, 24, 14, 14, 33, 34, 33, 34, 72, 71, 4, 44,
/*d0*/ 2, 2, 8, 8, 83, 60, 2, 11, 1, 1, 1, 1, 1, 1, 1, 1,
/*e0*/ 6, 5, 5, 6, 14, 14, 14, 14, 23, 15, 15, 15, 12, 12, 12, 12,
/*f0*/ 1, 0, 9, 9, 2, 3, 5, 5, 2, 2, 2, 2, 2, 2, 3, 2,
};
void i8086::update_index8( uint16_t & index_register ) // si or di
{
if ( fDirection )
index_register--;
else
index_register++;
} //update_index16
void i8086::update_index16( uint16_t & index_register ) // si or di
{
if ( fDirection )
index_register -= 2;
else
index_register += 2;
} //update_index16
void i8086::update_rep_sidi8()
{
update_index8( si );
update_index8( di );
} //update_rep_sidi8
void i8086::update_rep_sidi16()
{
update_index16( si );
update_index16( di );
} //update_rep_sidi16
force_inlined uint8_t i8086::op_sub8( uint8_t lhs, uint8_t rhs, bool borrow )
{
uint8_t com_rhs = ~rhs; // com == ones-compliment
uint8_t borrow_int = borrow ? 0 : 1;
uint16_t res16 = (uint16_t) lhs + (uint16_t) com_rhs + (uint16_t) borrow_int;
uint8_t res8 = res16 & 0xff;
fCarry = ( 0 == ( res16 & 0x100 ) );
set_PSZ8( res8 );
fOverflow = ( ! ( ( lhs ^ com_rhs ) & 0x80 ) ) && ( ( lhs ^ res8 ) & 0x80 );
fAuxCarry = ( 0 != ( ( ( lhs & 0xf ) - ( rhs & 0xf ) - ( borrow ? 1 : 0 ) ) & ~0xf ) );
return res8;
} //op_sub8
force_inlined uint16_t i8086::op_sub16( uint16_t lhs, uint16_t rhs, bool borrow )
{
uint16_t com_rhs = ~rhs; // com == ones-compliment
uint16_t borrow_int = borrow ? 0 : 1;
uint32_t res32 = (uint32_t) lhs + (uint32_t) com_rhs + (uint32_t) borrow_int;
uint16_t res16 = res32 & 0xffff;
fCarry = ( 0 == ( res32 & 0x10000 ) );
set_PSZ16( res16 );
fOverflow = ( ! ( ( lhs ^ com_rhs ) & 0x8000 ) ) && ( ( lhs ^ res16 ) & 0x8000 );
fAuxCarry = ( 0 != ( ( ( lhs & 0xf ) - ( rhs & 0xf ) - ( borrow ? 1 : 0 ) ) & ~0xf ) );
return res16;
} //op_sub16
force_inlined uint8_t i8086::op_add8( uint8_t lhs, uint8_t rhs, bool carry )
{
uint16_t carry_int = carry ? 1 : 0;
uint16_t res16 = (uint16_t) lhs + (uint16_t) rhs + carry_int;
uint8_t res8 = res16 & 0xff;
fCarry = ( 0 != ( res16 & 0x100 ) );
set_PSZ8( res8 );
fOverflow = ( ! ( ( lhs ^ rhs ) & 0x80 ) ) && ( ( lhs ^ res8 ) & 0x80 );
fAuxCarry = ( 0 != ( ( ( 0xf & lhs ) + ( 0xf & rhs ) + carry_int ) & 0x10 ) );
return res8;
} //op_add8
force_inlined uint16_t i8086::op_add16( uint16_t lhs, uint16_t rhs, bool carry )
{
uint32_t carry_int = carry ? 1 : 0;
uint32_t res32 = (uint32_t) lhs + (uint32_t) rhs + carry_int;
uint16_t res16 = res32 & 0xffff;
fCarry = ( 0 != ( res32 & 0x10000 ) );
set_PSZ16( res16 );
fOverflow = ( ! ( ( lhs ^ rhs ) & 0x8000 ) ) && ( ( lhs ^ res16 ) & 0x8000 );
fAuxCarry = ( 0 != ( ( ( 0xf & lhs ) + ( 0xf & rhs ) + carry_int ) & 0x10 ) );
return res16;
} //op_add16
uint8_t i8086::op_and8( uint8_t lhs, uint8_t rhs )
{
lhs &= rhs;
set_PSZ8( lhs );
reset_carry_overflow();
return lhs;
} //op_and8
uint16_t i8086::op_and16( uint16_t lhs, uint16_t rhs )
{
lhs &= rhs;
set_PSZ16( lhs );
reset_carry_overflow();
return lhs;
} //op_and16
uint8_t i8086::op_or8( uint8_t lhs, uint8_t rhs )
{
lhs |= rhs;
set_PSZ8( lhs );
reset_carry_overflow();
return lhs;
} //op_or8
uint16_t i8086::op_or16( uint16_t lhs, uint16_t rhs )
{
lhs |= rhs;
set_PSZ16( lhs );
reset_carry_overflow();
return lhs;
} //op_or16
uint8_t i8086::op_xor8( uint8_t lhs, uint8_t rhs )
{
lhs ^= rhs;
set_PSZ8( lhs );
reset_carry_overflow();
return lhs;
} //op_xor8
uint16_t i8086::op_xor16( uint16_t lhs, uint16_t rhs )
{
lhs ^= rhs;
set_PSZ16( lhs );
reset_carry_overflow();
return lhs;
} //op_xor16
force_inlined void i8086::do_math8( uint8_t math, uint8_t * psrc, uint8_t rhs )
{
assert( math <= 7 );
switch ( math )
{
case 0: *psrc = op_add8( *psrc, rhs ); break;
case 1: *psrc = op_or8( *psrc, rhs ); break;
case 2: *psrc = op_add8( *psrc, rhs, fCarry ); break;
case 3: *psrc = op_sub8( *psrc, rhs, fCarry ); break;
case 4: *psrc = op_and8( *psrc, rhs ); break;
case 5: *psrc = op_sub8( *psrc, rhs ); break;
case 6: *psrc = op_xor8( *psrc, rhs ); break;
default: op_sub8( *psrc, rhs ); break; // 7 is cmp
}
} //do_math8
force_inlined void i8086::do_math16( uint8_t math, uint16_t * psrc, uint16_t rhs )
{
assert( math <= 7 );
uint16_t val = read_word( psrc );
uint16_t result;
switch( math )
{
case 0: result = op_add16( val, rhs ); break;
case 1: result = op_or16( val, rhs ); break;
case 2: result = op_add16( val, rhs, fCarry ); break;
case 3: result = op_sub16( val, rhs, fCarry ); break;
case 4: result = op_and16( val, rhs ); break;
case 5: result = op_sub16( val, rhs ); break;
case 6: result = op_xor16( val, rhs ); break;
default: op_sub16( val, rhs ); return; // 7 is cmp
}
write_word( psrc, result );
} //do_math16
uint8_t i8086::op_inc8( uint8_t val )
{
fOverflow = ( 0x7f == val );
val++;
fAuxCarry = ( 0 == ( val & 0xf ) );
set_PSZ8( val );
return val;
} //op_inc8
uint16_t i8086::op_inc16( uint16_t val )
{
fOverflow = ( 0x7fff == val );
val++;
fAuxCarry = ( 0 == ( val & 0xf ) );
set_PSZ16( val );
return val;
} //op_inc16
uint8_t i8086::op_dec8( uint8_t val )
{
fOverflow = ( 0x80 == val );
val--;
fAuxCarry = ( 0xf == ( val & 0xf ) );
set_PSZ8( val );
return val;
} //op_dec8
uint16_t i8086::op_dec16( uint16_t val )
{
fOverflow = ( 0x8000 == val );
val--;
fAuxCarry = ( 0xf == ( val & 0xf ) );
set_PSZ16( val );
return val;
} //op_dec16
void i8086::op_rol8( uint8_t * pval, uint8_t shift )
{
if ( 0 == shift )
return;
uint8_t original = *pval;
uint8_t val = original;
for ( uint8_t sh = 0; sh < shift; sh++ )
{
bool highBit = ( 0 != ( 0x80 & val ) );
val <<= 1;
if ( highBit )
val |= 1;
fCarry = highBit;
}
fOverflow = ( ( val & 0x80 ) != ( original & 0x80 ) ); // only defined when shift is 1
*pval = val;
} //op_rol8
void i8086::op_rol16( uint16_t * pval, uint8_t shift )
{
if ( 0 == shift )
{
fOverflow = false;
return;
}
uint16_t original = *pval;
uint16_t val = original;
for ( uint8_t sh = 0; sh < shift; sh++ )
{
bool highBit = ( 0 != ( 0x8000 & val ) );
val <<= 1;
if ( highBit )
val |= 1;
fCarry = highBit;
}
fOverflow = ( ( val & 0x8000 ) != ( original & 0x8000 ) ); // only defined when shift is 1
*pval = val;
} //op_rol16
void i8086::op_ror8( uint8_t * pval, uint8_t shift )
{
if ( 0 == shift )
return;
uint8_t val = *pval;
for ( uint8_t sh = 0; sh < shift; sh++ )
{
bool lowBit = ( 0 != ( 1 & val ) );
val >>= 1;
if ( lowBit )
val |= 0x80;
fCarry = lowBit;
}
fOverflow = ( ( 0 != ( val & 0x80 ) ) ^ ( 0 != ( val & 0x40 ) ) ); // only defined when shift is 1
*pval = val;
} //op_ror8
void i8086::op_ror16( uint16_t * pval, uint8_t shift )
{
if ( 0 == shift )
return;
uint16_t val = *pval;
for ( uint8_t sh = 0; sh < shift; sh++ )
{
bool lowBit = ( 0 != ( 1 & val ) );
val >>= 1;
if ( lowBit )
val |= 0x8000;
fCarry = lowBit;
}
fOverflow = ( ( 0 != ( val & 0x8000 ) ) ^ ( 0 != ( val & 0x4000 ) ) ); // only defined when shift is 1
*pval = val;
} //op_ror16
not_inlined void i8086::op_rcl8( uint8_t * pval, uint8_t shift )
{
if ( 0 == shift )
return;
uint8_t val = *pval;
for ( uint8_t sh = 0; sh < shift; sh++ )
{
bool newCarry = ( 0 != ( 0x80 & val ) );
val <<= 1;
if ( fCarry )
val |= 1;
fCarry = newCarry;
}
fOverflow = ( ( 0 != ( val & 0x80 ) ) ^ fCarry ); // only defined when shift is 1
*pval = val;
} //op_rcl8
not_inlined void i8086::op_rcl16( uint16_t * pval, uint8_t shift )
{
if ( 0 == shift )
return;
uint16_t val = *pval;
for ( uint8_t sh = 0; sh < shift; sh++ )
{
bool newCarry = ( 0 != ( 0x8000 & val ) );
val <<= 1;
if ( fCarry )
val |= 1;
fCarry = newCarry;
}
fOverflow = ( ( 0 != ( val & 0x8000 ) ) ^ fCarry ); // only defined when shift is 1
*pval = val;
} //op_rcl16
not_inlined void i8086::op_rcr8( uint8_t * pval, uint8_t shift )
{
if ( 0 == shift )
return;
uint8_t val = *pval;
for ( uint8_t sh = 0; sh < shift; sh++ )
{
bool newCarry = ( 0 != ( 1 & val ) );
val >>= 1;
if ( fCarry )
val |= 0x80;
fCarry = newCarry;
}
fOverflow = ( ( 0 != ( val & 0x80 ) ) ^ ( 0 != ( val & 0x40 ) ) ); // only defined when shift is 1
*pval = val;
} //op_rcr8
not_inlined void i8086::op_rcr16( uint16_t * pval, uint8_t shift )
{
if ( 0 == shift )
return;
uint16_t val = *pval;
for ( uint8_t sh = 0; sh < shift; sh++ )
{
bool newCarry = ( 0 != ( 1 & val ) );
val >>= 1;
if ( fCarry )
val |= 0x8000;
fCarry = newCarry;
}
fOverflow = ( ( 0 != ( val & 0x8000 ) ) ^ ( 0 != ( val & 0x4000 ) ) ); // only defined when shift is 1
*pval = val;
} //op_rcr16
void i8086::op_sal8( uint8_t * pval, uint8_t shift )
{
if ( 0 == shift )
return;
if ( shift > 8 )
{
*pval = 0;
fCarry = false;
}
else
{
uint8_t orig = *pval;
*pval <<= ( shift - 1 );
fCarry = ( 0 != ( *pval & 0x80 ) );
*pval <<= 1;
fOverflow = ! ( ( orig & 0x80 ) == ( *pval & 0x80 ) ); // only defined when shift is 1
}
set_PSZ8( *pval );
} //op_sal8
void i8086::op_sal16( uint16_t * pval, uint8_t shift )
{
if ( 0 == shift )
return;
if ( shift > 16 )
*pval = 0;
else
{
uint16_t orig = *pval;
*pval <<= ( shift - 1 );
fCarry = ( 0 != ( *pval & 0x8000 ) );
*pval <<= 1;
fOverflow = ! ( ( orig & 0x8000 ) == ( *pval & 0x8000 ) ); // only defined when shift is 1
}
set_PSZ16( *pval );
} //op_sal16
void i8086::op_shr8( uint8_t * pval, uint8_t shift )
{
if ( 0 == shift )
return;
if ( shift > 8 )
*pval = 0;
else
{
fOverflow = ( 0 != ( *pval & 0x80 ) ); // only defined when shift is 1
*pval >>= ( shift - 1 );
fCarry = ( 0 != ( *pval & 1 ) );
*pval >>= 1;
}
set_PSZ8( *pval );
} //op_shr8
void i8086::op_shr16( uint16_t * pval, uint8_t shift )
{
if ( 0 == shift )
return;
if ( shift > 16 )
*pval = 0;
else
{
fOverflow = ( 0 != ( *pval & 0x8000 ) ); // only defined when shift is 1
*pval >>= ( shift - 1 );
fCarry = ( 0 != ( *pval & 1 ) );
*pval >>= 1;
}
set_PSZ16( *pval );
} //op_shr16
not_inlined void i8086::op_sar8( uint8_t * pval, uint8_t shift )
{
if ( 0 == shift )
return;
uint8_t val = *pval;
bool highBit = ( 0 != ( val & 0x80 ) );
for ( uint8_t sh = 0; sh < shift; sh++ )
{
fCarry = ( 0 != ( 1 & val ) );
val >>= 1;
if ( highBit )
val |= 0x80;
}
fOverflow = false; // only defined when shift is 1
set_PSZ8( val );
*pval = val;
} //op_sar8
void i8086::op_sar16( uint16_t * pval, uint8_t shift )
{
if ( 0 == shift )
return;
uint16_t val = *pval;
bool highBit = ( 0 != ( val & 0x8000 ) );
for ( uint8_t sh = 0; sh < shift; sh++ )
{
fCarry = ( 0 != ( 1 & val ) );
val >>= 1;
if ( highBit )
val |= 0x8000;
}
fOverflow = false; // only defined when shift is 1
set_PSZ16( val );
*pval = val;
} //op_sar16
void i8086::op_cmps8()
{
op_sub8( * flat_address8( get_seg_value(), si ), * flat_address8( es, di ) ); // es cannot be overridden
update_rep_sidi8();
} //op_cmps8
void i8086::op_cmps16()
{
op_sub16( * flat_address16( get_seg_value(), si ), * flat_address16( es, di ) ); // es cannot be overridden
update_rep_sidi16();
} //op_cmps16
void i8086::op_movs8()
{
* flat_address8( es, di ) = * flat_address8( get_seg_value(), si );
update_rep_sidi8();
} //op_movs8
void i8086::op_movs16()
{
// one byte at a time for segment wrapping. in this order in case addresses are near. turbo c v2.0 does this.
uint16_t seg = get_seg_value();
uint8_t l = * flat_address8( seg, si );
uint8_t h = * flat_address8( seg, si + 1 );
* flat_address8( es, di ) = l;
* flat_address8( es, di + 1 ) = h;
update_rep_sidi16();
} //op_movs16
void i8086::op_sto8()
{
* flat_address8( es, di ) = al();
update_index8( di );
} //op_sto8
void i8086::op_sto16()
{
// one byte at a time for segment wrapping. in this order in case addresses are near
* flat_address8( es, di + 1 ) = ah();
* flat_address8( es, di ) = al();
update_index16( di );
} //op_sto16
void i8086::op_lods8()
{
set_al( * flat_address8( get_seg_value(), si ) );
update_index8( si );
} //op_lods8
void i8086::op_lods16()
{
ax = * flat_address16( get_seg_value(), si );
update_index16( si );
} //op_lods16
void i8086::op_scas8()
{
op_sub8( al(), * flat_address8( es, di ) ); // es cannot be overridden
update_index8( di );
} //op_scas8
void i8086::op_scas16()
{
op_sub16( ax, * flat_address16( es, di ) ); // es cannot be overridden
update_index16( di );
} //op_scas16
#if I8086_UNDOCUMENTED
void i8086::op_setmo8( uint8_t * pval, uint8_t shift )
{
if ( 0 == shift )
return;
*pval = 0xff;
fCarry = false;
fOverflow = false;
set_PSZ8( *pval );
} //op_setmo8
void i8086::op_setmo16( uint16_t * pval, uint8_t shift )
{
if ( 0 == shift )
{
fOverflow = false;
return;
}
*pval = 0xffff;
fCarry = false;
fOverflow = false;
set_PSZ16( *pval );
} //op_setmo16
#endif
void i8086::op_rotate8( uint8_t * pval, uint8_t operation, uint8_t amount )
{
switch( operation )
{
case 0: op_rol8( pval, amount ); break;
case 1: op_ror8( pval, amount ); break;
case 2: op_rcl8( pval, amount ); break;
case 3: op_rcr8( pval, amount ); break;
case 4: op_sal8( pval, amount ); break; // aka shl
case 5: op_shr8( pval, amount ); break;
#if I8086_UNDOCUMENTED
case 6: op_setmo8( pval, amount ); break;
#endif
case 7: op_sar8( pval, amount ); break;
}
} //op_rotate8
void i8086::op_rotate16( uint16_t * pval, uint8_t operation, uint8_t amount )
{
switch( operation )
{
case 0: op_rol16( pval, amount ); break;
case 1: op_ror16( pval, amount ); break;
case 2: op_rcl16( pval, amount ); break;
case 3: op_rcr16( pval, amount ); break;
case 4: op_sal16( pval, amount ); break; // aka shl
case 5: op_shr16( pval, amount ); break;
#if I8086_UNDOCUMENTED
case 6: op_setmo16( pval, amount ); break;
#endif
case 7: op_sar16( pval, amount ); break;
}
} //op_rotate16
not_inlined void i8086::op_interrupt( uint8_t interrupt_num, uint8_t instruction_length )
{
if ( g_State & stateTraceInstructions )
tracer.Trace( "op_interrupt num %#x, length %d\n", interrupt_num, instruction_length );
materializeFlags();
push( flags );
fInterrupt = false; // will be set again if/when flags are popped on iret
fTrap = false;
//fAuxCarry = false; // some doc says this but not the October '79 Intel doc.
push( cs );
push( ip + instruction_length );
uint16_t * vectorItem = flat_address16( 0, 4 * interrupt_num );
ip = vectorItem[ 0 ];
cs = vectorItem[ 1 ];
if ( ( 0 == ip ) && ( 0 == cs ) )
{
tracer.Trace( "probable app bug: invoking interrupt %02x, which has a vector of 0:0\n", interrupt_num );
i8086_hard_exit( "fatal error: interrupt vector points to 0:0\n" );
}
} //op_interrupt
not_inlined void i8086::op_daa()
{
// Simplified code from https://www.righto.com/2023/01/understanding-x86s-decimal-adjust-after.html
uint8_t old_al = al();
// This funny check is not actually documented anywhere but checked against real hardware.
// What's "documented" is that the check is done against 0x9f or 0x99 depending on the documentation you check :)
uint8_t al_check = fAuxCarry ? 0x9F : 0x99;
if ( ( ( al() & 0xf ) > 9 ) || fAuxCarry )
{
set_al( al() + 6 );
fAuxCarry = true;
}
if ( ( old_al > al_check ) || fCarry )
{
set_al( al() + 0x60 );
fCarry = true;
}
set_PSZ8( al() );
} //op_daa
not_inlined void i8086::op_das()
{
uint8_t old_al = al();
uint8_t al_check = fAuxCarry ? 0x9F : 0x99;
if ( ( ( al() & 0xf ) > 9 ) || ( fAuxCarry ) )
{
set_al( al() - 6 );
fAuxCarry = true;
}
else
fAuxCarry = false;
if ( ( old_al > al_check ) || ( fCarry ) )
{
set_al( al() - 0x60 );
fCarry = true;
}
else
fCarry = false;
set_PSZ8( al() );
} //op_das
not_inlined void i8086::op_aas()
{
if ( ( ( al() & 0x0f ) > 9 ) || fAuxCarry )
{
// Intel's documentation shows `ax` being affected here, but actual HW behavior seems to use `al` instead
uint8_t new_al = al() - 6;
set_ah( ah() - 1 );
fAuxCarry = 1;
fCarry = 1;
set_al( new_al & 0x0f );
}
else
{
fAuxCarry = false;
fCarry = false;
set_al( al() & 0x0f );
}
} //op_aas
not_inlined void i8086::op_aaa()
{
if ( ( ( al() & 0xf ) > 9 ) || fAuxCarry )
{
// Intel's documentation does `ax = ax + 0x106`, but this leads to incorrect behavior when `al` carries into `ah`
set_al( al() + 6 );
set_ah( ah() + 1 );
fAuxCarry = true;
fCarry = true;
}
else
{
fAuxCarry = false;
fCarry = false;
}
set_al( al() & 0x0f );
} //op_aaa
not_inlined void i8086::op_sahf()
{
uint8_t fl = ah();
fSign = ( 0 != ( fl & 0x80 ) );
fZero = ( 0 != ( fl & 0x40 ) );
fAuxCarry = ( 0 != ( fl & 0x10 ) );
fParityEven = ( 0 != ( fl & 0x04 ) );
fCarry = ( 0 != ( fl & 1 ) );
} //op_sahf
not_inlined void i8086::op_lahf()
{
uint8_t fl = 0x02;
if ( fSign ) fl |= 0x80;
if ( fZero ) fl |= 0x40;
if ( fAuxCarry ) fl |= 0x10;
if ( fParityEven ) fl |= 0x04;
if ( fCarry ) fl |= 1;
set_ah( fl );
} //op_lahf
not_inlined bool i8086::op_f6() // return true if divide by 0
{
_bc++;
if ( ( 0 == _reg ) || ( I8086_UNDOCUMENTED && ( 1 == _reg ) ) ) // test reg8/mem8, immed8
{
AddMemCycles( 10 );
uint8_t lhs = * get_rm_ptr8();
uint8_t rhs = _pcode[ _bc++ ];
op_and8( lhs, rhs );
}
else if ( 2 == _reg ) // not reg8/mem8 -- no flags updated
{
AddMemCycles( 19 );
uint8_t * pval = get_rm_ptr8();
*pval = ~ ( *pval );
}
else if ( 3 == _reg ) // neg reg8/mem8 (subtract from 0)
{
AddMemCycles( 19 );
uint8_t * pval = get_rm_ptr8();
*pval = op_sub8( 0, *pval );
}
else if ( 4 == _reg ) // mul. ax = al * r/m8
{
AddCycles( 77 ); // assume worst-case
uint8_t rhs = * get_rm_ptr8();
ax = (uint16_t) al() * (uint16_t) rhs;
fCarry = fOverflow = ( 0 != ah() );
set_PSZ16( ax ); // documentation says these bits are undefined, but real hardware does this
fSign = ( 0 != ( 0x80 & al() ) ); // documentation says these bits are undefined, but real hardware does this
}
else if ( 5 == _reg ) // imul. ax = al * r/m8
{
AddCycles( 98 ); // assume worst-case
uint8_t rhs = * get_rm_ptr8();
uint32_t result = (int16_t) (int8_t) al() * (int16_t) (int8_t) rhs;
ax = result & 0xffff;
result &= 0xffffff80;
fCarry = fOverflow = ( ( 0 != result ) && ( 0xffffff80 != result ) );
set_PSZ16( ax ); // documentation says these bits are undefined, but real hardware does this
}
else if ( 6 == _reg ) // div m, r8 / src. al = result, ah = remainder
{
AddCycles( 90 ); // assume worst-case
uint8_t rhs = * get_rm_ptr8();
if ( 0 != rhs )
{
uint16_t lhs = ax;
uint16_t result = lhs / (uint16_t) rhs;
if ( result <= 0xff )
{
set_al( (uint8_t) result );
set_ah( lhs % rhs );
// Intel documentation says "The content of AF, CF, OF, PF, SF and ZF is undefined following DIV."
}
else
return true;
}
else
return true;
}
else if ( 7 == _reg ) // idiv r/m8
{
AddCycles( 112 ); // assume worst-case
uint8_t rhs = * get_rm_ptr8();
if ( 0 != rhs )
{
int16_t lhs = ax;
int16_t result = lhs / (int16_t) (int8_t) rhs;
if ( result <= 127 && result >= -127 ) // odd that -128 is invalid, but that's how it works
{
if ( 0xff != prefix_repeat_opcode ) // https://github.com/TomHarte/ProcessorTests/tree/main/8088
result = -result;
set_al( result & 0xff );
set_ah( lhs % (int16_t) (int8_t) rhs );
assert( ( 0 == ah() ) || ( ( 0 == ( ah() & 0x80 ) ) == ( 0 == ( lhs & 0x8000 ) ) ) ); // remainder is 0 or has same sign as dividend
// Intel documentation says "The content of AF, CF, OF, PF, SF and ZF is undefined following IDIV."
// Some other emulators set O, S, and C flags.
}
else
return true;
}
else
return true;
}
else
unhandled_instruction();
return false;
} //op_f6
not_inlined bool i8086::op_f7() // return true if divide by 0
{
_bc++;
if ( ( 0 == _reg ) || ( I8086_UNDOCUMENTED && ( 1 == _reg ) ) ) // test reg16/mem16, immed16
{
AddMemCycles( 10 );
uint16_t lhs = * get_rm_ptr16();
uint16_t rhs = * (uint16_t *) ( _pcode + _bc );
_bc += 2;
op_and16( lhs, rhs );
}
else if ( 2 == _reg ) // not reg16/mem16 -- no flags updated
{
AddMemCycles( 19 );
uint16_t * pval = get_rm_ptr16();
*pval = ~ ( *pval );
}
else if ( 3 == _reg ) // neg reg16/mem16 (subtract from 0)
{
AddMemCycles( 19 );
uint16_t * pval = get_rm_ptr16();
*pval = op_sub16( 0, *pval );
}
else if ( 4 == _reg ) // mul. dx:ax = ax * src
{
AddCycles( 133 ); // assume worst-case
uint16_t rhs = * get_rm_ptr16();
uint32_t result = (uint32_t) ax * (uint32_t) rhs;
dx = result >> 16;
ax = result & 0xffff;
fCarry = fOverflow = ( result > 0xffff );
set_PSZ16( ax ); // documentation says these bits are undefined, but real hardware does this
}
else if ( 5 == _reg ) // imul. dx:ax = ax * src
{
AddCycles( 154 ); // assume worst-case
uint16_t rhs = * get_rm_ptr16();
uint32_t result = (int32_t) (int16_t) ax * (int32_t) (int16_t) rhs;
dx = result >> 16;
ax = result & 0xffff;
result &= 0xffff8000;
fCarry = fOverflow = ( ( 0 != result ) && ( 0xffff8000 != result ) );
set_PSZ16( ax ); // documentation says these bits are undefined, but real hardware does this
}
else if ( 6 == _reg ) // div dx:ax / src. ax = result, dx = remainder
{
AddCycles( 162 ); // assume worst-case
uint16_t rhs = * get_rm_ptr16();
if ( 0 != rhs )
{
uint32_t lhs = ( (uint32_t) dx << 16 ) + (uint32_t) ax;
uint32_t result = lhs / (uint32_t) rhs;
if ( result <= 0xffff )
{
ax = (uint16_t) result;
dx = lhs % rhs;
}
else
return true;
// Intel documentation says "The content of AF, CF, OF, PF, SF and ZF is undefined following DIV."
}
else
return true;
}
else if ( 7 == _reg ) // idiv dx:ax / src. signed division. ax = result, dx = remainder (same sign as result)
{
AddCycles( 184 ); // assume worst-case
uint16_t rhs = * get_rm_ptr16();
if ( 0 != rhs )