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Merge pull request #1233 from diffblue/buechi-sequence_first_match
SVA->Buechi: implement `first_match(...)` sequence operator
2 parents b516979 + 4c4e2e5 commit 8637364

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-18
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+23
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regression/ebmc-spot/sva-buechi/sequence_first_match1.desc

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CORE
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../../verilog/SVA/sequence_first_match1.sv
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--buechi --k-induction --bound 1
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^\[.*\] first_match\(main\.x == 0\): PROVED$
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^\[.*\] first_match\(main\.x == 0, main\.x\+\+\): PROVED$
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^EXIT=0$
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^SIGNAL=0$
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--
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^warning: ignoring
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--
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CORE
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../../verilog/SVA/sequence_first_match2.sv
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--buechi --bound 5
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^error: failed to convert sva_sequence_first_match$
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^EXIT=6$
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^SIGNAL=0$
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--
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--buechi --k-induction --bound 2
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^\[.*\] \(\(##1 1\) or \(##2 1\)\) \|-> main.x == 1: REFUTED$
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^\[.*\] first_match\(\(##1 1\) or \(##2 1\)\) \|-> main\.x == 1: PROVED up to bound 5$
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^\[.*\] first_match\(\(##1 1\) or \(##2 1\)\) \|-> main\.x == 1: PROVED$
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^\[.*\] \(1 or \(##1 1\)\) \|-> main\.x == 0: REFUTED$
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^\[.*\] first_match\(1 or \(##1 1\)\) \|-> main\.x == 0: PROVED up to bound 5$
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^\[.*\] first_match\(1 or \(##1 1\)\) \|-> main\.x == 0: PROVED$
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^EXIT=10$
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^SIGNAL=0$
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--
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^warning: ignoring
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--

src/temporal-logic/ltl_sva_to_string.cpp

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@@ -541,6 +541,13 @@ ltl_sva_to_stringt::rec(const exprt &expr, modet mode)
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DATA_INVARIANT(
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false, "unexpected sva_sequence_non_consecutive_repetition");
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}
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else if(expr.id() == ID_sva_sequence_first_match) // first_match(...)
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{
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PRECONDITION(mode == SVA_SEQUENCE);
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auto &sequence = to_sva_sequence_first_match_expr(expr).sequence();
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auto op_rec = rec(sequence, SVA_SEQUENCE);
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return resultt{precedencet::ATOM, "first_match(" + op_rec.s + ')'};
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}
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else if(!is_temporal_operator(expr))
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{
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auto number = atoms.number(expr);

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