.gitignore

*~
all-tests
cmake_install.cmake
*.a
CMakeCache.txt
CMakeFiles/
Makefile
test/ll_files/*.ll
single_store
single_store.v
plus
plus.v
if_else.v
if_else
read_2
read_2.v
loop_add_7.v
loop_add_7
obj_dir/
many_adds
many_adds.v
read_2_failing.v
cmp_gt
cmp_gt.v
loop_add_4.v
loop_add_4
loop_add_4_6_iters
loop_add_4_6_iters.v
loop_add_4_copy
loop_add_4_copy.v
a.out
blur_no_lb_tb.v
blur_no_lb
blur_no_lb.v
*.txt
blur_lb
blur_lb.ll
blur_lb.v
blur_lb_tb.v
/#*
mvmul
mvmul.v
stalled_single_store
stalled_single_store.v
stalled_single_store_axi
stalled_single_store_axi.v
brighter
brighter.v
brighter_tb.v
using_shift_register
using_shift_register.v
using_shift_register_tb.v
one_register.v
one_register_tb.v
sr_stencil_loop
sr_stencil_loop.v
sr_stencil_loop_tb.v
*.ll
*.o
accum_loop
accum_loop.v
accum_loop_tb.v
one_d_stencil
one_d_stencil.v
one_d_stencil_sr
one_d_stencil_sr.v
one_d_stencil_sr_tb.v
one_d_stencil_tb.v
bb_diamond*
mem_16_test*
tf
shift_register*
constrained_pipe*
mem_dep_pipe*
temp_storage_pipe*
outer_read_pipe*
experiments/
fifo_user*
fifo_read_delay*
sys_array_1_2*
timed_wire_reduce*
timed_wire_reduce_fp.v
add_reduce_15*
fifo
fifo_3
fifo_in_loop
fifo_in_loop.v
test/ll_files/host/
test/host
timed_wire_fp_add*
direct_port_fp_add*
dh_test
dh_test*
loop_add_4_tb_cpy.v
one_register
sys_array_2x2
sys_array_2x2.v
sys_array_fifo.v
dynamic_arch
dynamic_arch.v
make-bindings
synthesize-reduce-4
fix_assert_calls.py
dynamic_arch_sram_class
dynamic_arch_sram_class.v
reduce_4.v
add_10_channel*
add_10_template*
channel_reduce_4*
channel_add*
li_loop*
_Z15add_10_templatePN4DHLS4FifoIiLi32EEES2_.v
_Z7if_elseP5RAM_2IiLi16EE.v
.#complex_num.v
_Z15loop_add_4_copyP5RAM_2IiLi16EE.v
_Z5mvmulP5RAM_2IiLi32EE.v
_Z5mvmulP5RAM_3IiLi32EE.v
_Z7blur_lbP3RAMIiLi16EE.v
complex_num
complex_num.v
compound_fifo.v
histogram.v
reduce_4
reduce_4_tb.v
stencil_stream_rw*
stencil_mul_2*
stencil_stream_mul*
stencil_copy*
median_filter*
raw_axi_wr*
vhls_target*
parser
count_packets*
*.json
synthesize-interface-functions
axi_multi_transfer*
filter_ram*
write_one_byte_packet*
fadd_32*
store_to_reg*
test/ll_files/iclass.h
test/ll_files/intuitive.cpp
test/ll_files/intuitive.v
test/ll_files/ip_counter.cpp
test/ll_files/ip_counter_sw.cpp
axi_burst_multi*
axi_read_burst_func*
*.bc
axi_write_burst*
fadd*
run_median_func.v
abstract.tex
instantiate_reg.v
old_single_store.v
ram_write_cleaned_up.v
run_median_func*
test/ll_files/block_ram_256_16.h
test/ll_files/block_ram_256_16_test.cpp
test/ll_files/channel_scratch.cpp
stencil_write_loop*
outer_loop_pipe*
simple_outer_pipe*
simple_outer_loop.v
task_parallel_loop*
cascade_halide_first_lb*
halid_cascade*
independent_writes*
hist_simple_illegal*
hist_simple*
cascade_halide_ram_set_loop*
halide_cascade*
hist_forwarded*
pipelined_structural_hazard*
pipelined_independent_writes*
pipelined_memory_hazard*
conv_2_1*
custom_if*
packet_example*
packet_mixed_assign*
primitive_assign*
halide_stencil_get_01*
lb_3x3
lb_3x3_unit_test.v
lb_basic
lb_tb
cascade_push*
conv_3_3*
aha-HLS
convs.v
int_add_func.v
int_add_wrapper.h