-
Notifications
You must be signed in to change notification settings - Fork 19
/
Copy pathsys_array_2x2_tb.v
290 lines (216 loc) · 9.13 KB
/
sys_array_2x2_tb.v
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
`define assert(signal, value) if ((signal) !== (value)) begin $display("ASSERTION FAILED in %m: signal != value"); $finish(1); end
`define POSEDGE #1 clk = 0; #1 clk = 1;
module sys_array_2x2_tb();
reg [0:0] rst;
reg [0:0] clk;
wire [0:0] valid;
wire [31:0] global_state_dbg;
wire read_valid0;
wire read_ready0;
reg write_valid0;
wire write_ready0;
reg [15:0] in_data0;
wire [15:0] out_data0;
wire read_valid1;
wire read_ready1;
reg write_valid1;
wire write_ready1;
reg [15:0] in_data1;
wire [15:0] out_data1;
wire read_valid2;
wire read_ready2;
reg write_valid2;
wire write_ready2;
reg [15:0] in_data2;
wire [15:0] out_data2;
wire read_valid3;
wire read_ready3;
reg write_valid3;
wire write_ready3;
reg [15:0] in_data3;
wire [15:0] out_data3;
reg read_valid4;
wire read_ready4;
wire write_valid4;
wire write_ready4;
wire [15:0] in_data4;
wire [15:0] out_data4;
reg read_valid5;
wire read_ready5;
wire write_valid5;
wire write_ready5;
wire [15:0] in_data5;
wire [15:0] out_data5;
initial begin
#1 rst = 1;
#1 write_valid0 = 0;
#1 write_valid1 = 0;
#1 write_valid2 = 0;
#1 write_valid3 = 0;
#1 read_valid4 = 0;
#1 read_valid5 = 0;
`POSEDGE
#1 rst = 0;
// After reset we are in global state 0,
// and the first read has not been done so the ready is zero
#1 `assert(global_state_dbg, 0)
#1 write_valid0 = 1;
#1 write_valid1 = 1;
#1 write_valid2 = 1;
#1 write_valid3 = 1;
#1 in_data0 = 1;
#1 in_data1 = 0;
#1 in_data2 = 5;
#1 in_data3 = 0;
`POSEDGE
// Still in global state 0, but read readys are now 1
#1 `assert(global_state_dbg, 0)
#1 `assert(read_ready0, 1)
#1 `assert(read_ready1, 1)
#1 `assert(read_ready2, 1)
#1 `assert(read_ready3, 1)
#1 write_valid0 = 1;
#1 write_valid1 = 1;
#1 write_valid2 = 1;
#1 write_valid3 = 1;
#1 in_data0 = 2;
#1 in_data1 = 3;
#1 in_data2 = 7;
#1 in_data3 = 6;
`POSEDGE
#1 `assert(global_state_dbg, 1)
#1 write_valid0 = 1;
#1 write_valid1 = 1;
#1 write_valid2 = 1;
#1 write_valid3 = 1;
#1 in_data0 = 0;
#1 in_data1 = 4;
#1 in_data2 = 0;
#1 in_data3 = 8;
`POSEDGE
#1 `assert(global_state_dbg, 2)
#1 write_valid0 = 1;
#1 write_valid1 = 1;
#1 write_valid2 = 1;
#1 write_valid3 = 1;
#1 in_data0 = 0;
#1 in_data1 = 0;
#1 in_data2 = 0;
#1 in_data3 = 0;
`POSEDGE
#1 write_valid0 = 0;
#1 write_valid1 = 0;
#1 write_valid2 = 0;
#1 write_valid3 = 0;
#1 `assert(global_state_dbg, 3)
`POSEDGE
#1 `assert(global_state_dbg, 4)
#1 `assert(valid, 1'b0)
`POSEDGE
#1 `assert(global_state_dbg, 5)
#1 `assert(valid, 1'b0)
`POSEDGE
`POSEDGE
`POSEDGE
`POSEDGE
`POSEDGE
`POSEDGE
`POSEDGE
`POSEDGE
`POSEDGE
// #1 `assert(global_state_dbg, 6)
#1 `assert(valid, 1'b1)
`POSEDGE
#1 `assert(read_ready4, 1'b1)
#1 `assert(read_ready5, 1'b1)
#1 read_valid4 = 1;
#1 read_valid5 = 1;
`POSEDGE
#1 `assert(out_data4, 19)
#1 `assert(out_data5, 22)
#1 `assert(read_ready4, 1'b1)
#1 `assert(read_ready5, 1'b1)
#1 read_valid4 = 1;
#1 read_valid5 = 1;
`POSEDGE
#1 `assert(out_data4, 43)
#1 `assert(out_data5, 50)
#1 read_valid4 = 0;
#1 read_valid5 = 0;
`POSEDGE
$display("Passed");
end // initial begin
// always @(posedge clk) begin
// $display("out_data4 = %d", out_data4);
// $display("out_data5 = %d", out_data5);
// end
fifo #(.WIDTH(16), .DEPTH(8)) fifo0(.clk(clk),
.rst(rst),
.read_valid(read_valid0),
.write_valid(write_valid0),
.read_ready(read_ready0),
.write_ready(write_ready0),
.in_data(in_data0),
.out_data(out_data0));
fifo #(.WIDTH(16), .DEPTH(8)) fifo1(.clk(clk),
.rst(rst),
.read_valid(read_valid1),
.write_valid(write_valid1),
.read_ready(read_ready1),
.write_ready(write_ready1),
.in_data(in_data1),
.out_data(out_data1));
fifo #(.WIDTH(16), .DEPTH(8)) fifo2(.clk(clk),
.rst(rst),
.read_valid(read_valid2),
.write_valid(write_valid2),
.read_ready(read_ready2),
.write_ready(write_ready2),
.in_data(in_data2),
.out_data(out_data2));
fifo #(.WIDTH(16), .DEPTH(8)) fifo3(.clk(clk),
.rst(rst),
.read_valid(read_valid3),
.write_valid(write_valid3),
.read_ready(read_ready3),
.write_ready(write_ready3),
.in_data(in_data3),
.out_data(out_data3));
fifo #(.WIDTH(16), .DEPTH(8)) fifo4(.clk(clk),
.rst(rst),
.read_valid(read_valid4),
.write_valid(write_valid4),
.read_ready(read_ready4),
.write_ready(write_ready4),
.in_data(in_data4),
.out_data(out_data4));
fifo #(.WIDTH(16), .DEPTH(8)) fifo5(.clk(clk),
.rst(rst),
.read_valid(read_valid5),
.write_valid(write_valid5),
.read_ready(read_ready5),
.write_ready(write_ready5),
.in_data(in_data5),
.out_data(out_data5));
sys_array_2x2 dut(.clk(clk), .rst(rst), .valid(valid),
.arg_0_out_data(out_data0),
.arg_0_read_valid(read_valid0),
.arg_0_read_ready(read_ready0),
.arg_1_out_data(out_data1),
.arg_1_read_valid(read_valid1),
.arg_1_read_ready(read_ready1),
.arg_2_out_data(out_data2),
.arg_2_read_valid(read_valid2),
.arg_2_read_ready(read_ready2),
.arg_3_out_data(out_data3),
.arg_3_read_valid(read_valid3),
.arg_3_read_ready(read_ready3),
.arg_4_in_data(in_data4),
.arg_4_write_valid(write_valid4),
.arg_4_write_ready(write_ready4),
.arg_5_in_data(in_data5),
.arg_5_write_valid(write_valid5),
.arg_5_write_ready(write_ready5),
.global_state_dbg(global_state_dbg)
);
endmodule