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scheduling.cpp
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#define CATCH_CONFIG_MAIN
#include "catch.hpp"
#include "verilog_backend.h"
#include "llvm_codegen.h"
#include "test_utils.h"
#include <llvm/IR/Dominators.h>
#include <llvm/Analysis/LoopInfo.h>
#include <llvm/Transforms/Utils/BasicBlockUtils.h>
using namespace dbhc;
using namespace llvm;
using namespace std;
namespace ahaHLS {
void resetOnCycle(const int rstCycle, TestBenchSpec& tb) {
map_insert(tb.actionsInCycles, rstCycle, string("rst_reg = 1;"));
map_insert(tb.actionsInCycles, rstCycle + 1, string("rst_reg = 0;"));
}
void addRAMFunctions(Value* ramArg,
HardwareConstraints& hcs,
InterfaceFunctions& interfaces) {
hcs.typeSpecs[string("SRAM_32_16")] =
[](StructType* tp) { return ramSpec(32, 16); };
Function* ramRead = ramLoadFunction(ramArg);
interfaces.addFunction(ramRead);
implementRAMRead0(ramRead,
interfaces.getConstraints(ramRead));
Function* ramWrite = ramStoreFunction(ramArg);
interfaces.addFunction(ramWrite);
implementRAMWrite0(ramWrite,
interfaces.getConstraints(ramWrite));
}
TestBenchSpec buildTB(std::string name,
map<string, vector<int> >& memoryInit,
map<string, vector<int> >& memoryExpected,
map<string, int>& testLayout);
ModuleSpec axiWriterSpec(llvm::StructType* tp) {
map<string, string> modParams;
map<string, Port> ports{{"write_data", inputPort(32, "write_data")},
{"write_addr", inputPort(5, "write_addr")},
{"valid", outputPort(1, "valid")},
{"ready", outputPort(1, "ready")},
{"start_write", inputPort(1, "start_write")}};
map<string, int> defaults{{"start_write", 0}};
return {modParams, "axi_write_handler", ports, defaults};
}
ModuleSpec axiReaderSpec(llvm::StructType* tp) {
map<string, string> modParams;
map<string, Port> ports{{"read_data", outputPort(32, "read_data")},
{"read_addr", inputPort(5, "read_addr")},
{"valid", outputPort(1, "valid")},
{"ready", outputPort(1, "ready")},
{"start_read", inputPort(1, "start_read")}};
map<string, int> defaults{{"start_read", 0}};
return {modParams, "axi_read_handler", ports, defaults};
}
// Q: System TODOs:
// A: Remove useless address fields from registers (allow custom memory interfaces)
// Move test layout into testbenchspec
// Add some simple examples to the README
// Convert ptr to builtin codes to RAM templates
// Shrink registers to reduce area costs
// Remove modspecs
// Remove internal RAM code
// Add full paths for interface classes
// NOTE: The code for testbenches is getting really complicated. Some of that
// is automatic testbench generation, but some of it is just the hodgepodge of
// different data structures for scheduling, verilog code generation, and
// constraint generation. These really need to be fixed up.
// Ideas?
// 1. Merge schedule and STG creation in to one function when the schedule
// does not need to be checked
// 2. Remove or wrap the function -> SchedulingConstraints map
// Q: What test cases do I need?
// A: Test case with outer loop pipelining
// Test case that pipelines inner loop surrounded by outer loop
// Test case using a ready-valid interface together with pipelining
// Test case that builds a linebuffer from LLVM
// Test case with struct (compound type) passed via channel (or used by value)
TEST_CASE("Schedule a single store operation") {
SMDiagnostic err;
LLVMContext context;
setGlobalLLVMContext(&context);
auto mod = loadCppModule(context, err, "single_store");
setGlobalLLVMModule(mod.get());
auto f = getFunctionByDemangledName(mod.get(), "single_store");
getArg(f, 0)->setName("a");
cout << "LLVM Function" << endl;
cout << valueString(f) << endl;
InterfaceFunctions interfaces;
interfaces.functionTemplates[string("read")] = implementRAMRead0;
interfaces.functionTemplates[string("write")] = implementRAMWrite0;
HardwareConstraints hcs = standardConstraints();
hcs.typeSpecs["class.RAM"] = ramSpecFunc;
hcs.typeSpecs["class.RAM_2"] = ram2SpecFunc;
Schedule s = scheduleInterface(f, hcs, interfaces);
REQUIRE(s.numStates() == 4);
auto& retInstr = f->getBasicBlockList().back().back();
REQUIRE(s.startTime(&retInstr) == 3);
STG graph = buildSTG(s, f);
cout << "STG Is" << endl;
graph.print(cout);
REQUIRE(graph.numControlStates() == 4);
map<llvm::Value*, int> layout = {};
//ArchOptions options;
auto arch = buildMicroArchitecture(graph, layout, hcs);
VerilogDebugInfo info;
emitVerilog("single_store", arch, info);
REQUIRE(runIVerilogTB("single_store"));
}
TEST_CASE("Histogram with pipelining") {
SMDiagnostic err;
LLVMContext context;
setGlobalLLVMContext(&context);
auto mod = loadCppModule(context, err, "hist_simple");
setGlobalLLVMModule(mod.get());
auto f = getFunctionByDemangledName(mod.get(), "hist_simple");
getArg(f, 0)->setName("img");
getArg(f, 1)->setName("hist");
cout << "LLVM Function" << endl;
cout << valueString(f) << endl;
InterfaceFunctions interfaces;
interfaces.functionTemplates[string("read")] = implementRAMRead0;
interfaces.functionTemplates[string("write")] = implementRAMWrite0;
HardwareConstraints hcs = standardConstraints();
hcs.typeSpecs["class.RAM"] = ramSpecFunc;
hcs.typeSpecs["class.RAM.0"] = ramSpecFunc;
hcs.typeSpecs["class.RAM.0.2"] = ramSpecFunc;
hcs.typeSpecs["class.RAM.1"] = ramSpecFunc;
hcs.typeSpecs["class.RAM_2"] = ram2SpecFunc;
map<string, int> testLayout = {};
TestBenchSpec tb;
tb.memoryExpected = {};
tb.runCycles = 100;
tb.name = "hist_simple";
tb.useModSpecs = true;
int startSetMemCycle = 1;
int startRunCycle = startSetMemCycle + 20;
map_insert(tb.actionsOnCycles, 1, string("rst_reg <= 1;"));
map_insert(tb.actionsInCycles, startRunCycle, string("rst_reg = 1;"));
map_insert(tb.actionsInCycles, startRunCycle + 1, string("rst_reg = 0;"));
int checkMemCycle = 100;
//checkRAM(tb, checkMemCycle, "arg_0", memoryExpected, testLayout);
setRAMContents(tb, startSetMemCycle, "img", {0, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2, 3, 3});
setRAMContents(tb, startSetMemCycle, "hist", {0, 0, 0, 0});
checkRAMContents(tb, checkMemCycle + 100, "hist", {1, 8, 5, 2});
SECTION("Baseline: No pipelining") {
Schedule s = scheduleInterface(f, hcs, interfaces);
STG graph = buildSTG(s, f);
cout << "STG Is" << endl;
graph.print(cout);
map<llvm::Value*, int> layout = {};
auto arch = buildMicroArchitecture(graph, layout, hcs);
VerilogDebugInfo info;
addNoXChecks(arch, info);
emitVerilog("hist_simple", arch, info);
emitVerilogTestBench(tb, arch, testLayout);
REQUIRE(runIVerilogTB("hist_simple"));
}
SECTION("With illegal pipeline II") {
set<BasicBlock*> toPipeline;
for (auto& bb : f->getBasicBlockList()) {
toPipeline.insert(&bb);
}
Schedule s = scheduleInterface(f, hcs, interfaces, toPipeline);
STG graph = buildSTG(s, f);
cout << "STG Is" << endl;
graph.print(cout);
map<llvm::Value*, int> layout = {};
auto arch = buildMicroArchitecture(graph, layout, hcs);
VerilogDebugInfo info;
addNoXChecks(arch, info);
emitVerilog("hist_simple_illegal", arch, info);
tb.name = "hist_simple_illegal";
emitVerilogTestBench(tb, arch, testLayout);
// This should fail
REQUIRE(!runIVerilogTB("hist_simple_illegal"));
}
SECTION("Pipelined, forwarded histogram") {
auto mod = loadCppModule(context, err, "hist_forwarded");
setGlobalLLVMModule(mod.get());
auto f = getFunctionByDemangledName(mod.get(), "hist_forwarded");
getArg(f, 0)->setName("img");
getArg(f, 1)->setName("hist");
cout << "LLVM Function" << endl;
cout << valueString(f) << endl;
ExecutionConstraints exec;
inlineWireCalls(f, exec, interfaces);
addDataConstraints(f, exec);
cout << "After inlining" << endl;
cout << valueString(f) << endl;
auto preds = buildControlPreds(f);
set<PipelineSpec> toPipeline;
PipelineSpec all{false, {}};
for (auto& blk : f->getBasicBlockList()) {
if (&blk != &(f->getEntryBlock())) {
if (!ReturnInst::classof(blk.getTerminator())) {
all.blks.insert(&blk);
cout << "Pipelining block " << endl;
cout << valueString(&blk) << endl;
}
}
}
toPipeline.insert(all);
// Changed
SchedulingProblem p = createSchedulingProblem(f, hcs, toPipeline, preds);
exec.addConstraints(p, f);
map<Function*, SchedulingProblem> constraints{{f, p}};
Schedule s = scheduleFunction(f, hcs, toPipeline, constraints);
STG graph = buildSTG(s, f);
cout << "STG Is" << endl;
graph.print(cout);
map<llvm::Value*, int> layout = {};
auto arch = buildMicroArchitecture(graph, layout, hcs);
VerilogDebugInfo info;
addNoXChecks(arch, info);
emitVerilog("hist_forwarded", arch, info);
tb.name = "hist_forwarded";
emitVerilogTestBench(tb, arch, testLayout);
//REQUIRE(runIVerilogTB("hist_forwarded"));
}
}
TEST_CASE("Schedule a single store operation and lowering the microarchitecture") {
SMDiagnostic err;
LLVMContext context;
setGlobalLLVMContext(&context);
auto mod = loadCppModule(context, err, "single_store");
setGlobalLLVMModule(mod.get());
auto f = getFunctionByDemangledName(mod.get(), "single_store");
getArg(f, 0)->setName("a");
cout << "LLVM Function" << endl;
cout << valueString(f) << endl;
InterfaceFunctions interfaces;
interfaces.functionTemplates[string("read")] = implementRAMRead0;
interfaces.functionTemplates[string("write")] = implementRAMWrite0;
HardwareConstraints hcs = standardConstraints();
hcs.typeSpecs["class.RAM"] = ramSpecFunc;
hcs.typeSpecs["class.RAM_2"] = ram2SpecFunc;
Schedule s = scheduleInterface(f, hcs, interfaces);
REQUIRE(s.numStates() == 4);
auto& retInstr = f->getBasicBlockList().back().back();
REQUIRE(s.startTime(&retInstr) == 3);
STG graph = buildSTG(s, f);
cout << "STG Is" << endl;
graph.print(cout);
REQUIRE(graph.numControlStates() == 4);
map<llvm::Value*, int> layout = {};
//ArchOptions options;
auto arch = buildMicroArchitecture(graph, layout, hcs);
convertRegisterControllersToPortControllers(arch);
VerilogDebugInfo info;
emitVerilog("single_store", arch, info);
REQUIRE(runIVerilogTB("single_store"));
}
TEST_CASE("Adding two numbers and storing them back") {
SMDiagnostic Err;
LLVMContext Context;
setGlobalLLVMContext(&Context);
std::unique_ptr<Module> Mod = loadCppModule(Context, Err, "plus");
setGlobalLLVMModule(Mod.get());
Function* f = getFunctionByDemangledName(Mod.get(), "plus");
getArg(f, 0)->setName("mem");
InterfaceFunctions interfaces;
interfaces.functionTemplates[string("read_0")] = implementRAMRead0;
interfaces.functionTemplates[string("read_1")] = implementRAMRead1;
interfaces.functionTemplates[string("write_0")] = implementRAMWrite0;
HardwareConstraints hcs = standardConstraints();
hcs.typeSpecs["class.RAM"] = ramSpecFunc;
hcs.typeSpecs["class.RAM_2"] = ram2SpecFunc;
Schedule s = scheduleInterface(f, hcs, interfaces);
REQUIRE(s.numStates() == 5);
STG graph = buildSTG(s, f);
cout << "STG Is" << endl;
graph.print(cout);
REQUIRE(graph.numControlStates() == 5);
map<llvm::Value*, int> layout = {};
//ArchOptions options;
auto arch = buildMicroArchitecture(graph, layout, hcs);
VerilogDebugInfo info;
emitVerilog("plus", arch, info);
REQUIRE(runIVerilogTB("plus"));
}
TEST_CASE("A simple if") {
SMDiagnostic Err;
LLVMContext Context;
setGlobalLLVMContext(&Context);
std::unique_ptr<Module> Mod = loadCppModule(Context, Err, "if_else");
setGlobalLLVMModule(Mod.get());
Function* f = getFunctionByDemangledName(Mod.get(), "if_else");
getArg(f, 0)->setName("mem");
InterfaceFunctions interfaces;
interfaces.functionTemplates[string("read_0")] = implementRAMRead0;
interfaces.functionTemplates[string("read_1")] = implementRAMRead1;
interfaces.functionTemplates[string("write_0")] = implementRAMWrite0;
HardwareConstraints hcs = standardConstraints();
hcs.typeSpecs["class.RAM"] = ramSpecFunc;
hcs.typeSpecs["class.RAM_2"] = ram2SpecFunc;
Schedule s = scheduleInterface(f, hcs, interfaces);
STG graph = buildSTG(s, f);
cout << "STG Is" << endl;
graph.print(cout);
REQUIRE(!graph.hasTransition(1, 1));
map<llvm::Value*, int> layout = {};
//ArchOptions options;
auto arch = buildMicroArchitecture(graph, layout, hcs);
VerilogDebugInfo info;
addNoXChecks(arch, info);
emitVerilog("if_else", arch, info);
REQUIRE(runIVerilogTB("if_else"));
}
TEST_CASE("Accessing a memory address that requires address calculation") {
SMDiagnostic Err;
LLVMContext Context;
setGlobalLLVMContext(&Context);
std::unique_ptr<Module> Mod = loadCppModule(Context, Err, "read_2"); // Cpp
setGlobalLLVMModule(Mod.get());
Function* f = getFunctionByDemangledName(Mod.get(), "read_2");
getArg(f, 0)->setName("mem");
InterfaceFunctions interfaces;
interfaces.functionTemplates[string("read_0")] = implementRAMRead0;
interfaces.functionTemplates[string("read_1")] = implementRAMRead1;
interfaces.functionTemplates[string("write_0")] = implementRAMWrite0;
HardwareConstraints hcs = standardConstraints();
hcs.typeSpecs["class.RAM"] = ramSpecFunc;
hcs.typeSpecs["class.RAM_2"] = ram2SpecFunc;
Schedule s = scheduleInterface(f, hcs, interfaces);
STG graph = buildSTG(s, f);
cout << "STG Is" << endl;
graph.print(cout);
emitVerilog("read_2", graph, hcs);
REQUIRE(runIVerilogTB("read_2"));
}
TEST_CASE("Histogram of image colors") {
SMDiagnostic Err;
LLVMContext Context;
setGlobalLLVMContext(&Context);
std::unique_ptr<Module> Mod = loadCppModule(Context, Err, "histogram");
setGlobalLLVMModule(Mod.get());
Function* f = getFunctionByDemangledName(Mod.get(), "histogram");
getArg(f, 0)->setName("ram");
InterfaceFunctions interfaces;
interfaces.functionTemplates[string("read")] = implementRAMRead0;
interfaces.functionTemplates[string("write")] = implementRAMWrite0;
HardwareConstraints hcs = standardConstraints();
hcs.typeSpecs["class.RAM"] = ramSpecFunc;
hcs.typeSpecs["class.RAM_2"] = ram2SpecFunc;
Schedule s = scheduleInterface(f, hcs, interfaces);
STG graph = buildSTG(s, f);
cout << "STG Is" << endl;
graph.print(cout);
// emitVerilog("histogram", graph, hcs);
// REQUIRE(runIVerilogTB("histogram"));
}
TEST_CASE("Looping over an array doing a[i] + 7") {
SMDiagnostic Err;
LLVMContext Context;
setGlobalLLVMContext(&Context);
//std::unique_ptr<Module> Mod = loadModule(Context, Err, "loop_add_7");
std::unique_ptr<Module> Mod = loadCppModule(Context, Err, "loop_add_7");
setGlobalLLVMModule(Mod.get());
Function* f = getFunctionByDemangledName(Mod.get(), "loop_add_7");
getArg(f, 0)->setName("ram");
InterfaceFunctions interfaces;
interfaces.functionTemplates[string("read")] = implementRAMRead0;
interfaces.functionTemplates[string("write")] = implementRAMWrite0;
HardwareConstraints hcs = standardConstraints();
hcs.typeSpecs["class.RAM"] = ramSpecFunc;
hcs.typeSpecs["class.RAM_2"] = ram2SpecFunc;
Schedule s = scheduleInterface(f, hcs, interfaces);
STG graph = buildSTG(s, f);
cout << "STG Is" << endl;
graph.print(cout);
VerilogDebugInfo info;
map<Value*, int> layout;
auto arch = buildMicroArchitecture(graph, layout, hcs);
addControlSanityChecks(arch, info);
emitVerilog("loop_add_7", arch, info);
// auto arch = buildMicroArchictecture(graph, hcs);
// addNoXChecks(arch, info);
// //emitVerilog("loop_add_7", graph, hcs);
// emitVerilog("loop_add_7", arch, info);
REQUIRE(runIVerilogTB("loop_add_7"));
}
TEST_CASE("Adding numbers with resource limits") {
SMDiagnostic Err;
LLVMContext Context;
setGlobalLLVMContext(&Context);
std::unique_ptr<Module> Mod =
loadCppModule(Context, Err, "many_adds");
setGlobalLLVMModule(Mod.get());
Function* f = getFunctionByDemangledName(Mod.get(), "many_adds");
getArg(f, 0)->setName("ram");
InterfaceFunctions interfaces;
interfaces.functionTemplates[string("read_0")] = implementRAMRead0;
interfaces.functionTemplates[string("read_1")] = implementRAMRead1;
interfaces.functionTemplates[string("read_2")] = implementRAMRead2;
interfaces.functionTemplates[string("write_0")] = implementRAMWrite0;
HardwareConstraints hcs = standardConstraints();
hcs.typeSpecs["class.RAM"] = ramSpecFunc;
hcs.typeSpecs["class.RAM_2"] = ram2SpecFunc;
hcs.typeSpecs["class.RAM_3"] = ram3SpecFunc;
// Limits number of adders
hcs.setCount(ADD_OP, 1);
Schedule s = scheduleInterface(f, hcs, interfaces);
STG graph = buildSTG(s, f);
cout << "STG Is" << endl;
graph.print(cout);
for (auto st : graph.opStates) {
map<OperationType, int> opCounts;
for (auto instrG : st.second) {
Instruction* instr = instrG;
OperationType tp = opType(instr);
if (contains_key(tp, opCounts)) {
opCounts[tp] = opCounts[tp] + 1;
} else {
opCounts[tp] = 1;
}
}
for (auto op : opCounts) {
REQUIRE(op.second <= hcs.getCount(op.first));
}
}
emitVerilog("many_adds", graph, hcs);
REQUIRE(runIVerilogTB("many_adds"));
}
TEST_CASE("Greater than") {
SMDiagnostic Err;
LLVMContext Context;
setGlobalLLVMContext(&Context);
std::unique_ptr<Module> Mod =
loadCppModule(Context, Err, "cmp_gt");
setGlobalLLVMModule(Mod.get());
Function* f = getFunctionByDemangledName(Mod.get(), "cmp_gt");
getArg(f, 0)->setName("ram");
InterfaceFunctions interfaces;
interfaces.functionTemplates[string("read_0")] = implementRAMRead0;
interfaces.functionTemplates[string("read_1")] = implementRAMRead1;
interfaces.functionTemplates[string("read_2")] = implementRAMRead2;
interfaces.functionTemplates[string("write_0")] = implementRAMWrite0;
HardwareConstraints hcs = standardConstraints();
hcs.typeSpecs["class.RAM"] = ramSpecFunc;
hcs.typeSpecs["class.RAM_2"] = ram2SpecFunc;
hcs.typeSpecs["class.RAM_3"] = ram3SpecFunc;
Schedule s = scheduleInterface(f, hcs, interfaces);
STG graph = buildSTG(s, f);
cout << "STG Is" << endl;
graph.print(cout);
REQUIRE(!graph.hasTransition(1, 1));
emitVerilog("cmp_gt", graph, hcs);
REQUIRE(runIVerilogTB("cmp_gt"));
}
TEST_CASE("Pipelining an array doing a[i] + 7") {
SMDiagnostic Err;
LLVMContext Context;
setGlobalLLVMContext(&Context);
std::unique_ptr<Module> Mod = loadCppModule(Context, Err, "loop_add_7");
setGlobalLLVMModule(Mod.get());
Function* f = getFunctionByDemangledName(Mod.get(), "loop_add_7");
getArg(f, 0)->setName("ram");
std::set<BasicBlock*> blocksToPipeline;
for (auto& bb : f->getBasicBlockList()) {
auto term = bb.getTerminator();
if (BranchInst::classof(term)) {
BranchInst* branch = dyn_cast<BranchInst>(term);
if (branch->isConditional()) {
for (auto succ : branch->successors()) {
if (succ == &bb) {
cout << "Found looped basic block" << endl;
// Now need to compute two things:
// 1. The internal schedule that will be used within iterations
// of the loop
// 2. The initiation interval
// To incorporate this into real code we will also need
// a way to express which blocks are pipelined to the whole
// system scheduler. This scheduler will then have to isolate
// those blocks from the rest of the system
blocksToPipeline.insert(&bb);
}
}
}
}
}
InterfaceFunctions interfaces;
interfaces.functionTemplates[string("read")] = implementRAMRead0;
interfaces.functionTemplates[string("write")] = implementRAMWrite0;
HardwareConstraints hcs = standardConstraints();
hcs.typeSpecs["class.RAM"] = ramSpecFunc;
hcs.typeSpecs["class.RAM_2"] = ram2SpecFunc;
Schedule s = scheduleInterface(f, hcs, interfaces, blocksToPipeline);
REQUIRE(s.numStates() == 7);
PipelineSpec spec{true, {*begin(blocksToPipeline)}};
//REQUIRE(map_find(*begin(blocksToPipeline), s.pipelineSchedules) == 1);
REQUIRE(map_find(spec, s.pipelineSchedules) == 1);
STG graph = buildSTG(s, f);
cout << "STG Is" << endl;
graph.print(cout);
REQUIRE(graph.pipelines.size() == 1);
REQUIRE(graph.pipelines[0].depth() == 5);
REQUIRE(graph.pipelines[0].II() == 1);
emitVerilog("loop_add_7", graph, hcs);
REQUIRE(runIVerilogTB("loop_add_7"));
}
TEST_CASE("Pipelining an array doing a[i] + 4, and exiting the pipeline in the TB, with a number of iterations small enough to never fill the pipeline") {
SMDiagnostic Err;
LLVMContext Context;
setGlobalLLVMContext(&Context);
std::unique_ptr<Module> Mod = loadCppModule(Context, Err, "loop_add_4");
setGlobalLLVMModule(Mod.get());
Function* f = getFunctionByDemangledName(Mod.get(), "loop_add_4");
getArg(f, 0)->setName("ram");
std::set<BasicBlock*> blocksToPipeline;
for (auto& bb : f->getBasicBlockList()) {
auto term = bb.getTerminator();
if (BranchInst::classof(term)) {
BranchInst* branch = dyn_cast<BranchInst>(term);
if (branch->isConditional()) {
for (auto succ : branch->successors()) {
if (succ == &bb) {
cout << "Found looped basic block" << endl;
blocksToPipeline.insert(&bb);
}
}
}
}
}
InterfaceFunctions interfaces;
interfaces.functionTemplates[string("read")] = implementRAMRead0;
interfaces.functionTemplates[string("write")] = implementRAMWrite0;
HardwareConstraints hcs = standardConstraints();
hcs.typeSpecs["class.RAM"] = ramSpecFunc;
hcs.typeSpecs["class.RAM_2"] = ram2SpecFunc;
Schedule s = scheduleInterface(f, hcs, interfaces, blocksToPipeline);
REQUIRE(s.numStates() == 7);
PipelineSpec spec{true, {*begin(blocksToPipeline)}};
//REQUIRE(map_find(*begin(blocksToPipeline), s.pipelineSchedules) == 1);
REQUIRE(map_find(spec, s.pipelineSchedules) == 1);
STG graph = buildSTG(s, f);
cout << "STG Is" << endl;
graph.print(cout);
REQUIRE(graph.pipelines.size() == 1);
REQUIRE(graph.pipelines[0].depth() == 5);
REQUIRE(graph.pipelines[0].II() == 1);
VerilogDebugInfo info;
info.wiresToWatch.push_back({false, 32, "global_state_dbg"});
info.debugAssigns.push_back({"global_state_dbg", "global_state"});
emitVerilog("loop_add_4", graph, hcs, info);
REQUIRE(runIVerilogTB("loop_add_4"));
}
// Issue: How do we express the need to set defaults on ports? We need to be
// able to express that the wen == 0 at the end of a RAM write is only a default
// value and should not be considered essential
TEST_CASE("Pipelining an array doing a[i] + 4, and exiting the pipeline in the TB, with a number of iterations large enough to fill the pipeline") {
SMDiagnostic Err;
LLVMContext Context;
setGlobalLLVMContext(&Context);
std::unique_ptr<Module> Mod =
loadCppModule(Context, Err, "loop_add_4_6_iters");
setGlobalLLVMModule(Mod.get());
InterfaceFunctions interfaces;
interfaces.functionTemplates[string("read_0")] = implementRAMRead0;
interfaces.functionTemplates[string("read_1")] = implementRAMRead1;
interfaces.functionTemplates[string("write_0")] = implementRAMWrite0;
Function* f = getFunctionByDemangledName(Mod.get(), "loop_add_4_6_iters");
getArg(f, 0)->setName("ram");
cout << "LLVM Function" << endl;
cout << valueString(f) << endl;
HardwareConstraints hcs = standardConstraints();
hcs.typeSpecs["class.RAM"] = ramSpecFunc;
hcs.typeSpecs["class.RAM_2"] = ram2SpecFunc;
std::set<BasicBlock*> blocksToPipeline = findPipelinedBlocks(f);
// Pipelined
ExecutionConstraints exec;
addDataConstraints(f, exec);
inlineWireCalls(f, exec, interfaces);
SchedulingProblem p = createSchedulingProblem(f, hcs, blocksToPipeline);
exec.addConstraints(p, f);
map<Function*, SchedulingProblem> constraints{{f, p}};
Schedule s = scheduleFunction(f, hcs, blocksToPipeline, constraints);
// Pipelined
REQUIRE(s.numStates() == 7);
PipelineSpec spec{true, {*(begin(blocksToPipeline))}};
REQUIRE(map_find(spec, s.pipelineSchedules) == 1);
//REQUIRE(map_find(*begin(blocksToPipeline), s.pipelineSchedules) == 1);
STG graph = buildSTG(s, f);
cout << "STG Is" << endl;
graph.print(cout);
REQUIRE(graph.pipelines.size() == 1);
REQUIRE(graph.pipelines[0].depth() == 5);
REQUIRE(graph.pipelines[0].II() == 1);
map<llvm::Value*, int> layout = {};
// ArchOptions options;
auto arch = buildMicroArchitecture(graph, layout, hcs);
VerilogDebugInfo info;
info.wiresToWatch.push_back({false, 32, "global_state_dbg"});
info.debugAssigns.push_back({"global_state_dbg", "global_state"});
emitVerilog("loop_add_4_6_iters", arch, info);
REQUIRE(runIVerilogTB("loop_add_4_6_iters"));
}
TEST_CASE("Using temporary memory") {
SMDiagnostic Err;
LLVMContext Context;
setGlobalLLVMContext(&Context);
std::unique_ptr<Module> Mod = loadCppModule(Context, Err, "loop_add_4_copy");
setGlobalLLVMModule(Mod.get());
Function* f = getFunctionByDemangledName(Mod.get(), "loop_add_4_copy");
assert(f != nullptr);
getArg(f, 0)->setName("ram");
InterfaceFunctions interfaces;
interfaces.functionTemplates[string("read")] = implementRAMRead0;
interfaces.functionTemplates[string("write")] = implementRAMWrite0;
interfaces.functionTemplates[string("read_0")] = implementRAMRead0;
interfaces.functionTemplates[string("read_1")] = implementRAMRead0;
interfaces.functionTemplates[string("write_0")] = implementRAMWrite0;
HardwareConstraints hcs = standardConstraints();
hcs.typeSpecs["class.RAM"] = ramSpecFunc;
hcs.typeSpecs["class.RAM_2"] = ram2SpecFunc;
Schedule s = scheduleInterface(f, hcs, interfaces);
STG graph = buildSTG(s, f);
cout << "STG Is" << endl;
graph.print(cout);
// Arch debug
VerilogDebugInfo info;
info.debugAssigns.push_back({"global_state_dbg", "global_state"});
info.wiresToWatch.push_back({false, 32, "global_state_dbg"});
emitVerilog("loop_add_4_copy", graph, hcs, info);
// runCmd("cat loop_add_4_copy.v");
// runCmd("cat RAM2.v");
// runCmd("cat loop_add_4_copy_tb.v");
REQUIRE(runIVerilogTB("loop_add_4_copy"));
}
TestBenchSpec buildTB(std::string name,
map<string, vector<int> >& memoryInit,
map<string, vector<int> >& memoryExpected,
map<string, int>& testLayout) {
TestBenchSpec tb;
tb.useModSpecs = true;
tb.memoryInit = memoryInit;
tb.memoryExpected = memoryExpected;
tb.runCycles = 200;
tb.name = name;
int startSetMemCycle = 1;
setRAM(tb, 1, "ram", memoryInit, testLayout);
int startRunCycle = startSetMemCycle + 10;
map_insert(tb.actionsInCycles, startRunCycle, string("rst_reg = 1;"));
map_insert(tb.actionsInCycles, startRunCycle + 1, string("rst_reg = 0;"));
int checkMemCycle = 150;
checkRAM(tb, checkMemCycle, "ram", memoryExpected, testLayout);
return tb;
}
TEST_CASE("Blur without linebuffering") {
SMDiagnostic Err;
LLVMContext Context;
setGlobalLLVMContext(&Context);
std::unique_ptr<Module> Mod =
loadCppModule(Context, Err, "blur_no_lb");
setGlobalLLVMModule(Mod.get());
Function* f = getFunctionByDemangledName(Mod.get(), "blur_no_lb");
getArg(f, 0)->setName("ram");
InterfaceFunctions interfaces;
interfaces.functionTemplates[string("read_0")] = implementRAMRead0;
interfaces.functionTemplates[string("read_1")] = implementRAMRead1;
interfaces.functionTemplates[string("read_2")] = implementRAMRead2;
interfaces.functionTemplates[string("write_0")] = implementRAMWrite0;
HardwareConstraints hcs = standardConstraints();
hcs.typeSpecs["class.RAM"] = ramSpecFunc;
hcs.typeSpecs["class.RAM_2"] = ram2SpecFunc;
hcs.typeSpecs["class.RAM_3"] = ram3SpecFunc;
Schedule s = scheduleInterface(f, hcs, interfaces);
STG graph = buildSTG(s, f);
VerilogDebugInfo info;
map<llvm::Value*, int> layout = {{getArg(f, 0), 0}}; //, {getArg(f, 1), 8}};
// ArchOptions options;
auto arch = buildMicroArchitecture(graph, layout, hcs);
addNoXChecks(arch, info);
//emitVerilog("blur_no_lb", graph, hcs);
emitVerilog("blur_no_lb", arch, info);
map<string, int> testLayout = {{"a", 0}, {"b", 8}};
map<string, vector<int> > memoryInit{{"a", {0, 1, 2, 3, 7, 5, 5, 2}}};
map<string, vector<int> > memoryExpected{{"b", {}}};
auto ma = map_find(string("a"), memoryInit);
for (int i = 1; i < 8 - 1; i++) {
map_insert(memoryExpected, string("b"), (ma[i - 1] + ma[i] + ma[i + 1]));
}
cout << "Expected values" << endl;
for (auto val : map_find(string("b"), memoryExpected)) {
cout << "\t" << val << endl;
}
TestBenchSpec tb = buildTB("blur_no_lb", memoryInit, memoryExpected, testLayout);
emitVerilogTestBench(tb, arch, testLayout);
REQUIRE(runIVerilogTB("blur_no_lb"));
}
TEST_CASE("Blur with linebuffering") {
SMDiagnostic Err;
LLVMContext Context;
setGlobalLLVMContext(&Context);
std::unique_ptr<Module> Mod = loadCppModule(Context, Err, "blur_lb");
setGlobalLLVMModule(Mod.get());
// HardwareConstraints hcs;
// hcs.setLatency(STORE_OP, 3);
// hcs.setLatency(LOAD_OP, 1);
// hcs.setLatency(CMP_OP, 0);
// hcs.setLatency(BR_OP, 0);
// hcs.setLatency(ADD_OP, 0);
// HardwareConstraints hcs = standardConstraints();
Function* f = getFunctionByDemangledName(Mod.get(), "blur_lb"); //Mod->getFunction("blur_lb");
assert(f != nullptr);
getArg(f, 0)->setName("ram");
InterfaceFunctions interfaces;
interfaces.functionTemplates[string("read")] = implementRAMRead0;
interfaces.functionTemplates[string("write")] = implementRAMWrite0;
HardwareConstraints hcs = standardConstraints();
hcs.typeSpecs["class.RAM"] = ramSpecFunc;
hcs.typeSpecs["class.RAM_2"] = ram2SpecFunc;
hcs.typeSpecs["class.RAM_3"] = ram3SpecFunc;
Schedule s = scheduleInterface(f, hcs, interfaces);
// Schedule s = scheduleInter
//Schedule s = scheduleFunction(f, hcs);
STG graph = buildSTG(s, f);
cout << "STG Is" << endl;
graph.print(cout);
//map<llvm::Value*, int> layout = {{getArg(f, 0), 0}, {getArg(f, 1), 8}};
map<llvm::Value*, int> layout;
// ArchOptions options;
auto arch = buildMicroArchitecture(graph, layout, hcs);
//auto arch = buildMicroArchitecture(graph, layout);
VerilogDebugInfo info;
addNoXChecks(arch, info);
info.wiresToWatch.push_back({false, 32, "global_state_dbg"});
info.wiresToWatch.push_back({false, 32, "wdata_temp_reg_dbg"});
info.debugAssigns.push_back({"global_state_dbg", "global_state"});
info.debugWires.push_back({true, 32, "num_clocks_after_reset"});
addAlwaysBlock({"clk"}, "if (rst) begin num_clocks_after_reset <= 0; end else begin num_clocks_after_reset <= num_clocks_after_reset + 1; end", info);
//emitVerilog(f, arch, info);
emitVerilog("blur_lb", graph, hcs); //, arch, info);
// Testbench specification