v0.12.0-esp32-20230221

Features:

• target: Added base support for ESP32-C6.
• target: Added base support for ESP32-H2.
• flash/esp: Added support for the detection of 32-256MB flash chips. See #245.
• flash/esp: Added possibility to control if binary needs to be written encrypted or not. Added encrypt option to program_esp command. program_esp_bins decides if the partition is encrypted or not based on flash_args.json. Previously the decision was based on the fuses' configuration only. Solves the problem described here.
• flash/esp: Added esp stub_log <on|off> command. This command controls if flasher stub log messages should be read and printed along with OpenOCD ones. It should be very useful for user issues diagnostics.
• driver/usb: Updated libusb to 1.0.26 in MacOS and Windows builts. It eliminates LIBUSB_ERROR_NOT_SUPPORTED error reported on Windows which actually did not break anything. See #255.
• flash/esp: Added extra warning messages for some flasher stub return codes. They are intended to avoid users' confusion described in #260 (comment)

Bug Fixes:

• flash/esp: Fixes PSRAM corruption by flasher stub on ESP32-S2/S3. Solves #264.
• rtos/FreeRTOS: decrease log level of uxTopUsedPriority read issue. This error is also reported when the chip is just reset and the app data segment is not mapped yet by the bootloader. To avoid user's confusion its log level was changed.
• target/xtensa: change the log level of Unexpected OCD_ID error. This error is also reported when single-core app is running on a multi-core chip (only one core is enabled). To avoid user confusion its log level was changed.
• target/esp_riscv: Corrects maximum breakpoints and watchpoints numbers per target for different chips

Other:

• openocd: Added cmake build support.
• jtag/drivers: esp32 gpio bitbang changed to use dedicated gpio driver. This should improve the performance of the esp32gpio bitbang driver.
• Synced with upstream at https://github.com/openocd-org/openocd/commits/master/85ae73de03ebcc723842b7978a6c94b73166f027.loaders/esp: convert return codes to warning messages

v0.11.0-esp32-20221026

Features:

• esp: Adds reset cause printing. Now message with reset cause for every core of the chip is printed in a numerical and human-readable format.
• esp/xtensa: Adds exception cause printing. Now message with the exception cause for Xtensa chips is printed in a numerical and human-readable format.
• esp32c2: Adds flash encryption support.
• rtos/nuttx: Adds ESP32-C3 support.
• rtos/nuttx: Adds ESP32-S2 support.
• rtos/nuttx: Adds ESP32-S3 support.
• Releases binaries with remote bitbang support enabled.

Bug fixes:

• Workarounds problem reported again in espressif/esp-idf#8065 (comment) by retrying memory read on failure. That problem led to "Step into" instead of "Step over" and other weird stuff like seemingly corrupting the stack during debugging.
• esp/xtensa: Allows reading internal ROM by default. This bug led to memory read errors when GDB tried to unwind backtraces containing ROM functions.
• esp/xtensa: Fixes data corruption on the first variable read. In some cases, this bug led to the reading of garbage data from memory.
• esp_usb_jtag: Sanity check to prevent possible buffer overflow at the output buffer
• esp/riscv: Filters out target halts caused normal debugging activities. This bug led to the message with exception reason printed on any target halt including those caused by normal debugging activities: breakpoints, stepping, manual program interruption by the user, etc.
• esp/riscv: Fixes watchpoints reconfiguration from target. This bug led to "HW watchpoints slots leaks" when the target program set/re-configured the watchpoint with the same ID several times.

Other:

• esp/xtensa: Rebased code base onto upstream Cadence generic Xtensa target implementation.
• Synchronized with upstream changes.
• Refactored for upstreaming patches.

v0.11.0-esp32-20220706

2022/07/06 Release, based on OpenOCD v0.11.0

Features:

• esp32c2: Adds generic support for ESP32-C2.
• esp32c3: Implements logging the reason of the reset. The reason is printed in numerical and human readable format.
• espxx: Implements soft_reset_halt command.
• esp/semihosting: Adds full support for ESP IDF VFS driver directory API.
• esp/flash: Adds no_clock_boost argument to program_esp and program_esp_bins commands. This can be helpful when users experience problems with flash programming. It forbids OpenOCD to modify (boost) CPU clock in order to speed up flashing.
• freertos: Adds support for qGetTLSAddr GDB packet. This fixes problem appeared on Xtensa targets when user tried to print TLS variable value in GDB.
• freertos: Enables reading some Xtensa registers for waiting tasks (e.g. threadptr). Zero values were returned before this change.
• freertos: Support Amazon FreeRTOS SMP port (available in IDF starting from IDF 5.0)
• doc: Updates description of Espressif-specific commands.

Bug fixes:

• esp32s3: call smp_target_init instead of single core init.
• rtos/esp32: Fixed AddressSanitizer heap-buffer-overflow issue when reading registers from ESP32 stack.
• xtensa: Invalidates register cache on reset. This could lead to writing to target old registers values after chip reset and could lead to unpredictable behavior.
• esp/flash: Fixed memory leaks in ESP flash driver reported by valgrind.

Other:

• Synchronized with upstream changes
• Refactored for upstreaming patches

v0.11.0-esp32-20220411

2022/04/11 Release, based on OpenOCD v0.11.0

Features:

• Synchronized with upstream.
• esp/ci: Added build for MacOS ARM64.
• esp-config: Added Espressif USB bridge board configs.
• esp/flash: Added octal flash support.
• esp/flash: Added MXIC 32MB flash chip support. Solves problem mention in #218.
• esp/freertos: Print FreeRTOS kernel version.
• esp/freertos: Read TCB_t offsets from ESP-IDF symbol table. This adds support for different TCB block layouts which can be caused by different FreeRTOS configurations.
• esp/semihosting: Refactored code and minimized arch-specific changes in common semihosting implementation.
• semihosting: Added 'arm semihosting_basedir' command. See description here

Bug fixes:

• xtensa: Call 'keep_alive during' register/memory restore to avoid gdb warning.
• esp32s3: Added automatic target reset upon GDB connection if memory protection is enabled (#190, #183, #176 (comment))
• esp/xtensa: Added support for proper Xtensa semihosting break instruction. According to Xtensa spec 'break 1,14' should be used for semihosting calls. This will be fixed in IDF soon too.
• target/esp: Fixed ESP32-S2 & S3 IROM region boundaries. It could lead to ROM debugging problems.
• esp_riscv: Fix SBA access alignment for size < sba_access_size.

v0.11.0-esp32-20211220

2021/12/20 Release, based on OpenOCD v0.11.0

Features:

• Merge with upstream. Bump version to v0.11.0. This also closes a couple of issues: #198, #199, and #196
• esp/riscv: Add flash breakpoints support for Espresif RISCV chips. Currently, only ESP32-C3 is supported.
• jtag/esp_usb: Add Espressif USB bridge support

Bug fixes:

• esp/flash: Add check for a maximum number of flash mappings. Prevent flash driver crash when flasher stub returns garbage upon flash mappings request.
• esp32s3/esp_usb_jtag: Dummy jtag call before running an algorithm. It works around the problem on ESP32-S3 when USB JTAG device gets stuck after running flasher stub algorithm. That problem leads to a flash probing problem upon GDB connection or any other flash access command.
• jtag/esp_usb: Check if USB device handle is valid before close
• esp32s3: Add missed irom_mask_low mem region to the config.
• rtos: Fix heap usage after free during rtos_destroy
• esp_apptrace: Restart idle timeout after target reconnection. That could lead to data timeout error after target reset during tracing.

v0.10.0-esp32-20211111

2021/11/11 Release, based on OpenOCD v0.10.0

Features:

• flash/esp32s3: Added ESP32-S3 flash support (#178 (comment)). Access to chip's flash is supported including setting breakpoints there.
• esp/riscv: Added coverage data collection support for Espressif RISCV chips. Currently this functionality is verified for ESP32-C3 only.
• esp_usb_jtag: Added ability to filter out USB device by product serial. Now it is possible to specify which USB device should be used by command espusbjtag serial <serial_num>.

Bug fixes:

• esp32s2-c3: Added automatic target reset upon GDB connection if memory protection is enabled (#190, #183, #176 (comment)).
• esp32c3: Avoided missing chip reset due to problems with dmi_scan. This led to the problem when SW breakpoints and syscalls do not work.
• esp32c3: Enables ebreaks in 'FLASH_BOOT' mode only. This led to the problem with flashing esp32c3 over UART with connected OpenOCD.
• flash/esp: Added detection of unexpected target algorithm exit during a flash read/write. Now the error message is printed if flash stub invocation ended up accidentally.
• flash/esp: Fixed cache flush in flasher stub for esp32s2/esp32c3. This problem led to partial data writes to flash.
• esp_usb_jtag: Added USB device re-enumeration in case of data transfer problem (#176, #178). This problem led to built-in USB-JTAG getting stuck after HW reset.
• esp_usb_jtag: Made tx/rx routines a bit more responsive and reliable. Added several attempts to tx/rx data in of failure.
• esp32s2-s3: Added power config register reset to prevent getting stuck in soft reset. This problem led to application getting stuck after resetting the target with reset run.
• esp32c3: Fixed WDT reset issue while waiting for resume after soft reset. This problem led to application getting stuck after resetting the target with reset run.
• esp_remote: Fixed runtest function. This problem was causing error during ESP32-C3 examination.
• gdb_server: Fixed registers access error reporting. Now it is controlled by gdb_report_register_access_error command. This problem led to RISCV GDB register access reporting and when GDB register packet is received when target is running.
• algorithm: Fixed cleaning up algorithm data upon failure.
• algorithm: Fixed '.data' and '.bss' section size alignment to avoid possible data corruption when running algorithms.

v0.10.0-esp32-20210902

2021/09/02 Release, based on OpenOCD v0.10.0

Features:

• esp_remote: New command to set JTAG clock freqency

Bug fixes:

• esp_xtensa_smp: Fixes problem when APP CPU is left unexamined after target is reset externally by esptool.py (#160)
• esp_xtensa_smp: Fixes TRAX tracing start on one core only
• xtensa: Fixes memory leak in TRAX tracing dump command handler
• algorithm: Skip loading sections with zero size. This led to the algoritm run failure when algorithm image has zero-sized sections.

v0.10.0-esp32-20210721

2021/07/21 Release, based on OpenOCD v0.10.0

Features:

• esp32s3: Added base support for the latest ESP32-S3 chip revision. It includes base debugging support w/o flash support and other features.
• tcl/esp32s3: Added esp_get_mac support for ESP32-S3.
• esp32c3: Added separate target for ESP32-C3 chip. Now ESP32-C3 has its own target implemented basing on RISCV one. Thsi allows to keep ESP32-C3 specific features in separate module and minimize modification to base RISCV target.
• esp/apptrace/esp32c3: Added application level tracing support for ESP32-C3.
• algorithm/esp32c3: Added support for running algorithms on ESP32-C3.
• flash/esp32c3: Added flash support for ESP32-C3 (#165).
• riscv: Added command to mask IRQ during stepping. Implemented ARM-like command to control how IRQs are controlled during stepping. Currently to modes are supported: off and steponly.
• riscv: Implemented batch JTAG ops for memory read. Combined JTAG operations into batches to speed up memory reads.
• riscv: Emulated 8-/16-bit memory access via SBA using 32-bit read/write. SBA mode allows to access memory on running target. When 8-/16-bit memory accesses via SBA are not supported they are emulated via 32-bit ones if it is possible.
• loaders/esp: Added encrypted flash support for esp32, esp32s2 and esp32c3.
• loaders/esp: Added command to enable/disable CPU clock boosting when flasher stub is running on target. This allows to increase flash programing speed significantly.
• loaders/esp: Enable by default CPU clock boosting when programming via program_esp. Clock can be restored after flashing when restore_clock option is specified.
• loaders/esp: Added command esp verify_bank_hash to verify flash uploads using sha256 hash.
• esp: Added Espressif USB JTAG/serial debug unit and USB Bridge udev rules.
• esp: Added release binaries signing for MacOS.

Bug fixes:

• riscv: Disabled watchpoints on stepping to avoid watchpoint re-triggering.
• tcl/esp: Added check for flash support before running program_esp to provide clearer error reasoning for users (#165 (comment)).
• freertos: Made threads list updating tolerant to list reading errors.
• target/riscv: Added get_gdb_arch target API implementation to avoid GDB errors when riscv arch is not exactly specifed (#144 (comment)).
• esp32c3: Call rtos post_reset_cleanup method after reset to clear RTOS data (#144).
• riscv: Avoided increasing dmi_busy_delay due to garbage data received by dmi_scan during chip reset. Thsi allows to avoid unnecessary and abnormal increasin of dmi_busy_delay leading to quite slow JTAG communication after several target resets.
• esp/apptrace: Added target connection status check while polling for apptrace data (#149). This allows to avoid apptrace data losing due to target reset.
• target/{esp32s2,esp32s3,esp32c3}: Disabled SWD on reset or halt (#153).
• jtag_esp_remote: Added several fixes of the ESP Remote protocol JTAG driver.
• esp_usb_jtag: Fixed stack overflow. This prevents OpenOCD crashing or stucking in infinite loop when started w/o connected device.
• esp: Fixed files paths typo in boards description file.

v0.10.0-esp32-20210401

2020/04/01 Release, based on OpenOCD v0.10.0

Bug fixes:

• Add missing zlib DLL into Windows release package (#151)

v0.10.0-esp32-20210329

2021/03/29 Release, based on OpenOCD v0.10.0

Features

• flash/esp_xtensa: Added compression support for write operations. Compression can be enabled by adding compress argument to program_esp command. Compression is not enabled by default, yet.
• rtos/FreeRTOS: Changed task list update algorithm basing on uxTaskNumber. This reduces the amount of data transferred over JTAG in some cases, and makes stepping through the code faster.
• target/esp32c3: Added SoC reset support. reset halt command now resets the digital peripherals, in addition to the CPU, same as it does on esp32 and esp32s2.
• target/esp32c3: Reduced timeouts to reasonable values
• board/esp32c3-ftdi: set lower JTAG clock used by default. Since there is no development board with FT2232H and ESP32-C3 yet, they are most likely connected by jumper cables, so a lower frequency should be used.
• xtensa: Made 'xtensa_smpbreak_get' returning configured value

Bug fixes:

• esp32s3: Disabled flash support by default, since it's not implemented yet. It will be re-enabled once the feature is implemented.
• esp/semihost: Added callback to disable WDTs upon syscall.
• riscv: Maintain target halted state across reset
• riscv: Fixed RTOS checks in reset procedure
• riscv: Fixed semihosting code to adjust the PC to the next instruction also for GDB fileio
• esp/gcov: Ensured that esp gcov dump is run on examined target
• esp/gcov: Fixed acknowledgement of the block with command w/o response data
• esp/gcov: Halt target before on-the-fly gcov dump
• semihosting: Fixed file name length parameter for GDB File IO to match GDB docs.
• xtensa: Marked target as unexamined when 'powered' bit is reset during several polling periods.
• In this release we have stared running the test suite with sanitizers (AddressSanitizer, UndefinedBehaviorSanitizer) enabled, and fixed the following issues:
  • target/esp_xtensa_apptrace: Fixed 'unaligned buffer' issue
  • esp32s2: Fixed left shift runtime errors found by sanitizers
  • gdb_server: Fixed AdressSanitizer issue caused by missing null character
  • xtensa: Fixed sanitizer warnings when shifting integer constants
  • xtensa: Fixed buffer overflow due to incorrect size allocated for wide user registers
  • xtensa: Fixed buffer overflow when reading trace data