Verilog rules in prelude

[rzig]

Hey! I've been working on some hardware dev in Buck2 over the last several months and have built up a set of Verilog rules + rules for associated tools like Verilator. I'm not entirely sure of the process of adding things to the prelude, but I'd be interested in contributing these if there's interest.

[cormacrelf]

I would recommend making a repo that works when loaded as an external cell. A very big advantage of external cells is that you don't need to go through review here to push tweaks. Not to be underestimated. And for users of the rules, they don't have to update prelude + buck2 to get those tweaks. Ultimately this is the lowest friction option. I don't think Meta is saying no to new prelude rules, but I think this way just works better.

There are rules repos out there like https://github.com/benbrittain/oci-rules, and others at the buck2 topic on github. There should probably be a buck2 documentation page to make these a bit more discoverable.

[mrkmndz]

Hi @rzig! I'm from a DevInfra team at Meta that supports ASIC engineers with things like Verilog. I'd be happy to review the rules that you've put together and then we can advise you on what the best home for them would be.

To get started, you could either put up a PR against the prelude, or just share a repo where you have them written out.

cc @get9