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Copy pathscratch
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scratch
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Signals:
Clocks: trigger things on rise/fall edge, have a clock tree / clock domain, can't be directly driven by a listener but can eg depend on the state of some other signal
Busses: Sample / drive at a point, maybe have pull up / pull down set so driving it only affects it in the relevant way eg driving 0 when something else is driving 1 might not do anything
Interrupts: Kind of like a clock, has a trigger?
Network: Model propagation delay somehow?
Clocked vs combinatorial stuff?
---
A = top
B = side
or
|0 1
-+-----
0|0 1
|
1|1 1
nor
|0 1
-+-----
0|1 0
|
1|0 0
orn
|0 1
-+-----
0|1 1
|
1|1 0
Current status: So ⌜orn⌝ is ⌜⊃⌝.
and
|0 1
-+-----
0|0 0
|
1|0 1
andn
|0 1
-+-----
0|0 1
|
1|0 0
All 16 binary logical ops: l r dest
Add, sub
integer signed, integer unsigned
36 bit, 32 bit zeroing high, 32 bit preserve high, 32 bit flags (sat/carry) high, 2 × packed 16 bit flags high, 4 × 8 packed bit flags high
saturating
and also
add, sub
fp signed
36 bit, 32 bit flags high, 32 bit zeroing high, 32 bit preserve high
saturating
mul, div
integer signed, integer unsigned, fp signed
36 bit, 32 bit zeroing high, 32 bit flags high
saturating
jumps
set jump priority queue on unstall dest1 dest2 dest3
try jumps if unstalled: dest1 dest2 dest3
jump if equal: l r dest
jump if not equal: l r dest
jump if eq imm: imm src dest
bitops
popcnt
roll
ror
4 way instruction
select l r choice_also_dest
fma a b c_and_dest
---
banana todo
4 major instruction format kinds
Format 0: 000000 0000000000 0000000000 [opcode_0place; 10]
Format 1: 000000 0000000000 [opcode_1place; 10] [address1; 10]
Format 2-full: 000000 0 [opcode_2place_full; 9] [address1; 10] [address2; 10]
Format 2-imm: 000000 1 [opcode_2place_imm; 4] [imm; 5] [address1; 10] [address2; 10]
Format 3: [opcode_3place; 6] [address1; 10] [address2; 10] [address3; 10]
where opcode_{1,2,3}place is nonzero.
Up to 1024 format 0 instructions
Up to 1023 format 1 and 2 instructions
31 format 3 instructions
Format 3:
8 × logic: Nor, Material Nonimplication, XOR, NAND, AND, XNOR, Material Conditional, OR
x × arithmetic: ???
y × jumps
z × bitmanip: grev
Format 2-full:
3 × logic with mask: bitset (eg T with mask), bitunset (eg F with mask), bitflip (eg ¬ with mask)
3 × logic: ¬, = (eg copy), ←→ (eg swap)
Format 2-imm:
rotate left/right, shift left right with fill 0/1,
shuffle
unshuffle
Format 1:
2 × logic: T, F
---
lotus chip
banks in addition to channel IO
8 bits of direct addressing. 32-bit words, word addressable.
16 segments of 16 words.
15 banks, with bank 0 meaning 'whatever bank is currently selected'.
7 major instruction format kinds
Format 0: 0000000 0 00000000 00000000 [opcode_0place; 8] (256)
Format 1-full: 0000000 0 00000000 1 [opcode_1place; 7] [address1; 8] (128)
Format 1-imm 0000000 0 00000000 0 [opcode_1place; 7] [imm; 8] (127)
Format 2-full: 0000000 0 000 [opcode_2place_full; 5] [address1; 8] [address2; 8] (31)
Format 2-imm: 0000000 [opcode_2place_imm; 4] [imm; 5] [address1; 8] [address2; 8] (15)
Format 3-full: 1 [opcode_3place; 7] [address1; 8] [address2; 8] [address3; 8] (127)
Format 3-imm: 0 [opcode_3place; 7] [address1; 8] [address2; 8] [address3; 8] (126)
Format 0:
Nop
Halt
Sleep
Format 1-full:
3 × logic direct: T, F, ¬
Instructions with unconditional/unless stall variants:
- Jump
- Bank switching indirect, where the cell at the address has segment:bank in the lower 8 bits
- Execute the instruction at %address without changing PC
Format 1-imm:
Bank switching, where the arg is 4 bits of segment and 4 bits of bank (with bank 0 being ...)
Format 2-imm:
roli, rori, shl0i, shl1i, shr0i, shr1i, grevi, shuffle, unshuffle
Format 2-full:
3 × logic with mask: bitset (eg T with mask), bitunset (eg F with mask), bitflip (eg ¬ with mask)
3 × logic: ¬, = (eg copy), ←→ (eg swap)
Format 3-full:
a × bitops: grev, pdep+pext (for bitfields), ror/rol/shr0/shl0/shr1/shl1
8 × logic: Nor, Material Nonimplication, XOR, NAND, AND, XNOR, Material Conditional, OR
x × arithmetic: ???
y × jumps
Format 3-imm:
x × bitops: grevi, rori/roli/shr0i/shl0i/shr1i/shl1i
cmovs
bank switching:
---
Ram very small processor - bean chip
array of lines of cells
2 × buffer line
executor can read a line into a buffer, write a buffer into a line, perform an op on either one or both buffers (potentially with an immediate), write a buffer or a segment of a buffer out to the fabric, or load a buffer or segment of a buffer from the fabric
ops = logic, shifts/rotates/funnels, masks
---
(A: bitmask) OP (B: memory)
Bit set: send bitmask (all zeros except for bits to set) + OR
Bit unset:
- send bitmask (all zeros except for bits to clear) + Xq (which is ((¬A) ∧ B))
- send bitmask (all ones except for bits to clear) + AND
Bit flip: send bitmask (all zeros except for bits to flip) + XNOR
B 0 1
A
0 0 1
1 1 0