DCM_1x_2x.vhd

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-- Copyright (c) 1995-2003 Xilinx, Inc.
-- All Right Reserved.
--------------------------------------------------------------------------------
--   ____  ____ 
--  /   /\/   / 
-- /___/  \  /    Vendor: Xilinx 
-- \   \   \/     Version : 6.3.02i
--  \   \         Application : 
--  /   /         Filename : DCM_1x_2x.vhd
-- /___/   /\     Timestamp : 11/03/2004 08:56:04
-- \   \  /  \ 
--  \___\/\___\ 
--
--Command: 
--Design Name: DCM_1x_2x
--
-- Module DCM_1x_2x
-- Generated by Xilinx Architecture Wizard
-- Written for synthesis tool: XST

library ieee;
use ieee.std_logic_1164.ALL;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.ALL;
library unisim;
use unisim.vcomponents.ALL;

entity DCM_1x_2x is
   port ( CLKIN_IN        : in    std_logic; 
          RST_IN          : in    std_logic; 
          CLKIN_IBUFG_OUT : out   std_logic; 
          CLK0_OUT        : out   std_logic; 
          CLK2X_OUT       : out   std_logic; 
          LOCKED_OUT      : out   std_logic);
end DCM_1x_2x;

architecture Synth of DCM_1x_2x is
   signal CLKFB_IN        : std_logic;
   signal CLKIN_IBUFG     : std_logic;
   signal CLK0_BUF        : std_logic;
   signal CLK2X_BUF       : std_logic;
   signal GND             : std_logic_vector (6 downto 0);
   signal GND1            : std_logic_vector (15 downto 0);
   signal GND2            : std_logic;
   
begin
   GND(6 downto 0) <= "0000000";
   GND1(15 downto 0) <= "0000000000000000";
   GND2 <= '0';
   CLKIN_IBUFG_OUT <= CLKIN_IBUFG;
   CLK0_OUT <= CLKFB_IN;
   CLKIN_IBUFG_INST : IBUFG
      port map (I=>CLKIN_IN,      
                O=>CLKIN_IBUFG);
   
   CLK0_BUFG_INST : BUFG
      port map (I=>CLK0_BUF,      
                O=>CLKFB_IN);
   
   CLK2X_BUFG_INST : BUFG
      port map (I=>CLK2X_BUF,      
                O=>CLK2X_OUT);
   
   DCM_ADV_INST : DCM_ADV
   generic map( CLK_FEEDBACK => "1X",
            CLKDV_DIVIDE => 2.000000,
            CLKFX_DIVIDE => 1,
            CLKFX_MULTIPLY => 4,
            CLKIN_DIVIDE_BY_2 => FALSE,
            CLKIN_PERIOD => 4.000000,
            CLKOUT_PHASE_SHIFT => "NONE",
            DCM_PERFORMANCE_MODE => "MAX_SPEED",
            DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
            DFS_FREQUENCY_MODE => "HIGH",
            DLL_FREQUENCY_MODE => "HIGH",
            DUTY_CYCLE_CORRECTION => TRUE,
            PHASE_SHIFT => 0,
            STARTUP_WAIT => FALSE,
            FACTORY_JF => x"F0F0")
      port map (CLKFB=>CLKFB_IN,      
                CLKIN=>CLKIN_IBUFG,      
                DADDR(6 downto 0)=>GND(6 downto 0),      
                DCLK=>GND2,      
                DEN=>GND2,      
                DI(15 downto 0)=>GND1(15 downto 0),      
                DWE=>GND2,      
                PSCLK=>GND2,      
                PSEN=>GND2,      
                PSINCDEC=>GND2,      
                RST=>RST_IN,      
                CLKDV=>open,      
                CLKFX=>open,      
                CLKFX180=>open,      
                CLK0=>CLK0_BUF,      
                CLK2X=>CLK2X_BUF,      
                CLK2X180=>open,      
                CLK90=>open,      
                CLK180=>open,      
                CLK270=>open,      
                DO=>open,      
                DRDY=>open,      
                LOCKED=>LOCKED_OUT,      
                PSDONE=>open);
   
end Synth;