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weiyu-chenZuul
weiyu-chen
authored and
Zuul
committed
Remove all references to MRF as they have been obsolete for years now.
Change-Id: Ia236e7f99102c697f05c199f5bda6e1c28e68f2b
1 parent e932ed8 commit 0efaaf9

18 files changed

+379
-428
lines changed

‎visa/BinaryEncoding.cpp

-9
Original file line numberDiff line numberDiff line change
@@ -42,7 +42,6 @@ using namespace vISA;
4242
// should never invoke the jitter twice with different platform strings.
4343
unsigned long bitsFlagSubRegNum[] = {128, 128};
4444
unsigned long bitsNibCtrl[] = {128, 128};
45-
unsigned long bitsMrfRegNumHWord[] = {128, 128};
4645
unsigned long bits3SrcFlagSubRegNum[] = {128, 128};
4746
unsigned long bits3SrcSrcType[] = {128, 128};
4847
unsigned long bits3SrcDstType[] = {128, 128};
@@ -2567,14 +2566,6 @@ inline BinaryEncoding::Status BinaryEncoding::EncodeOperandSrc2(G4_INST* inst)
25672566
return SUCCESS;
25682567
}
25692568

2570-
void SetMrfRegNumHWord(BinInst *mybin, uint32_t value)
2571-
{
2572-
if( mybin->GetIs3Src() )
2573-
return;
2574-
else
2575-
mybin->SetBits(bitsMrfRegNumHWord[0], bitsMrfRegNumHWord[1], value);
2576-
}
2577-
25782569
void SetExtMsgDescr(G4_INST *inst, BinInst *mybin, uint32_t value)
25792570
{
25802571

‎visa/BinaryEncoding.h

-2
Original file line numberDiff line numberDiff line change
@@ -636,7 +636,6 @@ typedef union _EncExtMsgDescriptor_
636636
// these will be set dynamically once
637637
extern unsigned long bitsFlagSubRegNum[2];
638638
extern unsigned long bitsNibCtrl[2];
639-
extern unsigned long bitsMrfRegNumHWord[2];
640639
extern unsigned long bits3SrcFlagSubRegNum[2];
641640
extern unsigned long bits3SrcSrcType[2];
642641
extern unsigned long bits3SrcDstType[2];
@@ -762,7 +761,6 @@ namespace vISA
762761
SET_BIT_RANGE(bitsFlagRegNum, 33, 33);
763762
SET_BIT_RANGE(bitsFlagSubRegNum, 32, 32);
764763
SET_BIT_RANGE(bitsNibCtrl, 11, 11);
765-
SET_BIT_RANGE(bitsMrfRegNumHWord, 76, 69); // MRF is not used
766764
SET_BIT_RANGE(bits3SrcFlagSubRegNum, 32, 32);
767765
SET_BIT_RANGE(bits3SrcFlagRegNum, 33, 33);
768766
SET_BIT_RANGE(bits3SrcSrcType, 45, 43);

‎visa/BuildIR.h

+1-1
Original file line numberDiff line numberDiff line change
@@ -1808,7 +1808,7 @@ class IR_Builder {
18081808
bool is_sendc);
18091809

18101810
// helper functions
1811-
G4_Declare *Create_MRF_Dcl( unsigned num_elt, G4_Type type );
1811+
G4_Declare *createSendPayloadDcl( unsigned num_elt, G4_Type type );
18121812
void Create_MOVR0_Inst(
18131813
G4_Declare* dcl,
18141814
short refOff,

‎visa/BuildIRImpl.cpp

+21-22
Original file line numberDiff line numberDiff line change
@@ -1177,12 +1177,12 @@ G4_InstSend *IR_Builder::Create_SplitSend_Inst_For_RTWrite(G4_Predicate *pred,
11771177
option, msgDesc, extDescOpnd);
11781178
}
11791179

1180-
// create a dcl for MRF, size in UD is given
1181-
G4_Declare* IR_Builder::Create_MRF_Dcl( unsigned num_elt, G4_Type type )
1180+
// create a declare for send payload
1181+
G4_Declare* IR_Builder::createSendPayloadDcl( unsigned num_elt, G4_Type type )
11821182
{
11831183
const char* name = getNameString(mem, 16, "M%u", ++num_general_dcl);
1184-
unsigned short numRow = ( num_elt * G4_Type_Table[type].byteSize - 1 ) / GENX_MRF_REG_SIZ + 1;
1185-
unsigned short numElt = ( numRow == 1 ) ? num_elt : (GENX_MRF_REG_SIZ/G4_Type_Table[type].byteSize);
1184+
unsigned short numRow = ( num_elt * G4_Type_Table[type].byteSize - 1 ) / GENX_GRF_REG_SIZ + 1;
1185+
unsigned short numElt = ( numRow == 1 ) ? num_elt : (GENX_GRF_REG_SIZ/G4_Type_Table[type].byteSize);
11861186
G4_Declare *dcl = createDeclareNoLookup(
11871187
name,
11881188
G4_GRF,
@@ -1191,7 +1191,7 @@ G4_Declare* IR_Builder::Create_MRF_Dcl( unsigned num_elt, G4_Type type )
11911191
type);
11921192
return dcl;
11931193
}
1194-
// create mov(8) mrf, r0
1194+
11951195
void IR_Builder::Create_MOVR0_Inst( G4_Declare* dcl, short regOff, short subregOff, bool use_nomask )
11961196
{
11971197
G4_DstRegRegion dst1(
@@ -1273,8 +1273,8 @@ void IR_Builder::Create_MOV_Inst(
12731273
0 );
12741274
}
12751275

1276-
// create multiple MOV inst for send src --> MRF if there are more than 64 byte data in src.
1277-
// dcl: decl for MRF
1276+
// send payload preparation.
1277+
// dcl: decl for send payload
12781278
// num_dword: number of DW to send
12791279
// src_opnd: send src, its size may be several GRFs
12801280
void IR_Builder::Create_MOV_Send_Src_Inst(
@@ -1303,7 +1303,7 @@ void IR_Builder::Create_MOV_Send_Src_Inst(
13031303
if( scalar_src && src_opnd->getType() != Type_UD ){
13041304
// change the type of dst dcl to src type
13051305
remained_dword = num_dword * ( G4_Type_Table[Type_UD].byteSize/G4_Type_Table[src_opnd->getType()].byteSize );
1306-
dst_dcl = Create_MRF_Dcl(remained_dword, src_opnd->getType());
1306+
dst_dcl = createSendPayloadDcl(remained_dword, src_opnd->getType());
13071307
dst_dcl->setAliasDeclare( dcl, regoff * G4_GRF_REG_NBYTES + subregoff * G4_Type_Table[Type_UD].byteSize );
13081308
dst_regoff = 0;
13091309
dst_subregoff = 0;
@@ -1343,7 +1343,6 @@ void IR_Builder::Create_MOV_Send_Src_Inst(
13431343
{
13441344
if( remained_dword >= 32 )
13451345
{
1346-
// mov(16) mrf src
13471346
execsize = 32;
13481347
}
13491348
else if( remained_dword >= 16 )
@@ -1369,7 +1368,6 @@ void IR_Builder::Create_MOV_Send_Src_Inst(
13691368
{
13701369
if( remained_dword >= 16 )
13711370
{
1372-
// mov(16) mrf src
13731371
execsize = 16;
13741372
}
13751373
else if( remained_dword >= 8 )
@@ -1425,30 +1423,31 @@ void IR_Builder::Create_MOV_Send_Src_Inst(
14251423
true );
14261424

14271425
// update offset in decl
1428-
if( remained_dword >= execsize ){
1426+
if (remained_dword >= execsize) {
14291427
remained_dword -= execsize;
1430-
if( execsize * dst_dcl->getElemSize() == 2 * G4_GRF_REG_NBYTES ){
1431-
// mov(16) mrf src
1428+
if (execsize * dst_dcl->getElemSize() == 2 * G4_GRF_REG_NBYTES) {
14321429
dst_regoff += 2;
1433-
if( !scalar_src ){
1430+
if (!scalar_src) {
14341431
src_regoff += 2;
14351432
}
1436-
}else if( execsize * dst_dcl->getElemSize() == G4_GRF_REG_NBYTES ){
1433+
}
1434+
else if (execsize * dst_dcl->getElemSize() == G4_GRF_REG_NBYTES) {
14371435
dst_regoff += 1;
1438-
if( !scalar_src ){
1436+
if (!scalar_src) {
14391437
src_regoff += 1;
14401438
}
1441-
}else{
1439+
}
1440+
else {
14421441
dst_subregoff += execsize;
1443-
if( dst_subregoff > (G4_GRF_REG_NBYTES/dst_dcl->getElemSize()) ){
1442+
if (dst_subregoff > (G4_GRF_REG_NBYTES / dst_dcl->getElemSize())) {
14441443
dst_regoff++;
1445-
dst_subregoff -= G4_GRF_REG_NBYTES/dst_dcl->getElemSize();
1444+
dst_subregoff -= G4_GRF_REG_NBYTES / dst_dcl->getElemSize();
14461445
}
1447-
if( !scalar_src ){
1446+
if (!scalar_src) {
14481447
src_subregoff += execsize;
1449-
if( src_subregoff > (short)(G4_GRF_REG_NBYTES/G4_Type_Table[Type_UD].byteSize) ){
1448+
if (src_subregoff > (short)(G4_GRF_REG_NBYTES / G4_Type_Table[Type_UD].byteSize)) {
14501449
src_regoff++;
1451-
src_subregoff -= G4_GRF_REG_NBYTES/G4_Type_Table[Type_UD].byteSize;
1450+
src_subregoff -= G4_GRF_REG_NBYTES / G4_Type_Table[Type_UD].byteSize;
14521451
}
14531452
}
14541453
}

‎visa/CISA.l

+1-1
Original file line numberDiff line numberDiff line change
@@ -890,7 +890,7 @@ V0 {
890890
return FENCE_OPTIONS;
891891
}
892892

893-
[ \n\t]+"\\"\n {TRACE("\n** Multiple instructions in a line");} //gen4 define macro use "\n" to allow multiple instr in a line
893+
[ \n\t]+"\\"\n {TRACE("\n** Multiple instructions in a line");}
894894

895895
'<EOF>' {
896896
TRACE("\n** End Of File");

‎visa/FlowGraph.cpp

+2-19
Original file line numberDiff line numberDiff line change
@@ -363,22 +363,6 @@ bool FlowGraph::matchBranch(int &sn, INST_LIST& instlist, INST_LIST_ITER &it)
363363
}
364364
else if (inst->opcode() == G4_endif)
365365
{
366-
// For GT, if/else/endif are different from Gen4:
367-
// (1). if - endif
368-
// if endif_label
369-
// ...
370-
// endif_label:
371-
// endif
372-
// (2). if - else - endif
373-
// if else_label
374-
// ...
375-
// else endif_label
376-
// else_label:
377-
// ...
378-
// endif_label: // this is different from Gen4
379-
// endif
380-
//
381-
382366
if (elseCount == 0) // if-endif case
383367
{
384368
// insert endif label
@@ -784,8 +768,7 @@ void FlowGraph::constructFlowGraph(INST_LIST& instlist)
784768
}
785769
else
786770
{
787-
MUST_BE_TRUE1(false, i->getLineNo(),
788-
ERROR_INVALID_G4INST); // not yet handled
771+
assert(false && "should not reach here");
789772
}
790773
} // need edge
791774
curr_BB = next_BB;
@@ -3802,7 +3785,7 @@ void G4_BB::addEOTSend(G4_INST* lastInst)
38023785
// mov (8) r1.0<1>:ud r0.0<8;8,1>:ud {NoMask}
38033786
// send (8) null r1 0x27 desc
38043787
IR_Builder* builder = parent->builder;
3805-
G4_Declare *dcl = builder->Create_MRF_Dcl(NUM_DWORDS_PER_GRF, Type_UD);
3788+
G4_Declare *dcl = builder->createSendPayloadDcl(NUM_DWORDS_PER_GRF, Type_UD);
38063789
G4_DstRegRegion* movDst = builder->Create_Dst_Opnd_From_Dcl(dcl, 1);
38073790
G4_SrcRegRegion* r0Src = builder->Create_Src_Opnd_From_Dcl(
38083791
builder->getBuiltinR0(), builder->getRegionStride1());

‎visa/Gen4_IR.hpp

+2-6
Original file line numberDiff line numberDiff line change
@@ -1529,7 +1529,7 @@ class G4_InstIntrinsic : public G4_INST
15291529
void setTmpFlagStart(int startFlag) { tmpFlagStart = startFlag; }
15301530
};
15311531
}
1532-
// see Gen4 Spec
1532+
15331533
// RegionWH and RegionV are special for the different modes of source register indirect addressing
15341534
// RegionWH = <width, horzStride>, we set vertStride to UNDEFINED_SHORT
15351535
// RegionV = <horzStride>, we set both vertStride and width to UNDEFINED_SHORT
@@ -3042,11 +3042,7 @@ enum ChannelEnable {
30423042

30433043
namespace vISA
30443044
{
3045-
//
3046-
// look up Gen4 ISA summary
3047-
// <DstReg><DstRegion><WriteMask><DstType>
3048-
// for both direct and indirect dst regions
3049-
//
3045+
30503046
class G4_DstRegRegion final : public G4_Operand
30513047
{
30523048
friend class IR_Builder;

‎visa/GraphColor.cpp

+10-11
Original file line numberDiff line numberDiff line change
@@ -28,7 +28,6 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
2828
#include "FlowGraph.h"
2929
#include "GraphColor.h"
3030
#include "SpillCode.h"
31-
#include "SpillManagerGMRF.h"
3231
#include <list>
3332
#include <iostream>
3433
#include <sstream>
@@ -4970,7 +4969,7 @@ void GraphColor::computeSpillCosts(bool useSplitLLRHeuristic)
49704969
// Also ARF live ranges with exclusively sequential references within the code are
49714970
// assigned an infinite spill cost as spilling them will not lower the register
49724971
// pressure in the region they are referenced. This does not necessarily hold for
4973-
// GRF/MRF live ranges are these are potentially large in size but the portions
4972+
// GRF live ranges are these are potentially large in size but the portions
49744973
// accessed by each sequential use are limited to 2 registers for general instructions
49754974
// and 8 registers for SEND instructions.
49764975
//
@@ -5901,8 +5900,8 @@ bool GraphColor::regAlloc(bool doBankConflictReduction,
59015900
}
59025901
}
59035902
//
5904-
// assign registers for GRFs/MRFs, GRFs are first attempted to be assigned using round-robin and if it fails
5905-
// then we retry using a first-fit heuristic; for MRFs we always use the round-robin heuristic
5903+
// assign registers for GRFs, GRFs are first attempted to be assigned using round-robin and if it fails
5904+
// then we retry using a first-fit heuristic.
59065905
//
59075906
if (liveAnalysis.livenessClass(G4_GRF))
59085907
{
@@ -8695,7 +8694,7 @@ int GlobalRA::coloringRegAlloc()
86958694
unsigned maxRAIterations = 10;
86968695
unsigned iterationNo = 0;
86978696

8698-
std::vector<SpillManagerGMRF::EDGE> prevIntfEdges;
8697+
std::vector<SpillManagerGRF::EDGE> prevIntfEdges;
86998698

87008699
int globalScratchOffset = builder.getOptions()->getuInt32Option(vISA_SpillMemOffset);
87018700
bool useScratchMsgForSpill = globalScratchOffset < (int) (SCRATCH_MSG_LIMIT * 0.6) && !hasStackCall;
@@ -8932,7 +8931,7 @@ int GlobalRA::coloringRegAlloc()
89328931
}
89338932

89348933
startTimer(TIMER_SPILL);
8935-
SpillManagerGMRF spillGMRF(*this,
8934+
SpillManagerGRF spillGRF(*this,
89368935
nextSpillOffset,
89378936
liveAnalysis.getNumSelectedVar(),
89388937
&liveAnalysis,
@@ -8946,8 +8945,8 @@ int GlobalRA::coloringRegAlloc()
89468945
enableSpillSpaceCompression,
89478946
useScratchMsgForSpill);
89488947

8949-
bool success = spillGMRF.insertSpillFillCode(&kernel, pointsToAnalysis);
8950-
nextSpillOffset = spillGMRF.getNextOffset();
8948+
bool success = spillGRF.insertSpillFillCode(&kernel, pointsToAnalysis);
8949+
nextSpillOffset = spillGRF.getNextOffset();
89518950

89528951
if (builder.getOption(vISA_RATrace))
89538952
{
@@ -8966,19 +8965,19 @@ int GlobalRA::coloringRegAlloc()
89668965
kernel.dumpDotFile("Spill_GRF");
89678966
}
89688967

8969-
scratchOffset = std::max(scratchOffset, spillGMRF.getNextScratchOffset());
8968+
scratchOffset = std::max(scratchOffset, spillGRF.getNextScratchOffset());
89708969
#ifdef FIX_SCRATCH_SPILL_MESSAGE
89718970
if (scratchOffset >= SCRATCH_MSG_LIMIT && useScratchMsgForSpill)
89728971
{
8973-
spillGMRF.fixSpillFillCode(&kernel);
8972+
spillGRF.fixSpillFillCode(&kernel);
89748973
}
89758974
#endif
89768975
bool disableSpillCoalecse = builder.getOption(vISA_DisableSpillCoalescing) ||
89778976
builder.getOption(vISA_FastSpill) || builder.getOption(vISA_Debug);
89788977
if (!reserveSpillReg && !disableSpillCoalecse && builder.useSends() &&
89798978
!kernel.fg.getHasStackCalls() && !kernel.fg.getIsStackCallFunc())
89808979
{
8981-
CoalesceSpillFills c(kernel, liveAnalysis, coloring, spillGMRF, iterationNo, rpe, *this);
8980+
CoalesceSpillFills c(kernel, liveAnalysis, coloring, spillGRF, iterationNo, rpe, *this);
89828981
c.run();
89838982
}
89848983

‎visa/IGfxHwEuIsaCNL.h

+1-1
Original file line numberDiff line numberDiff line change
@@ -5058,7 +5058,7 @@ typedef union tagEU_INSTRUCTION_OPERAND_SEND_MSG {
50585058
DWORD MessageDescriptor_ResponseLength : BITFIELD_RANGE( 20, 24); //
50595059

50605060
/*****************************************************************************\
5061-
This field specifies the number of 256-bit MRF registers starting from &lt;curr_dest&gt; to be sent out on the request message payload. Valid value ranges from 1 to 15. A value of 0 is considered erroneous.
5061+
This field specifies the number of 256-bit registers starting from &lt;curr_dest&gt; to be sent out on the request message payload. Valid value ranges from 1 to 15. A value of 0 is considered erroneous.
50625062
\*****************************************************************************/
50635063
DWORD MessageDescriptor_MessageLength : BITFIELD_RANGE( 25, 28); //
50645064
DWORD __CODEGEN_UNIQUE(Overridden) : BITFIELD_RANGE( 29, 31); // Override

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