Fix skip to DW_OP_stack_value in DWARF split variables

When building a sliced variable, we are emitting two SIMD16 subprograms.
Currently only the upper half lanes (16-31) reaches the `DW_OP_stack_value`
at the end of the source variable's DI Block. The first-half lanes (0-15)
are skipped to the end of the block after emitting the first half,
making the variable unreadable in the debugger.

Author: MiloszSkobejko

IGC/DebugInfo/DwarfCompileUnit.cpp

@@ -2775,6 +2775,7 @@ IGC::DIEBlock *CompileUnit::buildGeneral(
   offsetTaken = 0;
   skipOff = nullptr;
   emitLocation = false;
+  stackValueOffset = 0;
 
   LLVM_DEBUG(dbgs() << "  building DWARF info for the variable ["
                     << var.getName() << "]\n");
@@ -2810,7 +2811,9 @@ IGC::DIEBlock *CompileUnit::buildGeneral(
   }
 
   if (skipOff) {
-    unsigned int offsetEnd = Block->ComputeSizeOnTheFly(Asm);
+    // In split SIMD case, we want to skip to DW_OP_stack_value at the end,
+    // not past it.
+    unsigned int offsetEnd = Block->ComputeSizeOnTheFly(Asm) - stackValueOffset;
     cast<DIEInteger>(skipOff)->setValue(offsetEnd - offsetTaken);
   }
 

IGC/DebugInfo/DwarfCompileUnit.hpp

@@ -527,6 +527,7 @@ class CompileUnit {
   DIEBlock *buildGeneral(DbgVariable &, const VISAVariableLocation &,
                          const std::vector<DbgDecoder::LiveIntervalsVISA> *,
                          IGC::DIE *);
+  unsigned int stackValueOffset = 0;
 
 private:
   bool buildPrivateBaseRegBased(const DbgVariable &, IGC::DIEBlock *,

IGC/DebugInfo/DwarfDebug.cpp

@@ -232,6 +232,7 @@ void DbgVariable::emitExpression(CompileUnit *CU, IGC::DIEBlock *Block) const {
 
   if (isStackValueNeeded) {
     CU->addUInt(Block, dwarf::DW_FORM_data1, dwarf::DW_OP_stack_value);
+    CU->stackValueOffset = 1;
   }
 }
 

IGC/ocloc_tests/DebugInfo/simd32-sliced-stack-value.cl

@@ -77,7 +77,8 @@ kernel void test(global int* in, global int* out) {
 // CHECK-DWARF-SAME: (DW_OP_INTEL_push_simd_lane; DW_OP_lit16; DW_OP_ge; DW_OP_bra: [[GID_BR:[0-9]+]];
 // CHECK-DWARF-SAME: DW_OP_INTEL_push_simd_lane; DW_OP_lit3; DW_OP_shr; DW_OP_plus_uconst: {{[0-9]+}};
 // CHECK-DWARF-SAME: DW_OP_INTEL_push_simd_lane; [[GID_MAIN_EXPR:DW_OP_lit7; DW_OP_and; DW_OP_const1u: 32; DW_OP_mul; DW_OP_INTEL_regval_bits: 32; DW_OP_const4u: 4294967295; DW_OP_and]];
-// CHECK-DWARF-SAME: DW_OP_skip: [[GID_BR]];
+// COM: skip to DW_OP_stack_value, where all lanes should meet
+// CHECK-DWARF-SAME: DW_OP_skip: 21
 // CHECK-DWARF-SAME: DW_OP_INTEL_push_simd_lane; DW_OP_lit16; DW_OP_minus; DW_OP_lit3; DW_OP_shr; DW_OP_plus_uconst: {{[0-9]+}};
 // CHECK-DWARF-SAME: DW_OP_INTEL_push_simd_lane; [[GID_MAIN_EXPR]]; DW_OP_stack_value)
 // CHECK-DWARF-NEXT: <End of list>
@@ -86,7 +87,8 @@ kernel void test(global int* in, global int* out) {
 // CHECK-DWARF-SAME: (DW_OP_INTEL_push_simd_lane; DW_OP_lit16; DW_OP_ge; DW_OP_bra: [[MUL_BR:[0-9]+]];
 // CHECK-DWARF-SAME: DW_OP_INTEL_push_simd_lane; DW_OP_lit3; DW_OP_shr; DW_OP_plus_uconst: {{[0-9]+}};
 // CHECK-DWARF-SAME: DW_OP_INTEL_push_simd_lane; [[MUL_MAIN_EXPR:DW_OP_lit7; DW_OP_and; DW_OP_const1u: 32; DW_OP_mul; DW_OP_INTEL_regval_bits: 32]];
-// CHECK-DWARF-SAME: DW_OP_skip: [[MUL_BR]];
+// COM: skip to DW_OP_stack_value, where all lanes should meet
+// CHECK-DWARF-SAME: DW_OP_skip: 15
 // CHECK-DWARF-SAME: DW_OP_INTEL_push_simd_lane; DW_OP_lit16; DW_OP_minus; DW_OP_lit3; DW_OP_shr; DW_OP_plus_uconst: {{[0-9]+}};
 // CHECK-DWARF-SAME: DW_OP_INTEL_push_simd_lane; [[MUL_MAIN_EXPR]]; DW_OP_stack_value)
 // CHECK-DWARF-NEXT: <End of list>