Remove FPGA features from DPC++

[gmlueck]

With the launch of Altera as a separate entity, oneAPI DPC++ will concentrate on support for GPU and CPU devices. Altera will continue to provide FPGA support through their dedicated FPGA software development tools. You can read more about this in the deprecation notice at the top of the oneAPI DPC++ release notes. As a result, the following features are scheduled for removal:

1. We will remove the sycl_ext_oneapi_annotated_arg extension. We added this in order to decorate kernel arguments with properties, which were mostly specific to FPGA. It is possible that non-FPGA code could use this extension to decorate kernel arguments with the alignment or unaliased properties, though it would be more common to use sycl_ext_oneapi_annotated_ptr for this purpose because these properties apply only to pointers. (Note the difference is “arg” vs. “ptr”.) We plan to keep supporting sycl_ext_oneapi_annotated_ptr. Therefore, code using sycl_ext_oneapi_annotated_arg should migrate to use sycl_ext_oneapi_annotated_ptr instead.

2. We will remove the sycl_ext_intel_usm_address_spaces extension. This extension adds address spaces named ext_intel_global_device_space and ext_intel_global_host_space as well as multi_ptr aliases named device_ptr and host_ptr (and some other variants). Although it’s possible to use these on non-FPGA devices, they provide no benefit. Therefore, code using this extension should use the standard SYCL address spaces instead.

3. We will remove the following compiler command line options which are all specific to FPGA:

   • -fsycl-targets=spir64_fpga
   • -fsycl-targets=spir64_fpga-unknown-unknown
   • -fintelfpga
   • -fsycl-help=fpga
   • -fsycl-link=early
   • -fsycl-link=image
   • -reuse-exe
   • -fhls
   • -Xsycl-target-backend=spir64_fpga

4. We will remove “fpga” from the device types recognized by the ONEAPI_DEVICE_SELECTOR environment variable.

5. We will remove “fpga” from the device types recognized by the SYCL_DEVICE_ALLOWLIST environment variable.

6. We will remove all of the following extensions that are specific to FPGA devices:

   • https://github.com/intel/llvm/blob/sycl/sycl/doc/extensions/supported/sycl_ext_intel_buffer_location.asciidoc
   • https://github.com/intel/llvm/blob/sycl/sycl/doc/extensions/supported/sycl_ext_intel_dataflow_pipes.asciidoc
   • https://github.com/intel/llvm/blob/sycl/sycl/doc/extensions/supported/sycl_ext_intel_fpga_device_selector.asciidoc
   • https://github.com/intel/llvm/blob/sycl/sycl/doc/extensions/supported/sycl_ext_intel_fpga_lsu.md
   • https://github.com/intel/llvm/blob/sycl/sycl/doc/extensions/supported/sycl_ext_intel_fpga_reg.md
   • https://github.com/intel/llvm/blob/sycl/sycl/doc/extensions/supported/sycl_ext_intel_mem_channel_property.asciidoc
   • https://github.com/intel/llvm/blob/sycl/sycl/doc/extensions/experimental/sycl_ext_intel_data_flow_pipes_properties.asciidoc
   • https://github.com/intel/llvm/blob/sycl/sycl/doc/extensions/experimental/sycl_ext_intel_fpga_task_sequence.asciidoc

7. We will remove two properties from the sycl_ext_oneapi_device_global extension that are specific to FPGA named init_mode and implement_in_csr.

[keryell]

It is sad to remove so much work from an open-source project if someone wants to reuse it later.
Perhaps you could just keep it, not advertising it, with minimal CI without e2e execution on hardware or simulator and skipping it during the LLVM up-streaming process.
At least keep a tag on the last commit supporting it.

[gmlueck]

The last oneAPI / DPC++ release to support FPGA is 2025.0. The corresponding branch in this "intel/llvm" repo is sycl-rel-6_0_0.

As you know, Intel is in the process of adding support for SYCL into the upstream "llvm" repo. The community expects us to support the features we upstream, and we do not have the resources to support FPGA devices or features that are specific to FPGA. However, we would be very happy to see other members of the community pick up this work and add FPGA support to upstream "llvm".

[fwyzard]

Altera will continue to provide FPGA support through their dedicated FPGA software development tools.

Is it known if this means the old OpenCL stack, or if Altera will support SYCL ?

[gmlueck]

Is it known if this means the old OpenCL stack, or if Altera will support SYCL ?

I cannot speak for Altera. If someone from Altera is monitoring this issue, maybe they will answer.