Covertion of non-genx_volatile globals to genx_volatile ones can/must be removed.

[lsatanov]

Hi, @igorban-intel

vc-intrinsics/GenXIntrinsics/lib/GenXIntrinsics/GenXSimdCFLowering.cpp

Line 472 in f9c3440

* it generate issue in register allocator - because it will be put to

The issue is not in register allocator or a special case for coalescing as the comment in the source code states.

The faulty situation is reflected in this LIT test: https://github.com/intel/intel-graphics-compiler/blob/1b038250fd5eb6c6b51d2c8062174f645ceefad2/IGC/VectorCompiler/test/GenXLegalizeGVLoadUses/mem2reg_gv_clobbering_avoidance.ll
The comment in the test explains it in pseudocode: LLVM's optimization replaced non-genx_volatile variable with genx_volatile one while it has proved that they constitute the same value (totally legitimate from LLVM semantics standpoint).

This was fixed (intel/intel-graphics-compiler@9fa222a) in the compiler by "legalization" of genx.vload users to genx-controlled subset hence mem2reg or any other LLVM optimizations are not to break the implied genx-middle-end semantics anymore. After the abovementioned fix was applied in IGC VectorCompiler this is no longer an issue.

This particular change (covertion of non-genx_volatile globals to genx_volatile ones) now can be removed. Otherwize, it increases register pressure and potentially can cause some workloads not compile.