-
Notifications
You must be signed in to change notification settings - Fork 0
/
Copy path.gitignore
154 lines (134 loc) · 4.9 KB
/
.gitignore
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
*.nfs*
*.swp
*.log
*a.out
*.o
*.img
#Ignore bootrom baremetal
piton/design/chip/tile/ariane/openpiton/bootrom/baremetal/bootrom.h
piton/design/chip/tile/ariane/openpiton/bootrom/baremetal/bootrom.img
piton/design/chip/tile/ariane/openpiton/bootrom/baremetal/bootrom.sv
piton/design/chip/tile/ariane/openpiton/bootrom/linux/ariane.dtb
#EDITIONS ON 23/JUIN
#Ignore build files -- See these files to better understad
piton/design/chip/tile/ariane/openpiton/bootrom/ariane.dts
piton/design/chip/tile/ariane/openpiton/bootrom/info.h
piton/design/chip/tile/ariane/openpiton/bootrom/linux/bootrom_linux.bin
piton/design/chip/tile/ariane/openpiton/bootrom/linux/bootrom_linux.elf
piton/design/chip/tile/ariane/openpiton/bootrom/linux/bootrom_linux.h
piton/design/chip/tile/ariane/openpiton/bootrom/linux/bootrom_linux.img
piton/design/chip/tile/ariane/openpiton/bootrom/linux/bootrom_linux.sv
piton/design/chip/tile/ariane/openpiton/bootrom/linux/src/*
#Other files
diag.c
diag.dump
diag.ev
diag.exe
mem.image
my_top.vcd
symbol.tbl
trace_hart_00.dasm
# Ignore everything in model directory
.vscode/*
build/*
!build/.keep
piton/design/chip/tile/ariane/tmp/*
# Ignore generated logs from back-end
# Good for 10 levels of hierarchy
piton/design/*/synopsys/*
!piton/design/*/synopsys/script
piton/design/*/*/synopsys/*
!piton/design/*/*/synopsys/script
piton/design/*/*/*/synopsys/*
!piton/design/*/*/*/synopsys/script
piton/design/*/*/*/*/synopsys/*
!piton/design/*/*/*/*/synopsys/script
piton/design/*/*/*/*/*/synopsys/*
!piton/design/*/*/*/*/*/synopsys/script
piton/design/*/*/*/*/*/*/synopsys/*
!piton/design/*/*/*/*/*/*/synopsys/script
piton/design/*/*/*/*/*/*/*/synopsys/*
!piton/design/*/*/*/*/*/*/*/synopsys/script
piton/design/*/*/*/*/*/*/*/*/synopsys/*
!piton/design/*/*/*/*/*/*/*/*/synopsys/script
piton/design/*/*/*/*/*/*/*/*/*/synopsys/*
!piton/design/*/*/*/*/*/*/*/*/*/synopsys/script
piton/design/*/*/*/*/*/*/*/*/*/*/synopsys/*
!piton/design/*/*/*/*/*/*/*/*/*/*/synopsys/script
# IP for FPGA designs is generated in palce
# where .xci file is located, so need to ignore
# these generated files.
# Good for 10 levels of hierarchy
piton/design/xilinx/*/ip_cores/*/*
!piton/design/xilinx/*/ip_cores/*/*.xci
!piton/design/xilinx/*/ip_cores/*/*.xco
!piton/design/xilinx/*/ip_cores/*/*.coe
piton/design/*/xilinx/*/ip_cores/*/*
!piton/design/*/xilinx/*/ip_cores/*/*.xci
!piton/design/*/xilinx/*/ip_cores/*/*.xco
!piton/design/*/xilinx/*/ip_cores/*/*.coe
piton/design/*/*/xilinx/*/ip_cores/*/*
!piton/design/*/*/xilinx/*/ip_cores/*/*.xci
!piton/design/*/*/xilinx/*/ip_cores/*/*.xco
!piton/design/*/*/xilinx/*/ip_cores/*/*.coe
piton/design/*/*/*/xilinx/*/ip_cores/*/*
!piton/design/*/*/*/xilinx/*/ip_cores/*/*.xci
!piton/design/*/*/*/xilinx/*/ip_cores/*/*.xco
!piton/design/*/*/*/xilinx/*/ip_cores/*/*.coe
piton/design/*/*/*/*/xilinx/*/ip_cores/*/*
!piton/design/*/*/*/*/xilinx/*/ip_cores/*/*.xci
!piton/design/*/*/*/*/xilinx/*/ip_cores/*/*.xco
!piton/design/*/*/*/*/xilinx/*/ip_cores/*/*.coe
piton/design/*/*/*/*/*/xilinx/*/ip_cores/*/*
!piton/design/*/*/*/*/*/xilinx/*/ip_cores/*/*.xci
!piton/design/*/*/*/*/*/xilinx/*/ip_cores/*/*.xco
!piton/design/*/*/*/*/*/xilinx/*/ip_cores/*/*.coe
piton/design/*/*/*/*/*/*/xilinx/*/ip_cores/*/*
!piton/design/*/*/*/*/*/*/xilinx/*/ip_cores/*/*.xci
!piton/design/*/*/*/*/*/*/xilinx/*/ip_cores/*/*.xco
!piton/design/*/*/*/*/*/*/xilinx/*/ip_cores/*/*.coe
piton/design/*/*/*/*/*/*/*/xilinx/*/ip_cores/*/*
!piton/design/*/*/*/*/*/*/*/xilinx/*/ip_cores/*/*.xci
!piton/design/*/*/*/*/*/*/*/xilinx/*/ip_cores/*/*.xco
!piton/design/*/*/*/*/*/*/*/xilinx/*/ip_cores/*/*.coe
piton/design/*/*/*/*/*/*/*/*/xilinx/*/ip_cores/*/*
!piton/design/*/*/*/*/*/*/*/*/xilinx/*/ip_cores/*/*.xci
!piton/design/*/*/*/*/*/*/*/*/xilinx/*/ip_cores/*/*.xco
!piton/design/*/*/*/*/*/*/*/*/xilinx/*/ip_cores/*/*.coe
piton/design/*/*/*/*/*/*/*/*/*/xilinx/*/ip_cores/*/*
!piton/design/*/*/*/*/*/*/*/*/*/xilinx/*/ip_cores/*/*.xci
!piton/design/*/*/*/*/*/*/*/*/*/xilinx/*/ip_cores/*/*.xco
!piton/design/*/*/*/*/*/*/*/*/*/xilinx/*/ip_cores/*/*.coe
piton/design/*/*/*/*/*/*/*/*/*/*/xilinx/*/ip_cores/*/*
!piton/design/*/*/*/*/*/*/*/*/*/*/xilinx/*/ip_cores/*/*.xci
!piton/design/*/*/*/*/*/*/*/*/*/*/xilinx/*/ip_cores/*/*.xco
!piton/design/*/*/*/*/*/*/*/*/*/*/xilinx/*/ip_cores/*/*.coe
# Ignore files generated for DMBR unit testing
piton/verif/diag/assembly/princeton/dmbr_stream_hyper_gen.s
piton/verif/env/dmbr_test/dmbr_test_top.v
piton/verif/env/dmbr_test/test_cases/simple_sink.vmh
piton/verif/env/dmbr_test/test_cases/simple_src.vmh
piton/verif/diag/assembly/princeton/dmbr_assembly.s
# Ignore Vivado
.Xil/*
vivado*.log
vivado*.str
# Ignore sims logs
flist
history.sims
ucli.key
# Ignore temporary pyv files
*.v.tmp
*.h.tmp
*.tmp.v
*.tmp.h
*.elf
# Ignore generated .pyc files (specifically for pyhplib)
*.pyc
# Ignore deprecated automated IBM wrapper generated files
*_TWRAPPER.v.TWRAPPER.v
# trin ignore some other files
cscope.*
tags
*.bak
piton/design/chip/tile/ariane/src/rv_plic/rtl/plic_regmap.sv