This CPU implementation uses the RISC-V ISA, version RV32I. It is a 32-bit architecture and implements the following subset of RV32I instructions:
add, addi, and, sub, slli, srai, srli, slt
bne, beq, , jal, jalr
lw, sw, lui
mv, nop, j, jr, la, ret
This CPU implementation uses the RISC-V ISA, version RV32I. It is a 32-bit architecture and implements the following subset of RV32I instructions:
add, addi, and, sub, slli, srai, srli, slt
bne, beq, , jal, jalr
lw, sw, lui
mv, nop, j, jr, la, ret