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Merge tag 'riscv-for-linus-6.8-mw4' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux
Pull more RISC-V updates from Palmer Dabbelt: - Support for tuning for systems with fast misaligned accesses. - Support for SBI-based suspend. - Support for the new SBI debug console extension. - The T-Head CMOs now use PA-based flushes. - Support for enabling the V extension in kernel code. - Optimized IP checksum routines. - Various ftrace improvements. - Support for archrandom, which depends on the Zkr extension. - The build is no longer broken under NET=n, KUNIT=y for ports that don't define their own ipv6 checksum. * tag 'riscv-for-linus-6.8-mw4' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: (56 commits) lib: checksum: Fix build with CONFIG_NET=n riscv: lib: Check if output in asm goto supported riscv: Fix build error on rv32 + XIP riscv: optimize ELF relocation function in riscv RISC-V: Implement archrandom when Zkr is available riscv: Optimize hweight API with Zbb extension riscv: add dependency among Image(.gz), loader(.bin), and vmlinuz.efi samples: ftrace: Add RISC-V support for SAMPLE_FTRACE_DIRECT[_MULTI] riscv: ftrace: Add DYNAMIC_FTRACE_WITH_DIRECT_CALLS support riscv: ftrace: Make function graph use ftrace directly riscv: select FTRACE_MCOUNT_USE_PATCHABLE_FUNCTION_ENTRY lib/Kconfig.debug: Update AS_HAS_NON_CONST_LEB128 comment and name riscv: Restrict DWARF5 when building with LLVM to known working versions riscv: Hoist linker relaxation disabling logic into Kconfig kunit: Add tests for csum_ipv6_magic and ip_fast_csum riscv: Add checksum library riscv: Add checksum header riscv: Add static key for misaligned accesses asm-generic: Improve csum_fold RISC-V: selftests: cbo: Ensure asm operands match constraints ...
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‎Documentation/devicetree/bindings/riscv/cpus.yaml

+7-2
Original file line numberDiff line numberDiff line change
@@ -63,8 +63,8 @@ properties:
6363

6464
mmu-type:
6565
description:
66-
Identifies the MMU address translation mode used on this
67-
hart. These values originate from the RISC-V Privileged
66+
Identifies the largest MMU address translation mode supported by
67+
this hart. These values originate from the RISC-V Privileged
6868
Specification document, available from
6969
https://riscv.org/specifications/
7070
$ref: /schemas/types.yaml#/definitions/string
@@ -80,6 +80,11 @@ properties:
8080
description:
8181
The blocksize in bytes for the Zicbom cache operations.
8282

83+
riscv,cbop-block-size:
84+
$ref: /schemas/types.yaml#/definitions/uint32
85+
description:
86+
The blocksize in bytes for the Zicbop cache operations.
87+
8388
riscv,cboz-block-size:
8489
$ref: /schemas/types.yaml#/definitions/uint32
8590
description:

‎Documentation/devicetree/bindings/riscv/extensions.yaml

+1-1
Original file line numberDiff line numberDiff line change
@@ -48,7 +48,7 @@ properties:
4848
insensitive, letters in the riscv,isa string must be all
4949
lowercase.
5050
$ref: /schemas/types.yaml#/definitions/string
51-
pattern: ^rv(?:64|32)imaf?d?q?c?b?k?j?p?v?h?(?:[hsxz](?:[a-z])+)?(?:_[hsxz](?:[a-z])+)*$
51+
pattern: ^rv(?:64|32)imaf?d?q?c?b?k?j?p?v?h?(?:[hsxz](?:[0-9a-z])+)?(?:_[hsxz](?:[0-9a-z])+)*$
5252
deprecated: true
5353

5454
riscv,isa-base:

‎Documentation/features/vm/TLB/arch-support.txt

+1-1
Original file line numberDiff line numberDiff line change
@@ -20,7 +20,7 @@
2020
| openrisc: | .. |
2121
| parisc: | TODO |
2222
| powerpc: | TODO |
23-
| riscv: | TODO |
23+
| riscv: | ok |
2424
| s390: | TODO |
2525
| sh: | TODO |
2626
| sparc: | TODO |

‎arch/riscv/Kconfig

+56-1
Original file line numberDiff line numberDiff line change
@@ -53,6 +53,7 @@ config RISCV
5353
select ARCH_USE_MEMTEST
5454
select ARCH_USE_QUEUED_RWLOCKS
5555
select ARCH_USES_CFI_TRAPS if CFI_CLANG
56+
select ARCH_WANT_BATCHED_UNMAP_TLB_FLUSH if SMP && MMU
5657
select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU
5758
select ARCH_WANT_FRAME_POINTERS
5859
select ARCH_WANT_GENERAL_HUGETLB if !RISCV_ISA_SVNAPOT
@@ -66,9 +67,10 @@ config RISCV
6667
select CLINT_TIMER if !MMU
6768
select CLONE_BACKWARDS
6869
select COMMON_CLK
69-
select CPU_PM if CPU_IDLE || HIBERNATION
70+
select CPU_PM if CPU_IDLE || HIBERNATION || SUSPEND
7071
select EDAC_SUPPORT
7172
select FRAME_POINTER if PERF_EVENTS || (FUNCTION_TRACER && !DYNAMIC_FTRACE)
73+
select FTRACE_MCOUNT_USE_PATCHABLE_FUNCTION_ENTRY if DYNAMIC_FTRACE
7274
select GENERIC_ARCH_TOPOLOGY
7375
select GENERIC_ATOMIC64 if !64BIT
7476
select GENERIC_CLOCKEVENTS_BROADCAST if SMP
@@ -115,6 +117,7 @@ config RISCV
115117
select HAVE_DEBUG_KMEMLEAK
116118
select HAVE_DMA_CONTIGUOUS if MMU
117119
select HAVE_DYNAMIC_FTRACE if !XIP_KERNEL && MMU && (CLANG_SUPPORTS_DYNAMIC_FTRACE || GCC_SUPPORTS_DYNAMIC_FTRACE)
120+
select HAVE_DYNAMIC_FTRACE_WITH_DIRECT_CALLS
118121
select HAVE_DYNAMIC_FTRACE_WITH_REGS if HAVE_DYNAMIC_FTRACE
119122
select HAVE_FTRACE_MCOUNT_RECORD if !XIP_KERNEL
120123
select HAVE_FUNCTION_GRAPH_TRACER
@@ -142,6 +145,8 @@ config RISCV
142145
select HAVE_REGS_AND_STACK_ACCESS_API
143146
select HAVE_RETHOOK if !XIP_KERNEL
144147
select HAVE_RSEQ
148+
select HAVE_SAMPLE_FTRACE_DIRECT
149+
select HAVE_SAMPLE_FTRACE_DIRECT_MULTI
145150
select HAVE_STACKPROTECTOR
146151
select HAVE_SYSCALL_TRACEPOINTS
147152
select HOTPLUG_CORE_SYNC_DEAD if HOTPLUG_CPU
@@ -183,6 +188,20 @@ config HAVE_SHADOW_CALL_STACK
183188
# https://github.com/riscv-non-isa/riscv-elf-psabi-doc/commit/a484e843e6eeb51f0cb7b8819e50da6d2444d769
184189
depends on $(ld-option,--no-relax-gp)
185190

191+
config RISCV_USE_LINKER_RELAXATION
192+
def_bool y
193+
# https://github.com/llvm/llvm-project/commit/6611d58f5bbcbec77262d392e2923e1d680f6985
194+
depends on !LD_IS_LLD || LLD_VERSION >= 150000
195+
196+
# https://github.com/llvm/llvm-project/commit/bbc0f99f3bc96f1db16f649fc21dd18e5b0918f6
197+
config ARCH_HAS_BROKEN_DWARF5
198+
def_bool y
199+
depends on RISCV_USE_LINKER_RELAXATION
200+
# https://github.com/llvm/llvm-project/commit/1df5ea29b43690b6622db2cad7b745607ca4de6a
201+
depends on AS_IS_LLVM && AS_VERSION < 180000
202+
# https://github.com/llvm/llvm-project/commit/7ffabb61a5569444b5ac9322e22e5471cc5e4a77
203+
depends on LD_IS_LLD && LLD_VERSION < 180000
204+
186205
config ARCH_MMAP_RND_BITS_MIN
187206
default 18 if 64BIT
188207
default 8
@@ -529,6 +548,28 @@ config RISCV_ISA_V_DEFAULT_ENABLE
529548

530549
If you don't know what to do here, say Y.
531550

551+
config RISCV_ISA_V_UCOPY_THRESHOLD
552+
int "Threshold size for vectorized user copies"
553+
depends on RISCV_ISA_V
554+
default 768
555+
help
556+
Prefer using vectorized copy_to_user()/copy_from_user() when the
557+
workload size exceeds this value.
558+
559+
config RISCV_ISA_V_PREEMPTIVE
560+
bool "Run kernel-mode Vector with kernel preemption"
561+
depends on PREEMPTION
562+
depends on RISCV_ISA_V
563+
default y
564+
help
565+
Usually, in-kernel SIMD routines are run with preemption disabled.
566+
Functions which envoke long running SIMD thus must yield core's
567+
vector unit to prevent blocking other tasks for too long.
568+
569+
This config allows kernel to run SIMD without explicitly disable
570+
preemption. Enabling this config will result in higher memory
571+
consumption due to the allocation of per-task's kernel Vector context.
572+
532573
config TOOLCHAIN_HAS_ZBB
533574
bool
534575
default y
@@ -655,6 +696,20 @@ config RISCV_MISALIGNED
655696
load/store for both kernel and userspace. When disable, misaligned
656697
accesses will generate SIGBUS in userspace and panic in kernel.
657698

699+
config RISCV_EFFICIENT_UNALIGNED_ACCESS
700+
bool "Assume the CPU supports fast unaligned memory accesses"
701+
depends on NONPORTABLE
702+
select DCACHE_WORD_ACCESS if MMU
703+
select HAVE_EFFICIENT_UNALIGNED_ACCESS
704+
help
705+
Say Y here if you want the kernel to assume that the CPU supports
706+
efficient unaligned memory accesses. When enabled, this option
707+
improves the performance of the kernel on such CPUs. However, the
708+
kernel will run much more slowly, or will not be able to run at all,
709+
on CPUs that do not support efficient unaligned memory accesses.
710+
711+
If unsure what to do here, say N.
712+
658713
endmenu # "Platform type"
659714

660715
menu "Kernel features"

‎arch/riscv/Kconfig.errata

+1
Original file line numberDiff line numberDiff line change
@@ -98,6 +98,7 @@ config ERRATA_THEAD_CMO
9898
depends on ERRATA_THEAD && MMU
9999
select DMA_DIRECT_REMAP
100100
select RISCV_DMA_NONCOHERENT
101+
select RISCV_NONSTANDARD_CACHE_OPS
101102
default y
102103
help
103104
This will apply the cache management errata to handle the

‎arch/riscv/Makefile

+5-3
Original file line numberDiff line numberDiff line change
@@ -43,16 +43,14 @@ else
4343
KBUILD_LDFLAGS += -melf32lriscv
4444
endif
4545

46-
ifeq ($(CONFIG_LD_IS_LLD),y)
47-
ifeq ($(call test-lt, $(CONFIG_LLD_VERSION), 150000),y)
46+
ifndef CONFIG_RISCV_USE_LINKER_RELAXATION
4847
KBUILD_CFLAGS += -mno-relax
4948
KBUILD_AFLAGS += -mno-relax
5049
ifndef CONFIG_AS_IS_LLVM
5150
KBUILD_CFLAGS += -Wa,-mno-relax
5251
KBUILD_AFLAGS += -Wa,-mno-relax
5352
endif
5453
endif
55-
endif
5654

5755
ifeq ($(CONFIG_SHADOW_CALL_STACK),y)
5856
KBUILD_LDFLAGS += --no-relax-gp
@@ -108,7 +106,9 @@ KBUILD_AFLAGS_MODULE += $(call as-option,-Wa$(comma)-mno-relax)
108106
# unaligned accesses. While unaligned accesses are explicitly allowed in the
109107
# RISC-V ISA, they're emulated by machine mode traps on all extant
110108
# architectures. It's faster to have GCC emit only aligned accesses.
109+
ifneq ($(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS),y)
111110
KBUILD_CFLAGS += $(call cc-option,-mstrict-align)
111+
endif
112112

113113
ifeq ($(CONFIG_STACKPROTECTOR_PER_TASK),y)
114114
prepare: stack_protector_prepare
@@ -163,6 +163,8 @@ BOOT_TARGETS := Image Image.gz loader loader.bin xipImage vmlinuz.efi
163163

164164
all: $(notdir $(KBUILD_IMAGE))
165165

166+
loader.bin: loader
167+
Image.gz loader vmlinuz.efi: Image
166168
$(BOOT_TARGETS): vmlinux
167169
$(Q)$(MAKE) $(build)=$(boot) $(boot)/$@
168170
@$(kecho) ' Kernel: $(boot)/$@ is ready'

‎arch/riscv/configs/defconfig

+1
Original file line numberDiff line numberDiff line change
@@ -149,6 +149,7 @@ CONFIG_SERIAL_8250_CONSOLE=y
149149
CONFIG_SERIAL_8250_DW=y
150150
CONFIG_SERIAL_OF_PLATFORM=y
151151
CONFIG_SERIAL_SH_SCI=y
152+
CONFIG_SERIAL_EARLYCON_RISCV_SBI=y
152153
CONFIG_VIRTIO_CONSOLE=y
153154
CONFIG_HW_RANDOM=y
154155
CONFIG_HW_RANDOM_VIRTIO=y

‎arch/riscv/errata/thead/errata.c

+67-2
Original file line numberDiff line numberDiff line change
@@ -12,8 +12,10 @@
1212
#include <asm/alternative.h>
1313
#include <asm/cacheflush.h>
1414
#include <asm/cpufeature.h>
15+
#include <asm/dma-noncoherent.h>
1516
#include <asm/errata_list.h>
1617
#include <asm/hwprobe.h>
18+
#include <asm/io.h>
1719
#include <asm/patch.h>
1820
#include <asm/vendorid_list.h>
1921

@@ -33,6 +35,69 @@ static bool errata_probe_pbmt(unsigned int stage,
3335
return false;
3436
}
3537

38+
/*
39+
* th.dcache.ipa rs1 (invalidate, physical address)
40+
* | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 |
41+
* 0000001 01010 rs1 000 00000 0001011
42+
* th.dcache.iva rs1 (invalidate, virtual address)
43+
* 0000001 00110 rs1 000 00000 0001011
44+
*
45+
* th.dcache.cpa rs1 (clean, physical address)
46+
* | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 |
47+
* 0000001 01001 rs1 000 00000 0001011
48+
* th.dcache.cva rs1 (clean, virtual address)
49+
* 0000001 00101 rs1 000 00000 0001011
50+
*
51+
* th.dcache.cipa rs1 (clean then invalidate, physical address)
52+
* | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 |
53+
* 0000001 01011 rs1 000 00000 0001011
54+
* th.dcache.civa rs1 (clean then invalidate, virtual address)
55+
* 0000001 00111 rs1 000 00000 0001011
56+
*
57+
* th.sync.s (make sure all cache operations finished)
58+
* | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 |
59+
* 0000000 11001 00000 000 00000 0001011
60+
*/
61+
#define THEAD_INVAL_A0 ".long 0x02a5000b"
62+
#define THEAD_CLEAN_A0 ".long 0x0295000b"
63+
#define THEAD_FLUSH_A0 ".long 0x02b5000b"
64+
#define THEAD_SYNC_S ".long 0x0190000b"
65+
66+
#define THEAD_CMO_OP(_op, _start, _size, _cachesize) \
67+
asm volatile("mv a0, %1\n\t" \
68+
"j 2f\n\t" \
69+
"3:\n\t" \
70+
THEAD_##_op##_A0 "\n\t" \
71+
"add a0, a0, %0\n\t" \
72+
"2:\n\t" \
73+
"bltu a0, %2, 3b\n\t" \
74+
THEAD_SYNC_S \
75+
: : "r"(_cachesize), \
76+
"r"((unsigned long)(_start) & ~((_cachesize) - 1UL)), \
77+
"r"((unsigned long)(_start) + (_size)) \
78+
: "a0")
79+
80+
static void thead_errata_cache_inv(phys_addr_t paddr, size_t size)
81+
{
82+
THEAD_CMO_OP(INVAL, paddr, size, riscv_cbom_block_size);
83+
}
84+
85+
static void thead_errata_cache_wback(phys_addr_t paddr, size_t size)
86+
{
87+
THEAD_CMO_OP(CLEAN, paddr, size, riscv_cbom_block_size);
88+
}
89+
90+
static void thead_errata_cache_wback_inv(phys_addr_t paddr, size_t size)
91+
{
92+
THEAD_CMO_OP(FLUSH, paddr, size, riscv_cbom_block_size);
93+
}
94+
95+
static const struct riscv_nonstd_cache_ops thead_errata_cmo_ops = {
96+
.wback = &thead_errata_cache_wback,
97+
.inv = &thead_errata_cache_inv,
98+
.wback_inv = &thead_errata_cache_wback_inv,
99+
};
100+
36101
static bool errata_probe_cmo(unsigned int stage,
37102
unsigned long arch_id, unsigned long impid)
38103
{
@@ -48,6 +113,7 @@ static bool errata_probe_cmo(unsigned int stage,
48113
if (stage == RISCV_ALTERNATIVES_BOOT) {
49114
riscv_cbom_block_size = L1_CACHE_BYTES;
50115
riscv_noncoherent_supported();
116+
riscv_noncoherent_register_cache_ops(&thead_errata_cmo_ops);
51117
}
52118

53119
return true;
@@ -77,8 +143,7 @@ static u32 thead_errata_probe(unsigned int stage,
77143
if (errata_probe_pbmt(stage, archid, impid))
78144
cpu_req_errata |= BIT(ERRATA_THEAD_PBMT);
79145

80-
if (errata_probe_cmo(stage, archid, impid))
81-
cpu_req_errata |= BIT(ERRATA_THEAD_CMO);
146+
errata_probe_cmo(stage, archid, impid);
82147

83148
if (errata_probe_pmu(stage, archid, impid))
84149
cpu_req_errata |= BIT(ERRATA_THEAD_PMU);

‎arch/riscv/include/asm/arch_hweight.h

+78
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,78 @@
1+
/* SPDX-License-Identifier: GPL-2.0 */
2+
/*
3+
* Based on arch/x86/include/asm/arch_hweight.h
4+
*/
5+
6+
#ifndef _ASM_RISCV_HWEIGHT_H
7+
#define _ASM_RISCV_HWEIGHT_H
8+
9+
#include <asm/alternative-macros.h>
10+
#include <asm/hwcap.h>
11+
12+
#if (BITS_PER_LONG == 64)
13+
#define CPOPW "cpopw "
14+
#elif (BITS_PER_LONG == 32)
15+
#define CPOPW "cpop "
16+
#else
17+
#error "Unexpected BITS_PER_LONG"
18+
#endif
19+
20+
static __always_inline unsigned int __arch_hweight32(unsigned int w)
21+
{
22+
#ifdef CONFIG_RISCV_ISA_ZBB
23+
asm_volatile_goto(ALTERNATIVE("j %l[legacy]", "nop", 0,
24+
RISCV_ISA_EXT_ZBB, 1)
25+
: : : : legacy);
26+
27+
asm (".option push\n"
28+
".option arch,+zbb\n"
29+
CPOPW "%0, %0\n"
30+
".option pop\n"
31+
: "+r" (w) : :);
32+
33+
return w;
34+
35+
legacy:
36+
#endif
37+
return __sw_hweight32(w);
38+
}
39+
40+
static inline unsigned int __arch_hweight16(unsigned int w)
41+
{
42+
return __arch_hweight32(w & 0xffff);
43+
}
44+
45+
static inline unsigned int __arch_hweight8(unsigned int w)
46+
{
47+
return __arch_hweight32(w & 0xff);
48+
}
49+
50+
#if BITS_PER_LONG == 64
51+
static __always_inline unsigned long __arch_hweight64(__u64 w)
52+
{
53+
# ifdef CONFIG_RISCV_ISA_ZBB
54+
asm_volatile_goto(ALTERNATIVE("j %l[legacy]", "nop", 0,
55+
RISCV_ISA_EXT_ZBB, 1)
56+
: : : : legacy);
57+
58+
asm (".option push\n"
59+
".option arch,+zbb\n"
60+
"cpop %0, %0\n"
61+
".option pop\n"
62+
: "+r" (w) : :);
63+
64+
return w;
65+
66+
legacy:
67+
# endif
68+
return __sw_hweight64(w);
69+
}
70+
#else /* BITS_PER_LONG == 64 */
71+
static inline unsigned long __arch_hweight64(__u64 w)
72+
{
73+
return __arch_hweight32((u32)w) +
74+
__arch_hweight32((u32)(w >> 32));
75+
}
76+
#endif /* !(BITS_PER_LONG == 64) */
77+
78+
#endif /* _ASM_RISCV_HWEIGHT_H */

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