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@seldridge seldridge released this 26 Jul 16:48
· 651 commits to main since this release
firtool-1.79.0
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seldridge Schuyler Eldridge
GPG key ID: 50C5E9936AAD536D
Learn about vigilant mode.
a4730e5

What's Changed

  • [ESI][Runtime] Publish Windows wheels by @teqdruid in #7363
  • [firtool][test] Check layer specialization options work. by @dtzSiFive in #7364
  • [SV][ExportVerilog] Add UnpackedOpenArrayType, cast op and emission by @uenoku in #7304
  • [ImportVerilog] Add basic function support by @fabianschuiki in #7349
  • [FIRRTL] Support layer-colored probes in force, force_initial. by @dtzSiFive in #7371
  • [PrepareForEmission][Prettify] Extend allowExprInClock to handle new verif ops by @uenoku in #7332
  • [FIRRTL] Add lowering support for inline layers by @rwy7 in #7322
  • [CI] Report failure of clang-tidy by @rwy7 in #7355
  • [ImportVerilog] Fix use after free by @fzi-hielscher in #7368
  • [StringDebugInfoPred] Workaround FusedLoc bytecode issue by @uenoku in #7375
  • [Seq] Fix ClockConstAttr definition to pass roundstrip test by @uenoku in #7379
  • [ESI runtime] Host memory service by @teqdruid in #7367
  • [CI][lit] Enable roundtrip tests in CI by @uenoku in #7377
  • [ESI] Separate data delay from signaling standard by @teqdruid in #7354
  • [Moore] Distinguish the dynamic and constant extract. by @hailongSun2000 in #7340
  • [circt-bmc] Add LowerToBMC Pass by @TaoBi22 in #7343
  • [FIRRTL][ProbesToSignals] Add pass to replace probes with signals. by @dtzSiFive in #7342

Full Changelog: firtool-1.78.1...firtool-1.79.0

What's Changed

  • [ESI][Runtime] Publish Windows wheels by @teqdruid in #7363
  • [firtool][test] Check layer specialization options work. by @dtzSiFive in #7364
  • [SV][ExportVerilog] Add UnpackedOpenArrayType, cast op and emission by @uenoku in #7304
  • [ImportVerilog] Add basic function support by @fabianschuiki in #7349
  • [FIRRTL] Support layer-colored probes in force, force_initial. by @dtzSiFive in #7371
  • [PrepareForEmission][Prettify] Extend allowExprInClock to handle new verif ops by @uenoku in #7332
  • [FIRRTL] Add lowering support for inline layers by @rwy7 in #7322
  • [CI] Report failure of clang-tidy by @rwy7 in #7355
  • [ImportVerilog] Fix use after free by @fzi-hielscher in #7368
  • [StringDebugInfoPred] Workaround FusedLoc bytecode issue by @uenoku in #7375
  • [Seq] Fix ClockConstAttr definition to pass roundstrip test by @uenoku in #7379
  • [ESI runtime] Host memory service by @teqdruid in #7367
  • [CI][lit] Enable roundtrip tests in CI by @uenoku in #7377
  • [ESI] Separate data delay from signaling standard by @teqdruid in #7354
  • [Moore] Distinguish the dynamic and constant extract. by @hailongSun2000 in #7340
  • [circt-bmc] Add LowerToBMC Pass by @TaoBi22 in #7343
  • [FIRRTL][ProbesToSignals] Add pass to replace probes with signals. by @dtzSiFive in #7342

Full Changelog: firtool-1.78.1...firtool-1.79.0

Contributors

fabianschuiki, teqdruid, and 6 other contributors
Assets 20
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