-
Notifications
You must be signed in to change notification settings - Fork 186
/
rtw8703b.c
2077 lines (1816 loc) · 62 KB
/
rtw8703b.c
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
/* Copyright Fiona Klute <[email protected]> */
#include <linux/of.h>
#include <linux/of_net.h>
#include "main.h"
#include "coex.h"
#include "debug.h"
#include "mac.h"
#include "phy.h"
#include "reg.h"
#include "rx.h"
#include "rtw8703b.h"
#include "rtw8703b_tables.h"
#include "rtw8723x.h"
#define BIT_MASK_TXQ_INIT (BIT(7))
#define WLAN_RL_VAL 0x3030
/* disable BAR */
#define WLAN_BAR_VAL 0x0201ffff
#define WLAN_PIFS_VAL 0
#define WLAN_RX_PKT_LIMIT 0x18
#define WLAN_SLOT_TIME 0x09
#define WLAN_SPEC_SIFS 0x100a
#define WLAN_MAX_AGG_NR 0x1f
#define WLAN_AMPDU_MAX_TIME 0x70
/* unit is 32us */
#define TBTT_PROHIBIT_SETUP_TIME 0x04
#define TBTT_PROHIBIT_HOLD_TIME 0x80
#define TBTT_PROHIBIT_HOLD_TIME_STOP_BCN 0x64
#define TRANS_SEQ_END \
0xFFFF, \
RTW_PWR_CUT_ALL_MSK, \
RTW_PWR_INTF_ALL_MSK, \
0, \
RTW_PWR_CMD_END, 0, 0
/* rssi in percentage % (dbm = % - 100) */
/* These are used to select simple signal quality levels, might need
* tweaking. Same for rf_para tables below.
*/
static const u8 wl_rssi_step_8703b[] = {60, 50, 44, 30};
static const u8 bt_rssi_step_8703b[] = {30, 30, 30, 30};
static const struct coex_5g_afh_map afh_5g_8703b[] = { {0, 0, 0} };
/* Actually decreasing wifi TX power/RX gain isn't implemented in
* rtw8703b, but hopefully adjusting the BT side helps.
*/
static const struct coex_rf_para rf_para_tx_8703b[] = {
{0, 0, false, 7}, /* for normal */
{0, 10, false, 7}, /* for WL-CPT */
{1, 0, true, 4},
{1, 2, true, 4},
{1, 10, true, 4},
{1, 15, true, 4}
};
static const struct coex_rf_para rf_para_rx_8703b[] = {
{0, 0, false, 7}, /* for normal */
{0, 10, false, 7}, /* for WL-CPT */
{1, 0, true, 5},
{1, 2, true, 5},
{1, 10, true, 5},
{1, 15, true, 5}
};
static const u32 rtw8703b_ofdm_swing_table[] = {
0x0b40002d, /* 0, -15.0dB */
0x0c000030, /* 1, -14.5dB */
0x0cc00033, /* 2, -14.0dB */
0x0d800036, /* 3, -13.5dB */
0x0e400039, /* 4, -13.0dB */
0x0f00003c, /* 5, -12.5dB */
0x10000040, /* 6, -12.0dB */
0x11000044, /* 7, -11.5dB */
0x12000048, /* 8, -11.0dB */
0x1300004c, /* 9, -10.5dB */
0x14400051, /* 10, -10.0dB */
0x15800056, /* 11, -9.5dB */
0x16c0005b, /* 12, -9.0dB */
0x18000060, /* 13, -8.5dB */
0x19800066, /* 14, -8.0dB */
0x1b00006c, /* 15, -7.5dB */
0x1c800072, /* 16, -7.0dB */
0x1e400079, /* 17, -6.5dB */
0x20000080, /* 18, -6.0dB */
0x22000088, /* 19, -5.5dB */
0x24000090, /* 20, -5.0dB */
0x26000098, /* 21, -4.5dB */
0x288000a2, /* 22, -4.0dB */
0x2ac000ab, /* 23, -3.5dB */
0x2d4000b5, /* 24, -3.0dB */
0x300000c0, /* 25, -2.5dB */
0x32c000cb, /* 26, -2.0dB */
0x35c000d7, /* 27, -1.5dB */
0x390000e4, /* 28, -1.0dB */
0x3c8000f2, /* 29, -0.5dB */
0x40000100, /* 30, +0dB */
0x43c0010f, /* 31, +0.5dB */
0x47c0011f, /* 32, +1.0dB */
0x4c000130, /* 33, +1.5dB */
0x50800142, /* 34, +2.0dB */
0x55400155, /* 35, +2.5dB */
0x5a400169, /* 36, +3.0dB */
0x5fc0017f, /* 37, +3.5dB */
0x65400195, /* 38, +4.0dB */
0x6b8001ae, /* 39, +4.5dB */
0x71c001c7, /* 40, +5.0dB */
0x788001e2, /* 41, +5.5dB */
0x7f8001fe /* 42, +6.0dB */
};
static const u32 rtw8703b_cck_pwr_regs[] = {
0x0a22, 0x0a23, 0x0a24, 0x0a25, 0x0a26, 0x0a27, 0x0a28, 0x0a29,
0x0a9a, 0x0a9b, 0x0a9c, 0x0a9d, 0x0aa0, 0x0aa1, 0x0aa2, 0x0aa3,
};
static const u8 rtw8703b_cck_swing_table[][16] = {
{0x44, 0x42, 0x3C, 0x33, 0x28, 0x1C, 0x13, 0x0B, 0x05, 0x02,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-16dB*/
{0x48, 0x46, 0x3F, 0x36, 0x2A, 0x1E, 0x14, 0x0B, 0x05, 0x02,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15.5dB*/
{0x4D, 0x4A, 0x43, 0x39, 0x2C, 0x20, 0x15, 0x0C, 0x06, 0x02,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15dB*/
{0x51, 0x4F, 0x47, 0x3C, 0x2F, 0x22, 0x16, 0x0D, 0x06, 0x02,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14.5dB*/
{0x56, 0x53, 0x4B, 0x40, 0x32, 0x24, 0x17, 0x0E, 0x06, 0x02,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14dB*/
{0x5B, 0x58, 0x50, 0x43, 0x35, 0x26, 0x19, 0x0E, 0x07, 0x02,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13.5dB*/
{0x60, 0x5D, 0x54, 0x47, 0x38, 0x28, 0x1A, 0x0F, 0x07, 0x02,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13dB*/
{0x66, 0x63, 0x59, 0x4C, 0x3B, 0x2B, 0x1C, 0x10, 0x08, 0x02,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12.5dB*/
{0x6C, 0x69, 0x5F, 0x50, 0x3F, 0x2D, 0x1E, 0x11, 0x08, 0x03,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12dB*/
{0x73, 0x6F, 0x64, 0x55, 0x42, 0x30, 0x1F, 0x12, 0x08, 0x03,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11.5dB*/
{0x79, 0x76, 0x6A, 0x5A, 0x46, 0x33, 0x21, 0x13, 0x09, 0x03,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11dB*/
{0x81, 0x7C, 0x71, 0x5F, 0x4A, 0x36, 0x23, 0x14, 0x0A, 0x03,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10.5dB*/
{0x88, 0x84, 0x77, 0x65, 0x4F, 0x39, 0x25, 0x15, 0x0A, 0x03,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10dB*/
{0x90, 0x8C, 0x7E, 0x6B, 0x54, 0x3C, 0x27, 0x17, 0x0B, 0x03,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9.5dB*/
{0x99, 0x94, 0x86, 0x71, 0x58, 0x40, 0x2A, 0x18, 0x0B, 0x04,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9dB*/
{0xA2, 0x9D, 0x8E, 0x78, 0x5E, 0x43, 0x2C, 0x19, 0x0C, 0x04,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8.5dB*/
{0xAC, 0xA6, 0x96, 0x7F, 0x63, 0x47, 0x2F, 0x1B, 0x0D, 0x04,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8dB*/
{0xB6, 0xB0, 0x9F, 0x87, 0x69, 0x4C, 0x32, 0x1D, 0x0D, 0x04,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7.5dB*/
{0xC1, 0xBA, 0xA8, 0x8F, 0x6F, 0x50, 0x35, 0x1E, 0x0E, 0x04,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7dB*/
{0xCC, 0xC5, 0xB2, 0x97, 0x76, 0x55, 0x38, 0x20, 0x0F, 0x05,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-6.5dB*/
{0xD8, 0xD1, 0xBD, 0xA0, 0x7D, 0x5A, 0x3B, 0x22, 0x10, 0x05,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00} /*-6dB*/
};
#define RTW_OFDM_SWING_TABLE_SIZE ARRAY_SIZE(rtw8703b_ofdm_swing_table)
#define RTW_CCK_SWING_TABLE_SIZE ARRAY_SIZE(rtw8703b_cck_swing_table)
static const struct rtw_pwr_seq_cmd trans_pre_enable_8703b[] = {
/* set up external crystal (XTAL) */
{REG_PAD_CTRL1 + 2,
RTW_PWR_CUT_ALL_MSK,
RTW_PWR_INTF_ALL_MSK,
RTW_PWR_ADDR_MAC,
RTW_PWR_CMD_WRITE, BIT(7), BIT(7)},
/* set CLK_REQ to high active */
{0x0069,
RTW_PWR_CUT_ALL_MSK,
RTW_PWR_INTF_ALL_MSK,
RTW_PWR_ADDR_MAC,
RTW_PWR_CMD_WRITE, BIT(5), BIT(5)},
/* unlock ISO/CLK/power control register */
{REG_RSV_CTRL,
RTW_PWR_CUT_ALL_MSK,
RTW_PWR_INTF_ALL_MSK,
RTW_PWR_ADDR_MAC,
RTW_PWR_CMD_WRITE, 0xff, 0},
{TRANS_SEQ_END},
};
static const struct rtw_pwr_seq_cmd trans_carddis_to_cardemu_8703b[] = {
{0x0005,
RTW_PWR_CUT_ALL_MSK,
RTW_PWR_INTF_ALL_MSK,
RTW_PWR_ADDR_MAC,
RTW_PWR_CMD_WRITE, BIT(7), 0},
{TRANS_SEQ_END},
};
static const struct rtw_pwr_seq_cmd trans_cardemu_to_carddis_8703b[] = {
{0x0023,
RTW_PWR_CUT_ALL_MSK,
RTW_PWR_INTF_SDIO_MSK,
RTW_PWR_ADDR_MAC,
RTW_PWR_CMD_WRITE, BIT(4), BIT(4)},
{0x0007,
RTW_PWR_CUT_ALL_MSK,
RTW_PWR_INTF_SDIO_MSK | RTW_PWR_INTF_USB_MSK,
RTW_PWR_ADDR_MAC,
RTW_PWR_CMD_WRITE, 0xFF, 0x20},
{0x0006,
RTW_PWR_CUT_ALL_MSK,
RTW_PWR_INTF_ALL_MSK,
RTW_PWR_ADDR_MAC,
RTW_PWR_CMD_WRITE, BIT(0), 0},
{0x0005,
RTW_PWR_CUT_ALL_MSK,
RTW_PWR_INTF_ALL_MSK,
RTW_PWR_ADDR_MAC,
RTW_PWR_CMD_WRITE, BIT(7), BIT(7)},
{TRANS_SEQ_END},
};
static const struct rtw_pwr_seq_cmd trans_cardemu_to_act_8703b[] = {
{0x0020,
RTW_PWR_CUT_ALL_MSK,
RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK,
RTW_PWR_ADDR_MAC,
RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
{0x0067,
RTW_PWR_CUT_ALL_MSK,
RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK,
RTW_PWR_ADDR_MAC,
RTW_PWR_CMD_WRITE, BIT(4), 0},
{0x0001,
RTW_PWR_CUT_ALL_MSK,
RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK,
RTW_PWR_ADDR_MAC,
RTW_PWR_CMD_DELAY, 1, RTW_PWR_DELAY_MS},
{0x0000,
RTW_PWR_CUT_ALL_MSK,
RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK,
RTW_PWR_ADDR_MAC,
RTW_PWR_CMD_WRITE, BIT(5), 0},
{0x0005,
RTW_PWR_CUT_ALL_MSK,
RTW_PWR_INTF_ALL_MSK,
RTW_PWR_ADDR_MAC,
RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3) | BIT(2)), 0},
{0x0075,
RTW_PWR_CUT_ALL_MSK,
RTW_PWR_INTF_PCI_MSK,
RTW_PWR_ADDR_MAC,
RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
{0x0004,
RTW_PWR_CUT_ALL_MSK,
RTW_PWR_INTF_PCI_MSK,
RTW_PWR_ADDR_MAC,
RTW_PWR_CMD_WRITE, BIT(3), BIT(3)},
{0x0004,
RTW_PWR_CUT_ALL_MSK,
RTW_PWR_INTF_PCI_MSK,
RTW_PWR_ADDR_MAC,
RTW_PWR_CMD_WRITE, BIT(3), 0},
/* wait for power ready */
{0x0006,
RTW_PWR_CUT_ALL_MSK,
RTW_PWR_INTF_ALL_MSK,
RTW_PWR_ADDR_MAC,
RTW_PWR_CMD_POLLING, BIT(1), BIT(1)},
{0x0075,
RTW_PWR_CUT_ALL_MSK,
RTW_PWR_INTF_PCI_MSK,
RTW_PWR_ADDR_MAC,
RTW_PWR_CMD_WRITE, BIT(0), 0},
{0x0006,
RTW_PWR_CUT_ALL_MSK,
RTW_PWR_INTF_ALL_MSK,
RTW_PWR_ADDR_MAC,
RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
{0x0005,
RTW_PWR_CUT_ALL_MSK,
RTW_PWR_INTF_ALL_MSK,
RTW_PWR_ADDR_MAC,
RTW_PWR_CMD_WRITE, BIT(7), 0},
{0x0005,
RTW_PWR_CUT_ALL_MSK,
RTW_PWR_INTF_ALL_MSK,
RTW_PWR_ADDR_MAC,
RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3)), 0},
{0x0005,
RTW_PWR_CUT_ALL_MSK,
RTW_PWR_INTF_ALL_MSK,
RTW_PWR_ADDR_MAC,
RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
{0x0005,
RTW_PWR_CUT_ALL_MSK,
RTW_PWR_INTF_ALL_MSK,
RTW_PWR_ADDR_MAC,
RTW_PWR_CMD_POLLING, BIT(0), 0},
{0x0010,
RTW_PWR_CUT_ALL_MSK,
RTW_PWR_INTF_ALL_MSK,
RTW_PWR_ADDR_MAC,
RTW_PWR_CMD_WRITE, BIT(6), BIT(6)},
{0x0049,
RTW_PWR_CUT_ALL_MSK,
RTW_PWR_INTF_ALL_MSK,
RTW_PWR_ADDR_MAC,
RTW_PWR_CMD_WRITE, BIT(1), BIT(1)},
{0x0063,
RTW_PWR_CUT_ALL_MSK,
RTW_PWR_INTF_ALL_MSK,
RTW_PWR_ADDR_MAC,
RTW_PWR_CMD_WRITE, BIT(1), BIT(1)},
{0x0062,
RTW_PWR_CUT_ALL_MSK,
RTW_PWR_INTF_ALL_MSK,
RTW_PWR_ADDR_MAC,
RTW_PWR_CMD_WRITE, BIT(1), 0},
{0x0058,
RTW_PWR_CUT_ALL_MSK,
RTW_PWR_INTF_ALL_MSK,
RTW_PWR_ADDR_MAC,
RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
{0x005A,
RTW_PWR_CUT_ALL_MSK,
RTW_PWR_INTF_ALL_MSK,
RTW_PWR_ADDR_MAC,
RTW_PWR_CMD_WRITE, BIT(1), BIT(1)},
{0x0068,
RTW_PWR_CUT_TEST_MSK,
RTW_PWR_INTF_ALL_MSK,
RTW_PWR_ADDR_MAC,
RTW_PWR_CMD_WRITE, BIT(3), BIT(3)},
{0x0069,
RTW_PWR_CUT_ALL_MSK,
RTW_PWR_INTF_ALL_MSK,
RTW_PWR_ADDR_MAC,
RTW_PWR_CMD_WRITE, BIT(6), BIT(6)},
{TRANS_SEQ_END},
};
static const struct rtw_pwr_seq_cmd trans_act_to_cardemu_8703b[] = {
{0x001f,
RTW_PWR_CUT_ALL_MSK,
RTW_PWR_INTF_ALL_MSK,
RTW_PWR_ADDR_MAC,
RTW_PWR_CMD_WRITE, 0xff, 0},
{0x0049,
RTW_PWR_CUT_ALL_MSK,
RTW_PWR_INTF_ALL_MSK,
RTW_PWR_ADDR_MAC,
RTW_PWR_CMD_WRITE, BIT(1), 0},
{0x0006,
RTW_PWR_CUT_ALL_MSK,
RTW_PWR_INTF_ALL_MSK,
RTW_PWR_ADDR_MAC,
RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
{0x0005,
RTW_PWR_CUT_ALL_MSK,
RTW_PWR_INTF_ALL_MSK,
RTW_PWR_ADDR_MAC,
RTW_PWR_CMD_WRITE, BIT(1), BIT(1)},
{0x0005,
RTW_PWR_CUT_ALL_MSK,
RTW_PWR_INTF_ALL_MSK,
RTW_PWR_ADDR_MAC,
RTW_PWR_CMD_POLLING, BIT(1), 0},
{0x0010,
RTW_PWR_CUT_ALL_MSK,
RTW_PWR_INTF_ALL_MSK,
RTW_PWR_ADDR_MAC,
RTW_PWR_CMD_WRITE, BIT(6), 0},
{0x0000,
RTW_PWR_CUT_ALL_MSK,
RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK,
RTW_PWR_ADDR_MAC,
RTW_PWR_CMD_WRITE, BIT(5), BIT(5)},
{0x0020,
RTW_PWR_CUT_ALL_MSK,
RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK,
RTW_PWR_ADDR_MAC,
RTW_PWR_CMD_WRITE, BIT(0), 0},
{TRANS_SEQ_END},
};
static const struct rtw_pwr_seq_cmd trans_act_to_reset_mcu_8703b[] = {
{REG_SYS_FUNC_EN + 1,
RTW_PWR_CUT_ALL_MSK,
RTW_PWR_INTF_SDIO_MSK,
RTW_PWR_ADDR_MAC,
RTW_PWR_CMD_WRITE, BIT_FEN_CPUEN, 0},
/* reset MCU ready */
{REG_MCUFW_CTRL,
RTW_PWR_CUT_ALL_MSK,
RTW_PWR_INTF_SDIO_MSK,
RTW_PWR_ADDR_MAC,
RTW_PWR_CMD_WRITE, 0xff, 0},
/* reset MCU IO wrapper */
{REG_RSV_CTRL + 1,
RTW_PWR_CUT_ALL_MSK,
RTW_PWR_INTF_SDIO_MSK,
RTW_PWR_ADDR_MAC,
RTW_PWR_CMD_WRITE, BIT(0), 0},
{REG_RSV_CTRL + 1,
RTW_PWR_CUT_ALL_MSK,
RTW_PWR_INTF_SDIO_MSK,
RTW_PWR_ADDR_MAC,
RTW_PWR_CMD_WRITE, BIT(0), 1},
{TRANS_SEQ_END},
};
static const struct rtw_pwr_seq_cmd trans_act_to_lps_8703b[] = {
{0x0301,
RTW_PWR_CUT_ALL_MSK,
RTW_PWR_INTF_ALL_MSK,
RTW_PWR_ADDR_MAC,
RTW_PWR_CMD_WRITE, 0xff, 0xff},
{0x0522,
RTW_PWR_CUT_ALL_MSK,
RTW_PWR_INTF_ALL_MSK,
RTW_PWR_ADDR_MAC,
RTW_PWR_CMD_WRITE, 0xff, 0xff},
{0x05f8,
RTW_PWR_CUT_ALL_MSK,
RTW_PWR_INTF_ALL_MSK,
RTW_PWR_ADDR_MAC,
RTW_PWR_CMD_POLLING, 0xff, 0},
{0x05f9,
RTW_PWR_CUT_ALL_MSK,
RTW_PWR_INTF_ALL_MSK,
RTW_PWR_ADDR_MAC,
RTW_PWR_CMD_POLLING, 0xff, 0},
{0x05fa,
RTW_PWR_CUT_ALL_MSK,
RTW_PWR_INTF_ALL_MSK,
RTW_PWR_ADDR_MAC,
RTW_PWR_CMD_POLLING, 0xff, 0},
{0x05fb,
RTW_PWR_CUT_ALL_MSK,
RTW_PWR_INTF_ALL_MSK,
RTW_PWR_ADDR_MAC,
RTW_PWR_CMD_POLLING, 0xff, 0},
{0x0002,
RTW_PWR_CUT_ALL_MSK,
RTW_PWR_INTF_ALL_MSK,
RTW_PWR_ADDR_MAC,
RTW_PWR_CMD_WRITE, BIT(0), 0},
{0x0002,
RTW_PWR_CUT_ALL_MSK,
RTW_PWR_INTF_ALL_MSK,
RTW_PWR_ADDR_MAC,
RTW_PWR_CMD_DELAY, 0, RTW_PWR_DELAY_US},
{0x0002,
RTW_PWR_CUT_ALL_MSK,
RTW_PWR_INTF_ALL_MSK,
RTW_PWR_ADDR_MAC,
RTW_PWR_CMD_WRITE, BIT(1), 0},
{0x0100,
RTW_PWR_CUT_ALL_MSK,
RTW_PWR_INTF_ALL_MSK,
RTW_PWR_ADDR_MAC,
RTW_PWR_CMD_WRITE, 0xff, 0x03},
{0x0101,
RTW_PWR_CUT_ALL_MSK,
RTW_PWR_INTF_ALL_MSK,
RTW_PWR_ADDR_MAC,
RTW_PWR_CMD_WRITE, BIT(1), 0},
{0x0093,
RTW_PWR_CUT_ALL_MSK,
RTW_PWR_INTF_SDIO_MSK,
RTW_PWR_ADDR_MAC,
RTW_PWR_CMD_WRITE, 0xff, 0},
{0x0553,
RTW_PWR_CUT_ALL_MSK,
RTW_PWR_INTF_ALL_MSK,
RTW_PWR_ADDR_MAC,
RTW_PWR_CMD_WRITE, BIT(5), BIT(5)},
{TRANS_SEQ_END},
};
static const struct rtw_pwr_seq_cmd * const card_enable_flow_8703b[] = {
trans_pre_enable_8703b,
trans_carddis_to_cardemu_8703b,
trans_cardemu_to_act_8703b,
NULL
};
static const struct rtw_pwr_seq_cmd * const card_disable_flow_8703b[] = {
trans_act_to_lps_8703b,
trans_act_to_reset_mcu_8703b,
trans_act_to_cardemu_8703b,
trans_cardemu_to_carddis_8703b,
NULL
};
static const struct rtw_page_table page_table_8703b[] = {
{12, 2, 2, 0, 1},
{12, 2, 2, 0, 1},
{12, 2, 2, 0, 1},
{12, 2, 2, 0, 1},
{12, 2, 2, 0, 1},
};
static const struct rtw_rqpn rqpn_table_8703b[] = {
{RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL,
RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW,
RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH},
{RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL,
RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW,
RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH},
{RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL,
RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_HIGH,
RTW_DMA_MAPPING_HIGH, RTW_DMA_MAPPING_HIGH},
{RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL,
RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW,
RTW_DMA_MAPPING_HIGH, RTW_DMA_MAPPING_HIGH},
{RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL,
RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW,
RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH},
};
/* Default power index table for RTL8703B, used if EFUSE does not
* contain valid data. Replaces EFUSE data from offset 0x10 (start of
* txpwr_idx_table).
*/
static const u8 rtw8703b_txpwr_idx_table[] = {
0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D,
0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x02
};
static void try_mac_from_devicetree(struct rtw_dev *rtwdev)
{
struct device_node *node = rtwdev->dev->of_node;
struct rtw_efuse *efuse = &rtwdev->efuse;
#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 13, 0)
int ret;
#else
const void *ret;
#endif
if (node) {
#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 13, 0)
ret = of_get_mac_address(node, efuse->addr);
if (ret == 0) {
#else
ret = of_get_mac_address(node);
if (!IS_ERR(ret)) {
ether_addr_copy(efuse->addr, ret);
#endif
rtw_dbg(rtwdev, RTW_DBG_EFUSE,
"got wifi mac address from DT: %pM\n",
efuse->addr);
}
}
}
#define DBG_EFUSE_FIX(rtwdev, name) \
rtw_dbg(rtwdev, RTW_DBG_EFUSE, "Fixed invalid EFUSE value: " \
# name "=0x%x\n", rtwdev->efuse.name)
static int rtw8703b_read_efuse(struct rtw_dev *rtwdev, u8 *log_map)
{
struct rtw_efuse *efuse = &rtwdev->efuse;
u8 *pwr = (u8 *)efuse->txpwr_idx_table;
bool valid = false;
int ret;
ret = rtw8723x_read_efuse(rtwdev, log_map);
if (ret != 0)
return ret;
if (!is_valid_ether_addr(efuse->addr))
try_mac_from_devicetree(rtwdev);
/* If TX power index table in EFUSE is invalid, fall back to
* built-in table.
*/
for (int i = 0; i < ARRAY_SIZE(rtw8703b_txpwr_idx_table); i++)
if (pwr[i] != 0xff) {
valid = true;
break;
}
if (!valid) {
for (int i = 0; i < ARRAY_SIZE(rtw8703b_txpwr_idx_table); i++)
pwr[i] = rtw8703b_txpwr_idx_table[i];
rtw_dbg(rtwdev, RTW_DBG_EFUSE,
"Replaced invalid EFUSE TX power index table.");
rtw8723x_debug_txpwr_limit(rtwdev,
efuse->txpwr_idx_table, 2);
}
/* Override invalid antenna settings. */
if (efuse->bt_setting == 0xff) {
/* shared antenna */
efuse->bt_setting |= BIT(0);
/* RF path A */
efuse->bt_setting &= ~BIT(6);
DBG_EFUSE_FIX(rtwdev, bt_setting);
}
/* Override invalid board options: The coex code incorrectly
* assumes that if bits 6 & 7 are set the board doesn't
* support coex. Regd is also derived from rf_board_option and
* should be 0 if there's no valid data.
*/
if (efuse->rf_board_option == 0xff) {
efuse->regd = 0;
efuse->rf_board_option &= GENMASK(5, 0);
DBG_EFUSE_FIX(rtwdev, rf_board_option);
}
/* Override invalid crystal cap setting, default comes from
* vendor driver. Chip specific.
*/
if (efuse->crystal_cap == 0xff) {
efuse->crystal_cap = 0x20;
DBG_EFUSE_FIX(rtwdev, crystal_cap);
}
return 0;
}
static void rtw8703b_pwrtrack_init(struct rtw_dev *rtwdev)
{
struct rtw_dm_info *dm_info = &rtwdev->dm_info;
u8 path;
/* TODO: The vendor driver selects these using tables in
* halrf_powertracking_ce.c, functions are called
* get_swing_index and get_cck_swing_index. There the current
* fixed values are only the defaults in case no match is
* found.
*/
dm_info->default_ofdm_index = 30;
dm_info->default_cck_index = 20;
for (path = RF_PATH_A; path < rtwdev->hal.rf_path_num; path++) {
ewma_thermal_init(&dm_info->avg_thermal[path]);
dm_info->delta_power_index[path] = 0;
}
dm_info->pwr_trk_triggered = false;
dm_info->pwr_trk_init_trigger = true;
dm_info->thermal_meter_k = rtwdev->efuse.thermal_meter_k;
dm_info->txagc_remnant_cck = 0;
dm_info->txagc_remnant_ofdm[RF_PATH_A] = 0;
}
#if LINUX_VERSION_CODE < KERNEL_VERSION(6, 3, 0)
#define FIELD_PREP_CONST FIELD_PREP
#endif
static void rtw8703b_phy_set_param(struct rtw_dev *rtwdev)
{
u8 xtal_cap = rtwdev->efuse.crystal_cap & 0x3F;
/* power on BB/RF domain */
rtw_write16_set(rtwdev, REG_SYS_FUNC_EN,
BIT_FEN_EN_25_1 | BIT_FEN_BB_GLB_RST | BIT_FEN_BB_RSTB);
rtw_write8_set(rtwdev, REG_RF_CTRL,
BIT_RF_EN | BIT_RF_RSTB | BIT_RF_SDM_RSTB);
rtw_write_rf(rtwdev, RF_PATH_A, RF_WLINT, RFREG_MASK, 0x0780);
rtw_write8(rtwdev, REG_AFE_CTRL1 + 1, 0x80);
rtw_phy_load_tables(rtwdev);
rtw_write32_clr(rtwdev, REG_RCR, BIT_RCR_ADF);
/* 0xff is from vendor driver, rtw8723d uses
* BIT_HIQ_NO_LMT_EN_ROOT. Comment in vendor driver: "Packet
* in Hi Queue Tx immediately". I wonder if setting all bits
* is really necessary.
*/
rtw_write8_set(rtwdev, REG_HIQ_NO_LMT_EN, 0xff);
rtw_write16_set(rtwdev, REG_AFE_CTRL_4, BIT_CK320M_AFE_EN | BIT_EN_SYN);
rtw_write32_mask(rtwdev, REG_AFE_CTRL3, BIT_MASK_XTAL,
xtal_cap | (xtal_cap << 6));
rtw_write32_set(rtwdev, REG_FPGA0_RFMOD, BIT_CCKEN | BIT_OFDMEN);
/* Init EDCA */
rtw_write16(rtwdev, REG_SPEC_SIFS, WLAN_SPEC_SIFS);
rtw_write16(rtwdev, REG_MAC_SPEC_SIFS, WLAN_SPEC_SIFS);
rtw_write16(rtwdev, REG_SIFS, WLAN_SPEC_SIFS); /* CCK */
rtw_write16(rtwdev, REG_SIFS + 2, WLAN_SPEC_SIFS); /* OFDM */
/* TXOP */
rtw_write32(rtwdev, REG_EDCA_VO_PARAM, 0x002FA226);
rtw_write32(rtwdev, REG_EDCA_VI_PARAM, 0x005EA324);
rtw_write32(rtwdev, REG_EDCA_BE_PARAM, 0x005EA42B);
rtw_write32(rtwdev, REG_EDCA_BK_PARAM, 0x0000A44F);
/* Init retry */
rtw_write8(rtwdev, REG_ACKTO, 0x40);
/* Set up RX aggregation. sdio.c also sets DMA mode, but not
* the burst parameters.
*/
rtw_write8(rtwdev, REG_RXDMA_MODE,
BIT_DMA_MODE |
FIELD_PREP_CONST(BIT_MASK_AGG_BURST_NUM, AGG_BURST_NUM) |
FIELD_PREP_CONST(BIT_MASK_AGG_BURST_SIZE, AGG_BURST_SIZE));
/* Init beacon parameters */
rtw_write8(rtwdev, REG_BCN_CTRL,
BIT_DIS_TSF_UDT | BIT_EN_BCN_FUNCTION | BIT_EN_TXBCN_RPT);
rtw_write8(rtwdev, REG_TBTT_PROHIBIT, TBTT_PROHIBIT_SETUP_TIME);
rtw_write8(rtwdev, REG_TBTT_PROHIBIT + 1,
TBTT_PROHIBIT_HOLD_TIME_STOP_BCN & 0xFF);
rtw_write8(rtwdev, REG_TBTT_PROHIBIT + 2,
(rtw_read8(rtwdev, REG_TBTT_PROHIBIT + 2) & 0xF0)
| (TBTT_PROHIBIT_HOLD_TIME_STOP_BCN >> 8));
/* configure packet burst */
rtw_write8_set(rtwdev, REG_SINGLE_AMPDU_CTRL, BIT_EN_SINGLE_APMDU);
rtw_write8(rtwdev, REG_RX_PKT_LIMIT, WLAN_RX_PKT_LIMIT);
rtw_write8(rtwdev, REG_MAX_AGGR_NUM, WLAN_MAX_AGG_NR);
rtw_write8(rtwdev, REG_PIFS, WLAN_PIFS_VAL);
rtw_write8_clr(rtwdev, REG_FWHW_TXQ_CTRL, BIT_MASK_TXQ_INIT);
rtw_write8(rtwdev, REG_AMPDU_MAX_TIME, WLAN_AMPDU_MAX_TIME);
rtw_write8(rtwdev, REG_SLOT, WLAN_SLOT_TIME);
rtw_write16(rtwdev, REG_RETRY_LIMIT, WLAN_RL_VAL);
rtw_write32(rtwdev, REG_BAR_MODE_CTRL, WLAN_BAR_VAL);
rtw_write16(rtwdev, REG_ATIMWND, 0x2);
rtw_phy_init(rtwdev);
if (rtw_read32_mask(rtwdev, REG_BB_AMP, BIT_MASK_RX_LNA) != 0) {
rtwdev->dm_info.rx_cck_agc_report_type = 1;
} else {
rtwdev->dm_info.rx_cck_agc_report_type = 0;
rtw_warn(rtwdev, "unexpected cck agc report type");
}
rtw8723x_lck(rtwdev);
rtw_write32_mask(rtwdev, REG_OFDM0_XAAGC1, MASKBYTE0, 0x50);
rtw_write32_mask(rtwdev, REG_OFDM0_XAAGC1, MASKBYTE0, 0x20);
rtw8703b_pwrtrack_init(rtwdev);
}
static bool rtw8703b_check_spur_ov_thres(struct rtw_dev *rtwdev,
u32 freq, u32 thres)
{
bool ret = false;
rtw_write32(rtwdev, REG_ANALOG_P4, DIS_3WIRE);
rtw_write32(rtwdev, REG_PSDFN, freq);
rtw_write32(rtwdev, REG_PSDFN, START_PSD | freq);
msleep(30);
if (rtw_read32(rtwdev, REG_PSDRPT) >= thres)
ret = true;
rtw_write32(rtwdev, REG_PSDFN, freq);
rtw_write32(rtwdev, REG_ANALOG_P4, EN_3WIRE);
return ret;
}
static void rtw8703b_cfg_notch(struct rtw_dev *rtwdev, u8 channel, bool notch)
{
if (!notch) {
rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_MASK_RXDSP, 0x1f);
rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_EN_RXDSP, 0x0);
rtw_write32(rtwdev, REG_OFDM1_CSI1, 0x00000000);
rtw_write32(rtwdev, REG_OFDM1_CSI2, 0x00000000);
rtw_write32(rtwdev, REG_OFDM1_CSI3, 0x00000000);
rtw_write32(rtwdev, REG_OFDM1_CSI4, 0x00000000);
rtw_write32_mask(rtwdev, REG_OFDM1_CFOTRK, BIT_EN_CFOTRK, 0x0);
return;
}
switch (channel) {
case 5:
fallthrough;
case 13:
rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_MASK_RXDSP, 0xb);
rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_EN_RXDSP, 0x1);
rtw_write32(rtwdev, REG_OFDM1_CSI1, 0x06000000);
rtw_write32(rtwdev, REG_OFDM1_CSI2, 0x00000000);
rtw_write32(rtwdev, REG_OFDM1_CSI3, 0x00000000);
rtw_write32(rtwdev, REG_OFDM1_CSI4, 0x00000000);
rtw_write32_mask(rtwdev, REG_OFDM1_CFOTRK, BIT_EN_CFOTRK, 0x1);
break;
case 6:
rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_MASK_RXDSP, 0x4);
rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_EN_RXDSP, 0x1);
rtw_write32(rtwdev, REG_OFDM1_CSI1, 0x00000600);
rtw_write32(rtwdev, REG_OFDM1_CSI2, 0x00000000);
rtw_write32(rtwdev, REG_OFDM1_CSI3, 0x00000000);
rtw_write32(rtwdev, REG_OFDM1_CSI4, 0x00000000);
rtw_write32_mask(rtwdev, REG_OFDM1_CFOTRK, BIT_EN_CFOTRK, 0x1);
break;
case 7:
rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_MASK_RXDSP, 0x3);
rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_EN_RXDSP, 0x1);
rtw_write32(rtwdev, REG_OFDM1_CSI1, 0x00000000);
rtw_write32(rtwdev, REG_OFDM1_CSI2, 0x00000000);
rtw_write32(rtwdev, REG_OFDM1_CSI3, 0x00000000);
rtw_write32(rtwdev, REG_OFDM1_CSI4, 0x06000000);
rtw_write32_mask(rtwdev, REG_OFDM1_CFOTRK, BIT_EN_CFOTRK, 0x1);
break;
case 8:
rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_MASK_RXDSP, 0xa);
rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_EN_RXDSP, 0x1);
rtw_write32(rtwdev, REG_OFDM1_CSI1, 0x00000000);
rtw_write32(rtwdev, REG_OFDM1_CSI2, 0x00000000);
rtw_write32(rtwdev, REG_OFDM1_CSI3, 0x00000000);
rtw_write32(rtwdev, REG_OFDM1_CSI4, 0x00000380);
rtw_write32_mask(rtwdev, REG_OFDM1_CFOTRK, BIT_EN_CFOTRK, 0x1);
break;
case 14:
rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_MASK_RXDSP, 0x5);
rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_EN_RXDSP, 0x1);
rtw_write32(rtwdev, REG_OFDM1_CSI1, 0x00000000);
rtw_write32(rtwdev, REG_OFDM1_CSI2, 0x00000000);
rtw_write32(rtwdev, REG_OFDM1_CSI3, 0x00000000);
rtw_write32(rtwdev, REG_OFDM1_CSI4, 0x00180000);
rtw_write32_mask(rtwdev, REG_OFDM1_CFOTRK, BIT_EN_CFOTRK, 0x1);
break;
default:
rtw_warn(rtwdev,
"Bug: Notch filter enable called for channel %u!",
channel);
rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_EN_RXDSP, 0x0);
rtw_write32_mask(rtwdev, REG_OFDM1_CFOTRK, BIT_EN_CFOTRK, 0x0);
break;
}
}
static void rtw8703b_spur_cal(struct rtw_dev *rtwdev, u8 channel)
{
bool notch;
u32 freq;
if (channel == 5) {
freq = FREQ_CH5;
} else if (channel == 6) {
freq = FREQ_CH6;
} else if (channel == 7) {
freq = FREQ_CH7;
} else if (channel == 8) {
freq = FREQ_CH8;
} else if (channel == 13) {
freq = FREQ_CH13;
} else if (channel == 14) {
freq = FREQ_CH14;
} else {
rtw8703b_cfg_notch(rtwdev, channel, false);
return;
}
notch = rtw8703b_check_spur_ov_thres(rtwdev, freq, SPUR_THRES);
rtw8703b_cfg_notch(rtwdev, channel, notch);
}
static void rtw8703b_set_channel_rf(struct rtw_dev *rtwdev, u8 channel, u8 bw)
{
u32 rf_cfgch_a;
u32 rf_cfgch_b;
/* default value for 20M */
u32 rf_rck = 0x00000C08;
rf_cfgch_a = rtw_read_rf(rtwdev, RF_PATH_A, RF_CFGCH, RFREG_MASK);
rf_cfgch_b = rtw_read_rf(rtwdev, RF_PATH_B, RF_CFGCH, RFREG_MASK);
rf_cfgch_a &= ~RFCFGCH_CHANNEL_MASK;
rf_cfgch_b &= ~RFCFGCH_CHANNEL_MASK;
rf_cfgch_a |= (channel & RFCFGCH_CHANNEL_MASK);
rf_cfgch_b |= (channel & RFCFGCH_CHANNEL_MASK);
rf_cfgch_a &= ~RFCFGCH_BW_MASK;
switch (bw) {
case RTW_CHANNEL_WIDTH_20:
rf_cfgch_a |= RFCFGCH_BW_20M;
break;
case RTW_CHANNEL_WIDTH_40:
rf_cfgch_a |= RFCFGCH_BW_40M;
rf_rck = 0x00000C4C;
break;
default:
break;
}
rtw_write_rf(rtwdev, RF_PATH_A, RF_CFGCH, RFREG_MASK, rf_cfgch_a);
rtw_write_rf(rtwdev, RF_PATH_B, RF_CFGCH, RFREG_MASK, rf_cfgch_b);
rtw_write_rf(rtwdev, RF_PATH_A, RF_RCK1, RFREG_MASK, rf_rck);
rtw8703b_spur_cal(rtwdev, channel);
}
#define CCK_DFIR_NR_8703B 2
static const struct rtw_backup_info cck_dfir_cfg[][CCK_DFIR_NR_8703B] = {
[0] = {
{ .len = 4, .reg = REG_CCK_TXSF2, .val = 0x5A7DA0BD },
{ .len = 4, .reg = REG_CCK_DBG, .val = 0x0000223B },
},
[1] = {
{ .len = 4, .reg = REG_CCK_TXSF2, .val = 0x00000000 },
{ .len = 4, .reg = REG_CCK_DBG, .val = 0x00000000 },
},
};
static void rtw8703b_set_channel_bb(struct rtw_dev *rtwdev, u8 channel, u8 bw,
u8 primary_ch_idx)
{
const struct rtw_backup_info *cck_dfir;
int i;
cck_dfir = channel <= 13 ? cck_dfir_cfg[0] : cck_dfir_cfg[1];
for (i = 0; i < CCK_DFIR_NR_8703B; i++, cck_dfir++)
rtw_write32(rtwdev, cck_dfir->reg, cck_dfir->val);
switch (bw) {
case RTW_CHANNEL_WIDTH_20:
rtw_write32_mask(rtwdev, REG_FPGA0_RFMOD, BIT_MASK_RFMOD, 0x0);
rtw_write32_mask(rtwdev, REG_FPGA1_RFMOD, BIT_MASK_RFMOD, 0x0);
rtw_write32_mask(rtwdev, REG_OFDM0_TX_PSD_NOISE,
GENMASK(31, 20), 0x0);
rtw_write32(rtwdev, REG_BBRX_DFIR, 0x4A880000);
rtw_write32(rtwdev, REG_OFDM0_A_TX_AFE, 0x19F60000);
break;
case RTW_CHANNEL_WIDTH_40:
rtw_write32_mask(rtwdev, REG_FPGA0_RFMOD, BIT_MASK_RFMOD, 0x1);
rtw_write32_mask(rtwdev, REG_FPGA1_RFMOD, BIT_MASK_RFMOD, 0x1);
rtw_write32(rtwdev, REG_BBRX_DFIR, 0x40100000);
rtw_write32(rtwdev, REG_OFDM0_A_TX_AFE, 0x51F60000);
rtw_write32_mask(rtwdev, REG_CCK0_SYS, BIT_CCK_SIDE_BAND,
primary_ch_idx == RTW_SC_20_UPPER ? 1 : 0);
rtw_write32_mask(rtwdev, REG_OFDM_FA_RSTD_11N, 0xC00,
primary_ch_idx == RTW_SC_20_UPPER ? 2 : 1);
rtw_write32_mask(rtwdev, REG_BB_PWR_SAV5_11N, GENMASK(27, 26),
primary_ch_idx == RTW_SC_20_UPPER ? 1 : 2);
break;
default:
break;
}
}
static void rtw8703b_set_channel(struct rtw_dev *rtwdev, u8 channel,
u8 bw, u8 primary_chan_idx)
{
rtw8703b_set_channel_rf(rtwdev, channel, bw);
rtw_set_channel_mac(rtwdev, channel, bw, primary_chan_idx);
rtw8703b_set_channel_bb(rtwdev, channel, bw, primary_chan_idx);
}
/* Not all indices are valid, based on available data. None of the
* known valid values are positive, so use 0x7f as "invalid".
*/
#define LNA_IDX_INVALID 0x7f
static const s8 lna_gain_table[16] = {
-2, LNA_IDX_INVALID, LNA_IDX_INVALID, LNA_IDX_INVALID,
-6, LNA_IDX_INVALID, LNA_IDX_INVALID, -19,
-32, LNA_IDX_INVALID, -36, -42,
LNA_IDX_INVALID, LNA_IDX_INVALID, LNA_IDX_INVALID, -48,
};
static s8 get_cck_rx_pwr(struct rtw_dev *rtwdev, u8 lna_idx, u8 vga_idx)
{
s8 lna_gain = 0;
if (lna_idx < ARRAY_SIZE(lna_gain_table))
lna_gain = lna_gain_table[lna_idx];
if (lna_gain >= 0) {
rtw_warn(rtwdev, "incorrect lna index (%d)\n", lna_idx);
return -120;
}
return lna_gain - 2 * vga_idx;
}
static void query_phy_status_cck(struct rtw_dev *rtwdev, u8 *phy_raw,
struct rtw_rx_pkt_stat *pkt_stat)
{
struct phy_status_8703b *phy_status = (struct phy_status_8703b *)phy_raw;
u8 vga_idx = phy_status->cck_agc_rpt_ofdm_cfosho_a & VGA_BITS;
u8 lna_idx = phy_status->cck_agc_rpt_ofdm_cfosho_a & LNA_L_BITS;
s8 rx_power;
if (rtwdev->dm_info.rx_cck_agc_report_type == 1)
lna_idx = FIELD_PREP(BIT_LNA_H_MASK,
phy_status->cck_rpt_b_ofdm_cfosho_b & LNA_H_BIT)
| FIELD_PREP(BIT_LNA_L_MASK, lna_idx);
else
lna_idx = FIELD_PREP(BIT_LNA_L_MASK, lna_idx);
rx_power = get_cck_rx_pwr(rtwdev, lna_idx, vga_idx);
pkt_stat->rx_power[RF_PATH_A] = rx_power;
pkt_stat->rssi = rtw_phy_rf_power_2_rssi(pkt_stat->rx_power, 1);
rtwdev->dm_info.rssi[RF_PATH_A] = pkt_stat->rssi;
pkt_stat->signal_power = rx_power;
}
static void query_phy_status_ofdm(struct rtw_dev *rtwdev, u8 *phy_raw,
struct rtw_rx_pkt_stat *pkt_stat)