This is UART with an AXI-Stream inspired by https://github.com/alexforencich/verilog-uart. The prescale signal must be set to clk_freq/(16 * baudrate).
This is UART with an AXI-Stream inspired by https://github.com/alexforencich/verilog-uart. The prescale signal must be set to clk_freq/(16 * baudrate).