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NDS.cpp
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/*
Copyright 2016-2024 melonDS team
This file is part of melonDS.
melonDS is free software: you can redistribute it and/or modify it under
the terms of the GNU General Public License as published by the Free
Software Foundation, either version 3 of the License, or (at your option)
any later version.
melonDS is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
You should have received a copy of the GNU General Public License along
with melonDS. If not, see http://www.gnu.org/licenses/.
*/
#include <assert.h>
#include <stdio.h>
#include <string.h>
#include <inttypes.h>
#include "NDS.h"
#include "ARM.h"
#include "NDSCart.h"
#include "GBACart.h"
#include "DMA.h"
#include "FIFO.h"
#include "GPU.h"
#include "SPU.h"
#include "SPI.h"
#include "RTC.h"
#include "Wifi.h"
#include "AREngine.h"
#include "Platform.h"
#include "FreeBIOS.h"
#include "Args.h"
#include "version.h"
#include "DSi.h"
#include "DSi_SPI_TSC.h"
#include "DSi_NWifi.h"
#include "DSi_Camera.h"
#include "DSi_DSP.h"
#include "ARMJIT.h"
#include "ARMJIT_Memory.h"
namespace melonDS
{
using namespace Platform;
const s32 kMaxIterationCycles = 64;
const s32 kIterationCycleMargin = 8;
// timing notes
//
// * this implementation is technically wrong for VRAM
// each bank is considered a separate region
// but this would only matter in specific VRAM->VRAM DMA transfers or
// when running code in VRAM, which is way unlikely
//
// bus/basedelay/nspenalty
//
// bus types:
// * 0 / 32-bit: nothing special
// * 1 / 16-bit: 32-bit accesses split into two 16-bit accesses, second is always sequential
// * 2 / 8-bit/GBARAM: (presumably) split into multiple 8-bit accesses?
// * 3 / ARM9 internal: cache/TCM
//
// ARM9 always gets 3c nonseq penalty when using the bus (except for mainRAM where the penalty is 7c)
// /!\ 3c penalty doesn't apply to DMA!
//
// ARM7 only gets nonseq penalty when accessing mainRAM (7c as for ARM9)
//
// timings for GBA slot and wifi are set up at runtime
thread_local NDS* NDS::Current = nullptr;
NDS::NDS() noexcept :
NDS(
NDSArgs {
std::make_unique<ARM9BIOSImage>(bios_arm9_bin),
std::make_unique<ARM7BIOSImage>(bios_arm7_bin),
Firmware(0),
}
)
{
}
NDS::NDS(NDSArgs&& args, int type, void* userdata) noexcept :
ConsoleType(type),
UserData(userdata),
ARM7BIOS(*args.ARM7BIOS),
ARM9BIOS(*args.ARM9BIOS),
ARM7BIOSNative(CRC32(ARM7BIOS.data(), ARM7BIOS.size()) == ARM7BIOSCRC32),
ARM9BIOSNative(CRC32(ARM9BIOS.data(), ARM9BIOS.size()) == ARM9BIOSCRC32),
JIT(*this, args.JIT),
SPU(*this, args.BitDepth, args.Interpolation),
GPU(*this, std::move(args.Renderer3D)),
SPI(*this, std::move(args.Firmware)),
RTC(*this),
Wifi(*this),
NDSCartSlot(*this, nullptr),
GBACartSlot(*this, nullptr),
AREngine(*this),
ARM9(*this, args.GDB, args.JIT.has_value()),
ARM7(*this, args.GDB, args.JIT.has_value()),
#ifdef GDBSTUB_ENABLED
EnableGDBStub(args.GDB.has_value()),
#endif
#ifdef JIT_ENABLED
EnableJIT(args.JIT.has_value()),
#endif
DMAs {
DMA(0, 0, *this),
DMA(0, 1, *this),
DMA(0, 2, *this),
DMA(0, 3, *this),
DMA(1, 0, *this),
DMA(1, 1, *this),
DMA(1, 2, *this),
DMA(1, 3, *this),
}
{
RegisterEventFuncs(Event_Div, this, {MakeEventThunk(NDS, DivDone)});
RegisterEventFuncs(Event_Sqrt, this, {MakeEventThunk(NDS, SqrtDone)});
MainRAM = JIT.Memory.GetMainRAM();
SharedWRAM = JIT.Memory.GetSharedWRAM();
ARM7WRAM = JIT.Memory.GetARM7WRAM();
}
NDS::~NDS() noexcept
{
UnregisterEventFuncs(Event_Div);
UnregisterEventFuncs(Event_Sqrt);
// The destructor for each component is automatically called by the compiler
}
void NDS::SetARM9RegionTimings(u32 addrstart, u32 addrend, u32 region, int buswidth, int nonseq, int seq)
{
addrstart >>= 2;
addrend >>= 2;
int N16, S16, N32, S32, cpuN;
N16 = nonseq;
S16 = seq;
if (buswidth == 16)
{
N32 = N16 + S16;
S32 = S16 + S16;
}
else
{
N32 = N16;
S32 = S16;
}
// nonseq accesses on the CPU get a 3-cycle penalty for all regions except main RAM
cpuN = (region == Mem9_MainRAM) ? 0 : 3;
for (u32 i = addrstart; i < addrend; i++)
{
// CPU timings
ARM9MemTimings[i][0] = N16 + cpuN;
ARM9MemTimings[i][1] = S16;
ARM9MemTimings[i][2] = N32 + cpuN;
ARM9MemTimings[i][3] = S32;
// DMA timings
ARM9MemTimings[i][4] = N16;
ARM9MemTimings[i][5] = S16;
ARM9MemTimings[i][6] = N32;
ARM9MemTimings[i][7] = S32;
ARM9Regions[i] = region;
}
ARM9.UpdateRegionTimings(addrstart<<2, addrend<<2);
}
void NDS::SetARM7RegionTimings(u32 addrstart, u32 addrend, u32 region, int buswidth, int nonseq, int seq)
{
addrstart >>= 3;
addrend >>= 3;
int N16, S16, N32, S32;
N16 = nonseq;
S16 = seq;
if (buswidth == 16)
{
N32 = N16 + S16;
S32 = S16 + S16;
}
else
{
N32 = N16;
S32 = S16;
}
for (u32 i = addrstart; i < addrend; i++)
{
// CPU and DMA timings are the same
ARM7MemTimings[i][0] = N16;
ARM7MemTimings[i][1] = S16;
ARM7MemTimings[i][2] = N32;
ARM7MemTimings[i][3] = S32;
ARM7Regions[i] = region;
}
}
#ifdef JIT_ENABLED
void NDS::SetJITArgs(std::optional<JITArgs> args) noexcept
{
if (args)
{ // If we want to turn the JIT on...
JIT.SetJITArgs(*args);
}
else if (args.has_value() != EnableJIT)
{ // Else if we want to turn the JIT off, and it wasn't already off...
JIT.ResetBlockCache();
}
EnableJIT = args.has_value();
}
#endif
#ifdef GDBSTUB_ENABLED
void NDS::SetGdbArgs(std::optional<GDBArgs> args) noexcept
{
ARM9.SetGdbArgs(args);
ARM7.SetGdbArgs(args);
EnableGDBStub = args.has_value();
}
#endif
void NDS::InitTimings()
{
// TODO, eventually:
// VRAM is initially unmapped. The timings should be those of void regions.
// Similarly for any unmapped VRAM area.
// Need to check whether supporting these timing characteristics would impact performance
// (especially wrt VRAM mirroring and overlapping and whatnot).
// Also, each VRAM bank is its own memory region. This would matter when DMAing from a VRAM
// bank to another (if this is a thing) for example.
// TODO: check in detail how WRAM works, although it seems to be one region.
// TODO: DSi-specific timings!!
SetARM9RegionTimings(0x00000, 0x100000, 0, 32, 1, 1); // void
SetARM9RegionTimings(0xFFFF0, 0x100000, Mem9_BIOS, 32, 1, 1); // BIOS
SetARM9RegionTimings(0x02000, 0x03000, Mem9_MainRAM, 16, 8, 1); // main RAM
SetARM9RegionTimings(0x03000, 0x04000, Mem9_WRAM, 32, 1, 1); // ARM9/shared WRAM
SetARM9RegionTimings(0x04000, 0x05000, Mem9_IO, 32, 1, 1); // IO
SetARM9RegionTimings(0x05000, 0x06000, Mem9_Pal, 16, 1, 1); // palette
SetARM9RegionTimings(0x06000, 0x07000, Mem9_VRAM, 16, 1, 1); // VRAM
SetARM9RegionTimings(0x07000, 0x08000, Mem9_OAM, 32, 1, 1); // OAM
// ARM7
SetARM7RegionTimings(0x00000, 0x100000, 0, 32, 1, 1); // void
SetARM7RegionTimings(0x00000, 0x00010, Mem7_BIOS, 32, 1, 1); // BIOS
SetARM7RegionTimings(0x02000, 0x03000, Mem7_MainRAM, 16, 8, 1); // main RAM
SetARM7RegionTimings(0x03000, 0x04000, Mem7_WRAM, 32, 1, 1); // ARM7/shared WRAM
SetARM7RegionTimings(0x04000, 0x04800, Mem7_IO, 32, 1, 1); // IO
SetARM7RegionTimings(0x06000, 0x07000, Mem7_VRAM, 16, 1, 1); // ARM7 VRAM
// handled later: GBA slot, wifi
}
bool NDS::NeedsDirectBoot() const
{
if (ConsoleType == 1)
{
// for now, DSi mode requires original BIOS/NAND
return false;
}
else
{
// DSi/3DS firmwares aren't bootable, neither is the generated firmware
if (!SPI.GetFirmware().IsBootable())
return true;
// FreeBIOS requires direct boot (it can't boot firmware)
if (!IsLoadedARM9BIOSKnownNative() || !IsLoadedARM7BIOSKnownNative())
return true;
return false;
}
}
void NDS::SetupDirectBoot()
{
const NDSHeader& header = NDSCartSlot.GetCart()->GetHeader();
u32 cartid = NDSCartSlot.GetCart()->ID();
const u8* cartrom = NDSCartSlot.GetCart()->GetROM();
MapSharedWRAM(3);
// Copy the Nintendo logo from the NDS ROM header to the ARM9 BIOS if using FreeBIOS
// Games need this for DS<->GBA comm to work
if (!IsLoadedARM9BIOSKnownNative())
{
memcpy(ARM9BIOS.data() + 0x20, header.NintendoLogo, 0x9C);
}
// setup main RAM data
for (u32 i = 0; i < 0x170; i+=4)
{
u32 tmp = *(u32*)&cartrom[i];
NDS::ARM9Write32(0x027FFE00+i, tmp);
}
NDS::ARM9Write32(0x027FF800, cartid);
NDS::ARM9Write32(0x027FF804, cartid);
NDS::ARM9Write16(0x027FF808, header.HeaderCRC16);
NDS::ARM9Write16(0x027FF80A, header.SecureAreaCRC16);
NDS::ARM9Write16(0x027FF850, 0x5835);
NDS::ARM9Write32(0x027FFC00, cartid);
NDS::ARM9Write32(0x027FFC04, cartid);
NDS::ARM9Write16(0x027FFC08, header.HeaderCRC16);
NDS::ARM9Write16(0x027FFC0A, header.SecureAreaCRC16);
NDS::ARM9Write16(0x027FFC10, 0x5835);
NDS::ARM9Write16(0x027FFC30, 0xFFFF);
NDS::ARM9Write16(0x027FFC40, 0x0001);
u32 arm9start = 0;
// load the ARM9 secure area
if (header.ARM9ROMOffset >= 0x4000 && header.ARM9ROMOffset < 0x8000)
{
u8 securearea[0x800];
NDSCartSlot.DecryptSecureArea(securearea);
for (u32 i = 0; i < 0x800; i+=4)
{
NDS::ARM9Write32(header.ARM9RAMAddress+i, *(u32*)&securearea[i]);
arm9start += 4;
}
}
// CHECKME: firmware seems to load this in 0x200 byte chunks
for (u32 i = arm9start; i < header.ARM9Size; i+=4)
{
u32 tmp = *(u32*)&cartrom[header.ARM9ROMOffset+i];
NDS::ARM9Write32(header.ARM9RAMAddress+i, tmp);
}
for (u32 i = 0; i < header.ARM7Size; i+=4)
{
u32 tmp = *(u32*)&cartrom[header.ARM7ROMOffset+i];
NDS::ARM7Write32(header.ARM7RAMAddress+i, tmp);
}
ARM7BIOSProt = 0x1204;
SPI.GetFirmwareMem()->SetupDirectBoot();
ARM9.CP15Write(0x100, 0x00012078);
ARM9.CP15Write(0x200, 0x00000042);
ARM9.CP15Write(0x201, 0x00000042);
ARM9.CP15Write(0x300, 0x00000002);
ARM9.CP15Write(0x502, 0x15111011);
ARM9.CP15Write(0x503, 0x05100011);
ARM9.CP15Write(0x600, 0x04000033);
ARM9.CP15Write(0x601, 0x04000033);
ARM9.CP15Write(0x610, 0x0200002B);
ARM9.CP15Write(0x611, 0x0200002B);
ARM9.CP15Write(0x620, 0x00000000);
ARM9.CP15Write(0x621, 0x00000000);
ARM9.CP15Write(0x630, 0x08000035);
ARM9.CP15Write(0x631, 0x08000035);
ARM9.CP15Write(0x640, 0x0300001B);
ARM9.CP15Write(0x641, 0x0300001B);
ARM9.CP15Write(0x650, 0x00000000);
ARM9.CP15Write(0x651, 0x00000000);
ARM9.CP15Write(0x660, 0xFFFF001D);
ARM9.CP15Write(0x661, 0xFFFF001D);
ARM9.CP15Write(0x670, 0x027FF017);
ARM9.CP15Write(0x671, 0x027FF017);
ARM9.CP15Write(0x910, 0x0300000A);
ARM9.CP15Write(0x911, 0x00000020);
}
void NDS::SetupDirectBoot(const std::string& romname)
{
const NDSHeader& header = NDSCartSlot.GetCart()->GetHeader();
SetupDirectBoot();
NDSCartSlot.SetupDirectBoot(romname);
ARM9.R[12] = header.ARM9EntryAddress;
ARM9.R[13] = 0x03002F7C;
ARM9.R[14] = header.ARM9EntryAddress;
ARM9.R_IRQ[0] = 0x03003F80;
ARM9.R_SVC[0] = 0x03003FC0;
ARM7.R[12] = header.ARM7EntryAddress;
ARM7.R[13] = 0x0380FD80;
ARM7.R[14] = header.ARM7EntryAddress;
ARM7.R_IRQ[0] = 0x0380FF80;
ARM7.R_SVC[0] = 0x0380FFC0;
ARM9.JumpTo(header.ARM9EntryAddress);
ARM7.JumpTo(header.ARM7EntryAddress);
PostFlag9 = 0x01;
PostFlag7 = 0x01;
PowerControl9 = 0x820F;
GPU.SetPowerCnt(PowerControl9);
// checkme
RCnt = 0x8000;
NDSCartSlot.SetSPICnt(0x8000);
SPU.SetBias(0x200);
SetWifiWaitCnt(0x0030);
}
void NDS::Reset()
{
Platform::FileHandle* f;
u32 i;
RunningGame = false;
LastSysClockCycles = 0;
// BIOS files are now loaded by the frontend
JIT.Reset();
if (ConsoleType == 1)
{
// BIOS files are now loaded by the frontend
ARM9ClockShift = 2;
MainRAMMask = 0xFFFFFF;
}
else
{
ARM9ClockShift = 1;
MainRAMMask = 0x3FFFFF;
}
// has to be called before InitTimings
// otherwise some PU settings are completely
// unitialised on the first run
ARM9.CP15Reset();
ARM9Timestamp = 0; ARM9Target = 0;
ARM7Timestamp = 0; ARM7Target = 0;
SysTimestamp = 0;
InitTimings();
memset(MainRAM, 0, MainRAMMask + 1);
memset(SharedWRAM, 0, 0x8000);
memset(ARM7WRAM, 0, 0x10000);
MapSharedWRAM(0);
ExMemCnt[0] = 0x4000;
ExMemCnt[1] = 0x4000;
memset(ROMSeed0, 0, 2*8);
memset(ROMSeed1, 0, 2*8);
SetGBASlotTimings();
IME[0] = 0;
IE[0] = 0;
IF[0] = 0;
IME[1] = 0;
IE[1] = 0;
IF[1] = 0;
IE2 = 0;
IF2 = 0;
PostFlag9 = 0x00;
PostFlag7 = 0x00;
PowerControl9 = 0x0001;
PowerControl7 = 0x0001;
WifiWaitCnt = 0xFFFF; // temp
SetWifiWaitCnt(0);
ARM7BIOSProt = 0;
IPCSync9 = 0;
IPCSync7 = 0;
IPCFIFOCnt9 = 0;
IPCFIFOCnt7 = 0;
IPCFIFO9.Clear();
IPCFIFO7.Clear();
DivCnt = 0;
SqrtCnt = 0;
ARM9.Reset();
ARM7.Reset();
CPUStop = 0;
memset(Timers, 0, 8*sizeof(Timer));
TimerCheckMask[0] = 0;
TimerCheckMask[1] = 0;
TimerTimestamp[0] = 0;
TimerTimestamp[1] = 0;
for (i = 0; i < 8; i++) DMAs[i].Reset();
memset(DMA9Fill, 0, 4*4);
for (i = 0; i < Event_MAX; i++)
{
SchedEvent& evt = SchedList[i];
evt.Timestamp = 0;
evt.FuncID = 0;
evt.Param = 0;
}
SchedListMask = 0;
KeyInput = 0x007F03FF;
KeyCnt[0] = 0;
KeyCnt[1] = 0;
RCnt = 0;
GPU.Reset();
NDSCartSlot.Reset();
GBACartSlot.Reset();
SPU.Reset();
SPI.Reset();
RTC.Reset();
Wifi.Reset();
}
void NDS::Start()
{
Running = true;
}
static const char* StopReasonName(Platform::StopReason reason)
{
switch (reason)
{
case Platform::StopReason::External:
return "External";
case Platform::StopReason::PowerOff:
return "PowerOff";
case Platform::StopReason::GBAModeNotSupported:
return "GBAModeNotSupported";
case Platform::StopReason::BadExceptionRegion:
return "BadExceptionRegion";
default:
return "Unknown";
}
}
void NDS::Stop(Platform::StopReason reason)
{
Platform::LogLevel level;
switch (reason)
{
case Platform::StopReason::External:
case Platform::StopReason::PowerOff:
level = LogLevel::Info;
break;
case Platform::StopReason::GBAModeNotSupported:
case Platform::StopReason::BadExceptionRegion:
level = LogLevel::Error;
break;
default:
level = LogLevel::Warn;
break;
}
Log(level, "Stopping emulated console (Reason: %s)\n", StopReasonName(reason));
Running = false;
Platform::SignalStop(reason, UserData);
GPU.Stop();
SPU.Stop();
}
bool NDS::DoSavestate(Savestate* file)
{
file->Section("NDSG");
if (file->Saving)
{
u32 console = ConsoleType;
file->Var32(&console);
}
else
{
u32 console;
file->Var32(&console);
if (console != ConsoleType)
{
Log(LogLevel::Error, "savestate: Expected console type %d, got console type %d. cannot load.\n", ConsoleType, console);
return false;
}
}
file->VarArray(MainRAM, MainRAMMaxSize);
file->VarArray(SharedWRAM, SharedWRAMSize);
file->VarArray(ARM7WRAM, ARM7WRAMSize);
//file->VarArray(ARM9BIOS, 0x1000);
//file->VarArray(ARM7BIOS, 0x4000);
file->VarArray(ExMemCnt, 2*sizeof(u16));
file->VarArray(ROMSeed0, 2*8);
file->VarArray(ROMSeed1, 2*8);
file->Var16(&WifiWaitCnt);
file->VarArray(IME, 2*sizeof(u32));
file->VarArray(IE, 2*sizeof(u32));
file->VarArray(IF, 2*sizeof(u32));
file->Var32(&IE2);
file->Var32(&IF2);
file->Var8(&PostFlag9);
file->Var8(&PostFlag7);
file->Var16(&PowerControl9);
file->Var16(&PowerControl7);
file->Var16(&ARM7BIOSProt);
file->Var16(&IPCSync9);
file->Var16(&IPCSync7);
file->Var16(&IPCFIFOCnt9);
file->Var16(&IPCFIFOCnt7);
IPCFIFO9.DoSavestate(file);
IPCFIFO7.DoSavestate(file);
file->Var16(&DivCnt);
file->Var16(&SqrtCnt);
file->Var32(&CPUStop);
for (int i = 0; i < 8; i++)
{
Timer* timer = &Timers[i];
file->Var16(&timer->Reload);
file->Var16(&timer->Cnt);
file->Var32(&timer->Counter);
file->Var32(&timer->CycleShift);
}
file->VarArray(TimerCheckMask, 2*sizeof(u8));
file->VarArray(TimerTimestamp, 2*sizeof(u64));
file->VarArray(DMA9Fill, 4*sizeof(u32));
for (int i = 0; i < Event_MAX; i++)
{
SchedEvent& evt = SchedList[i];
file->Var64(&evt.Timestamp);
file->Var32(&evt.FuncID);
file->Var32(&evt.Param);
}
file->Var32(&SchedListMask);
file->Var64(&ARM9Timestamp);
file->Var64(&ARM9Target);
file->Var64(&ARM7Timestamp);
file->Var64(&ARM7Target);
file->Var64(&SysTimestamp);
file->Var64(&LastSysClockCycles);
file->Var64(&FrameStartTimestamp);
file->Var32(&NumFrames);
file->Var32(&NumLagFrames);
file->Bool32(&LagFrameFlag);
// TODO: save KeyInput????
file->VarArray(KeyCnt, 2*sizeof(u16));
file->Var16(&RCnt);
file->Var8(&WRAMCnt);
file->Bool32(&RunningGame);
if (!file->Saving)
{
// 'dept of redundancy dept'
// but we do need to update the mappings
MapSharedWRAM(WRAMCnt);
InitTimings();
SetGBASlotTimings();
UpdateWifiTimings();
}
for (int i = 0; i < 8; i++)
DMAs[i].DoSavestate(file);
ARM9.DoSavestate(file);
ARM7.DoSavestate(file);
NDSCartSlot.DoSavestate(file);
if (ConsoleType == 0)
GBACartSlot.DoSavestate(file);
GPU.DoSavestate(file);
SPU.DoSavestate(file);
SPI.DoSavestate(file);
RTC.DoSavestate(file);
Wifi.DoSavestate(file);
DoSavestateExtra(file); // Handles DSi state if applicable
if (!file->Saving)
{
GPU.SetPowerCnt(PowerControl9);
SPU.SetPowerCnt(PowerControl7 & 0x0001);
Wifi.SetPowerCnt(PowerControl7 & 0x0002);
#ifdef JIT_ENABLED
JIT.Reset();
#endif
}
file->Finish();
return true;
}
void NDS::SetNDSCart(std::unique_ptr<NDSCart::CartCommon>&& cart)
{
NDSCartSlot.SetCart(std::move(cart));
// The existing cart will always be ejected;
// if cart is null, then that's equivalent to ejecting a cart
// without inserting a new one.
}
void NDS::SetNDSSave(const u8* savedata, u32 savelen)
{
if (savedata && savelen)
NDSCartSlot.SetSaveMemory(savedata, savelen);
}
void NDS::SetGBASave(const u8* savedata, u32 savelen)
{
if (ConsoleType == 0 && savedata && savelen)
{
GBACartSlot.SetSaveMemory(savedata, savelen);
}
}
void NDS::LoadBIOS()
{
Reset();
}
void NDS::SetARM7BIOS(const std::array<u8, ARM7BIOSSize>& bios) noexcept
{
ARM7BIOS = bios;
ARM7BIOSNative = CRC32(ARM7BIOS.data(), ARM7BIOS.size()) == ARM7BIOSCRC32;
}
void NDS::SetARM9BIOS(const std::array<u8, ARM9BIOSSize>& bios) noexcept
{
ARM9BIOS = bios;
ARM9BIOSNative = CRC32(ARM9BIOS.data(), ARM9BIOS.size()) == ARM9BIOSCRC32;
}
u64 NDS::NextTarget()
{
u64 minEvent = UINT64_MAX;
u32 mask = SchedListMask;
for (int i = 0; i < Event_MAX; i++)
{
if (!mask) break;
if (mask & 0x1)
{
if (SchedList[i].Timestamp < minEvent)
minEvent = SchedList[i].Timestamp;
}
mask >>= 1;
}
u64 max = SysTimestamp + kMaxIterationCycles;
if (minEvent < max + kIterationCycleMargin)
return minEvent;
return max;
}
void NDS::RunSystem(u64 timestamp)
{
SysTimestamp = timestamp;
u32 mask = SchedListMask;
for (int i = 0; i < Event_MAX; i++)
{
if (!mask) break;
if (mask & 0x1)
{
SchedEvent& evt = SchedList[i];
if (evt.Timestamp <= SysTimestamp)
{
SchedListMask &= ~(1<<i);
EventFunc func = evt.Funcs[evt.FuncID];
func(evt.That, evt.Param);
}
}
mask >>= 1;
}
}
u64 NDS::NextTargetSleep()
{
u64 minEvent = UINT64_MAX;
u32 mask = SchedListMask;
for (int i = 0; i < Event_MAX; i++)
{
if (!mask) break;
if (i == Event_SPU || i == Event_RTC)
{
if (mask & 0x1)
{
if (SchedList[i].Timestamp < minEvent)
minEvent = SchedList[i].Timestamp;
}
}
mask >>= 1;
}
return minEvent;
}
void NDS::RunSystemSleep(u64 timestamp)
{
u64 offset = timestamp - SysTimestamp;
SysTimestamp = timestamp;
u32 mask = SchedListMask;
for (int i = 0; i < Event_MAX; i++)
{
if (!mask) break;
if (i == Event_SPU || i == Event_RTC)
{
if (mask & 0x1)
{
SchedEvent& evt = SchedList[i];
if (evt.Timestamp <= SysTimestamp)
{
SchedListMask &= ~(1<<i);
u32 param;
if (i == Event_SPU)
param = 1;
else
param = evt.Param;
EventFunc func = evt.Funcs[evt.FuncID];
func(evt.That, param);
}
}
}
else if (mask & 0x1)
{
if (SchedList[i].Timestamp <= SysTimestamp)
{
SchedList[i].Timestamp += offset;
}
}
mask >>= 1;
}
}
template <CPUExecuteMode cpuMode>
u32 NDS::RunFrame()
{
Current = this;
FrameStartTimestamp = SysTimestamp;
GPU.TotalScanlines = 0;
LagFrameFlag = true;
bool runFrame = Running && !(CPUStop & CPUStop_Sleep);
while (Running)
{
u64 frametarget = SysTimestamp + 560190;
if (CPUStop & CPUStop_Sleep)
{
// we are running in sleep mode
// we still need to run the RTC during this mode
// we also keep outputting audio, so that frontends using audio sync don't skyrocket to 1000+FPS
while (Running && (SysTimestamp < frametarget))
{
u64 target = NextTargetSleep();
if (target > frametarget)
target = frametarget;
ARM9Timestamp = target << ARM9ClockShift;
ARM7Timestamp = target;
TimerTimestamp[0] = target;
TimerTimestamp[1] = target;
GPU.GPU3D.Timestamp = target;
RunSystemSleep(target);
if (!(CPUStop & CPUStop_Sleep))
break;
}
if (SysTimestamp >= frametarget)
GPU.BlankFrame();
}
else
{
if (cpuMode == CPUExecuteMode::InterpreterGDB)
{
ARM9.CheckGdbIncoming();
ARM7.CheckGdbIncoming();
}
if (!(CPUStop & CPUStop_Wakeup))
{
GPU.StartFrame();
}
CPUStop &= ~CPUStop_Wakeup;
while (Running && GPU.TotalScanlines==0)
{
u64 target = NextTarget();
ARM9Target = target << ARM9ClockShift;
CurCPU = 0;
if (CPUStop & CPUStop_GXStall)
{
// GXFIFO stall
s32 cycles = GPU.GPU3D.CyclesToRunFor();
ARM9Timestamp = std::min(ARM9Target, ARM9Timestamp+(cycles<<ARM9ClockShift));
}
else if (CPUStop & CPUStop_DMA9)
{
DMAs[0].Run();
if (!(CPUStop & CPUStop_GXStall)) DMAs[1].Run();
if (!(CPUStop & CPUStop_GXStall)) DMAs[2].Run();
if (!(CPUStop & CPUStop_GXStall)) DMAs[3].Run();
if (ConsoleType == 1)
{
auto& dsi = dynamic_cast<melonDS::DSi&>(*this);
dsi.RunNDMAs(0);
}
}
else
{
ARM9.Execute<cpuMode>();
}
RunTimers(0);
GPU.GPU3D.Run();
target = ARM9Timestamp >> ARM9ClockShift;
CurCPU = 1;
while (ARM7Timestamp < target)
{
ARM7Target = target; // might be changed by a reschedule
if (CPUStop & CPUStop_DMA7)
{
DMAs[4].Run();
DMAs[5].Run();
DMAs[6].Run();
DMAs[7].Run();
if (ConsoleType == 1)
{
auto& dsi = dynamic_cast<melonDS::DSi&>(*this);
dsi.RunNDMAs(1);
}
}