Issue with LiteX running Minerva

[TarikHamedovic]

Hello, I don't know if I should post the Issue here or on the LiteX repository, after running the following command I get this terminal output:

python3 -m litex_boards.targets.radiona_ulx3s --device LFE5U-85F --cpu-type minerva --cpu-variant standard --sdram-module MT48LC16M16 --build
INFO:ECP5PLL:Creating ECP5PLL.
INFO:ECP5PLL:Registering Single Ended ClkIn of 25.00MHz.
INFO:ECP5PLL:Creating ClkOut0 sys of 50.00MHz (+-10000.00ppm).
INFO:ECP5PLL:Creating ClkOut1 sys_ps of 50.00MHz (+-10000.00ppm).
INFO:SoC:        __   _ __      _  __  
INFO:SoC:       / /  (_) /____ | |/_/  
INFO:SoC:      / /__/ / __/ -_)>  <    
INFO:SoC:     /____/_/\__/\__/_/|_|  
INFO:SoC:  Build your hardware, easily!
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:Creating SoC... (2024-08-23 22:17:45)
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:FPGA device : LFE5U-85F-6BG381C.
INFO:SoC:System clock: 50.000MHz.
INFO:SoCBusHandler:Creating Bus Handler...
INFO:SoCBusHandler:32-bit wishbone Bus, 4.0GiB Address Space.
INFO:SoCBusHandler:Adding reserved Bus Regions...
INFO:SoCBusHandler:Bus Handler created.
INFO:SoCCSRHandler:Creating CSR Handler...
INFO:SoCCSRHandler:32-bit CSR Bus, 32-bit Aligned, 16.0KiB Address Space, 2048B Paging, big Ordering (Up to 32 Locations).
INFO:SoCCSRHandler:Adding reserved CSRs...
INFO:SoCCSRHandler:CSR Handler created.
INFO:SoCIRQHandler:Creating IRQ Handler...
INFO:SoCIRQHandler:IRQ Handler (up to 32 Locations).
INFO:SoCIRQHandler:Adding reserved IRQs...
INFO:SoCIRQHandler:IRQ Handler created.
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:Initial SoC:
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:32-bit wishbone Bus, 4.0GiB Address Space.
INFO:SoC:32-bit CSR Bus, 32-bit Aligned, 16.0KiB Address Space, 2048B Paging, big Ordering (Up to 32 Locations).
INFO:SoC:IRQ Handler (up to 32 Locations).
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:Controller ctrl added.
INFO:SoC:CPU minerva added.
INFO:SoC:CPU minerva adding IO Region 0 at 0x80000000 (Size: 0x80000000).
INFO:SoCBusHandler:io0 Region added at Origin: 0x80000000, Size: 0x80000000, Mode:  RW, Cached: False, Linker: False.
INFO:SoC:CPU minerva setting reset address to 0x00000000.
INFO:SoC:CPU minerva adding Bus Master(s).
INFO:SoCBusHandler:cpu_bus0 added as Bus Master.
INFO:SoCBusHandler:cpu_bus1 added as Bus Master.
INFO:SoC:CPU minerva adding Interrupt(s).
INFO:SoCBusHandler:rom Region added at Origin: 0x00000000, Size: 0x00020000, Mode:  RX, Cached:  True, Linker: False.
INFO:SoCBusHandler:rom added as Bus Slave.
INFO:SoC:RAM rom added Origin: 0x00000000, Size: 0x00020000, Mode:  RX, Cached:  True, Linker: False.
INFO:SoCBusHandler:sram Region added at Origin: 0x01000000, Size: 0x00002000, Mode: RWX, Cached:  True, Linker: False.
INFO:SoCBusHandler:sram added as Bus Slave.
INFO:SoC:RAM sram added Origin: 0x01000000, Size: 0x00002000, Mode: RWX, Cached:  True, Linker: False.
INFO:SoCIRQHandler:uart IRQ allocated at Location 0.
INFO:SoCIRQHandler:timer0 IRQ allocated at Location 1.
INFO:SoCBusHandler:main_ram Region added at Origin: 0x40000000, Size: 0x02000000, Mode: RWX, Cached:  True, Linker: False.
INFO:SoCBusHandler:main_ram added as Bus Slave.
INFO:SoC:CSR Bridge csr added.
INFO:SoCBusHandler:csr Region added at Origin: 0x82000000, Size: 0x00010000, Mode:  RW, Cached: False, Linker: False.
INFO:SoCBusHandler:csr added as Bus Slave.
INFO:SoCCSRHandler:csr added as CSR Master.
INFO:SoCBusHandler:Interconnect: InterconnectShared (2 <-> 4).
INFO:SoCCSRHandler:ctrl CSR allocated at Location 0.
INFO:SoCCSRHandler:identifier_mem CSR allocated at Location 1.
INFO:SoCCSRHandler:leds CSR allocated at Location 2.
INFO:SoCCSRHandler:sdram CSR allocated at Location 3.
INFO:SoCCSRHandler:timer0 CSR allocated at Location 4.
INFO:SoCCSRHandler:uart CSR allocated at Location 5.
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:Finalized SoC:
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:32-bit wishbone Bus, 4.0GiB Address Space.
IO Regions: (1)
io0                 : Origin: 0x80000000, Size: 0x80000000, Mode:  RW, Cached: False, Linker: False
Bus Regions: (4)
rom                 : Origin: 0x00000000, Size: 0x00020000, Mode:  RX, Cached:  True, Linker: False
sram                : Origin: 0x01000000, Size: 0x00002000, Mode: RWX, Cached:  True, Linker: False
main_ram            : Origin: 0x40000000, Size: 0x02000000, Mode: RWX, Cached:  True, Linker: False
csr                 : Origin: 0x82000000, Size: 0x00010000, Mode:  RW, Cached: False, Linker: False
Bus Masters: (2)
- cpu_bus0
- cpu_bus1
Bus Slaves: (4)
- rom
- sram
- main_ram
- csr
INFO:SoC:32-bit CSR Bus, 32-bit Aligned, 16.0KiB Address Space, 2048B Paging, big Ordering (Up to 32 Locations).
CSR Locations: (6)
- ctrl           : 0
- identifier_mem : 1
- leds           : 2
- sdram          : 3
- timer0         : 4
- uart           : 5
INFO:SoC:IRQ Handler (up to 32 Locations).
IRQ Locations: (2)
- uart   : 0
- timer0 : 1
INFO:SoC:--------------------------------------------------------------------------------
INFO:ECP5PLL:Config:
clki_div   : 1
clkfb      : 2
clko0_freq : 50.00MHz
clko0_div  : 8
clko0_phase: 0.00°
clko1_freq : 50.00MHz
clko1_div  : 8
clko1_phase: 90.00°
clko2_div  : 1
vco        : 400.00MHz
clkfb_div  : 16
Traceback (most recent call last):
  File "/home/user/.local/lib/python3.10/site-packages/amaranth/hdl/_rec.py", line 54, in __init__
    Shape.cast(shape, src_loc_at=1 + src_loc_at)
  File "/home/user/.local/lib/python3.10/site-packages/amaranth/hdl/_ast.py", line 152, in cast
    raise TypeError(f"Object {obj!r} cannot be converted to an Amaranth shape")
TypeError: Object (1, False) cannot be converted to an Amaranth shape

During handling of the above exception, another exception occurred:

Traceback (most recent call last):
  File "/home/user/.local/lib/python3.10/site-packages/pythondata_cpu_minerva/sources/cli.py", line 118, in <module>
    main()
  File "/home/user/.local/lib/python3.10/site-packages/pythondata_cpu_minerva/sources/cli.py", line 83, in main
    cpu = Minerva(args.reset_addr,
  File "/home/user/.local/lib/python3.10/site-packages/pythondata_cpu_minerva/sources/minerva/core.py", line 200, in __init__
    self._exception = ExceptionUnit()
  File "/home/user/.local/lib/python3.10/site-packages/pythondata_cpu_minerva/sources/minerva/units/exception.py", line 13, in __init__
    self.mstatus     = CSR(0x300, mstatus_layout)
  File "/home/user/.local/lib/python3.10/site-packages/pythondata_cpu_minerva/sources/minerva/csr.py", line 33, in __init__
    super().__init__([
  File "/home/user/.local/lib/python3.10/site-packages/amaranth/hdl/_rec.py", line 130, in __init__
    self.layout = Layout.cast(layout, src_loc_at=1 + src_loc_at)
  File "/home/user/.local/lib/python3.10/site-packages/amaranth/hdl/_rec.py", line 28, in cast
    return Layout(obj, src_loc_at=1 + src_loc_at)
  File "/home/user/.local/lib/python3.10/site-packages/amaranth/hdl/_rec.py", line 41, in __init__
    shape = Layout.cast(shape)
  File "/home/user/.local/lib/python3.10/site-packages/amaranth/hdl/_rec.py", line 28, in cast
    return Layout(obj, src_loc_at=1 + src_loc_at)
  File "/home/user/.local/lib/python3.10/site-packages/amaranth/hdl/_rec.py", line 56, in __init__
    raise TypeError("Field {!r} has invalid shape: should be castable to Shape "
TypeError: Field ('uie', (1, False)) has invalid shape: should be castable to Shape or a list of fields of a nested record
Traceback (most recent call last):
  File "/usr/lib/python3.10/runpy.py", line 196, in _run_module_as_main
    return _run_code(code, main_globals, None,
  File "/usr/lib/python3.10/runpy.py", line 86, in _run_code
    exec(code, run_globals)
  File "/home/user/FPGA/tools/LiteX/litex-boards/litex_boards/targets/radiona_ulx3s.py", line 193, in <module>
    main()
  File "/home/user/FPGA/tools/LiteX/litex-boards/litex_boards/targets/radiona_ulx3s.py", line 186, in main
    builder.build(**parser.toolchain_argdict)
  File "/home/user/FPGA/tools/LiteX/litex/litex/soc/integration/builder.py", line 373, in build
    self.soc.finalize()
  File "/home/user/FPGA/tools/LiteX/litex/litex/soc/integration/soc.py", line 1477, in finalize
    Module.finalize(self)
  File "/home/user/FPGA/tools/LiteX/migen/migen/fhdl/module.py", line 156, in finalize
    subfragments = self._collect_submodules()
  File "/home/user/FPGA/tools/LiteX/migen/migen/fhdl/module.py", line 149, in _collect_submodules
    r.append((name, submodule.get_fragment()))
  File "/home/user/FPGA/tools/LiteX/migen/migen/fhdl/module.py", line 102, in get_fragment
    self.finalize()
  File "/home/user/FPGA/tools/LiteX/migen/migen/fhdl/module.py", line 157, in finalize
    self.do_finalize(*args, **kwargs)
  File "/home/user/FPGA/tools/LiteX/litex/litex/soc/cores/cpu/minerva/core.py", line 118, in do_finalize
    self.elaborate(
  File "/home/user/FPGA/tools/LiteX/litex/litex/soc/cores/cpu/minerva/core.py", line 113, in elaborate
    raise OSError("Unable to elaborate Minerva CPU, please check your Amaranth/Yosys install")
OSError: Unable to elaborate Minerva CPU, please check your Amaranth/Yosys install

This happens only when I add the --build flag.

To note I downgraded the Amaranth to 0.5.1 version, the one that is on the branch on the official github repository and I also installed the pythondata-cpu-minerva via pip.

Trying the Minerva on LiteX with Amaranth 0.6 version gives me back an error that it doesn't have a file in amaranth.lib.coding which is true, I assume you are aware of this change affecting Minerva with LiteX.

[whitequark]

Minerva is known to be currently incompatible with the git HEAD of Amaranth. In general, I would advise using the latest release of Amaranth to avoid incompatibilities like this.