Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Quick start example won't produce output #2

Open
AntonBabushkin opened this issue Jun 7, 2019 · 0 comments
Open

Quick start example won't produce output #2

AntonBabushkin opened this issue Jun 7, 2019 · 0 comments

Comments

@AntonBabushkin
Copy link

Hi,
I am not able to successfully run a quick start example.
Could you please suggest what might be wrong.
Thanks.

Environment (Win10):

  1. nmigen installed
  2. Yosys (yosys-win32-mxebin-0.8.zip) installed
  3. Minerva installed
  4. Issue No module named 'jtagtap' #1 bypassed by commenting out missing module import and tap creation in file top.py

Execution log:

C:\Users\anton\OneDrive\Desktop\RISC-V\minerva>python build.py > minerva.v
Traceback (most recent call last):
File "build.py", line 48, in
main()
File "build.py", line 44, in main
print(verilog.convert(frag, name="minerva_cpu", ports=ports))
File "C:\Users\anton\AppData\Local\Programs\Python\Python37-32\lib\site-packages\nmigen\back\verilog.py", line 48, in convert
raise YosysError(error.strip())
nmigen.back.verilog.YosysError: ERROR: Parser error in line 5444: syntax error

Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Labels
None yet
Projects
None yet
Development

No branches or pull requests

1 participant