nios2.dts

/*
 * This devicetree is generated by sopc2dts
 * Sopc2dts is written by Walter Goossens <waltergoossens@home.nl>
 * in cooperation with the nios2 community <Nios2-dev@sopc.et.ntust.edu.tw>
 */
/dts-v1/;

/ {
	model = "ALTR,qsys";
	compatible = "ALTR,qsys";
	#address-cells = < 1 >;
	#size-cells = < 1 >;

	cpus {
		#address-cells = < 1 >;
		#size-cells = < 0 >;

		cpu: cpu@0x0 {
			device_type = "cpu";
			compatible = "altr,nios2-16.1";
			reg = < 0x00000000 >;
			interrupt-controller;
			#interrupt-cells = < 1 >;
		}; //end cpu@0x0 (cpu)
	}; //end cpus

	memory@0 {
		device_type = "memory";
		reg = < 0x00000000 0x08000000 >;
	}; //end memory@0

	sopc@0 {
		device_type = "soc";
		ranges;
		#address-cells = < 1 >;
		#size-cells = < 1 >;
		compatible = "ALTR,avalon", "simple-bus";
		bus-frequency = < 50000000 >;

		jtag: serial@0x8001440 {
			compatible = "altr,juart-16.1";
			reg = < 0x08001440 0x00000008 >;
			interrupt-parent = < &cpu >;
			interrupts = < 1 >;
		}; //end serial@0x8001440 (jtag)

		ram_mmu: memory@0x8001000 {
			device_type = "memory";
			compatible = "ALTR,onchipmem-16.1";
			reg = < 0x08001000 0x00000400
				0x08001000 0x00000400 >;
		}; //end memory@0x8001000 (ram_mmu)

		timer: timer@0x8001420 {
			compatible = "altr,timer-16.1";
			reg = < 0x08001420 0x00000020 >;
			interrupt-parent = < &cpu >;
			interrupts = < 0 >;
		}; //end timer@0x8001420 (timer)

		uart: serial@0x8001400 {
			compatible = "altr,uart-16.1";
			reg = < 0x08001400 0x00000020 >;
			interrupt-parent = < &cpu >;
			interrupts = < 2 >;
		}; //end serial@0x8001400 (uart)

		timer_0: timer@0x8001460 {
			compatible = "altr,timer-16.1";
			reg = < 0x08001460 0x00000020 >;
			interrupt-parent = < &cpu >;
			interrupts = < 3 >;
		}; //end timer@0x8001460 (timer_0)
	}; //end sopc@0

	chosen {
		bootargs = "debug console=ttyAL0,115200";
	}; //end chosen
}; //end /