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intelmsr.h
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/*
* CoreFreq
* Copyright (C) 2015-2021 CYRIL INGENIERIE
* Licenses: GPL2
*/
#ifndef MSR_SMI_COUNT
#define MSR_SMI_COUNT 0x00000034
#endif
#ifndef MSR_IA32_FEAT_CTL
#define MSR_IA32_FEAT_CTL MSR_IA32_FEATURE_CONTROL
#endif
#ifndef MSR_PPIN_CTL
#define MSR_PPIN_CTL 0x0000004e
#endif
#ifndef MSR_PPIN
#define MSR_PPIN 0x0000004f
#endif
#ifndef MSR_IA32_SPEC_CTRL
#define MSR_IA32_SPEC_CTRL 0x00000048
#endif
#ifndef MSR_IA32_PRED_CMD
#define MSR_IA32_PRED_CMD 0x00000049
#endif
#ifndef MSR_IA32_FLUSH_CMD
#define MSR_IA32_FLUSH_CMD 0x0000010b
#endif
#ifndef MSR_IA32_ARCH_CAPABILITIES
#define MSR_IA32_ARCH_CAPABILITIES 0x0000010a
#endif
#ifndef MSR_IA32_CORE_CAPABILITIES
#define MSR_IA32_CORE_CAPABILITIES 0x000000cf
#endif
#ifndef MSR_IA32_TSX_CTRL
#define MSR_IA32_TSX_CTRL 0x00000122
#endif
#ifndef MSR_PLATFORM_INFO
#define MSR_PLATFORM_INFO 0x000000ce
#endif
#ifndef MSR_MISC_FEATURE_CONTROL
#define MSR_MISC_FEATURE_CONTROL 0x000001a4
#endif
#ifndef MSR_MISC_PWR_MGMT
#define MSR_MISC_PWR_MGMT 0x000001aa
#endif
#ifndef MSR_NHM_TURBO_RATIO_LIMIT
#define MSR_NHM_TURBO_RATIO_LIMIT 0x000001ad
#endif
#ifndef MSR_TURBO_RATIO_LIMIT
#define MSR_TURBO_RATIO_LIMIT MSR_NHM_TURBO_RATIO_LIMIT
#endif
#ifndef MSR_TURBO_RATIO_LIMIT1
#define MSR_TURBO_RATIO_LIMIT1 0x000001ae
#endif
#ifndef MSR_TURBO_RATIO_LIMIT2
#define MSR_TURBO_RATIO_LIMIT2 0x000001af
#endif
#ifndef MSR_TURBO_RATIO_LIMIT3
#define MSR_TURBO_RATIO_LIMIT3 0x000001ac
#endif
#ifndef MSR_TURBO_POWER_CURRENT_LIMIT
#define MSR_TURBO_POWER_CURRENT_LIMIT 0x000001ac
#endif
#ifndef MSR_IA32_POWER_CTL
#define MSR_IA32_POWER_CTL 0x000001fc
#endif
#ifndef MSR_PKG_CST_CONFIG_CONTROL
#define MSR_PKG_CST_CONFIG_CONTROL MSR_NHM_SNB_PKG_CST_CFG_CTL
#endif
#ifndef MSR_PMG_IO_CAPTURE_BASE
#define MSR_PMG_IO_CAPTURE_BASE 0x000000e4
#endif
#ifndef MSR_CC6_DEMOTION_POLICY_CONFIG
#define MSR_CC6_DEMOTION_POLICY_CONFIG 0x00000668
#endif
#ifndef MSR_MC6_DEMOTION_POLICY_CONFIG
#define MSR_MC6_DEMOTION_POLICY_CONFIG 0x00000669
#endif
#define MSR_NHM_UNCORE_PERF_GLOBAL_CTRL 0x00000391
#define MSR_SNB_UNCORE_PERF_GLOBAL_CTRL 0x00000391
#define MSR_SKL_UNCORE_PERF_GLOBAL_CTRL 0x00000e01
#define MSR_IVB_EP_PMON_GLOBAL_CTRL 0x00000c00
#define MSR_HSW_EP_PMON_GLOBAL_CTRL 0x00000700
#define MSR_NHM_UNCORE_PERF_GLOBAL_STATUS 0x00000392
#define MSR_SNB_UNCORE_PERF_GLOBAL_STATUS 0x00000392
#define MSR_SKL_UNCORE_PERF_GLOBAL_STATUS 0x00000e02
#define MSR_UNCORE_PERF_GLOBAL_OVF_CTRL 0x00000393
#define MSR_NHM_UNCORE_PERF_FIXED_CTR0 0x00000394
#define MSR_SNB_UNCORE_PERF_FIXED_CTR0 0x00000395
#define MSR_SKL_UNCORE_PERF_FIXED_CTR0 0x00000395
#define MSR_SNB_EP_UNCORE_PERF_FIXED_CTR0 0x00000c09
#define MSR_HSW_EP_UNCORE_PERF_FIXED_CTR0 0x00000704
#define MSR_NHM_UNCORE_PERF_FIXED_CTR_CTRL 0x00000395
#define MSR_SNB_UNCORE_PERF_FIXED_CTR_CTRL 0x00000394
#define MSR_SKL_UNCORE_PERF_FIXED_CTR_CTRL 0x00000394
#define MSR_SNB_EP_UNCORE_PERF_FIXED_CTR_CTRL 0x00000c08
#define MSR_HSW_EP_UNCORE_PERF_FIXED_CTR_CTRL 0x00000703
#define MSR_HSW_UNCORE_RATIO_LIMIT 0x00000620
#ifndef MSR_CONFIG_TDP_NOMINAL
#define MSR_CONFIG_TDP_NOMINAL 0x00000648
#endif
#ifndef MSR_CONFIG_TDP_LEVEL_1
#define MSR_CONFIG_TDP_LEVEL_1 0x00000649
#endif
#ifndef MSR_CONFIG_TDP_LEVEL_2
#define MSR_CONFIG_TDP_LEVEL_2 0x0000064a
#endif
#ifndef MSR_CONFIG_TDP_CONTROL
#define MSR_CONFIG_TDP_CONTROL 0x0000064b
#endif
#ifndef MSR_TURBO_ACTIVATION_RATIO
#define MSR_TURBO_ACTIVATION_RATIO 0x0000064c
#endif
#ifndef MSR_RAPL_POWER_UNIT
#define MSR_RAPL_POWER_UNIT 0x00000606
#endif
#ifndef MSR_PKG_POWER_LIMIT
#define MSR_PKG_POWER_LIMIT 0x00000610
#endif
#ifndef MSR_PKG_ENERGY_STATUS
#define MSR_PKG_ENERGY_STATUS 0x00000611
#endif
#ifndef MSR_PKG_PERF_STATUS
#define MSR_PKG_PERF_STATUS 0x00000613
#endif
#ifndef MSR_PKG_POWER_INFO
#define MSR_PKG_POWER_INFO 0x00000614
#endif
#ifndef MSR_DRAM_POWER_LIMIT
#define MSR_DRAM_POWER_LIMIT 0x00000618
#endif
#ifndef MSR_DRAM_ENERGY_STATUS
#define MSR_DRAM_ENERGY_STATUS 0x00000619
#endif
#ifndef MSR_DRAM_PERF_STATUS
#define MSR_DRAM_PERF_STATUS 0x0000061b
#endif
#ifndef MSR_PP0_POWER_LIMIT
#define MSR_PP0_POWER_LIMIT 0x00000638
#endif
#ifndef MSR_PP0_ENERGY_STATUS
#define MSR_PP0_ENERGY_STATUS 0x00000639
#endif
#ifndef MSR_PP0_POLICY
#define MSR_PP0_POLICY 0x0000063a
#endif
#ifndef MSR_PP0_PERF_STATUS
#define MSR_PP0_PERF_STATUS 0x0000063b
#endif
#ifndef MSR_PP1_POWER_LIMIT
#define MSR_PP1_POWER_LIMIT 0x00000640
#endif
#ifndef MSR_PP1_ENERGY_STATUS
#define MSR_PP1_ENERGY_STATUS 0x00000641
#endif
#ifndef MSR_PLATFORM_POWER_LIMIT
#define MSR_PLATFORM_POWER_LIMIT 0x0000065c
#endif
#ifndef MSR_PLATFORM_ENERGY_STATUS
#define MSR_PLATFORM_ENERGY_STATUS 0x0000064d
#endif
#ifndef MSR_PKG_C2_RESIDENCY
#define MSR_PKG_C2_RESIDENCY 0x0000060d
#endif
#ifndef MSR_ATOM_PKG_C2_RESIDENCY
#define MSR_ATOM_PKG_C2_RESIDENCY 0x000003f8
#endif
#ifndef MSR_PKG_C3_RESIDENCY
#define MSR_PKG_C3_RESIDENCY 0x000003f8
#endif
#ifndef MSR_ATOM_PKG_C4_RESIDENCY
#define MSR_ATOM_PKG_C4_RESIDENCY 0x000003f9
#endif
#ifndef MSR_PKG_C6_RESIDENCY
#define MSR_PKG_C6_RESIDENCY 0x000003f9
#endif
#ifndef MSR_ATOM_PKG_C6_RESIDENCY
#define MSR_ATOM_PKG_C6_RESIDENCY 0x000003fa
#endif
#ifndef MSR_ATOM_MC6_RESIDENCY
#define MSR_ATOM_MC6_RESIDENCY 0x00000664
#endif
#ifndef MSR_PKG_C7_RESIDENCY
#define MSR_PKG_C7_RESIDENCY 0x000003fa
#endif
#ifndef MSR_PKG_C8_RESIDENCY
#define MSR_PKG_C8_RESIDENCY 0x00000630
#endif
#ifndef MSR_PKG_C9_RESIDENCY
#define MSR_PKG_C9_RESIDENCY 0x00000631
#endif
#ifndef MSR_PKG_C10_RESIDENCY
#define MSR_PKG_C10_RESIDENCY 0x00000632
#endif
#ifndef MSR_CORE_C1_RESIDENCY
#ifdef MSR_CORE_C1_RES
#define MSR_CORE_C1_RESIDENCY MSR_CORE_C1_RES
#else
#define MSR_CORE_C1_RESIDENCY 0x00000660
#endif
#endif
#ifndef MSR_CORE_C3_RESIDENCY
#define MSR_CORE_C3_RESIDENCY 0x000003fc
#endif
#ifndef MSR_CORE_C6_RESIDENCY
#define MSR_CORE_C6_RESIDENCY 0x000003fd
#endif
#ifndef MSR_CORE_C7_RESIDENCY
#define MSR_CORE_C7_RESIDENCY 0x000003fe
#endif
#ifndef MSR_KNL_CORE_C6_RESIDENCY
#define MSR_KNL_CORE_C6_RESIDENCY 0x000003ff
#endif
#ifndef MSR_IA32_VMX_BASIC
#define MSR_IA32_VMX_BASIC 0x00000480
#endif
#ifndef MSR_PM_ENABLE
#define MSR_PM_ENABLE 0x00000770
#endif
#ifndef MSR_IA32_PM_ENABLE
#define MSR_IA32_PM_ENABLE MSR_PM_ENABLE
#endif
#ifndef MSR_HWP_CAPABILITIES
#define MSR_HWP_CAPABILITIES 0x00000771
#endif
#ifndef MSR_IA32_HWP_CAPABILITIES
#define MSR_IA32_HWP_CAPABILITIES MSR_HWP_CAPABILITIES
#endif
#ifndef MSR_HWP_REQUEST_PKG
#define MSR_HWP_REQUEST_PKG 0x00000772
#endif
#ifndef MSR_IA32_HWP_REQUEST_PKG
#define MSR_IA32_HWP_REQUEST_PKG MSR_HWP_REQUEST_PKG
#endif
#ifndef MSR_HWP_INTERRUPT
#define MSR_HWP_INTERRUPT 0x00000773
#endif
#ifndef MSR_HWP_REQUEST
#define MSR_HWP_REQUEST 0x00000774
#endif
#ifndef MSR_IA32_HWP_REQUEST
#define MSR_IA32_HWP_REQUEST MSR_HWP_REQUEST
#endif
#ifndef MSR_IA32_PKG_HDC_CTL
#define MSR_IA32_PKG_HDC_CTL 0x00000db0
#endif
/* Source: Intel Atom Processor E3800 Product Family Datasheet */
#define MSR_PKG_TURBO_CFG 0x00000670
#define MSR_THERM_CFG1 0x00000673
#define MSR_THERM_CFG2 0x00000674
typedef union
{
unsigned long long value;
struct
{
unsigned long long
ReservedBits : 32-0,
Signature : 64-32;
};
} MICROCODE_ID;
typedef union
{
unsigned long long value;
struct
{
unsigned long long
ReservedBits1 : 8-0,
MaxBusRatio : 13-8,
ReservedBits2 : 50-13,
PlatformId : 53-50,
ReservedBits3 : 64-53;
};
} PLATFORM_ID;
typedef union
{
unsigned long long value;
struct
{
unsigned long long
Bus_Speed : 3-0,
ReservedBits : 64-3;
};
} FSB_FREQ;
typedef union
{ /* R/W: bits are defined as SMT or Core scope. */
unsigned long long value;
struct
{
unsigned long long
IBRS : 1-0, /* CPUID(EAX=07H,ECX=0):EDX[26] == 1 */
STIBP : 2-1, /* CPUID(EAX=07H,ECX=0):EDX[27] == 1 */
SSBD : 3-2, /* CPUID(EAX=07H,ECX=0):EDX[31] == 1 */
ReservedBits : 64-3;
};
} SPEC_CTRL;
typedef union
{ /* W/O: on-demand,issue commands that affect the state of predictors.*/
unsigned long long value;
struct
{
unsigned long long
IBPB : 1-0, /* CPUID(EAX=07H,ECX=0):EDX[26] == 1 */
ReservedBits : 64-1;
};
} PRED_CMD;
typedef union
{ /* W/O: writeback & invalidate the L1 data cache, previous cachelines*/
unsigned long long value;
struct
{
unsigned long long
L1D_FLUSH_CMD : 1-0, /* CPUID(EAX=07H,ECX=0):EDX[28] == 1 */
ReservedBits : 64-1;
};
} FLUSH_CMD;
typedef union
{ /* R/O && CPUID.(EAX=07H,ECX=0):EDX[29] == 1 */
unsigned long long value;
struct
{
unsigned long long
RDCL_NO : 1-0,
IBRS_ALL : 2-1,
RSBA : 3-2,
L1DFL_VMENTRY_NO: 4-3,
SSB_NO : 5-4,
MDS_NO : 6-5,
PSCHANGE_MC_NO : 7-6,
TSX_CTRL : 8-7,
TAA_NO : 9-8,
ReservedBits : 64-9;
};
} ARCH_CAPABILITIES;
typedef union
{ /* 06_86 [TREMONT], 06_8D, 06_8C [Tiger Lake] */
unsigned long long value;
struct
{
unsigned long long
STLB_SUPPORTED : 1-0, /* STLB QoS MSRs (1A8FH-1A97H) */
ReservedBits1 : 2-1,
FUSA_SUPPORTED : 3-2,
RSM_IN_CPL0_ONLY: 4-3, /* RSM inst avail in all CPL if == 0 */
ReservedBits2 : 5-4,
SPLA_EXCEPTION : 6-5, /* split locked access MSR (0x33) */
SNOOP_FILTER_SUP: 7-6, /*Snoop Filter QoS Mask MSRs supported*/
ReservedBits3 : 64-7;
};
} CORE_CAPABILITIES;
typedef union
{
unsigned long long value;
struct
{
unsigned long long
RTM_DISABLE : 1-0, /*1:XBEGIN aborts w/ EAX=0 */
TSX_CPUID_CLEAR : 2-1, /*0:if TSX capable then RTM=0 & HLE=0*/
ReservedBits : 64-2;
};
} TSX_CTRL;
typedef union
{ /* MSR IA32_PERF_STATUS(0x198): 0F_03 [NetBurst] */
unsigned long long value;
struct
{
unsigned long long
CurrVID : 8-0,
CurrFID : 16-8,
ReservedBits1 : 31-16,
XE_Enable : 32-31, /* Intel Core */
ReservedBits2 : 40-32,
MaxBusRatio : 45-40, /* Architectural */
ReservedBits3 : 46-45,
NonInt_BusRatio : 47-46,
ReservedBits4 : 64-47;
} CORE;
struct
{
unsigned long long
CurrentRatio : 16-0,
ReservedBits : 64-16;
} NHM;
struct
{
unsigned long long
ReservedBits1 : 8-0,
CurrentRatio : 16-8,
ReservedBits2 : 32-16,
CurrVID : 48-32, /* Core Voltage ID (Sandy Bridge) */
ReservedBits3 : 64-48;
} SNB;
} PERF_STATUS;
typedef union
{ /* MSR IA32_PERF_CTL(0x199): 0F_03 [NetBurst] */
unsigned long long value;
struct
{
union {
struct {
unsigned int
TargetVoltage : 8-0,
TargetRatio : 16-8,
ReservedBits2 : 32-16;
} CORE;
struct {
unsigned int
TargetRatio : 16-0,
ReservedBits : 32-16;
} NHM;
struct {
unsigned int
ReservedBits1 : 8-0,
TargetRatio : 16-8,
ReservedBits2 : 32-16;
} SNB;
};
struct {
unsigned int
Turbo_IDA : 1-0, /* IDA Disengage bit: Mobile [06_0F] */
ReservedBits : 32-1;
};
};
} PERF_CONTROL;
typedef union
{
unsigned long long value;
struct
{
unsigned long long
ReservedBits1 : 8-0,
MaxNonTurboRatio: 16-8,
ReservedBits2 : 23-16, /* Bit[16]=1 in Westmere ? */
PPIN_CAP : 24-23, /* R/O:IVB-E,BDW-E,SKL-S : MSR_PPIN */
ReservedBits3 : 28-24,
ProgrammableTurbo:29-28, /* Phi,SKL,BDW,HSW,IVB,SNB,NHM,GLM */
ProgrammableTDP : 30-29, /* Nehalem: Turbo TDC-TDP Limit */
ProgrammableTj : 31-30, /* R/O: 1 = TjOffset is writable */
ReservedBits4 : 32-31,
LowPowerMode : 33-32, /* R/O: 1 = LPM is supported. */
ConfigTDPlevels : 35-33, /* Ivy Bridge, Haswell(-E), Phy */
ReservedBits5 : 40-35,
MinimumRatio : 48-40, /* Phi,SKL,BDW,HSW,IVB,SNB,NHM,GLM */
MinOperatRatio : 56-48, /* Ivy Bridge, Haswell(-E) */
ReservedBits6 : 64-56;
};
} PLATFORM_INFO;
/*
MSR_PLATFORM_INFO[0xCE:30] : Programmable TJ OFFSET : R/O : Package
06_5Ch [Atom_Goldmont], 06_3Eh [IvyBridge_EP], 06_4Fh [Broadwell_EP],
06_56h [Broadwell_D], 06_55h [Skylake_X], 06_57h [Xeon_Phi], 06_85h
*/
typedef union
{ /* MSR MISC_FEATURE_CONTROL(0x1a4) */
unsigned long long value;
struct /* R/W , Core scope , Disable=1 */
{
unsigned long long
L2_HW_Prefetch : 1-0, /* Avoton, Goldmont, NHM, SNB */
L2_HW_CL_Prefetch: 2-1, /* NHM, SNB */
L1_HW_Prefetch : 3-2, /* Avoton, Goldmont, NHM, SNB */
L1_HW_IP_Prefetch: 4-3, /* NHM, SNB */
ReservedBits : 64-4;
};
struct
{
unsigned long long
L1_DCU_Prefetch : 1-0,
L2_HW_Prefetch : 2-1,
ReservedBits : 64-2;
} Phi;
} MISC_FEATURE_CONTROL;
typedef union
{
unsigned long long value;
struct
{
unsigned long long
LockOut : 1-0, /* R/WO: iff PLATFORM_INFO.PPIN_CAP */
Enable : 2-1, /* R/W: iff PLATFORM_INFO.PPIN_CAP */
ReservedBits : 64-2;
};
} INTEL_PPIN_CTL;
typedef struct
{
unsigned long long value;
} INTEL_PPIN_NUM;
typedef union
{
unsigned long long value;
struct
{
unsigned long long
Pkg_CStateLimit : 4-0,
ReservedBits1 : 10-4,
IO_MWAIT_Redir : 11-10,
ReservedBits2 : 15-11,
CFG_Lock : 16-15,
AutoCStateConv : 17-16, /* BDW-D, BDW-EP, Phi */
ReservedBits3 : 24-17,
Int_Filtering : 25-24, /* Nehalem */
C3autoDemotion : 26-25, /* Nehalem */
C1autoDemotion : 27-26, /* Nehalem */
C3undemotion : 28-27, /* Sandy Bridge */
C1undemotion : 29-28, /* Sandy Bridge */
PkgCSTdemotion : 30-29, /* NHM,HSW-E,Core-M,BDW-E,SKL-S,Phi */
PkgCSTundemotion: 31-30, /* NHM,HSW-E,Core-M,BDW-E,SKL-S,Phi */
ReservedBits4 : 64-31;
};
} CSTATE_CONFIG;
typedef union
{
unsigned long long value;
struct
{
unsigned long long
LVL2_BaseAddr : 16-0,
CStateRange : 19-16, /* R/W */
ReservedBits : 64-19;
};
} CSTATE_IO_MWAIT;
/*
*MSR_PMG_IO_CAPTURE_BASE(E4h)
Silvermont, Airmont, Goldmont, Nehalem, Sandy Bridge, Ivy Bridge-E, Phi
if MSR_PKG_CST_CONFIG_CONTROL(E2h).IO_MWAIT_Redir is enable then
{
Per Module Phi.CStateRange = 100b C4
110b C6
Per Core SNB & IVB-E.CStateRange=000b C3
001b C6
010b C7
Per Core NHM.CStateRange = 000b C3
001b C6
010b C7
Per Module Airmont.CStateRange = 000b C3
001b Deep Power Down tech.
010b C7
Per Module Goldmont.CStateRange = 100b C4
110b C6
111b C7
}
*/
typedef union
{
unsigned long long value;
struct
{
unsigned long long
CC6demotion : 64-0; /* 06_37h : R/W: 1=Enable */
};
} CC6_CONFIG;
typedef union
{
unsigned long long value;
struct
{
unsigned long long
MC6demotion : 64-0; /* 06_37h : R/W: 1=Enable */
};
} MC6_CONFIG;
typedef union
{ /* MSR_TURBO_RATIO_LIMIT(1ADh) */
/*
Atom Avoton [06_4D] & Goldmont [06_5C], Nehalem [06_1A, 06_1E, 06_1F]
Xeon Westmere [06_25, 06_2C]
*must blackList w/ Nehalem Xeon 7500 [06_2E] & Westmere Xeon E7 [06_2F]
Sandy Bridge [06_2A] & Xeon SNB-E5 [06_2D]
Haswell [06_3C, 06_45, 06_46] & Xeon E5v3 [06_3F]
Broadwell [06_3D, 06_56] & Xeon E3v4 [06_47] & Xeon E5v4[06_4F]
Skylake Client [06_4E, 06_5E] & Xeon Skylake-X Server [06_55]
Kabylake [06_8E, 06_9E]
Cannonlake [06_66]
*/
unsigned long long value;
struct
{
unsigned long long
MaxRatio_1C : 8-0, /* NHM, SNB, HSW, BDW, SKL, KBL */
MaxRatio_2C : 16-8, /* NHM, SNB, HSW, BDW, SKL, KBL */
MaxRatio_3C : 24-16, /* NHM, SNB, HSW, BDW, SKL, KBL */
MaxRatio_4C : 32-24, /* NHM, SNB, HSW, BDW, SKL, KBL */
MaxRatio_5C : 40-32, /* Westmere, SNB-E5, E3v4 */
MaxRatio_6C : 48-40, /* Westmere, SNB-E5, E3v4 */
MaxRatio_7C : 56-48, /* SNB-E5, E5v3, E5v4, SKL-X */
MaxRatio_8C : 64-56; /* AVT, GLM, SNB-E5, E5v3-v4, SKL-X */
};
} TURBO_RATIO_CONFIG0;
typedef union
{ /* MSR_TURBO_RATIO_LIMIT1(1AEh) */
unsigned long long value;
struct
{ /* Haswell-E5v3 [06_3F], Broadwell-E [06_56] & Xeon E5v4 [06_4F] */
unsigned long long
MaxRatio_9C : 8-0,
MaxRatio_10C : 16-8,
MaxRatio_11C : 24-16,
MaxRatio_12C : 32-24,
MaxRatio_13C : 40-32,
MaxRatio_14C : 48-40,
MaxRatio_15C : 56-48,
MaxRatio_16C : 64-56;
} HSW_EP;
struct
{ /* Xeon IvyBridge-EPv2 [06_3E] */
unsigned long long
MaxRatio_9C : 8-0, /* E5 + E7 */
MaxRatio_10C : 16-8, /* E5 + E7 */
MaxRatio_11C : 24-16, /* E5 + E7 */
MaxRatio_12C : 32-24, /* E5 + E7 */
MaxRatio_13C : 40-32, /* E7 */
MaxRatio_14C : 48-40, /* E7 */
MaxRatio_15C : 56-48, /* E7 */
ReservedBits : 63-56, /* E7 */
Semaphore : 64-63; /* E7 */
} IVB_EP;
struct
{ /* Skylake_X [06_55] */
unsigned long long
NUMCORE_0 : 8-0,
NUMCORE_1 : 16-8,
NUMCORE_2 : 24-16,
NUMCORE_3 : 32-24,
NUMCORE_4 : 40-32,
NUMCORE_5 : 48-40,
NUMCORE_6 : 56-48,
NUMCORE_7 : 64-56;
} SKL_X;
} TURBO_RATIO_CONFIG1;
typedef union
{ /* MSR_TURBO_RATIO_LIMIT2(1AFh) */
unsigned long long value;
struct
{ /* Xeon Haswell-E5v3 [06_3F] */
unsigned long long
MaxRatio_17C : 8-0,
MaxRatio_18C : 16-8,
ReservedBits : 63-16,
Semaphore : 64-63;
};
} TURBO_RATIO_CONFIG2;
typedef union
{ /* MSR_TURBO_RATIO_LIMIT2(1ACh) */
unsigned long long value;
struct
{ /* Xeon Broadwell-EP [06_4F] */
unsigned long long
ReservedBits : 63-0,
Semaphore : 64-63;
};
} TURBO_RATIO_CONFIG3;
/* Config TDP MSRs: 06_3A/06_3C/06_3F/06_45/06_46/06_4E/
06_55/06_57/06_5C/06_5E/06_66/06_7A/06_8E */
typedef union
{
unsigned long long value;
struct
{
unsigned int
Ratio : 8-0, /* ratio x 100 MHz */
ReservedBits : 32-8;
unsigned int : 32-0;
};
} CONFIG_TDP_NOMINAL;
typedef union
{
unsigned long long value;
struct
{
unsigned long long
PkgPower : 15-0,
ReservedBits1 : 16-15,
Ratio : 24-16,
ReservedBits2 : 32-24,
MaxPower : 47-32,
ReservedBits3 : 48-47,
MinPower : 64-48;
};
} CONFIG_TDP_LEVEL;
typedef union
{
unsigned long long value;
struct
{ /* 0:Default; 1:TDP_LEVEL_1; 2:TDP_LEVEL_2; 3:reserved */
unsigned int
Level : 2-0,
ReservedBits : 31-2,
Lock : 32-31;
unsigned int : 32-0;
};
} CONFIG_TDP_CONTROL;
typedef union
{
unsigned long long value;
struct
{
unsigned int
MaxRatio : 8-0,
ReservedBits1 : 31-8,
Ratio_Lock : 32-31;
unsigned int : 32-0;
};
} TURBO_ACTIVATION;
typedef union
{ /* MSR_PKG_TURBO_CFG(0x00000670) */
unsigned long long value;
struct
{
unsigned long long
TjMax_Turbo : 3-0,
UnknownBits1 : 8-3,
DynamicTurbo : 9-8,
DynamicPolicy : 12-9,
UnknownBits2 : 64-12;
};
} PKG_TURBO_CONFIG;
/* Source: android: kernel/x86_64/.../drivers/thermal/intel_soc_thermal.c
SLM[06_37] set bits[0:2] to 0x2 to enable TjMax Turbo mode
[UNKNOWN] set bit[8] to 0 to disable Dynamic Turbo
[UNKNOWN] set bits[9:11] to 0 disable Dynamic Turbo Policy
*/
typedef union
{ /* P-Unit at Offset [Port: 0x04] + 4h */
unsigned int value;
struct {
unsigned int
OVERRIDE_EN : 1-0, /* RW: Turbo MSR */
SOC_TURBO_EN : 2-1, /* RW: PKG_TURBO_CFG1[SOC_TDP_EN] */
SOC_TDP_POLICY : 5-2, /* RW: PKG_TURBO_CFG1[SOC_TDP_POLICY]*/
RESERVED_4 : 32-5; /* RO: reserved */
};
} ATOM_TURBO_SOC_OVERRIDE;
typedef union
{
unsigned long long value;
struct
{
unsigned long long
FastStrings : 1-0, /* Fast-Strings Enable */
ReservedBits1 : 2-1,
x87Compat_Enable: 3-2, /* Pentium4, Xeon */
TCC : 4-3, /* Automatic Thermal Control Circuit */
SplitLockDisable: 5-4, /* Pentium4, Xeon */
ReservedBits2 : 6-5,
L3Cache_Disable : 7-6, /* Pentium4, Xeon */
PerfMonitoring : 8-7, /* Performance Monitoring Available */
SupprLock_Enable: 9-8, /* Pentium4, Xeon */
HW_Prefetch_Dis : 10-9, /* Pentium4, Xeon, Core (R/W) */
Int_FERR_Enable : 11-10, /* Pentium4, Xeon */
BTS : 12-11, /* Branch Trace Storage Unavailable */
PEBS : 13-12, /* No Precise Event Based Sampling */
TM2_Enable : 14-13,
ReservedBits3 : 16-14,
EIST : 17-16, /* Enhanced Intel SpeedStep Tech. */
BR_PROCHOT : 18-17, /* Broadwell */
FSM : 19-18,
PrefetchCacheDis: 20-19, /* Pentium4, Xeon */
ReservedBits4 : 22-20,
CPUID_MaxVal : 23-22,
xTPR : 24-23,
L1DataCacheMode : 25-24, /* Pentium4, Xeon */
ReservedBits5 : 26-25,
C2E : 27-26, /* Broadwell */
ReservedBits6 : 32-27,
C4E : 34-32, /* Broadwell Mobile */
XD_Bit_Disable : 35-34,
ReservedBits7 : 37-35,
DCU_L1_Prefetch : 38-37, /* Core (R/W) Disable=1 */
Turbo_IDA : 39-38, /* Disable=1 -> CPUID(0x6).IDA=0 */
IP_Prefetcher : 40-39,
ReservedBits8 : 64-40;
};
} MISC_PROC_FEATURES;
typedef union
{
unsigned long long value;
struct
{
unsigned long long int
BD_PROCHOT : 1-0, /* BiDirectional PROCHOT */
C1E : 2-1,
ReservedBits2 : 19-2,
R2H_Disable : 20-19, /* SKL,KBL,CFL:Race To Halt Disable=1*/
EEO_Disable : 21-20, /* SKL,KBL,CFL: Energy opt. Disable=1*/
ReservedBits3 : 25-21,
EBP_OS_Control : 26-25, /* SNB: 0=EBP controlled by OS */
ReservedBits4 : 30-26,
CST_PreWake_Dis : 31-30, /* 1=disable Cstate Pre-Wake [CFL/S] */
ReservedBits5 : 64-31;
};
} POWER_CONTROL;
typedef union
{
unsigned long long value;
struct
{
unsigned long long
DutyCycle : 4-0,/* OnDemand Clock Modulation Duty Cycle*/
ODCM_Enable : 5-4,
ReservedBits : 63-5,
ECMD : 64-63; /* Placeholder for CPUID(0x6)AX.5 */
};
} CLOCK_MODULATION;
typedef union
{
unsigned long long value;
struct
{
unsigned long long
PowerPolicy : 4-0,/*0=highest perf;15=Max energy saving* */
ReservedBits : 64-4;
};
} ENERGY_PERF_BIAS;
/*
*IA32_ENERGY_PERF_BIAS
Package: Westmere, Sandy Bridge,
Ivy Bridge[06_3AH],
Ivy Bridge-E v2[06_3EH],
Haswell[06_3CH][06_45H][06_46H],
Haswell-E[06_3F],
Broadwell[06_3DH][06_47H][06_4FH][06_56H],
Skylake[06_4EH][06_5EH]
Per Core: Silvermont
Per Thread: Nehalem, Knights Landing[06_57H]
Shared/Unique: Core Solo, Core Duo, Dual-Core-Xeon-LV
*/
typedef union
{
unsigned long long value;
struct
{
unsigned long long
HW_Coord_EIST : 1-0, /* Pkg: 0=Enable; 1=Disable */
Perf_BIAS_Enable: 2-1, /* SMT: 1=Enable; 0=Disable* */
ReservedBits1 : 22-2,
Therm_Intr_Coord: 23-22, /* Pkg: Goldmont 0=Disable; 1=Enable */
ReservedBits2 : 64-23;
};
} MISC_PWR_MGMT;
/*
*MSR_MISC_PWR_MGMT
Per Thread: Nehalem, Sandy Bridge
Perf_BIAS_Enable bit makes the IA32_ENERGY_PERF_BIAS register (MSR 1B0h)
visible to software with Ring 0 privileges. This bit’s status (1 or 0)
is also reflected by CPUID.(EAX=06h):ECX[3]
*/
typedef union
{ /* 06_4E/06_4F/06_5E/06_55/06_56/06_8E/06_9E */
unsigned long long value;
struct
{
unsigned long long
HWP_Enable : 1-0, /* Pkg: R/W-Once; 1=Enable */
ReservedBits : 64-1; /* **Must be zero** */
};
} PM_ENABLE;
typedef union
{ /* 06_4E/06_4F/06_5E/06_55/06_56/06_66/06_8E/06_9E */
unsigned long long value;
struct
{
unsigned long long
Highest : 8-0,
Guaranteed : 16-8,
Most_Efficient : 24-16,
Lowest : 32-24,
ReservedBits : 64-32; /* **Must be zero** */
};
} HWP_CAPABILITIES; /* SMT: If CPUID.06H:EAX.[7] = 1 */
typedef union
{
unsigned long long value;
struct
{
unsigned long long
EN_Guarantee_Chg: 1-0,
EN_Excursion_Min: 2-1,
EN_Highest_Chg : 3-2,
EN_PECI_OVERRIDE: 4-3, /* If CPUID[6].EAX[16] = 1 */
ReservedBits : 64-4; /* **Must be zero** */
};
} HWP_INTERRUPT; /* SMT[SKL,KBL,CFL,CNL] If CPUID.06H:EAX.[8] = 1 */
typedef union
{ /* 06_4E/06_4F/06_5E/06_55/06_56/06_66/06_8E/06_9E */