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mdtang_m60k.gprj
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<?xml version="1" encoding="UTF-8"?>
<!DOCTYPE gowin-fpga-project>
<Project>
<Template>FPGA</Template>
<Version>5</Version>
<Device name="GW5AT-60B" pn="GW5AT-LV60PG484AC1/I0">gw5at60b-002</Device>
<FileList>
<File path="src/common/dpram.v" type="file.verilog" enable="1"/>
<File path="src/common/dpram32_block.v" type="file.verilog" enable="1"/>
<File path="src/common/dpram_block.v" type="file.verilog" enable="1"/>
<File path="src/fx68k/fx68k.sv" type="file.verilog" enable="1"/>
<File path="src/fx68k/fx68kAlu.sv" type="file.verilog" enable="1"/>
<File path="src/fx68k/uaddrPla.sv" type="file.verilog" enable="1"/>
<File path="src/hdmi/audio_clock_regeneration_packet.sv" type="file.verilog" enable="1"/>
<File path="src/hdmi/audio_info_frame.sv" type="file.verilog" enable="1"/>
<File path="src/hdmi/audio_sample_packet.sv" type="file.verilog" enable="1"/>
<File path="src/hdmi/auxiliary_video_information_info_frame.sv" type="file.verilog" enable="1"/>
<File path="src/hdmi/hdmi.sv" type="file.verilog" enable="1"/>
<File path="src/hdmi/packet_assembler.sv" type="file.verilog" enable="1"/>
<File path="src/hdmi/packet_picker.sv" type="file.verilog" enable="1"/>
<File path="src/hdmi/serializer.sv" type="file.verilog" enable="1"/>
<File path="src/hdmi/source_product_description_info_frame.sv" type="file.verilog" enable="1"/>
<File path="src/hdmi/tmds_channel.sv" type="file.verilog" enable="1"/>
<File path="src/iosys/dualshock_controller.v" type="file.verilog" enable="1"/>
<File path="src/iosys/framebuffer_sync.sv" type="file.verilog" enable="1"/>
<File path="src/iosys/gowin_dpb_menu.v" type="file.verilog" enable="1"/>
<File path="src/iosys/iosys.v" type="file.verilog" enable="1"/>
<File path="src/iosys/picorv32.v" type="file.verilog" enable="1"/>
<File path="src/iosys/simplespimaster1x.v" type="file.verilog" enable="1"/>
<File path="src/iosys/simpleuart.v" type="file.verilog" enable="1"/>
<File path="src/iosys/spi_master.v" type="file.verilog" enable="1"/>
<File path="src/iosys/spiflash.v" type="file.verilog" enable="1"/>
<File path="src/iosys/textdisp.v" type="file.verilog" enable="1"/>
<File path="src/jt12/adpcm/jt10_adpcm_div.v" type="file.verilog" enable="1"/>
<File path="src/jt12/jt12.v" type="file.verilog" enable="1"/>
<File path="src/jt12/jt12_acc.v" type="file.verilog" enable="1"/>
<File path="src/jt12/jt12_csr.v" type="file.verilog" enable="1"/>
<File path="src/jt12/jt12_div.v" type="file.verilog" enable="1"/>
<File path="src/jt12/jt12_dout.v" type="file.verilog" enable="1"/>
<File path="src/jt12/jt12_eg.v" type="file.verilog" enable="1"/>
<File path="src/jt12/jt12_eg_cnt.v" type="file.verilog" enable="1"/>
<File path="src/jt12/jt12_eg_comb.v" type="file.verilog" enable="1"/>
<File path="src/jt12/jt12_eg_ctrl.v" type="file.verilog" enable="1"/>
<File path="src/jt12/jt12_eg_final.v" type="file.verilog" enable="1"/>
<File path="src/jt12/jt12_eg_pure.v" type="file.verilog" enable="1"/>
<File path="src/jt12/jt12_eg_step.v" type="file.verilog" enable="1"/>
<File path="src/jt12/jt12_exprom.v" type="file.verilog" enable="1"/>
<File path="src/jt12/jt12_kon.v" type="file.verilog" enable="1"/>
<File path="src/jt12/jt12_lfo.v" type="file.verilog" enable="1"/>
<File path="src/jt12/jt12_logsin.v" type="file.verilog" enable="1"/>
<File path="src/jt12/jt12_mmr.v" type="file.verilog" enable="1"/>
<File path="src/jt12/jt12_mod.v" type="file.verilog" enable="1"/>
<File path="src/jt12/jt12_op.v" type="file.verilog" enable="1"/>
<File path="src/jt12/jt12_pcm_interpol.v" type="file.verilog" enable="1"/>
<File path="src/jt12/jt12_pg.v" type="file.verilog" enable="1"/>
<File path="src/jt12/jt12_pg_comb.v" type="file.verilog" enable="1"/>
<File path="src/jt12/jt12_pg_dt.v" type="file.verilog" enable="1"/>
<File path="src/jt12/jt12_pg_inc.v" type="file.verilog" enable="1"/>
<File path="src/jt12/jt12_pg_sum.v" type="file.verilog" enable="1"/>
<File path="src/jt12/jt12_pm.v" type="file.verilog" enable="1"/>
<File path="src/jt12/jt12_reg.v" type="file.verilog" enable="1"/>
<File path="src/jt12/jt12_rst.v" type="file.verilog" enable="1"/>
<File path="src/jt12/jt12_sh.v" type="file.verilog" enable="1"/>
<File path="src/jt12/jt12_sh24.v" type="file.verilog" enable="1"/>
<File path="src/jt12/jt12_sh_rst.v" type="file.verilog" enable="1"/>
<File path="src/jt12/jt12_single_acc.v" type="file.verilog" enable="1"/>
<File path="src/jt12/jt12_sumch.v" type="file.verilog" enable="1"/>
<File path="src/jt12/jt12_timers.v" type="file.verilog" enable="1"/>
<File path="src/jt12/jt12_top.v" type="file.verilog" enable="1"/>
<File path="src/jt12/mixer/jt12_comb.v" type="file.verilog" enable="1"/>
<File path="src/jt12/mixer/jt12_decim.v" type="file.verilog" enable="1"/>
<File path="src/jt12/mixer/jt12_fm_uprate.v" type="file.verilog" enable="1"/>
<File path="src/jt12/mixer/jt12_genmix.v" type="file.verilog" enable="1"/>
<File path="src/jt12/mixer/jt12_interpol.v" type="file.verilog" enable="1"/>
<File path="src/jt89/jt89.v" type="file.verilog" enable="1"/>
<File path="src/jt89/jt89_mixer.v" type="file.verilog" enable="1"/>
<File path="src/jt89/jt89_noise.v" type="file.verilog" enable="1"/>
<File path="src/jt89/jt89_tone.v" type="file.verilog" enable="1"/>
<File path="src/jt89/jt89_vol.v" type="file.verilog" enable="1"/>
<File path="src/m60k/pll.v" type="file.verilog" enable="1"/>
<File path="src/m60k/pll_27.v" type="file.verilog" enable="1"/>
<File path="src/m60k/pll_74.v" type="file.verilog" enable="1"/>
<File path="src/mdtang_top.sv" type="file.verilog" enable="1"/>
<File path="src/memory/rv_sdram_adapter.v" type="file.verilog" enable="1"/>
<File path="src/memory/sdram.v" type="file.verilog" enable="1"/>
<File path="src/peripherals/audio_iir_filter.v" type="file.verilog" enable="1"/>
<File path="src/peripherals/fourway.v" type="file.verilog" enable="1"/>
<File path="src/peripherals/gen_io.sv" type="file.verilog" enable="1"/>
<File path="src/peripherals/genesis_lpf.v" type="file.verilog" enable="1"/>
<File path="src/peripherals/lightgun.sv" type="file.verilog" enable="1"/>
<File path="src/peripherals/multitap.sv" type="file.verilog" enable="1"/>
<File path="src/peripherals/teamplayer.sv" type="file.verilog" enable="1"/>
<File path="src/system.sv" type="file.verilog" enable="1"/>
<File path="src/t80/t80.v" type="file.verilog" enable="1"/>
<File path="src/t80/t80_alu.v" type="file.verilog" enable="1"/>
<File path="src/t80/t80_mcode.v" type="file.verilog" enable="1"/>
<File path="src/t80/t80_reg.v" type="file.verilog" enable="1"/>
<File path="src/t80/t80s.v" type="file.verilog" enable="1"/>
<File path="src/vdp/vdp.v" type="file.verilog" enable="1"/>
<File path="src/vdp/vdp_common.v" type="file.verilog" enable="1"/>
<File path="src/vdp/vram.v" type="file.verilog" enable="1"/>
<File path="src/m138k/m138k.cst" type="file.cst" enable="1"/>
<File path="src/mdtang.sdc" type="file.sdc" enable="1"/>
<File path="src/cpu.gao" type="file.gao" enable="0"/>
<File path="src/framebuffer.rao" type="file.gao" enable="0"/>
<File path="src/iosys.gao" type="file.gao" enable="0"/>
</FileList>
</Project>