Are Zicntr tests meaningful in lockstep?

[jordancarlin]

All of the counter CSRs are set as volatile, which means the reference model will just return whatever the DUT says for each of them. This means any reads or writes we do to them will appear to be successful no matter what actually happens.

This is an issue for cycle, mcycle, instret, minstret, time, hpmcounterx, mhpmcounterx, and the h versions of each of these CSRs.

[jordancarlin]

MIP and SIP are also set as volatile, but I think this should be ok with how we are testing interrupts.