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assign文の順番依存 #4

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Yamakatsu63 opened this issue Feb 22, 2022 · 0 comments

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Yamakatsu63 commented Feb 22, 2022

本来Verilogでは，assign文は記述される順番に依存せずシミュレートされる．
assign文を順番通りにGoに書き換えているため，順番に依存してassign文がシミュレートされている．

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